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This library was superseded by mbed-dev - https://os.mbed.com/users/mbed_official/code/mbed-dev/.

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If you are looking for a stable and tested release, please import one of the official mbed library releases:

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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Last commit 20 Feb 2019 by mbed official

targets/cmsis/TARGET_Freescale/TARGET_K22F/system_MK22F51212.c@600:7d17ca308cd1, 2015-07-31 (annotated)

Committer:
mbed_official
Date:
Fri Jul 31 14:15:09 2015 +0100
Revision:
600:7d17ca308cd1
Parent:
324:406fd2029f23 
Synchronized with git revision e4cd8bbd3e05b68e5a7f466c74035a85743d45e0



Full URL: https://github.com/mbedmicro/mbed/commit/e4cd8bbd3e05b68e5a7f466c74035a85743d45e0/



Enable LPC8xx usart when configuring it

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 324:406fd2029f23 1 /*
mbed_official 324:406fd2029f23 2 ** ###################################################################
mbed_official 324:406fd2029f23 3 ** Compilers: Keil ARM C/C++ Compiler
mbed_official 324:406fd2029f23 4 ** Freescale C/C++ for Embedded ARM
mbed_official 324:406fd2029f23 5 ** GNU C Compiler
mbed_official 324:406fd2029f23 6 ** GNU C Compiler - CodeSourcery Sourcery G++
mbed_official 324:406fd2029f23 7 ** IAR ANSI C/C++ Compiler for ARM
mbed_official 324:406fd2029f23 8 **
mbed_official 324:406fd2029f23 9 ** Reference manual: K22P121M120SF7RM, Rev. 1, March 24, 2014
mbed_official 324:406fd2029f23 10 ** Version: rev. 2.5, 2014-05-06
mbed_official 324:406fd2029f23 11 ** Build: b140611
mbed_official 324:406fd2029f23 12 **
mbed_official 324:406fd2029f23 13 ** Abstract:
mbed_official 324:406fd2029f23 14 ** Provides a system configuration function and a global variable that
mbed_official 324:406fd2029f23 15 ** contains the system frequency. It configures the device and initializes
mbed_official 324:406fd2029f23 16 ** the oscillator (PLL) that is part of the microcontroller device.
mbed_official 324:406fd2029f23 17 **
mbed_official 324:406fd2029f23 18 ** Copyright (c) 2014 Freescale Semiconductor, Inc.
mbed_official 324:406fd2029f23 19 ** All rights reserved.
mbed_official 324:406fd2029f23 20 **
mbed_official 324:406fd2029f23 21 ** Redistribution and use in source and binary forms, with or without modification,
mbed_official 324:406fd2029f23 22 ** are permitted provided that the following conditions are met:
mbed_official 324:406fd2029f23 23 **
mbed_official 324:406fd2029f23 24 ** o Redistributions of source code must retain the above copyright notice, this list
mbed_official 324:406fd2029f23 25 ** of conditions and the following disclaimer.
mbed_official 324:406fd2029f23 26 **
mbed_official 324:406fd2029f23 27 ** o Redistributions in binary form must reproduce the above copyright notice, this
mbed_official 324:406fd2029f23 28 ** list of conditions and the following disclaimer in the documentation and/or
mbed_official 324:406fd2029f23 29 ** other materials provided with the distribution.
mbed_official 324:406fd2029f23 30 **
mbed_official 324:406fd2029f23 31 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
mbed_official 324:406fd2029f23 32 ** contributors may be used to endorse or promote products derived from this
mbed_official 324:406fd2029f23 33 ** software without specific prior written permission.
mbed_official 324:406fd2029f23 34 **
mbed_official 324:406fd2029f23 35 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
mbed_official 324:406fd2029f23 36 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
mbed_official 324:406fd2029f23 37 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 324:406fd2029f23 38 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
mbed_official 324:406fd2029f23 39 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
mbed_official 324:406fd2029f23 40 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
mbed_official 324:406fd2029f23 41 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
mbed_official 324:406fd2029f23 42 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
mbed_official 324:406fd2029f23 43 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
mbed_official 324:406fd2029f23 44 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 324:406fd2029f23 45 **
mbed_official 324:406fd2029f23 46 ** http: www.freescale.com
mbed_official 324:406fd2029f23 47 ** mail: support@freescale.com
mbed_official 324:406fd2029f23 48 **
mbed_official 324:406fd2029f23 49 ** Revisions:
mbed_official 324:406fd2029f23 50 ** - rev. 1.0 (2013-07-23)
mbed_official 324:406fd2029f23 51 ** Initial version.
mbed_official 324:406fd2029f23 52 ** - rev. 1.1 (2013-09-17)
mbed_official 324:406fd2029f23 53 ** RM rev. 0.4 update.
mbed_official 324:406fd2029f23 54 ** - rev. 2.0 (2013-10-29)
mbed_official 324:406fd2029f23 55 ** Register accessor macros added to the memory map.
mbed_official 324:406fd2029f23 56 ** Symbols for Processor Expert memory map compatibility added to the memory map.
mbed_official 324:406fd2029f23 57 ** Startup file for gcc has been updated according to CMSIS 3.2.
mbed_official 324:406fd2029f23 58 ** System initialization updated.
mbed_official 324:406fd2029f23 59 ** - rev. 2.1 (2013-10-30)
mbed_official 324:406fd2029f23 60 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
mbed_official 324:406fd2029f23 61 ** - rev. 2.2 (2013-12-20)
mbed_official 324:406fd2029f23 62 ** Update according to reference manual rev. 0.6,
mbed_official 324:406fd2029f23 63 ** - rev. 2.3 (2014-01-13)
mbed_official 324:406fd2029f23 64 ** Update according to reference manual rev. 0.61,
mbed_official 324:406fd2029f23 65 ** - rev. 2.4 (2014-02-10)
mbed_official 324:406fd2029f23 66 ** The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
mbed_official 324:406fd2029f23 67 ** - rev. 2.5 (2014-05-06)
mbed_official 324:406fd2029f23 68 ** Update according to reference manual rev. 1.0,
mbed_official 324:406fd2029f23 69 ** Update of system and startup files.
mbed_official 324:406fd2029f23 70 ** Module access macro module_BASES replaced by module_BASE_PTRS.
mbed_official 324:406fd2029f23 71 **
mbed_official 324:406fd2029f23 72 ** ###################################################################
mbed_official 324:406fd2029f23 73 */
mbed_official 324:406fd2029f23 74
mbed_official 324:406fd2029f23 75 /*!
mbed_official 324:406fd2029f23 76 * @file MK22F51212
mbed_official 324:406fd2029f23 77 * @version 2.5
mbed_official 324:406fd2029f23 78 * @date 2014-05-06
mbed_official 324:406fd2029f23 79 * @brief Device specific configuration file for MK22F51212 (implementation file)
mbed_official 324:406fd2029f23 80 *
mbed_official 324:406fd2029f23 81 * Provides a system configuration function and a global variable that contains
mbed_official 324:406fd2029f23 82 * the system frequency. It configures the device and initializes the oscillator
mbed_official 324:406fd2029f23 83 * (PLL) that is part of the microcontroller device.
mbed_official 324:406fd2029f23 84 */
mbed_official 324:406fd2029f23 85
mbed_official 324:406fd2029f23 86 #include <stdint.h>
mbed_official 324:406fd2029f23 87 #include "cmsis.h"
mbed_official 324:406fd2029f23 88
mbed_official 324:406fd2029f23 89
mbed_official 324:406fd2029f23 90
mbed_official 324:406fd2029f23 91 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 92 -- Core clock
mbed_official 324:406fd2029f23 93 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 94
mbed_official 324:406fd2029f23 95 uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
mbed_official 324:406fd2029f23 96
mbed_official 324:406fd2029f23 97 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 98 -- SystemInit()
mbed_official 324:406fd2029f23 99 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 100
mbed_official 324:406fd2029f23 101 void SystemInit (void) {
mbed_official 324:406fd2029f23 102 #if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
mbed_official 324:406fd2029f23 103 SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access */
mbed_official 324:406fd2029f23 104 #endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
mbed_official 324:406fd2029f23 105
mbed_official 324:406fd2029f23 106 #if (DISABLE_WDOG)
mbed_official 324:406fd2029f23 107 /* WDOG->UNLOCK: WDOGUNLOCK=0xC520 */
mbed_official 324:406fd2029f23 108 WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xC520); /* Key 1 */
mbed_official 324:406fd2029f23 109 /* WDOG->UNLOCK: WDOGUNLOCK=0xD928 */
mbed_official 324:406fd2029f23 110 WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xD928); /* Key 2 */
mbed_official 324:406fd2029f23 111 /* WDOG->STCTRLH: ?=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,?=0,?=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */
mbed_official 324:406fd2029f23 112 WDOG->STCTRLH = WDOG_STCTRLH_BYTESEL(0x00) |
mbed_official 324:406fd2029f23 113 WDOG_STCTRLH_WAITEN_MASK |
mbed_official 324:406fd2029f23 114 WDOG_STCTRLH_STOPEN_MASK |
mbed_official 324:406fd2029f23 115 WDOG_STCTRLH_ALLOWUPDATE_MASK |
mbed_official 324:406fd2029f23 116 WDOG_STCTRLH_CLKSRC_MASK |
mbed_official 324:406fd2029f23 117 0x0100U;
mbed_official 324:406fd2029f23 118 #endif /* (DISABLE_WDOG) */
mbed_official 324:406fd2029f23 119 if((RCM->SRS0 & RCM_SRS0_WAKEUP_MASK) != 0x00U)
mbed_official 324:406fd2029f23 120 {
mbed_official 324:406fd2029f23 121 if((PMC->REGSC & PMC_REGSC_ACKISO_MASK) != 0x00U)
mbed_official 324:406fd2029f23 122 {
mbed_official 324:406fd2029f23 123 PMC->REGSC |= PMC_REGSC_ACKISO_MASK; /* Release hold with ACKISO: Only has an effect if recovering from VLLSx.*/
mbed_official 324:406fd2029f23 124 }
mbed_official 324:406fd2029f23 125 } else {
mbed_official 324:406fd2029f23 126 #ifdef SYSTEM_RTC_CR_VALUE
mbed_official 324:406fd2029f23 127 SIM_SCGC6 |= SIM_SCGC6_RTC_MASK;
mbed_official 324:406fd2029f23 128 if ((RTC_CR & RTC_CR_OSCE_MASK) == 0x00U) { /* Only if the OSCILLATOR is not already enabled */
mbed_official 324:406fd2029f23 129 RTC_CR = (uint32_t)((RTC_CR & (uint32_t)~(uint32_t)(RTC_CR_SC2P_MASK | RTC_CR_SC4P_MASK | RTC_CR_SC8P_MASK | RTC_CR_SC16P_MASK)) | (uint32_t)SYSTEM_RTC_CR_VALUE);
mbed_official 324:406fd2029f23 130 RTC_CR |= (uint32_t)RTC_CR_OSCE_MASK;
mbed_official 324:406fd2029f23 131 RTC_CR &= (uint32_t)~(uint32_t)RTC_CR_CLKO_MASK;
mbed_official 324:406fd2029f23 132 }
mbed_official 324:406fd2029f23 133 #endif
mbed_official 324:406fd2029f23 134 }
mbed_official 324:406fd2029f23 135
mbed_official 324:406fd2029f23 136 /* Power mode protection initialization */
mbed_official 324:406fd2029f23 137 #ifdef SYSTEM_SMC_PMPROT_VALUE
mbed_official 324:406fd2029f23 138 SMC->PMPROT = SYSTEM_SMC_PMPROT_VALUE;
mbed_official 324:406fd2029f23 139 #endif
mbed_official 324:406fd2029f23 140
mbed_official 324:406fd2029f23 141 /* High speed run mode enable */
mbed_official 324:406fd2029f23 142 #if (((SYSTEM_SMC_PMCTRL_VALUE) & SMC_PMCTRL_RUNM_MASK) == (0x03U << SMC_PMCTRL_RUNM_SHIFT))
mbed_official 324:406fd2029f23 143 SMC->PMCTRL = (uint8_t)((SYSTEM_SMC_PMCTRL_VALUE) & (SMC_PMCTRL_RUNM_MASK)); /* Enable HSRUN mode */
mbed_official 324:406fd2029f23 144 while(SMC->PMSTAT != 0x80U) { /* Wait until the system is in HSRUN mode */
mbed_official 324:406fd2029f23 145 }
mbed_official 324:406fd2029f23 146 #endif
mbed_official 324:406fd2029f23 147 /* System clock initialization */
mbed_official 324:406fd2029f23 148 /* Internal reference clock trim initialization */
mbed_official 324:406fd2029f23 149 #if defined(SLOW_TRIM_ADDRESS)
mbed_official 324:406fd2029f23 150 if ( *((uint8_t*)SLOW_TRIM_ADDRESS) != 0xFFU) { /* Skip if non-volatile flash memory is erased */
mbed_official 324:406fd2029f23 151 MCG->C3 = *((uint8_t*)SLOW_TRIM_ADDRESS);
mbed_official 324:406fd2029f23 152 #endif /* defined(SLOW_TRIM_ADDRESS) */
mbed_official 324:406fd2029f23 153 #if defined(SLOW_FINE_TRIM_ADDRESS)
mbed_official 324:406fd2029f23 154 MCG->C4 = (MCG->C4 & ~(MCG_C4_SCFTRIM_MASK)) | ((*((uint8_t*) SLOW_FINE_TRIM_ADDRESS)) & MCG_C4_SCFTRIM_MASK);
mbed_official 324:406fd2029f23 155 #endif
mbed_official 324:406fd2029f23 156 #if defined(FAST_TRIM_ADDRESS)
mbed_official 324:406fd2029f23 157 MCG->C4 = (MCG->C4 & ~(MCG_C4_FCTRIM_MASK)) |((*((uint8_t*) FAST_TRIM_ADDRESS)) & MCG_C4_FCTRIM_MASK);
mbed_official 324:406fd2029f23 158 #endif
mbed_official 324:406fd2029f23 159 #if defined(FAST_FINE_TRIM_ADDRESS)
mbed_official 324:406fd2029f23 160 MCG->C2 = (MCG->C2 & ~(MCG_C2_FCFTRIM_MASK)) | ((*((uint8_t*)FAST_TRIM_ADDRESS)) & MCG_C2_FCFTRIM_MASK);
mbed_official 324:406fd2029f23 161 #endif /* defined(FAST_FINE_TRIM_ADDRESS) */
mbed_official 324:406fd2029f23 162 #if defined(SLOW_TRIM_ADDRESS)
mbed_official 324:406fd2029f23 163 }
mbed_official 324:406fd2029f23 164 #endif /* defined(SLOW_TRIM_ADDRESS) */
mbed_official 324:406fd2029f23 165
mbed_official 324:406fd2029f23 166 /* Set system prescalers and clock sources */
mbed_official 324:406fd2029f23 167 SIM->CLKDIV1 = SYSTEM_SIM_CLKDIV1_VALUE; /* Set system prescalers */
mbed_official 324:406fd2029f23 168 SIM->SOPT1 = ((SIM->SOPT1) & (uint32_t)(~(SIM_SOPT1_OSC32KSEL_MASK))) | ((SYSTEM_SIM_SOPT1_VALUE) & (SIM_SOPT1_OSC32KSEL_MASK)); /* Set 32 kHz clock source (ERCLK32K) */
mbed_official 324:406fd2029f23 169 SIM->SOPT2 = ((SIM->SOPT2) & (uint32_t)(~(SIM_SOPT2_PLLFLLSEL_MASK))) | ((SYSTEM_SIM_SOPT2_VALUE) & (SIM_SOPT2_PLLFLLSEL_MASK)); /* Selects the high frequency clock for various peripheral clocking options. */
mbed_official 324:406fd2029f23 170 #if ((MCG_MODE == MCG_MODE_FEI) || (MCG_MODE == MCG_MODE_FBI) || (MCG_MODE == MCG_MODE_BLPI))
mbed_official 324:406fd2029f23 171 /* Set MCG and OSC */
mbed_official 324:406fd2029f23 172 #if ((((SYSTEM_OSC_CR_VALUE) & OSC_CR_ERCLKEN_MASK) != 0x00U) || ((((SYSTEM_MCG_C5_VALUE) & MCG_C5_PLLCLKEN0_MASK) != 0x00U) && (((SYSTEM_MCG_C7_VALUE) & MCG_C7_OSCSEL_MASK) == 0x00U)))
mbed_official 324:406fd2029f23 173 /* SIM_SCGC5: PORTA=1 */
mbed_official 324:406fd2029f23 174 SIM_SCGC5 |= SIM_SCGC5_PORTA_MASK;
mbed_official 324:406fd2029f23 175 /* PORTA_PCR18: ISF=0,MUX=0 */
mbed_official 324:406fd2029f23 176 PORTA_PCR18 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
mbed_official 324:406fd2029f23 177 if (((SYSTEM_MCG_C2_VALUE) & MCG_C2_EREFS_MASK) != 0x00U) {
mbed_official 324:406fd2029f23 178 /* PORTA_PCR19: ISF=0,MUX=0 */
mbed_official 324:406fd2029f23 179 PORTA_PCR19 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
mbed_official 324:406fd2029f23 180 }
mbed_official 324:406fd2029f23 181 #endif
mbed_official 324:406fd2029f23 182 MCG->SC = SYSTEM_MCG_SC_VALUE; /* Set SC (fast clock internal reference divider) */
mbed_official 324:406fd2029f23 183 MCG->C1 = SYSTEM_MCG_C1_VALUE; /* Set C1 (clock source selection, FLL ext. reference divider, int. reference enable etc.) */
mbed_official 324:406fd2029f23 184 /* Check that the source of the FLL reference clock is the requested one. */
mbed_official 324:406fd2029f23 185 if (((SYSTEM_MCG_C1_VALUE) & MCG_C1_IREFS_MASK) != 0x00U) {
mbed_official 324:406fd2029f23 186 while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) {
mbed_official 324:406fd2029f23 187 }
mbed_official 324:406fd2029f23 188 } else {
mbed_official 324:406fd2029f23 189 while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) {
mbed_official 324:406fd2029f23 190 }
mbed_official 324:406fd2029f23 191 }
mbed_official 324:406fd2029f23 192 MCG->C2 = (MCG->C2 & (uint8_t)(~(MCG_C2_FCFTRIM_MASK))) | (SYSTEM_MCG_C2_VALUE & (uint8_t)(~(MCG_C2_LP_MASK))); /* Set C2 (freq. range, ext. and int. reference selection etc. excluding trim bits; low power bit is set later) */
mbed_official 324:406fd2029f23 193 MCG->C4 = ((SYSTEM_MCG_C4_VALUE) & (uint8_t)(~(MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK))) | (MCG->C4 & (MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK)); /* Set C4 (FLL output; trim values not changed) */
mbed_official 324:406fd2029f23 194 OSC->CR = SYSTEM_OSC_CR_VALUE; /* Set OSC_CR (OSCERCLK enable, oscillator capacitor load) */
mbed_official 324:406fd2029f23 195 MCG->C7 = SYSTEM_MCG_C7_VALUE; /* Set C7 (OSC Clock Select) */
mbed_official 324:406fd2029f23 196 #if (MCG_MODE == MCG_MODE_BLPI)
mbed_official 324:406fd2029f23 197 /* BLPI specific */
mbed_official 324:406fd2029f23 198 MCG->C2 |= (MCG_C2_LP_MASK); /* Disable FLL and PLL in bypass mode */
mbed_official 324:406fd2029f23 199 #endif
mbed_official 324:406fd2029f23 200
mbed_official 324:406fd2029f23 201 #else /* MCG_MODE */
mbed_official 324:406fd2029f23 202 /* Set MCG and OSC */
mbed_official 324:406fd2029f23 203 #if (((SYSTEM_OSC_CR_VALUE) & OSC_CR_ERCLKEN_MASK) != 0x00U) || (((SYSTEM_MCG_C7_VALUE) & MCG_C7_OSCSEL_MASK) == 0x00U)
mbed_official 324:406fd2029f23 204 /* SIM_SCGC5: PORTA=1 */
mbed_official 324:406fd2029f23 205 SIM_SCGC5 |= SIM_SCGC5_PORTA_MASK;
mbed_official 324:406fd2029f23 206 /* PORTA_PCR18: ISF=0,MUX=0 */
mbed_official 324:406fd2029f23 207 PORTA_PCR18 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
mbed_official 324:406fd2029f23 208 if (((SYSTEM_MCG_C2_VALUE) & MCG_C2_EREFS_MASK) != 0x00U) {
mbed_official 324:406fd2029f23 209 /* PORTA_PCR19: ISF=0,MUX=0 */
mbed_official 324:406fd2029f23 210 PORTA_PCR19 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
mbed_official 324:406fd2029f23 211 }
mbed_official 324:406fd2029f23 212 #endif
mbed_official 324:406fd2029f23 213 MCG->SC = SYSTEM_MCG_SC_VALUE; /* Set SC (fast clock internal reference divider) */
mbed_official 324:406fd2029f23 214 MCG->C2 = (MCG->C2 & (uint8_t)(~(MCG_C2_FCFTRIM_MASK))) | (SYSTEM_MCG_C2_VALUE & (uint8_t)(~(MCG_C2_LP_MASK))); /* Set C2 (freq. range, ext. and int. reference selection etc. excluding trim bits; low power bit is set later) */
mbed_official 324:406fd2029f23 215 OSC->CR = SYSTEM_OSC_CR_VALUE; /* Set OSC_CR (OSCERCLK enable, oscillator capacitor load) */
mbed_official 324:406fd2029f23 216 MCG->C7 = SYSTEM_MCG_C7_VALUE; /* Set C7 (OSC Clock Select) */
mbed_official 324:406fd2029f23 217 #if (MCG_MODE == MCG_MODE_PEE)
mbed_official 324:406fd2029f23 218 MCG->C1 = (SYSTEM_MCG_C1_VALUE) | MCG_C1_CLKS(0x02); /* Set C1 (clock source selection, FLL ext. reference divider, int. reference enable etc.) - PBE mode*/
mbed_official 324:406fd2029f23 219 #else
mbed_official 324:406fd2029f23 220 MCG->C1 = SYSTEM_MCG_C1_VALUE; /* Set C1 (clock source selection, FLL ext. reference divider, int. reference enable etc.) */
mbed_official 324:406fd2029f23 221 #endif
mbed_official 324:406fd2029f23 222 if ((((SYSTEM_MCG_C2_VALUE) & MCG_C2_EREFS_MASK) != 0x00U) && (((SYSTEM_MCG_C7_VALUE) & MCG_C7_OSCSEL_MASK) == 0x00U)) {
mbed_official 324:406fd2029f23 223 while((MCG->S & MCG_S_OSCINIT0_MASK) == 0x00U) { /* Check that the oscillator is running */
mbed_official 324:406fd2029f23 224 }
mbed_official 324:406fd2029f23 225 }
mbed_official 324:406fd2029f23 226 /* Check that the source of the FLL reference clock is the requested one. */
mbed_official 324:406fd2029f23 227 if (((SYSTEM_MCG_C1_VALUE) & MCG_C1_IREFS_MASK) != 0x00U) {
mbed_official 324:406fd2029f23 228 while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) {
mbed_official 324:406fd2029f23 229 }
mbed_official 324:406fd2029f23 230 } else {
mbed_official 324:406fd2029f23 231 while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) {
mbed_official 324:406fd2029f23 232 }
mbed_official 324:406fd2029f23 233 }
mbed_official 324:406fd2029f23 234 MCG->C4 = ((SYSTEM_MCG_C4_VALUE) & (uint8_t)(~(MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK))) | (MCG->C4 & (MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK)); /* Set C4 (FLL output; trim values not changed) */
mbed_official 324:406fd2029f23 235 #endif /* MCG_MODE */
mbed_official 324:406fd2029f23 236
mbed_official 324:406fd2029f23 237 /* Common for all MCG modes */
mbed_official 324:406fd2029f23 238
mbed_official 324:406fd2029f23 239 /* PLL clock can be used to generate clock for some devices regardless of clock generator (MCGOUTCLK) mode. */
mbed_official 324:406fd2029f23 240 MCG->C5 = (SYSTEM_MCG_C5_VALUE) & (uint8_t)(~(MCG_C5_PLLCLKEN0_MASK)); /* Set C5 (PLL settings, PLL reference divider etc.) */
mbed_official 324:406fd2029f23 241 MCG->C6 = (SYSTEM_MCG_C6_VALUE) & (uint8_t)~(MCG_C6_PLLS_MASK); /* Set C6 (PLL select, VCO divider etc.) */
mbed_official 324:406fd2029f23 242 if ((SYSTEM_MCG_C5_VALUE) & MCG_C5_PLLCLKEN0_MASK) {
mbed_official 324:406fd2029f23 243 MCG->C5 |= MCG_C5_PLLCLKEN0_MASK; /* PLL clock enable in mode other than PEE or PBE */
mbed_official 324:406fd2029f23 244 }
mbed_official 324:406fd2029f23 245 /* BLPE, PEE and PBE MCG mode specific */
mbed_official 324:406fd2029f23 246
mbed_official 324:406fd2029f23 247 #if (MCG_MODE == MCG_MODE_BLPE)
mbed_official 324:406fd2029f23 248 MCG->C2 |= (MCG_C2_LP_MASK); /* Disable FLL and PLL in bypass mode */
mbed_official 324:406fd2029f23 249 #elif ((MCG_MODE == MCG_MODE_PBE) || (MCG_MODE == MCG_MODE_PEE))
mbed_official 324:406fd2029f23 250 MCG->C6 |= (MCG_C6_PLLS_MASK); /* Set C6 (PLL select, VCO divider etc.) */
mbed_official 324:406fd2029f23 251 while((MCG->S & MCG_S_LOCK0_MASK) == 0x00U) { /* Wait until PLL is locked*/
mbed_official 324:406fd2029f23 252 }
mbed_official 324:406fd2029f23 253 #if (MCG_MODE == MCG_MODE_PEE)
mbed_official 324:406fd2029f23 254 MCG->C1 &= (uint8_t)~(MCG_C1_CLKS_MASK);
mbed_official 324:406fd2029f23 255 #endif
mbed_official 324:406fd2029f23 256 #endif
mbed_official 324:406fd2029f23 257 #if ((MCG_MODE == MCG_MODE_FEI) || (MCG_MODE == MCG_MODE_FEE))
mbed_official 324:406fd2029f23 258 while((MCG->S & MCG_S_CLKST_MASK) != 0x00U) { /* Wait until output of the FLL is selected */
mbed_official 324:406fd2029f23 259 }
mbed_official 324:406fd2029f23 260 #elif ((MCG_MODE == MCG_MODE_FBI) || (MCG_MODE == MCG_MODE_BLPI))
mbed_official 324:406fd2029f23 261 while((MCG->S & MCG_S_CLKST_MASK) != 0x04U) { /* Wait until internal reference clock is selected as MCG output */
mbed_official 324:406fd2029f23 262 }
mbed_official 324:406fd2029f23 263 #elif ((MCG_MODE == MCG_MODE_FBE) || (MCG_MODE == MCG_MODE_PBE) || (MCG_MODE == MCG_MODE_BLPE))
mbed_official 324:406fd2029f23 264 while((MCG->S & MCG_S_CLKST_MASK) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
mbed_official 324:406fd2029f23 265 }
mbed_official 324:406fd2029f23 266 #elif (MCG_MODE == MCG_MODE_PEE)
mbed_official 324:406fd2029f23 267 while((MCG->S & MCG_S_CLKST_MASK) != 0x0CU) { /* Wait until output of the PLL is selected */
mbed_official 324:406fd2029f23 268 }
mbed_official 324:406fd2029f23 269 #endif
mbed_official 324:406fd2029f23 270 #if (((SYSTEM_SMC_PMCTRL_VALUE) & SMC_PMCTRL_RUNM_MASK) == (0x02U << SMC_PMCTRL_RUNM_SHIFT))
mbed_official 324:406fd2029f23 271 SMC->PMCTRL = (uint8_t)((SYSTEM_SMC_PMCTRL_VALUE) & (SMC_PMCTRL_RUNM_MASK)); /* Enable VLPR mode */
mbed_official 324:406fd2029f23 272 while(SMC->PMSTAT != 0x04U) { /* Wait until the system is in VLPR mode */
mbed_official 324:406fd2029f23 273 }
mbed_official 324:406fd2029f23 274 #endif
mbed_official 324:406fd2029f23 275
mbed_official 324:406fd2029f23 276 #if defined(SYSTEM_SIM_CLKDIV2_VALUE)
mbed_official 324:406fd2029f23 277 SIM->CLKDIV2 = ((SIM->CLKDIV2) & (uint32_t)(~(SIM_CLKDIV2_USBFRAC_MASK | SIM_CLKDIV2_USBDIV_MASK))) | ((SYSTEM_SIM_CLKDIV2_VALUE) & (SIM_CLKDIV2_USBFRAC_MASK | SIM_CLKDIV2_USBDIV_MASK)); /* Selects the USB clock divider. */
mbed_official 324:406fd2029f23 278 #endif
mbed_official 324:406fd2029f23 279
mbed_official 324:406fd2029f23 280 /* PLL loss of lock interrupt request initialization */
mbed_official 324:406fd2029f23 281 if (((SYSTEM_MCG_C6_VALUE) & MCG_C6_LOLIE0_MASK) != 0U) {
mbed_official 324:406fd2029f23 282 NVIC_EnableIRQ(MCG_IRQn); /* Enable PLL loss of lock interrupt request */
mbed_official 324:406fd2029f23 283 }
mbed_official 324:406fd2029f23 284 }
mbed_official 324:406fd2029f23 285
mbed_official 324:406fd2029f23 286 /* ----------------------------------------------------------------------------
mbed_official 324:406fd2029f23 287 -- SystemCoreClockUpdate()
mbed_official 324:406fd2029f23 288 ---------------------------------------------------------------------------- */
mbed_official 324:406fd2029f23 289
mbed_official 324:406fd2029f23 290 void SystemCoreClockUpdate (void) {
mbed_official 324:406fd2029f23 291
mbed_official 324:406fd2029f23 292 uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */
mbed_official 324:406fd2029f23 293 uint16_t Divider;
mbed_official 324:406fd2029f23 294
mbed_official 324:406fd2029f23 295 if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x00U) {
mbed_official 324:406fd2029f23 296 /* Output of FLL or PLL is selected */
mbed_official 324:406fd2029f23 297 if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U) {
mbed_official 324:406fd2029f23 298 /* FLL is selected */
mbed_official 324:406fd2029f23 299 if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U) {
mbed_official 324:406fd2029f23 300 /* External reference clock is selected */
mbed_official 324:406fd2029f23 301 switch (MCG->C7 & MCG_C7_OSCSEL_MASK) {
mbed_official 324:406fd2029f23 302 case 0x00U:
mbed_official 324:406fd2029f23 303 MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
mbed_official 324:406fd2029f23 304 break;
mbed_official 324:406fd2029f23 305 case 0x01U:
mbed_official 324:406fd2029f23 306 MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
mbed_official 324:406fd2029f23 307 break;
mbed_official 324:406fd2029f23 308 case 0x02U:
mbed_official 324:406fd2029f23 309 default:
mbed_official 324:406fd2029f23 310 MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
mbed_official 324:406fd2029f23 311 break;
mbed_official 324:406fd2029f23 312 }
mbed_official 324:406fd2029f23 313 if (((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) && ((MCG->C7 & MCG_C7_OSCSEL_MASK) != 0x01U)) {
mbed_official 324:406fd2029f23 314 switch (MCG->C1 & MCG_C1_FRDIV_MASK) {
mbed_official 324:406fd2029f23 315 case 0x38U:
mbed_official 324:406fd2029f23 316 Divider = 1536U;
mbed_official 324:406fd2029f23 317 break;
mbed_official 324:406fd2029f23 318 case 0x30U:
mbed_official 324:406fd2029f23 319 Divider = 1280U;
mbed_official 324:406fd2029f23 320 break;
mbed_official 324:406fd2029f23 321 default:
mbed_official 324:406fd2029f23 322 Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
mbed_official 324:406fd2029f23 323 break;
mbed_official 324:406fd2029f23 324 }
mbed_official 324:406fd2029f23 325 } else {/* ((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) */
mbed_official 324:406fd2029f23 326 Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
mbed_official 324:406fd2029f23 327 }
mbed_official 324:406fd2029f23 328 MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
mbed_official 324:406fd2029f23 329 } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
mbed_official 324:406fd2029f23 330 MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
mbed_official 324:406fd2029f23 331 } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
mbed_official 324:406fd2029f23 332 /* Select correct multiplier to calculate the MCG output clock */
mbed_official 324:406fd2029f23 333 switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
mbed_official 324:406fd2029f23 334 case 0x00U:
mbed_official 324:406fd2029f23 335 MCGOUTClock *= 640U;
mbed_official 324:406fd2029f23 336 break;
mbed_official 324:406fd2029f23 337 case 0x20U:
mbed_official 324:406fd2029f23 338 MCGOUTClock *= 1280U;
mbed_official 324:406fd2029f23 339 break;
mbed_official 324:406fd2029f23 340 case 0x40U:
mbed_official 324:406fd2029f23 341 MCGOUTClock *= 1920U;
mbed_official 324:406fd2029f23 342 break;
mbed_official 324:406fd2029f23 343 case 0x60U:
mbed_official 324:406fd2029f23 344 MCGOUTClock *= 2560U;
mbed_official 324:406fd2029f23 345 break;
mbed_official 324:406fd2029f23 346 case 0x80U:
mbed_official 324:406fd2029f23 347 MCGOUTClock *= 732U;
mbed_official 324:406fd2029f23 348 break;
mbed_official 324:406fd2029f23 349 case 0xA0U:
mbed_official 324:406fd2029f23 350 MCGOUTClock *= 1464U;
mbed_official 324:406fd2029f23 351 break;
mbed_official 324:406fd2029f23 352 case 0xC0U:
mbed_official 324:406fd2029f23 353 MCGOUTClock *= 2197U;
mbed_official 324:406fd2029f23 354 break;
mbed_official 324:406fd2029f23 355 case 0xE0U:
mbed_official 324:406fd2029f23 356 MCGOUTClock *= 2929U;
mbed_official 324:406fd2029f23 357 break;
mbed_official 324:406fd2029f23 358 default:
mbed_official 324:406fd2029f23 359 break;
mbed_official 324:406fd2029f23 360 }
mbed_official 324:406fd2029f23 361 } else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
mbed_official 324:406fd2029f23 362 /* PLL is selected */
mbed_official 324:406fd2029f23 363 Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV0_MASK) + 0x01U);
mbed_official 324:406fd2029f23 364 MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */
mbed_official 324:406fd2029f23 365 Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV0_MASK) + 24U);
mbed_official 324:406fd2029f23 366 MCGOUTClock *= Divider; /* Calculate the MCG output clock */
mbed_official 324:406fd2029f23 367 } /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
mbed_official 324:406fd2029f23 368 } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40U) {
mbed_official 324:406fd2029f23 369 /* Internal reference clock is selected */
mbed_official 324:406fd2029f23 370 if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U) {
mbed_official 324:406fd2029f23 371 MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
mbed_official 324:406fd2029f23 372 } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
mbed_official 324:406fd2029f23 373 Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT));
mbed_official 324:406fd2029f23 374 MCGOUTClock = (uint32_t) (CPU_INT_FAST_CLK_HZ / Divider); /* Fast internal reference clock selected */
mbed_official 324:406fd2029f23 375 } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
mbed_official 324:406fd2029f23 376 } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U) {
mbed_official 324:406fd2029f23 377 /* External reference clock is selected */
mbed_official 324:406fd2029f23 378 switch (MCG->C7 & MCG_C7_OSCSEL_MASK) {
mbed_official 324:406fd2029f23 379 case 0x00U:
mbed_official 324:406fd2029f23 380 MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
mbed_official 324:406fd2029f23 381 break;
mbed_official 324:406fd2029f23 382 case 0x01U:
mbed_official 324:406fd2029f23 383 MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
mbed_official 324:406fd2029f23 384 break;
mbed_official 324:406fd2029f23 385 case 0x02U:
mbed_official 324:406fd2029f23 386 default:
mbed_official 324:406fd2029f23 387 MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
mbed_official 324:406fd2029f23 388 break;
mbed_official 324:406fd2029f23 389 }
mbed_official 324:406fd2029f23 390 } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
mbed_official 324:406fd2029f23 391 /* Reserved value */
mbed_official 324:406fd2029f23 392 return;
mbed_official 324:406fd2029f23 393 } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
mbed_official 324:406fd2029f23 394 SystemCoreClock = (MCGOUTClock / (0x01U + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
mbed_official 324:406fd2029f23 395 }