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Last commit 20 Feb 2019 by 
mbed official
targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_ll_fsmc.h@579:53297373a894, 2015-07-01 (annotated)
- Committer:
- mbed_official
- Date:
- Wed Jul 01 09:45:11 2015 +0100
- Revision:
- 579:53297373a894
- Parent:
- 394:83f921546702
Synchronized with git revision d5b4d2ab9c47edb4dc5776e7177b0c2263459081
Full URL: https://github.com/mbedmicro/mbed/commit/d5b4d2ab9c47edb4dc5776e7177b0c2263459081/
Initial version of drivers for SAMR21
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| mbed_official | 354:e67efb2aab0e | 1 | /** |
| mbed_official | 354:e67efb2aab0e | 2 | ****************************************************************************** |
| mbed_official | 354:e67efb2aab0e | 3 | * @file stm32l1xx_ll_fsmc.h |
| mbed_official | 354:e67efb2aab0e | 4 | * @author MCD Application Team |
| mbed_official | 354:e67efb2aab0e | 5 | * @version V1.0.0 |
| mbed_official | 354:e67efb2aab0e | 6 | * @date 5-September-2014 |
| mbed_official | 354:e67efb2aab0e | 7 | * @brief Header file of FSMC HAL module. |
| mbed_official | 354:e67efb2aab0e | 8 | ****************************************************************************** |
| mbed_official | 354:e67efb2aab0e | 9 | * @attention |
| mbed_official | 354:e67efb2aab0e | 10 | * |
| mbed_official | 354:e67efb2aab0e | 11 | * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> |
| mbed_official | 354:e67efb2aab0e | 12 | * |
| mbed_official | 354:e67efb2aab0e | 13 | * Redistribution and use in source and binary forms, with or without modification, |
| mbed_official | 354:e67efb2aab0e | 14 | * are permitted provided that the following conditions are met: |
| mbed_official | 354:e67efb2aab0e | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
| mbed_official | 354:e67efb2aab0e | 16 | * this list of conditions and the following disclaimer. |
| mbed_official | 354:e67efb2aab0e | 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| mbed_official | 354:e67efb2aab0e | 18 | * this list of conditions and the following disclaimer in the documentation |
| mbed_official | 354:e67efb2aab0e | 19 | * and/or other materials provided with the distribution. |
| mbed_official | 354:e67efb2aab0e | 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| mbed_official | 354:e67efb2aab0e | 21 | * may be used to endorse or promote products derived from this software |
| mbed_official | 354:e67efb2aab0e | 22 | * without specific prior written permission. |
| mbed_official | 354:e67efb2aab0e | 23 | * |
| mbed_official | 354:e67efb2aab0e | 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| mbed_official | 354:e67efb2aab0e | 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| mbed_official | 354:e67efb2aab0e | 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| mbed_official | 354:e67efb2aab0e | 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| mbed_official | 354:e67efb2aab0e | 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| mbed_official | 354:e67efb2aab0e | 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| mbed_official | 354:e67efb2aab0e | 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| mbed_official | 354:e67efb2aab0e | 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| mbed_official | 354:e67efb2aab0e | 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| mbed_official | 354:e67efb2aab0e | 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| mbed_official | 354:e67efb2aab0e | 34 | * |
| mbed_official | 354:e67efb2aab0e | 35 | ****************************************************************************** |
| mbed_official | 354:e67efb2aab0e | 36 | */ |
| mbed_official | 354:e67efb2aab0e | 37 | |
| mbed_official | 354:e67efb2aab0e | 38 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| mbed_official | 354:e67efb2aab0e | 39 | #ifndef __STM32L1xx_LL_FSMC_H |
| mbed_official | 354:e67efb2aab0e | 40 | #define __STM32L1xx_LL_FSMC_H |
| mbed_official | 354:e67efb2aab0e | 41 | |
| mbed_official | 354:e67efb2aab0e | 42 | #ifdef __cplusplus |
| mbed_official | 354:e67efb2aab0e | 43 | extern "C" { |
| mbed_official | 354:e67efb2aab0e | 44 | #endif |
| mbed_official | 354:e67efb2aab0e | 45 | |
| mbed_official | 354:e67efb2aab0e | 46 | #if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) |
| mbed_official | 354:e67efb2aab0e | 47 | |
| mbed_official | 354:e67efb2aab0e | 48 | /* Includes ------------------------------------------------------------------*/ |
| mbed_official | 354:e67efb2aab0e | 49 | #include "stm32l1xx_hal_def.h" |
| mbed_official | 354:e67efb2aab0e | 50 | |
| mbed_official | 354:e67efb2aab0e | 51 | /** @addtogroup STM32L1xx_HAL_Driver |
| mbed_official | 354:e67efb2aab0e | 52 | * @{ |
| mbed_official | 354:e67efb2aab0e | 53 | */ |
| mbed_official | 354:e67efb2aab0e | 54 | |
| mbed_official | 354:e67efb2aab0e | 55 | /** @addtogroup FSMC_LL |
| mbed_official | 354:e67efb2aab0e | 56 | * @{ |
| mbed_official | 354:e67efb2aab0e | 57 | */ |
| mbed_official | 354:e67efb2aab0e | 58 | |
| mbed_official | 354:e67efb2aab0e | 59 | /* Exported typedef ----------------------------------------------------------*/ |
| mbed_official | 354:e67efb2aab0e | 60 | |
| mbed_official | 354:e67efb2aab0e | 61 | /** @defgroup FSMC_NORSRAM_Exported_typedef FSMC NOR/SRAM Exported typedef |
| mbed_official | 354:e67efb2aab0e | 62 | * @{ |
| mbed_official | 354:e67efb2aab0e | 63 | */ |
| mbed_official | 354:e67efb2aab0e | 64 | |
| mbed_official | 354:e67efb2aab0e | 65 | #define FSMC_NORSRAM_TYPEDEF FSMC_Bank1_TypeDef |
| mbed_official | 354:e67efb2aab0e | 66 | #define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_Bank1E_TypeDef |
| mbed_official | 354:e67efb2aab0e | 67 | |
| mbed_official | 354:e67efb2aab0e | 68 | #define FSMC_NORSRAM_DEVICE FSMC_Bank1 |
| mbed_official | 354:e67efb2aab0e | 69 | #define FSMC_NORSRAM_EXTENDED_DEVICE FSMC_Bank1E |
| mbed_official | 354:e67efb2aab0e | 70 | |
| mbed_official | 354:e67efb2aab0e | 71 | /** |
| mbed_official | 354:e67efb2aab0e | 72 | * @brief FSMC_NORSRAM Configuration Structure definition |
| mbed_official | 354:e67efb2aab0e | 73 | */ |
| mbed_official | 354:e67efb2aab0e | 74 | typedef struct |
| mbed_official | 354:e67efb2aab0e | 75 | { |
| mbed_official | 354:e67efb2aab0e | 76 | uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used. |
| mbed_official | 354:e67efb2aab0e | 77 | This parameter can be a value of @ref FSMC_NORSRAM_Bank */ |
| mbed_official | 354:e67efb2aab0e | 78 | |
| mbed_official | 354:e67efb2aab0e | 79 | uint32_t DataAddressMux; /*!< Specifies whether the address and data values are |
| mbed_official | 354:e67efb2aab0e | 80 | multiplexed on the data bus or not. |
| mbed_official | 354:e67efb2aab0e | 81 | This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */ |
| mbed_official | 354:e67efb2aab0e | 82 | |
| mbed_official | 354:e67efb2aab0e | 83 | uint32_t MemoryType; /*!< Specifies the type of external memory attached to |
| mbed_official | 354:e67efb2aab0e | 84 | the corresponding memory device. |
| mbed_official | 354:e67efb2aab0e | 85 | This parameter can be a value of @ref FSMC_Memory_Type */ |
| mbed_official | 354:e67efb2aab0e | 86 | |
| mbed_official | 354:e67efb2aab0e | 87 | uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. |
| mbed_official | 354:e67efb2aab0e | 88 | This parameter can be a value of @ref FSMC_NORSRAM_Data_Width */ |
| mbed_official | 354:e67efb2aab0e | 89 | |
| mbed_official | 354:e67efb2aab0e | 90 | uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory, |
| mbed_official | 354:e67efb2aab0e | 91 | valid only with synchronous burst Flash memories. |
| mbed_official | 354:e67efb2aab0e | 92 | This parameter can be a value of @ref FSMC_Burst_Access_Mode */ |
| mbed_official | 354:e67efb2aab0e | 93 | |
| mbed_official | 354:e67efb2aab0e | 94 | uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing |
| mbed_official | 354:e67efb2aab0e | 95 | the Flash memory in burst mode. |
| mbed_official | 354:e67efb2aab0e | 96 | This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */ |
| mbed_official | 354:e67efb2aab0e | 97 | |
| mbed_official | 354:e67efb2aab0e | 98 | uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash |
| mbed_official | 354:e67efb2aab0e | 99 | memory, valid only when accessing Flash memories in burst mode. |
| mbed_official | 354:e67efb2aab0e | 100 | This parameter can be a value of @ref FSMC_Wrap_Mode */ |
| mbed_official | 354:e67efb2aab0e | 101 | |
| mbed_official | 354:e67efb2aab0e | 102 | uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one |
| mbed_official | 354:e67efb2aab0e | 103 | clock cycle before the wait state or during the wait state, |
| mbed_official | 354:e67efb2aab0e | 104 | valid only when accessing memories in burst mode. |
| mbed_official | 354:e67efb2aab0e | 105 | This parameter can be a value of @ref FSMC_Wait_Timing */ |
| mbed_official | 354:e67efb2aab0e | 106 | |
| mbed_official | 354:e67efb2aab0e | 107 | uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FSMC. |
| mbed_official | 354:e67efb2aab0e | 108 | This parameter can be a value of @ref FSMC_Write_Operation */ |
| mbed_official | 354:e67efb2aab0e | 109 | |
| mbed_official | 354:e67efb2aab0e | 110 | uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait |
| mbed_official | 354:e67efb2aab0e | 111 | signal, valid for Flash memory access in burst mode. |
| mbed_official | 354:e67efb2aab0e | 112 | This parameter can be a value of @ref FSMC_Wait_Signal */ |
| mbed_official | 354:e67efb2aab0e | 113 | |
| mbed_official | 354:e67efb2aab0e | 114 | uint32_t ExtendedMode; /*!< Enables or disables the extended mode. |
| mbed_official | 354:e67efb2aab0e | 115 | This parameter can be a value of @ref FSMC_Extended_Mode */ |
| mbed_official | 354:e67efb2aab0e | 116 | |
| mbed_official | 354:e67efb2aab0e | 117 | uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers, |
| mbed_official | 354:e67efb2aab0e | 118 | valid only with asynchronous Flash memories. |
| mbed_official | 354:e67efb2aab0e | 119 | This parameter can be a value of @ref FSMC_AsynchronousWait */ |
| mbed_official | 354:e67efb2aab0e | 120 | |
| mbed_official | 354:e67efb2aab0e | 121 | uint32_t WriteBurst; /*!< Enables or disables the write burst operation. |
| mbed_official | 354:e67efb2aab0e | 122 | This parameter can be a value of @ref FSMC_Write_Burst */ |
| mbed_official | 354:e67efb2aab0e | 123 | |
| mbed_official | 354:e67efb2aab0e | 124 | }FSMC_NORSRAM_InitTypeDef; |
| mbed_official | 354:e67efb2aab0e | 125 | |
| mbed_official | 354:e67efb2aab0e | 126 | |
| mbed_official | 354:e67efb2aab0e | 127 | /** |
| mbed_official | 354:e67efb2aab0e | 128 | * @brief FSMC_NORSRAM Timing parameters structure definition |
| mbed_official | 354:e67efb2aab0e | 129 | */ |
| mbed_official | 354:e67efb2aab0e | 130 | typedef struct |
| mbed_official | 354:e67efb2aab0e | 131 | { |
| mbed_official | 354:e67efb2aab0e | 132 | uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure |
| mbed_official | 354:e67efb2aab0e | 133 | the duration of the address setup time. |
| mbed_official | 354:e67efb2aab0e | 134 | This parameter can be a value between Min_Data = 0 and Max_Data = 15. |
| mbed_official | 354:e67efb2aab0e | 135 | @note This parameter is not used with synchronous NOR Flash memories. */ |
| mbed_official | 354:e67efb2aab0e | 136 | |
| mbed_official | 354:e67efb2aab0e | 137 | uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure |
| mbed_official | 354:e67efb2aab0e | 138 | the duration of the address hold time. |
| mbed_official | 354:e67efb2aab0e | 139 | This parameter can be a value between Min_Data = 1 and Max_Data = 15. |
| mbed_official | 354:e67efb2aab0e | 140 | @note This parameter is not used with synchronous NOR Flash memories. */ |
| mbed_official | 354:e67efb2aab0e | 141 | |
| mbed_official | 354:e67efb2aab0e | 142 | uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure |
| mbed_official | 354:e67efb2aab0e | 143 | the duration of the data setup time. |
| mbed_official | 354:e67efb2aab0e | 144 | This parameter can be a value between Min_Data = 1 and Max_Data = 255. |
| mbed_official | 354:e67efb2aab0e | 145 | @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed |
| mbed_official | 354:e67efb2aab0e | 146 | NOR Flash memories. */ |
| mbed_official | 354:e67efb2aab0e | 147 | |
| mbed_official | 354:e67efb2aab0e | 148 | uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure |
| mbed_official | 354:e67efb2aab0e | 149 | the duration of the bus turnaround. |
| mbed_official | 354:e67efb2aab0e | 150 | This parameter can be a value between Min_Data = 0 and Max_Data = 15. |
| mbed_official | 354:e67efb2aab0e | 151 | @note This parameter is only used for multiplexed NOR Flash memories. */ |
| mbed_official | 354:e67efb2aab0e | 152 | |
| mbed_official | 354:e67efb2aab0e | 153 | uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of |
| mbed_official | 354:e67efb2aab0e | 154 | HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16. |
| mbed_official | 354:e67efb2aab0e | 155 | @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM |
| mbed_official | 354:e67efb2aab0e | 156 | accesses. */ |
| mbed_official | 354:e67efb2aab0e | 157 | |
| mbed_official | 354:e67efb2aab0e | 158 | uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue |
| mbed_official | 354:e67efb2aab0e | 159 | to the memory before getting the first data. |
| mbed_official | 354:e67efb2aab0e | 160 | The parameter value depends on the memory type as shown below: |
| mbed_official | 354:e67efb2aab0e | 161 | - It must be set to 0 in case of a CRAM |
| mbed_official | 354:e67efb2aab0e | 162 | - It is don't care in asynchronous NOR, SRAM or ROM accesses |
| mbed_official | 354:e67efb2aab0e | 163 | - It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories |
| mbed_official | 354:e67efb2aab0e | 164 | with synchronous burst mode enable */ |
| mbed_official | 354:e67efb2aab0e | 165 | |
| mbed_official | 354:e67efb2aab0e | 166 | uint32_t AccessMode; /*!< Specifies the asynchronous access mode. |
| mbed_official | 354:e67efb2aab0e | 167 | This parameter can be a value of @ref FSMC_Access_Mode */ |
| mbed_official | 354:e67efb2aab0e | 168 | |
| mbed_official | 354:e67efb2aab0e | 169 | }FSMC_NORSRAM_TimingTypeDef; |
| mbed_official | 354:e67efb2aab0e | 170 | |
| mbed_official | 354:e67efb2aab0e | 171 | /** |
| mbed_official | 354:e67efb2aab0e | 172 | * @} |
| mbed_official | 354:e67efb2aab0e | 173 | */ |
| mbed_official | 354:e67efb2aab0e | 174 | |
| mbed_official | 354:e67efb2aab0e | 175 | /* Exported constants --------------------------------------------------------*/ |
| mbed_official | 354:e67efb2aab0e | 176 | |
| mbed_official | 354:e67efb2aab0e | 177 | /** @defgroup FSMC_NORSRAM_Exported_constants FSMC NOR/SRAM Exported constants |
| mbed_official | 354:e67efb2aab0e | 178 | * @{ |
| mbed_official | 354:e67efb2aab0e | 179 | */ |
| mbed_official | 354:e67efb2aab0e | 180 | |
| mbed_official | 354:e67efb2aab0e | 181 | /** @defgroup FSMC_NORSRAM_Bank FSMC NOR/SRAM Bank |
| mbed_official | 354:e67efb2aab0e | 182 | * @{ |
| mbed_official | 354:e67efb2aab0e | 183 | */ |
| mbed_official | 354:e67efb2aab0e | 184 | #define FSMC_BANK1_NORSRAM1 ((uint32_t)0x00000000) |
| mbed_official | 354:e67efb2aab0e | 185 | #define FSMC_BANK1_NORSRAM2 ((uint32_t)0x00000002) |
| mbed_official | 354:e67efb2aab0e | 186 | #define FSMC_BANK1_NORSRAM3 ((uint32_t)0x00000004) |
| mbed_official | 354:e67efb2aab0e | 187 | #define FSMC_BANK1_NORSRAM4 ((uint32_t)0x00000006) |
| mbed_official | 354:e67efb2aab0e | 188 | |
| mbed_official | 354:e67efb2aab0e | 189 | /* To keep compatibility with previous families */ |
| mbed_official | 354:e67efb2aab0e | 190 | #define FSMC_NORSRAM_BANK1 FSMC_BANK1_NORSRAM1 |
| mbed_official | 354:e67efb2aab0e | 191 | #define FSMC_NORSRAM_BANK2 FSMC_BANK1_NORSRAM2 |
| mbed_official | 354:e67efb2aab0e | 192 | #define FSMC_NORSRAM_BANK3 FSMC_BANK1_NORSRAM3 |
| mbed_official | 354:e67efb2aab0e | 193 | #define FSMC_NORSRAM_BANK4 FSMC_BANK1_NORSRAM4 |
| mbed_official | 354:e67efb2aab0e | 194 | |
| mbed_official | 354:e67efb2aab0e | 195 | #define IS_FSMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FSMC_BANK1_NORSRAM1) || \ |
| mbed_official | 354:e67efb2aab0e | 196 | ((__BANK__) == FSMC_BANK1_NORSRAM2) || \ |
| mbed_official | 354:e67efb2aab0e | 197 | ((__BANK__) == FSMC_BANK1_NORSRAM3) || \ |
| mbed_official | 354:e67efb2aab0e | 198 | ((__BANK__) == FSMC_BANK1_NORSRAM4)) |
| mbed_official | 354:e67efb2aab0e | 199 | /** |
| mbed_official | 354:e67efb2aab0e | 200 | * @} |
| mbed_official | 354:e67efb2aab0e | 201 | */ |
| mbed_official | 354:e67efb2aab0e | 202 | |
| mbed_official | 354:e67efb2aab0e | 203 | /** @defgroup FSMC_Data_Address_Bus_Multiplexing FSMC Data Address Bus Multiplexing |
| mbed_official | 354:e67efb2aab0e | 204 | * @{ |
| mbed_official | 354:e67efb2aab0e | 205 | */ |
| mbed_official | 354:e67efb2aab0e | 206 | |
| mbed_official | 354:e67efb2aab0e | 207 | #define FSMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000) |
| mbed_official | 354:e67efb2aab0e | 208 | #define FSMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)FSMC_BCRx_MUXEN) |
| mbed_official | 354:e67efb2aab0e | 209 | |
| mbed_official | 354:e67efb2aab0e | 210 | #define IS_FSMC_MUX(__MUX__) (((__MUX__) == FSMC_DATA_ADDRESS_MUX_DISABLE) || \ |
| mbed_official | 354:e67efb2aab0e | 211 | ((__MUX__) == FSMC_DATA_ADDRESS_MUX_ENABLE)) |
| mbed_official | 354:e67efb2aab0e | 212 | /** |
| mbed_official | 354:e67efb2aab0e | 213 | * @} |
| mbed_official | 354:e67efb2aab0e | 214 | */ |
| mbed_official | 354:e67efb2aab0e | 215 | |
| mbed_official | 354:e67efb2aab0e | 216 | /** @defgroup FSMC_Memory_Type FSMC Memory Type |
| mbed_official | 354:e67efb2aab0e | 217 | * @{ |
| mbed_official | 354:e67efb2aab0e | 218 | */ |
| mbed_official | 354:e67efb2aab0e | 219 | |
| mbed_official | 354:e67efb2aab0e | 220 | #define FSMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000) |
| mbed_official | 354:e67efb2aab0e | 221 | #define FSMC_MEMORY_TYPE_PSRAM ((uint32_t)FSMC_BCRx_MTYP_0) |
| mbed_official | 354:e67efb2aab0e | 222 | #define FSMC_MEMORY_TYPE_NOR ((uint32_t)FSMC_BCRx_MTYP_1) |
| mbed_official | 354:e67efb2aab0e | 223 | |
| mbed_official | 354:e67efb2aab0e | 224 | |
| mbed_official | 354:e67efb2aab0e | 225 | #define IS_FSMC_MEMORY(__MEMORY__) (((__MEMORY__) == FSMC_MEMORY_TYPE_SRAM) || \ |
| mbed_official | 354:e67efb2aab0e | 226 | ((__MEMORY__) == FSMC_MEMORY_TYPE_PSRAM)|| \ |
| mbed_official | 354:e67efb2aab0e | 227 | ((__MEMORY__) == FSMC_MEMORY_TYPE_NOR)) |
| mbed_official | 354:e67efb2aab0e | 228 | /** |
| mbed_official | 354:e67efb2aab0e | 229 | * @} |
| mbed_official | 354:e67efb2aab0e | 230 | */ |
| mbed_official | 354:e67efb2aab0e | 231 | |
| mbed_official | 354:e67efb2aab0e | 232 | /** @defgroup FSMC_NORSRAM_Data_Width FSMC NOR/SRAM Data Width |
| mbed_official | 354:e67efb2aab0e | 233 | * @{ |
| mbed_official | 354:e67efb2aab0e | 234 | */ |
| mbed_official | 354:e67efb2aab0e | 235 | |
| mbed_official | 354:e67efb2aab0e | 236 | #define FSMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000) |
| mbed_official | 354:e67efb2aab0e | 237 | #define FSMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)FSMC_BCRx_MWID_0) |
| mbed_official | 354:e67efb2aab0e | 238 | #define FSMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)FSMC_BCRx_MWID_1) |
| mbed_official | 354:e67efb2aab0e | 239 | |
| mbed_official | 354:e67efb2aab0e | 240 | #define IS_FSMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_8) || \ |
| mbed_official | 354:e67efb2aab0e | 241 | ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_16) || \ |
| mbed_official | 354:e67efb2aab0e | 242 | ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_32)) |
| mbed_official | 354:e67efb2aab0e | 243 | /** |
| mbed_official | 354:e67efb2aab0e | 244 | * @} |
| mbed_official | 354:e67efb2aab0e | 245 | */ |
| mbed_official | 354:e67efb2aab0e | 246 | |
| mbed_official | 354:e67efb2aab0e | 247 | /** @defgroup FSMC_NORSRAM_Flash_Access FSMC NOR/SRAM Flash Access |
| mbed_official | 354:e67efb2aab0e | 248 | * @{ |
| mbed_official | 354:e67efb2aab0e | 249 | */ |
| mbed_official | 354:e67efb2aab0e | 250 | |
| mbed_official | 354:e67efb2aab0e | 251 | #define FSMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)FSMC_BCRx_FACCEN) |
| mbed_official | 354:e67efb2aab0e | 252 | #define FSMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000) |
| mbed_official | 354:e67efb2aab0e | 253 | /** |
| mbed_official | 354:e67efb2aab0e | 254 | * @} |
| mbed_official | 354:e67efb2aab0e | 255 | */ |
| mbed_official | 354:e67efb2aab0e | 256 | |
| mbed_official | 354:e67efb2aab0e | 257 | /** @defgroup FSMC_Burst_Access_Mode FSMC Burst Access Mode |
| mbed_official | 354:e67efb2aab0e | 258 | * @{ |
| mbed_official | 354:e67efb2aab0e | 259 | */ |
| mbed_official | 354:e67efb2aab0e | 260 | |
| mbed_official | 354:e67efb2aab0e | 261 | #define FSMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000) |
| mbed_official | 354:e67efb2aab0e | 262 | #define FSMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)FSMC_BCRx_BURSTEN) |
| mbed_official | 354:e67efb2aab0e | 263 | |
| mbed_official | 354:e67efb2aab0e | 264 | #define IS_FSMC_BURSTMODE(__STATE__) (((__STATE__) == FSMC_BURST_ACCESS_MODE_DISABLE) || \ |
| mbed_official | 354:e67efb2aab0e | 265 | ((__STATE__) == FSMC_BURST_ACCESS_MODE_ENABLE)) |
| mbed_official | 354:e67efb2aab0e | 266 | /** |
| mbed_official | 354:e67efb2aab0e | 267 | * @} |
| mbed_official | 354:e67efb2aab0e | 268 | */ |
| mbed_official | 354:e67efb2aab0e | 269 | |
| mbed_official | 354:e67efb2aab0e | 270 | |
| mbed_official | 354:e67efb2aab0e | 271 | /** @defgroup FSMC_Wait_Signal_Polarity FSMC Wait Signal Polarity |
| mbed_official | 354:e67efb2aab0e | 272 | * @{ |
| mbed_official | 354:e67efb2aab0e | 273 | */ |
| mbed_official | 354:e67efb2aab0e | 274 | |
| mbed_official | 354:e67efb2aab0e | 275 | #define FSMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000) |
| mbed_official | 354:e67efb2aab0e | 276 | #define FSMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)FSMC_BCRx_WAITPOL) |
| mbed_official | 354:e67efb2aab0e | 277 | |
| mbed_official | 354:e67efb2aab0e | 278 | #define IS_FSMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_LOW) || \ |
| mbed_official | 354:e67efb2aab0e | 279 | ((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_HIGH)) |
| mbed_official | 354:e67efb2aab0e | 280 | /** |
| mbed_official | 354:e67efb2aab0e | 281 | * @} |
| mbed_official | 354:e67efb2aab0e | 282 | */ |
| mbed_official | 354:e67efb2aab0e | 283 | |
| mbed_official | 354:e67efb2aab0e | 284 | /** @defgroup FSMC_Wrap_Mode FSMC Wrap Mode |
| mbed_official | 354:e67efb2aab0e | 285 | * @{ |
| mbed_official | 354:e67efb2aab0e | 286 | */ |
| mbed_official | 354:e67efb2aab0e | 287 | |
| mbed_official | 354:e67efb2aab0e | 288 | #define FSMC_WRAP_MODE_DISABLE ((uint32_t)0x00000000) |
| mbed_official | 354:e67efb2aab0e | 289 | #define FSMC_WRAP_MODE_ENABLE ((uint32_t)FSMC_BCRx_WRAPMOD) |
| mbed_official | 354:e67efb2aab0e | 290 | |
| mbed_official | 354:e67efb2aab0e | 291 | #define IS_FSMC_WRAP_MODE(__MODE__) (((__MODE__) == FSMC_WRAP_MODE_DISABLE) || \ |
| mbed_official | 354:e67efb2aab0e | 292 | ((__MODE__) == FSMC_WRAP_MODE_ENABLE)) |
| mbed_official | 354:e67efb2aab0e | 293 | /** |
| mbed_official | 354:e67efb2aab0e | 294 | * @} |
| mbed_official | 354:e67efb2aab0e | 295 | */ |
| mbed_official | 354:e67efb2aab0e | 296 | |
| mbed_official | 354:e67efb2aab0e | 297 | /** @defgroup FSMC_Wait_Timing FSMC Wait Timing |
| mbed_official | 354:e67efb2aab0e | 298 | * @{ |
| mbed_official | 354:e67efb2aab0e | 299 | */ |
| mbed_official | 354:e67efb2aab0e | 300 | |
| mbed_official | 354:e67efb2aab0e | 301 | #define FSMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000) |
| mbed_official | 354:e67efb2aab0e | 302 | #define FSMC_WAIT_TIMING_DURING_WS ((uint32_t)FSMC_BCRx_WAITCFG) |
| mbed_official | 354:e67efb2aab0e | 303 | |
| mbed_official | 354:e67efb2aab0e | 304 | #define IS_FSMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FSMC_WAIT_TIMING_BEFORE_WS) || \ |
| mbed_official | 354:e67efb2aab0e | 305 | ((__ACTIVE__) == FSMC_WAIT_TIMING_DURING_WS)) |
| mbed_official | 354:e67efb2aab0e | 306 | /** |
| mbed_official | 354:e67efb2aab0e | 307 | * @} |
| mbed_official | 354:e67efb2aab0e | 308 | */ |
| mbed_official | 354:e67efb2aab0e | 309 | |
| mbed_official | 354:e67efb2aab0e | 310 | /** @defgroup FSMC_Write_Operation FSMC Write Operation |
| mbed_official | 354:e67efb2aab0e | 311 | * @{ |
| mbed_official | 354:e67efb2aab0e | 312 | */ |
| mbed_official | 354:e67efb2aab0e | 313 | |
| mbed_official | 354:e67efb2aab0e | 314 | #define FSMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000) |
| mbed_official | 354:e67efb2aab0e | 315 | #define FSMC_WRITE_OPERATION_ENABLE ((uint32_t)FSMC_BCRx_WREN) |
| mbed_official | 354:e67efb2aab0e | 316 | |
| mbed_official | 354:e67efb2aab0e | 317 | #define IS_FSMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FSMC_WRITE_OPERATION_DISABLE) || \ |
| mbed_official | 354:e67efb2aab0e | 318 | ((__OPERATION__) == FSMC_WRITE_OPERATION_ENABLE)) |
| mbed_official | 354:e67efb2aab0e | 319 | /** |
| mbed_official | 354:e67efb2aab0e | 320 | * @} |
| mbed_official | 354:e67efb2aab0e | 321 | */ |
| mbed_official | 354:e67efb2aab0e | 322 | |
| mbed_official | 354:e67efb2aab0e | 323 | /** @defgroup FSMC_Wait_Signal FSMC Wait Signal |
| mbed_official | 354:e67efb2aab0e | 324 | * @{ |
| mbed_official | 354:e67efb2aab0e | 325 | */ |
| mbed_official | 354:e67efb2aab0e | 326 | |
| mbed_official | 354:e67efb2aab0e | 327 | #define FSMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000) |
| mbed_official | 354:e67efb2aab0e | 328 | #define FSMC_WAIT_SIGNAL_ENABLE ((uint32_t)FSMC_BCRx_WAITEN) |
| mbed_official | 354:e67efb2aab0e | 329 | |
| mbed_official | 354:e67efb2aab0e | 330 | #define IS_FSMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FSMC_WAIT_SIGNAL_DISABLE) || \ |
| mbed_official | 354:e67efb2aab0e | 331 | ((__SIGNAL__) == FSMC_WAIT_SIGNAL_ENABLE)) |
| mbed_official | 354:e67efb2aab0e | 332 | |
| mbed_official | 354:e67efb2aab0e | 333 | /** |
| mbed_official | 354:e67efb2aab0e | 334 | * @} |
| mbed_official | 354:e67efb2aab0e | 335 | */ |
| mbed_official | 354:e67efb2aab0e | 336 | |
| mbed_official | 354:e67efb2aab0e | 337 | /** @defgroup FSMC_Extended_Mode FSMC Extended Mode |
| mbed_official | 354:e67efb2aab0e | 338 | * @{ |
| mbed_official | 354:e67efb2aab0e | 339 | */ |
| mbed_official | 354:e67efb2aab0e | 340 | |
| mbed_official | 354:e67efb2aab0e | 341 | #define FSMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000) |
| mbed_official | 354:e67efb2aab0e | 342 | #define FSMC_EXTENDED_MODE_ENABLE ((uint32_t)FSMC_BCRx_EXTMOD) |
| mbed_official | 354:e67efb2aab0e | 343 | |
| mbed_official | 354:e67efb2aab0e | 344 | #define IS_FSMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FSMC_EXTENDED_MODE_DISABLE) || \ |
| mbed_official | 354:e67efb2aab0e | 345 | ((__MODE__) == FSMC_EXTENDED_MODE_ENABLE)) |
| mbed_official | 354:e67efb2aab0e | 346 | /** |
| mbed_official | 354:e67efb2aab0e | 347 | * @} |
| mbed_official | 354:e67efb2aab0e | 348 | */ |
| mbed_official | 354:e67efb2aab0e | 349 | |
| mbed_official | 354:e67efb2aab0e | 350 | /** @defgroup FSMC_AsynchronousWait FSMC Asynchronous Wait |
| mbed_official | 354:e67efb2aab0e | 351 | * @{ |
| mbed_official | 354:e67efb2aab0e | 352 | */ |
| mbed_official | 354:e67efb2aab0e | 353 | |
| mbed_official | 354:e67efb2aab0e | 354 | #define FSMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000) |
| mbed_official | 354:e67efb2aab0e | 355 | #define FSMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)FSMC_BCRx_ASYNCWAIT) |
| mbed_official | 354:e67efb2aab0e | 356 | |
| mbed_official | 354:e67efb2aab0e | 357 | #define IS_FSMC_ASYNWAIT(__STATE__) (((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_DISABLE) || \ |
| mbed_official | 354:e67efb2aab0e | 358 | ((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_ENABLE)) |
| mbed_official | 354:e67efb2aab0e | 359 | |
| mbed_official | 354:e67efb2aab0e | 360 | /** |
| mbed_official | 354:e67efb2aab0e | 361 | * @} |
| mbed_official | 354:e67efb2aab0e | 362 | */ |
| mbed_official | 354:e67efb2aab0e | 363 | |
| mbed_official | 354:e67efb2aab0e | 364 | /** @defgroup FSMC_Write_Burst FSMC Write Burst |
| mbed_official | 354:e67efb2aab0e | 365 | * @{ |
| mbed_official | 354:e67efb2aab0e | 366 | */ |
| mbed_official | 354:e67efb2aab0e | 367 | |
| mbed_official | 354:e67efb2aab0e | 368 | #define FSMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000) |
| mbed_official | 354:e67efb2aab0e | 369 | #define FSMC_WRITE_BURST_ENABLE ((uint32_t)FSMC_BCRx_CBURSTRW) |
| mbed_official | 354:e67efb2aab0e | 370 | |
| mbed_official | 354:e67efb2aab0e | 371 | #define IS_FSMC_WRITE_BURST(__BURST__) (((__BURST__) == FSMC_WRITE_BURST_DISABLE) || \ |
| mbed_official | 354:e67efb2aab0e | 372 | ((__BURST__) == FSMC_WRITE_BURST_ENABLE)) |
| mbed_official | 354:e67efb2aab0e | 373 | /** |
| mbed_official | 354:e67efb2aab0e | 374 | * @} |
| mbed_official | 354:e67efb2aab0e | 375 | */ |
| mbed_official | 354:e67efb2aab0e | 376 | |
| mbed_official | 354:e67efb2aab0e | 377 | /** @defgroup FSMC_Address_Setup_Time FSMC Address Setup Time |
| mbed_official | 354:e67efb2aab0e | 378 | * @{ |
| mbed_official | 354:e67efb2aab0e | 379 | */ |
| mbed_official | 354:e67efb2aab0e | 380 | |
| mbed_official | 354:e67efb2aab0e | 381 | #define IS_FSMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15) |
| mbed_official | 354:e67efb2aab0e | 382 | /** |
| mbed_official | 354:e67efb2aab0e | 383 | * @} |
| mbed_official | 354:e67efb2aab0e | 384 | */ |
| mbed_official | 354:e67efb2aab0e | 385 | |
| mbed_official | 354:e67efb2aab0e | 386 | /** @defgroup FSMC_Address_Hold_Time FSMC Address Hold Time |
| mbed_official | 354:e67efb2aab0e | 387 | * @{ |
| mbed_official | 354:e67efb2aab0e | 388 | */ |
| mbed_official | 354:e67efb2aab0e | 389 | |
| mbed_official | 354:e67efb2aab0e | 390 | #define IS_FSMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 15)) |
| mbed_official | 354:e67efb2aab0e | 391 | /** |
| mbed_official | 354:e67efb2aab0e | 392 | * @} |
| mbed_official | 354:e67efb2aab0e | 393 | */ |
| mbed_official | 354:e67efb2aab0e | 394 | |
| mbed_official | 354:e67efb2aab0e | 395 | /** @defgroup FSMC_Data_Setup_Time FSMC Data Setup Time |
| mbed_official | 354:e67efb2aab0e | 396 | * @{ |
| mbed_official | 354:e67efb2aab0e | 397 | */ |
| mbed_official | 354:e67efb2aab0e | 398 | |
| mbed_official | 354:e67efb2aab0e | 399 | #define IS_FSMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 255)) |
| mbed_official | 354:e67efb2aab0e | 400 | /** |
| mbed_official | 354:e67efb2aab0e | 401 | * @} |
| mbed_official | 354:e67efb2aab0e | 402 | */ |
| mbed_official | 354:e67efb2aab0e | 403 | |
| mbed_official | 354:e67efb2aab0e | 404 | /** @defgroup FSMC_Bus_Turn_around_Duration FSMC Bus Turn around Duration |
| mbed_official | 354:e67efb2aab0e | 405 | * @{ |
| mbed_official | 354:e67efb2aab0e | 406 | */ |
| mbed_official | 354:e67efb2aab0e | 407 | |
| mbed_official | 354:e67efb2aab0e | 408 | #define IS_FSMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15) |
| mbed_official | 354:e67efb2aab0e | 409 | /** |
| mbed_official | 354:e67efb2aab0e | 410 | * @} |
| mbed_official | 354:e67efb2aab0e | 411 | */ |
| mbed_official | 354:e67efb2aab0e | 412 | |
| mbed_official | 354:e67efb2aab0e | 413 | /** @defgroup FSMC_CLK_Division FSMC CLK Division |
| mbed_official | 354:e67efb2aab0e | 414 | * @{ |
| mbed_official | 354:e67efb2aab0e | 415 | */ |
| mbed_official | 354:e67efb2aab0e | 416 | |
| mbed_official | 354:e67efb2aab0e | 417 | #define FSMC_CLK_DIV2 ((uint32_t)0x00000002) |
| mbed_official | 354:e67efb2aab0e | 418 | #define FSMC_CLK_DIV3 ((uint32_t)0x00000003) |
| mbed_official | 354:e67efb2aab0e | 419 | #define FSMC_CLK_DIV4 ((uint32_t)0x00000004) |
| mbed_official | 354:e67efb2aab0e | 420 | #define FSMC_CLK_DIV5 ((uint32_t)0x00000005) |
| mbed_official | 354:e67efb2aab0e | 421 | #define FSMC_CLK_DIV6 ((uint32_t)0x00000006) |
| mbed_official | 354:e67efb2aab0e | 422 | #define FSMC_CLK_DIV7 ((uint32_t)0x00000007) |
| mbed_official | 354:e67efb2aab0e | 423 | #define FSMC_CLK_DIV8 ((uint32_t)0x00000008) |
| mbed_official | 354:e67efb2aab0e | 424 | #define FSMC_CLK_DIV9 ((uint32_t)0x00000009) |
| mbed_official | 354:e67efb2aab0e | 425 | #define FSMC_CLK_DIV10 ((uint32_t)0x0000000A) |
| mbed_official | 354:e67efb2aab0e | 426 | #define FSMC_CLK_DIV11 ((uint32_t)0x0000000B) |
| mbed_official | 354:e67efb2aab0e | 427 | #define FSMC_CLK_DIV12 ((uint32_t)0x0000000C) |
| mbed_official | 354:e67efb2aab0e | 428 | #define FSMC_CLK_DIV13 ((uint32_t)0x0000000D) |
| mbed_official | 354:e67efb2aab0e | 429 | #define FSMC_CLK_DIV14 ((uint32_t)0x0000000E) |
| mbed_official | 354:e67efb2aab0e | 430 | #define FSMC_CLK_DIV15 ((uint32_t)0x0000000F) |
| mbed_official | 354:e67efb2aab0e | 431 | #define FSMC_CLK_DIV16 ((uint32_t)0x00000010) |
| mbed_official | 354:e67efb2aab0e | 432 | #define IS_FSMC_CLK_DIV(__DIV__) (((__DIV__) > 1) && ((__DIV__) <= 16)) |
| mbed_official | 354:e67efb2aab0e | 433 | /** |
| mbed_official | 354:e67efb2aab0e | 434 | * @} |
| mbed_official | 354:e67efb2aab0e | 435 | */ |
| mbed_official | 354:e67efb2aab0e | 436 | |
| mbed_official | 354:e67efb2aab0e | 437 | /** @defgroup FSMC_Data_Latency FSMC Data Latency |
| mbed_official | 354:e67efb2aab0e | 438 | * @{ |
| mbed_official | 354:e67efb2aab0e | 439 | */ |
| mbed_official | 354:e67efb2aab0e | 440 | |
| mbed_official | 354:e67efb2aab0e | 441 | #define IS_FSMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1) && ((__LATENCY__) <= 17)) |
| mbed_official | 354:e67efb2aab0e | 442 | /** |
| mbed_official | 354:e67efb2aab0e | 443 | * @} |
| mbed_official | 354:e67efb2aab0e | 444 | */ |
| mbed_official | 354:e67efb2aab0e | 445 | |
| mbed_official | 354:e67efb2aab0e | 446 | /** @defgroup FSMC_Access_Mode FSMC Access Mode |
| mbed_official | 354:e67efb2aab0e | 447 | * @{ |
| mbed_official | 354:e67efb2aab0e | 448 | */ |
| mbed_official | 354:e67efb2aab0e | 449 | |
| mbed_official | 354:e67efb2aab0e | 450 | #define FSMC_ACCESS_MODE_A ((uint32_t)0x00000000) |
| mbed_official | 354:e67efb2aab0e | 451 | #define FSMC_ACCESS_MODE_B ((uint32_t)FSMC_BTRx_ACCMOD_0) |
| mbed_official | 354:e67efb2aab0e | 452 | #define FSMC_ACCESS_MODE_C ((uint32_t)FSMC_BTRx_ACCMOD_1) |
| mbed_official | 354:e67efb2aab0e | 453 | #define FSMC_ACCESS_MODE_D ((uint32_t)(FSMC_BTRx_ACCMOD_0 | FSMC_BTRx_ACCMOD_1)) |
| mbed_official | 354:e67efb2aab0e | 454 | |
| mbed_official | 354:e67efb2aab0e | 455 | #define IS_FSMC_ACCESS_MODE(__MODE__) (((__MODE__) == FSMC_ACCESS_MODE_A) || \ |
| mbed_official | 354:e67efb2aab0e | 456 | ((__MODE__) == FSMC_ACCESS_MODE_B) || \ |
| mbed_official | 354:e67efb2aab0e | 457 | ((__MODE__) == FSMC_ACCESS_MODE_C) || \ |
| mbed_official | 354:e67efb2aab0e | 458 | ((__MODE__) == FSMC_ACCESS_MODE_D)) |
| mbed_official | 354:e67efb2aab0e | 459 | /** |
| mbed_official | 354:e67efb2aab0e | 460 | * @} |
| mbed_official | 354:e67efb2aab0e | 461 | */ |
| mbed_official | 354:e67efb2aab0e | 462 | |
| mbed_official | 354:e67efb2aab0e | 463 | /** @defgroup FSMC_NORSRAM_Device_Instance FSMC NOR/SRAM Device Instance |
| mbed_official | 354:e67efb2aab0e | 464 | * @{ |
| mbed_official | 354:e67efb2aab0e | 465 | */ |
| mbed_official | 354:e67efb2aab0e | 466 | |
| mbed_official | 354:e67efb2aab0e | 467 | #define IS_FSMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_DEVICE) |
| mbed_official | 354:e67efb2aab0e | 468 | |
| mbed_official | 354:e67efb2aab0e | 469 | /** |
| mbed_official | 354:e67efb2aab0e | 470 | * @} |
| mbed_official | 354:e67efb2aab0e | 471 | */ |
| mbed_official | 354:e67efb2aab0e | 472 | |
| mbed_official | 354:e67efb2aab0e | 473 | /** @defgroup FSMC_NORSRAM_EXTENDED_Device_Instance FSMC NOR/SRAM EXTENDED Device Instance |
| mbed_official | 354:e67efb2aab0e | 474 | * @{ |
| mbed_official | 354:e67efb2aab0e | 475 | */ |
| mbed_official | 354:e67efb2aab0e | 476 | |
| mbed_official | 354:e67efb2aab0e | 477 | #define IS_FSMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_EXTENDED_DEVICE) |
| mbed_official | 354:e67efb2aab0e | 478 | |
| mbed_official | 354:e67efb2aab0e | 479 | /** |
| mbed_official | 354:e67efb2aab0e | 480 | * @} |
| mbed_official | 354:e67efb2aab0e | 481 | */ |
| mbed_official | 354:e67efb2aab0e | 482 | |
| mbed_official | 354:e67efb2aab0e | 483 | /** |
| mbed_official | 354:e67efb2aab0e | 484 | * @} |
| mbed_official | 354:e67efb2aab0e | 485 | */ |
| mbed_official | 354:e67efb2aab0e | 486 | |
| mbed_official | 354:e67efb2aab0e | 487 | /* Exported macro ------------------------------------------------------------*/ |
| mbed_official | 354:e67efb2aab0e | 488 | |
| mbed_official | 354:e67efb2aab0e | 489 | /** @defgroup FSMC_NOR_Macros FSMC NOR/SRAM Exported Macros |
| mbed_official | 354:e67efb2aab0e | 490 | * @brief macros to handle NOR device enable/disable and read/write operations |
| mbed_official | 354:e67efb2aab0e | 491 | * @{ |
| mbed_official | 354:e67efb2aab0e | 492 | */ |
| mbed_official | 354:e67efb2aab0e | 493 | |
| mbed_official | 354:e67efb2aab0e | 494 | /** |
| mbed_official | 354:e67efb2aab0e | 495 | * @brief Enable the NORSRAM device access. |
| mbed_official | 354:e67efb2aab0e | 496 | * @param __INSTANCE__: FSMC_NORSRAM Instance |
| mbed_official | 354:e67efb2aab0e | 497 | * @param __BANK__: FSMC_NORSRAM Bank |
| mbed_official | 354:e67efb2aab0e | 498 | * @retval none |
| mbed_official | 354:e67efb2aab0e | 499 | */ |
| mbed_official | 354:e67efb2aab0e | 500 | #define __FSMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] |= FSMC_BCRx_MBKEN) |
| mbed_official | 354:e67efb2aab0e | 501 | |
| mbed_official | 354:e67efb2aab0e | 502 | /** |
| mbed_official | 354:e67efb2aab0e | 503 | * @brief Disable the NORSRAM device access. |
| mbed_official | 354:e67efb2aab0e | 504 | * @param __INSTANCE__: FSMC_NORSRAM Instance |
| mbed_official | 354:e67efb2aab0e | 505 | * @param __BANK__: FSMC_NORSRAM Bank |
| mbed_official | 354:e67efb2aab0e | 506 | * @retval none |
| mbed_official | 354:e67efb2aab0e | 507 | */ |
| mbed_official | 354:e67efb2aab0e | 508 | #define __FSMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FSMC_BCRx_MBKEN) |
| mbed_official | 354:e67efb2aab0e | 509 | |
| mbed_official | 354:e67efb2aab0e | 510 | /** |
| mbed_official | 354:e67efb2aab0e | 511 | * @} |
| mbed_official | 354:e67efb2aab0e | 512 | */ |
| mbed_official | 354:e67efb2aab0e | 513 | |
| mbed_official | 354:e67efb2aab0e | 514 | /* Exported functions --------------------------------------------------------*/ |
| mbed_official | 354:e67efb2aab0e | 515 | |
| mbed_official | 354:e67efb2aab0e | 516 | /** @addtogroup FSMC_Exported_Functions |
| mbed_official | 354:e67efb2aab0e | 517 | * @{ |
| mbed_official | 354:e67efb2aab0e | 518 | */ |
| mbed_official | 354:e67efb2aab0e | 519 | |
| mbed_official | 354:e67efb2aab0e | 520 | /** @addtogroup HAL_FSMC_NORSRAM_Group1 |
| mbed_official | 354:e67efb2aab0e | 521 | * @{ |
| mbed_official | 354:e67efb2aab0e | 522 | */ |
| mbed_official | 354:e67efb2aab0e | 523 | |
| mbed_official | 354:e67efb2aab0e | 524 | /* FSMC_NORSRAM Controller functions ******************************************/ |
| mbed_official | 354:e67efb2aab0e | 525 | /* Initialization/de-initialization functions */ |
| mbed_official | 354:e67efb2aab0e | 526 | HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TYPEDEF *Device, FSMC_NORSRAM_InitTypeDef *Init); |
| mbed_official | 354:e67efb2aab0e | 527 | HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TYPEDEF *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank); |
| mbed_official | 354:e67efb2aab0e | 528 | HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TYPEDEF *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode); |
| mbed_official | 354:e67efb2aab0e | 529 | HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TYPEDEF *Device, FSMC_NORSRAM_EXTENDED_TYPEDEF *ExDevice, uint32_t Bank); |
| mbed_official | 354:e67efb2aab0e | 530 | |
| mbed_official | 354:e67efb2aab0e | 531 | /** |
| mbed_official | 354:e67efb2aab0e | 532 | * @} |
| mbed_official | 354:e67efb2aab0e | 533 | */ |
| mbed_official | 354:e67efb2aab0e | 534 | |
| mbed_official | 354:e67efb2aab0e | 535 | /** @addtogroup HAL_FSMC_NORSRAM_Group2 |
| mbed_official | 354:e67efb2aab0e | 536 | * @{ |
| mbed_official | 354:e67efb2aab0e | 537 | */ |
| mbed_official | 354:e67efb2aab0e | 538 | |
| mbed_official | 354:e67efb2aab0e | 539 | /* FSMC_NORSRAM Control functions */ |
| mbed_official | 354:e67efb2aab0e | 540 | HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TYPEDEF *Device, uint32_t Bank); |
| mbed_official | 354:e67efb2aab0e | 541 | HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TYPEDEF *Device, uint32_t Bank); |
| mbed_official | 354:e67efb2aab0e | 542 | |
| mbed_official | 354:e67efb2aab0e | 543 | /** |
| mbed_official | 354:e67efb2aab0e | 544 | * @} |
| mbed_official | 354:e67efb2aab0e | 545 | */ |
| mbed_official | 354:e67efb2aab0e | 546 | |
| mbed_official | 354:e67efb2aab0e | 547 | #endif /* STM32L151xD || STM32L152xD || STM32L162xD */ |
| mbed_official | 354:e67efb2aab0e | 548 | |
| mbed_official | 354:e67efb2aab0e | 549 | /** |
| mbed_official | 354:e67efb2aab0e | 550 | * @} |
| mbed_official | 354:e67efb2aab0e | 551 | */ |
| mbed_official | 354:e67efb2aab0e | 552 | |
| mbed_official | 354:e67efb2aab0e | 553 | /** |
| mbed_official | 354:e67efb2aab0e | 554 | * @} |
| mbed_official | 354:e67efb2aab0e | 555 | */ |
| mbed_official | 354:e67efb2aab0e | 556 | |
| mbed_official | 354:e67efb2aab0e | 557 | /** |
| mbed_official | 354:e67efb2aab0e | 558 | * @} |
| mbed_official | 354:e67efb2aab0e | 559 | */ |
| mbed_official | 354:e67efb2aab0e | 560 | |
| mbed_official | 354:e67efb2aab0e | 561 | #ifdef __cplusplus |
| mbed_official | 354:e67efb2aab0e | 562 | } |
| mbed_official | 354:e67efb2aab0e | 563 | #endif |
| mbed_official | 354:e67efb2aab0e | 564 | |
| mbed_official | 354:e67efb2aab0e | 565 | #endif /* __STM32L1xx_LL_FSMC_H */ |
| mbed_official | 354:e67efb2aab0e | 566 | |
| mbed_official | 354:e67efb2aab0e | 567 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
