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Last commit 20 Feb 2019 by 
mbed official
targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_tim.c@579:53297373a894, 2015-07-01 (annotated)
- Committer:
- mbed_official
- Date:
- Wed Jul 01 09:45:11 2015 +0100
- Revision:
- 579:53297373a894
- Parent:
- 394:83f921546702
Synchronized with git revision d5b4d2ab9c47edb4dc5776e7177b0c2263459081
Full URL: https://github.com/mbedmicro/mbed/commit/d5b4d2ab9c47edb4dc5776e7177b0c2263459081/
Initial version of drivers for SAMR21
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| mbed_official | 354:e67efb2aab0e | 1 | /** |
| mbed_official | 354:e67efb2aab0e | 2 | ****************************************************************************** |
| mbed_official | 354:e67efb2aab0e | 3 | * @file stm32l1xx_hal_tim.c |
| mbed_official | 354:e67efb2aab0e | 4 | * @author MCD Application Team |
| mbed_official | 354:e67efb2aab0e | 5 | * @version V1.0.0 |
| mbed_official | 354:e67efb2aab0e | 6 | * @date 5-September-2014 |
| mbed_official | 354:e67efb2aab0e | 7 | * @brief TIM HAL module driver. |
| mbed_official | 354:e67efb2aab0e | 8 | * This file provides firmware functions to manage the following |
| mbed_official | 354:e67efb2aab0e | 9 | * functionalities of the Timer (TIM) peripheral: |
| mbed_official | 354:e67efb2aab0e | 10 | * + Time Base Initialization |
| mbed_official | 354:e67efb2aab0e | 11 | * + Time Base Start |
| mbed_official | 354:e67efb2aab0e | 12 | * + Time Base Start Interruption |
| mbed_official | 354:e67efb2aab0e | 13 | * + Time Base Start DMA |
| mbed_official | 354:e67efb2aab0e | 14 | * + Time Output Compare/PWM Initialization |
| mbed_official | 354:e67efb2aab0e | 15 | * + Time Output Compare/PWM Channel Configuration |
| mbed_official | 354:e67efb2aab0e | 16 | * + Time Output Compare/PWM Start |
| mbed_official | 354:e67efb2aab0e | 17 | * + Time Output Compare/PWM Start Interruption |
| mbed_official | 354:e67efb2aab0e | 18 | * + Time Output Compare/PWM Start DMA |
| mbed_official | 354:e67efb2aab0e | 19 | * + Time Input Capture Initialization |
| mbed_official | 354:e67efb2aab0e | 20 | * + Time Input Capture Channel Configuration |
| mbed_official | 354:e67efb2aab0e | 21 | * + Time Input Capture Start |
| mbed_official | 354:e67efb2aab0e | 22 | * + Time Input Capture Start Interruption |
| mbed_official | 354:e67efb2aab0e | 23 | * + Time Input Capture Start DMA |
| mbed_official | 354:e67efb2aab0e | 24 | * + Time One Pulse Initialization |
| mbed_official | 354:e67efb2aab0e | 25 | * + Time One Pulse Channel Configuration |
| mbed_official | 354:e67efb2aab0e | 26 | * + Time One Pulse Start |
| mbed_official | 354:e67efb2aab0e | 27 | * + Time Encoder Interface Initialization |
| mbed_official | 354:e67efb2aab0e | 28 | * + Time Encoder Interface Start |
| mbed_official | 354:e67efb2aab0e | 29 | * + Time Encoder Interface Start Interruption |
| mbed_official | 354:e67efb2aab0e | 30 | * + Time Encoder Interface Start DMA |
| mbed_official | 354:e67efb2aab0e | 31 | * + Commutation Event configuration with Interruption and DMA |
| mbed_official | 354:e67efb2aab0e | 32 | * + Time OCRef clear configuration |
| mbed_official | 354:e67efb2aab0e | 33 | * + Time External Clock configuration |
| mbed_official | 354:e67efb2aab0e | 34 | * + Time Master and Slave synchronization configuration |
| mbed_official | 354:e67efb2aab0e | 35 | @verbatim |
| mbed_official | 354:e67efb2aab0e | 36 | ============================================================================== |
| mbed_official | 354:e67efb2aab0e | 37 | ##### TIMER Generic features ##### |
| mbed_official | 354:e67efb2aab0e | 38 | ============================================================================== |
| mbed_official | 354:e67efb2aab0e | 39 | [..] The Timer features include: |
| mbed_official | 354:e67efb2aab0e | 40 | (#) 16-bit up, down, up/down auto-reload counter. |
| mbed_official | 354:e67efb2aab0e | 41 | (#) 16-bit programmable prescaler allowing dividing (also on the fly) the |
| mbed_official | 354:e67efb2aab0e | 42 | counter clock frequency either by any factor between 1 and 65536. |
| mbed_official | 354:e67efb2aab0e | 43 | (#) Up to 4 independent channels for: |
| mbed_official | 354:e67efb2aab0e | 44 | (++) Input Capture |
| mbed_official | 354:e67efb2aab0e | 45 | (++) Output Compare |
| mbed_official | 354:e67efb2aab0e | 46 | (++) PWM generation (Edge and Center-aligned Mode) |
| mbed_official | 354:e67efb2aab0e | 47 | (++) One-pulse mode output |
| mbed_official | 354:e67efb2aab0e | 48 | (#) Synchronization circuit to control the timer with external signals and to interconnect |
| mbed_official | 354:e67efb2aab0e | 49 | several timers together. |
| mbed_official | 354:e67efb2aab0e | 50 | (#) Supports incremental (quadrature) encoder |
| mbed_official | 354:e67efb2aab0e | 51 | |
| mbed_official | 354:e67efb2aab0e | 52 | ##### How to use this driver ##### |
| mbed_official | 354:e67efb2aab0e | 53 | ================================================================================ |
| mbed_official | 354:e67efb2aab0e | 54 | [..] |
| mbed_official | 354:e67efb2aab0e | 55 | (#) Initialize the TIM low level resources by implementing the following functions |
| mbed_official | 354:e67efb2aab0e | 56 | depending from feature used : |
| mbed_official | 354:e67efb2aab0e | 57 | (++) Time Base : HAL_TIM_Base_MspInit() |
| mbed_official | 354:e67efb2aab0e | 58 | (++) Input Capture : HAL_TIM_IC_MspInit() |
| mbed_official | 354:e67efb2aab0e | 59 | (++) Output Compare : HAL_TIM_OC_MspInit() |
| mbed_official | 354:e67efb2aab0e | 60 | (++) PWM generation : HAL_TIM_PWM_MspInit() |
| mbed_official | 354:e67efb2aab0e | 61 | (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit() |
| mbed_official | 354:e67efb2aab0e | 62 | (++) Encoder mode output : HAL_TIM_Encoder_MspInit() |
| mbed_official | 354:e67efb2aab0e | 63 | |
| mbed_official | 354:e67efb2aab0e | 64 | (#) Initialize the TIM low level resources : |
| mbed_official | 354:e67efb2aab0e | 65 | (##) Enable the TIM interface clock using __TIMx_CLK_ENABLE(); |
| mbed_official | 354:e67efb2aab0e | 66 | (##) TIM pins configuration |
| mbed_official | 354:e67efb2aab0e | 67 | (+++) Enable the clock for the TIM GPIOs using the following function: |
| mbed_official | 354:e67efb2aab0e | 68 | __GPIOx_CLK_ENABLE(); |
| mbed_official | 354:e67efb2aab0e | 69 | (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init(); |
| mbed_official | 354:e67efb2aab0e | 70 | |
| mbed_official | 354:e67efb2aab0e | 71 | (#) The external Clock can be configured, if needed (the default clock is the |
| mbed_official | 354:e67efb2aab0e | 72 | internal clock from the APBx), using the following function: |
| mbed_official | 354:e67efb2aab0e | 73 | HAL_TIM_ConfigClockSource, the clock configuration should be done before |
| mbed_official | 354:e67efb2aab0e | 74 | any start function. |
| mbed_official | 354:e67efb2aab0e | 75 | |
| mbed_official | 354:e67efb2aab0e | 76 | (#) Configure the TIM in the desired functioning mode using one of the |
| mbed_official | 354:e67efb2aab0e | 77 | Initialization function of this driver: |
| mbed_official | 354:e67efb2aab0e | 78 | (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base |
| mbed_official | 354:e67efb2aab0e | 79 | (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an |
| mbed_official | 354:e67efb2aab0e | 80 | Output Compare signal. |
| mbed_official | 354:e67efb2aab0e | 81 | (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a |
| mbed_official | 354:e67efb2aab0e | 82 | PWM signal. |
| mbed_official | 354:e67efb2aab0e | 83 | (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an |
| mbed_official | 354:e67efb2aab0e | 84 | external signal. |
| mbed_official | 354:e67efb2aab0e | 85 | (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer |
| mbed_official | 354:e67efb2aab0e | 86 | in One Pulse Mode. |
| mbed_official | 354:e67efb2aab0e | 87 | (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface. |
| mbed_official | 354:e67efb2aab0e | 88 | |
| mbed_official | 354:e67efb2aab0e | 89 | (#) Activate the TIM peripheral using one of the start functions depending from the feature used: |
| mbed_official | 354:e67efb2aab0e | 90 | (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT() |
| mbed_official | 354:e67efb2aab0e | 91 | (++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT() |
| mbed_official | 354:e67efb2aab0e | 92 | (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT() |
| mbed_official | 354:e67efb2aab0e | 93 | (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT() |
| mbed_official | 354:e67efb2aab0e | 94 | (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT() |
| mbed_official | 354:e67efb2aab0e | 95 | (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(). |
| mbed_official | 354:e67efb2aab0e | 96 | |
| mbed_official | 354:e67efb2aab0e | 97 | (#) The DMA Burst is managed with the two following functions: |
| mbed_official | 354:e67efb2aab0e | 98 | HAL_TIM_DMABurst_WriteStart() |
| mbed_official | 354:e67efb2aab0e | 99 | HAL_TIM_DMABurst_ReadStart() |
| mbed_official | 354:e67efb2aab0e | 100 | |
| mbed_official | 354:e67efb2aab0e | 101 | @endverbatim |
| mbed_official | 354:e67efb2aab0e | 102 | ****************************************************************************** |
| mbed_official | 354:e67efb2aab0e | 103 | * @attention |
| mbed_official | 354:e67efb2aab0e | 104 | * |
| mbed_official | 354:e67efb2aab0e | 105 | * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> |
| mbed_official | 354:e67efb2aab0e | 106 | * |
| mbed_official | 354:e67efb2aab0e | 107 | * Redistribution and use in source and binary forms, with or without modification, |
| mbed_official | 354:e67efb2aab0e | 108 | * are permitted provided that the following conditions are met: |
| mbed_official | 354:e67efb2aab0e | 109 | * 1. Redistributions of source code must retain the above copyright notice, |
| mbed_official | 354:e67efb2aab0e | 110 | * this list of conditions and the following disclaimer. |
| mbed_official | 354:e67efb2aab0e | 111 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| mbed_official | 354:e67efb2aab0e | 112 | * this list of conditions and the following disclaimer in the documentation |
| mbed_official | 354:e67efb2aab0e | 113 | * and/or other materials provided with the distribution. |
| mbed_official | 354:e67efb2aab0e | 114 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| mbed_official | 354:e67efb2aab0e | 115 | * may be used to endorse or promote products derived from this software |
| mbed_official | 354:e67efb2aab0e | 116 | * without specific prior written permission. |
| mbed_official | 354:e67efb2aab0e | 117 | * |
| mbed_official | 354:e67efb2aab0e | 118 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| mbed_official | 354:e67efb2aab0e | 119 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| mbed_official | 354:e67efb2aab0e | 120 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| mbed_official | 354:e67efb2aab0e | 121 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| mbed_official | 354:e67efb2aab0e | 122 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| mbed_official | 354:e67efb2aab0e | 123 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| mbed_official | 354:e67efb2aab0e | 124 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| mbed_official | 354:e67efb2aab0e | 125 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| mbed_official | 354:e67efb2aab0e | 126 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| mbed_official | 354:e67efb2aab0e | 127 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| mbed_official | 354:e67efb2aab0e | 128 | * |
| mbed_official | 354:e67efb2aab0e | 129 | ****************************************************************************** |
| mbed_official | 354:e67efb2aab0e | 130 | */ |
| mbed_official | 354:e67efb2aab0e | 131 | |
| mbed_official | 354:e67efb2aab0e | 132 | /* Includes ------------------------------------------------------------------*/ |
| mbed_official | 354:e67efb2aab0e | 133 | #include "stm32l1xx_hal.h" |
| mbed_official | 354:e67efb2aab0e | 134 | |
| mbed_official | 354:e67efb2aab0e | 135 | /** @addtogroup STM32L1xx_HAL_Driver |
| mbed_official | 354:e67efb2aab0e | 136 | * @{ |
| mbed_official | 354:e67efb2aab0e | 137 | */ |
| mbed_official | 354:e67efb2aab0e | 138 | |
| mbed_official | 354:e67efb2aab0e | 139 | /** @defgroup TIM TIM |
| mbed_official | 354:e67efb2aab0e | 140 | * @brief TIM HAL module driver |
| mbed_official | 354:e67efb2aab0e | 141 | * @{ |
| mbed_official | 354:e67efb2aab0e | 142 | */ |
| mbed_official | 354:e67efb2aab0e | 143 | |
| mbed_official | 354:e67efb2aab0e | 144 | #ifdef HAL_TIM_MODULE_ENABLED |
| mbed_official | 354:e67efb2aab0e | 145 | |
| mbed_official | 354:e67efb2aab0e | 146 | /* Private typedef -----------------------------------------------------------*/ |
| mbed_official | 354:e67efb2aab0e | 147 | /* Private define ------------------------------------------------------------*/ |
| mbed_official | 354:e67efb2aab0e | 148 | /* Private macro -------------------------------------------------------------*/ |
| mbed_official | 354:e67efb2aab0e | 149 | /* Private variables ---------------------------------------------------------*/ |
| mbed_official | 354:e67efb2aab0e | 150 | /* Private function prototypes -----------------------------------------------*/ |
| mbed_official | 354:e67efb2aab0e | 151 | /** @defgroup TIM_Private_Functions TIM Private Functions |
| mbed_official | 354:e67efb2aab0e | 152 | * @{ |
| mbed_official | 354:e67efb2aab0e | 153 | */ |
| mbed_official | 354:e67efb2aab0e | 154 | static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); |
| mbed_official | 354:e67efb2aab0e | 155 | static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); |
| mbed_official | 354:e67efb2aab0e | 156 | static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); |
| mbed_official | 354:e67efb2aab0e | 157 | |
| mbed_official | 354:e67efb2aab0e | 158 | static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter); |
| mbed_official | 354:e67efb2aab0e | 159 | static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, |
| mbed_official | 354:e67efb2aab0e | 160 | uint32_t TIM_ICFilter); |
| mbed_official | 354:e67efb2aab0e | 161 | static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter); |
| mbed_official | 354:e67efb2aab0e | 162 | static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, |
| mbed_official | 354:e67efb2aab0e | 163 | uint32_t TIM_ICFilter); |
| mbed_official | 354:e67efb2aab0e | 164 | static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, |
| mbed_official | 354:e67efb2aab0e | 165 | uint32_t TIM_ICFilter); |
| mbed_official | 354:e67efb2aab0e | 166 | |
| mbed_official | 354:e67efb2aab0e | 167 | static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler, |
| mbed_official | 354:e67efb2aab0e | 168 | uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter); |
| mbed_official | 354:e67efb2aab0e | 169 | |
| mbed_official | 354:e67efb2aab0e | 170 | static void TIM_ITRx_SetConfig(TIM_TypeDef* TIMx, uint16_t InputTriggerSource); |
| mbed_official | 354:e67efb2aab0e | 171 | static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma); |
| mbed_official | 354:e67efb2aab0e | 172 | static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma); |
| mbed_official | 354:e67efb2aab0e | 173 | static void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure); |
| mbed_official | 354:e67efb2aab0e | 174 | static void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter); |
| mbed_official | 354:e67efb2aab0e | 175 | static void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); |
| mbed_official | 354:e67efb2aab0e | 176 | static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma); |
| mbed_official | 354:e67efb2aab0e | 177 | static void TIM_DMAError(DMA_HandleTypeDef *hdma); |
| mbed_official | 354:e67efb2aab0e | 178 | static void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma); |
| mbed_official | 354:e67efb2aab0e | 179 | static void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState); |
| mbed_official | 354:e67efb2aab0e | 180 | |
| mbed_official | 354:e67efb2aab0e | 181 | /** |
| mbed_official | 354:e67efb2aab0e | 182 | * @} |
| mbed_official | 354:e67efb2aab0e | 183 | */ |
| mbed_official | 354:e67efb2aab0e | 184 | |
| mbed_official | 354:e67efb2aab0e | 185 | /* External functions ---------------------------------------------------------*/ |
| mbed_official | 354:e67efb2aab0e | 186 | |
| mbed_official | 354:e67efb2aab0e | 187 | /** @defgroup TIM_Exported_Functions TIM Exported Functions |
| mbed_official | 354:e67efb2aab0e | 188 | * @{ |
| mbed_official | 354:e67efb2aab0e | 189 | */ |
| mbed_official | 354:e67efb2aab0e | 190 | |
| mbed_official | 354:e67efb2aab0e | 191 | /** @defgroup TIM_Exported_Functions_Group1 Time Base functions |
| mbed_official | 354:e67efb2aab0e | 192 | * @brief Time Base functions |
| mbed_official | 354:e67efb2aab0e | 193 | * |
| mbed_official | 354:e67efb2aab0e | 194 | @verbatim |
| mbed_official | 354:e67efb2aab0e | 195 | ============================================================================== |
| mbed_official | 354:e67efb2aab0e | 196 | ##### Time Base functions ##### |
| mbed_official | 354:e67efb2aab0e | 197 | ============================================================================== |
| mbed_official | 354:e67efb2aab0e | 198 | [..] |
| mbed_official | 354:e67efb2aab0e | 199 | This section provides functions allowing to: |
| mbed_official | 354:e67efb2aab0e | 200 | (+) Initialize and configure the TIM base. |
| mbed_official | 354:e67efb2aab0e | 201 | (+) De-initialize the TIM base. |
| mbed_official | 354:e67efb2aab0e | 202 | (+) Start the Time Base. |
| mbed_official | 354:e67efb2aab0e | 203 | (+) Stop the Time Base. |
| mbed_official | 354:e67efb2aab0e | 204 | (+) Start the Time Base and enable interrupt. |
| mbed_official | 354:e67efb2aab0e | 205 | (+) Stop the Time Base and disable interrupt. |
| mbed_official | 354:e67efb2aab0e | 206 | (+) Start the Time Base and enable DMA transfer. |
| mbed_official | 354:e67efb2aab0e | 207 | (+) Stop the Time Base and disable DMA transfer. |
| mbed_official | 354:e67efb2aab0e | 208 | |
| mbed_official | 354:e67efb2aab0e | 209 | @endverbatim |
| mbed_official | 354:e67efb2aab0e | 210 | * @{ |
| mbed_official | 354:e67efb2aab0e | 211 | */ |
| mbed_official | 354:e67efb2aab0e | 212 | /** |
| mbed_official | 354:e67efb2aab0e | 213 | * @brief Initializes the TIM Time base Unit according to the specified |
| mbed_official | 354:e67efb2aab0e | 214 | * parameters in the TIM_HandleTypeDef and create the associated handle. |
| mbed_official | 354:e67efb2aab0e | 215 | * @param htim: TIM Base handle |
| mbed_official | 354:e67efb2aab0e | 216 | * @retval HAL status |
| mbed_official | 354:e67efb2aab0e | 217 | */ |
| mbed_official | 354:e67efb2aab0e | 218 | HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) |
| mbed_official | 354:e67efb2aab0e | 219 | { |
| mbed_official | 354:e67efb2aab0e | 220 | /* Check the TIM handle allocation */ |
| mbed_official | 354:e67efb2aab0e | 221 | if(htim == HAL_NULL) |
| mbed_official | 354:e67efb2aab0e | 222 | { |
| mbed_official | 354:e67efb2aab0e | 223 | return HAL_ERROR; |
| mbed_official | 354:e67efb2aab0e | 224 | } |
| mbed_official | 354:e67efb2aab0e | 225 | |
| mbed_official | 354:e67efb2aab0e | 226 | /* Check the parameters */ |
| mbed_official | 354:e67efb2aab0e | 227 | assert_param(IS_TIM_INSTANCE(htim->Instance)); |
| mbed_official | 354:e67efb2aab0e | 228 | assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); |
| mbed_official | 354:e67efb2aab0e | 229 | assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); |
| mbed_official | 354:e67efb2aab0e | 230 | |
| mbed_official | 354:e67efb2aab0e | 231 | if(htim->State == HAL_TIM_STATE_RESET) |
| mbed_official | 354:e67efb2aab0e | 232 | { |
| mbed_official | 354:e67efb2aab0e | 233 | /* Init the low level hardware : GPIO, CLOCK, NVIC */ |
| mbed_official | 354:e67efb2aab0e | 234 | HAL_TIM_Base_MspInit(htim); |
| mbed_official | 354:e67efb2aab0e | 235 | } |
| mbed_official | 354:e67efb2aab0e | 236 | |
| mbed_official | 354:e67efb2aab0e | 237 | /* Set the TIM state */ |
| mbed_official | 354:e67efb2aab0e | 238 | htim->State= HAL_TIM_STATE_BUSY; |
| mbed_official | 354:e67efb2aab0e | 239 | |
| mbed_official | 354:e67efb2aab0e | 240 | /* Set the Time Base configuration */ |
| mbed_official | 354:e67efb2aab0e | 241 | TIM_Base_SetConfig(htim->Instance, &htim->Init); |
| mbed_official | 354:e67efb2aab0e | 242 | |
| mbed_official | 354:e67efb2aab0e | 243 | /* Initialize the TIM state*/ |
| mbed_official | 354:e67efb2aab0e | 244 | htim->State= HAL_TIM_STATE_READY; |
| mbed_official | 354:e67efb2aab0e | 245 | |
| mbed_official | 354:e67efb2aab0e | 246 | return HAL_OK; |
| mbed_official | 354:e67efb2aab0e | 247 | } |
| mbed_official | 354:e67efb2aab0e | 248 | |
| mbed_official | 354:e67efb2aab0e | 249 | /** |
| mbed_official | 354:e67efb2aab0e | 250 | * @brief DeInitializes the TIM Base peripheral |
| mbed_official | 354:e67efb2aab0e | 251 | * @param htim: TIM Base handle |
| mbed_official | 354:e67efb2aab0e | 252 | * @retval HAL status |
| mbed_official | 354:e67efb2aab0e | 253 | */ |
| mbed_official | 354:e67efb2aab0e | 254 | HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim) |
| mbed_official | 354:e67efb2aab0e | 255 | { |
| mbed_official | 354:e67efb2aab0e | 256 | /* Check the parameters */ |
| mbed_official | 354:e67efb2aab0e | 257 | assert_param(IS_TIM_INSTANCE(htim->Instance)); |
| mbed_official | 354:e67efb2aab0e | 258 | |
| mbed_official | 354:e67efb2aab0e | 259 | htim->State = HAL_TIM_STATE_BUSY; |
| mbed_official | 354:e67efb2aab0e | 260 | |
| mbed_official | 354:e67efb2aab0e | 261 | /* Disable the TIM Peripheral Clock */ |
| mbed_official | 354:e67efb2aab0e | 262 | __HAL_TIM_DISABLE(htim); |
| mbed_official | 354:e67efb2aab0e | 263 | |
| mbed_official | 354:e67efb2aab0e | 264 | /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ |
| mbed_official | 354:e67efb2aab0e | 265 | HAL_TIM_Base_MspDeInit(htim); |
| mbed_official | 354:e67efb2aab0e | 266 | |
| mbed_official | 354:e67efb2aab0e | 267 | /* Change TIM state */ |
| mbed_official | 354:e67efb2aab0e | 268 | htim->State = HAL_TIM_STATE_RESET; |
| mbed_official | 354:e67efb2aab0e | 269 | |
| mbed_official | 354:e67efb2aab0e | 270 | /* Release Lock */ |
| mbed_official | 354:e67efb2aab0e | 271 | __HAL_UNLOCK(htim); |
| mbed_official | 354:e67efb2aab0e | 272 | |
| mbed_official | 354:e67efb2aab0e | 273 | return HAL_OK; |
| mbed_official | 354:e67efb2aab0e | 274 | } |
| mbed_official | 354:e67efb2aab0e | 275 | |
| mbed_official | 354:e67efb2aab0e | 276 | /** |
| mbed_official | 354:e67efb2aab0e | 277 | * @brief Initializes the TIM Base MSP. |
| mbed_official | 354:e67efb2aab0e | 278 | * @param htim: TIM handle |
| mbed_official | 354:e67efb2aab0e | 279 | * @retval None |
| mbed_official | 354:e67efb2aab0e | 280 | */ |
| mbed_official | 354:e67efb2aab0e | 281 | __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim) |
| mbed_official | 354:e67efb2aab0e | 282 | { |
| mbed_official | 354:e67efb2aab0e | 283 | /* NOTE : This function Should not be modified, when the callback is needed, |
| mbed_official | 354:e67efb2aab0e | 284 | the HAL_TIM_Base_MspInit could be implemented in the user file |
| mbed_official | 354:e67efb2aab0e | 285 | */ |
| mbed_official | 354:e67efb2aab0e | 286 | } |
| mbed_official | 354:e67efb2aab0e | 287 | |
| mbed_official | 354:e67efb2aab0e | 288 | /** |
| mbed_official | 354:e67efb2aab0e | 289 | * @brief DeInitializes TIM Base MSP. |
| mbed_official | 354:e67efb2aab0e | 290 | * @param htim: TIM handle |
| mbed_official | 354:e67efb2aab0e | 291 | * @retval None |
| mbed_official | 354:e67efb2aab0e | 292 | */ |
| mbed_official | 354:e67efb2aab0e | 293 | __weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim) |
| mbed_official | 354:e67efb2aab0e | 294 | { |
| mbed_official | 354:e67efb2aab0e | 295 | /* NOTE : This function Should not be modified, when the callback is needed, |
| mbed_official | 354:e67efb2aab0e | 296 | the HAL_TIM_Base_MspDeInit could be implemented in the user file |
| mbed_official | 354:e67efb2aab0e | 297 | */ |
| mbed_official | 354:e67efb2aab0e | 298 | } |
| mbed_official | 354:e67efb2aab0e | 299 | |
| mbed_official | 354:e67efb2aab0e | 300 | |
| mbed_official | 354:e67efb2aab0e | 301 | /** |
| mbed_official | 354:e67efb2aab0e | 302 | * @brief Starts the TIM Base generation. |
| mbed_official | 354:e67efb2aab0e | 303 | * @param htim : TIM handle |
| mbed_official | 354:e67efb2aab0e | 304 | * @retval HAL status |
| mbed_official | 354:e67efb2aab0e | 305 | */ |
| mbed_official | 354:e67efb2aab0e | 306 | HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim) |
| mbed_official | 354:e67efb2aab0e | 307 | { |
| mbed_official | 354:e67efb2aab0e | 308 | /* Check the parameters */ |
| mbed_official | 354:e67efb2aab0e | 309 | assert_param(IS_TIM_INSTANCE(htim->Instance)); |
| mbed_official | 354:e67efb2aab0e | 310 | |
| mbed_official | 354:e67efb2aab0e | 311 | /* Set the TIM state */ |
| mbed_official | 354:e67efb2aab0e | 312 | htim->State= HAL_TIM_STATE_BUSY; |
| mbed_official | 354:e67efb2aab0e | 313 | |
| mbed_official | 354:e67efb2aab0e | 314 | /* Enable the Peripheral */ |
| mbed_official | 354:e67efb2aab0e | 315 | __HAL_TIM_ENABLE(htim); |
| mbed_official | 354:e67efb2aab0e | 316 | |
| mbed_official | 354:e67efb2aab0e | 317 | /* Change the TIM state*/ |
| mbed_official | 354:e67efb2aab0e | 318 | htim->State= HAL_TIM_STATE_READY; |
| mbed_official | 354:e67efb2aab0e | 319 | |
| mbed_official | 354:e67efb2aab0e | 320 | /* Return function status */ |
| mbed_official | 354:e67efb2aab0e | 321 | return HAL_OK; |
| mbed_official | 354:e67efb2aab0e | 322 | } |
| mbed_official | 354:e67efb2aab0e | 323 | |
| mbed_official | 354:e67efb2aab0e | 324 | /** |
| mbed_official | 354:e67efb2aab0e | 325 | * @brief Stops the TIM Base generation. |
| mbed_official | 354:e67efb2aab0e | 326 | * @param htim : TIM handle |
| mbed_official | 354:e67efb2aab0e | 327 | * @retval HAL status |
| mbed_official | 354:e67efb2aab0e | 328 | */ |
| mbed_official | 354:e67efb2aab0e | 329 | HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim) |
| mbed_official | 354:e67efb2aab0e | 330 | { |
| mbed_official | 354:e67efb2aab0e | 331 | /* Check the parameters */ |
| mbed_official | 354:e67efb2aab0e | 332 | assert_param(IS_TIM_INSTANCE(htim->Instance)); |
| mbed_official | 354:e67efb2aab0e | 333 | |
| mbed_official | 354:e67efb2aab0e | 334 | /* Set the TIM state */ |
| mbed_official | 354:e67efb2aab0e | 335 | htim->State= HAL_TIM_STATE_BUSY; |
| mbed_official | 354:e67efb2aab0e | 336 | |
| mbed_official | 354:e67efb2aab0e | 337 | /* Disable the Peripheral */ |
| mbed_official | 354:e67efb2aab0e | 338 | __HAL_TIM_DISABLE(htim); |
| mbed_official | 354:e67efb2aab0e | 339 | |
| mbed_official | 354:e67efb2aab0e | 340 | /* Change the TIM state*/ |
| mbed_official | 354:e67efb2aab0e | 341 | htim->State= HAL_TIM_STATE_READY; |
| mbed_official | 354:e67efb2aab0e | 342 | |
| mbed_official | 354:e67efb2aab0e | 343 | /* Return function status */ |
| mbed_official | 354:e67efb2aab0e | 344 | return HAL_OK; |
| mbed_official | 354:e67efb2aab0e | 345 | } |
| mbed_official | 354:e67efb2aab0e | 346 | |
| mbed_official | 354:e67efb2aab0e | 347 | /** |
| mbed_official | 354:e67efb2aab0e | 348 | * @brief Starts the TIM Base generation in interrupt mode. |
| mbed_official | 354:e67efb2aab0e | 349 | * @param htim : TIM handle |
| mbed_official | 354:e67efb2aab0e | 350 | * @retval HAL status |
| mbed_official | 354:e67efb2aab0e | 351 | */ |
| mbed_official | 354:e67efb2aab0e | 352 | HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) |
| mbed_official | 354:e67efb2aab0e | 353 | { |
| mbed_official | 354:e67efb2aab0e | 354 | /* Check the parameters */ |
| mbed_official | 354:e67efb2aab0e | 355 | assert_param(IS_TIM_INSTANCE(htim->Instance)); |
| mbed_official | 354:e67efb2aab0e | 356 | |
| mbed_official | 354:e67efb2aab0e | 357 | /* Enable the TIM Update interrupt */ |
| mbed_official | 354:e67efb2aab0e | 358 | __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); |
| mbed_official | 354:e67efb2aab0e | 359 | |
| mbed_official | 354:e67efb2aab0e | 360 | /* Enable the Peripheral */ |
| mbed_official | 354:e67efb2aab0e | 361 | __HAL_TIM_ENABLE(htim); |
| mbed_official | 354:e67efb2aab0e | 362 | |
| mbed_official | 354:e67efb2aab0e | 363 | /* Return function status */ |
| mbed_official | 354:e67efb2aab0e | 364 | return HAL_OK; |
| mbed_official | 354:e67efb2aab0e | 365 | } |
| mbed_official | 354:e67efb2aab0e | 366 | |
| mbed_official | 354:e67efb2aab0e | 367 | /** |
| mbed_official | 354:e67efb2aab0e | 368 | * @brief Stops the TIM Base generation in interrupt mode. |
| mbed_official | 354:e67efb2aab0e | 369 | * @param htim : TIM handle |
| mbed_official | 354:e67efb2aab0e | 370 | * @retval HAL status |
| mbed_official | 354:e67efb2aab0e | 371 | */ |
| mbed_official | 354:e67efb2aab0e | 372 | HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim) |
| mbed_official | 354:e67efb2aab0e | 373 | { |
| mbed_official | 354:e67efb2aab0e | 374 | /* Check the parameters */ |
| mbed_official | 354:e67efb2aab0e | 375 | assert_param(IS_TIM_INSTANCE(htim->Instance)); |
| mbed_official | 354:e67efb2aab0e | 376 | /* Disable the TIM Update interrupt */ |
| mbed_official | 354:e67efb2aab0e | 377 | __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE); |
| mbed_official | 354:e67efb2aab0e | 378 | |
| mbed_official | 354:e67efb2aab0e | 379 | /* Disable the Peripheral */ |
| mbed_official | 354:e67efb2aab0e | 380 | __HAL_TIM_DISABLE(htim); |
| mbed_official | 354:e67efb2aab0e | 381 | |
| mbed_official | 354:e67efb2aab0e | 382 | /* Return function status */ |
| mbed_official | 354:e67efb2aab0e | 383 | return HAL_OK; |
| mbed_official | 354:e67efb2aab0e | 384 | } |
| mbed_official | 354:e67efb2aab0e | 385 | |
| mbed_official | 354:e67efb2aab0e | 386 | /** |
| mbed_official | 354:e67efb2aab0e | 387 | * @brief Starts the TIM Base generation in DMA mode. |
| mbed_official | 354:e67efb2aab0e | 388 | * @param htim : TIM handle |
| mbed_official | 354:e67efb2aab0e | 389 | * @param pData: The source Buffer address. |
| mbed_official | 354:e67efb2aab0e | 390 | * @param Length: The length of data to be transferred from memory to peripheral. |
| mbed_official | 354:e67efb2aab0e | 391 | * @retval HAL status |
| mbed_official | 354:e67efb2aab0e | 392 | */ |
| mbed_official | 354:e67efb2aab0e | 393 | HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length) |
| mbed_official | 354:e67efb2aab0e | 394 | { |
| mbed_official | 354:e67efb2aab0e | 395 | /* Check the parameters */ |
| mbed_official | 354:e67efb2aab0e | 396 | assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); |
| mbed_official | 354:e67efb2aab0e | 397 | |
| mbed_official | 354:e67efb2aab0e | 398 | if((htim->State == HAL_TIM_STATE_BUSY)) |
| mbed_official | 354:e67efb2aab0e | 399 | { |
| mbed_official | 354:e67efb2aab0e | 400 | return HAL_BUSY; |
| mbed_official | 354:e67efb2aab0e | 401 | } |
| mbed_official | 354:e67efb2aab0e | 402 | else if((htim->State == HAL_TIM_STATE_READY)) |
| mbed_official | 354:e67efb2aab0e | 403 | { |
| mbed_official | 354:e67efb2aab0e | 404 | if((pData == 0 ) && (Length > 0)) |
| mbed_official | 354:e67efb2aab0e | 405 | { |
| mbed_official | 354:e67efb2aab0e | 406 | return HAL_ERROR; |
| mbed_official | 354:e67efb2aab0e | 407 | } |
| mbed_official | 354:e67efb2aab0e | 408 | else |
| mbed_official | 354:e67efb2aab0e | 409 | { |
| mbed_official | 354:e67efb2aab0e | 410 | htim->State = HAL_TIM_STATE_BUSY; |
| mbed_official | 354:e67efb2aab0e | 411 | } |
| mbed_official | 354:e67efb2aab0e | 412 | } |
| mbed_official | 354:e67efb2aab0e | 413 | else |
| mbed_official | 354:e67efb2aab0e | 414 | { |
| mbed_official | 354:e67efb2aab0e | 415 | return HAL_ERROR; |
| mbed_official | 354:e67efb2aab0e | 416 | } |
| mbed_official | 354:e67efb2aab0e | 417 | |
| mbed_official | 354:e67efb2aab0e | 418 | /* Set the DMA Period elapsed callback */ |
| mbed_official | 354:e67efb2aab0e | 419 | htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; |
| mbed_official | 354:e67efb2aab0e | 420 | |
| mbed_official | 354:e67efb2aab0e | 421 | /* Set the DMA error callback */ |
| mbed_official | 354:e67efb2aab0e | 422 | htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; |
| mbed_official | 354:e67efb2aab0e | 423 | |
| mbed_official | 354:e67efb2aab0e | 424 | /* Enable the DMA channel */ |
| mbed_official | 354:e67efb2aab0e | 425 | HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length); |
| mbed_official | 354:e67efb2aab0e | 426 | |
| mbed_official | 354:e67efb2aab0e | 427 | /* Enable the TIM Update DMA request */ |
| mbed_official | 354:e67efb2aab0e | 428 | __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE); |
| mbed_official | 354:e67efb2aab0e | 429 | |
| mbed_official | 354:e67efb2aab0e | 430 | /* Enable the Peripheral */ |
| mbed_official | 354:e67efb2aab0e | 431 | __HAL_TIM_ENABLE(htim); |
| mbed_official | 354:e67efb2aab0e | 432 | |
| mbed_official | 354:e67efb2aab0e | 433 | /* Return function status */ |
| mbed_official | 354:e67efb2aab0e | 434 | return HAL_OK; |
| mbed_official | 354:e67efb2aab0e | 435 | } |
| mbed_official | 354:e67efb2aab0e | 436 | |
| mbed_official | 354:e67efb2aab0e | 437 | /** |
| mbed_official | 354:e67efb2aab0e | 438 | * @brief Stops the TIM Base generation in DMA mode. |
| mbed_official | 354:e67efb2aab0e | 439 | * @param htim : TIM handle |
| mbed_official | 354:e67efb2aab0e | 440 | * @retval HAL status |
| mbed_official | 354:e67efb2aab0e | 441 | */ |
| mbed_official | 354:e67efb2aab0e | 442 | HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim) |
| mbed_official | 354:e67efb2aab0e | 443 | { |
| mbed_official | 354:e67efb2aab0e | 444 | /* Check the parameters */ |
| mbed_official | 354:e67efb2aab0e | 445 | assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); |
| mbed_official | 354:e67efb2aab0e | 446 | |
| mbed_official | 354:e67efb2aab0e | 447 | /* Disable the TIM Update DMA request */ |
| mbed_official | 354:e67efb2aab0e | 448 | __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE); |
| mbed_official | 354:e67efb2aab0e | 449 | |
| mbed_official | 354:e67efb2aab0e | 450 | /* Disable the Peripheral */ |
| mbed_official | 354:e67efb2aab0e | 451 | __HAL_TIM_DISABLE(htim); |
| mbed_official | 354:e67efb2aab0e | 452 | |
| mbed_official | 354:e67efb2aab0e | 453 | /* Change the htim state */ |
| mbed_official | 354:e67efb2aab0e | 454 | htim->State = HAL_TIM_STATE_READY; |
| mbed_official | 354:e67efb2aab0e | 455 | |
| mbed_official | 354:e67efb2aab0e | 456 | /* Return function status */ |
| mbed_official | 354:e67efb2aab0e | 457 | return HAL_OK; |
| mbed_official | 354:e67efb2aab0e | 458 | } |
| mbed_official | 354:e67efb2aab0e | 459 | |
| mbed_official | 354:e67efb2aab0e | 460 | /** |
| mbed_official | 354:e67efb2aab0e | 461 | * @} |
| mbed_official | 354:e67efb2aab0e | 462 | */ |
| mbed_official | 354:e67efb2aab0e | 463 | |
| mbed_official | 354:e67efb2aab0e | 464 | /** @defgroup TIM_Exported_Functions_Group2 Time Output Compare functions |
| mbed_official | 354:e67efb2aab0e | 465 | * @brief Time Output Compare functions |
| mbed_official | 354:e67efb2aab0e | 466 | * |
| mbed_official | 354:e67efb2aab0e | 467 | @verbatim |
| mbed_official | 354:e67efb2aab0e | 468 | ============================================================================== |
| mbed_official | 354:e67efb2aab0e | 469 | ##### Time Output Compare functions ##### |
| mbed_official | 354:e67efb2aab0e | 470 | ============================================================================== |
| mbed_official | 354:e67efb2aab0e | 471 | [..] |
| mbed_official | 354:e67efb2aab0e | 472 | This section provides functions allowing to: |
| mbed_official | 354:e67efb2aab0e | 473 | (+) Initialize and configure the TIM Output Compare. |
| mbed_official | 354:e67efb2aab0e | 474 | (+) De-initialize the TIM Output Compare. |
| mbed_official | 354:e67efb2aab0e | 475 | (+) Start the Time Output Compare. |
| mbed_official | 354:e67efb2aab0e | 476 | (+) Stop the Time Output Compare. |
| mbed_official | 354:e67efb2aab0e | 477 | (+) Start the Time Output Compare and enable interrupt. |
| mbed_official | 354:e67efb2aab0e | 478 | (+) Stop the Time Output Compare and disable interrupt. |
| mbed_official | 354:e67efb2aab0e | 479 | (+) Start the Time Output Compare and enable DMA transfer. |
| mbed_official | 354:e67efb2aab0e | 480 | (+) Stop the Time Output Compare and disable DMA transfer. |
| mbed_official | 354:e67efb2aab0e | 481 | |
| mbed_official | 354:e67efb2aab0e | 482 | @endverbatim |
| mbed_official | 354:e67efb2aab0e | 483 | * @{ |
| mbed_official | 354:e67efb2aab0e | 484 | */ |
| mbed_official | 354:e67efb2aab0e | 485 | /** |
| mbed_official | 354:e67efb2aab0e | 486 | * @brief Initializes the TIM Output Compare according to the specified |
| mbed_official | 354:e67efb2aab0e | 487 | * parameters in the TIM_HandleTypeDef and create the associated handle. |
| mbed_official | 354:e67efb2aab0e | 488 | * @param htim: TIM Output Compare handle |
| mbed_official | 354:e67efb2aab0e | 489 | * @retval HAL status |
| mbed_official | 354:e67efb2aab0e | 490 | */ |
| mbed_official | 354:e67efb2aab0e | 491 | HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim) |
| mbed_official | 354:e67efb2aab0e | 492 | { |
| mbed_official | 354:e67efb2aab0e | 493 | /* Check the TIM handle allocation */ |
| mbed_official | 354:e67efb2aab0e | 494 | if(htim == HAL_NULL) |
| mbed_official | 354:e67efb2aab0e | 495 | { |
| mbed_official | 354:e67efb2aab0e | 496 | return HAL_ERROR; |
| mbed_official | 354:e67efb2aab0e | 497 | } |
| mbed_official | 354:e67efb2aab0e | 498 | |
| mbed_official | 354:e67efb2aab0e | 499 | /* Check the parameters */ |
| mbed_official | 354:e67efb2aab0e | 500 | assert_param(IS_TIM_INSTANCE(htim->Instance)); |
| mbed_official | 354:e67efb2aab0e | 501 | assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); |
| mbed_official | 354:e67efb2aab0e | 502 | assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); |
| mbed_official | 354:e67efb2aab0e | 503 | |
| mbed_official | 354:e67efb2aab0e | 504 | if(htim->State == HAL_TIM_STATE_RESET) |
| mbed_official | 354:e67efb2aab0e | 505 | { |
| mbed_official | 354:e67efb2aab0e | 506 | /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ |
| mbed_official | 354:e67efb2aab0e | 507 | HAL_TIM_OC_MspInit(htim); |
| mbed_official | 354:e67efb2aab0e | 508 | } |
| mbed_official | 354:e67efb2aab0e | 509 | |
| mbed_official | 354:e67efb2aab0e | 510 | /* Set the TIM state */ |
| mbed_official | 354:e67efb2aab0e | 511 | htim->State= HAL_TIM_STATE_BUSY; |
| mbed_official | 354:e67efb2aab0e | 512 | |
| mbed_official | 354:e67efb2aab0e | 513 | /* Init the base time for the Output Compare */ |
| mbed_official | 354:e67efb2aab0e | 514 | TIM_Base_SetConfig(htim->Instance, &htim->Init); |
| mbed_official | 354:e67efb2aab0e | 515 | |
| mbed_official | 354:e67efb2aab0e | 516 | /* Initialize the TIM state*/ |
| mbed_official | 354:e67efb2aab0e | 517 | htim->State= HAL_TIM_STATE_READY; |
| mbed_official | 354:e67efb2aab0e | 518 | |
| mbed_official | 354:e67efb2aab0e | 519 | return HAL_OK; |
| mbed_official | 354:e67efb2aab0e | 520 | } |
| mbed_official | 354:e67efb2aab0e | 521 | |
| mbed_official | 354:e67efb2aab0e | 522 | /** |
| mbed_official | 354:e67efb2aab0e | 523 | * @brief DeInitializes the TIM peripheral |
| mbed_official | 354:e67efb2aab0e | 524 | * @param htim: TIM Output Compare handle |
| mbed_official | 354:e67efb2aab0e | 525 | * @retval HAL status |
| mbed_official | 354:e67efb2aab0e | 526 | */ |
| mbed_official | 354:e67efb2aab0e | 527 | HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim) |
| mbed_official | 354:e67efb2aab0e | 528 | { |
| mbed_official | 354:e67efb2aab0e | 529 | /* Check the parameters */ |
| mbed_official | 354:e67efb2aab0e | 530 | assert_param(IS_TIM_INSTANCE(htim->Instance)); |
| mbed_official | 354:e67efb2aab0e | 531 | |
| mbed_official | 354:e67efb2aab0e | 532 | htim->State = HAL_TIM_STATE_BUSY; |
| mbed_official | 354:e67efb2aab0e | 533 | |
| mbed_official | 354:e67efb2aab0e | 534 | /* Disable the TIM Peripheral Clock */ |
| mbed_official | 354:e67efb2aab0e | 535 | __HAL_TIM_DISABLE(htim); |
| mbed_official | 354:e67efb2aab0e | 536 | |
| mbed_official | 354:e67efb2aab0e | 537 | /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ |
| mbed_official | 354:e67efb2aab0e | 538 | HAL_TIM_OC_MspDeInit(htim); |
| mbed_official | 354:e67efb2aab0e | 539 | |
| mbed_official | 354:e67efb2aab0e | 540 | /* Change TIM state */ |
| mbed_official | 354:e67efb2aab0e | 541 | htim->State = HAL_TIM_STATE_RESET; |
| mbed_official | 354:e67efb2aab0e | 542 | |
| mbed_official | 354:e67efb2aab0e | 543 | /* Release Lock */ |
| mbed_official | 354:e67efb2aab0e | 544 | __HAL_UNLOCK(htim); |
| mbed_official | 354:e67efb2aab0e | 545 | |
| mbed_official | 354:e67efb2aab0e | 546 | return HAL_OK; |
| mbed_official | 354:e67efb2aab0e | 547 | } |
| mbed_official | 354:e67efb2aab0e | 548 | |
| mbed_official | 354:e67efb2aab0e | 549 | /** |
| mbed_official | 354:e67efb2aab0e | 550 | * @brief Initializes the TIM Output Compare MSP. |
| mbed_official | 354:e67efb2aab0e | 551 | * @param htim: TIM handle |
| mbed_official | 354:e67efb2aab0e | 552 | * @retval None |
| mbed_official | 354:e67efb2aab0e | 553 | */ |
| mbed_official | 354:e67efb2aab0e | 554 | __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim) |
| mbed_official | 354:e67efb2aab0e | 555 | { |
| mbed_official | 354:e67efb2aab0e | 556 | /* NOTE : This function Should not be modified, when the callback is needed, |
| mbed_official | 354:e67efb2aab0e | 557 | the HAL_TIM_OC_MspInit could be implemented in the user file |
| mbed_official | 354:e67efb2aab0e | 558 | */ |
| mbed_official | 354:e67efb2aab0e | 559 | } |
| mbed_official | 354:e67efb2aab0e | 560 | |
| mbed_official | 354:e67efb2aab0e | 561 | /** |
| mbed_official | 354:e67efb2aab0e | 562 | * @brief DeInitializes TIM Output Compare MSP. |
| mbed_official | 354:e67efb2aab0e | 563 | * @param htim: TIM handle |
| mbed_official | 354:e67efb2aab0e | 564 | * @retval None |
| mbed_official | 354:e67efb2aab0e | 565 | */ |
| mbed_official | 354:e67efb2aab0e | 566 | __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim) |
| mbed_official | 354:e67efb2aab0e | 567 | { |
| mbed_official | 354:e67efb2aab0e | 568 | /* NOTE : This function Should not be modified, when the callback is needed, |
| mbed_official | 354:e67efb2aab0e | 569 | the HAL_TIM_OC_MspDeInit could be implemented in the user file |
| mbed_official | 354:e67efb2aab0e | 570 | */ |
| mbed_official | 354:e67efb2aab0e | 571 | } |
| mbed_official | 354:e67efb2aab0e | 572 | |
| mbed_official | 354:e67efb2aab0e | 573 | /** |
| mbed_official | 354:e67efb2aab0e | 574 | * @brief Starts the TIM Output Compare signal generation. |
| mbed_official | 354:e67efb2aab0e | 575 | * @param htim : TIM Output Compare handle |
| mbed_official | 354:e67efb2aab0e | 576 | * @param Channel : TIM Channel to be enabled |
| mbed_official | 354:e67efb2aab0e | 577 | * This parameter can be one of the following values: |
| mbed_official | 354:e67efb2aab0e | 578 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| mbed_official | 354:e67efb2aab0e | 579 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| mbed_official | 354:e67efb2aab0e | 580 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
| mbed_official | 354:e67efb2aab0e | 581 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
| mbed_official | 354:e67efb2aab0e | 582 | * @retval HAL status |
| mbed_official | 354:e67efb2aab0e | 583 | */ |
| mbed_official | 354:e67efb2aab0e | 584 | HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) |
| mbed_official | 354:e67efb2aab0e | 585 | { |
| mbed_official | 354:e67efb2aab0e | 586 | /* Check the parameters */ |
| mbed_official | 354:e67efb2aab0e | 587 | assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); |
| mbed_official | 354:e67efb2aab0e | 588 | |
| mbed_official | 354:e67efb2aab0e | 589 | /* Enable the Output compare channel */ |
| mbed_official | 354:e67efb2aab0e | 590 | TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); |
| mbed_official | 354:e67efb2aab0e | 591 | |
| mbed_official | 354:e67efb2aab0e | 592 | /* Enable the Peripheral */ |
| mbed_official | 354:e67efb2aab0e | 593 | __HAL_TIM_ENABLE(htim); |
| mbed_official | 354:e67efb2aab0e | 594 | |
| mbed_official | 354:e67efb2aab0e | 595 | /* Return function status */ |
| mbed_official | 354:e67efb2aab0e | 596 | return HAL_OK; |
| mbed_official | 354:e67efb2aab0e | 597 | } |
| mbed_official | 354:e67efb2aab0e | 598 | |
| mbed_official | 354:e67efb2aab0e | 599 | /** |
| mbed_official | 354:e67efb2aab0e | 600 | * @brief Stops the TIM Output Compare signal generation. |
| mbed_official | 354:e67efb2aab0e | 601 | * @param htim : TIM handle |
| mbed_official | 354:e67efb2aab0e | 602 | * @param Channel : TIM Channel to be disabled |
| mbed_official | 354:e67efb2aab0e | 603 | * This parameter can be one of the following values: |
| mbed_official | 354:e67efb2aab0e | 604 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| mbed_official | 354:e67efb2aab0e | 605 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| mbed_official | 354:e67efb2aab0e | 606 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
| mbed_official | 354:e67efb2aab0e | 607 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
| mbed_official | 354:e67efb2aab0e | 608 | * @retval HAL status |
| mbed_official | 354:e67efb2aab0e | 609 | */ |
| mbed_official | 354:e67efb2aab0e | 610 | HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) |
| mbed_official | 354:e67efb2aab0e | 611 | { |
| mbed_official | 354:e67efb2aab0e | 612 | /* Check the parameters */ |
| mbed_official | 354:e67efb2aab0e | 613 | assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); |
| mbed_official | 354:e67efb2aab0e | 614 | |
| mbed_official | 354:e67efb2aab0e | 615 | /* Disable the Output compare channel */ |
| mbed_official | 354:e67efb2aab0e | 616 | TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); |
| mbed_official | 354:e67efb2aab0e | 617 | |
| mbed_official | 354:e67efb2aab0e | 618 | /* Disable the Peripheral */ |
| mbed_official | 354:e67efb2aab0e | 619 | __HAL_TIM_DISABLE(htim); |
| mbed_official | 354:e67efb2aab0e | 620 | |
| mbed_official | 354:e67efb2aab0e | 621 | /* Return function status */ |
| mbed_official | 354:e67efb2aab0e | 622 | return HAL_OK; |
| mbed_official | 354:e67efb2aab0e | 623 | } |
| mbed_official | 354:e67efb2aab0e | 624 | |
| mbed_official | 354:e67efb2aab0e | 625 | /** |
| mbed_official | 354:e67efb2aab0e | 626 | * @brief Starts the TIM Output Compare signal generation in interrupt mode. |
| mbed_official | 354:e67efb2aab0e | 627 | * @param htim : TIM OC handle |
| mbed_official | 354:e67efb2aab0e | 628 | * @param Channel : TIM Channel to be enabled |
| mbed_official | 354:e67efb2aab0e | 629 | * This parameter can be one of the following values: |
| mbed_official | 354:e67efb2aab0e | 630 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| mbed_official | 354:e67efb2aab0e | 631 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| mbed_official | 354:e67efb2aab0e | 632 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
| mbed_official | 354:e67efb2aab0e | 633 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
| mbed_official | 354:e67efb2aab0e | 634 | * @retval HAL status |
| mbed_official | 354:e67efb2aab0e | 635 | */ |
| mbed_official | 354:e67efb2aab0e | 636 | HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) |
| mbed_official | 354:e67efb2aab0e | 637 | { |
| mbed_official | 354:e67efb2aab0e | 638 | /* Check the parameters */ |
| mbed_official | 354:e67efb2aab0e | 639 | assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); |
| mbed_official | 354:e67efb2aab0e | 640 | |
| mbed_official | 354:e67efb2aab0e | 641 | switch (Channel) |
| mbed_official | 354:e67efb2aab0e | 642 | { |
| mbed_official | 354:e67efb2aab0e | 643 | case TIM_CHANNEL_1: |
| mbed_official | 354:e67efb2aab0e | 644 | { |
| mbed_official | 354:e67efb2aab0e | 645 | /* Enable the TIM Capture/Compare 1 interrupt */ |
| mbed_official | 354:e67efb2aab0e | 646 | __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); |
| mbed_official | 354:e67efb2aab0e | 647 | } |
| mbed_official | 354:e67efb2aab0e | 648 | break; |
| mbed_official | 354:e67efb2aab0e | 649 | |
| mbed_official | 354:e67efb2aab0e | 650 | case TIM_CHANNEL_2: |
| mbed_official | 354:e67efb2aab0e | 651 | { |
| mbed_official | 354:e67efb2aab0e | 652 | /* Enable the TIM Capture/Compare 2 interrupt */ |
| mbed_official | 354:e67efb2aab0e | 653 | __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); |
| mbed_official | 354:e67efb2aab0e | 654 | } |
| mbed_official | 354:e67efb2aab0e | 655 | break; |
| mbed_official | 354:e67efb2aab0e | 656 | |
| mbed_official | 354:e67efb2aab0e | 657 | case TIM_CHANNEL_3: |
| mbed_official | 354:e67efb2aab0e | 658 | { |
| mbed_official | 354:e67efb2aab0e | 659 | /* Enable the TIM Capture/Compare 3 interrupt */ |
| mbed_official | 354:e67efb2aab0e | 660 | __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); |
| mbed_official | 354:e67efb2aab0e | 661 | } |
| mbed_official | 354:e67efb2aab0e | 662 | break; |
| mbed_official | 354:e67efb2aab0e | 663 | |
| mbed_official | 354:e67efb2aab0e | 664 | case TIM_CHANNEL_4: |
| mbed_official | 354:e67efb2aab0e | 665 | { |
| mbed_official | 354:e67efb2aab0e | 666 | /* Enable the TIM Capture/Compare 4 interrupt */ |
| mbed_official | 354:e67efb2aab0e | 667 | __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); |
| mbed_official | 354:e67efb2aab0e | 668 | } |
| mbed_official | 354:e67efb2aab0e | 669 | break; |
| mbed_official | 354:e67efb2aab0e | 670 | |
| mbed_official | 354:e67efb2aab0e | 671 | default: |
| mbed_official | 354:e67efb2aab0e | 672 | break; |
| mbed_official | 354:e67efb2aab0e | 673 | } |
| mbed_official | 354:e67efb2aab0e | 674 | |
| mbed_official | 354:e67efb2aab0e | 675 | /* Enable the Output compare channel */ |
| mbed_official | 354:e67efb2aab0e | 676 | TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); |
| mbed_official | 354:e67efb2aab0e | 677 | |
| mbed_official | 354:e67efb2aab0e | 678 | /* Enable the Peripheral */ |
| mbed_official | 354:e67efb2aab0e | 679 | __HAL_TIM_ENABLE(htim); |
| mbed_official | 354:e67efb2aab0e | 680 | |
| mbed_official | 354:e67efb2aab0e | 681 | /* Return function status */ |
| mbed_official | 354:e67efb2aab0e | 682 | return HAL_OK; |
| mbed_official | 354:e67efb2aab0e | 683 | } |
| mbed_official | 354:e67efb2aab0e | 684 | |
| mbed_official | 354:e67efb2aab0e | 685 | /** |
| mbed_official | 354:e67efb2aab0e | 686 | * @brief Stops the TIM Output Compare signal generation in interrupt mode. |
| mbed_official | 354:e67efb2aab0e | 687 | * @param htim : TIM Output Compare handle |
| mbed_official | 354:e67efb2aab0e | 688 | * @param Channel : TIM Channel to be disabled |
| mbed_official | 354:e67efb2aab0e | 689 | * This parameter can be one of the following values: |
| mbed_official | 354:e67efb2aab0e | 690 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| mbed_official | 354:e67efb2aab0e | 691 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| mbed_official | 354:e67efb2aab0e | 692 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
| mbed_official | 354:e67efb2aab0e | 693 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
| mbed_official | 354:e67efb2aab0e | 694 | * @retval HAL status |
| mbed_official | 354:e67efb2aab0e | 695 | */ |
| mbed_official | 354:e67efb2aab0e | 696 | HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) |
| mbed_official | 354:e67efb2aab0e | 697 | { |
| mbed_official | 354:e67efb2aab0e | 698 | /* Check the parameters */ |
| mbed_official | 354:e67efb2aab0e | 699 | assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); |
| mbed_official | 354:e67efb2aab0e | 700 | |
| mbed_official | 354:e67efb2aab0e | 701 | switch (Channel) |
| mbed_official | 354:e67efb2aab0e | 702 | { |
| mbed_official | 354:e67efb2aab0e | 703 | case TIM_CHANNEL_1: |
| mbed_official | 354:e67efb2aab0e | 704 | { |
| mbed_official | 354:e67efb2aab0e | 705 | /* Disable the TIM Capture/Compare 1 interrupt */ |
| mbed_official | 354:e67efb2aab0e | 706 | __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); |
| mbed_official | 354:e67efb2aab0e | 707 | } |
| mbed_official | 354:e67efb2aab0e | 708 | break; |
| mbed_official | 354:e67efb2aab0e | 709 | |
| mbed_official | 354:e67efb2aab0e | 710 | case TIM_CHANNEL_2: |
| mbed_official | 354:e67efb2aab0e | 711 | { |
| mbed_official | 354:e67efb2aab0e | 712 | /* Disable the TIM Capture/Compare 2 interrupt */ |
| mbed_official | 354:e67efb2aab0e | 713 | __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); |
| mbed_official | 354:e67efb2aab0e | 714 | } |
| mbed_official | 354:e67efb2aab0e | 715 | break; |
| mbed_official | 354:e67efb2aab0e | 716 | |
| mbed_official | 354:e67efb2aab0e | 717 | case TIM_CHANNEL_3: |
| mbed_official | 354:e67efb2aab0e | 718 | { |
| mbed_official | 354:e67efb2aab0e | 719 | /* Disable the TIM Capture/Compare 3 interrupt */ |
| mbed_official | 354:e67efb2aab0e | 720 | __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); |
| mbed_official | 354:e67efb2aab0e | 721 | } |
| mbed_official | 354:e67efb2aab0e | 722 | break; |
| mbed_official | 354:e67efb2aab0e | 723 | |
| mbed_official | 354:e67efb2aab0e | 724 | case TIM_CHANNEL_4: |
| mbed_official | 354:e67efb2aab0e | 725 | { |
| mbed_official | 354:e67efb2aab0e | 726 | /* Disable the TIM Capture/Compare 4 interrupt */ |
| mbed_official | 354:e67efb2aab0e | 727 | __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); |
| mbed_official | 354:e67efb2aab0e | 728 | } |
| mbed_official | 354:e67efb2aab0e | 729 | break; |
| mbed_official | 354:e67efb2aab0e | 730 | |
| mbed_official | 354:e67efb2aab0e | 731 | default: |
| mbed_official | 354:e67efb2aab0e | 732 | break; |
| mbed_official | 354:e67efb2aab0e | 733 | } |
| mbed_official | 354:e67efb2aab0e | 734 | |
| mbed_official | 354:e67efb2aab0e | 735 | /* Disable the Output compare channel */ |
| mbed_official | 354:e67efb2aab0e | 736 | TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); |
| mbed_official | 354:e67efb2aab0e | 737 | |
| mbed_official | 354:e67efb2aab0e | 738 | /* Disable the Peripheral */ |
| mbed_official | 354:e67efb2aab0e | 739 | __HAL_TIM_DISABLE(htim); |
| mbed_official | 354:e67efb2aab0e | 740 | |
| mbed_official | 354:e67efb2aab0e | 741 | /* Return function status */ |
| mbed_official | 354:e67efb2aab0e | 742 | return HAL_OK; |
| mbed_official | 354:e67efb2aab0e | 743 | } |
| mbed_official | 354:e67efb2aab0e | 744 | |
| mbed_official | 354:e67efb2aab0e | 745 | /** |
| mbed_official | 354:e67efb2aab0e | 746 | * @brief Starts the TIM Output Compare signal generation in DMA mode. |
| mbed_official | 354:e67efb2aab0e | 747 | * @param htim : TIM Output Compare handle |
| mbed_official | 354:e67efb2aab0e | 748 | * @param Channel : TIM Channel to be enabled |
| mbed_official | 354:e67efb2aab0e | 749 | * This parameter can be one of the following values: |
| mbed_official | 354:e67efb2aab0e | 750 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| mbed_official | 354:e67efb2aab0e | 751 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| mbed_official | 354:e67efb2aab0e | 752 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
| mbed_official | 354:e67efb2aab0e | 753 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
| mbed_official | 354:e67efb2aab0e | 754 | * @param pData: The source Buffer address. |
| mbed_official | 354:e67efb2aab0e | 755 | * @param Length: The length of data to be transferred from memory to TIM peripheral |
| mbed_official | 354:e67efb2aab0e | 756 | * @retval HAL status |
| mbed_official | 354:e67efb2aab0e | 757 | */ |
| mbed_official | 354:e67efb2aab0e | 758 | HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) |
| mbed_official | 354:e67efb2aab0e | 759 | { |
| mbed_official | 354:e67efb2aab0e | 760 | /* Check the parameters */ |
| mbed_official | 354:e67efb2aab0e | 761 | assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); |
| mbed_official | 354:e67efb2aab0e | 762 | |
| mbed_official | 354:e67efb2aab0e | 763 | if((htim->State == HAL_TIM_STATE_BUSY)) |
| mbed_official | 354:e67efb2aab0e | 764 | { |
| mbed_official | 354:e67efb2aab0e | 765 | return HAL_BUSY; |
| mbed_official | 354:e67efb2aab0e | 766 | } |
| mbed_official | 354:e67efb2aab0e | 767 | else if((htim->State == HAL_TIM_STATE_READY)) |
| mbed_official | 354:e67efb2aab0e | 768 | { |
| mbed_official | 354:e67efb2aab0e | 769 | if(((uint32_t)pData == 0 ) && (Length > 0)) |
| mbed_official | 354:e67efb2aab0e | 770 | { |
| mbed_official | 354:e67efb2aab0e | 771 | return HAL_ERROR; |
| mbed_official | 354:e67efb2aab0e | 772 | } |
| mbed_official | 354:e67efb2aab0e | 773 | else |
| mbed_official | 354:e67efb2aab0e | 774 | { |
| mbed_official | 354:e67efb2aab0e | 775 | htim->State = HAL_TIM_STATE_BUSY; |
| mbed_official | 354:e67efb2aab0e | 776 | } |
| mbed_official | 354:e67efb2aab0e | 777 | } |
| mbed_official | 354:e67efb2aab0e | 778 | else |
| mbed_official | 354:e67efb2aab0e | 779 | { |
| mbed_official | 354:e67efb2aab0e | 780 | return HAL_ERROR; |
| mbed_official | 354:e67efb2aab0e | 781 | } |
| mbed_official | 354:e67efb2aab0e | 782 | |
| mbed_official | 354:e67efb2aab0e | 783 | switch (Channel) |
| mbed_official | 354:e67efb2aab0e | 784 | { |
| mbed_official | 354:e67efb2aab0e | 785 | case TIM_CHANNEL_1: |
| mbed_official | 354:e67efb2aab0e | 786 | { |
| mbed_official | 354:e67efb2aab0e | 787 | /* Set the DMA Period elapsed callback */ |
| mbed_official | 354:e67efb2aab0e | 788 | htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; |
| mbed_official | 354:e67efb2aab0e | 789 | |
| mbed_official | 354:e67efb2aab0e | 790 | /* Set the DMA error callback */ |
| mbed_official | 354:e67efb2aab0e | 791 | htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; |
| mbed_official | 354:e67efb2aab0e | 792 | |
| mbed_official | 354:e67efb2aab0e | 793 | /* Enable the DMA channel */ |
| mbed_official | 354:e67efb2aab0e | 794 | HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length); |
| mbed_official | 354:e67efb2aab0e | 795 | |
| mbed_official | 354:e67efb2aab0e | 796 | /* Enable the TIM Capture/Compare 1 DMA request */ |
| mbed_official | 354:e67efb2aab0e | 797 | __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); |
| mbed_official | 354:e67efb2aab0e | 798 | } |
| mbed_official | 354:e67efb2aab0e | 799 | break; |
| mbed_official | 354:e67efb2aab0e | 800 | |
| mbed_official | 354:e67efb2aab0e | 801 | case TIM_CHANNEL_2: |
| mbed_official | 354:e67efb2aab0e | 802 | { |
| mbed_official | 354:e67efb2aab0e | 803 | /* Set the DMA Period elapsed callback */ |
| mbed_official | 354:e67efb2aab0e | 804 | htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; |
| mbed_official | 354:e67efb2aab0e | 805 | |
| mbed_official | 354:e67efb2aab0e | 806 | /* Set the DMA error callback */ |
| mbed_official | 354:e67efb2aab0e | 807 | htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; |
| mbed_official | 354:e67efb2aab0e | 808 | |
| mbed_official | 354:e67efb2aab0e | 809 | /* Enable the DMA channel */ |
| mbed_official | 354:e67efb2aab0e | 810 | HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length); |
| mbed_official | 354:e67efb2aab0e | 811 | |
| mbed_official | 354:e67efb2aab0e | 812 | /* Enable the TIM Capture/Compare 2 DMA request */ |
| mbed_official | 354:e67efb2aab0e | 813 | __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); |
| mbed_official | 354:e67efb2aab0e | 814 | } |
| mbed_official | 354:e67efb2aab0e | 815 | break; |
| mbed_official | 354:e67efb2aab0e | 816 | |
| mbed_official | 354:e67efb2aab0e | 817 | case TIM_CHANNEL_3: |
| mbed_official | 354:e67efb2aab0e | 818 | { |
| mbed_official | 354:e67efb2aab0e | 819 | /* Set the DMA Period elapsed callback */ |
| mbed_official | 354:e67efb2aab0e | 820 | htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; |
| mbed_official | 354:e67efb2aab0e | 821 | |
| mbed_official | 354:e67efb2aab0e | 822 | /* Set the DMA error callback */ |
| mbed_official | 354:e67efb2aab0e | 823 | htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; |
| mbed_official | 354:e67efb2aab0e | 824 | |
| mbed_official | 354:e67efb2aab0e | 825 | /* Enable the DMA channel */ |
| mbed_official | 354:e67efb2aab0e | 826 | HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length); |
| mbed_official | 354:e67efb2aab0e | 827 | |
| mbed_official | 354:e67efb2aab0e | 828 | /* Enable the TIM Capture/Compare 3 DMA request */ |
| mbed_official | 354:e67efb2aab0e | 829 | __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); |
| mbed_official | 354:e67efb2aab0e | 830 | } |
| mbed_official | 354:e67efb2aab0e | 831 | break; |
| mbed_official | 354:e67efb2aab0e | 832 | |
| mbed_official | 354:e67efb2aab0e | 833 | case TIM_CHANNEL_4: |
| mbed_official | 354:e67efb2aab0e | 834 | { |
| mbed_official | 354:e67efb2aab0e | 835 | /* Set the DMA Period elapsed callback */ |
| mbed_official | 354:e67efb2aab0e | 836 | htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; |
| mbed_official | 354:e67efb2aab0e | 837 | |
| mbed_official | 354:e67efb2aab0e | 838 | /* Set the DMA error callback */ |
| mbed_official | 354:e67efb2aab0e | 839 | htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; |
| mbed_official | 354:e67efb2aab0e | 840 | |
| mbed_official | 354:e67efb2aab0e | 841 | /* Enable the DMA channel */ |
| mbed_official | 354:e67efb2aab0e | 842 | HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length); |
| mbed_official | 354:e67efb2aab0e | 843 | |
| mbed_official | 354:e67efb2aab0e | 844 | /* Enable the TIM Capture/Compare 4 DMA request */ |
| mbed_official | 354:e67efb2aab0e | 845 | __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); |
| mbed_official | 354:e67efb2aab0e | 846 | } |
| mbed_official | 354:e67efb2aab0e | 847 | break; |
| mbed_official | 354:e67efb2aab0e | 848 | |
| mbed_official | 354:e67efb2aab0e | 849 | default: |
| mbed_official | 354:e67efb2aab0e | 850 | break; |
| mbed_official | 354:e67efb2aab0e | 851 | } |
| mbed_official | 354:e67efb2aab0e | 852 | |
| mbed_official | 354:e67efb2aab0e | 853 | /* Enable the Output compare channel */ |
| mbed_official | 354:e67efb2aab0e | 854 | TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); |
| mbed_official | 354:e67efb2aab0e | 855 | |
| mbed_official | 354:e67efb2aab0e | 856 | /* Enable the Peripheral */ |
| mbed_official | 354:e67efb2aab0e | 857 | __HAL_TIM_ENABLE(htim); |
| mbed_official | 354:e67efb2aab0e | 858 | |
| mbed_official | 354:e67efb2aab0e | 859 | /* Return function status */ |
| mbed_official | 354:e67efb2aab0e | 860 | return HAL_OK; |
| mbed_official | 354:e67efb2aab0e | 861 | } |
| mbed_official | 354:e67efb2aab0e | 862 | |
| mbed_official | 354:e67efb2aab0e | 863 | /** |
| mbed_official | 354:e67efb2aab0e | 864 | * @brief Stops the TIM Output Compare signal generation in DMA mode. |
| mbed_official | 354:e67efb2aab0e | 865 | * @param htim : TIM Output Compare handle |
| mbed_official | 354:e67efb2aab0e | 866 | * @param Channel : TIM Channel to be disabled |
| mbed_official | 354:e67efb2aab0e | 867 | * This parameter can be one of the following values: |
| mbed_official | 354:e67efb2aab0e | 868 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| mbed_official | 354:e67efb2aab0e | 869 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| mbed_official | 354:e67efb2aab0e | 870 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
| mbed_official | 354:e67efb2aab0e | 871 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
| mbed_official | 354:e67efb2aab0e | 872 | * @retval HAL status |
| mbed_official | 354:e67efb2aab0e | 873 | */ |
| mbed_official | 354:e67efb2aab0e | 874 | HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) |
| mbed_official | 354:e67efb2aab0e | 875 | { |
| mbed_official | 354:e67efb2aab0e | 876 | /* Check the parameters */ |
| mbed_official | 354:e67efb2aab0e | 877 | assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); |
| mbed_official | 354:e67efb2aab0e | 878 | |
| mbed_official | 354:e67efb2aab0e | 879 | switch (Channel) |
| mbed_official | 354:e67efb2aab0e | 880 | { |
| mbed_official | 354:e67efb2aab0e | 881 | case TIM_CHANNEL_1: |
| mbed_official | 354:e67efb2aab0e | 882 | { |
| mbed_official | 354:e67efb2aab0e | 883 | /* Disable the TIM Capture/Compare 1 DMA request */ |
| mbed_official | 354:e67efb2aab0e | 884 | __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); |
| mbed_official | 354:e67efb2aab0e | 885 | } |
| mbed_official | 354:e67efb2aab0e | 886 | break; |
| mbed_official | 354:e67efb2aab0e | 887 | |
| mbed_official | 354:e67efb2aab0e | 888 | case TIM_CHANNEL_2: |
| mbed_official | 354:e67efb2aab0e | 889 | { |
| mbed_official | 354:e67efb2aab0e | 890 | /* Disable the TIM Capture/Compare 2 DMA request */ |
| mbed_official | 354:e67efb2aab0e | 891 | __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); |
| mbed_official | 354:e67efb2aab0e | 892 | } |
| mbed_official | 354:e67efb2aab0e | 893 | break; |
| mbed_official | 354:e67efb2aab0e | 894 | |
| mbed_official | 354:e67efb2aab0e | 895 | case TIM_CHANNEL_3: |
| mbed_official | 354:e67efb2aab0e | 896 | { |
| mbed_official | 354:e67efb2aab0e | 897 | /* Disable the TIM Capture/Compare 3 DMA request */ |
| mbed_official | 354:e67efb2aab0e | 898 | __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); |
| mbed_official | 354:e67efb2aab0e | 899 | } |
| mbed_official | 354:e67efb2aab0e | 900 | break; |
| mbed_official | 354:e67efb2aab0e | 901 | |
| mbed_official | 354:e67efb2aab0e | 902 | case TIM_CHANNEL_4: |
| mbed_official | 354:e67efb2aab0e | 903 | { |
| mbed_official | 354:e67efb2aab0e | 904 | /* Disable the TIM Capture/Compare 4 interrupt */ |
| mbed_official | 354:e67efb2aab0e | 905 | __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); |
| mbed_official | 354:e67efb2aab0e | 906 | } |
| mbed_official | 354:e67efb2aab0e | 907 | break; |
| mbed_official | 354:e67efb2aab0e | 908 | |
| mbed_official | 354:e67efb2aab0e | 909 | default: |
| mbed_official | 354:e67efb2aab0e | 910 | break; |
| mbed_official | 354:e67efb2aab0e | 911 | } |
| mbed_official | 354:e67efb2aab0e | 912 | |
| mbed_official | 354:e67efb2aab0e | 913 | /* Disable the Output compare channel */ |
| mbed_official | 354:e67efb2aab0e | 914 | TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); |
| mbed_official | 354:e67efb2aab0e | 915 | |
| mbed_official | 354:e67efb2aab0e | 916 | /* Disable the Peripheral */ |
| mbed_official | 354:e67efb2aab0e | 917 | __HAL_TIM_DISABLE(htim); |
| mbed_official | 354:e67efb2aab0e | 918 | |
| mbed_official | 354:e67efb2aab0e | 919 | /* Change the htim state */ |
| mbed_official | 354:e67efb2aab0e | 920 | htim->State = HAL_TIM_STATE_READY; |
| mbed_official | 354:e67efb2aab0e | 921 | |
| mbed_official | 354:e67efb2aab0e | 922 | /* Return function status */ |
| mbed_official | 354:e67efb2aab0e | 923 | return HAL_OK; |
| mbed_official | 354:e67efb2aab0e | 924 | } |
| mbed_official | 354:e67efb2aab0e | 925 | |
| mbed_official | 354:e67efb2aab0e | 926 | /** |
| mbed_official | 354:e67efb2aab0e | 927 | * @} |
| mbed_official | 354:e67efb2aab0e | 928 | */ |
| mbed_official | 354:e67efb2aab0e | 929 | |
| mbed_official | 354:e67efb2aab0e | 930 | /** @defgroup TIM_Exported_Functions_Group3 Time PWM functions |
| mbed_official | 354:e67efb2aab0e | 931 | * @brief Time PWM functions |
| mbed_official | 354:e67efb2aab0e | 932 | * |
| mbed_official | 354:e67efb2aab0e | 933 | @verbatim |
| mbed_official | 354:e67efb2aab0e | 934 | ============================================================================== |
| mbed_official | 354:e67efb2aab0e | 935 | ##### Time PWM functions ##### |
| mbed_official | 354:e67efb2aab0e | 936 | ============================================================================== |
| mbed_official | 354:e67efb2aab0e | 937 | [..] |
| mbed_official | 354:e67efb2aab0e | 938 | This section provides functions allowing to: |
| mbed_official | 354:e67efb2aab0e | 939 | (+) Initialize and configure the TIM OPWM. |
| mbed_official | 354:e67efb2aab0e | 940 | (+) De-initialize the TIM PWM. |
| mbed_official | 354:e67efb2aab0e | 941 | (+) Start the Time PWM. |
| mbed_official | 354:e67efb2aab0e | 942 | (+) Stop the Time PWM. |
| mbed_official | 354:e67efb2aab0e | 943 | (+) Start the Time PWM and enable interrupt. |
| mbed_official | 354:e67efb2aab0e | 944 | (+) Stop the Time PWM and disable interrupt. |
| mbed_official | 354:e67efb2aab0e | 945 | (+) Start the Time PWM and enable DMA transfer. |
| mbed_official | 354:e67efb2aab0e | 946 | (+) Stop the Time PWM and disable DMA transfer. |
| mbed_official | 354:e67efb2aab0e | 947 | |
| mbed_official | 354:e67efb2aab0e | 948 | @endverbatim |
| mbed_official | 354:e67efb2aab0e | 949 | * @{ |
| mbed_official | 354:e67efb2aab0e | 950 | */ |
| mbed_official | 354:e67efb2aab0e | 951 | /** |
| mbed_official | 354:e67efb2aab0e | 952 | * @brief Initializes the TIM PWM Time Base according to the specified |
| mbed_official | 354:e67efb2aab0e | 953 | * parameters in the TIM_HandleTypeDef and create the associated handle. |
| mbed_official | 354:e67efb2aab0e | 954 | * @param htim: TIM handle |
| mbed_official | 354:e67efb2aab0e | 955 | * @retval HAL status |
| mbed_official | 354:e67efb2aab0e | 956 | */ |
| mbed_official | 354:e67efb2aab0e | 957 | HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) |
| mbed_official | 354:e67efb2aab0e | 958 | { |
| mbed_official | 354:e67efb2aab0e | 959 | /* Check the TIM handle allocation */ |
| mbed_official | 354:e67efb2aab0e | 960 | if(htim == HAL_NULL) |
| mbed_official | 354:e67efb2aab0e | 961 | { |
| mbed_official | 354:e67efb2aab0e | 962 | return HAL_ERROR; |
| mbed_official | 354:e67efb2aab0e | 963 | } |
| mbed_official | 354:e67efb2aab0e | 964 | |
| mbed_official | 354:e67efb2aab0e | 965 | /* Check the parameters */ |
| mbed_official | 354:e67efb2aab0e | 966 | assert_param(IS_TIM_INSTANCE(htim->Instance)); |
| mbed_official | 354:e67efb2aab0e | 967 | assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); |
| mbed_official | 354:e67efb2aab0e | 968 | assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); |
| mbed_official | 354:e67efb2aab0e | 969 | |
| mbed_official | 354:e67efb2aab0e | 970 | if(htim->State == HAL_TIM_STATE_RESET) |
| mbed_official | 354:e67efb2aab0e | 971 | { |
| mbed_official | 354:e67efb2aab0e | 972 | /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ |
| mbed_official | 354:e67efb2aab0e | 973 | HAL_TIM_PWM_MspInit(htim); |
| mbed_official | 354:e67efb2aab0e | 974 | } |
| mbed_official | 354:e67efb2aab0e | 975 | |
| mbed_official | 354:e67efb2aab0e | 976 | /* Set the TIM state */ |
| mbed_official | 354:e67efb2aab0e | 977 | htim->State= HAL_TIM_STATE_BUSY; |
| mbed_official | 354:e67efb2aab0e | 978 | |
| mbed_official | 354:e67efb2aab0e | 979 | /* Init the base time for the PWM */ |
| mbed_official | 354:e67efb2aab0e | 980 | TIM_Base_SetConfig(htim->Instance, &htim->Init); |
| mbed_official | 354:e67efb2aab0e | 981 | |
| mbed_official | 354:e67efb2aab0e | 982 | /* Initialize the TIM state*/ |
| mbed_official | 354:e67efb2aab0e | 983 | htim->State= HAL_TIM_STATE_READY; |
| mbed_official | 354:e67efb2aab0e | 984 | |
| mbed_official | 354:e67efb2aab0e | 985 | return HAL_OK; |
| mbed_official | 354:e67efb2aab0e | 986 | } |
| mbed_official | 354:e67efb2aab0e | 987 | |
| mbed_official | 354:e67efb2aab0e | 988 | /** |
| mbed_official | 354:e67efb2aab0e | 989 | * @brief DeInitializes the TIM peripheral |
| mbed_official | 354:e67efb2aab0e | 990 | * @param htim: TIM handle |
| mbed_official | 354:e67efb2aab0e | 991 | * @retval HAL status |
| mbed_official | 354:e67efb2aab0e | 992 | */ |
| mbed_official | 354:e67efb2aab0e | 993 | HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim) |
| mbed_official | 354:e67efb2aab0e | 994 | { |
| mbed_official | 354:e67efb2aab0e | 995 | /* Check the parameters */ |
| mbed_official | 354:e67efb2aab0e | 996 | assert_param(IS_TIM_INSTANCE(htim->Instance)); |
| mbed_official | 354:e67efb2aab0e | 997 | |
| mbed_official | 354:e67efb2aab0e | 998 | htim->State = HAL_TIM_STATE_BUSY; |
| mbed_official | 354:e67efb2aab0e | 999 | |
| mbed_official | 354:e67efb2aab0e | 1000 | /* Disable the TIM Peripheral Clock */ |
| mbed_official | 354:e67efb2aab0e | 1001 | __HAL_TIM_DISABLE(htim); |
| mbed_official | 354:e67efb2aab0e | 1002 | |
| mbed_official | 354:e67efb2aab0e | 1003 | /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ |
| mbed_official | 354:e67efb2aab0e | 1004 | HAL_TIM_PWM_MspDeInit(htim); |
| mbed_official | 354:e67efb2aab0e | 1005 | |
| mbed_official | 354:e67efb2aab0e | 1006 | /* Change TIM state */ |
| mbed_official | 354:e67efb2aab0e | 1007 | htim->State = HAL_TIM_STATE_RESET; |
| mbed_official | 354:e67efb2aab0e | 1008 | |
| mbed_official | 354:e67efb2aab0e | 1009 | /* Release Lock */ |
| mbed_official | 354:e67efb2aab0e | 1010 | __HAL_UNLOCK(htim); |
| mbed_official | 354:e67efb2aab0e | 1011 | |
| mbed_official | 354:e67efb2aab0e | 1012 | return HAL_OK; |
| mbed_official | 354:e67efb2aab0e | 1013 | } |
| mbed_official | 354:e67efb2aab0e | 1014 | |
| mbed_official | 354:e67efb2aab0e | 1015 | /** |
| mbed_official | 354:e67efb2aab0e | 1016 | * @brief Initializes the TIM PWM MSP. |
| mbed_official | 354:e67efb2aab0e | 1017 | * @param htim: TIM handle |
| mbed_official | 354:e67efb2aab0e | 1018 | * @retval None |
| mbed_official | 354:e67efb2aab0e | 1019 | */ |
| mbed_official | 354:e67efb2aab0e | 1020 | __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim) |
| mbed_official | 354:e67efb2aab0e | 1021 | { |
| mbed_official | 354:e67efb2aab0e | 1022 | /* NOTE : This function Should not be modified, when the callback is needed, |
| mbed_official | 354:e67efb2aab0e | 1023 | the HAL_TIM_PWM_MspInit could be implemented in the user file |
| mbed_official | 354:e67efb2aab0e | 1024 | */ |
| mbed_official | 354:e67efb2aab0e | 1025 | } |
| mbed_official | 354:e67efb2aab0e | 1026 | |
| mbed_official | 354:e67efb2aab0e | 1027 | /** |
| mbed_official | 354:e67efb2aab0e | 1028 | * @brief DeInitializes TIM PWM MSP. |
| mbed_official | 354:e67efb2aab0e | 1029 | * @param htim: TIM handle |
| mbed_official | 354:e67efb2aab0e | 1030 | * @retval None |
| mbed_official | 354:e67efb2aab0e | 1031 | */ |
| mbed_official | 354:e67efb2aab0e | 1032 | __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim) |
| mbed_official | 354:e67efb2aab0e | 1033 | { |
| mbed_official | 354:e67efb2aab0e | 1034 | /* NOTE : This function Should not be modified, when the callback is needed, |
| mbed_official | 354:e67efb2aab0e | 1035 | the HAL_TIM_PWM_MspDeInit could be implemented in the user file |
| mbed_official | 354:e67efb2aab0e | 1036 | */ |
| mbed_official | 354:e67efb2aab0e | 1037 | } |
| mbed_official | 354:e67efb2aab0e | 1038 | |
| mbed_official | 354:e67efb2aab0e | 1039 | /** |
| mbed_official | 354:e67efb2aab0e | 1040 | * @brief Starts the PWM signal generation. |
| mbed_official | 354:e67efb2aab0e | 1041 | * @param htim : TIM handle |
| mbed_official | 354:e67efb2aab0e | 1042 | * @param Channel : TIM Channels to be enabled |
| mbed_official | 354:e67efb2aab0e | 1043 | * This parameter can be one of the following values: |
| mbed_official | 354:e67efb2aab0e | 1044 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| mbed_official | 354:e67efb2aab0e | 1045 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| mbed_official | 354:e67efb2aab0e | 1046 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
| mbed_official | 354:e67efb2aab0e | 1047 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
| mbed_official | 354:e67efb2aab0e | 1048 | * @retval HAL status |
| mbed_official | 354:e67efb2aab0e | 1049 | */ |
| mbed_official | 354:e67efb2aab0e | 1050 | HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) |
| mbed_official | 354:e67efb2aab0e | 1051 | { |
| mbed_official | 354:e67efb2aab0e | 1052 | /* Check the parameters */ |
| mbed_official | 354:e67efb2aab0e | 1053 | assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); |
| mbed_official | 354:e67efb2aab0e | 1054 | |
| mbed_official | 354:e67efb2aab0e | 1055 | /* Enable the Capture compare channel */ |
| mbed_official | 354:e67efb2aab0e | 1056 | TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); |
| mbed_official | 354:e67efb2aab0e | 1057 | |
| mbed_official | 354:e67efb2aab0e | 1058 | /* Enable the Peripheral */ |
| mbed_official | 354:e67efb2aab0e | 1059 | __HAL_TIM_ENABLE(htim); |
| mbed_official | 354:e67efb2aab0e | 1060 | |
| mbed_official | 354:e67efb2aab0e | 1061 | /* Return function status */ |
| mbed_official | 354:e67efb2aab0e | 1062 | return HAL_OK; |
| mbed_official | 354:e67efb2aab0e | 1063 | } |
| mbed_official | 354:e67efb2aab0e | 1064 | |
| mbed_official | 354:e67efb2aab0e | 1065 | /** |
| mbed_official | 354:e67efb2aab0e | 1066 | * @brief Stops the PWM signal generation. |
| mbed_official | 354:e67efb2aab0e | 1067 | * @param htim : TIM handle |
| mbed_official | 354:e67efb2aab0e | 1068 | * @param Channel : TIM Channels to be disabled |
| mbed_official | 354:e67efb2aab0e | 1069 | * This parameter can be one of the following values: |
| mbed_official | 354:e67efb2aab0e | 1070 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| mbed_official | 354:e67efb2aab0e | 1071 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| mbed_official | 354:e67efb2aab0e | 1072 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
| mbed_official | 354:e67efb2aab0e | 1073 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
| mbed_official | 354:e67efb2aab0e | 1074 | * @retval HAL status |
| mbed_official | 354:e67efb2aab0e | 1075 | */ |
| mbed_official | 354:e67efb2aab0e | 1076 | HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) |
| mbed_official | 354:e67efb2aab0e | 1077 | { |
| mbed_official | 354:e67efb2aab0e | 1078 | /* Check the parameters */ |
| mbed_official | 354:e67efb2aab0e | 1079 | assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); |
| mbed_official | 354:e67efb2aab0e | 1080 | |
| mbed_official | 354:e67efb2aab0e | 1081 | /* Disable the Capture compare channel */ |
| mbed_official | 354:e67efb2aab0e | 1082 | TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); |
| mbed_official | 354:e67efb2aab0e | 1083 | |
| mbed_official | 354:e67efb2aab0e | 1084 | /* Disable the Peripheral */ |
| mbed_official | 354:e67efb2aab0e | 1085 | __HAL_TIM_DISABLE(htim); |
| mbed_official | 354:e67efb2aab0e | 1086 | |
| mbed_official | 354:e67efb2aab0e | 1087 | /* Change the htim state */ |
| mbed_official | 354:e67efb2aab0e | 1088 | htim->State = HAL_TIM_STATE_READY; |
| mbed_official | 354:e67efb2aab0e | 1089 | |
| mbed_official | 354:e67efb2aab0e | 1090 | /* Return function status */ |
| mbed_official | 354:e67efb2aab0e | 1091 | return HAL_OK; |
| mbed_official | 354:e67efb2aab0e | 1092 | } |
| mbed_official | 354:e67efb2aab0e | 1093 | |
| mbed_official | 354:e67efb2aab0e | 1094 | /** |
| mbed_official | 354:e67efb2aab0e | 1095 | * @brief Starts the PWM signal generation in interrupt mode. |
| mbed_official | 354:e67efb2aab0e | 1096 | * @param htim : TIM handle |
| mbed_official | 354:e67efb2aab0e | 1097 | * @param Channel : TIM Channel to be disabled |
| mbed_official | 354:e67efb2aab0e | 1098 | * This parameter can be one of the following values: |
| mbed_official | 354:e67efb2aab0e | 1099 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| mbed_official | 354:e67efb2aab0e | 1100 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| mbed_official | 354:e67efb2aab0e | 1101 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
| mbed_official | 354:e67efb2aab0e | 1102 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
| mbed_official | 354:e67efb2aab0e | 1103 | * @retval HAL status |
| mbed_official | 354:e67efb2aab0e | 1104 | */ |
| mbed_official | 354:e67efb2aab0e | 1105 | HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) |
| mbed_official | 354:e67efb2aab0e | 1106 | { |
| mbed_official | 354:e67efb2aab0e | 1107 | /* Check the parameters */ |
| mbed_official | 354:e67efb2aab0e | 1108 | assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); |
| mbed_official | 354:e67efb2aab0e | 1109 | |
| mbed_official | 354:e67efb2aab0e | 1110 | switch (Channel) |
| mbed_official | 354:e67efb2aab0e | 1111 | { |
| mbed_official | 354:e67efb2aab0e | 1112 | case TIM_CHANNEL_1: |
| mbed_official | 354:e67efb2aab0e | 1113 | { |
| mbed_official | 354:e67efb2aab0e | 1114 | /* Enable the TIM Capture/Compare 1 interrupt */ |
| mbed_official | 354:e67efb2aab0e | 1115 | __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); |
| mbed_official | 354:e67efb2aab0e | 1116 | } |
| mbed_official | 354:e67efb2aab0e | 1117 | break; |
| mbed_official | 354:e67efb2aab0e | 1118 | |
| mbed_official | 354:e67efb2aab0e | 1119 | case TIM_CHANNEL_2: |
| mbed_official | 354:e67efb2aab0e | 1120 | { |
| mbed_official | 354:e67efb2aab0e | 1121 | /* Enable the TIM Capture/Compare 2 interrupt */ |
| mbed_official | 354:e67efb2aab0e | 1122 | __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); |
| mbed_official | 354:e67efb2aab0e | 1123 | } |
| mbed_official | 354:e67efb2aab0e | 1124 | break; |
| mbed_official | 354:e67efb2aab0e | 1125 | |
| mbed_official | 354:e67efb2aab0e | 1126 | case TIM_CHANNEL_3: |
| mbed_official | 354:e67efb2aab0e | 1127 | { |
| mbed_official | 354:e67efb2aab0e | 1128 | /* Enable the TIM Capture/Compare 3 interrupt */ |
| mbed_official | 354:e67efb2aab0e | 1129 | __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); |
| mbed_official | 354:e67efb2aab0e | 1130 | } |
| mbed_official | 354:e67efb2aab0e | 1131 | break; |
| mbed_official | 354:e67efb2aab0e | 1132 | |
| mbed_official | 354:e67efb2aab0e | 1133 | case TIM_CHANNEL_4: |
| mbed_official | 354:e67efb2aab0e | 1134 | { |
| mbed_official | 354:e67efb2aab0e | 1135 | /* Enable the TIM Capture/Compare 4 interrupt */ |
| mbed_official | 354:e67efb2aab0e | 1136 | __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); |
| mbed_official | 354:e67efb2aab0e | 1137 | } |
| mbed_official | 354:e67efb2aab0e | 1138 | break; |
| mbed_official | 354:e67efb2aab0e | 1139 | |
| mbed_official | 354:e67efb2aab0e | 1140 | default: |
| mbed_official | 354:e67efb2aab0e | 1141 | break; |
| mbed_official | 354:e67efb2aab0e | 1142 | } |
| mbed_official | 354:e67efb2aab0e | 1143 | |
| mbed_official | 354:e67efb2aab0e | 1144 | /* Enable the Capture compare channel */ |
| mbed_official | 354:e67efb2aab0e | 1145 | TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); |
| mbed_official | 354:e67efb2aab0e | 1146 | |
| mbed_official | 354:e67efb2aab0e | 1147 | /* Enable the Peripheral */ |
| mbed_official | 354:e67efb2aab0e | 1148 | __HAL_TIM_ENABLE(htim); |
| mbed_official | 354:e67efb2aab0e | 1149 | |
| mbed_official | 354:e67efb2aab0e | 1150 | /* Return function status */ |
| mbed_official | 354:e67efb2aab0e | 1151 | return HAL_OK; |
| mbed_official | 354:e67efb2aab0e | 1152 | } |
| mbed_official | 354:e67efb2aab0e | 1153 | |
| mbed_official | 354:e67efb2aab0e | 1154 | /** |
| mbed_official | 354:e67efb2aab0e | 1155 | * @brief Stops the PWM signal generation in interrupt mode. |
| mbed_official | 354:e67efb2aab0e | 1156 | * @param htim : TIM handle |
| mbed_official | 354:e67efb2aab0e | 1157 | * @param Channel : TIM Channels to be disabled |
| mbed_official | 354:e67efb2aab0e | 1158 | * This parameter can be one of the following values: |
| mbed_official | 354:e67efb2aab0e | 1159 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| mbed_official | 354:e67efb2aab0e | 1160 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| mbed_official | 354:e67efb2aab0e | 1161 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
| mbed_official | 354:e67efb2aab0e | 1162 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
| mbed_official | 354:e67efb2aab0e | 1163 | * @retval HAL status |
| mbed_official | 354:e67efb2aab0e | 1164 | */ |
| mbed_official | 354:e67efb2aab0e | 1165 | HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel) |
| mbed_official | 354:e67efb2aab0e | 1166 | { |
| mbed_official | 354:e67efb2aab0e | 1167 | /* Check the parameters */ |
| mbed_official | 354:e67efb2aab0e | 1168 | assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); |
| mbed_official | 354:e67efb2aab0e | 1169 | |
| mbed_official | 354:e67efb2aab0e | 1170 | switch (Channel) |
| mbed_official | 354:e67efb2aab0e | 1171 | { |
| mbed_official | 354:e67efb2aab0e | 1172 | case TIM_CHANNEL_1: |
| mbed_official | 354:e67efb2aab0e | 1173 | { |
| mbed_official | 354:e67efb2aab0e | 1174 | /* Disable the TIM Capture/Compare 1 interrupt */ |
| mbed_official | 354:e67efb2aab0e | 1175 | __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); |
| mbed_official | 354:e67efb2aab0e | 1176 | } |
| mbed_official | 354:e67efb2aab0e | 1177 | break; |
| mbed_official | 354:e67efb2aab0e | 1178 | |
| mbed_official | 354:e67efb2aab0e | 1179 | case TIM_CHANNEL_2: |
| mbed_official | 354:e67efb2aab0e | 1180 | { |
| mbed_official | 354:e67efb2aab0e | 1181 | /* Disable the TIM Capture/Compare 2 interrupt */ |
| mbed_official | 354:e67efb2aab0e | 1182 | __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); |
| mbed_official | 354:e67efb2aab0e | 1183 | } |
| mbed_official | 354:e67efb2aab0e | 1184 | break; |
| mbed_official | 354:e67efb2aab0e | 1185 | |
| mbed_official | 354:e67efb2aab0e | 1186 | case TIM_CHANNEL_3: |
| mbed_official | 354:e67efb2aab0e | 1187 | { |
| mbed_official | 354:e67efb2aab0e | 1188 | /* Disable the TIM Capture/Compare 3 interrupt */ |
| mbed_official | 354:e67efb2aab0e | 1189 | __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); |
| mbed_official | 354:e67efb2aab0e | 1190 | } |
| mbed_official | 354:e67efb2aab0e | 1191 | break; |
| mbed_official | 354:e67efb2aab0e | 1192 | |
| mbed_official | 354:e67efb2aab0e | 1193 | case TIM_CHANNEL_4: |
| mbed_official | 354:e67efb2aab0e | 1194 | { |
| mbed_official | 354:e67efb2aab0e | 1195 | /* Disable the TIM Capture/Compare 4 interrupt */ |
| mbed_official | 354:e67efb2aab0e | 1196 | __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); |
| mbed_official | 354:e67efb2aab0e | 1197 | } |
| mbed_official | 354:e67efb2aab0e | 1198 | break; |
| mbed_official | 354:e67efb2aab0e | 1199 | |
| mbed_official | 354:e67efb2aab0e | 1200 | default: |
| mbed_official | 354:e67efb2aab0e | 1201 | break; |
| mbed_official | 354:e67efb2aab0e | 1202 | } |
| mbed_official | 354:e67efb2aab0e | 1203 | |
| mbed_official | 354:e67efb2aab0e | 1204 | /* Disable the Capture compare channel */ |
| mbed_official | 354:e67efb2aab0e | 1205 | TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); |
| mbed_official | 354:e67efb2aab0e | 1206 | |
| mbed_official | 354:e67efb2aab0e | 1207 | |
| mbed_official | 354:e67efb2aab0e | 1208 | /* Disable the Peripheral */ |
| mbed_official | 354:e67efb2aab0e | 1209 | __HAL_TIM_DISABLE(htim); |
| mbed_official | 354:e67efb2aab0e | 1210 | |
| mbed_official | 354:e67efb2aab0e | 1211 | /* Return function status */ |
| mbed_official | 354:e67efb2aab0e | 1212 | return HAL_OK; |
| mbed_official | 354:e67efb2aab0e | 1213 | } |
| mbed_official | 354:e67efb2aab0e | 1214 | |
| mbed_official | 354:e67efb2aab0e | 1215 | /** |
| mbed_official | 354:e67efb2aab0e | 1216 | * @brief Starts the TIM PWM signal generation in DMA mode. |
| mbed_official | 354:e67efb2aab0e | 1217 | * @param htim : TIM handle |
| mbed_official | 354:e67efb2aab0e | 1218 | * @param Channel : TIM Channels to be enabled |
| mbed_official | 354:e67efb2aab0e | 1219 | * This parameter can be one of the following values: |
| mbed_official | 354:e67efb2aab0e | 1220 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| mbed_official | 354:e67efb2aab0e | 1221 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| mbed_official | 354:e67efb2aab0e | 1222 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
| mbed_official | 354:e67efb2aab0e | 1223 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
| mbed_official | 354:e67efb2aab0e | 1224 | * @param pData: The source Buffer address. |
| mbed_official | 354:e67efb2aab0e | 1225 | * @param Length: The length of data to be transferred from memory to TIM peripheral |
| mbed_official | 354:e67efb2aab0e | 1226 | * @retval HAL status |
| mbed_official | 354:e67efb2aab0e | 1227 | */ |
| mbed_official | 354:e67efb2aab0e | 1228 | HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) |
| mbed_official | 354:e67efb2aab0e | 1229 | { |
| mbed_official | 354:e67efb2aab0e | 1230 | /* Check the parameters */ |
| mbed_official | 354:e67efb2aab0e | 1231 | assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); |
| mbed_official | 354:e67efb2aab0e | 1232 | |
| mbed_official | 354:e67efb2aab0e | 1233 | if((htim->State == HAL_TIM_STATE_BUSY)) |
| mbed_official | 354:e67efb2aab0e | 1234 | { |
| mbed_official | 354:e67efb2aab0e | 1235 | return HAL_BUSY; |
| mbed_official | 354:e67efb2aab0e | 1236 | } |
| mbed_official | 354:e67efb2aab0e | 1237 | else if((htim->State == HAL_TIM_STATE_READY)) |
| mbed_official | 354:e67efb2aab0e | 1238 | { |
| mbed_official | 354:e67efb2aab0e | 1239 | if(((uint32_t)pData == 0 ) && (Length > 0)) |
| mbed_official | 354:e67efb2aab0e | 1240 | { |
| mbed_official | 354:e67efb2aab0e | 1241 | return HAL_ERROR; |
| mbed_official | 354:e67efb2aab0e | 1242 | } |
| mbed_official | 354:e67efb2aab0e | 1243 | else |
| mbed_official | 354:e67efb2aab0e | 1244 | { |
| mbed_official | 354:e67efb2aab0e | 1245 | htim->State = HAL_TIM_STATE_BUSY; |
| mbed_official | 354:e67efb2aab0e | 1246 | } |
| mbed_official | 354:e67efb2aab0e | 1247 | } |
| mbed_official | 354:e67efb2aab0e | 1248 | else |
| mbed_official | 354:e67efb2aab0e | 1249 | { |
| mbed_official | 354:e67efb2aab0e | 1250 | return HAL_ERROR; |
| mbed_official | 354:e67efb2aab0e | 1251 | } |
| mbed_official | 354:e67efb2aab0e | 1252 | |
| mbed_official | 354:e67efb2aab0e | 1253 | switch (Channel) |
| mbed_official | 354:e67efb2aab0e | 1254 | { |
| mbed_official | 354:e67efb2aab0e | 1255 | case TIM_CHANNEL_1: |
| mbed_official | 354:e67efb2aab0e | 1256 | { |
| mbed_official | 354:e67efb2aab0e | 1257 | /* Set the DMA Period elapsed callback */ |
| mbed_official | 354:e67efb2aab0e | 1258 | htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; |
| mbed_official | 354:e67efb2aab0e | 1259 | |
| mbed_official | 354:e67efb2aab0e | 1260 | /* Set the DMA error callback */ |
| mbed_official | 354:e67efb2aab0e | 1261 | htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; |
| mbed_official | 354:e67efb2aab0e | 1262 | |
| mbed_official | 354:e67efb2aab0e | 1263 | /* Enable the DMA channel */ |
| mbed_official | 354:e67efb2aab0e | 1264 | HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length); |
| mbed_official | 354:e67efb2aab0e | 1265 | |
| mbed_official | 354:e67efb2aab0e | 1266 | /* Enable the TIM Capture/Compare 1 DMA request */ |
| mbed_official | 354:e67efb2aab0e | 1267 | __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); |
| mbed_official | 354:e67efb2aab0e | 1268 | } |
| mbed_official | 354:e67efb2aab0e | 1269 | break; |
| mbed_official | 354:e67efb2aab0e | 1270 | |
| mbed_official | 354:e67efb2aab0e | 1271 | case TIM_CHANNEL_2: |
| mbed_official | 354:e67efb2aab0e | 1272 | { |
| mbed_official | 354:e67efb2aab0e | 1273 | /* Set the DMA Period elapsed callback */ |
| mbed_official | 354:e67efb2aab0e | 1274 | htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; |
| mbed_official | 354:e67efb2aab0e | 1275 | |
| mbed_official | 354:e67efb2aab0e | 1276 | /* Set the DMA error callback */ |
| mbed_official | 354:e67efb2aab0e | 1277 | htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; |
| mbed_official | 354:e67efb2aab0e | 1278 | |
| mbed_official | 354:e67efb2aab0e | 1279 | /* Enable the DMA channel */ |
| mbed_official | 354:e67efb2aab0e | 1280 | HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length); |
| mbed_official | 354:e67efb2aab0e | 1281 | |
| mbed_official | 354:e67efb2aab0e | 1282 | /* Enable the TIM Capture/Compare 2 DMA request */ |
| mbed_official | 354:e67efb2aab0e | 1283 | __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); |
| mbed_official | 354:e67efb2aab0e | 1284 | } |
| mbed_official | 354:e67efb2aab0e | 1285 | break; |
| mbed_official | 354:e67efb2aab0e | 1286 | |
| mbed_official | 354:e67efb2aab0e | 1287 | case TIM_CHANNEL_3: |
| mbed_official | 354:e67efb2aab0e | 1288 | { |
| mbed_official | 354:e67efb2aab0e | 1289 | /* Set the DMA Period elapsed callback */ |
| mbed_official | 354:e67efb2aab0e | 1290 | htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; |
| mbed_official | 354:e67efb2aab0e | 1291 | |
| mbed_official | 354:e67efb2aab0e | 1292 | /* Set the DMA error callback */ |
| mbed_official | 354:e67efb2aab0e | 1293 | htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; |
| mbed_official | 354:e67efb2aab0e | 1294 | |
| mbed_official | 354:e67efb2aab0e | 1295 | /* Enable the DMA channel */ |
| mbed_official | 354:e67efb2aab0e | 1296 | HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length); |
| mbed_official | 354:e67efb2aab0e | 1297 | |
| mbed_official | 354:e67efb2aab0e | 1298 | /* Enable the TIM Output Capture/Compare 3 request */ |
| mbed_official | 354:e67efb2aab0e | 1299 | __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); |
| mbed_official | 354:e67efb2aab0e | 1300 | } |
| mbed_official | 354:e67efb2aab0e | 1301 | break; |
| mbed_official | 354:e67efb2aab0e | 1302 | |
| mbed_official | 354:e67efb2aab0e | 1303 | case TIM_CHANNEL_4: |
| mbed_official | 354:e67efb2aab0e | 1304 | { |
| mbed_official | 354:e67efb2aab0e | 1305 | /* Set the DMA Period elapsed callback */ |
| mbed_official | 354:e67efb2aab0e | 1306 | htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; |
| mbed_official | 354:e67efb2aab0e | 1307 | |
| mbed_official | 354:e67efb2aab0e | 1308 | /* Set the DMA error callback */ |
| mbed_official | 354:e67efb2aab0e | 1309 | htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; |
| mbed_official | 354:e67efb2aab0e | 1310 | |
| mbed_official | 354:e67efb2aab0e | 1311 | /* Enable the DMA channel */ |
| mbed_official | 354:e67efb2aab0e | 1312 | HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length); |
| mbed_official | 354:e67efb2aab0e | 1313 | |
| mbed_official | 354:e67efb2aab0e | 1314 | /* Enable the TIM Capture/Compare 4 DMA request */ |
| mbed_official | 354:e67efb2aab0e | 1315 | __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); |
| mbed_official | 354:e67efb2aab0e | 1316 | } |
| mbed_official | 354:e67efb2aab0e | 1317 | break; |
| mbed_official | 354:e67efb2aab0e | 1318 | |
| mbed_official | 354:e67efb2aab0e | 1319 | default: |
| mbed_official | 354:e67efb2aab0e | 1320 | break; |
| mbed_official | 354:e67efb2aab0e | 1321 | } |
| mbed_official | 354:e67efb2aab0e | 1322 | |
| mbed_official | 354:e67efb2aab0e | 1323 | /* Enable the Capture compare channel */ |
| mbed_official | 354:e67efb2aab0e | 1324 | TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); |
| mbed_official | 354:e67efb2aab0e | 1325 | |
| mbed_official | 354:e67efb2aab0e | 1326 | /* Enable the Peripheral */ |
| mbed_official | 354:e67efb2aab0e | 1327 | __HAL_TIM_ENABLE(htim); |
| mbed_official | 354:e67efb2aab0e | 1328 | |
| mbed_official | 354:e67efb2aab0e | 1329 | /* Return function status */ |
| mbed_official | 354:e67efb2aab0e | 1330 | return HAL_OK; |
| mbed_official | 354:e67efb2aab0e | 1331 | } |
| mbed_official | 354:e67efb2aab0e | 1332 | |
| mbed_official | 354:e67efb2aab0e | 1333 | /** |
| mbed_official | 354:e67efb2aab0e | 1334 | * @brief Stops the TIM PWM signal generation in DMA mode. |
| mbed_official | 354:e67efb2aab0e | 1335 | * @param htim : TIM handle |
| mbed_official | 354:e67efb2aab0e | 1336 | * @param Channel : TIM Channels to be disabled |
| mbed_official | 354:e67efb2aab0e | 1337 | * This parameter can be one of the following values: |
| mbed_official | 354:e67efb2aab0e | 1338 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| mbed_official | 354:e67efb2aab0e | 1339 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| mbed_official | 354:e67efb2aab0e | 1340 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
| mbed_official | 354:e67efb2aab0e | 1341 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
| mbed_official | 354:e67efb2aab0e | 1342 | * @retval HAL status |
| mbed_official | 354:e67efb2aab0e | 1343 | */ |
| mbed_official | 354:e67efb2aab0e | 1344 | HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) |
| mbed_official | 354:e67efb2aab0e | 1345 | { |
| mbed_official | 354:e67efb2aab0e | 1346 | /* Check the parameters */ |
| mbed_official | 354:e67efb2aab0e | 1347 | assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); |
| mbed_official | 354:e67efb2aab0e | 1348 | |
| mbed_official | 354:e67efb2aab0e | 1349 | switch (Channel) |
| mbed_official | 354:e67efb2aab0e | 1350 | { |
| mbed_official | 354:e67efb2aab0e | 1351 | case TIM_CHANNEL_1: |
| mbed_official | 354:e67efb2aab0e | 1352 | { |
| mbed_official | 354:e67efb2aab0e | 1353 | /* Disable the TIM Capture/Compare 1 DMA request */ |
| mbed_official | 354:e67efb2aab0e | 1354 | __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); |
| mbed_official | 354:e67efb2aab0e | 1355 | } |
| mbed_official | 354:e67efb2aab0e | 1356 | break; |
| mbed_official | 354:e67efb2aab0e | 1357 | |
| mbed_official | 354:e67efb2aab0e | 1358 | case TIM_CHANNEL_2: |
| mbed_official | 354:e67efb2aab0e | 1359 | { |
| mbed_official | 354:e67efb2aab0e | 1360 | /* Disable the TIM Capture/Compare 2 DMA request */ |
| mbed_official | 354:e67efb2aab0e | 1361 | __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); |
| mbed_official | 354:e67efb2aab0e | 1362 | } |
| mbed_official | 354:e67efb2aab0e | 1363 | break; |
| mbed_official | 354:e67efb2aab0e | 1364 | |
| mbed_official | 354:e67efb2aab0e | 1365 | case TIM_CHANNEL_3: |
| mbed_official | 354:e67efb2aab0e | 1366 | { |
| mbed_official | 354:e67efb2aab0e | 1367 | /* Disable the TIM Capture/Compare 3 DMA request */ |
| mbed_official | 354:e67efb2aab0e | 1368 | __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); |
| mbed_official | 354:e67efb2aab0e | 1369 | } |
| mbed_official | 354:e67efb2aab0e | 1370 | break; |
| mbed_official | 354:e67efb2aab0e | 1371 | |
| mbed_official | 354:e67efb2aab0e | 1372 | case TIM_CHANNEL_4: |
| mbed_official | 354:e67efb2aab0e | 1373 | { |
| mbed_official | 354:e67efb2aab0e | 1374 | /* Disable the TIM Capture/Compare 4 interrupt */ |
| mbed_official | 354:e67efb2aab0e | 1375 | __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); |
| mbed_official | 354:e67efb2aab0e | 1376 | } |
| mbed_official | 354:e67efb2aab0e | 1377 | break; |
| mbed_official | 354:e67efb2aab0e | 1378 | |
| mbed_official | 354:e67efb2aab0e | 1379 | default: |
| mbed_official | 354:e67efb2aab0e | 1380 | break; |
| mbed_official | 354:e67efb2aab0e | 1381 | } |
| mbed_official | 354:e67efb2aab0e | 1382 | |
| mbed_official | 354:e67efb2aab0e | 1383 | /* Disable the Capture compare channel */ |
| mbed_official | 354:e67efb2aab0e | 1384 | TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); |
| mbed_official | 354:e67efb2aab0e | 1385 | |
| mbed_official | 354:e67efb2aab0e | 1386 | /* Disable the Peripheral */ |
| mbed_official | 354:e67efb2aab0e | 1387 | __HAL_TIM_DISABLE(htim); |
| mbed_official | 354:e67efb2aab0e | 1388 | |
| mbed_official | 354:e67efb2aab0e | 1389 | /* Change the htim state */ |
| mbed_official | 354:e67efb2aab0e | 1390 | htim->State = HAL_TIM_STATE_READY; |
| mbed_official | 354:e67efb2aab0e | 1391 | |
| mbed_official | 354:e67efb2aab0e | 1392 | /* Return function status */ |
| mbed_official | 354:e67efb2aab0e | 1393 | return HAL_OK; |
| mbed_official | 354:e67efb2aab0e | 1394 | } |
| mbed_official | 354:e67efb2aab0e | 1395 | |
| mbed_official | 354:e67efb2aab0e | 1396 | /** |
| mbed_official | 354:e67efb2aab0e | 1397 | * @} |
| mbed_official | 354:e67efb2aab0e | 1398 | */ |
| mbed_official | 354:e67efb2aab0e | 1399 | |
| mbed_official | 354:e67efb2aab0e | 1400 | /** @defgroup TIM_Exported_Functions_Group4 Time Input Capture functions |
| mbed_official | 354:e67efb2aab0e | 1401 | * @brief Time Input Capture functions |
| mbed_official | 354:e67efb2aab0e | 1402 | * |
| mbed_official | 354:e67efb2aab0e | 1403 | @verbatim |
| mbed_official | 354:e67efb2aab0e | 1404 | ============================================================================== |
| mbed_official | 354:e67efb2aab0e | 1405 | ##### Time Input Capture functions ##### |
| mbed_official | 354:e67efb2aab0e | 1406 | ============================================================================== |
| mbed_official | 354:e67efb2aab0e | 1407 | [..] |
| mbed_official | 354:e67efb2aab0e | 1408 | This section provides functions allowing to: |
| mbed_official | 354:e67efb2aab0e | 1409 | (+) Initialize and configure the TIM Input Capture. |
| mbed_official | 354:e67efb2aab0e | 1410 | (+) De-initialize the TIM Input Capture. |
| mbed_official | 354:e67efb2aab0e | 1411 | (+) Start the Time Input Capture. |
| mbed_official | 354:e67efb2aab0e | 1412 | (+) Stop the Time Input Capture. |
| mbed_official | 354:e67efb2aab0e | 1413 | (+) Start the Time Input Capture and enable interrupt. |
| mbed_official | 354:e67efb2aab0e | 1414 | (+) Stop the Time Input Capture and disable interrupt. |
| mbed_official | 354:e67efb2aab0e | 1415 | (+) Start the Time Input Capture and enable DMA transfer. |
| mbed_official | 354:e67efb2aab0e | 1416 | (+) Stop the Time Input Capture and disable DMA transfer. |
| mbed_official | 354:e67efb2aab0e | 1417 | |
| mbed_official | 354:e67efb2aab0e | 1418 | @endverbatim |
| mbed_official | 354:e67efb2aab0e | 1419 | * @{ |
| mbed_official | 354:e67efb2aab0e | 1420 | */ |
| mbed_official | 354:e67efb2aab0e | 1421 | /** |
| mbed_official | 354:e67efb2aab0e | 1422 | * @brief Initializes the TIM Input Capture Time base according to the specified |
| mbed_official | 354:e67efb2aab0e | 1423 | * parameters in the TIM_HandleTypeDef and create the associated handle. |
| mbed_official | 354:e67efb2aab0e | 1424 | * @param htim: TIM Input Capture handle |
| mbed_official | 354:e67efb2aab0e | 1425 | * @retval HAL status |
| mbed_official | 354:e67efb2aab0e | 1426 | */ |
| mbed_official | 354:e67efb2aab0e | 1427 | HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim) |
| mbed_official | 354:e67efb2aab0e | 1428 | { |
| mbed_official | 354:e67efb2aab0e | 1429 | /* Check the TIM handle allocation */ |
| mbed_official | 354:e67efb2aab0e | 1430 | if(htim == HAL_NULL) |
| mbed_official | 354:e67efb2aab0e | 1431 | { |
| mbed_official | 354:e67efb2aab0e | 1432 | return HAL_ERROR; |
| mbed_official | 354:e67efb2aab0e | 1433 | } |
| mbed_official | 354:e67efb2aab0e | 1434 | |
| mbed_official | 354:e67efb2aab0e | 1435 | /* Check the parameters */ |
| mbed_official | 354:e67efb2aab0e | 1436 | assert_param(IS_TIM_INSTANCE(htim->Instance)); |
| mbed_official | 354:e67efb2aab0e | 1437 | assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); |
| mbed_official | 354:e67efb2aab0e | 1438 | assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); |
| mbed_official | 354:e67efb2aab0e | 1439 | |
| mbed_official | 354:e67efb2aab0e | 1440 | if(htim->State == HAL_TIM_STATE_RESET) |
| mbed_official | 354:e67efb2aab0e | 1441 | { |
| mbed_official | 354:e67efb2aab0e | 1442 | /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ |
| mbed_official | 354:e67efb2aab0e | 1443 | HAL_TIM_IC_MspInit(htim); |
| mbed_official | 354:e67efb2aab0e | 1444 | } |
| mbed_official | 354:e67efb2aab0e | 1445 | |
| mbed_official | 354:e67efb2aab0e | 1446 | /* Set the TIM state */ |
| mbed_official | 354:e67efb2aab0e | 1447 | htim->State= HAL_TIM_STATE_BUSY; |
| mbed_official | 354:e67efb2aab0e | 1448 | |
| mbed_official | 354:e67efb2aab0e | 1449 | /* Init the base time for the input capture */ |
| mbed_official | 354:e67efb2aab0e | 1450 | TIM_Base_SetConfig(htim->Instance, &htim->Init); |
| mbed_official | 354:e67efb2aab0e | 1451 | |
| mbed_official | 354:e67efb2aab0e | 1452 | /* Initialize the TIM state*/ |
| mbed_official | 354:e67efb2aab0e | 1453 | htim->State= HAL_TIM_STATE_READY; |
| mbed_official | 354:e67efb2aab0e | 1454 | |
| mbed_official | 354:e67efb2aab0e | 1455 | return HAL_OK; |
| mbed_official | 354:e67efb2aab0e | 1456 | } |
| mbed_official | 354:e67efb2aab0e | 1457 | |
| mbed_official | 354:e67efb2aab0e | 1458 | /** |
| mbed_official | 354:e67efb2aab0e | 1459 | * @brief DeInitializes the TIM peripheral |
| mbed_official | 354:e67efb2aab0e | 1460 | * @param htim: TIM Input Capture handle |
| mbed_official | 354:e67efb2aab0e | 1461 | * @retval HAL status |
| mbed_official | 354:e67efb2aab0e | 1462 | */ |
| mbed_official | 354:e67efb2aab0e | 1463 | HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim) |
| mbed_official | 354:e67efb2aab0e | 1464 | { |
| mbed_official | 354:e67efb2aab0e | 1465 | /* Check the parameters */ |
| mbed_official | 354:e67efb2aab0e | 1466 | assert_param(IS_TIM_INSTANCE(htim->Instance)); |
| mbed_official | 354:e67efb2aab0e | 1467 | |
| mbed_official | 354:e67efb2aab0e | 1468 | htim->State = HAL_TIM_STATE_BUSY; |
| mbed_official | 354:e67efb2aab0e | 1469 | |
| mbed_official | 354:e67efb2aab0e | 1470 | /* Disable the TIM Peripheral Clock */ |
| mbed_official | 354:e67efb2aab0e | 1471 | __HAL_TIM_DISABLE(htim); |
| mbed_official | 354:e67efb2aab0e | 1472 | |
| mbed_official | 354:e67efb2aab0e | 1473 | /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ |
| mbed_official | 354:e67efb2aab0e | 1474 | HAL_TIM_IC_MspDeInit(htim); |
| mbed_official | 354:e67efb2aab0e | 1475 | |
| mbed_official | 354:e67efb2aab0e | 1476 | /* Change TIM state */ |
| mbed_official | 354:e67efb2aab0e | 1477 | htim->State = HAL_TIM_STATE_RESET; |
| mbed_official | 354:e67efb2aab0e | 1478 | |
| mbed_official | 354:e67efb2aab0e | 1479 | /* Release Lock */ |
| mbed_official | 354:e67efb2aab0e | 1480 | __HAL_UNLOCK(htim); |
| mbed_official | 354:e67efb2aab0e | 1481 | |
| mbed_official | 354:e67efb2aab0e | 1482 | return HAL_OK; |
| mbed_official | 354:e67efb2aab0e | 1483 | } |
| mbed_official | 354:e67efb2aab0e | 1484 | |
| mbed_official | 354:e67efb2aab0e | 1485 | /** |
| mbed_official | 354:e67efb2aab0e | 1486 | * @brief Initializes the TIM INput Capture MSP. |
| mbed_official | 354:e67efb2aab0e | 1487 | * @param htim: TIM handle |
| mbed_official | 354:e67efb2aab0e | 1488 | * @retval None |
| mbed_official | 354:e67efb2aab0e | 1489 | */ |
| mbed_official | 354:e67efb2aab0e | 1490 | __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim) |
| mbed_official | 354:e67efb2aab0e | 1491 | { |
| mbed_official | 354:e67efb2aab0e | 1492 | /* NOTE : This function Should not be modified, when the callback is needed, |
| mbed_official | 354:e67efb2aab0e | 1493 | the HAL_TIM_IC_MspInit could be implemented in the user file |
| mbed_official | 354:e67efb2aab0e | 1494 | */ |
| mbed_official | 354:e67efb2aab0e | 1495 | } |
| mbed_official | 354:e67efb2aab0e | 1496 | |
| mbed_official | 354:e67efb2aab0e | 1497 | /** |
| mbed_official | 354:e67efb2aab0e | 1498 | * @brief DeInitializes TIM Input Capture MSP. |
| mbed_official | 354:e67efb2aab0e | 1499 | * @param htim: TIM handle |
| mbed_official | 354:e67efb2aab0e | 1500 | * @retval None |
| mbed_official | 354:e67efb2aab0e | 1501 | */ |
| mbed_official | 354:e67efb2aab0e | 1502 | __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim) |
| mbed_official | 354:e67efb2aab0e | 1503 | { |
| mbed_official | 354:e67efb2aab0e | 1504 | /* NOTE : This function Should not be modified, when the callback is needed, |
| mbed_official | 354:e67efb2aab0e | 1505 | the HAL_TIM_IC_MspDeInit could be implemented in the user file |
| mbed_official | 354:e67efb2aab0e | 1506 | */ |
| mbed_official | 354:e67efb2aab0e | 1507 | } |
| mbed_official | 354:e67efb2aab0e | 1508 | |
| mbed_official | 354:e67efb2aab0e | 1509 | /** |
| mbed_official | 354:e67efb2aab0e | 1510 | * @brief Starts the TIM Input Capture measurement. |
| mbed_official | 354:e67efb2aab0e | 1511 | * @param htim : TIM Input Capture handle |
| mbed_official | 354:e67efb2aab0e | 1512 | * @param Channel : TIM Channels to be enabled |
| mbed_official | 354:e67efb2aab0e | 1513 | * This parameter can be one of the following values: |
| mbed_official | 354:e67efb2aab0e | 1514 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| mbed_official | 354:e67efb2aab0e | 1515 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| mbed_official | 354:e67efb2aab0e | 1516 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
| mbed_official | 354:e67efb2aab0e | 1517 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
| mbed_official | 354:e67efb2aab0e | 1518 | * @retval HAL status |
| mbed_official | 354:e67efb2aab0e | 1519 | */ |
| mbed_official | 354:e67efb2aab0e | 1520 | HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel) |
| mbed_official | 354:e67efb2aab0e | 1521 | { |
| mbed_official | 354:e67efb2aab0e | 1522 | /* Check the parameters */ |
| mbed_official | 354:e67efb2aab0e | 1523 | assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); |
| mbed_official | 354:e67efb2aab0e | 1524 | |
| mbed_official | 354:e67efb2aab0e | 1525 | /* Enable the Input Capture channel */ |
| mbed_official | 354:e67efb2aab0e | 1526 | TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); |
| mbed_official | 354:e67efb2aab0e | 1527 | |
| mbed_official | 354:e67efb2aab0e | 1528 | /* Enable the Peripheral */ |
| mbed_official | 354:e67efb2aab0e | 1529 | __HAL_TIM_ENABLE(htim); |
| mbed_official | 354:e67efb2aab0e | 1530 | |
| mbed_official | 354:e67efb2aab0e | 1531 | /* Return function status */ |
| mbed_official | 354:e67efb2aab0e | 1532 | return HAL_OK; |
| mbed_official | 354:e67efb2aab0e | 1533 | } |
| mbed_official | 354:e67efb2aab0e | 1534 | |
| mbed_official | 354:e67efb2aab0e | 1535 | /** |
| mbed_official | 354:e67efb2aab0e | 1536 | * @brief Stops the TIM Input Capture measurement. |
| mbed_official | 354:e67efb2aab0e | 1537 | * @param htim : TIM handle |
| mbed_official | 354:e67efb2aab0e | 1538 | * @param Channel : TIM Channels to be disabled |
| mbed_official | 354:e67efb2aab0e | 1539 | * This parameter can be one of the following values: |
| mbed_official | 354:e67efb2aab0e | 1540 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| mbed_official | 354:e67efb2aab0e | 1541 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| mbed_official | 354:e67efb2aab0e | 1542 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
| mbed_official | 354:e67efb2aab0e | 1543 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
| mbed_official | 354:e67efb2aab0e | 1544 | * @retval HAL status |
| mbed_official | 354:e67efb2aab0e | 1545 | */ |
| mbed_official | 354:e67efb2aab0e | 1546 | HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) |
| mbed_official | 354:e67efb2aab0e | 1547 | { |
| mbed_official | 354:e67efb2aab0e | 1548 | /* Check the parameters */ |
| mbed_official | 354:e67efb2aab0e | 1549 | assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); |
| mbed_official | 354:e67efb2aab0e | 1550 | |
| mbed_official | 354:e67efb2aab0e | 1551 | /* Disable the Input Capture channel */ |
| mbed_official | 354:e67efb2aab0e | 1552 | TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); |
| mbed_official | 354:e67efb2aab0e | 1553 | |
| mbed_official | 354:e67efb2aab0e | 1554 | /* Disable the Peripheral */ |
| mbed_official | 354:e67efb2aab0e | 1555 | __HAL_TIM_DISABLE(htim); |
| mbed_official | 354:e67efb2aab0e | 1556 | |
| mbed_official | 354:e67efb2aab0e | 1557 | /* Return function status */ |
| mbed_official | 354:e67efb2aab0e | 1558 | return HAL_OK; |
| mbed_official | 354:e67efb2aab0e | 1559 | } |
| mbed_official | 354:e67efb2aab0e | 1560 | |
| mbed_official | 354:e67efb2aab0e | 1561 | /** |
| mbed_official | 354:e67efb2aab0e | 1562 | * @brief Starts the TIM Input Capture measurement in interrupt mode. |
| mbed_official | 354:e67efb2aab0e | 1563 | * @param htim : TIM Input Capture handle |
| mbed_official | 354:e67efb2aab0e | 1564 | * @param Channel : TIM Channels to be enabled |
| mbed_official | 354:e67efb2aab0e | 1565 | * This parameter can be one of the following values: |
| mbed_official | 354:e67efb2aab0e | 1566 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| mbed_official | 354:e67efb2aab0e | 1567 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| mbed_official | 354:e67efb2aab0e | 1568 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
| mbed_official | 354:e67efb2aab0e | 1569 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
| mbed_official | 354:e67efb2aab0e | 1570 | * @retval HAL status |
| mbed_official | 354:e67efb2aab0e | 1571 | */ |
| mbed_official | 354:e67efb2aab0e | 1572 | HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel) |
| mbed_official | 354:e67efb2aab0e | 1573 | { |
| mbed_official | 354:e67efb2aab0e | 1574 | /* Check the parameters */ |
| mbed_official | 354:e67efb2aab0e | 1575 | assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); |
| mbed_official | 354:e67efb2aab0e | 1576 | |
| mbed_official | 354:e67efb2aab0e | 1577 | switch (Channel) |
| mbed_official | 354:e67efb2aab0e | 1578 | { |
| mbed_official | 354:e67efb2aab0e | 1579 | case TIM_CHANNEL_1: |
| mbed_official | 354:e67efb2aab0e | 1580 | { |
| mbed_official | 354:e67efb2aab0e | 1581 | /* Enable the TIM Capture/Compare 1 interrupt */ |
| mbed_official | 354:e67efb2aab0e | 1582 | __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); |
| mbed_official | 354:e67efb2aab0e | 1583 | } |
| mbed_official | 354:e67efb2aab0e | 1584 | break; |
| mbed_official | 354:e67efb2aab0e | 1585 | |
| mbed_official | 354:e67efb2aab0e | 1586 | case TIM_CHANNEL_2: |
| mbed_official | 354:e67efb2aab0e | 1587 | { |
| mbed_official | 354:e67efb2aab0e | 1588 | /* Enable the TIM Capture/Compare 2 interrupt */ |
| mbed_official | 354:e67efb2aab0e | 1589 | __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); |
| mbed_official | 354:e67efb2aab0e | 1590 | } |
| mbed_official | 354:e67efb2aab0e | 1591 | break; |
| mbed_official | 354:e67efb2aab0e | 1592 | |
| mbed_official | 354:e67efb2aab0e | 1593 | case TIM_CHANNEL_3: |
| mbed_official | 354:e67efb2aab0e | 1594 | { |
| mbed_official | 354:e67efb2aab0e | 1595 | /* Enable the TIM Capture/Compare 3 interrupt */ |
| mbed_official | 354:e67efb2aab0e | 1596 | __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); |
| mbed_official | 354:e67efb2aab0e | 1597 | } |
| mbed_official | 354:e67efb2aab0e | 1598 | break; |
| mbed_official | 354:e67efb2aab0e | 1599 | |
| mbed_official | 354:e67efb2aab0e | 1600 | case TIM_CHANNEL_4: |
| mbed_official | 354:e67efb2aab0e | 1601 | { |
| mbed_official | 354:e67efb2aab0e | 1602 | /* Enable the TIM Capture/Compare 4 interrupt */ |
| mbed_official | 354:e67efb2aab0e | 1603 | __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); |
| mbed_official | 354:e67efb2aab0e | 1604 | } |
| mbed_official | 354:e67efb2aab0e | 1605 | break; |
| mbed_official | 354:e67efb2aab0e | 1606 | |
| mbed_official | 354:e67efb2aab0e | 1607 | default: |
| mbed_official | 354:e67efb2aab0e | 1608 | break; |
| mbed_official | 354:e67efb2aab0e | 1609 | } |
| mbed_official | 354:e67efb2aab0e | 1610 | /* Enable the Input Capture channel */ |
| mbed_official | 354:e67efb2aab0e | 1611 | TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); |
| mbed_official | 354:e67efb2aab0e | 1612 | |
| mbed_official | 354:e67efb2aab0e | 1613 | /* Enable the Peripheral */ |
| mbed_official | 354:e67efb2aab0e | 1614 | __HAL_TIM_ENABLE(htim); |
| mbed_official | 354:e67efb2aab0e | 1615 | |
| mbed_official | 354:e67efb2aab0e | 1616 | /* Return function status */ |
| mbed_official | 354:e67efb2aab0e | 1617 | return HAL_OK; |
| mbed_official | 354:e67efb2aab0e | 1618 | } |
| mbed_official | 354:e67efb2aab0e | 1619 | |
| mbed_official | 354:e67efb2aab0e | 1620 | /** |
| mbed_official | 354:e67efb2aab0e | 1621 | * @brief Stops the TIM Input Capture measurement in interrupt mode. |
| mbed_official | 354:e67efb2aab0e | 1622 | * @param htim : TIM handle |
| mbed_official | 354:e67efb2aab0e | 1623 | * @param Channel : TIM Channels to be disabled |
| mbed_official | 354:e67efb2aab0e | 1624 | * This parameter can be one of the following values: |
| mbed_official | 354:e67efb2aab0e | 1625 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| mbed_official | 354:e67efb2aab0e | 1626 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| mbed_official | 354:e67efb2aab0e | 1627 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
| mbed_official | 354:e67efb2aab0e | 1628 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
| mbed_official | 354:e67efb2aab0e | 1629 | * @retval HAL status |
| mbed_official | 354:e67efb2aab0e | 1630 | */ |
| mbed_official | 354:e67efb2aab0e | 1631 | HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) |
| mbed_official | 354:e67efb2aab0e | 1632 | { |
| mbed_official | 354:e67efb2aab0e | 1633 | /* Check the parameters */ |
| mbed_official | 354:e67efb2aab0e | 1634 | assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); |
| mbed_official | 354:e67efb2aab0e | 1635 | |
| mbed_official | 354:e67efb2aab0e | 1636 | switch (Channel) |
| mbed_official | 354:e67efb2aab0e | 1637 | { |
| mbed_official | 354:e67efb2aab0e | 1638 | case TIM_CHANNEL_1: |
| mbed_official | 354:e67efb2aab0e | 1639 | { |
| mbed_official | 354:e67efb2aab0e | 1640 | /* Disable the TIM Capture/Compare 1 interrupt */ |
| mbed_official | 354:e67efb2aab0e | 1641 | __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); |
| mbed_official | 354:e67efb2aab0e | 1642 | } |
| mbed_official | 354:e67efb2aab0e | 1643 | break; |
| mbed_official | 354:e67efb2aab0e | 1644 | |
| mbed_official | 354:e67efb2aab0e | 1645 | case TIM_CHANNEL_2: |
| mbed_official | 354:e67efb2aab0e | 1646 | { |
| mbed_official | 354:e67efb2aab0e | 1647 | /* Disable the TIM Capture/Compare 2 interrupt */ |
| mbed_official | 354:e67efb2aab0e | 1648 | __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); |
| mbed_official | 354:e67efb2aab0e | 1649 | } |
| mbed_official | 354:e67efb2aab0e | 1650 | break; |
| mbed_official | 354:e67efb2aab0e | 1651 | |
| mbed_official | 354:e67efb2aab0e | 1652 | case TIM_CHANNEL_3: |
| mbed_official | 354:e67efb2aab0e | 1653 | { |
| mbed_official | 354:e67efb2aab0e | 1654 | /* Disable the TIM Capture/Compare 3 interrupt */ |
| mbed_official | 354:e67efb2aab0e | 1655 | __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); |
| mbed_official | 354:e67efb2aab0e | 1656 | } |
| mbed_official | 354:e67efb2aab0e | 1657 | break; |
| mbed_official | 354:e67efb2aab0e | 1658 | |
| mbed_official | 354:e67efb2aab0e | 1659 | case TIM_CHANNEL_4: |
| mbed_official | 354:e67efb2aab0e | 1660 | { |
| mbed_official | 354:e67efb2aab0e | 1661 | /* Disable the TIM Capture/Compare 4 interrupt */ |
| mbed_official | 354:e67efb2aab0e | 1662 | __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); |
| mbed_official | 354:e67efb2aab0e | 1663 | } |
| mbed_official | 354:e67efb2aab0e | 1664 | break; |
| mbed_official | 354:e67efb2aab0e | 1665 | |
| mbed_official | 354:e67efb2aab0e | 1666 | default: |
| mbed_official | 354:e67efb2aab0e | 1667 | break; |
| mbed_official | 354:e67efb2aab0e | 1668 | } |
| mbed_official | 354:e67efb2aab0e | 1669 | |
| mbed_official | 354:e67efb2aab0e | 1670 | /* Disable the Input Capture channel */ |
| mbed_official | 354:e67efb2aab0e | 1671 | TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); |
| mbed_official | 354:e67efb2aab0e | 1672 | |
| mbed_official | 354:e67efb2aab0e | 1673 | /* Disable the Peripheral */ |
| mbed_official | 354:e67efb2aab0e | 1674 | __HAL_TIM_DISABLE(htim); |
| mbed_official | 354:e67efb2aab0e | 1675 | |
| mbed_official | 354:e67efb2aab0e | 1676 | /* Return function status */ |
| mbed_official | 354:e67efb2aab0e | 1677 | return HAL_OK; |
| mbed_official | 354:e67efb2aab0e | 1678 | } |
| mbed_official | 354:e67efb2aab0e | 1679 | |
| mbed_official | 354:e67efb2aab0e | 1680 | /** |
| mbed_official | 354:e67efb2aab0e | 1681 | * @brief Starts the TIM Input Capture measurement on in DMA mode. |
| mbed_official | 354:e67efb2aab0e | 1682 | * @param htim : TIM Input Capture handle |
| mbed_official | 354:e67efb2aab0e | 1683 | * @param Channel : TIM Channels to be enabled |
| mbed_official | 354:e67efb2aab0e | 1684 | * This parameter can be one of the following values: |
| mbed_official | 354:e67efb2aab0e | 1685 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| mbed_official | 354:e67efb2aab0e | 1686 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| mbed_official | 354:e67efb2aab0e | 1687 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
| mbed_official | 354:e67efb2aab0e | 1688 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
| mbed_official | 354:e67efb2aab0e | 1689 | * @param pData: The destination Buffer address. |
| mbed_official | 354:e67efb2aab0e | 1690 | * @param Length: The length of data to be transferred from TIM peripheral to memory. |
| mbed_official | 354:e67efb2aab0e | 1691 | * @retval HAL status |
| mbed_official | 354:e67efb2aab0e | 1692 | */ |
| mbed_official | 354:e67efb2aab0e | 1693 | HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) |
| mbed_official | 354:e67efb2aab0e | 1694 | { |
| mbed_official | 354:e67efb2aab0e | 1695 | /* Check the parameters */ |
| mbed_official | 354:e67efb2aab0e | 1696 | assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); |
| mbed_official | 354:e67efb2aab0e | 1697 | assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); |
| mbed_official | 354:e67efb2aab0e | 1698 | |
| mbed_official | 354:e67efb2aab0e | 1699 | if((htim->State == HAL_TIM_STATE_BUSY)) |
| mbed_official | 354:e67efb2aab0e | 1700 | { |
| mbed_official | 354:e67efb2aab0e | 1701 | return HAL_BUSY; |
| mbed_official | 354:e67efb2aab0e | 1702 | } |
| mbed_official | 354:e67efb2aab0e | 1703 | else if((htim->State == HAL_TIM_STATE_READY)) |
| mbed_official | 354:e67efb2aab0e | 1704 | { |
| mbed_official | 354:e67efb2aab0e | 1705 | if((pData == 0 ) && (Length > 0)) |
| mbed_official | 354:e67efb2aab0e | 1706 | { |
| mbed_official | 354:e67efb2aab0e | 1707 | return HAL_ERROR; |
| mbed_official | 354:e67efb2aab0e | 1708 | } |
| mbed_official | 354:e67efb2aab0e | 1709 | else |
| mbed_official | 354:e67efb2aab0e | 1710 | { |
| mbed_official | 354:e67efb2aab0e | 1711 | htim->State = HAL_TIM_STATE_BUSY; |
| mbed_official | 354:e67efb2aab0e | 1712 | } |
| mbed_official | 354:e67efb2aab0e | 1713 | } |
| mbed_official | 354:e67efb2aab0e | 1714 | else |
| mbed_official | 354:e67efb2aab0e | 1715 | { |
| mbed_official | 354:e67efb2aab0e | 1716 | return HAL_ERROR; |
| mbed_official | 354:e67efb2aab0e | 1717 | } |
| mbed_official | 354:e67efb2aab0e | 1718 | |
| mbed_official | 354:e67efb2aab0e | 1719 | switch (Channel) |
| mbed_official | 354:e67efb2aab0e | 1720 | { |
| mbed_official | 354:e67efb2aab0e | 1721 | case TIM_CHANNEL_1: |
| mbed_official | 354:e67efb2aab0e | 1722 | { |
| mbed_official | 354:e67efb2aab0e | 1723 | /* Set the DMA Period elapsed callback */ |
| mbed_official | 354:e67efb2aab0e | 1724 | htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; |
| mbed_official | 354:e67efb2aab0e | 1725 | |
| mbed_official | 354:e67efb2aab0e | 1726 | /* Set the DMA error callback */ |
| mbed_official | 354:e67efb2aab0e | 1727 | htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; |
| mbed_official | 354:e67efb2aab0e | 1728 | |
| mbed_official | 354:e67efb2aab0e | 1729 | /* Enable the DMA channel */ |
| mbed_official | 354:e67efb2aab0e | 1730 | HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length); |
| mbed_official | 354:e67efb2aab0e | 1731 | |
| mbed_official | 354:e67efb2aab0e | 1732 | /* Enable the TIM Capture/Compare 1 DMA request */ |
| mbed_official | 354:e67efb2aab0e | 1733 | __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); |
| mbed_official | 354:e67efb2aab0e | 1734 | } |
| mbed_official | 354:e67efb2aab0e | 1735 | break; |
| mbed_official | 354:e67efb2aab0e | 1736 | |
| mbed_official | 354:e67efb2aab0e | 1737 | case TIM_CHANNEL_2: |
| mbed_official | 354:e67efb2aab0e | 1738 | { |
| mbed_official | 354:e67efb2aab0e | 1739 | /* Set the DMA Period elapsed callback */ |
| mbed_official | 354:e67efb2aab0e | 1740 | htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; |
| mbed_official | 354:e67efb2aab0e | 1741 | |
| mbed_official | 354:e67efb2aab0e | 1742 | /* Set the DMA error callback */ |
| mbed_official | 354:e67efb2aab0e | 1743 | htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; |
| mbed_official | 354:e67efb2aab0e | 1744 | |
| mbed_official | 354:e67efb2aab0e | 1745 | /* Enable the DMA channel */ |
| mbed_official | 354:e67efb2aab0e | 1746 | HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length); |
| mbed_official | 354:e67efb2aab0e | 1747 | |
| mbed_official | 354:e67efb2aab0e | 1748 | /* Enable the TIM Capture/Compare 2 DMA request */ |
| mbed_official | 354:e67efb2aab0e | 1749 | __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); |
| mbed_official | 354:e67efb2aab0e | 1750 | } |
| mbed_official | 354:e67efb2aab0e | 1751 | break; |
| mbed_official | 354:e67efb2aab0e | 1752 | |
| mbed_official | 354:e67efb2aab0e | 1753 | case TIM_CHANNEL_3: |
| mbed_official | 354:e67efb2aab0e | 1754 | { |
| mbed_official | 354:e67efb2aab0e | 1755 | /* Set the DMA Period elapsed callback */ |
| mbed_official | 354:e67efb2aab0e | 1756 | htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt; |
| mbed_official | 354:e67efb2aab0e | 1757 | |
| mbed_official | 354:e67efb2aab0e | 1758 | /* Set the DMA error callback */ |
| mbed_official | 354:e67efb2aab0e | 1759 | htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; |
| mbed_official | 354:e67efb2aab0e | 1760 | |
| mbed_official | 354:e67efb2aab0e | 1761 | /* Enable the DMA channel */ |
| mbed_official | 354:e67efb2aab0e | 1762 | HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length); |
| mbed_official | 354:e67efb2aab0e | 1763 | |
| mbed_official | 354:e67efb2aab0e | 1764 | /* Enable the TIM Capture/Compare 3 DMA request */ |
| mbed_official | 354:e67efb2aab0e | 1765 | __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); |
| mbed_official | 354:e67efb2aab0e | 1766 | } |
| mbed_official | 354:e67efb2aab0e | 1767 | break; |
| mbed_official | 354:e67efb2aab0e | 1768 | |
| mbed_official | 354:e67efb2aab0e | 1769 | case TIM_CHANNEL_4: |
| mbed_official | 354:e67efb2aab0e | 1770 | { |
| mbed_official | 354:e67efb2aab0e | 1771 | /* Set the DMA Period elapsed callback */ |
| mbed_official | 354:e67efb2aab0e | 1772 | htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt; |
| mbed_official | 354:e67efb2aab0e | 1773 | |
| mbed_official | 354:e67efb2aab0e | 1774 | /* Set the DMA error callback */ |
| mbed_official | 354:e67efb2aab0e | 1775 | htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; |
| mbed_official | 354:e67efb2aab0e | 1776 | |
| mbed_official | 354:e67efb2aab0e | 1777 | /* Enable the DMA channel */ |
| mbed_official | 354:e67efb2aab0e | 1778 | HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length); |
| mbed_official | 354:e67efb2aab0e | 1779 | |
| mbed_official | 354:e67efb2aab0e | 1780 | /* Enable the TIM Capture/Compare 4 DMA request */ |
| mbed_official | 354:e67efb2aab0e | 1781 | __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); |
| mbed_official | 354:e67efb2aab0e | 1782 | } |
| mbed_official | 354:e67efb2aab0e | 1783 | break; |
| mbed_official | 354:e67efb2aab0e | 1784 | |
| mbed_official | 354:e67efb2aab0e | 1785 | default: |
| mbed_official | 354:e67efb2aab0e | 1786 | break; |
| mbed_official | 354:e67efb2aab0e | 1787 | } |
| mbed_official | 354:e67efb2aab0e | 1788 | |
| mbed_official | 354:e67efb2aab0e | 1789 | /* Enable the Input Capture channel */ |
| mbed_official | 354:e67efb2aab0e | 1790 | TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); |
| mbed_official | 354:e67efb2aab0e | 1791 | |
| mbed_official | 354:e67efb2aab0e | 1792 | /* Enable the Peripheral */ |
| mbed_official | 354:e67efb2aab0e | 1793 | __HAL_TIM_ENABLE(htim); |
| mbed_official | 354:e67efb2aab0e | 1794 | |
| mbed_official | 354:e67efb2aab0e | 1795 | /* Return function status */ |
| mbed_official | 354:e67efb2aab0e | 1796 | return HAL_OK; |
| mbed_official | 354:e67efb2aab0e | 1797 | } |
| mbed_official | 354:e67efb2aab0e | 1798 | |
| mbed_official | 354:e67efb2aab0e | 1799 | /** |
| mbed_official | 354:e67efb2aab0e | 1800 | * @brief Stops the TIM Input Capture measurement on in DMA mode. |
| mbed_official | 354:e67efb2aab0e | 1801 | * @param htim : TIM Input Capture handle |
| mbed_official | 354:e67efb2aab0e | 1802 | * @param Channel : TIM Channels to be disabled |
| mbed_official | 354:e67efb2aab0e | 1803 | * This parameter can be one of the following values: |
| mbed_official | 354:e67efb2aab0e | 1804 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| mbed_official | 354:e67efb2aab0e | 1805 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| mbed_official | 354:e67efb2aab0e | 1806 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
| mbed_official | 354:e67efb2aab0e | 1807 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
| mbed_official | 354:e67efb2aab0e | 1808 | * @retval HAL status |
| mbed_official | 354:e67efb2aab0e | 1809 | */ |
| mbed_official | 354:e67efb2aab0e | 1810 | HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) |
| mbed_official | 354:e67efb2aab0e | 1811 | { |
| mbed_official | 354:e67efb2aab0e | 1812 | /* Check the parameters */ |
| mbed_official | 354:e67efb2aab0e | 1813 | assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); |
| mbed_official | 354:e67efb2aab0e | 1814 | assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); |
| mbed_official | 354:e67efb2aab0e | 1815 | |
| mbed_official | 354:e67efb2aab0e | 1816 | switch (Channel) |
| mbed_official | 354:e67efb2aab0e | 1817 | { |
| mbed_official | 354:e67efb2aab0e | 1818 | case TIM_CHANNEL_1: |
| mbed_official | 354:e67efb2aab0e | 1819 | { |
| mbed_official | 354:e67efb2aab0e | 1820 | /* Disable the TIM Capture/Compare 1 DMA request */ |
| mbed_official | 354:e67efb2aab0e | 1821 | __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); |
| mbed_official | 354:e67efb2aab0e | 1822 | } |
| mbed_official | 354:e67efb2aab0e | 1823 | break; |
| mbed_official | 354:e67efb2aab0e | 1824 | |
| mbed_official | 354:e67efb2aab0e | 1825 | case TIM_CHANNEL_2: |
| mbed_official | 354:e67efb2aab0e | 1826 | { |
| mbed_official | 354:e67efb2aab0e | 1827 | /* Disable the TIM Capture/Compare 2 DMA request */ |
| mbed_official | 354:e67efb2aab0e | 1828 | __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); |
| mbed_official | 354:e67efb2aab0e | 1829 | } |
| mbed_official | 354:e67efb2aab0e | 1830 | break; |
| mbed_official | 354:e67efb2aab0e | 1831 | |
| mbed_official | 354:e67efb2aab0e | 1832 | case TIM_CHANNEL_3: |
| mbed_official | 354:e67efb2aab0e | 1833 | { |
| mbed_official | 354:e67efb2aab0e | 1834 | /* Disable the TIM Capture/Compare 3 DMA request */ |
| mbed_official | 354:e67efb2aab0e | 1835 | __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); |
| mbed_official | 354:e67efb2aab0e | 1836 | } |
| mbed_official | 354:e67efb2aab0e | 1837 | break; |
| mbed_official | 354:e67efb2aab0e | 1838 | |
| mbed_official | 354:e67efb2aab0e | 1839 | case TIM_CHANNEL_4: |
| mbed_official | 354:e67efb2aab0e | 1840 | { |
| mbed_official | 354:e67efb2aab0e | 1841 | /* Disable the TIM Capture/Compare 4 DMA request */ |
| mbed_official | 354:e67efb2aab0e | 1842 | __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); |
| mbed_official | 354:e67efb2aab0e | 1843 | } |
| mbed_official | 354:e67efb2aab0e | 1844 | break; |
| mbed_official | 354:e67efb2aab0e | 1845 | |
| mbed_official | 354:e67efb2aab0e | 1846 | default: |
| mbed_official | 354:e67efb2aab0e | 1847 | break; |
| mbed_official | 354:e67efb2aab0e | 1848 | } |
| mbed_official | 354:e67efb2aab0e | 1849 | |
| mbed_official | 354:e67efb2aab0e | 1850 | /* Disable the Input Capture channel */ |
| mbed_official | 354:e67efb2aab0e | 1851 | TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); |
| mbed_official | 354:e67efb2aab0e | 1852 | |
| mbed_official | 354:e67efb2aab0e | 1853 | /* Disable the Peripheral */ |
| mbed_official | 354:e67efb2aab0e | 1854 | __HAL_TIM_DISABLE(htim); |
| mbed_official | 354:e67efb2aab0e | 1855 | |
| mbed_official | 354:e67efb2aab0e | 1856 | /* Change the htim state */ |
| mbed_official | 354:e67efb2aab0e | 1857 | htim->State = HAL_TIM_STATE_READY; |
| mbed_official | 354:e67efb2aab0e | 1858 | |
| mbed_official | 354:e67efb2aab0e | 1859 | /* Return function status */ |
| mbed_official | 354:e67efb2aab0e | 1860 | return HAL_OK; |
| mbed_official | 354:e67efb2aab0e | 1861 | } |
| mbed_official | 354:e67efb2aab0e | 1862 | /** |
| mbed_official | 354:e67efb2aab0e | 1863 | * @} |
| mbed_official | 354:e67efb2aab0e | 1864 | */ |
| mbed_official | 354:e67efb2aab0e | 1865 | |
| mbed_official | 354:e67efb2aab0e | 1866 | /** @defgroup TIM_Exported_Functions_Group5 Time One Pulse functions |
| mbed_official | 354:e67efb2aab0e | 1867 | * @brief Time One Pulse functions |
| mbed_official | 354:e67efb2aab0e | 1868 | * |
| mbed_official | 354:e67efb2aab0e | 1869 | @verbatim |
| mbed_official | 354:e67efb2aab0e | 1870 | ============================================================================== |
| mbed_official | 354:e67efb2aab0e | 1871 | ##### Time One Pulse functions ##### |
| mbed_official | 354:e67efb2aab0e | 1872 | ============================================================================== |
| mbed_official | 354:e67efb2aab0e | 1873 | [..] |
| mbed_official | 354:e67efb2aab0e | 1874 | This section provides functions allowing to: |
| mbed_official | 354:e67efb2aab0e | 1875 | (+) Initialize and configure the TIM One Pulse. |
| mbed_official | 354:e67efb2aab0e | 1876 | (+) De-initialize the TIM One Pulse. |
| mbed_official | 354:e67efb2aab0e | 1877 | (+) Start the Time One Pulse. |
| mbed_official | 354:e67efb2aab0e | 1878 | (+) Stop the Time One Pulse. |
| mbed_official | 354:e67efb2aab0e | 1879 | (+) Start the Time One Pulse and enable interrupt. |
| mbed_official | 354:e67efb2aab0e | 1880 | (+) Stop the Time One Pulse and disable interrupt. |
| mbed_official | 354:e67efb2aab0e | 1881 | (+) Start the Time One Pulse and enable DMA transfer. |
| mbed_official | 354:e67efb2aab0e | 1882 | (+) Stop the Time One Pulse and disable DMA transfer. |
| mbed_official | 354:e67efb2aab0e | 1883 | |
| mbed_official | 354:e67efb2aab0e | 1884 | @endverbatim |
| mbed_official | 354:e67efb2aab0e | 1885 | * @{ |
| mbed_official | 354:e67efb2aab0e | 1886 | */ |
| mbed_official | 354:e67efb2aab0e | 1887 | /** |
| mbed_official | 354:e67efb2aab0e | 1888 | * @brief Initializes the TIM One Pulse Time Base according to the specified |
| mbed_official | 354:e67efb2aab0e | 1889 | * parameters in the TIM_HandleTypeDef and create the associated handle. |
| mbed_official | 354:e67efb2aab0e | 1890 | * @param htim: TIM OnePulse handle |
| mbed_official | 354:e67efb2aab0e | 1891 | * @param OnePulseMode: Select the One pulse mode. |
| mbed_official | 354:e67efb2aab0e | 1892 | * This parameter can be one of the following values: |
| mbed_official | 354:e67efb2aab0e | 1893 | * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated. |
| mbed_official | 354:e67efb2aab0e | 1894 | * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses wil be generated. |
| mbed_official | 354:e67efb2aab0e | 1895 | * @retval HAL status |
| mbed_official | 354:e67efb2aab0e | 1896 | */ |
| mbed_official | 354:e67efb2aab0e | 1897 | HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode) |
| mbed_official | 354:e67efb2aab0e | 1898 | { |
| mbed_official | 354:e67efb2aab0e | 1899 | /* Check the TIM handle allocation */ |
| mbed_official | 354:e67efb2aab0e | 1900 | if(htim == HAL_NULL) |
| mbed_official | 354:e67efb2aab0e | 1901 | { |
| mbed_official | 354:e67efb2aab0e | 1902 | return HAL_ERROR; |
| mbed_official | 354:e67efb2aab0e | 1903 | } |
| mbed_official | 354:e67efb2aab0e | 1904 | |
| mbed_official | 354:e67efb2aab0e | 1905 | /* Check the parameters */ |
| mbed_official | 354:e67efb2aab0e | 1906 | assert_param(IS_TIM_INSTANCE(htim->Instance)); |
| mbed_official | 354:e67efb2aab0e | 1907 | assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); |
| mbed_official | 354:e67efb2aab0e | 1908 | assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); |
| mbed_official | 354:e67efb2aab0e | 1909 | assert_param(IS_TIM_OPM_MODE(OnePulseMode)); |
| mbed_official | 354:e67efb2aab0e | 1910 | |
| mbed_official | 354:e67efb2aab0e | 1911 | if(htim->State == HAL_TIM_STATE_RESET) |
| mbed_official | 354:e67efb2aab0e | 1912 | { |
| mbed_official | 354:e67efb2aab0e | 1913 | /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ |
| mbed_official | 354:e67efb2aab0e | 1914 | HAL_TIM_OnePulse_MspInit(htim); |
| mbed_official | 354:e67efb2aab0e | 1915 | } |
| mbed_official | 354:e67efb2aab0e | 1916 | |
| mbed_official | 354:e67efb2aab0e | 1917 | /* Set the TIM state */ |
| mbed_official | 354:e67efb2aab0e | 1918 | htim->State= HAL_TIM_STATE_BUSY; |
| mbed_official | 354:e67efb2aab0e | 1919 | |
| mbed_official | 354:e67efb2aab0e | 1920 | /* Configure the Time base in the One Pulse Mode */ |
| mbed_official | 354:e67efb2aab0e | 1921 | TIM_Base_SetConfig(htim->Instance, &htim->Init); |
| mbed_official | 354:e67efb2aab0e | 1922 | |
| mbed_official | 354:e67efb2aab0e | 1923 | /* Reset the OPM Bit */ |
| mbed_official | 354:e67efb2aab0e | 1924 | htim->Instance->CR1 &= ~TIM_CR1_OPM; |
| mbed_official | 354:e67efb2aab0e | 1925 | |
| mbed_official | 354:e67efb2aab0e | 1926 | /* Configure the OPM Mode */ |
| mbed_official | 354:e67efb2aab0e | 1927 | htim->Instance->CR1 |= OnePulseMode; |
| mbed_official | 354:e67efb2aab0e | 1928 | |
| mbed_official | 354:e67efb2aab0e | 1929 | /* Initialize the TIM state*/ |
| mbed_official | 354:e67efb2aab0e | 1930 | htim->State= HAL_TIM_STATE_READY; |
| mbed_official | 354:e67efb2aab0e | 1931 | |
| mbed_official | 354:e67efb2aab0e | 1932 | return HAL_OK; |
| mbed_official | 354:e67efb2aab0e | 1933 | } |
| mbed_official | 354:e67efb2aab0e | 1934 | |
| mbed_official | 354:e67efb2aab0e | 1935 | /** |
| mbed_official | 354:e67efb2aab0e | 1936 | * @brief DeInitializes the TIM One Pulse |
| mbed_official | 354:e67efb2aab0e | 1937 | * @param htim: TIM One Pulse handle |
| mbed_official | 354:e67efb2aab0e | 1938 | * @retval HAL status |
| mbed_official | 354:e67efb2aab0e | 1939 | */ |
| mbed_official | 354:e67efb2aab0e | 1940 | HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim) |
| mbed_official | 354:e67efb2aab0e | 1941 | { |
| mbed_official | 354:e67efb2aab0e | 1942 | /* Check the parameters */ |
| mbed_official | 354:e67efb2aab0e | 1943 | assert_param(IS_TIM_INSTANCE(htim->Instance)); |
| mbed_official | 354:e67efb2aab0e | 1944 | |
| mbed_official | 354:e67efb2aab0e | 1945 | htim->State = HAL_TIM_STATE_BUSY; |
| mbed_official | 354:e67efb2aab0e | 1946 | |
| mbed_official | 354:e67efb2aab0e | 1947 | /* Disable the TIM Peripheral Clock */ |
| mbed_official | 354:e67efb2aab0e | 1948 | __HAL_TIM_DISABLE(htim); |
| mbed_official | 354:e67efb2aab0e | 1949 | |
| mbed_official | 354:e67efb2aab0e | 1950 | /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ |
| mbed_official | 354:e67efb2aab0e | 1951 | HAL_TIM_OnePulse_MspDeInit(htim); |
| mbed_official | 354:e67efb2aab0e | 1952 | |
| mbed_official | 354:e67efb2aab0e | 1953 | /* Change TIM state */ |
| mbed_official | 354:e67efb2aab0e | 1954 | htim->State = HAL_TIM_STATE_RESET; |
| mbed_official | 354:e67efb2aab0e | 1955 | |
| mbed_official | 354:e67efb2aab0e | 1956 | /* Release Lock */ |
| mbed_official | 354:e67efb2aab0e | 1957 | __HAL_UNLOCK(htim); |
| mbed_official | 354:e67efb2aab0e | 1958 | |
| mbed_official | 354:e67efb2aab0e | 1959 | return HAL_OK; |
| mbed_official | 354:e67efb2aab0e | 1960 | } |
| mbed_official | 354:e67efb2aab0e | 1961 | |
| mbed_official | 354:e67efb2aab0e | 1962 | /** |
| mbed_official | 354:e67efb2aab0e | 1963 | * @brief Initializes the TIM One Pulse MSP. |
| mbed_official | 354:e67efb2aab0e | 1964 | * @param htim: TIM handle |
| mbed_official | 354:e67efb2aab0e | 1965 | * @retval None |
| mbed_official | 354:e67efb2aab0e | 1966 | */ |
| mbed_official | 354:e67efb2aab0e | 1967 | __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim) |
| mbed_official | 354:e67efb2aab0e | 1968 | { |
| mbed_official | 354:e67efb2aab0e | 1969 | /* NOTE : This function Should not be modified, when the callback is needed, |
| mbed_official | 354:e67efb2aab0e | 1970 | the HAL_TIM_OnePulse_MspInit could be implemented in the user file |
| mbed_official | 354:e67efb2aab0e | 1971 | */ |
| mbed_official | 354:e67efb2aab0e | 1972 | } |
| mbed_official | 354:e67efb2aab0e | 1973 | |
| mbed_official | 354:e67efb2aab0e | 1974 | /** |
| mbed_official | 354:e67efb2aab0e | 1975 | * @brief DeInitializes TIM One Pulse MSP. |
| mbed_official | 354:e67efb2aab0e | 1976 | * @param htim: TIM handle |
| mbed_official | 354:e67efb2aab0e | 1977 | * @retval None |
| mbed_official | 354:e67efb2aab0e | 1978 | */ |
| mbed_official | 354:e67efb2aab0e | 1979 | __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim) |
| mbed_official | 354:e67efb2aab0e | 1980 | { |
| mbed_official | 354:e67efb2aab0e | 1981 | /* NOTE : This function Should not be modified, when the callback is needed, |
| mbed_official | 354:e67efb2aab0e | 1982 | the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file |
| mbed_official | 354:e67efb2aab0e | 1983 | */ |
| mbed_official | 354:e67efb2aab0e | 1984 | } |
| mbed_official | 354:e67efb2aab0e | 1985 | |
| mbed_official | 354:e67efb2aab0e | 1986 | /** |
| mbed_official | 354:e67efb2aab0e | 1987 | * @brief Starts the TIM One Pulse signal generation. |
| mbed_official | 354:e67efb2aab0e | 1988 | * @param htim : TIM One Pulse handle |
| mbed_official | 354:e67efb2aab0e | 1989 | * @param OutputChannel : TIM Channels to be enabled |
| mbed_official | 354:e67efb2aab0e | 1990 | * This parameter can be one of the following values: |
| mbed_official | 354:e67efb2aab0e | 1991 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| mbed_official | 354:e67efb2aab0e | 1992 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| mbed_official | 354:e67efb2aab0e | 1993 | * @retval HAL status |
| mbed_official | 354:e67efb2aab0e | 1994 | */ |
| mbed_official | 354:e67efb2aab0e | 1995 | HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) |
| mbed_official | 354:e67efb2aab0e | 1996 | { |
| mbed_official | 354:e67efb2aab0e | 1997 | /* Enable the Capture compare and the Input Capture channels |
| mbed_official | 354:e67efb2aab0e | 1998 | (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) |
| mbed_official | 354:e67efb2aab0e | 1999 | if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and |
| mbed_official | 354:e67efb2aab0e | 2000 | if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output |
| mbed_official | 354:e67efb2aab0e | 2001 | in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together |
| mbed_official | 354:e67efb2aab0e | 2002 | |
| mbed_official | 354:e67efb2aab0e | 2003 | No need to enable the counter, it's enabled automatically by hardware |
| mbed_official | 354:e67efb2aab0e | 2004 | (the counter starts in response to a stimulus and generate a pulse */ |
| mbed_official | 354:e67efb2aab0e | 2005 | |
| mbed_official | 354:e67efb2aab0e | 2006 | TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); |
| mbed_official | 354:e67efb2aab0e | 2007 | TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); |
| mbed_official | 354:e67efb2aab0e | 2008 | |
| mbed_official | 354:e67efb2aab0e | 2009 | /* Return function status */ |
| mbed_official | 354:e67efb2aab0e | 2010 | return HAL_OK; |
| mbed_official | 354:e67efb2aab0e | 2011 | } |
| mbed_official | 354:e67efb2aab0e | 2012 | |
| mbed_official | 354:e67efb2aab0e | 2013 | /** |
| mbed_official | 354:e67efb2aab0e | 2014 | * @brief Stops the TIM One Pulse signal generation. |
| mbed_official | 354:e67efb2aab0e | 2015 | * @param htim : TIM One Pulse handle |
| mbed_official | 354:e67efb2aab0e | 2016 | * @param OutputChannel : TIM Channels to be disable |
| mbed_official | 354:e67efb2aab0e | 2017 | * This parameter can be one of the following values: |
| mbed_official | 354:e67efb2aab0e | 2018 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| mbed_official | 354:e67efb2aab0e | 2019 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| mbed_official | 354:e67efb2aab0e | 2020 | * @retval HAL status |
| mbed_official | 354:e67efb2aab0e | 2021 | */ |
| mbed_official | 354:e67efb2aab0e | 2022 | HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel) |
| mbed_official | 354:e67efb2aab0e | 2023 | { |
| mbed_official | 354:e67efb2aab0e | 2024 | /* Disable the Capture compare and the Input Capture channels |
| mbed_official | 354:e67efb2aab0e | 2025 | (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) |
| mbed_official | 354:e67efb2aab0e | 2026 | if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and |
| mbed_official | 354:e67efb2aab0e | 2027 | if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output |
| mbed_official | 354:e67efb2aab0e | 2028 | in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ |
| mbed_official | 354:e67efb2aab0e | 2029 | |
| mbed_official | 354:e67efb2aab0e | 2030 | TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); |
| mbed_official | 354:e67efb2aab0e | 2031 | TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); |
| mbed_official | 354:e67efb2aab0e | 2032 | |
| mbed_official | 354:e67efb2aab0e | 2033 | /* Disable the Peripheral */ |
| mbed_official | 354:e67efb2aab0e | 2034 | __HAL_TIM_DISABLE(htim); |
| mbed_official | 354:e67efb2aab0e | 2035 | |
| mbed_official | 354:e67efb2aab0e | 2036 | /* Return function status */ |
| mbed_official | 354:e67efb2aab0e | 2037 | return HAL_OK; |
| mbed_official | 354:e67efb2aab0e | 2038 | } |
| mbed_official | 354:e67efb2aab0e | 2039 | |
| mbed_official | 354:e67efb2aab0e | 2040 | /** |
| mbed_official | 354:e67efb2aab0e | 2041 | * @brief Starts the TIM One Pulse signal generation in interrupt mode. |
| mbed_official | 354:e67efb2aab0e | 2042 | * @param htim : TIM One Pulse handle |
| mbed_official | 354:e67efb2aab0e | 2043 | * @param OutputChannel : TIM Channels to be enabled |
| mbed_official | 354:e67efb2aab0e | 2044 | * This parameter can be one of the following values: |
| mbed_official | 354:e67efb2aab0e | 2045 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| mbed_official | 354:e67efb2aab0e | 2046 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| mbed_official | 354:e67efb2aab0e | 2047 | * @retval HAL status |
| mbed_official | 354:e67efb2aab0e | 2048 | */ |
| mbed_official | 354:e67efb2aab0e | 2049 | HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) |
| mbed_official | 354:e67efb2aab0e | 2050 | { |
| mbed_official | 354:e67efb2aab0e | 2051 | /* Enable the Capture compare and the Input Capture channels |
| mbed_official | 354:e67efb2aab0e | 2052 | (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) |
| mbed_official | 354:e67efb2aab0e | 2053 | if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and |
| mbed_official | 354:e67efb2aab0e | 2054 | if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output |
| mbed_official | 354:e67efb2aab0e | 2055 | in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together |
| mbed_official | 354:e67efb2aab0e | 2056 | |
| mbed_official | 354:e67efb2aab0e | 2057 | No need to enable the counter, it's enabled automatically by hardware |
| mbed_official | 354:e67efb2aab0e | 2058 | (the counter starts in response to a stimulus and generate a pulse */ |
| mbed_official | 354:e67efb2aab0e | 2059 | |
| mbed_official | 354:e67efb2aab0e | 2060 | /* Enable the TIM Capture/Compare 1 interrupt */ |
| mbed_official | 354:e67efb2aab0e | 2061 | __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); |
| mbed_official | 354:e67efb2aab0e | 2062 | |
| mbed_official | 354:e67efb2aab0e | 2063 | /* Enable the TIM Capture/Compare 2 interrupt */ |
| mbed_official | 354:e67efb2aab0e | 2064 | __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); |
| mbed_official | 354:e67efb2aab0e | 2065 | |
| mbed_official | 354:e67efb2aab0e | 2066 | TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); |
| mbed_official | 354:e67efb2aab0e | 2067 | TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); |
| mbed_official | 354:e67efb2aab0e | 2068 | |
| mbed_official | 354:e67efb2aab0e | 2069 | /* Return function status */ |
| mbed_official | 354:e67efb2aab0e | 2070 | return HAL_OK; |
| mbed_official | 354:e67efb2aab0e | 2071 | } |
| mbed_official | 354:e67efb2aab0e | 2072 | |
| mbed_official | 354:e67efb2aab0e | 2073 | /** |
| mbed_official | 354:e67efb2aab0e | 2074 | * @brief Stops the TIM One Pulse signal generation in interrupt mode. |
| mbed_official | 354:e67efb2aab0e | 2075 | * @param htim : TIM One Pulse handle |
| mbed_official | 354:e67efb2aab0e | 2076 | * @param OutputChannel : TIM Channels to be enabled |
| mbed_official | 354:e67efb2aab0e | 2077 | * This parameter can be one of the following values: |
| mbed_official | 354:e67efb2aab0e | 2078 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| mbed_official | 354:e67efb2aab0e | 2079 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| mbed_official | 354:e67efb2aab0e | 2080 | * @retval HAL status |
| mbed_official | 354:e67efb2aab0e | 2081 | */ |
| mbed_official | 354:e67efb2aab0e | 2082 | HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) |
| mbed_official | 354:e67efb2aab0e | 2083 | { |
| mbed_official | 354:e67efb2aab0e | 2084 | /* Disable the TIM Capture/Compare 1 interrupt */ |
| mbed_official | 354:e67efb2aab0e | 2085 | __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); |
| mbed_official | 354:e67efb2aab0e | 2086 | |
| mbed_official | 354:e67efb2aab0e | 2087 | /* Disable the TIM Capture/Compare 2 interrupt */ |
| mbed_official | 354:e67efb2aab0e | 2088 | __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); |
| mbed_official | 354:e67efb2aab0e | 2089 | |
| mbed_official | 354:e67efb2aab0e | 2090 | /* Disable the Capture compare and the Input Capture channels |
| mbed_official | 354:e67efb2aab0e | 2091 | (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) |
| mbed_official | 354:e67efb2aab0e | 2092 | if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and |
| mbed_official | 354:e67efb2aab0e | 2093 | if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output |
| mbed_official | 354:e67efb2aab0e | 2094 | in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ |
| mbed_official | 354:e67efb2aab0e | 2095 | TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); |
| mbed_official | 354:e67efb2aab0e | 2096 | TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); |
| mbed_official | 354:e67efb2aab0e | 2097 | |
| mbed_official | 354:e67efb2aab0e | 2098 | /* Disable the Peripheral */ |
| mbed_official | 354:e67efb2aab0e | 2099 | __HAL_TIM_DISABLE(htim); |
| mbed_official | 354:e67efb2aab0e | 2100 | |
| mbed_official | 354:e67efb2aab0e | 2101 | /* Return function status */ |
| mbed_official | 354:e67efb2aab0e | 2102 | return HAL_OK; |
| mbed_official | 354:e67efb2aab0e | 2103 | } |
| mbed_official | 354:e67efb2aab0e | 2104 | |
| mbed_official | 354:e67efb2aab0e | 2105 | /** |
| mbed_official | 354:e67efb2aab0e | 2106 | * @} |
| mbed_official | 354:e67efb2aab0e | 2107 | */ |
| mbed_official | 354:e67efb2aab0e | 2108 | |
| mbed_official | 354:e67efb2aab0e | 2109 | /** @defgroup TIM_Exported_Functions_Group6 Time Encoder functions |
| mbed_official | 354:e67efb2aab0e | 2110 | * @brief Time Encoder functions |
| mbed_official | 354:e67efb2aab0e | 2111 | * |
| mbed_official | 354:e67efb2aab0e | 2112 | @verbatim |
| mbed_official | 354:e67efb2aab0e | 2113 | ============================================================================== |
| mbed_official | 354:e67efb2aab0e | 2114 | ##### Time Encoder functions ##### |
| mbed_official | 354:e67efb2aab0e | 2115 | ============================================================================== |
| mbed_official | 354:e67efb2aab0e | 2116 | [..] |
| mbed_official | 354:e67efb2aab0e | 2117 | This section provides functions allowing to: |
| mbed_official | 354:e67efb2aab0e | 2118 | (+) Initialize and configure the TIM Encoder. |
| mbed_official | 354:e67efb2aab0e | 2119 | (+) De-initialize the TIM Encoder. |
| mbed_official | 354:e67efb2aab0e | 2120 | (+) Start the Time Encoder. |
| mbed_official | 354:e67efb2aab0e | 2121 | (+) Stop the Time Encoder. |
| mbed_official | 354:e67efb2aab0e | 2122 | (+) Start the Time Encoder and enable interrupt. |
| mbed_official | 354:e67efb2aab0e | 2123 | (+) Stop the Time Encoder and disable interrupt. |
| mbed_official | 354:e67efb2aab0e | 2124 | (+) Start the Time Encoder and enable DMA transfer. |
| mbed_official | 354:e67efb2aab0e | 2125 | (+) Stop the Time Encoder and disable DMA transfer. |
| mbed_official | 354:e67efb2aab0e | 2126 | |
| mbed_official | 354:e67efb2aab0e | 2127 | @endverbatim |
| mbed_official | 354:e67efb2aab0e | 2128 | * @{ |
| mbed_official | 354:e67efb2aab0e | 2129 | */ |
| mbed_official | 354:e67efb2aab0e | 2130 | /** |
| mbed_official | 354:e67efb2aab0e | 2131 | * @brief Initializes the TIM Encoder Interface and create the associated handle. |
| mbed_official | 354:e67efb2aab0e | 2132 | * @param htim: TIM Encoder Interface handle |
| mbed_official | 354:e67efb2aab0e | 2133 | * @param sConfig: TIM Encoder Interface configuration structure |
| mbed_official | 354:e67efb2aab0e | 2134 | * @retval HAL status |
| mbed_official | 354:e67efb2aab0e | 2135 | */ |
| mbed_official | 354:e67efb2aab0e | 2136 | HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig) |
| mbed_official | 354:e67efb2aab0e | 2137 | { |
| mbed_official | 354:e67efb2aab0e | 2138 | uint32_t tmpsmcr = 0; |
| mbed_official | 354:e67efb2aab0e | 2139 | uint32_t tmpccmr1 = 0; |
| mbed_official | 354:e67efb2aab0e | 2140 | uint32_t tmpccer = 0; |
| mbed_official | 354:e67efb2aab0e | 2141 | |
| mbed_official | 354:e67efb2aab0e | 2142 | /* Check the TIM handle allocation */ |
| mbed_official | 354:e67efb2aab0e | 2143 | if(htim == HAL_NULL) |
| mbed_official | 354:e67efb2aab0e | 2144 | { |
| mbed_official | 354:e67efb2aab0e | 2145 | return HAL_ERROR; |
| mbed_official | 354:e67efb2aab0e | 2146 | } |
| mbed_official | 354:e67efb2aab0e | 2147 | |
| mbed_official | 354:e67efb2aab0e | 2148 | /* Check the parameters */ |
| mbed_official | 354:e67efb2aab0e | 2149 | assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); |
| mbed_official | 354:e67efb2aab0e | 2150 | assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode)); |
| mbed_official | 354:e67efb2aab0e | 2151 | assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection)); |
| mbed_official | 354:e67efb2aab0e | 2152 | assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection)); |
| mbed_official | 354:e67efb2aab0e | 2153 | assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity)); |
| mbed_official | 354:e67efb2aab0e | 2154 | assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity)); |
| mbed_official | 354:e67efb2aab0e | 2155 | assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); |
| mbed_official | 354:e67efb2aab0e | 2156 | assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler)); |
| mbed_official | 354:e67efb2aab0e | 2157 | assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); |
| mbed_official | 354:e67efb2aab0e | 2158 | assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter)); |
| mbed_official | 354:e67efb2aab0e | 2159 | |
| mbed_official | 354:e67efb2aab0e | 2160 | if(htim->State == HAL_TIM_STATE_RESET) |
| mbed_official | 354:e67efb2aab0e | 2161 | { |
| mbed_official | 354:e67efb2aab0e | 2162 | /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ |
| mbed_official | 354:e67efb2aab0e | 2163 | HAL_TIM_Encoder_MspInit(htim); |
| mbed_official | 354:e67efb2aab0e | 2164 | } |
| mbed_official | 354:e67efb2aab0e | 2165 | |
| mbed_official | 354:e67efb2aab0e | 2166 | /* Set the TIM state */ |
| mbed_official | 354:e67efb2aab0e | 2167 | htim->State= HAL_TIM_STATE_BUSY; |
| mbed_official | 354:e67efb2aab0e | 2168 | |
| mbed_official | 354:e67efb2aab0e | 2169 | /* Reset the SMS bits */ |
| mbed_official | 354:e67efb2aab0e | 2170 | htim->Instance->SMCR &= ~TIM_SMCR_SMS; |
| mbed_official | 354:e67efb2aab0e | 2171 | |
| mbed_official | 354:e67efb2aab0e | 2172 | /* Configure the Time base in the Encoder Mode */ |
| mbed_official | 354:e67efb2aab0e | 2173 | TIM_Base_SetConfig(htim->Instance, &htim->Init); |
| mbed_official | 354:e67efb2aab0e | 2174 | |
| mbed_official | 354:e67efb2aab0e | 2175 | /* Get the TIMx SMCR register value */ |
| mbed_official | 354:e67efb2aab0e | 2176 | tmpsmcr = htim->Instance->SMCR; |
| mbed_official | 354:e67efb2aab0e | 2177 | |
| mbed_official | 354:e67efb2aab0e | 2178 | /* Get the TIMx CCMR1 register value */ |
| mbed_official | 354:e67efb2aab0e | 2179 | tmpccmr1 = htim->Instance->CCMR1; |
| mbed_official | 354:e67efb2aab0e | 2180 | |
| mbed_official | 354:e67efb2aab0e | 2181 | /* Get the TIMx CCER register value */ |
| mbed_official | 354:e67efb2aab0e | 2182 | tmpccer = htim->Instance->CCER; |
| mbed_official | 354:e67efb2aab0e | 2183 | |
| mbed_official | 354:e67efb2aab0e | 2184 | /* Set the encoder Mode */ |
| mbed_official | 354:e67efb2aab0e | 2185 | tmpsmcr |= sConfig->EncoderMode; |
| mbed_official | 354:e67efb2aab0e | 2186 | |
| mbed_official | 354:e67efb2aab0e | 2187 | /* Select the Capture Compare 1 and the Capture Compare 2 as input */ |
| mbed_official | 354:e67efb2aab0e | 2188 | tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S); |
| mbed_official | 354:e67efb2aab0e | 2189 | tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8)); |
| mbed_official | 354:e67efb2aab0e | 2190 | |
| mbed_official | 354:e67efb2aab0e | 2191 | /* Set the the Capture Compare 1 and the Capture Compare 2 prescalers and filters */ |
| mbed_official | 354:e67efb2aab0e | 2192 | tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC); |
| mbed_official | 354:e67efb2aab0e | 2193 | tmpccmr1 &= (~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F)); |
| mbed_official | 354:e67efb2aab0e | 2194 | tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8); |
| mbed_official | 354:e67efb2aab0e | 2195 | tmpccmr1 |= (sConfig->IC1Filter << 4) | (sConfig->IC2Filter << 12); |
| mbed_official | 354:e67efb2aab0e | 2196 | |
| mbed_official | 354:e67efb2aab0e | 2197 | /* Set the TI1 and the TI2 Polarities */ |
| mbed_official | 354:e67efb2aab0e | 2198 | tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P); |
| mbed_official | 354:e67efb2aab0e | 2199 | tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP); |
| mbed_official | 354:e67efb2aab0e | 2200 | tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4); |
| mbed_official | 354:e67efb2aab0e | 2201 | |
| mbed_official | 354:e67efb2aab0e | 2202 | /* Write to TIMx SMCR */ |
| mbed_official | 354:e67efb2aab0e | 2203 | htim->Instance->SMCR = tmpsmcr; |
| mbed_official | 354:e67efb2aab0e | 2204 | |
| mbed_official | 354:e67efb2aab0e | 2205 | /* Write to TIMx CCMR1 */ |
| mbed_official | 354:e67efb2aab0e | 2206 | htim->Instance->CCMR1 = tmpccmr1; |
| mbed_official | 354:e67efb2aab0e | 2207 | |
| mbed_official | 354:e67efb2aab0e | 2208 | /* Write to TIMx CCER */ |
| mbed_official | 354:e67efb2aab0e | 2209 | htim->Instance->CCER = tmpccer; |
| mbed_official | 354:e67efb2aab0e | 2210 | |
| mbed_official | 354:e67efb2aab0e | 2211 | /* Initialize the TIM state*/ |
| mbed_official | 354:e67efb2aab0e | 2212 | htim->State= HAL_TIM_STATE_READY; |
| mbed_official | 354:e67efb2aab0e | 2213 | |
| mbed_official | 354:e67efb2aab0e | 2214 | return HAL_OK; |
| mbed_official | 354:e67efb2aab0e | 2215 | } |
| mbed_official | 354:e67efb2aab0e | 2216 | |
| mbed_official | 354:e67efb2aab0e | 2217 | |
| mbed_official | 354:e67efb2aab0e | 2218 | /** |
| mbed_official | 354:e67efb2aab0e | 2219 | * @brief DeInitializes the TIM Encoder interface |
| mbed_official | 354:e67efb2aab0e | 2220 | * @param htim: TIM Encoder handle |
| mbed_official | 354:e67efb2aab0e | 2221 | * @retval HAL status |
| mbed_official | 354:e67efb2aab0e | 2222 | */ |
| mbed_official | 354:e67efb2aab0e | 2223 | HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim) |
| mbed_official | 354:e67efb2aab0e | 2224 | { |
| mbed_official | 354:e67efb2aab0e | 2225 | /* Check the parameters */ |
| mbed_official | 354:e67efb2aab0e | 2226 | assert_param(IS_TIM_INSTANCE(htim->Instance)); |
| mbed_official | 354:e67efb2aab0e | 2227 | |
| mbed_official | 354:e67efb2aab0e | 2228 | htim->State = HAL_TIM_STATE_BUSY; |
| mbed_official | 354:e67efb2aab0e | 2229 | |
| mbed_official | 354:e67efb2aab0e | 2230 | /* Disable the TIM Peripheral Clock */ |
| mbed_official | 354:e67efb2aab0e | 2231 | __HAL_TIM_DISABLE(htim); |
| mbed_official | 354:e67efb2aab0e | 2232 | |
| mbed_official | 354:e67efb2aab0e | 2233 | /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ |
| mbed_official | 354:e67efb2aab0e | 2234 | HAL_TIM_Encoder_MspDeInit(htim); |
| mbed_official | 354:e67efb2aab0e | 2235 | |
| mbed_official | 354:e67efb2aab0e | 2236 | /* Change TIM state */ |
| mbed_official | 354:e67efb2aab0e | 2237 | htim->State = HAL_TIM_STATE_RESET; |
| mbed_official | 354:e67efb2aab0e | 2238 | |
| mbed_official | 354:e67efb2aab0e | 2239 | /* Release Lock */ |
| mbed_official | 354:e67efb2aab0e | 2240 | __HAL_UNLOCK(htim); |
| mbed_official | 354:e67efb2aab0e | 2241 | |
| mbed_official | 354:e67efb2aab0e | 2242 | return HAL_OK; |
| mbed_official | 354:e67efb2aab0e | 2243 | } |
| mbed_official | 354:e67efb2aab0e | 2244 | |
| mbed_official | 354:e67efb2aab0e | 2245 | /** |
| mbed_official | 354:e67efb2aab0e | 2246 | * @brief Initializes the TIM Encoder Interface MSP. |
| mbed_official | 354:e67efb2aab0e | 2247 | * @param htim: TIM handle |
| mbed_official | 354:e67efb2aab0e | 2248 | * @retval None |
| mbed_official | 354:e67efb2aab0e | 2249 | */ |
| mbed_official | 354:e67efb2aab0e | 2250 | __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim) |
| mbed_official | 354:e67efb2aab0e | 2251 | { |
| mbed_official | 354:e67efb2aab0e | 2252 | /* NOTE : This function Should not be modified, when the callback is needed, |
| mbed_official | 354:e67efb2aab0e | 2253 | the HAL_TIM_Encoder_MspInit could be implemented in the user file |
| mbed_official | 354:e67efb2aab0e | 2254 | */ |
| mbed_official | 354:e67efb2aab0e | 2255 | } |
| mbed_official | 354:e67efb2aab0e | 2256 | |
| mbed_official | 354:e67efb2aab0e | 2257 | /** |
| mbed_official | 354:e67efb2aab0e | 2258 | * @brief DeInitializes TIM Encoder Interface MSP. |
| mbed_official | 354:e67efb2aab0e | 2259 | * @param htim: TIM handle |
| mbed_official | 354:e67efb2aab0e | 2260 | * @retval None |
| mbed_official | 354:e67efb2aab0e | 2261 | */ |
| mbed_official | 354:e67efb2aab0e | 2262 | __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim) |
| mbed_official | 354:e67efb2aab0e | 2263 | { |
| mbed_official | 354:e67efb2aab0e | 2264 | /* NOTE : This function Should not be modified, when the callback is needed, |
| mbed_official | 354:e67efb2aab0e | 2265 | the HAL_TIM_Encoder_MspDeInit could be implemented in the user file |
| mbed_official | 354:e67efb2aab0e | 2266 | */ |
| mbed_official | 354:e67efb2aab0e | 2267 | } |
| mbed_official | 354:e67efb2aab0e | 2268 | |
| mbed_official | 354:e67efb2aab0e | 2269 | /** |
| mbed_official | 354:e67efb2aab0e | 2270 | * @brief Starts the TIM Encoder Interface. |
| mbed_official | 354:e67efb2aab0e | 2271 | * @param htim : TIM Encoder Interface handle |
| mbed_official | 354:e67efb2aab0e | 2272 | * @param Channel : TIM Channels to be enabled |
| mbed_official | 354:e67efb2aab0e | 2273 | * This parameter can be one of the following values: |
| mbed_official | 354:e67efb2aab0e | 2274 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| mbed_official | 354:e67efb2aab0e | 2275 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| mbed_official | 354:e67efb2aab0e | 2276 | * @retval HAL status |
| mbed_official | 354:e67efb2aab0e | 2277 | */ |
| mbed_official | 354:e67efb2aab0e | 2278 | HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel) |
| mbed_official | 354:e67efb2aab0e | 2279 | { |
| mbed_official | 354:e67efb2aab0e | 2280 | /* Check the parameters */ |
| mbed_official | 354:e67efb2aab0e | 2281 | assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); |
| mbed_official | 354:e67efb2aab0e | 2282 | |
| mbed_official | 354:e67efb2aab0e | 2283 | /* Enable the encoder interface channels */ |
| mbed_official | 354:e67efb2aab0e | 2284 | switch (Channel) |
| mbed_official | 354:e67efb2aab0e | 2285 | { |
| mbed_official | 354:e67efb2aab0e | 2286 | case TIM_CHANNEL_1: |
| mbed_official | 354:e67efb2aab0e | 2287 | { |
| mbed_official | 354:e67efb2aab0e | 2288 | TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); |
| mbed_official | 354:e67efb2aab0e | 2289 | break; |
| mbed_official | 354:e67efb2aab0e | 2290 | } |
| mbed_official | 354:e67efb2aab0e | 2291 | case TIM_CHANNEL_2: |
| mbed_official | 354:e67efb2aab0e | 2292 | { |
| mbed_official | 354:e67efb2aab0e | 2293 | TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); |
| mbed_official | 354:e67efb2aab0e | 2294 | break; |
| mbed_official | 354:e67efb2aab0e | 2295 | } |
| mbed_official | 354:e67efb2aab0e | 2296 | default : |
| mbed_official | 354:e67efb2aab0e | 2297 | { |
| mbed_official | 354:e67efb2aab0e | 2298 | TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); |
| mbed_official | 354:e67efb2aab0e | 2299 | TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); |
| mbed_official | 354:e67efb2aab0e | 2300 | break; |
| mbed_official | 354:e67efb2aab0e | 2301 | } |
| mbed_official | 354:e67efb2aab0e | 2302 | } |
| mbed_official | 354:e67efb2aab0e | 2303 | /* Enable the Peripheral */ |
| mbed_official | 354:e67efb2aab0e | 2304 | __HAL_TIM_ENABLE(htim); |
| mbed_official | 354:e67efb2aab0e | 2305 | |
| mbed_official | 354:e67efb2aab0e | 2306 | /* Return function status */ |
| mbed_official | 354:e67efb2aab0e | 2307 | return HAL_OK; |
| mbed_official | 354:e67efb2aab0e | 2308 | } |
| mbed_official | 354:e67efb2aab0e | 2309 | |
| mbed_official | 354:e67efb2aab0e | 2310 | /** |
| mbed_official | 354:e67efb2aab0e | 2311 | * @brief Stops the TIM Encoder Interface. |
| mbed_official | 354:e67efb2aab0e | 2312 | * @param htim : TIM Encoder Interface handle |
| mbed_official | 354:e67efb2aab0e | 2313 | * @param Channel : TIM Channels to be disabled |
| mbed_official | 354:e67efb2aab0e | 2314 | * This parameter can be one of the following values: |
| mbed_official | 354:e67efb2aab0e | 2315 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| mbed_official | 354:e67efb2aab0e | 2316 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| mbed_official | 354:e67efb2aab0e | 2317 | * @retval HAL status |
| mbed_official | 354:e67efb2aab0e | 2318 | */ |
| mbed_official | 354:e67efb2aab0e | 2319 | HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) |
| mbed_official | 354:e67efb2aab0e | 2320 | { |
| mbed_official | 354:e67efb2aab0e | 2321 | /* Check the parameters */ |
| mbed_official | 354:e67efb2aab0e | 2322 | assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); |
| mbed_official | 354:e67efb2aab0e | 2323 | |
| mbed_official | 354:e67efb2aab0e | 2324 | /* Disable the Input Capture channels 1 and 2 |
| mbed_official | 354:e67efb2aab0e | 2325 | (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ |
| mbed_official | 354:e67efb2aab0e | 2326 | switch (Channel) |
| mbed_official | 354:e67efb2aab0e | 2327 | { |
| mbed_official | 354:e67efb2aab0e | 2328 | case TIM_CHANNEL_1: |
| mbed_official | 354:e67efb2aab0e | 2329 | { |
| mbed_official | 354:e67efb2aab0e | 2330 | TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); |
| mbed_official | 354:e67efb2aab0e | 2331 | break; |
| mbed_official | 354:e67efb2aab0e | 2332 | } |
| mbed_official | 354:e67efb2aab0e | 2333 | case TIM_CHANNEL_2: |
| mbed_official | 354:e67efb2aab0e | 2334 | { |
| mbed_official | 354:e67efb2aab0e | 2335 | TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); |
| mbed_official | 354:e67efb2aab0e | 2336 | break; |
| mbed_official | 354:e67efb2aab0e | 2337 | } |
| mbed_official | 354:e67efb2aab0e | 2338 | default : |
| mbed_official | 354:e67efb2aab0e | 2339 | { |
| mbed_official | 354:e67efb2aab0e | 2340 | TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); |
| mbed_official | 354:e67efb2aab0e | 2341 | TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); |
| mbed_official | 354:e67efb2aab0e | 2342 | break; |
| mbed_official | 354:e67efb2aab0e | 2343 | } |
| mbed_official | 354:e67efb2aab0e | 2344 | } |
| mbed_official | 354:e67efb2aab0e | 2345 | |
| mbed_official | 354:e67efb2aab0e | 2346 | /* Disable the Peripheral */ |
| mbed_official | 354:e67efb2aab0e | 2347 | __HAL_TIM_DISABLE(htim); |
| mbed_official | 354:e67efb2aab0e | 2348 | |
| mbed_official | 354:e67efb2aab0e | 2349 | /* Return function status */ |
| mbed_official | 354:e67efb2aab0e | 2350 | return HAL_OK; |
| mbed_official | 354:e67efb2aab0e | 2351 | } |
| mbed_official | 354:e67efb2aab0e | 2352 | |
| mbed_official | 354:e67efb2aab0e | 2353 | /** |
| mbed_official | 354:e67efb2aab0e | 2354 | * @brief Starts the TIM Encoder Interface in interrupt mode. |
| mbed_official | 354:e67efb2aab0e | 2355 | * @param htim : TIM Encoder Interface handle |
| mbed_official | 354:e67efb2aab0e | 2356 | * @param Channel : TIM Channels to be enabled |
| mbed_official | 354:e67efb2aab0e | 2357 | * This parameter can be one of the following values: |
| mbed_official | 354:e67efb2aab0e | 2358 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| mbed_official | 354:e67efb2aab0e | 2359 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| mbed_official | 354:e67efb2aab0e | 2360 | * @retval HAL status |
| mbed_official | 354:e67efb2aab0e | 2361 | */ |
| mbed_official | 354:e67efb2aab0e | 2362 | HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) |
| mbed_official | 354:e67efb2aab0e | 2363 | { |
| mbed_official | 354:e67efb2aab0e | 2364 | /* Check the parameters */ |
| mbed_official | 354:e67efb2aab0e | 2365 | assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); |
| mbed_official | 354:e67efb2aab0e | 2366 | |
| mbed_official | 354:e67efb2aab0e | 2367 | /* Enable the encoder interface channels */ |
| mbed_official | 354:e67efb2aab0e | 2368 | /* Enable the capture compare Interrupts 1 and/or 2 */ |
| mbed_official | 354:e67efb2aab0e | 2369 | switch (Channel) |
| mbed_official | 354:e67efb2aab0e | 2370 | { |
| mbed_official | 354:e67efb2aab0e | 2371 | case TIM_CHANNEL_1: |
| mbed_official | 354:e67efb2aab0e | 2372 | { |
| mbed_official | 354:e67efb2aab0e | 2373 | TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); |
| mbed_official | 354:e67efb2aab0e | 2374 | __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); |
| mbed_official | 354:e67efb2aab0e | 2375 | break; |
| mbed_official | 354:e67efb2aab0e | 2376 | } |
| mbed_official | 354:e67efb2aab0e | 2377 | case TIM_CHANNEL_2: |
| mbed_official | 354:e67efb2aab0e | 2378 | { |
| mbed_official | 354:e67efb2aab0e | 2379 | TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); |
| mbed_official | 354:e67efb2aab0e | 2380 | __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); |
| mbed_official | 354:e67efb2aab0e | 2381 | break; |
| mbed_official | 354:e67efb2aab0e | 2382 | } |
| mbed_official | 354:e67efb2aab0e | 2383 | default : |
| mbed_official | 354:e67efb2aab0e | 2384 | { |
| mbed_official | 354:e67efb2aab0e | 2385 | TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); |
| mbed_official | 354:e67efb2aab0e | 2386 | TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); |
| mbed_official | 354:e67efb2aab0e | 2387 | __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); |
| mbed_official | 354:e67efb2aab0e | 2388 | __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); |
| mbed_official | 354:e67efb2aab0e | 2389 | break; |
| mbed_official | 354:e67efb2aab0e | 2390 | } |
| mbed_official | 354:e67efb2aab0e | 2391 | } |
| mbed_official | 354:e67efb2aab0e | 2392 | |
| mbed_official | 354:e67efb2aab0e | 2393 | /* Enable the Peripheral */ |
| mbed_official | 354:e67efb2aab0e | 2394 | __HAL_TIM_ENABLE(htim); |
| mbed_official | 354:e67efb2aab0e | 2395 | |
| mbed_official | 354:e67efb2aab0e | 2396 | /* Return function status */ |
| mbed_official | 354:e67efb2aab0e | 2397 | return HAL_OK; |
| mbed_official | 354:e67efb2aab0e | 2398 | } |
| mbed_official | 354:e67efb2aab0e | 2399 | |
| mbed_official | 354:e67efb2aab0e | 2400 | /** |
| mbed_official | 354:e67efb2aab0e | 2401 | * @brief Stops the TIM Encoder Interface in interrupt mode. |
| mbed_official | 354:e67efb2aab0e | 2402 | * @param htim : TIM Encoder Interface handle |
| mbed_official | 354:e67efb2aab0e | 2403 | * @param Channel : TIM Channels to be disabled |
| mbed_official | 354:e67efb2aab0e | 2404 | * This parameter can be one of the following values: |
| mbed_official | 354:e67efb2aab0e | 2405 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| mbed_official | 354:e67efb2aab0e | 2406 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| mbed_official | 354:e67efb2aab0e | 2407 | * @retval HAL status |
| mbed_official | 354:e67efb2aab0e | 2408 | */ |
| mbed_official | 354:e67efb2aab0e | 2409 | HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) |
| mbed_official | 354:e67efb2aab0e | 2410 | { |
| mbed_official | 354:e67efb2aab0e | 2411 | /* Check the parameters */ |
| mbed_official | 354:e67efb2aab0e | 2412 | assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); |
| mbed_official | 354:e67efb2aab0e | 2413 | |
| mbed_official | 354:e67efb2aab0e | 2414 | /* Disable the Input Capture channels 1 and 2 |
| mbed_official | 354:e67efb2aab0e | 2415 | (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ |
| mbed_official | 354:e67efb2aab0e | 2416 | if(Channel == TIM_CHANNEL_1) |
| mbed_official | 354:e67efb2aab0e | 2417 | { |
| mbed_official | 354:e67efb2aab0e | 2418 | TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); |
| mbed_official | 354:e67efb2aab0e | 2419 | |
| mbed_official | 354:e67efb2aab0e | 2420 | /* Disable the capture compare Interrupts 1 */ |
| mbed_official | 354:e67efb2aab0e | 2421 | __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); |
| mbed_official | 354:e67efb2aab0e | 2422 | } |
| mbed_official | 354:e67efb2aab0e | 2423 | else if(Channel == TIM_CHANNEL_2) |
| mbed_official | 354:e67efb2aab0e | 2424 | { |
| mbed_official | 354:e67efb2aab0e | 2425 | TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); |
| mbed_official | 354:e67efb2aab0e | 2426 | |
| mbed_official | 354:e67efb2aab0e | 2427 | /* Disable the capture compare Interrupts 2 */ |
| mbed_official | 354:e67efb2aab0e | 2428 | __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); |
| mbed_official | 354:e67efb2aab0e | 2429 | } |
| mbed_official | 354:e67efb2aab0e | 2430 | else |
| mbed_official | 354:e67efb2aab0e | 2431 | { |
| mbed_official | 354:e67efb2aab0e | 2432 | TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); |
| mbed_official | 354:e67efb2aab0e | 2433 | TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); |
| mbed_official | 354:e67efb2aab0e | 2434 | |
| mbed_official | 354:e67efb2aab0e | 2435 | /* Disable the capture compare Interrupts 1 and 2 */ |
| mbed_official | 354:e67efb2aab0e | 2436 | __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); |
| mbed_official | 354:e67efb2aab0e | 2437 | __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); |
| mbed_official | 354:e67efb2aab0e | 2438 | } |
| mbed_official | 354:e67efb2aab0e | 2439 | |
| mbed_official | 354:e67efb2aab0e | 2440 | /* Disable the Peripheral */ |
| mbed_official | 354:e67efb2aab0e | 2441 | __HAL_TIM_DISABLE(htim); |
| mbed_official | 354:e67efb2aab0e | 2442 | |
| mbed_official | 354:e67efb2aab0e | 2443 | /* Change the htim state */ |
| mbed_official | 354:e67efb2aab0e | 2444 | htim->State = HAL_TIM_STATE_READY; |
| mbed_official | 354:e67efb2aab0e | 2445 | |
| mbed_official | 354:e67efb2aab0e | 2446 | /* Return function status */ |
| mbed_official | 354:e67efb2aab0e | 2447 | return HAL_OK; |
| mbed_official | 354:e67efb2aab0e | 2448 | } |
| mbed_official | 354:e67efb2aab0e | 2449 | |
| mbed_official | 354:e67efb2aab0e | 2450 | /** |
| mbed_official | 354:e67efb2aab0e | 2451 | * @brief Starts the TIM Encoder Interface in DMA mode. |
| mbed_official | 354:e67efb2aab0e | 2452 | * @param htim : TIM Encoder Interface handle |
| mbed_official | 354:e67efb2aab0e | 2453 | * @param Channel : TIM Channels to be enabled |
| mbed_official | 354:e67efb2aab0e | 2454 | * This parameter can be one of the following values: |
| mbed_official | 354:e67efb2aab0e | 2455 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| mbed_official | 354:e67efb2aab0e | 2456 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| mbed_official | 354:e67efb2aab0e | 2457 | * @param pData1: The destination Buffer address for IC1. |
| mbed_official | 354:e67efb2aab0e | 2458 | * @param pData2: The destination Buffer address for IC2. |
| mbed_official | 354:e67efb2aab0e | 2459 | * @param Length: The length of data to be transferred from TIM peripheral to memory. |
| mbed_official | 354:e67efb2aab0e | 2460 | * @retval HAL status |
| mbed_official | 354:e67efb2aab0e | 2461 | */ |
| mbed_official | 354:e67efb2aab0e | 2462 | HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length) |
| mbed_official | 354:e67efb2aab0e | 2463 | { |
| mbed_official | 354:e67efb2aab0e | 2464 | /* Check the parameters */ |
| mbed_official | 354:e67efb2aab0e | 2465 | assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); |
| mbed_official | 354:e67efb2aab0e | 2466 | |
| mbed_official | 354:e67efb2aab0e | 2467 | if((htim->State == HAL_TIM_STATE_BUSY)) |
| mbed_official | 354:e67efb2aab0e | 2468 | { |
| mbed_official | 354:e67efb2aab0e | 2469 | return HAL_BUSY; |
| mbed_official | 354:e67efb2aab0e | 2470 | } |
| mbed_official | 354:e67efb2aab0e | 2471 | else if((htim->State == HAL_TIM_STATE_READY)) |
| mbed_official | 354:e67efb2aab0e | 2472 | { |
| mbed_official | 354:e67efb2aab0e | 2473 | if((((pData1 == 0) || (pData2 == 0) )) && (Length > 0)) |
| mbed_official | 354:e67efb2aab0e | 2474 | { |
| mbed_official | 354:e67efb2aab0e | 2475 | return HAL_ERROR; |
| mbed_official | 354:e67efb2aab0e | 2476 | } |
| mbed_official | 354:e67efb2aab0e | 2477 | else |
| mbed_official | 354:e67efb2aab0e | 2478 | { |
| mbed_official | 354:e67efb2aab0e | 2479 | htim->State = HAL_TIM_STATE_BUSY; |
| mbed_official | 354:e67efb2aab0e | 2480 | } |
| mbed_official | 354:e67efb2aab0e | 2481 | } |
| mbed_official | 354:e67efb2aab0e | 2482 | else |
| mbed_official | 354:e67efb2aab0e | 2483 | { |
| mbed_official | 354:e67efb2aab0e | 2484 | return HAL_ERROR; |
| mbed_official | 354:e67efb2aab0e | 2485 | } |
| mbed_official | 354:e67efb2aab0e | 2486 | |
| mbed_official | 354:e67efb2aab0e | 2487 | switch (Channel) |
| mbed_official | 354:e67efb2aab0e | 2488 | { |
| mbed_official | 354:e67efb2aab0e | 2489 | case TIM_CHANNEL_1: |
| mbed_official | 354:e67efb2aab0e | 2490 | { |
| mbed_official | 354:e67efb2aab0e | 2491 | /* Set the DMA Period elapsed callback */ |
| mbed_official | 354:e67efb2aab0e | 2492 | htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; |
| mbed_official | 354:e67efb2aab0e | 2493 | |
| mbed_official | 354:e67efb2aab0e | 2494 | /* Set the DMA error callback */ |
| mbed_official | 354:e67efb2aab0e | 2495 | htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; |
| mbed_official | 354:e67efb2aab0e | 2496 | |
| mbed_official | 354:e67efb2aab0e | 2497 | /* Enable the DMA channel */ |
| mbed_official | 354:e67efb2aab0e | 2498 | HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t )pData1, Length); |
| mbed_official | 354:e67efb2aab0e | 2499 | |
| mbed_official | 354:e67efb2aab0e | 2500 | /* Enable the TIM Input Capture DMA request */ |
| mbed_official | 354:e67efb2aab0e | 2501 | __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); |
| mbed_official | 354:e67efb2aab0e | 2502 | |
| mbed_official | 354:e67efb2aab0e | 2503 | /* Enable the Peripheral */ |
| mbed_official | 354:e67efb2aab0e | 2504 | __HAL_TIM_ENABLE(htim); |
| mbed_official | 354:e67efb2aab0e | 2505 | |
| mbed_official | 354:e67efb2aab0e | 2506 | /* Enable the Capture compare channel */ |
| mbed_official | 354:e67efb2aab0e | 2507 | TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); |
| mbed_official | 354:e67efb2aab0e | 2508 | } |
| mbed_official | 354:e67efb2aab0e | 2509 | break; |
| mbed_official | 354:e67efb2aab0e | 2510 | |
| mbed_official | 354:e67efb2aab0e | 2511 | case TIM_CHANNEL_2: |
| mbed_official | 354:e67efb2aab0e | 2512 | { |
| mbed_official | 354:e67efb2aab0e | 2513 | /* Set the DMA Period elapsed callback */ |
| mbed_official | 354:e67efb2aab0e | 2514 | htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; |
| mbed_official | 354:e67efb2aab0e | 2515 | |
| mbed_official | 354:e67efb2aab0e | 2516 | /* Set the DMA error callback */ |
| mbed_official | 354:e67efb2aab0e | 2517 | htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError; |
| mbed_official | 354:e67efb2aab0e | 2518 | /* Enable the DMA channel */ |
| mbed_official | 354:e67efb2aab0e | 2519 | HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length); |
| mbed_official | 354:e67efb2aab0e | 2520 | |
| mbed_official | 354:e67efb2aab0e | 2521 | /* Enable the TIM Input Capture DMA request */ |
| mbed_official | 354:e67efb2aab0e | 2522 | __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); |
| mbed_official | 354:e67efb2aab0e | 2523 | |
| mbed_official | 354:e67efb2aab0e | 2524 | /* Enable the Peripheral */ |
| mbed_official | 354:e67efb2aab0e | 2525 | __HAL_TIM_ENABLE(htim); |
| mbed_official | 354:e67efb2aab0e | 2526 | |
| mbed_official | 354:e67efb2aab0e | 2527 | /* Enable the Capture compare channel */ |
| mbed_official | 354:e67efb2aab0e | 2528 | TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); |
| mbed_official | 354:e67efb2aab0e | 2529 | } |
| mbed_official | 354:e67efb2aab0e | 2530 | break; |
| mbed_official | 354:e67efb2aab0e | 2531 | |
| mbed_official | 354:e67efb2aab0e | 2532 | case TIM_CHANNEL_ALL: |
| mbed_official | 354:e67efb2aab0e | 2533 | { |
| mbed_official | 354:e67efb2aab0e | 2534 | /* Set the DMA Period elapsed callback */ |
| mbed_official | 354:e67efb2aab0e | 2535 | htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; |
| mbed_official | 354:e67efb2aab0e | 2536 | |
| mbed_official | 354:e67efb2aab0e | 2537 | /* Set the DMA error callback */ |
| mbed_official | 354:e67efb2aab0e | 2538 | htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; |
| mbed_official | 354:e67efb2aab0e | 2539 | |
| mbed_official | 354:e67efb2aab0e | 2540 | /* Enable the DMA channel */ |
| mbed_official | 354:e67efb2aab0e | 2541 | HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length); |
| mbed_official | 354:e67efb2aab0e | 2542 | |
| mbed_official | 354:e67efb2aab0e | 2543 | /* Set the DMA Period elapsed callback */ |
| mbed_official | 354:e67efb2aab0e | 2544 | htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; |
| mbed_official | 354:e67efb2aab0e | 2545 | |
| mbed_official | 354:e67efb2aab0e | 2546 | /* Set the DMA error callback */ |
| mbed_official | 354:e67efb2aab0e | 2547 | htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; |
| mbed_official | 354:e67efb2aab0e | 2548 | |
| mbed_official | 354:e67efb2aab0e | 2549 | /* Enable the DMA channel */ |
| mbed_official | 354:e67efb2aab0e | 2550 | HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length); |
| mbed_official | 354:e67efb2aab0e | 2551 | |
| mbed_official | 354:e67efb2aab0e | 2552 | /* Enable the Peripheral */ |
| mbed_official | 354:e67efb2aab0e | 2553 | __HAL_TIM_ENABLE(htim); |
| mbed_official | 354:e67efb2aab0e | 2554 | |
| mbed_official | 354:e67efb2aab0e | 2555 | /* Enable the Capture compare channel */ |
| mbed_official | 354:e67efb2aab0e | 2556 | TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); |
| mbed_official | 354:e67efb2aab0e | 2557 | TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); |
| mbed_official | 354:e67efb2aab0e | 2558 | |
| mbed_official | 354:e67efb2aab0e | 2559 | /* Enable the TIM Input Capture DMA request */ |
| mbed_official | 354:e67efb2aab0e | 2560 | __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); |
| mbed_official | 354:e67efb2aab0e | 2561 | /* Enable the TIM Input Capture DMA request */ |
| mbed_official | 354:e67efb2aab0e | 2562 | __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); |
| mbed_official | 354:e67efb2aab0e | 2563 | } |
| mbed_official | 354:e67efb2aab0e | 2564 | break; |
| mbed_official | 354:e67efb2aab0e | 2565 | |
| mbed_official | 354:e67efb2aab0e | 2566 | default: |
| mbed_official | 354:e67efb2aab0e | 2567 | break; |
| mbed_official | 354:e67efb2aab0e | 2568 | } |
| mbed_official | 354:e67efb2aab0e | 2569 | /* Return function status */ |
| mbed_official | 354:e67efb2aab0e | 2570 | return HAL_OK; |
| mbed_official | 354:e67efb2aab0e | 2571 | } |
| mbed_official | 354:e67efb2aab0e | 2572 | |
| mbed_official | 354:e67efb2aab0e | 2573 | /** |
| mbed_official | 354:e67efb2aab0e | 2574 | * @brief Stops the TIM Encoder Interface in DMA mode. |
| mbed_official | 354:e67efb2aab0e | 2575 | * @param htim : TIM Encoder Interface handle |
| mbed_official | 354:e67efb2aab0e | 2576 | * @param Channel : TIM Channels to be enabled |
| mbed_official | 354:e67efb2aab0e | 2577 | * This parameter can be one of the following values: |
| mbed_official | 354:e67efb2aab0e | 2578 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| mbed_official | 354:e67efb2aab0e | 2579 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| mbed_official | 354:e67efb2aab0e | 2580 | * @retval HAL status |
| mbed_official | 354:e67efb2aab0e | 2581 | */ |
| mbed_official | 354:e67efb2aab0e | 2582 | HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) |
| mbed_official | 354:e67efb2aab0e | 2583 | { |
| mbed_official | 354:e67efb2aab0e | 2584 | /* Check the parameters */ |
| mbed_official | 354:e67efb2aab0e | 2585 | assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); |
| mbed_official | 354:e67efb2aab0e | 2586 | |
| mbed_official | 354:e67efb2aab0e | 2587 | /* Disable the Input Capture channels 1 and 2 |
| mbed_official | 354:e67efb2aab0e | 2588 | (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ |
| mbed_official | 354:e67efb2aab0e | 2589 | if(Channel == TIM_CHANNEL_1) |
| mbed_official | 354:e67efb2aab0e | 2590 | { |
| mbed_official | 354:e67efb2aab0e | 2591 | TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); |
| mbed_official | 354:e67efb2aab0e | 2592 | |
| mbed_official | 354:e67efb2aab0e | 2593 | /* Disable the capture compare DMA Request 1 */ |
| mbed_official | 354:e67efb2aab0e | 2594 | __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); |
| mbed_official | 354:e67efb2aab0e | 2595 | } |
| mbed_official | 354:e67efb2aab0e | 2596 | else if(Channel == TIM_CHANNEL_2) |
| mbed_official | 354:e67efb2aab0e | 2597 | { |
| mbed_official | 354:e67efb2aab0e | 2598 | TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); |
| mbed_official | 354:e67efb2aab0e | 2599 | |
| mbed_official | 354:e67efb2aab0e | 2600 | /* Disable the capture compare DMA Request 2 */ |
| mbed_official | 354:e67efb2aab0e | 2601 | __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); |
| mbed_official | 354:e67efb2aab0e | 2602 | } |
| mbed_official | 354:e67efb2aab0e | 2603 | else |
| mbed_official | 354:e67efb2aab0e | 2604 | { |
| mbed_official | 354:e67efb2aab0e | 2605 | TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); |
| mbed_official | 354:e67efb2aab0e | 2606 | TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); |
| mbed_official | 354:e67efb2aab0e | 2607 | |
| mbed_official | 354:e67efb2aab0e | 2608 | /* Disable the capture compare DMA Request 1 and 2 */ |
| mbed_official | 354:e67efb2aab0e | 2609 | __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); |
| mbed_official | 354:e67efb2aab0e | 2610 | __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); |
| mbed_official | 354:e67efb2aab0e | 2611 | } |
| mbed_official | 354:e67efb2aab0e | 2612 | |
| mbed_official | 354:e67efb2aab0e | 2613 | /* Disable the Peripheral */ |
| mbed_official | 354:e67efb2aab0e | 2614 | __HAL_TIM_DISABLE(htim); |
| mbed_official | 354:e67efb2aab0e | 2615 | |
| mbed_official | 354:e67efb2aab0e | 2616 | /* Change the htim state */ |
| mbed_official | 354:e67efb2aab0e | 2617 | htim->State = HAL_TIM_STATE_READY; |
| mbed_official | 354:e67efb2aab0e | 2618 | |
| mbed_official | 354:e67efb2aab0e | 2619 | /* Return function status */ |
| mbed_official | 354:e67efb2aab0e | 2620 | return HAL_OK; |
| mbed_official | 354:e67efb2aab0e | 2621 | } |
| mbed_official | 354:e67efb2aab0e | 2622 | |
| mbed_official | 354:e67efb2aab0e | 2623 | /** |
| mbed_official | 354:e67efb2aab0e | 2624 | * @} |
| mbed_official | 354:e67efb2aab0e | 2625 | */ |
| mbed_official | 354:e67efb2aab0e | 2626 | /** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management |
| mbed_official | 354:e67efb2aab0e | 2627 | * @brief IRQ handler management |
| mbed_official | 354:e67efb2aab0e | 2628 | * |
| mbed_official | 354:e67efb2aab0e | 2629 | @verbatim |
| mbed_official | 354:e67efb2aab0e | 2630 | ============================================================================== |
| mbed_official | 354:e67efb2aab0e | 2631 | ##### IRQ handler management ##### |
| mbed_official | 354:e67efb2aab0e | 2632 | ============================================================================== |
| mbed_official | 354:e67efb2aab0e | 2633 | [..] |
| mbed_official | 354:e67efb2aab0e | 2634 | This section provides Timer IRQ handler function. |
| mbed_official | 354:e67efb2aab0e | 2635 | |
| mbed_official | 354:e67efb2aab0e | 2636 | @endverbatim |
| mbed_official | 354:e67efb2aab0e | 2637 | * @{ |
| mbed_official | 354:e67efb2aab0e | 2638 | */ |
| mbed_official | 354:e67efb2aab0e | 2639 | /** |
| mbed_official | 354:e67efb2aab0e | 2640 | * @brief This function handles TIM interrupts requests. |
| mbed_official | 354:e67efb2aab0e | 2641 | * @param htim: TIM handle |
| mbed_official | 354:e67efb2aab0e | 2642 | * @retval None |
| mbed_official | 354:e67efb2aab0e | 2643 | */ |
| mbed_official | 354:e67efb2aab0e | 2644 | void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) |
| mbed_official | 354:e67efb2aab0e | 2645 | { |
| mbed_official | 354:e67efb2aab0e | 2646 | /* Capture compare 1 event */ |
| mbed_official | 354:e67efb2aab0e | 2647 | if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET) |
| mbed_official | 354:e67efb2aab0e | 2648 | { |
| mbed_official | 354:e67efb2aab0e | 2649 | if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_CC1) !=RESET) |
| mbed_official | 354:e67efb2aab0e | 2650 | { |
| mbed_official | 354:e67efb2aab0e | 2651 | { |
| mbed_official | 354:e67efb2aab0e | 2652 | __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1); |
| mbed_official | 354:e67efb2aab0e | 2653 | htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; |
| mbed_official | 354:e67efb2aab0e | 2654 | |
| mbed_official | 354:e67efb2aab0e | 2655 | /* Input capture event */ |
| mbed_official | 354:e67efb2aab0e | 2656 | if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00) |
| mbed_official | 354:e67efb2aab0e | 2657 | { |
| mbed_official | 354:e67efb2aab0e | 2658 | HAL_TIM_IC_CaptureCallback(htim); |
| mbed_official | 354:e67efb2aab0e | 2659 | } |
| mbed_official | 354:e67efb2aab0e | 2660 | /* Output compare event */ |
| mbed_official | 354:e67efb2aab0e | 2661 | else |
| mbed_official | 354:e67efb2aab0e | 2662 | { |
| mbed_official | 354:e67efb2aab0e | 2663 | HAL_TIM_OC_DelayElapsedCallback(htim); |
| mbed_official | 354:e67efb2aab0e | 2664 | HAL_TIM_PWM_PulseFinishedCallback(htim); |
| mbed_official | 354:e67efb2aab0e | 2665 | } |
| mbed_official | 354:e67efb2aab0e | 2666 | htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; |
| mbed_official | 354:e67efb2aab0e | 2667 | } |
| mbed_official | 354:e67efb2aab0e | 2668 | } |
| mbed_official | 354:e67efb2aab0e | 2669 | } |
| mbed_official | 354:e67efb2aab0e | 2670 | /* Capture compare 2 event */ |
| mbed_official | 354:e67efb2aab0e | 2671 | if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET) |
| mbed_official | 354:e67efb2aab0e | 2672 | { |
| mbed_official | 354:e67efb2aab0e | 2673 | if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_CC2) !=RESET) |
| mbed_official | 354:e67efb2aab0e | 2674 | { |
| mbed_official | 354:e67efb2aab0e | 2675 | __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2); |
| mbed_official | 354:e67efb2aab0e | 2676 | htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; |
| mbed_official | 354:e67efb2aab0e | 2677 | /* Input capture event */ |
| mbed_official | 354:e67efb2aab0e | 2678 | if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00) |
| mbed_official | 354:e67efb2aab0e | 2679 | { |
| mbed_official | 354:e67efb2aab0e | 2680 | HAL_TIM_IC_CaptureCallback(htim); |
| mbed_official | 354:e67efb2aab0e | 2681 | } |
| mbed_official | 354:e67efb2aab0e | 2682 | /* Output compare event */ |
| mbed_official | 354:e67efb2aab0e | 2683 | else |
| mbed_official | 354:e67efb2aab0e | 2684 | { |
| mbed_official | 354:e67efb2aab0e | 2685 | HAL_TIM_OC_DelayElapsedCallback(htim); |
| mbed_official | 354:e67efb2aab0e | 2686 | HAL_TIM_PWM_PulseFinishedCallback(htim); |
| mbed_official | 354:e67efb2aab0e | 2687 | } |
| mbed_official | 354:e67efb2aab0e | 2688 | htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; |
| mbed_official | 354:e67efb2aab0e | 2689 | } |
| mbed_official | 354:e67efb2aab0e | 2690 | } |
| mbed_official | 354:e67efb2aab0e | 2691 | /* Capture compare 3 event */ |
| mbed_official | 354:e67efb2aab0e | 2692 | if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET) |
| mbed_official | 354:e67efb2aab0e | 2693 | { |
| mbed_official | 354:e67efb2aab0e | 2694 | if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_CC3) !=RESET) |
| mbed_official | 354:e67efb2aab0e | 2695 | { |
| mbed_official | 354:e67efb2aab0e | 2696 | __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3); |
| mbed_official | 354:e67efb2aab0e | 2697 | htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; |
| mbed_official | 354:e67efb2aab0e | 2698 | /* Input capture event */ |
| mbed_official | 354:e67efb2aab0e | 2699 | if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00) |
| mbed_official | 354:e67efb2aab0e | 2700 | { |
| mbed_official | 354:e67efb2aab0e | 2701 | HAL_TIM_IC_CaptureCallback(htim); |
| mbed_official | 354:e67efb2aab0e | 2702 | } |
| mbed_official | 354:e67efb2aab0e | 2703 | /* Output compare event */ |
| mbed_official | 354:e67efb2aab0e | 2704 | else |
| mbed_official | 354:e67efb2aab0e | 2705 | { |
| mbed_official | 354:e67efb2aab0e | 2706 | HAL_TIM_OC_DelayElapsedCallback(htim); |
| mbed_official | 354:e67efb2aab0e | 2707 | HAL_TIM_PWM_PulseFinishedCallback(htim); |
| mbed_official | 354:e67efb2aab0e | 2708 | } |
| mbed_official | 354:e67efb2aab0e | 2709 | htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; |
| mbed_official | 354:e67efb2aab0e | 2710 | } |
| mbed_official | 354:e67efb2aab0e | 2711 | } |
| mbed_official | 354:e67efb2aab0e | 2712 | /* Capture compare 4 event */ |
| mbed_official | 354:e67efb2aab0e | 2713 | if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET) |
| mbed_official | 354:e67efb2aab0e | 2714 | { |
| mbed_official | 354:e67efb2aab0e | 2715 | if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_CC4) !=RESET) |
| mbed_official | 354:e67efb2aab0e | 2716 | { |
| mbed_official | 354:e67efb2aab0e | 2717 | __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4); |
| mbed_official | 354:e67efb2aab0e | 2718 | htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; |
| mbed_official | 354:e67efb2aab0e | 2719 | /* Input capture event */ |
| mbed_official | 354:e67efb2aab0e | 2720 | if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00) |
| mbed_official | 354:e67efb2aab0e | 2721 | { |
| mbed_official | 354:e67efb2aab0e | 2722 | HAL_TIM_IC_CaptureCallback(htim); |
| mbed_official | 354:e67efb2aab0e | 2723 | } |
| mbed_official | 354:e67efb2aab0e | 2724 | /* Output compare event */ |
| mbed_official | 354:e67efb2aab0e | 2725 | else |
| mbed_official | 354:e67efb2aab0e | 2726 | { |
| mbed_official | 354:e67efb2aab0e | 2727 | HAL_TIM_OC_DelayElapsedCallback(htim); |
| mbed_official | 354:e67efb2aab0e | 2728 | HAL_TIM_PWM_PulseFinishedCallback(htim); |
| mbed_official | 354:e67efb2aab0e | 2729 | } |
| mbed_official | 354:e67efb2aab0e | 2730 | htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; |
| mbed_official | 354:e67efb2aab0e | 2731 | } |
| mbed_official | 354:e67efb2aab0e | 2732 | } |
| mbed_official | 354:e67efb2aab0e | 2733 | /* TIM Update event */ |
| mbed_official | 354:e67efb2aab0e | 2734 | if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET) |
| mbed_official | 354:e67efb2aab0e | 2735 | { |
| mbed_official | 354:e67efb2aab0e | 2736 | if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_UPDATE) !=RESET) |
| mbed_official | 354:e67efb2aab0e | 2737 | { |
| mbed_official | 354:e67efb2aab0e | 2738 | __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE); |
| mbed_official | 354:e67efb2aab0e | 2739 | HAL_TIM_PeriodElapsedCallback(htim); |
| mbed_official | 354:e67efb2aab0e | 2740 | } |
| mbed_official | 354:e67efb2aab0e | 2741 | } |
| mbed_official | 354:e67efb2aab0e | 2742 | /* TIM Trigger detection event */ |
| mbed_official | 354:e67efb2aab0e | 2743 | if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET) |
| mbed_official | 354:e67efb2aab0e | 2744 | { |
| mbed_official | 354:e67efb2aab0e | 2745 | if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_TRIGGER) !=RESET) |
| mbed_official | 354:e67efb2aab0e | 2746 | { |
| mbed_official | 354:e67efb2aab0e | 2747 | __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER); |
| mbed_official | 354:e67efb2aab0e | 2748 | HAL_TIM_TriggerCallback(htim); |
| mbed_official | 354:e67efb2aab0e | 2749 | } |
| mbed_official | 354:e67efb2aab0e | 2750 | } |
| mbed_official | 354:e67efb2aab0e | 2751 | } |
| mbed_official | 354:e67efb2aab0e | 2752 | |
| mbed_official | 354:e67efb2aab0e | 2753 | /** |
| mbed_official | 354:e67efb2aab0e | 2754 | * @} |
| mbed_official | 354:e67efb2aab0e | 2755 | */ |
| mbed_official | 354:e67efb2aab0e | 2756 | |
| mbed_official | 354:e67efb2aab0e | 2757 | /** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions |
| mbed_official | 354:e67efb2aab0e | 2758 | * @brief Peripheral Control functions |
| mbed_official | 354:e67efb2aab0e | 2759 | * |
| mbed_official | 354:e67efb2aab0e | 2760 | @verbatim |
| mbed_official | 354:e67efb2aab0e | 2761 | ============================================================================== |
| mbed_official | 354:e67efb2aab0e | 2762 | ##### Peripheral Control functions ##### |
| mbed_official | 354:e67efb2aab0e | 2763 | ============================================================================== |
| mbed_official | 354:e67efb2aab0e | 2764 | [..] |
| mbed_official | 354:e67efb2aab0e | 2765 | This section provides functions allowing to: |
| mbed_official | 354:e67efb2aab0e | 2766 | (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode. |
| mbed_official | 354:e67efb2aab0e | 2767 | (+) Configure External Clock source. |
| mbed_official | 354:e67efb2aab0e | 2768 | (+) Configure Complementary channels, break features and dead time. |
| mbed_official | 354:e67efb2aab0e | 2769 | (+) Configure Master and the Slave synchronization. |
| mbed_official | 354:e67efb2aab0e | 2770 | (+) Configure the DMA Burst Mode. |
| mbed_official | 354:e67efb2aab0e | 2771 | |
| mbed_official | 354:e67efb2aab0e | 2772 | @endverbatim |
| mbed_official | 354:e67efb2aab0e | 2773 | * @{ |
| mbed_official | 354:e67efb2aab0e | 2774 | */ |
| mbed_official | 354:e67efb2aab0e | 2775 | |
| mbed_official | 354:e67efb2aab0e | 2776 | /** |
| mbed_official | 354:e67efb2aab0e | 2777 | * @brief Initializes the TIM Output Compare Channels according to the specified |
| mbed_official | 354:e67efb2aab0e | 2778 | * parameters in the TIM_OC_InitTypeDef. |
| mbed_official | 354:e67efb2aab0e | 2779 | * @param htim: TIM Output Compare handle |
| mbed_official | 354:e67efb2aab0e | 2780 | * @param sConfig: TIM Output Compare configuration structure |
| mbed_official | 354:e67efb2aab0e | 2781 | * @param Channel : TIM Channels to be enabled |
| mbed_official | 354:e67efb2aab0e | 2782 | * This parameter can be one of the following values: |
| mbed_official | 354:e67efb2aab0e | 2783 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| mbed_official | 354:e67efb2aab0e | 2784 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| mbed_official | 354:e67efb2aab0e | 2785 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
| mbed_official | 354:e67efb2aab0e | 2786 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
| mbed_official | 354:e67efb2aab0e | 2787 | * @retval HAL status |
| mbed_official | 354:e67efb2aab0e | 2788 | */ |
| mbed_official | 354:e67efb2aab0e | 2789 | HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel) |
| mbed_official | 354:e67efb2aab0e | 2790 | { |
| mbed_official | 354:e67efb2aab0e | 2791 | /* Check the parameters */ |
| mbed_official | 354:e67efb2aab0e | 2792 | assert_param(IS_TIM_CHANNELS(Channel)); |
| mbed_official | 354:e67efb2aab0e | 2793 | assert_param(IS_TIM_OC_MODE(sConfig->OCMode)); |
| mbed_official | 354:e67efb2aab0e | 2794 | assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); |
| mbed_official | 354:e67efb2aab0e | 2795 | assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode)); |
| mbed_official | 354:e67efb2aab0e | 2796 | |
| mbed_official | 354:e67efb2aab0e | 2797 | /* Check input state */ |
| mbed_official | 354:e67efb2aab0e | 2798 | __HAL_LOCK(htim); |
| mbed_official | 354:e67efb2aab0e | 2799 | |
| mbed_official | 354:e67efb2aab0e | 2800 | htim->State = HAL_TIM_STATE_BUSY; |
| mbed_official | 354:e67efb2aab0e | 2801 | |
| mbed_official | 354:e67efb2aab0e | 2802 | switch (Channel) |
| mbed_official | 354:e67efb2aab0e | 2803 | { |
| mbed_official | 354:e67efb2aab0e | 2804 | case TIM_CHANNEL_1: |
| mbed_official | 354:e67efb2aab0e | 2805 | { |
| mbed_official | 354:e67efb2aab0e | 2806 | assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); |
| mbed_official | 354:e67efb2aab0e | 2807 | /* Configure the TIM Channel 1 in Output Compare */ |
| mbed_official | 354:e67efb2aab0e | 2808 | TIM_OC1_SetConfig(htim->Instance, sConfig); |
| mbed_official | 354:e67efb2aab0e | 2809 | } |
| mbed_official | 354:e67efb2aab0e | 2810 | break; |
| mbed_official | 354:e67efb2aab0e | 2811 | |
| mbed_official | 354:e67efb2aab0e | 2812 | case TIM_CHANNEL_2: |
| mbed_official | 354:e67efb2aab0e | 2813 | { |
| mbed_official | 354:e67efb2aab0e | 2814 | assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); |
| mbed_official | 354:e67efb2aab0e | 2815 | /* Configure the TIM Channel 2 in Output Compare */ |
| mbed_official | 354:e67efb2aab0e | 2816 | TIM_OC2_SetConfig(htim->Instance, sConfig); |
| mbed_official | 354:e67efb2aab0e | 2817 | } |
| mbed_official | 354:e67efb2aab0e | 2818 | break; |
| mbed_official | 354:e67efb2aab0e | 2819 | |
| mbed_official | 354:e67efb2aab0e | 2820 | case TIM_CHANNEL_3: |
| mbed_official | 354:e67efb2aab0e | 2821 | { |
| mbed_official | 354:e67efb2aab0e | 2822 | assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); |
| mbed_official | 354:e67efb2aab0e | 2823 | /* Configure the TIM Channel 3 in Output Compare */ |
| mbed_official | 354:e67efb2aab0e | 2824 | TIM_OC3_SetConfig(htim->Instance, sConfig); |
| mbed_official | 354:e67efb2aab0e | 2825 | } |
| mbed_official | 354:e67efb2aab0e | 2826 | break; |
| mbed_official | 354:e67efb2aab0e | 2827 | |
| mbed_official | 354:e67efb2aab0e | 2828 | case TIM_CHANNEL_4: |
| mbed_official | 354:e67efb2aab0e | 2829 | { |
| mbed_official | 354:e67efb2aab0e | 2830 | assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); |
| mbed_official | 354:e67efb2aab0e | 2831 | /* Configure the TIM Channel 4 in Output Compare */ |
| mbed_official | 354:e67efb2aab0e | 2832 | TIM_OC4_SetConfig(htim->Instance, sConfig); |
| mbed_official | 354:e67efb2aab0e | 2833 | } |
| mbed_official | 354:e67efb2aab0e | 2834 | break; |
| mbed_official | 354:e67efb2aab0e | 2835 | |
| mbed_official | 354:e67efb2aab0e | 2836 | default: |
| mbed_official | 354:e67efb2aab0e | 2837 | break; |
| mbed_official | 354:e67efb2aab0e | 2838 | } |
| mbed_official | 354:e67efb2aab0e | 2839 | htim->State = HAL_TIM_STATE_READY; |
| mbed_official | 354:e67efb2aab0e | 2840 | |
| mbed_official | 354:e67efb2aab0e | 2841 | __HAL_UNLOCK(htim); |
| mbed_official | 354:e67efb2aab0e | 2842 | |
| mbed_official | 354:e67efb2aab0e | 2843 | return HAL_OK; |
| mbed_official | 354:e67efb2aab0e | 2844 | } |
| mbed_official | 354:e67efb2aab0e | 2845 | |
| mbed_official | 354:e67efb2aab0e | 2846 | /** |
| mbed_official | 354:e67efb2aab0e | 2847 | * @brief Initializes the TIM Input Capture Channels according to the specified |
| mbed_official | 354:e67efb2aab0e | 2848 | * parameters in the TIM_IC_InitTypeDef. |
| mbed_official | 354:e67efb2aab0e | 2849 | * @param htim: TIM IC handle |
| mbed_official | 354:e67efb2aab0e | 2850 | * @param sConfig: TIM Input Capture configuration structure |
| mbed_official | 354:e67efb2aab0e | 2851 | * @param Channel : TIM Channels to be enabled |
| mbed_official | 354:e67efb2aab0e | 2852 | * This parameter can be one of the following values: |
| mbed_official | 354:e67efb2aab0e | 2853 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| mbed_official | 354:e67efb2aab0e | 2854 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| mbed_official | 354:e67efb2aab0e | 2855 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
| mbed_official | 354:e67efb2aab0e | 2856 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
| mbed_official | 354:e67efb2aab0e | 2857 | * @retval HAL status |
| mbed_official | 354:e67efb2aab0e | 2858 | */ |
| mbed_official | 354:e67efb2aab0e | 2859 | HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel) |
| mbed_official | 354:e67efb2aab0e | 2860 | { |
| mbed_official | 354:e67efb2aab0e | 2861 | /* Check the parameters */ |
| mbed_official | 354:e67efb2aab0e | 2862 | assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); |
| mbed_official | 354:e67efb2aab0e | 2863 | assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity)); |
| mbed_official | 354:e67efb2aab0e | 2864 | assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection)); |
| mbed_official | 354:e67efb2aab0e | 2865 | assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler)); |
| mbed_official | 354:e67efb2aab0e | 2866 | assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter)); |
| mbed_official | 354:e67efb2aab0e | 2867 | |
| mbed_official | 354:e67efb2aab0e | 2868 | __HAL_LOCK(htim); |
| mbed_official | 354:e67efb2aab0e | 2869 | |
| mbed_official | 354:e67efb2aab0e | 2870 | htim->State = HAL_TIM_STATE_BUSY; |
| mbed_official | 354:e67efb2aab0e | 2871 | |
| mbed_official | 354:e67efb2aab0e | 2872 | if (Channel == TIM_CHANNEL_1) |
| mbed_official | 354:e67efb2aab0e | 2873 | { |
| mbed_official | 354:e67efb2aab0e | 2874 | /* TI1 Configuration */ |
| mbed_official | 354:e67efb2aab0e | 2875 | TIM_TI1_SetConfig(htim->Instance, |
| mbed_official | 354:e67efb2aab0e | 2876 | sConfig->ICPolarity, |
| mbed_official | 354:e67efb2aab0e | 2877 | sConfig->ICSelection, |
| mbed_official | 354:e67efb2aab0e | 2878 | sConfig->ICFilter); |
| mbed_official | 354:e67efb2aab0e | 2879 | |
| mbed_official | 354:e67efb2aab0e | 2880 | /* Reset the IC1PSC Bits */ |
| mbed_official | 354:e67efb2aab0e | 2881 | htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; |
| mbed_official | 354:e67efb2aab0e | 2882 | |
| mbed_official | 354:e67efb2aab0e | 2883 | /* Set the IC1PSC value */ |
| mbed_official | 354:e67efb2aab0e | 2884 | htim->Instance->CCMR1 |= sConfig->ICPrescaler; |
| mbed_official | 354:e67efb2aab0e | 2885 | } |
| mbed_official | 354:e67efb2aab0e | 2886 | else if (Channel == TIM_CHANNEL_2) |
| mbed_official | 354:e67efb2aab0e | 2887 | { |
| mbed_official | 354:e67efb2aab0e | 2888 | /* TI2 Configuration */ |
| mbed_official | 354:e67efb2aab0e | 2889 | assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); |
| mbed_official | 354:e67efb2aab0e | 2890 | |
| mbed_official | 354:e67efb2aab0e | 2891 | TIM_TI2_SetConfig(htim->Instance, |
| mbed_official | 354:e67efb2aab0e | 2892 | sConfig->ICPolarity, |
| mbed_official | 354:e67efb2aab0e | 2893 | sConfig->ICSelection, |
| mbed_official | 354:e67efb2aab0e | 2894 | sConfig->ICFilter); |
| mbed_official | 354:e67efb2aab0e | 2895 | |
| mbed_official | 354:e67efb2aab0e | 2896 | /* Reset the IC2PSC Bits */ |
| mbed_official | 354:e67efb2aab0e | 2897 | htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; |
| mbed_official | 354:e67efb2aab0e | 2898 | |
| mbed_official | 354:e67efb2aab0e | 2899 | /* Set the IC2PSC value */ |
| mbed_official | 354:e67efb2aab0e | 2900 | htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8); |
| mbed_official | 354:e67efb2aab0e | 2901 | } |
| mbed_official | 354:e67efb2aab0e | 2902 | else if (Channel == TIM_CHANNEL_3) |
| mbed_official | 354:e67efb2aab0e | 2903 | { |
| mbed_official | 354:e67efb2aab0e | 2904 | /* TI3 Configuration */ |
| mbed_official | 354:e67efb2aab0e | 2905 | assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); |
| mbed_official | 354:e67efb2aab0e | 2906 | |
| mbed_official | 354:e67efb2aab0e | 2907 | TIM_TI3_SetConfig(htim->Instance, |
| mbed_official | 354:e67efb2aab0e | 2908 | sConfig->ICPolarity, |
| mbed_official | 354:e67efb2aab0e | 2909 | sConfig->ICSelection, |
| mbed_official | 354:e67efb2aab0e | 2910 | sConfig->ICFilter); |
| mbed_official | 354:e67efb2aab0e | 2911 | |
| mbed_official | 354:e67efb2aab0e | 2912 | /* Reset the IC3PSC Bits */ |
| mbed_official | 354:e67efb2aab0e | 2913 | htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC; |
| mbed_official | 354:e67efb2aab0e | 2914 | |
| mbed_official | 354:e67efb2aab0e | 2915 | /* Set the IC3PSC value */ |
| mbed_official | 354:e67efb2aab0e | 2916 | htim->Instance->CCMR2 |= sConfig->ICPrescaler; |
| mbed_official | 354:e67efb2aab0e | 2917 | } |
| mbed_official | 354:e67efb2aab0e | 2918 | else |
| mbed_official | 354:e67efb2aab0e | 2919 | { |
| mbed_official | 354:e67efb2aab0e | 2920 | /* TI4 Configuration */ |
| mbed_official | 354:e67efb2aab0e | 2921 | assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); |
| mbed_official | 354:e67efb2aab0e | 2922 | |
| mbed_official | 354:e67efb2aab0e | 2923 | TIM_TI4_SetConfig(htim->Instance, |
| mbed_official | 354:e67efb2aab0e | 2924 | sConfig->ICPolarity, |
| mbed_official | 354:e67efb2aab0e | 2925 | sConfig->ICSelection, |
| mbed_official | 354:e67efb2aab0e | 2926 | sConfig->ICFilter); |
| mbed_official | 354:e67efb2aab0e | 2927 | |
| mbed_official | 354:e67efb2aab0e | 2928 | /* Reset the IC4PSC Bits */ |
| mbed_official | 354:e67efb2aab0e | 2929 | htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC; |
| mbed_official | 354:e67efb2aab0e | 2930 | |
| mbed_official | 354:e67efb2aab0e | 2931 | /* Set the IC4PSC value */ |
| mbed_official | 354:e67efb2aab0e | 2932 | htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8); |
| mbed_official | 354:e67efb2aab0e | 2933 | } |
| mbed_official | 354:e67efb2aab0e | 2934 | |
| mbed_official | 354:e67efb2aab0e | 2935 | htim->State = HAL_TIM_STATE_READY; |
| mbed_official | 354:e67efb2aab0e | 2936 | |
| mbed_official | 354:e67efb2aab0e | 2937 | __HAL_UNLOCK(htim); |
| mbed_official | 354:e67efb2aab0e | 2938 | |
| mbed_official | 354:e67efb2aab0e | 2939 | return HAL_OK; |
| mbed_official | 354:e67efb2aab0e | 2940 | } |
| mbed_official | 354:e67efb2aab0e | 2941 | |
| mbed_official | 354:e67efb2aab0e | 2942 | /** |
| mbed_official | 354:e67efb2aab0e | 2943 | * @brief Initializes the TIM PWM channels according to the specified |
| mbed_official | 354:e67efb2aab0e | 2944 | * parameters in the TIM_OC_InitTypeDef. |
| mbed_official | 354:e67efb2aab0e | 2945 | * @param htim: TIM handle |
| mbed_official | 354:e67efb2aab0e | 2946 | * @param sConfig: TIM PWM configuration structure |
| mbed_official | 354:e67efb2aab0e | 2947 | * @param Channel : TIM Channels to be enabled |
| mbed_official | 354:e67efb2aab0e | 2948 | * This parameter can be one of the following values: |
| mbed_official | 354:e67efb2aab0e | 2949 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| mbed_official | 354:e67efb2aab0e | 2950 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| mbed_official | 354:e67efb2aab0e | 2951 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
| mbed_official | 354:e67efb2aab0e | 2952 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
| mbed_official | 354:e67efb2aab0e | 2953 | * @retval HAL status |
| mbed_official | 354:e67efb2aab0e | 2954 | */ |
| mbed_official | 354:e67efb2aab0e | 2955 | HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel) |
| mbed_official | 354:e67efb2aab0e | 2956 | { |
| mbed_official | 354:e67efb2aab0e | 2957 | /* Check the parameters */ |
| mbed_official | 354:e67efb2aab0e | 2958 | assert_param(IS_TIM_CHANNELS(Channel)); |
| mbed_official | 354:e67efb2aab0e | 2959 | assert_param(IS_TIM_PWM_MODE(sConfig->OCMode)); |
| mbed_official | 354:e67efb2aab0e | 2960 | assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); |
| mbed_official | 354:e67efb2aab0e | 2961 | |
| mbed_official | 354:e67efb2aab0e | 2962 | __HAL_LOCK(htim); |
| mbed_official | 354:e67efb2aab0e | 2963 | |
| mbed_official | 354:e67efb2aab0e | 2964 | htim->State = HAL_TIM_STATE_BUSY; |
| mbed_official | 354:e67efb2aab0e | 2965 | |
| mbed_official | 354:e67efb2aab0e | 2966 | switch (Channel) |
| mbed_official | 354:e67efb2aab0e | 2967 | { |
| mbed_official | 354:e67efb2aab0e | 2968 | case TIM_CHANNEL_1: |
| mbed_official | 354:e67efb2aab0e | 2969 | { |
| mbed_official | 354:e67efb2aab0e | 2970 | assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); |
| mbed_official | 354:e67efb2aab0e | 2971 | /* Configure the Channel 1 in PWM mode */ |
| mbed_official | 354:e67efb2aab0e | 2972 | TIM_OC1_SetConfig(htim->Instance, sConfig); |
| mbed_official | 354:e67efb2aab0e | 2973 | |
| mbed_official | 354:e67efb2aab0e | 2974 | /* Set the Preload enable bit for channel1 */ |
| mbed_official | 354:e67efb2aab0e | 2975 | htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE; |
| mbed_official | 354:e67efb2aab0e | 2976 | |
| mbed_official | 354:e67efb2aab0e | 2977 | /* Configure the Output Fast mode */ |
| mbed_official | 354:e67efb2aab0e | 2978 | htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE; |
| mbed_official | 354:e67efb2aab0e | 2979 | htim->Instance->CCMR1 |= sConfig->OCFastMode; |
| mbed_official | 354:e67efb2aab0e | 2980 | } |
| mbed_official | 354:e67efb2aab0e | 2981 | break; |
| mbed_official | 354:e67efb2aab0e | 2982 | |
| mbed_official | 354:e67efb2aab0e | 2983 | case TIM_CHANNEL_2: |
| mbed_official | 354:e67efb2aab0e | 2984 | { |
| mbed_official | 354:e67efb2aab0e | 2985 | assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); |
| mbed_official | 354:e67efb2aab0e | 2986 | /* Configure the Channel 2 in PWM mode */ |
| mbed_official | 354:e67efb2aab0e | 2987 | TIM_OC2_SetConfig(htim->Instance, sConfig); |
| mbed_official | 354:e67efb2aab0e | 2988 | |
| mbed_official | 354:e67efb2aab0e | 2989 | /* Set the Preload enable bit for channel2 */ |
| mbed_official | 354:e67efb2aab0e | 2990 | htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE; |
| mbed_official | 354:e67efb2aab0e | 2991 | |
| mbed_official | 354:e67efb2aab0e | 2992 | /* Configure the Output Fast mode */ |
| mbed_official | 354:e67efb2aab0e | 2993 | htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE; |
| mbed_official | 354:e67efb2aab0e | 2994 | htim->Instance->CCMR1 |= sConfig->OCFastMode << 8; |
| mbed_official | 354:e67efb2aab0e | 2995 | } |
| mbed_official | 354:e67efb2aab0e | 2996 | break; |
| mbed_official | 354:e67efb2aab0e | 2997 | |
| mbed_official | 354:e67efb2aab0e | 2998 | case TIM_CHANNEL_3: |
| mbed_official | 354:e67efb2aab0e | 2999 | { |
| mbed_official | 354:e67efb2aab0e | 3000 | assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); |
| mbed_official | 354:e67efb2aab0e | 3001 | /* Configure the Channel 3 in PWM mode */ |
| mbed_official | 354:e67efb2aab0e | 3002 | TIM_OC3_SetConfig(htim->Instance, sConfig); |
| mbed_official | 354:e67efb2aab0e | 3003 | |
| mbed_official | 354:e67efb2aab0e | 3004 | /* Set the Preload enable bit for channel3 */ |
| mbed_official | 354:e67efb2aab0e | 3005 | htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE; |
| mbed_official | 354:e67efb2aab0e | 3006 | |
| mbed_official | 354:e67efb2aab0e | 3007 | /* Configure the Output Fast mode */ |
| mbed_official | 354:e67efb2aab0e | 3008 | htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE; |
| mbed_official | 354:e67efb2aab0e | 3009 | htim->Instance->CCMR2 |= sConfig->OCFastMode; |
| mbed_official | 354:e67efb2aab0e | 3010 | } |
| mbed_official | 354:e67efb2aab0e | 3011 | break; |
| mbed_official | 354:e67efb2aab0e | 3012 | |
| mbed_official | 354:e67efb2aab0e | 3013 | case TIM_CHANNEL_4: |
| mbed_official | 354:e67efb2aab0e | 3014 | { |
| mbed_official | 354:e67efb2aab0e | 3015 | assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); |
| mbed_official | 354:e67efb2aab0e | 3016 | /* Configure the Channel 4 in PWM mode */ |
| mbed_official | 354:e67efb2aab0e | 3017 | TIM_OC4_SetConfig(htim->Instance, sConfig); |
| mbed_official | 354:e67efb2aab0e | 3018 | |
| mbed_official | 354:e67efb2aab0e | 3019 | /* Set the Preload enable bit for channel4 */ |
| mbed_official | 354:e67efb2aab0e | 3020 | htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE; |
| mbed_official | 354:e67efb2aab0e | 3021 | |
| mbed_official | 354:e67efb2aab0e | 3022 | /* Configure the Output Fast mode */ |
| mbed_official | 354:e67efb2aab0e | 3023 | htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE; |
| mbed_official | 354:e67efb2aab0e | 3024 | htim->Instance->CCMR2 |= sConfig->OCFastMode << 8; |
| mbed_official | 354:e67efb2aab0e | 3025 | } |
| mbed_official | 354:e67efb2aab0e | 3026 | break; |
| mbed_official | 354:e67efb2aab0e | 3027 | |
| mbed_official | 354:e67efb2aab0e | 3028 | default: |
| mbed_official | 354:e67efb2aab0e | 3029 | break; |
| mbed_official | 354:e67efb2aab0e | 3030 | } |
| mbed_official | 354:e67efb2aab0e | 3031 | |
| mbed_official | 354:e67efb2aab0e | 3032 | htim->State = HAL_TIM_STATE_READY; |
| mbed_official | 354:e67efb2aab0e | 3033 | |
| mbed_official | 354:e67efb2aab0e | 3034 | __HAL_UNLOCK(htim); |
| mbed_official | 354:e67efb2aab0e | 3035 | |
| mbed_official | 354:e67efb2aab0e | 3036 | return HAL_OK; |
| mbed_official | 354:e67efb2aab0e | 3037 | } |
| mbed_official | 354:e67efb2aab0e | 3038 | |
| mbed_official | 354:e67efb2aab0e | 3039 | /** |
| mbed_official | 354:e67efb2aab0e | 3040 | * @brief Initializes the TIM One Pulse Channels according to the specified |
| mbed_official | 354:e67efb2aab0e | 3041 | * parameters in the TIM_OnePulse_InitTypeDef. |
| mbed_official | 354:e67efb2aab0e | 3042 | * @param htim: TIM One Pulse handle |
| mbed_official | 354:e67efb2aab0e | 3043 | * @param sConfig: TIM One Pulse configuration structure |
| mbed_official | 354:e67efb2aab0e | 3044 | * @param OutputChannel : TIM Channels to be enabled |
| mbed_official | 354:e67efb2aab0e | 3045 | * This parameter can be one of the following values: |
| mbed_official | 354:e67efb2aab0e | 3046 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| mbed_official | 354:e67efb2aab0e | 3047 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| mbed_official | 354:e67efb2aab0e | 3048 | * @param InputChannel : TIM Channels to be enabled |
| mbed_official | 354:e67efb2aab0e | 3049 | * This parameter can be one of the following values: |
| mbed_official | 354:e67efb2aab0e | 3050 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| mbed_official | 354:e67efb2aab0e | 3051 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| mbed_official | 354:e67efb2aab0e | 3052 | * @retval HAL status |
| mbed_official | 354:e67efb2aab0e | 3053 | */ |
| mbed_official | 354:e67efb2aab0e | 3054 | HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel) |
| mbed_official | 354:e67efb2aab0e | 3055 | { |
| mbed_official | 354:e67efb2aab0e | 3056 | TIM_OC_InitTypeDef temp1; |
| mbed_official | 354:e67efb2aab0e | 3057 | |
| mbed_official | 354:e67efb2aab0e | 3058 | /* Check the parameters */ |
| mbed_official | 354:e67efb2aab0e | 3059 | assert_param(IS_TIM_OPM_CHANNELS(OutputChannel)); |
| mbed_official | 354:e67efb2aab0e | 3060 | assert_param(IS_TIM_OPM_CHANNELS(InputChannel)); |
| mbed_official | 354:e67efb2aab0e | 3061 | |
| mbed_official | 354:e67efb2aab0e | 3062 | if(OutputChannel != InputChannel) |
| mbed_official | 354:e67efb2aab0e | 3063 | { |
| mbed_official | 354:e67efb2aab0e | 3064 | __HAL_LOCK(htim); |
| mbed_official | 354:e67efb2aab0e | 3065 | |
| mbed_official | 354:e67efb2aab0e | 3066 | htim->State = HAL_TIM_STATE_BUSY; |
| mbed_official | 354:e67efb2aab0e | 3067 | |
| mbed_official | 354:e67efb2aab0e | 3068 | /* Extract the Ouput compare configuration from sConfig structure */ |
| mbed_official | 354:e67efb2aab0e | 3069 | temp1.OCMode = sConfig->OCMode; |
| mbed_official | 354:e67efb2aab0e | 3070 | temp1.Pulse = sConfig->Pulse; |
| mbed_official | 354:e67efb2aab0e | 3071 | temp1.OCPolarity = sConfig->OCPolarity; |
| mbed_official | 354:e67efb2aab0e | 3072 | temp1.OCIdleState = sConfig->OCIdleState; |
| mbed_official | 354:e67efb2aab0e | 3073 | |
| mbed_official | 354:e67efb2aab0e | 3074 | switch (OutputChannel) |
| mbed_official | 354:e67efb2aab0e | 3075 | { |
| mbed_official | 354:e67efb2aab0e | 3076 | case TIM_CHANNEL_1: |
| mbed_official | 354:e67efb2aab0e | 3077 | { |
| mbed_official | 354:e67efb2aab0e | 3078 | assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); |
| mbed_official | 354:e67efb2aab0e | 3079 | |
| mbed_official | 354:e67efb2aab0e | 3080 | TIM_OC1_SetConfig(htim->Instance, &temp1); |
| mbed_official | 354:e67efb2aab0e | 3081 | } |
| mbed_official | 354:e67efb2aab0e | 3082 | break; |
| mbed_official | 354:e67efb2aab0e | 3083 | case TIM_CHANNEL_2: |
| mbed_official | 354:e67efb2aab0e | 3084 | { |
| mbed_official | 354:e67efb2aab0e | 3085 | assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); |
| mbed_official | 354:e67efb2aab0e | 3086 | |
| mbed_official | 354:e67efb2aab0e | 3087 | TIM_OC2_SetConfig(htim->Instance, &temp1); |
| mbed_official | 354:e67efb2aab0e | 3088 | } |
| mbed_official | 354:e67efb2aab0e | 3089 | break; |
| mbed_official | 354:e67efb2aab0e | 3090 | default: |
| mbed_official | 354:e67efb2aab0e | 3091 | break; |
| mbed_official | 354:e67efb2aab0e | 3092 | } |
| mbed_official | 354:e67efb2aab0e | 3093 | switch (InputChannel) |
| mbed_official | 354:e67efb2aab0e | 3094 | { |
| mbed_official | 354:e67efb2aab0e | 3095 | case TIM_CHANNEL_1: |
| mbed_official | 354:e67efb2aab0e | 3096 | { |
| mbed_official | 354:e67efb2aab0e | 3097 | assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); |
| mbed_official | 354:e67efb2aab0e | 3098 | |
| mbed_official | 354:e67efb2aab0e | 3099 | TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity, |
| mbed_official | 354:e67efb2aab0e | 3100 | sConfig->ICSelection, sConfig->ICFilter); |
| mbed_official | 354:e67efb2aab0e | 3101 | |
| mbed_official | 354:e67efb2aab0e | 3102 | /* Reset the IC1PSC Bits */ |
| mbed_official | 354:e67efb2aab0e | 3103 | htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; |
| mbed_official | 354:e67efb2aab0e | 3104 | |
| mbed_official | 354:e67efb2aab0e | 3105 | /* Select the Trigger source */ |
| mbed_official | 354:e67efb2aab0e | 3106 | htim->Instance->SMCR &= ~TIM_SMCR_TS; |
| mbed_official | 354:e67efb2aab0e | 3107 | htim->Instance->SMCR |= TIM_TS_TI1FP1; |
| mbed_official | 354:e67efb2aab0e | 3108 | |
| mbed_official | 354:e67efb2aab0e | 3109 | /* Select the Slave Mode */ |
| mbed_official | 354:e67efb2aab0e | 3110 | htim->Instance->SMCR &= ~TIM_SMCR_SMS; |
| mbed_official | 354:e67efb2aab0e | 3111 | htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; |
| mbed_official | 354:e67efb2aab0e | 3112 | } |
| mbed_official | 354:e67efb2aab0e | 3113 | break; |
| mbed_official | 354:e67efb2aab0e | 3114 | case TIM_CHANNEL_2: |
| mbed_official | 354:e67efb2aab0e | 3115 | { |
| mbed_official | 354:e67efb2aab0e | 3116 | assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); |
| mbed_official | 354:e67efb2aab0e | 3117 | |
| mbed_official | 354:e67efb2aab0e | 3118 | TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity, |
| mbed_official | 354:e67efb2aab0e | 3119 | sConfig->ICSelection, sConfig->ICFilter); |
| mbed_official | 354:e67efb2aab0e | 3120 | |
| mbed_official | 354:e67efb2aab0e | 3121 | /* Reset the IC2PSC Bits */ |
| mbed_official | 354:e67efb2aab0e | 3122 | htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; |
| mbed_official | 354:e67efb2aab0e | 3123 | |
| mbed_official | 354:e67efb2aab0e | 3124 | /* Select the Trigger source */ |
| mbed_official | 354:e67efb2aab0e | 3125 | htim->Instance->SMCR &= ~TIM_SMCR_TS; |
| mbed_official | 354:e67efb2aab0e | 3126 | htim->Instance->SMCR |= TIM_TS_TI2FP2; |
| mbed_official | 354:e67efb2aab0e | 3127 | |
| mbed_official | 354:e67efb2aab0e | 3128 | /* Select the Slave Mode */ |
| mbed_official | 354:e67efb2aab0e | 3129 | htim->Instance->SMCR &= ~TIM_SMCR_SMS; |
| mbed_official | 354:e67efb2aab0e | 3130 | htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; |
| mbed_official | 354:e67efb2aab0e | 3131 | } |
| mbed_official | 354:e67efb2aab0e | 3132 | break; |
| mbed_official | 354:e67efb2aab0e | 3133 | |
| mbed_official | 354:e67efb2aab0e | 3134 | default: |
| mbed_official | 354:e67efb2aab0e | 3135 | break; |
| mbed_official | 354:e67efb2aab0e | 3136 | } |
| mbed_official | 354:e67efb2aab0e | 3137 | |
| mbed_official | 354:e67efb2aab0e | 3138 | htim->State = HAL_TIM_STATE_READY; |
| mbed_official | 354:e67efb2aab0e | 3139 | |
| mbed_official | 354:e67efb2aab0e | 3140 | __HAL_UNLOCK(htim); |
| mbed_official | 354:e67efb2aab0e | 3141 | |
| mbed_official | 354:e67efb2aab0e | 3142 | return HAL_OK; |
| mbed_official | 354:e67efb2aab0e | 3143 | } |
| mbed_official | 354:e67efb2aab0e | 3144 | else |
| mbed_official | 354:e67efb2aab0e | 3145 | { |
| mbed_official | 354:e67efb2aab0e | 3146 | return HAL_ERROR; |
| mbed_official | 354:e67efb2aab0e | 3147 | } |
| mbed_official | 354:e67efb2aab0e | 3148 | } |
| mbed_official | 354:e67efb2aab0e | 3149 | |
| mbed_official | 354:e67efb2aab0e | 3150 | /** |
| mbed_official | 354:e67efb2aab0e | 3151 | * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral |
| mbed_official | 354:e67efb2aab0e | 3152 | * @param htim: TIM handle |
| mbed_official | 354:e67efb2aab0e | 3153 | * @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data write |
| mbed_official | 354:e67efb2aab0e | 3154 | * This parameters can be on of the following values: |
| mbed_official | 354:e67efb2aab0e | 3155 | * @arg TIM_DMABase_CR1 |
| mbed_official | 354:e67efb2aab0e | 3156 | * @arg TIM_DMABase_CR2 |
| mbed_official | 354:e67efb2aab0e | 3157 | * @arg TIM_DMABase_SMCR |
| mbed_official | 354:e67efb2aab0e | 3158 | * @arg TIM_DMABase_DIER |
| mbed_official | 354:e67efb2aab0e | 3159 | * @arg TIM_DMABase_SR |
| mbed_official | 354:e67efb2aab0e | 3160 | * @arg TIM_DMABase_EGR |
| mbed_official | 354:e67efb2aab0e | 3161 | * @arg TIM_DMABase_CCMR1 |
| mbed_official | 354:e67efb2aab0e | 3162 | * @arg TIM_DMABase_CCMR2 |
| mbed_official | 354:e67efb2aab0e | 3163 | * @arg TIM_DMABase_CCER |
| mbed_official | 354:e67efb2aab0e | 3164 | * @arg TIM_DMABase_CNT |
| mbed_official | 354:e67efb2aab0e | 3165 | * @arg TIM_DMABase_PSC |
| mbed_official | 354:e67efb2aab0e | 3166 | * @arg TIM_DMABase_ARR |
| mbed_official | 354:e67efb2aab0e | 3167 | * @arg TIM_DMABase_CCR1 |
| mbed_official | 354:e67efb2aab0e | 3168 | * @arg TIM_DMABase_CCR2 |
| mbed_official | 354:e67efb2aab0e | 3169 | * @arg TIM_DMABase_CCR3 |
| mbed_official | 354:e67efb2aab0e | 3170 | * @arg TIM_DMABase_CCR4 |
| mbed_official | 354:e67efb2aab0e | 3171 | * @arg TIM_DMABase_DCR |
| mbed_official | 354:e67efb2aab0e | 3172 | * @param BurstRequestSrc: TIM DMA Request sources |
| mbed_official | 354:e67efb2aab0e | 3173 | * This parameters can be on of the following values: |
| mbed_official | 354:e67efb2aab0e | 3174 | * @arg TIM_DMA_UPDATE: TIM update Interrupt source |
| mbed_official | 354:e67efb2aab0e | 3175 | * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source |
| mbed_official | 354:e67efb2aab0e | 3176 | * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source |
| mbed_official | 354:e67efb2aab0e | 3177 | * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source |
| mbed_official | 354:e67efb2aab0e | 3178 | * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source |
| mbed_official | 354:e67efb2aab0e | 3179 | * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source |
| mbed_official | 354:e67efb2aab0e | 3180 | * @param BurstBuffer: The Buffer address. |
| mbed_official | 354:e67efb2aab0e | 3181 | * @param BurstLength: DMA Burst length. This parameter can be one value |
| mbed_official | 354:e67efb2aab0e | 3182 | * between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers. |
| mbed_official | 354:e67efb2aab0e | 3183 | * @retval HAL status |
| mbed_official | 354:e67efb2aab0e | 3184 | */ |
| mbed_official | 354:e67efb2aab0e | 3185 | HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, |
| mbed_official | 354:e67efb2aab0e | 3186 | uint32_t* BurstBuffer, uint32_t BurstLength) |
| mbed_official | 354:e67efb2aab0e | 3187 | { |
| mbed_official | 354:e67efb2aab0e | 3188 | /* Check the parameters */ |
| mbed_official | 354:e67efb2aab0e | 3189 | assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); |
| mbed_official | 354:e67efb2aab0e | 3190 | assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); |
| mbed_official | 354:e67efb2aab0e | 3191 | assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); |
| mbed_official | 354:e67efb2aab0e | 3192 | assert_param(IS_TIM_DMA_LENGTH(BurstLength)); |
| mbed_official | 354:e67efb2aab0e | 3193 | |
| mbed_official | 354:e67efb2aab0e | 3194 | if((htim->State == HAL_TIM_STATE_BUSY)) |
| mbed_official | 354:e67efb2aab0e | 3195 | { |
| mbed_official | 354:e67efb2aab0e | 3196 | return HAL_BUSY; |
| mbed_official | 354:e67efb2aab0e | 3197 | } |
| mbed_official | 354:e67efb2aab0e | 3198 | else if((htim->State == HAL_TIM_STATE_READY)) |
| mbed_official | 354:e67efb2aab0e | 3199 | { |
| mbed_official | 354:e67efb2aab0e | 3200 | if((BurstBuffer == 0 ) && (BurstLength > 0)) |
| mbed_official | 354:e67efb2aab0e | 3201 | { |
| mbed_official | 354:e67efb2aab0e | 3202 | return HAL_ERROR; |
| mbed_official | 354:e67efb2aab0e | 3203 | } |
| mbed_official | 354:e67efb2aab0e | 3204 | else |
| mbed_official | 354:e67efb2aab0e | 3205 | { |
| mbed_official | 354:e67efb2aab0e | 3206 | htim->State = HAL_TIM_STATE_BUSY; |
| mbed_official | 354:e67efb2aab0e | 3207 | } |
| mbed_official | 354:e67efb2aab0e | 3208 | } |
| mbed_official | 354:e67efb2aab0e | 3209 | else |
| mbed_official | 354:e67efb2aab0e | 3210 | { |
| mbed_official | 354:e67efb2aab0e | 3211 | return HAL_ERROR; |
| mbed_official | 354:e67efb2aab0e | 3212 | } |
| mbed_official | 354:e67efb2aab0e | 3213 | |
| mbed_official | 354:e67efb2aab0e | 3214 | switch(BurstRequestSrc) |
| mbed_official | 354:e67efb2aab0e | 3215 | { |
| mbed_official | 354:e67efb2aab0e | 3216 | case TIM_DMA_UPDATE: |
| mbed_official | 354:e67efb2aab0e | 3217 | { |
| mbed_official | 354:e67efb2aab0e | 3218 | /* Set the DMA Period elapsed callback */ |
| mbed_official | 354:e67efb2aab0e | 3219 | htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; |
| mbed_official | 354:e67efb2aab0e | 3220 | |
| mbed_official | 354:e67efb2aab0e | 3221 | /* Set the DMA error callback */ |
| mbed_official | 354:e67efb2aab0e | 3222 | htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; |
| mbed_official | 354:e67efb2aab0e | 3223 | |
| mbed_official | 354:e67efb2aab0e | 3224 | /* Enable the DMA channel */ |
| mbed_official | 354:e67efb2aab0e | 3225 | HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); |
| mbed_official | 354:e67efb2aab0e | 3226 | } |
| mbed_official | 354:e67efb2aab0e | 3227 | break; |
| mbed_official | 354:e67efb2aab0e | 3228 | case TIM_DMA_CC1: |
| mbed_official | 354:e67efb2aab0e | 3229 | { |
| mbed_official | 354:e67efb2aab0e | 3230 | /* Set the DMA Period elapsed callback */ |
| mbed_official | 354:e67efb2aab0e | 3231 | htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; |
| mbed_official | 354:e67efb2aab0e | 3232 | |
| mbed_official | 354:e67efb2aab0e | 3233 | /* Set the DMA error callback */ |
| mbed_official | 354:e67efb2aab0e | 3234 | htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; |
| mbed_official | 354:e67efb2aab0e | 3235 | |
| mbed_official | 354:e67efb2aab0e | 3236 | /* Enable the DMA channel */ |
| mbed_official | 354:e67efb2aab0e | 3237 | HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); |
| mbed_official | 354:e67efb2aab0e | 3238 | } |
| mbed_official | 354:e67efb2aab0e | 3239 | break; |
| mbed_official | 354:e67efb2aab0e | 3240 | case TIM_DMA_CC2: |
| mbed_official | 354:e67efb2aab0e | 3241 | { |
| mbed_official | 354:e67efb2aab0e | 3242 | /* Set the DMA Period elapsed callback */ |
| mbed_official | 354:e67efb2aab0e | 3243 | htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; |
| mbed_official | 354:e67efb2aab0e | 3244 | |
| mbed_official | 354:e67efb2aab0e | 3245 | /* Set the DMA error callback */ |
| mbed_official | 354:e67efb2aab0e | 3246 | htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; |
| mbed_official | 354:e67efb2aab0e | 3247 | |
| mbed_official | 354:e67efb2aab0e | 3248 | /* Enable the DMA channel */ |
| mbed_official | 354:e67efb2aab0e | 3249 | HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); |
| mbed_official | 354:e67efb2aab0e | 3250 | } |
| mbed_official | 354:e67efb2aab0e | 3251 | break; |
| mbed_official | 354:e67efb2aab0e | 3252 | case TIM_DMA_CC3: |
| mbed_official | 354:e67efb2aab0e | 3253 | { |
| mbed_official | 354:e67efb2aab0e | 3254 | /* Set the DMA Period elapsed callback */ |
| mbed_official | 354:e67efb2aab0e | 3255 | htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; |
| mbed_official | 354:e67efb2aab0e | 3256 | |
| mbed_official | 354:e67efb2aab0e | 3257 | /* Set the DMA error callback */ |
| mbed_official | 354:e67efb2aab0e | 3258 | htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; |
| mbed_official | 354:e67efb2aab0e | 3259 | |
| mbed_official | 354:e67efb2aab0e | 3260 | /* Enable the DMA channel */ |
| mbed_official | 354:e67efb2aab0e | 3261 | HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); |
| mbed_official | 354:e67efb2aab0e | 3262 | } |
| mbed_official | 354:e67efb2aab0e | 3263 | break; |
| mbed_official | 354:e67efb2aab0e | 3264 | case TIM_DMA_CC4: |
| mbed_official | 354:e67efb2aab0e | 3265 | { |
| mbed_official | 354:e67efb2aab0e | 3266 | /* Set the DMA Period elapsed callback */ |
| mbed_official | 354:e67efb2aab0e | 3267 | htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; |
| mbed_official | 354:e67efb2aab0e | 3268 | |
| mbed_official | 354:e67efb2aab0e | 3269 | /* Set the DMA error callback */ |
| mbed_official | 354:e67efb2aab0e | 3270 | htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; |
| mbed_official | 354:e67efb2aab0e | 3271 | |
| mbed_official | 354:e67efb2aab0e | 3272 | /* Enable the DMA channel */ |
| mbed_official | 354:e67efb2aab0e | 3273 | HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); |
| mbed_official | 354:e67efb2aab0e | 3274 | } |
| mbed_official | 354:e67efb2aab0e | 3275 | break; |
| mbed_official | 354:e67efb2aab0e | 3276 | case TIM_DMA_TRIGGER: |
| mbed_official | 354:e67efb2aab0e | 3277 | { |
| mbed_official | 354:e67efb2aab0e | 3278 | /* Set the DMA Period elapsed callback */ |
| mbed_official | 354:e67efb2aab0e | 3279 | htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt; |
| mbed_official | 354:e67efb2aab0e | 3280 | |
| mbed_official | 354:e67efb2aab0e | 3281 | /* Set the DMA error callback */ |
| mbed_official | 354:e67efb2aab0e | 3282 | htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ; |
| mbed_official | 354:e67efb2aab0e | 3283 | |
| mbed_official | 354:e67efb2aab0e | 3284 | /* Enable the DMA channel */ |
| mbed_official | 354:e67efb2aab0e | 3285 | HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); |
| mbed_official | 354:e67efb2aab0e | 3286 | } |
| mbed_official | 354:e67efb2aab0e | 3287 | break; |
| mbed_official | 354:e67efb2aab0e | 3288 | default: |
| mbed_official | 354:e67efb2aab0e | 3289 | break; |
| mbed_official | 354:e67efb2aab0e | 3290 | } |
| mbed_official | 354:e67efb2aab0e | 3291 | /* configure the DMA Burst Mode */ |
| mbed_official | 354:e67efb2aab0e | 3292 | htim->Instance->DCR = BurstBaseAddress | BurstLength; |
| mbed_official | 354:e67efb2aab0e | 3293 | |
| mbed_official | 354:e67efb2aab0e | 3294 | /* Enable the TIM DMA Request */ |
| mbed_official | 354:e67efb2aab0e | 3295 | __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); |
| mbed_official | 354:e67efb2aab0e | 3296 | |
| mbed_official | 354:e67efb2aab0e | 3297 | htim->State = HAL_TIM_STATE_READY; |
| mbed_official | 354:e67efb2aab0e | 3298 | |
| mbed_official | 354:e67efb2aab0e | 3299 | /* Return function status */ |
| mbed_official | 354:e67efb2aab0e | 3300 | return HAL_OK; |
| mbed_official | 354:e67efb2aab0e | 3301 | } |
| mbed_official | 354:e67efb2aab0e | 3302 | |
| mbed_official | 354:e67efb2aab0e | 3303 | /** |
| mbed_official | 354:e67efb2aab0e | 3304 | * @brief Stops the TIM DMA Burst mode |
| mbed_official | 354:e67efb2aab0e | 3305 | * @param htim: TIM handle |
| mbed_official | 354:e67efb2aab0e | 3306 | * @param BurstRequestSrc: TIM DMA Request sources to disable |
| mbed_official | 354:e67efb2aab0e | 3307 | * @retval HAL status |
| mbed_official | 354:e67efb2aab0e | 3308 | */ |
| mbed_official | 354:e67efb2aab0e | 3309 | HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) |
| mbed_official | 354:e67efb2aab0e | 3310 | { |
| mbed_official | 354:e67efb2aab0e | 3311 | /* Check the parameters */ |
| mbed_official | 354:e67efb2aab0e | 3312 | assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); |
| mbed_official | 354:e67efb2aab0e | 3313 | |
| mbed_official | 354:e67efb2aab0e | 3314 | /* Abort the DMA transfer (at least disable the DMA channel) */ |
| mbed_official | 354:e67efb2aab0e | 3315 | switch(BurstRequestSrc) |
| mbed_official | 354:e67efb2aab0e | 3316 | { |
| mbed_official | 354:e67efb2aab0e | 3317 | case TIM_DMA_UPDATE: |
| mbed_official | 354:e67efb2aab0e | 3318 | { |
| mbed_official | 354:e67efb2aab0e | 3319 | HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]); |
| mbed_official | 354:e67efb2aab0e | 3320 | } |
| mbed_official | 354:e67efb2aab0e | 3321 | break; |
| mbed_official | 354:e67efb2aab0e | 3322 | case TIM_DMA_CC1: |
| mbed_official | 354:e67efb2aab0e | 3323 | { |
| mbed_official | 354:e67efb2aab0e | 3324 | HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]); |
| mbed_official | 354:e67efb2aab0e | 3325 | } |
| mbed_official | 354:e67efb2aab0e | 3326 | break; |
| mbed_official | 354:e67efb2aab0e | 3327 | case TIM_DMA_CC2: |
| mbed_official | 354:e67efb2aab0e | 3328 | { |
| mbed_official | 354:e67efb2aab0e | 3329 | HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]); |
| mbed_official | 354:e67efb2aab0e | 3330 | } |
| mbed_official | 354:e67efb2aab0e | 3331 | break; |
| mbed_official | 354:e67efb2aab0e | 3332 | case TIM_DMA_CC3: |
| mbed_official | 354:e67efb2aab0e | 3333 | { |
| mbed_official | 354:e67efb2aab0e | 3334 | HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]); |
| mbed_official | 354:e67efb2aab0e | 3335 | } |
| mbed_official | 354:e67efb2aab0e | 3336 | break; |
| mbed_official | 354:e67efb2aab0e | 3337 | case TIM_DMA_CC4: |
| mbed_official | 354:e67efb2aab0e | 3338 | { |
| mbed_official | 354:e67efb2aab0e | 3339 | HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]); |
| mbed_official | 354:e67efb2aab0e | 3340 | } |
| mbed_official | 354:e67efb2aab0e | 3341 | break; |
| mbed_official | 354:e67efb2aab0e | 3342 | case TIM_DMA_TRIGGER: |
| mbed_official | 354:e67efb2aab0e | 3343 | { |
| mbed_official | 354:e67efb2aab0e | 3344 | HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]); |
| mbed_official | 354:e67efb2aab0e | 3345 | } |
| mbed_official | 354:e67efb2aab0e | 3346 | break; |
| mbed_official | 354:e67efb2aab0e | 3347 | default: |
| mbed_official | 354:e67efb2aab0e | 3348 | break; |
| mbed_official | 354:e67efb2aab0e | 3349 | } |
| mbed_official | 354:e67efb2aab0e | 3350 | |
| mbed_official | 354:e67efb2aab0e | 3351 | /* Disable the TIM Update DMA request */ |
| mbed_official | 354:e67efb2aab0e | 3352 | __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); |
| mbed_official | 354:e67efb2aab0e | 3353 | |
| mbed_official | 354:e67efb2aab0e | 3354 | /* Return function status */ |
| mbed_official | 354:e67efb2aab0e | 3355 | return HAL_OK; |
| mbed_official | 354:e67efb2aab0e | 3356 | } |
| mbed_official | 354:e67efb2aab0e | 3357 | |
| mbed_official | 354:e67efb2aab0e | 3358 | /** |
| mbed_official | 354:e67efb2aab0e | 3359 | * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory |
| mbed_official | 354:e67efb2aab0e | 3360 | * @param htim: TIM handle |
| mbed_official | 354:e67efb2aab0e | 3361 | * @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data read |
| mbed_official | 354:e67efb2aab0e | 3362 | * This parameters can be on of the following values: |
| mbed_official | 354:e67efb2aab0e | 3363 | * @arg TIM_DMABase_CR1 |
| mbed_official | 354:e67efb2aab0e | 3364 | * @arg TIM_DMABase_CR2 |
| mbed_official | 354:e67efb2aab0e | 3365 | * @arg TIM_DMABase_SMCR |
| mbed_official | 354:e67efb2aab0e | 3366 | * @arg TIM_DMABase_DIER |
| mbed_official | 354:e67efb2aab0e | 3367 | * @arg TIM_DMABase_SR |
| mbed_official | 354:e67efb2aab0e | 3368 | * @arg TIM_DMABase_EGR |
| mbed_official | 354:e67efb2aab0e | 3369 | * @arg TIM_DMABase_CCMR1 |
| mbed_official | 354:e67efb2aab0e | 3370 | * @arg TIM_DMABase_CCMR2 |
| mbed_official | 354:e67efb2aab0e | 3371 | * @arg TIM_DMABase_CCER |
| mbed_official | 354:e67efb2aab0e | 3372 | * @arg TIM_DMABase_CNT |
| mbed_official | 354:e67efb2aab0e | 3373 | * @arg TIM_DMABase_PSC |
| mbed_official | 354:e67efb2aab0e | 3374 | * @arg TIM_DMABase_ARR |
| mbed_official | 354:e67efb2aab0e | 3375 | * @arg TIM_DMABase_RCR |
| mbed_official | 354:e67efb2aab0e | 3376 | * @arg TIM_DMABase_CCR1 |
| mbed_official | 354:e67efb2aab0e | 3377 | * @arg TIM_DMABase_CCR2 |
| mbed_official | 354:e67efb2aab0e | 3378 | * @arg TIM_DMABase_CCR3 |
| mbed_official | 354:e67efb2aab0e | 3379 | * @arg TIM_DMABase_CCR4 |
| mbed_official | 354:e67efb2aab0e | 3380 | * @arg TIM_DMABase_BDTR |
| mbed_official | 354:e67efb2aab0e | 3381 | * @arg TIM_DMABase_DCR |
| mbed_official | 354:e67efb2aab0e | 3382 | * @param BurstRequestSrc: TIM DMA Request sources |
| mbed_official | 354:e67efb2aab0e | 3383 | * This parameters can be on of the following values: |
| mbed_official | 354:e67efb2aab0e | 3384 | * @arg TIM_DMA_UPDATE: TIM update Interrupt source |
| mbed_official | 354:e67efb2aab0e | 3385 | * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source |
| mbed_official | 354:e67efb2aab0e | 3386 | * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source |
| mbed_official | 354:e67efb2aab0e | 3387 | * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source |
| mbed_official | 354:e67efb2aab0e | 3388 | * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source |
| mbed_official | 354:e67efb2aab0e | 3389 | * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source |
| mbed_official | 354:e67efb2aab0e | 3390 | * @param BurstBuffer: The Buffer address. |
| mbed_official | 354:e67efb2aab0e | 3391 | * @param BurstLength: DMA Burst length. This parameter can be one value |
| mbed_official | 354:e67efb2aab0e | 3392 | * between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers. |
| mbed_official | 354:e67efb2aab0e | 3393 | * @retval HAL status |
| mbed_official | 354:e67efb2aab0e | 3394 | */ |
| mbed_official | 354:e67efb2aab0e | 3395 | HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, |
| mbed_official | 354:e67efb2aab0e | 3396 | uint32_t *BurstBuffer, uint32_t BurstLength) |
| mbed_official | 354:e67efb2aab0e | 3397 | { |
| mbed_official | 354:e67efb2aab0e | 3398 | /* Check the parameters */ |
| mbed_official | 354:e67efb2aab0e | 3399 | assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); |
| mbed_official | 354:e67efb2aab0e | 3400 | assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); |
| mbed_official | 354:e67efb2aab0e | 3401 | assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); |
| mbed_official | 354:e67efb2aab0e | 3402 | assert_param(IS_TIM_DMA_LENGTH(BurstLength)); |
| mbed_official | 354:e67efb2aab0e | 3403 | |
| mbed_official | 354:e67efb2aab0e | 3404 | if((htim->State == HAL_TIM_STATE_BUSY)) |
| mbed_official | 354:e67efb2aab0e | 3405 | { |
| mbed_official | 354:e67efb2aab0e | 3406 | return HAL_BUSY; |
| mbed_official | 354:e67efb2aab0e | 3407 | } |
| mbed_official | 354:e67efb2aab0e | 3408 | else if((htim->State == HAL_TIM_STATE_READY)) |
| mbed_official | 354:e67efb2aab0e | 3409 | { |
| mbed_official | 354:e67efb2aab0e | 3410 | if((BurstBuffer == 0 ) && (BurstLength > 0)) |
| mbed_official | 354:e67efb2aab0e | 3411 | { |
| mbed_official | 354:e67efb2aab0e | 3412 | return HAL_ERROR; |
| mbed_official | 354:e67efb2aab0e | 3413 | } |
| mbed_official | 354:e67efb2aab0e | 3414 | else |
| mbed_official | 354:e67efb2aab0e | 3415 | { |
| mbed_official | 354:e67efb2aab0e | 3416 | htim->State = HAL_TIM_STATE_BUSY; |
| mbed_official | 354:e67efb2aab0e | 3417 | } |
| mbed_official | 354:e67efb2aab0e | 3418 | } |
| mbed_official | 354:e67efb2aab0e | 3419 | else |
| mbed_official | 354:e67efb2aab0e | 3420 | { |
| mbed_official | 354:e67efb2aab0e | 3421 | return HAL_ERROR; |
| mbed_official | 354:e67efb2aab0e | 3422 | } |
| mbed_official | 354:e67efb2aab0e | 3423 | |
| mbed_official | 354:e67efb2aab0e | 3424 | switch(BurstRequestSrc) |
| mbed_official | 354:e67efb2aab0e | 3425 | { |
| mbed_official | 354:e67efb2aab0e | 3426 | case TIM_DMA_UPDATE: |
| mbed_official | 354:e67efb2aab0e | 3427 | { |
| mbed_official | 354:e67efb2aab0e | 3428 | /* Set the DMA Period elapsed callback */ |
| mbed_official | 354:e67efb2aab0e | 3429 | htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; |
| mbed_official | 354:e67efb2aab0e | 3430 | |
| mbed_official | 354:e67efb2aab0e | 3431 | /* Set the DMA error callback */ |
| mbed_official | 354:e67efb2aab0e | 3432 | htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; |
| mbed_official | 354:e67efb2aab0e | 3433 | |
| mbed_official | 354:e67efb2aab0e | 3434 | /* Enable the DMA channel */ |
| mbed_official | 354:e67efb2aab0e | 3435 | HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); |
| mbed_official | 354:e67efb2aab0e | 3436 | } |
| mbed_official | 354:e67efb2aab0e | 3437 | break; |
| mbed_official | 354:e67efb2aab0e | 3438 | case TIM_DMA_CC1: |
| mbed_official | 354:e67efb2aab0e | 3439 | { |
| mbed_official | 354:e67efb2aab0e | 3440 | /* Set the DMA Period elapsed callback */ |
| mbed_official | 354:e67efb2aab0e | 3441 | htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; |
| mbed_official | 354:e67efb2aab0e | 3442 | |
| mbed_official | 354:e67efb2aab0e | 3443 | /* Set the DMA error callback */ |
| mbed_official | 354:e67efb2aab0e | 3444 | htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; |
| mbed_official | 354:e67efb2aab0e | 3445 | |
| mbed_official | 354:e67efb2aab0e | 3446 | /* Enable the DMA channel */ |
| mbed_official | 354:e67efb2aab0e | 3447 | HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); |
| mbed_official | 354:e67efb2aab0e | 3448 | } |
| mbed_official | 354:e67efb2aab0e | 3449 | break; |
| mbed_official | 354:e67efb2aab0e | 3450 | case TIM_DMA_CC2: |
| mbed_official | 354:e67efb2aab0e | 3451 | { |
| mbed_official | 354:e67efb2aab0e | 3452 | /* Set the DMA Period elapsed callback */ |
| mbed_official | 354:e67efb2aab0e | 3453 | htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; |
| mbed_official | 354:e67efb2aab0e | 3454 | |
| mbed_official | 354:e67efb2aab0e | 3455 | /* Set the DMA error callback */ |
| mbed_official | 354:e67efb2aab0e | 3456 | htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; |
| mbed_official | 354:e67efb2aab0e | 3457 | |
| mbed_official | 354:e67efb2aab0e | 3458 | /* Enable the DMA channel */ |
| mbed_official | 354:e67efb2aab0e | 3459 | HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); |
| mbed_official | 354:e67efb2aab0e | 3460 | } |
| mbed_official | 354:e67efb2aab0e | 3461 | break; |
| mbed_official | 354:e67efb2aab0e | 3462 | case TIM_DMA_CC3: |
| mbed_official | 354:e67efb2aab0e | 3463 | { |
| mbed_official | 354:e67efb2aab0e | 3464 | /* Set the DMA Period elapsed callback */ |
| mbed_official | 354:e67efb2aab0e | 3465 | htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt; |
| mbed_official | 354:e67efb2aab0e | 3466 | |
| mbed_official | 354:e67efb2aab0e | 3467 | /* Set the DMA error callback */ |
| mbed_official | 354:e67efb2aab0e | 3468 | htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; |
| mbed_official | 354:e67efb2aab0e | 3469 | |
| mbed_official | 354:e67efb2aab0e | 3470 | /* Enable the DMA channel */ |
| mbed_official | 354:e67efb2aab0e | 3471 | HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); |
| mbed_official | 354:e67efb2aab0e | 3472 | } |
| mbed_official | 354:e67efb2aab0e | 3473 | break; |
| mbed_official | 354:e67efb2aab0e | 3474 | case TIM_DMA_CC4: |
| mbed_official | 354:e67efb2aab0e | 3475 | { |
| mbed_official | 354:e67efb2aab0e | 3476 | /* Set the DMA Period elapsed callback */ |
| mbed_official | 354:e67efb2aab0e | 3477 | htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt; |
| mbed_official | 354:e67efb2aab0e | 3478 | |
| mbed_official | 354:e67efb2aab0e | 3479 | /* Set the DMA error callback */ |
| mbed_official | 354:e67efb2aab0e | 3480 | htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; |
| mbed_official | 354:e67efb2aab0e | 3481 | |
| mbed_official | 354:e67efb2aab0e | 3482 | /* Enable the DMA channel */ |
| mbed_official | 354:e67efb2aab0e | 3483 | HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); |
| mbed_official | 354:e67efb2aab0e | 3484 | } |
| mbed_official | 354:e67efb2aab0e | 3485 | break; |
| mbed_official | 354:e67efb2aab0e | 3486 | case TIM_DMA_TRIGGER: |
| mbed_official | 354:e67efb2aab0e | 3487 | { |
| mbed_official | 354:e67efb2aab0e | 3488 | /* Set the DMA Period elapsed callback */ |
| mbed_official | 354:e67efb2aab0e | 3489 | htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt; |
| mbed_official | 354:e67efb2aab0e | 3490 | |
| mbed_official | 354:e67efb2aab0e | 3491 | /* Set the DMA error callback */ |
| mbed_official | 354:e67efb2aab0e | 3492 | htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ; |
| mbed_official | 354:e67efb2aab0e | 3493 | |
| mbed_official | 354:e67efb2aab0e | 3494 | /* Enable the DMA channel */ |
| mbed_official | 354:e67efb2aab0e | 3495 | HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); |
| mbed_official | 354:e67efb2aab0e | 3496 | } |
| mbed_official | 354:e67efb2aab0e | 3497 | break; |
| mbed_official | 354:e67efb2aab0e | 3498 | default: |
| mbed_official | 354:e67efb2aab0e | 3499 | break; |
| mbed_official | 354:e67efb2aab0e | 3500 | } |
| mbed_official | 354:e67efb2aab0e | 3501 | |
| mbed_official | 354:e67efb2aab0e | 3502 | /* configure the DMA Burst Mode */ |
| mbed_official | 354:e67efb2aab0e | 3503 | htim->Instance->DCR = BurstBaseAddress | BurstLength; |
| mbed_official | 354:e67efb2aab0e | 3504 | |
| mbed_official | 354:e67efb2aab0e | 3505 | /* Enable the TIM DMA Request */ |
| mbed_official | 354:e67efb2aab0e | 3506 | __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); |
| mbed_official | 354:e67efb2aab0e | 3507 | |
| mbed_official | 354:e67efb2aab0e | 3508 | htim->State = HAL_TIM_STATE_READY; |
| mbed_official | 354:e67efb2aab0e | 3509 | |
| mbed_official | 354:e67efb2aab0e | 3510 | /* Return function status */ |
| mbed_official | 354:e67efb2aab0e | 3511 | return HAL_OK; |
| mbed_official | 354:e67efb2aab0e | 3512 | } |
| mbed_official | 354:e67efb2aab0e | 3513 | |
| mbed_official | 354:e67efb2aab0e | 3514 | /** |
| mbed_official | 354:e67efb2aab0e | 3515 | * @brief Stop the DMA burst reading |
| mbed_official | 354:e67efb2aab0e | 3516 | * @param htim: TIM handle |
| mbed_official | 354:e67efb2aab0e | 3517 | * @param BurstRequestSrc: TIM DMA Request sources to disable. |
| mbed_official | 354:e67efb2aab0e | 3518 | * @retval HAL status |
| mbed_official | 354:e67efb2aab0e | 3519 | */ |
| mbed_official | 354:e67efb2aab0e | 3520 | HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) |
| mbed_official | 354:e67efb2aab0e | 3521 | { |
| mbed_official | 354:e67efb2aab0e | 3522 | /* Check the parameters */ |
| mbed_official | 354:e67efb2aab0e | 3523 | assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); |
| mbed_official | 354:e67efb2aab0e | 3524 | |
| mbed_official | 354:e67efb2aab0e | 3525 | /* Abort the DMA transfer (at least disable the DMA channel) */ |
| mbed_official | 354:e67efb2aab0e | 3526 | switch(BurstRequestSrc) |
| mbed_official | 354:e67efb2aab0e | 3527 | { |
| mbed_official | 354:e67efb2aab0e | 3528 | case TIM_DMA_UPDATE: |
| mbed_official | 354:e67efb2aab0e | 3529 | { |
| mbed_official | 354:e67efb2aab0e | 3530 | HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]); |
| mbed_official | 354:e67efb2aab0e | 3531 | } |
| mbed_official | 354:e67efb2aab0e | 3532 | break; |
| mbed_official | 354:e67efb2aab0e | 3533 | case TIM_DMA_CC1: |
| mbed_official | 354:e67efb2aab0e | 3534 | { |
| mbed_official | 354:e67efb2aab0e | 3535 | HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]); |
| mbed_official | 354:e67efb2aab0e | 3536 | } |
| mbed_official | 354:e67efb2aab0e | 3537 | break; |
| mbed_official | 354:e67efb2aab0e | 3538 | case TIM_DMA_CC2: |
| mbed_official | 354:e67efb2aab0e | 3539 | { |
| mbed_official | 354:e67efb2aab0e | 3540 | HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]); |
| mbed_official | 354:e67efb2aab0e | 3541 | } |
| mbed_official | 354:e67efb2aab0e | 3542 | break; |
| mbed_official | 354:e67efb2aab0e | 3543 | case TIM_DMA_CC3: |
| mbed_official | 354:e67efb2aab0e | 3544 | { |
| mbed_official | 354:e67efb2aab0e | 3545 | HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]); |
| mbed_official | 354:e67efb2aab0e | 3546 | } |
| mbed_official | 354:e67efb2aab0e | 3547 | break; |
| mbed_official | 354:e67efb2aab0e | 3548 | case TIM_DMA_CC4: |
| mbed_official | 354:e67efb2aab0e | 3549 | { |
| mbed_official | 354:e67efb2aab0e | 3550 | HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]); |
| mbed_official | 354:e67efb2aab0e | 3551 | } |
| mbed_official | 354:e67efb2aab0e | 3552 | break; |
| mbed_official | 354:e67efb2aab0e | 3553 | case TIM_DMA_TRIGGER: |
| mbed_official | 354:e67efb2aab0e | 3554 | { |
| mbed_official | 354:e67efb2aab0e | 3555 | HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]); |
| mbed_official | 354:e67efb2aab0e | 3556 | } |
| mbed_official | 354:e67efb2aab0e | 3557 | break; |
| mbed_official | 354:e67efb2aab0e | 3558 | default: |
| mbed_official | 354:e67efb2aab0e | 3559 | break; |
| mbed_official | 354:e67efb2aab0e | 3560 | } |
| mbed_official | 354:e67efb2aab0e | 3561 | |
| mbed_official | 354:e67efb2aab0e | 3562 | /* Disable the TIM Update DMA request */ |
| mbed_official | 354:e67efb2aab0e | 3563 | __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); |
| mbed_official | 354:e67efb2aab0e | 3564 | |
| mbed_official | 354:e67efb2aab0e | 3565 | /* Return function status */ |
| mbed_official | 354:e67efb2aab0e | 3566 | return HAL_OK; |
| mbed_official | 354:e67efb2aab0e | 3567 | } |
| mbed_official | 354:e67efb2aab0e | 3568 | |
| mbed_official | 354:e67efb2aab0e | 3569 | /** |
| mbed_official | 354:e67efb2aab0e | 3570 | * @brief Generate a software event |
| mbed_official | 354:e67efb2aab0e | 3571 | * @param htim: TIM handle |
| mbed_official | 354:e67efb2aab0e | 3572 | * @param EventSource: specifies the event source. |
| mbed_official | 354:e67efb2aab0e | 3573 | * This parameter can be one of the following values: |
| mbed_official | 354:e67efb2aab0e | 3574 | * @arg TIM_EventSource_Update: Timer update Event source |
| mbed_official | 354:e67efb2aab0e | 3575 | * @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source |
| mbed_official | 354:e67efb2aab0e | 3576 | * @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source |
| mbed_official | 354:e67efb2aab0e | 3577 | * @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source |
| mbed_official | 354:e67efb2aab0e | 3578 | * @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source |
| mbed_official | 354:e67efb2aab0e | 3579 | * @arg TIM_EventSource_COM: Timer COM event source |
| mbed_official | 354:e67efb2aab0e | 3580 | * @arg TIM_EventSource_Trigger: Timer Trigger Event source |
| mbed_official | 354:e67efb2aab0e | 3581 | * @arg TIM_EventSource_Break: Timer Break event source |
| mbed_official | 354:e67efb2aab0e | 3582 | * @note TBC can only generate an update event. |
| mbed_official | 354:e67efb2aab0e | 3583 | * @note TIM_EventSource_COM and TIM_EventSource_Break are used only with TBC. |
| mbed_official | 354:e67efb2aab0e | 3584 | * @retval HAL status |
| mbed_official | 354:e67efb2aab0e | 3585 | */ |
| mbed_official | 354:e67efb2aab0e | 3586 | |
| mbed_official | 354:e67efb2aab0e | 3587 | HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource) |
| mbed_official | 354:e67efb2aab0e | 3588 | { |
| mbed_official | 354:e67efb2aab0e | 3589 | /* Check the parameters */ |
| mbed_official | 354:e67efb2aab0e | 3590 | assert_param(IS_TIM_INSTANCE(htim->Instance)); |
| mbed_official | 354:e67efb2aab0e | 3591 | assert_param(IS_TIM_EVENT_SOURCE(EventSource)); |
| mbed_official | 354:e67efb2aab0e | 3592 | |
| mbed_official | 354:e67efb2aab0e | 3593 | /* Process Locked */ |
| mbed_official | 354:e67efb2aab0e | 3594 | __HAL_LOCK(htim); |
| mbed_official | 354:e67efb2aab0e | 3595 | |
| mbed_official | 354:e67efb2aab0e | 3596 | /* Change the TIM state */ |
| mbed_official | 354:e67efb2aab0e | 3597 | htim->State = HAL_TIM_STATE_BUSY; |
| mbed_official | 354:e67efb2aab0e | 3598 | |
| mbed_official | 354:e67efb2aab0e | 3599 | /* Set the event sources */ |
| mbed_official | 354:e67efb2aab0e | 3600 | htim->Instance->EGR = EventSource; |
| mbed_official | 354:e67efb2aab0e | 3601 | |
| mbed_official | 354:e67efb2aab0e | 3602 | /* Change the TIM state */ |
| mbed_official | 354:e67efb2aab0e | 3603 | htim->State = HAL_TIM_STATE_READY; |
| mbed_official | 354:e67efb2aab0e | 3604 | |
| mbed_official | 354:e67efb2aab0e | 3605 | __HAL_UNLOCK(htim); |
| mbed_official | 354:e67efb2aab0e | 3606 | |
| mbed_official | 354:e67efb2aab0e | 3607 | /* Return function status */ |
| mbed_official | 354:e67efb2aab0e | 3608 | return HAL_OK; |
| mbed_official | 354:e67efb2aab0e | 3609 | } |
| mbed_official | 354:e67efb2aab0e | 3610 | |
| mbed_official | 354:e67efb2aab0e | 3611 | /** |
| mbed_official | 354:e67efb2aab0e | 3612 | * @brief Configures the OCRef clear feature |
| mbed_official | 354:e67efb2aab0e | 3613 | * @param htim: TIM handle |
| mbed_official | 354:e67efb2aab0e | 3614 | * @param sClearInputConfig: pointer to a TIM_ClearInputConfigTypeDef structure that |
| mbed_official | 354:e67efb2aab0e | 3615 | * contains the OCREF clear feature and parameters for the TIM peripheral. |
| mbed_official | 354:e67efb2aab0e | 3616 | * @param Channel: specifies the TIM Channel |
| mbed_official | 354:e67efb2aab0e | 3617 | * This parameter can be one of the following values: |
| mbed_official | 354:e67efb2aab0e | 3618 | * @arg TIM_CHANNEL_1: TIM Channel 1 |
| mbed_official | 354:e67efb2aab0e | 3619 | * @arg TIM_CHANNEL_2: TIM Channel 2 |
| mbed_official | 354:e67efb2aab0e | 3620 | * @arg TIM_CHANNEL_3: TIM Channel 3 |
| mbed_official | 354:e67efb2aab0e | 3621 | * @arg TIM_CHANNEL_4: TIM Channel 4 |
| mbed_official | 354:e67efb2aab0e | 3622 | * @retval HAL status |
| mbed_official | 354:e67efb2aab0e | 3623 | */ |
| mbed_official | 354:e67efb2aab0e | 3624 | HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel) |
| mbed_official | 354:e67efb2aab0e | 3625 | { |
| mbed_official | 354:e67efb2aab0e | 3626 | |
| mbed_official | 354:e67efb2aab0e | 3627 | /* Check the parameters */ |
| mbed_official | 354:e67efb2aab0e | 3628 | assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance)); |
| mbed_official | 354:e67efb2aab0e | 3629 | assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource)); |
| mbed_official | 354:e67efb2aab0e | 3630 | assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity)); |
| mbed_official | 354:e67efb2aab0e | 3631 | assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler)); |
| mbed_official | 354:e67efb2aab0e | 3632 | assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter)); |
| mbed_official | 354:e67efb2aab0e | 3633 | |
| mbed_official | 354:e67efb2aab0e | 3634 | /* Process Locked */ |
| mbed_official | 354:e67efb2aab0e | 3635 | __HAL_LOCK(htim); |
| mbed_official | 354:e67efb2aab0e | 3636 | |
| mbed_official | 354:e67efb2aab0e | 3637 | htim->State = HAL_TIM_STATE_BUSY; |
| mbed_official | 354:e67efb2aab0e | 3638 | |
| mbed_official | 354:e67efb2aab0e | 3639 | switch (sClearInputConfig->ClearInputSource) |
| mbed_official | 354:e67efb2aab0e | 3640 | { |
| mbed_official | 354:e67efb2aab0e | 3641 | case TIM_CLEARINPUTSOURCE_NONE: |
| mbed_official | 354:e67efb2aab0e | 3642 | { |
| mbed_official | 354:e67efb2aab0e | 3643 | /* Clear the OCREF clear selection bit */ |
| mbed_official | 354:e67efb2aab0e | 3644 | CLEAR_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS); |
| mbed_official | 354:e67efb2aab0e | 3645 | |
| mbed_official | 354:e67efb2aab0e | 3646 | /* Clear the ETR Bits */ |
| mbed_official | 354:e67efb2aab0e | 3647 | CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP)); |
| mbed_official | 354:e67efb2aab0e | 3648 | |
| mbed_official | 354:e67efb2aab0e | 3649 | } |
| mbed_official | 354:e67efb2aab0e | 3650 | break; |
| mbed_official | 354:e67efb2aab0e | 3651 | |
| mbed_official | 354:e67efb2aab0e | 3652 | case TIM_CLEARINPUTSOURCE_OCREFCLR: |
| mbed_official | 354:e67efb2aab0e | 3653 | { |
| mbed_official | 354:e67efb2aab0e | 3654 | /* Clear the OCREF clear selection bit */ |
| mbed_official | 354:e67efb2aab0e | 3655 | CLEAR_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS); |
| mbed_official | 354:e67efb2aab0e | 3656 | } |
| mbed_official | 354:e67efb2aab0e | 3657 | break; |
| mbed_official | 354:e67efb2aab0e | 3658 | |
| mbed_official | 354:e67efb2aab0e | 3659 | case TIM_CLEARINPUTSOURCE_ETR: |
| mbed_official | 354:e67efb2aab0e | 3660 | { |
| mbed_official | 354:e67efb2aab0e | 3661 | TIM_ETR_SetConfig(htim->Instance, |
| mbed_official | 354:e67efb2aab0e | 3662 | sClearInputConfig->ClearInputPrescaler, |
| mbed_official | 354:e67efb2aab0e | 3663 | sClearInputConfig->ClearInputPolarity, |
| mbed_official | 354:e67efb2aab0e | 3664 | sClearInputConfig->ClearInputFilter); |
| mbed_official | 354:e67efb2aab0e | 3665 | |
| mbed_official | 354:e67efb2aab0e | 3666 | /* Set the OCREF clear selection bit */ |
| mbed_official | 354:e67efb2aab0e | 3667 | SET_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS); |
| mbed_official | 354:e67efb2aab0e | 3668 | } |
| mbed_official | 354:e67efb2aab0e | 3669 | break; |
| mbed_official | 354:e67efb2aab0e | 3670 | |
| mbed_official | 354:e67efb2aab0e | 3671 | default: |
| mbed_official | 354:e67efb2aab0e | 3672 | break; |
| mbed_official | 354:e67efb2aab0e | 3673 | |
| mbed_official | 354:e67efb2aab0e | 3674 | } |
| mbed_official | 354:e67efb2aab0e | 3675 | |
| mbed_official | 354:e67efb2aab0e | 3676 | switch (Channel) |
| mbed_official | 354:e67efb2aab0e | 3677 | { |
| mbed_official | 354:e67efb2aab0e | 3678 | case TIM_CHANNEL_1: |
| mbed_official | 354:e67efb2aab0e | 3679 | { |
| mbed_official | 354:e67efb2aab0e | 3680 | if(sClearInputConfig->ClearInputState != RESET) |
| mbed_official | 354:e67efb2aab0e | 3681 | { |
| mbed_official | 354:e67efb2aab0e | 3682 | /* Enable the Ocref clear feature for Channel 1 */ |
| mbed_official | 354:e67efb2aab0e | 3683 | htim->Instance->CCMR1 |= TIM_CCMR1_OC1CE; |
| mbed_official | 354:e67efb2aab0e | 3684 | } |
| mbed_official | 354:e67efb2aab0e | 3685 | else |
| mbed_official | 354:e67efb2aab0e | 3686 | { |
| mbed_official | 354:e67efb2aab0e | 3687 | /* Disable the Ocref clear feature for Channel 1 */ |
| mbed_official | 354:e67efb2aab0e | 3688 | htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE; |
| mbed_official | 354:e67efb2aab0e | 3689 | } |
| mbed_official | 354:e67efb2aab0e | 3690 | } |
| mbed_official | 354:e67efb2aab0e | 3691 | break; |
| mbed_official | 354:e67efb2aab0e | 3692 | case TIM_CHANNEL_2: |
| mbed_official | 354:e67efb2aab0e | 3693 | { |
| mbed_official | 354:e67efb2aab0e | 3694 | assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); |
| mbed_official | 354:e67efb2aab0e | 3695 | if(sClearInputConfig->ClearInputState != RESET) |
| mbed_official | 354:e67efb2aab0e | 3696 | { |
| mbed_official | 354:e67efb2aab0e | 3697 | /* Enable the Ocref clear feature for Channel 2 */ |
| mbed_official | 354:e67efb2aab0e | 3698 | htim->Instance->CCMR1 |= TIM_CCMR1_OC2CE; |
| mbed_official | 354:e67efb2aab0e | 3699 | } |
| mbed_official | 354:e67efb2aab0e | 3700 | else |
| mbed_official | 354:e67efb2aab0e | 3701 | { |
| mbed_official | 354:e67efb2aab0e | 3702 | /* Disable the Ocref clear feature for Channel 2 */ |
| mbed_official | 354:e67efb2aab0e | 3703 | htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE; |
| mbed_official | 354:e67efb2aab0e | 3704 | } |
| mbed_official | 354:e67efb2aab0e | 3705 | } |
| mbed_official | 354:e67efb2aab0e | 3706 | break; |
| mbed_official | 354:e67efb2aab0e | 3707 | case TIM_CHANNEL_3: |
| mbed_official | 354:e67efb2aab0e | 3708 | { |
| mbed_official | 354:e67efb2aab0e | 3709 | assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); |
| mbed_official | 354:e67efb2aab0e | 3710 | if(sClearInputConfig->ClearInputState != RESET) |
| mbed_official | 354:e67efb2aab0e | 3711 | { |
| mbed_official | 354:e67efb2aab0e | 3712 | /* Enable the Ocref clear feature for Channel 3 */ |
| mbed_official | 354:e67efb2aab0e | 3713 | htim->Instance->CCMR2 |= TIM_CCMR2_OC3CE; |
| mbed_official | 354:e67efb2aab0e | 3714 | } |
| mbed_official | 354:e67efb2aab0e | 3715 | else |
| mbed_official | 354:e67efb2aab0e | 3716 | { |
| mbed_official | 354:e67efb2aab0e | 3717 | /* Disable the Ocref clear feature for Channel 3 */ |
| mbed_official | 354:e67efb2aab0e | 3718 | htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE; |
| mbed_official | 354:e67efb2aab0e | 3719 | } |
| mbed_official | 354:e67efb2aab0e | 3720 | } |
| mbed_official | 354:e67efb2aab0e | 3721 | break; |
| mbed_official | 354:e67efb2aab0e | 3722 | case TIM_CHANNEL_4: |
| mbed_official | 354:e67efb2aab0e | 3723 | { |
| mbed_official | 354:e67efb2aab0e | 3724 | assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); |
| mbed_official | 354:e67efb2aab0e | 3725 | if(sClearInputConfig->ClearInputState != RESET) |
| mbed_official | 354:e67efb2aab0e | 3726 | { |
| mbed_official | 354:e67efb2aab0e | 3727 | /* Enable the Ocref clear feature for Channel 4 */ |
| mbed_official | 354:e67efb2aab0e | 3728 | htim->Instance->CCMR2 |= TIM_CCMR2_OC4CE; |
| mbed_official | 354:e67efb2aab0e | 3729 | } |
| mbed_official | 354:e67efb2aab0e | 3730 | else |
| mbed_official | 354:e67efb2aab0e | 3731 | { |
| mbed_official | 354:e67efb2aab0e | 3732 | /* Disable the Ocref clear feature for Channel 4 */ |
| mbed_official | 354:e67efb2aab0e | 3733 | htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE; |
| mbed_official | 354:e67efb2aab0e | 3734 | } |
| mbed_official | 354:e67efb2aab0e | 3735 | } |
| mbed_official | 354:e67efb2aab0e | 3736 | break; |
| mbed_official | 354:e67efb2aab0e | 3737 | default: |
| mbed_official | 354:e67efb2aab0e | 3738 | break; |
| mbed_official | 354:e67efb2aab0e | 3739 | } |
| mbed_official | 354:e67efb2aab0e | 3740 | |
| mbed_official | 354:e67efb2aab0e | 3741 | htim->State = HAL_TIM_STATE_READY; |
| mbed_official | 354:e67efb2aab0e | 3742 | |
| mbed_official | 354:e67efb2aab0e | 3743 | __HAL_UNLOCK(htim); |
| mbed_official | 354:e67efb2aab0e | 3744 | |
| mbed_official | 354:e67efb2aab0e | 3745 | return HAL_OK; |
| mbed_official | 354:e67efb2aab0e | 3746 | } |
| mbed_official | 354:e67efb2aab0e | 3747 | |
| mbed_official | 354:e67efb2aab0e | 3748 | /** |
| mbed_official | 354:e67efb2aab0e | 3749 | * @brief Configures the clock source to be used |
| mbed_official | 354:e67efb2aab0e | 3750 | * @param htim: TIM handle |
| mbed_official | 354:e67efb2aab0e | 3751 | * @param sClockSourceConfig: pointer to a TIM_ClockConfigTypeDef structure that |
| mbed_official | 354:e67efb2aab0e | 3752 | * contains the clock source information for the TIM peripheral. |
| mbed_official | 354:e67efb2aab0e | 3753 | * @retval HAL status |
| mbed_official | 354:e67efb2aab0e | 3754 | */ |
| mbed_official | 354:e67efb2aab0e | 3755 | HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig) |
| mbed_official | 354:e67efb2aab0e | 3756 | { |
| mbed_official | 354:e67efb2aab0e | 3757 | uint32_t tmpsmcr = 0; |
| mbed_official | 354:e67efb2aab0e | 3758 | |
| mbed_official | 354:e67efb2aab0e | 3759 | /* Check the parameters */ |
| mbed_official | 354:e67efb2aab0e | 3760 | assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource)); |
| mbed_official | 354:e67efb2aab0e | 3761 | assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); |
| mbed_official | 354:e67efb2aab0e | 3762 | assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); |
| mbed_official | 354:e67efb2aab0e | 3763 | assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); |
| mbed_official | 354:e67efb2aab0e | 3764 | |
| mbed_official | 354:e67efb2aab0e | 3765 | /* Process Locked */ |
| mbed_official | 354:e67efb2aab0e | 3766 | __HAL_LOCK(htim); |
| mbed_official | 354:e67efb2aab0e | 3767 | |
| mbed_official | 354:e67efb2aab0e | 3768 | htim->State = HAL_TIM_STATE_BUSY; |
| mbed_official | 354:e67efb2aab0e | 3769 | |
| mbed_official | 354:e67efb2aab0e | 3770 | /* Reset the SMS, TS, ECE, ETPS and ETRF bits */ |
| mbed_official | 354:e67efb2aab0e | 3771 | tmpsmcr = htim->Instance->SMCR; |
| mbed_official | 354:e67efb2aab0e | 3772 | tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS); |
| mbed_official | 354:e67efb2aab0e | 3773 | tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); |
| mbed_official | 354:e67efb2aab0e | 3774 | htim->Instance->SMCR = tmpsmcr; |
| mbed_official | 354:e67efb2aab0e | 3775 | |
| mbed_official | 354:e67efb2aab0e | 3776 | switch (sClockSourceConfig->ClockSource) |
| mbed_official | 354:e67efb2aab0e | 3777 | { |
| mbed_official | 354:e67efb2aab0e | 3778 | case TIM_CLOCKSOURCE_INTERNAL: |
| mbed_official | 354:e67efb2aab0e | 3779 | { |
| mbed_official | 354:e67efb2aab0e | 3780 | assert_param(IS_TIM_INSTANCE(htim->Instance)); |
| mbed_official | 354:e67efb2aab0e | 3781 | /* Disable slave mode to clock the prescaler directly with the internal clock */ |
| mbed_official | 354:e67efb2aab0e | 3782 | htim->Instance->SMCR &= ~TIM_SMCR_SMS; |
| mbed_official | 354:e67efb2aab0e | 3783 | } |
| mbed_official | 354:e67efb2aab0e | 3784 | break; |
| mbed_official | 354:e67efb2aab0e | 3785 | |
| mbed_official | 354:e67efb2aab0e | 3786 | case TIM_CLOCKSOURCE_ETRMODE1: |
| mbed_official | 354:e67efb2aab0e | 3787 | { |
| mbed_official | 354:e67efb2aab0e | 3788 | /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/ |
| mbed_official | 354:e67efb2aab0e | 3789 | assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance)); |
| mbed_official | 354:e67efb2aab0e | 3790 | |
| mbed_official | 354:e67efb2aab0e | 3791 | /* Configure the ETR Clock source */ |
| mbed_official | 354:e67efb2aab0e | 3792 | TIM_ETR_SetConfig(htim->Instance, |
| mbed_official | 354:e67efb2aab0e | 3793 | sClockSourceConfig->ClockPrescaler, |
| mbed_official | 354:e67efb2aab0e | 3794 | sClockSourceConfig->ClockPolarity, |
| mbed_official | 354:e67efb2aab0e | 3795 | sClockSourceConfig->ClockFilter); |
| mbed_official | 354:e67efb2aab0e | 3796 | /* Get the TIMx SMCR register value */ |
| mbed_official | 354:e67efb2aab0e | 3797 | tmpsmcr = htim->Instance->SMCR; |
| mbed_official | 354:e67efb2aab0e | 3798 | /* Reset the SMS and TS Bits */ |
| mbed_official | 354:e67efb2aab0e | 3799 | tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS); |
| mbed_official | 354:e67efb2aab0e | 3800 | /* Select the External clock mode1 and the ETRF trigger */ |
| mbed_official | 354:e67efb2aab0e | 3801 | tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1); |
| mbed_official | 354:e67efb2aab0e | 3802 | /* Write to TIMx SMCR */ |
| mbed_official | 354:e67efb2aab0e | 3803 | htim->Instance->SMCR = tmpsmcr; |
| mbed_official | 354:e67efb2aab0e | 3804 | } |
| mbed_official | 354:e67efb2aab0e | 3805 | break; |
| mbed_official | 354:e67efb2aab0e | 3806 | |
| mbed_official | 354:e67efb2aab0e | 3807 | case TIM_CLOCKSOURCE_ETRMODE2: |
| mbed_official | 354:e67efb2aab0e | 3808 | { |
| mbed_official | 354:e67efb2aab0e | 3809 | /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/ |
| mbed_official | 354:e67efb2aab0e | 3810 | assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance)); |
| mbed_official | 354:e67efb2aab0e | 3811 | |
| mbed_official | 354:e67efb2aab0e | 3812 | /* Configure the ETR Clock source */ |
| mbed_official | 354:e67efb2aab0e | 3813 | TIM_ETR_SetConfig(htim->Instance, |
| mbed_official | 354:e67efb2aab0e | 3814 | sClockSourceConfig->ClockPrescaler, |
| mbed_official | 354:e67efb2aab0e | 3815 | sClockSourceConfig->ClockPolarity, |
| mbed_official | 354:e67efb2aab0e | 3816 | sClockSourceConfig->ClockFilter); |
| mbed_official | 354:e67efb2aab0e | 3817 | /* Enable the External clock mode2 */ |
| mbed_official | 354:e67efb2aab0e | 3818 | htim->Instance->SMCR |= TIM_SMCR_ECE; |
| mbed_official | 354:e67efb2aab0e | 3819 | } |
| mbed_official | 354:e67efb2aab0e | 3820 | break; |
| mbed_official | 354:e67efb2aab0e | 3821 | |
| mbed_official | 354:e67efb2aab0e | 3822 | case TIM_CLOCKSOURCE_TI1: |
| mbed_official | 354:e67efb2aab0e | 3823 | { |
| mbed_official | 354:e67efb2aab0e | 3824 | /* Check whether or not the timer instance supports external clock mode 1 */ |
| mbed_official | 354:e67efb2aab0e | 3825 | assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); |
| mbed_official | 354:e67efb2aab0e | 3826 | |
| mbed_official | 354:e67efb2aab0e | 3827 | TIM_TI1_ConfigInputStage(htim->Instance, |
| mbed_official | 354:e67efb2aab0e | 3828 | sClockSourceConfig->ClockPolarity, |
| mbed_official | 354:e67efb2aab0e | 3829 | sClockSourceConfig->ClockFilter); |
| mbed_official | 354:e67efb2aab0e | 3830 | TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1); |
| mbed_official | 354:e67efb2aab0e | 3831 | } |
| mbed_official | 354:e67efb2aab0e | 3832 | break; |
| mbed_official | 354:e67efb2aab0e | 3833 | case TIM_CLOCKSOURCE_TI2: |
| mbed_official | 354:e67efb2aab0e | 3834 | { |
| mbed_official | 354:e67efb2aab0e | 3835 | /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/ |
| mbed_official | 354:e67efb2aab0e | 3836 | assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); |
| mbed_official | 354:e67efb2aab0e | 3837 | |
| mbed_official | 354:e67efb2aab0e | 3838 | TIM_TI2_ConfigInputStage(htim->Instance, |
| mbed_official | 354:e67efb2aab0e | 3839 | sClockSourceConfig->ClockPolarity, |
| mbed_official | 354:e67efb2aab0e | 3840 | sClockSourceConfig->ClockFilter); |
| mbed_official | 354:e67efb2aab0e | 3841 | TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2); |
| mbed_official | 354:e67efb2aab0e | 3842 | } |
| mbed_official | 354:e67efb2aab0e | 3843 | break; |
| mbed_official | 354:e67efb2aab0e | 3844 | case TIM_CLOCKSOURCE_TI1ED: |
| mbed_official | 354:e67efb2aab0e | 3845 | { |
| mbed_official | 354:e67efb2aab0e | 3846 | /* Check whether or not the timer instance supports external clock mode 1 */ |
| mbed_official | 354:e67efb2aab0e | 3847 | assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); |
| mbed_official | 354:e67efb2aab0e | 3848 | |
| mbed_official | 354:e67efb2aab0e | 3849 | TIM_TI1_ConfigInputStage(htim->Instance, |
| mbed_official | 354:e67efb2aab0e | 3850 | sClockSourceConfig->ClockPolarity, |
| mbed_official | 354:e67efb2aab0e | 3851 | sClockSourceConfig->ClockFilter); |
| mbed_official | 354:e67efb2aab0e | 3852 | TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED); |
| mbed_official | 354:e67efb2aab0e | 3853 | } |
| mbed_official | 354:e67efb2aab0e | 3854 | break; |
| mbed_official | 354:e67efb2aab0e | 3855 | case TIM_CLOCKSOURCE_ITR0: |
| mbed_official | 354:e67efb2aab0e | 3856 | { |
| mbed_official | 354:e67efb2aab0e | 3857 | /* Check whether or not the timer instance supports external clock mode 1 */ |
| mbed_official | 354:e67efb2aab0e | 3858 | assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); |
| mbed_official | 354:e67efb2aab0e | 3859 | |
| mbed_official | 354:e67efb2aab0e | 3860 | TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR0); |
| mbed_official | 354:e67efb2aab0e | 3861 | } |
| mbed_official | 354:e67efb2aab0e | 3862 | break; |
| mbed_official | 354:e67efb2aab0e | 3863 | case TIM_CLOCKSOURCE_ITR1: |
| mbed_official | 354:e67efb2aab0e | 3864 | { |
| mbed_official | 354:e67efb2aab0e | 3865 | /* Check whether or not the timer instance supports external clock mode 1 */ |
| mbed_official | 354:e67efb2aab0e | 3866 | assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); |
| mbed_official | 354:e67efb2aab0e | 3867 | |
| mbed_official | 354:e67efb2aab0e | 3868 | TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR1); |
| mbed_official | 354:e67efb2aab0e | 3869 | } |
| mbed_official | 354:e67efb2aab0e | 3870 | break; |
| mbed_official | 354:e67efb2aab0e | 3871 | case TIM_CLOCKSOURCE_ITR2: |
| mbed_official | 354:e67efb2aab0e | 3872 | { |
| mbed_official | 354:e67efb2aab0e | 3873 | /* Check whether or not the timer instance supports external clock mode 1 */ |
| mbed_official | 354:e67efb2aab0e | 3874 | assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); |
| mbed_official | 354:e67efb2aab0e | 3875 | |
| mbed_official | 354:e67efb2aab0e | 3876 | TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR2); |
| mbed_official | 354:e67efb2aab0e | 3877 | } |
| mbed_official | 354:e67efb2aab0e | 3878 | break; |
| mbed_official | 354:e67efb2aab0e | 3879 | case TIM_CLOCKSOURCE_ITR3: |
| mbed_official | 354:e67efb2aab0e | 3880 | { |
| mbed_official | 354:e67efb2aab0e | 3881 | /* Check whether or not the timer instance supports external clock mode 1 */ |
| mbed_official | 354:e67efb2aab0e | 3882 | assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); |
| mbed_official | 354:e67efb2aab0e | 3883 | |
| mbed_official | 354:e67efb2aab0e | 3884 | TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR3); |
| mbed_official | 354:e67efb2aab0e | 3885 | } |
| mbed_official | 354:e67efb2aab0e | 3886 | break; |
| mbed_official | 354:e67efb2aab0e | 3887 | |
| mbed_official | 354:e67efb2aab0e | 3888 | default: |
| mbed_official | 354:e67efb2aab0e | 3889 | break; |
| mbed_official | 354:e67efb2aab0e | 3890 | } |
| mbed_official | 354:e67efb2aab0e | 3891 | htim->State = HAL_TIM_STATE_READY; |
| mbed_official | 354:e67efb2aab0e | 3892 | |
| mbed_official | 354:e67efb2aab0e | 3893 | __HAL_UNLOCK(htim); |
| mbed_official | 354:e67efb2aab0e | 3894 | |
| mbed_official | 354:e67efb2aab0e | 3895 | return HAL_OK; |
| mbed_official | 354:e67efb2aab0e | 3896 | } |
| mbed_official | 354:e67efb2aab0e | 3897 | |
| mbed_official | 354:e67efb2aab0e | 3898 | /** |
| mbed_official | 354:e67efb2aab0e | 3899 | * @brief Selects the signal connected to the TI1 input: direct from CH1_input |
| mbed_official | 354:e67efb2aab0e | 3900 | * or a XOR combination between CH1_input, CH2_input & CH3_input |
| mbed_official | 354:e67efb2aab0e | 3901 | * @param htim: TIM handle. |
| mbed_official | 354:e67efb2aab0e | 3902 | * @param TI1_Selection: Indicate whether or not channel 1 is connected to the |
| mbed_official | 354:e67efb2aab0e | 3903 | * output of a XOR gate. |
| mbed_official | 354:e67efb2aab0e | 3904 | * This parameter can be one of the following values: |
| mbed_official | 354:e67efb2aab0e | 3905 | * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input |
| mbed_official | 354:e67efb2aab0e | 3906 | * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3 |
| mbed_official | 354:e67efb2aab0e | 3907 | * pins are connected to the TI1 input (XOR combination) |
| mbed_official | 354:e67efb2aab0e | 3908 | * @retval HAL status |
| mbed_official | 354:e67efb2aab0e | 3909 | */ |
| mbed_official | 354:e67efb2aab0e | 3910 | HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection) |
| mbed_official | 354:e67efb2aab0e | 3911 | { |
| mbed_official | 354:e67efb2aab0e | 3912 | uint32_t tmpcr2 = 0; |
| mbed_official | 354:e67efb2aab0e | 3913 | |
| mbed_official | 354:e67efb2aab0e | 3914 | /* Check the parameters */ |
| mbed_official | 354:e67efb2aab0e | 3915 | assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); |
| mbed_official | 354:e67efb2aab0e | 3916 | assert_param(IS_TIM_TI1SELECTION(TI1_Selection)); |
| mbed_official | 354:e67efb2aab0e | 3917 | |
| mbed_official | 354:e67efb2aab0e | 3918 | /* Get the TIMx CR2 register value */ |
| mbed_official | 354:e67efb2aab0e | 3919 | tmpcr2 = htim->Instance->CR2; |
| mbed_official | 354:e67efb2aab0e | 3920 | |
| mbed_official | 354:e67efb2aab0e | 3921 | /* Reset the TI1 selection */ |
| mbed_official | 354:e67efb2aab0e | 3922 | tmpcr2 &= ~TIM_CR2_TI1S; |
| mbed_official | 354:e67efb2aab0e | 3923 | |
| mbed_official | 354:e67efb2aab0e | 3924 | /* Set the the TI1 selection */ |
| mbed_official | 354:e67efb2aab0e | 3925 | tmpcr2 |= TI1_Selection; |
| mbed_official | 354:e67efb2aab0e | 3926 | |
| mbed_official | 354:e67efb2aab0e | 3927 | /* Write to TIMxCR2 */ |
| mbed_official | 354:e67efb2aab0e | 3928 | htim->Instance->CR2 = tmpcr2; |
| mbed_official | 354:e67efb2aab0e | 3929 | |
| mbed_official | 354:e67efb2aab0e | 3930 | return HAL_OK; |
| mbed_official | 354:e67efb2aab0e | 3931 | } |
| mbed_official | 354:e67efb2aab0e | 3932 | |
| mbed_official | 354:e67efb2aab0e | 3933 | /** |
| mbed_official | 354:e67efb2aab0e | 3934 | * @brief Configures the TIM in Slave mode |
| mbed_official | 354:e67efb2aab0e | 3935 | * @param htim: TIM handle. |
| mbed_official | 354:e67efb2aab0e | 3936 | * @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that |
| mbed_official | 354:e67efb2aab0e | 3937 | * contains the selected trigger (internal trigger input, filtered |
| mbed_official | 354:e67efb2aab0e | 3938 | * timer input or external trigger input) and the ) and the Slave |
| mbed_official | 354:e67efb2aab0e | 3939 | * mode (Disable, Reset, Gated, Trigger, External clock mode 1). |
| mbed_official | 354:e67efb2aab0e | 3940 | * @retval HAL status |
| mbed_official | 354:e67efb2aab0e | 3941 | */ |
| mbed_official | 354:e67efb2aab0e | 3942 | HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig) |
| mbed_official | 354:e67efb2aab0e | 3943 | { |
| mbed_official | 354:e67efb2aab0e | 3944 | uint32_t tmpsmcr = 0; |
| mbed_official | 354:e67efb2aab0e | 3945 | uint32_t tmpccmr1 = 0; |
| mbed_official | 354:e67efb2aab0e | 3946 | uint32_t tmpccer = 0; |
| mbed_official | 354:e67efb2aab0e | 3947 | |
| mbed_official | 354:e67efb2aab0e | 3948 | /* Check the parameters */ |
| mbed_official | 354:e67efb2aab0e | 3949 | assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); |
| mbed_official | 354:e67efb2aab0e | 3950 | assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode)); |
| mbed_official | 354:e67efb2aab0e | 3951 | assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger)); |
| mbed_official | 354:e67efb2aab0e | 3952 | |
| mbed_official | 354:e67efb2aab0e | 3953 | __HAL_LOCK(htim); |
| mbed_official | 354:e67efb2aab0e | 3954 | |
| mbed_official | 354:e67efb2aab0e | 3955 | htim->State = HAL_TIM_STATE_BUSY; |
| mbed_official | 354:e67efb2aab0e | 3956 | |
| mbed_official | 354:e67efb2aab0e | 3957 | /* Get the TIMx SMCR register value */ |
| mbed_official | 354:e67efb2aab0e | 3958 | tmpsmcr = htim->Instance->SMCR; |
| mbed_official | 354:e67efb2aab0e | 3959 | |
| mbed_official | 354:e67efb2aab0e | 3960 | /* Reset the Trigger Selection Bits */ |
| mbed_official | 354:e67efb2aab0e | 3961 | tmpsmcr &= ~TIM_SMCR_TS; |
| mbed_official | 354:e67efb2aab0e | 3962 | /* Set the Input Trigger source */ |
| mbed_official | 354:e67efb2aab0e | 3963 | tmpsmcr |= sSlaveConfig->InputTrigger; |
| mbed_official | 354:e67efb2aab0e | 3964 | |
| mbed_official | 354:e67efb2aab0e | 3965 | /* Reset the slave mode Bits */ |
| mbed_official | 354:e67efb2aab0e | 3966 | tmpsmcr &= ~TIM_SMCR_SMS; |
| mbed_official | 354:e67efb2aab0e | 3967 | /* Set the slave mode */ |
| mbed_official | 354:e67efb2aab0e | 3968 | tmpsmcr |= sSlaveConfig->SlaveMode; |
| mbed_official | 354:e67efb2aab0e | 3969 | |
| mbed_official | 354:e67efb2aab0e | 3970 | /* Write to TIMx SMCR */ |
| mbed_official | 354:e67efb2aab0e | 3971 | htim->Instance->SMCR = tmpsmcr; |
| mbed_official | 354:e67efb2aab0e | 3972 | |
| mbed_official | 354:e67efb2aab0e | 3973 | /* Configure the trigger prescaler, filter, and polarity */ |
| mbed_official | 354:e67efb2aab0e | 3974 | switch (sSlaveConfig->InputTrigger) |
| mbed_official | 354:e67efb2aab0e | 3975 | { |
| mbed_official | 354:e67efb2aab0e | 3976 | case TIM_TS_ETRF: |
| mbed_official | 354:e67efb2aab0e | 3977 | { |
| mbed_official | 354:e67efb2aab0e | 3978 | /* Check the parameters */ |
| mbed_official | 354:e67efb2aab0e | 3979 | assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance)); |
| mbed_official | 354:e67efb2aab0e | 3980 | assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler)); |
| mbed_official | 354:e67efb2aab0e | 3981 | assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); |
| mbed_official | 354:e67efb2aab0e | 3982 | assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); |
| mbed_official | 354:e67efb2aab0e | 3983 | /* Configure the ETR Trigger source */ |
| mbed_official | 354:e67efb2aab0e | 3984 | TIM_ETR_SetConfig(htim->Instance, |
| mbed_official | 354:e67efb2aab0e | 3985 | sSlaveConfig->TriggerPrescaler, |
| mbed_official | 354:e67efb2aab0e | 3986 | sSlaveConfig->TriggerPolarity, |
| mbed_official | 354:e67efb2aab0e | 3987 | sSlaveConfig->TriggerFilter); |
| mbed_official | 354:e67efb2aab0e | 3988 | } |
| mbed_official | 354:e67efb2aab0e | 3989 | break; |
| mbed_official | 354:e67efb2aab0e | 3990 | |
| mbed_official | 354:e67efb2aab0e | 3991 | case TIM_TS_TI1F_ED: |
| mbed_official | 354:e67efb2aab0e | 3992 | { |
| mbed_official | 354:e67efb2aab0e | 3993 | /* Check the parameters */ |
| mbed_official | 354:e67efb2aab0e | 3994 | assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); |
| mbed_official | 354:e67efb2aab0e | 3995 | assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); |
| mbed_official | 354:e67efb2aab0e | 3996 | assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); |
| mbed_official | 354:e67efb2aab0e | 3997 | |
| mbed_official | 354:e67efb2aab0e | 3998 | /* Disable the Channel 1: Reset the CC1E Bit */ |
| mbed_official | 354:e67efb2aab0e | 3999 | tmpccer = htim->Instance->CCER; |
| mbed_official | 354:e67efb2aab0e | 4000 | htim->Instance->CCER &= ~TIM_CCER_CC1E; |
| mbed_official | 354:e67efb2aab0e | 4001 | tmpccmr1 = htim->Instance->CCMR1; |
| mbed_official | 354:e67efb2aab0e | 4002 | |
| mbed_official | 354:e67efb2aab0e | 4003 | /* Set the filter */ |
| mbed_official | 354:e67efb2aab0e | 4004 | tmpccmr1 &= ~TIM_CCMR1_IC1F; |
| mbed_official | 354:e67efb2aab0e | 4005 | tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4); |
| mbed_official | 354:e67efb2aab0e | 4006 | |
| mbed_official | 354:e67efb2aab0e | 4007 | /* Write to TIMx CCMR1 and CCER registers */ |
| mbed_official | 354:e67efb2aab0e | 4008 | htim->Instance->CCMR1 = tmpccmr1; |
| mbed_official | 354:e67efb2aab0e | 4009 | htim->Instance->CCER = tmpccer; |
| mbed_official | 354:e67efb2aab0e | 4010 | |
| mbed_official | 354:e67efb2aab0e | 4011 | } |
| mbed_official | 354:e67efb2aab0e | 4012 | break; |
| mbed_official | 354:e67efb2aab0e | 4013 | |
| mbed_official | 354:e67efb2aab0e | 4014 | case TIM_TS_TI1FP1: |
| mbed_official | 354:e67efb2aab0e | 4015 | { |
| mbed_official | 354:e67efb2aab0e | 4016 | /* Check the parameters */ |
| mbed_official | 354:e67efb2aab0e | 4017 | assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); |
| mbed_official | 354:e67efb2aab0e | 4018 | assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); |
| mbed_official | 354:e67efb2aab0e | 4019 | assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); |
| mbed_official | 354:e67efb2aab0e | 4020 | |
| mbed_official | 354:e67efb2aab0e | 4021 | /* Configure TI1 Filter and Polarity */ |
| mbed_official | 354:e67efb2aab0e | 4022 | TIM_TI1_ConfigInputStage(htim->Instance, |
| mbed_official | 354:e67efb2aab0e | 4023 | sSlaveConfig->TriggerPolarity, |
| mbed_official | 354:e67efb2aab0e | 4024 | sSlaveConfig->TriggerFilter); |
| mbed_official | 354:e67efb2aab0e | 4025 | } |
| mbed_official | 354:e67efb2aab0e | 4026 | break; |
| mbed_official | 354:e67efb2aab0e | 4027 | |
| mbed_official | 354:e67efb2aab0e | 4028 | case TIM_TS_TI2FP2: |
| mbed_official | 354:e67efb2aab0e | 4029 | { |
| mbed_official | 354:e67efb2aab0e | 4030 | /* Check the parameters */ |
| mbed_official | 354:e67efb2aab0e | 4031 | assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); |
| mbed_official | 354:e67efb2aab0e | 4032 | assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); |
| mbed_official | 354:e67efb2aab0e | 4033 | assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); |
| mbed_official | 354:e67efb2aab0e | 4034 | |
| mbed_official | 354:e67efb2aab0e | 4035 | /* Configure TI2 Filter and Polarity */ |
| mbed_official | 354:e67efb2aab0e | 4036 | TIM_TI2_ConfigInputStage(htim->Instance, |
| mbed_official | 354:e67efb2aab0e | 4037 | sSlaveConfig->TriggerPolarity, |
| mbed_official | 354:e67efb2aab0e | 4038 | sSlaveConfig->TriggerFilter); |
| mbed_official | 354:e67efb2aab0e | 4039 | } |
| mbed_official | 354:e67efb2aab0e | 4040 | break; |
| mbed_official | 354:e67efb2aab0e | 4041 | |
| mbed_official | 354:e67efb2aab0e | 4042 | case TIM_TS_ITR0: |
| mbed_official | 354:e67efb2aab0e | 4043 | { |
| mbed_official | 354:e67efb2aab0e | 4044 | /* Check the parameter */ |
| mbed_official | 354:e67efb2aab0e | 4045 | assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); |
| mbed_official | 354:e67efb2aab0e | 4046 | } |
| mbed_official | 354:e67efb2aab0e | 4047 | break; |
| mbed_official | 354:e67efb2aab0e | 4048 | |
| mbed_official | 354:e67efb2aab0e | 4049 | case TIM_TS_ITR1: |
| mbed_official | 354:e67efb2aab0e | 4050 | { |
| mbed_official | 354:e67efb2aab0e | 4051 | /* Check the parameter */ |
| mbed_official | 354:e67efb2aab0e | 4052 | assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); |
| mbed_official | 354:e67efb2aab0e | 4053 | } |
| mbed_official | 354:e67efb2aab0e | 4054 | break; |
| mbed_official | 354:e67efb2aab0e | 4055 | |
| mbed_official | 354:e67efb2aab0e | 4056 | case TIM_TS_ITR2: |
| mbed_official | 354:e67efb2aab0e | 4057 | { |
| mbed_official | 354:e67efb2aab0e | 4058 | /* Check the parameter */ |
| mbed_official | 354:e67efb2aab0e | 4059 | assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); |
| mbed_official | 354:e67efb2aab0e | 4060 | } |
| mbed_official | 354:e67efb2aab0e | 4061 | break; |
| mbed_official | 354:e67efb2aab0e | 4062 | |
| mbed_official | 354:e67efb2aab0e | 4063 | case TIM_TS_ITR3: |
| mbed_official | 354:e67efb2aab0e | 4064 | { |
| mbed_official | 354:e67efb2aab0e | 4065 | /* Check the parameter */ |
| mbed_official | 354:e67efb2aab0e | 4066 | assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); |
| mbed_official | 354:e67efb2aab0e | 4067 | } |
| mbed_official | 354:e67efb2aab0e | 4068 | break; |
| mbed_official | 354:e67efb2aab0e | 4069 | |
| mbed_official | 354:e67efb2aab0e | 4070 | default: |
| mbed_official | 354:e67efb2aab0e | 4071 | break; |
| mbed_official | 354:e67efb2aab0e | 4072 | } |
| mbed_official | 354:e67efb2aab0e | 4073 | |
| mbed_official | 354:e67efb2aab0e | 4074 | htim->State = HAL_TIM_STATE_READY; |
| mbed_official | 354:e67efb2aab0e | 4075 | |
| mbed_official | 354:e67efb2aab0e | 4076 | __HAL_UNLOCK(htim); |
| mbed_official | 354:e67efb2aab0e | 4077 | |
| mbed_official | 354:e67efb2aab0e | 4078 | return HAL_OK; |
| mbed_official | 354:e67efb2aab0e | 4079 | } |
| mbed_official | 354:e67efb2aab0e | 4080 | |
| mbed_official | 354:e67efb2aab0e | 4081 | /** |
| mbed_official | 354:e67efb2aab0e | 4082 | * @brief Read the captured value from Capture Compare unit |
| mbed_official | 354:e67efb2aab0e | 4083 | * @param htim: TIM handle. |
| mbed_official | 354:e67efb2aab0e | 4084 | * @param Channel : TIM Channels to be enabled |
| mbed_official | 354:e67efb2aab0e | 4085 | * This parameter can be one of the following values: |
| mbed_official | 354:e67efb2aab0e | 4086 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| mbed_official | 354:e67efb2aab0e | 4087 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| mbed_official | 354:e67efb2aab0e | 4088 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
| mbed_official | 354:e67efb2aab0e | 4089 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
| mbed_official | 354:e67efb2aab0e | 4090 | * @retval Captured value |
| mbed_official | 354:e67efb2aab0e | 4091 | */ |
| mbed_official | 354:e67efb2aab0e | 4092 | uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel) |
| mbed_official | 354:e67efb2aab0e | 4093 | { |
| mbed_official | 354:e67efb2aab0e | 4094 | uint32_t tmpreg = 0; |
| mbed_official | 354:e67efb2aab0e | 4095 | |
| mbed_official | 354:e67efb2aab0e | 4096 | __HAL_LOCK(htim); |
| mbed_official | 354:e67efb2aab0e | 4097 | |
| mbed_official | 354:e67efb2aab0e | 4098 | switch (Channel) |
| mbed_official | 354:e67efb2aab0e | 4099 | { |
| mbed_official | 354:e67efb2aab0e | 4100 | case TIM_CHANNEL_1: |
| mbed_official | 354:e67efb2aab0e | 4101 | { |
| mbed_official | 354:e67efb2aab0e | 4102 | /* Check the parameters */ |
| mbed_official | 354:e67efb2aab0e | 4103 | assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); |
| mbed_official | 354:e67efb2aab0e | 4104 | |
| mbed_official | 354:e67efb2aab0e | 4105 | /* Return the capture 1 value */ |
| mbed_official | 354:e67efb2aab0e | 4106 | tmpreg = htim->Instance->CCR1; |
| mbed_official | 354:e67efb2aab0e | 4107 | |
| mbed_official | 354:e67efb2aab0e | 4108 | break; |
| mbed_official | 354:e67efb2aab0e | 4109 | } |
| mbed_official | 354:e67efb2aab0e | 4110 | case TIM_CHANNEL_2: |
| mbed_official | 354:e67efb2aab0e | 4111 | { |
| mbed_official | 354:e67efb2aab0e | 4112 | /* Check the parameters */ |
| mbed_official | 354:e67efb2aab0e | 4113 | assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); |
| mbed_official | 354:e67efb2aab0e | 4114 | |
| mbed_official | 354:e67efb2aab0e | 4115 | /* Return the capture 2 value */ |
| mbed_official | 354:e67efb2aab0e | 4116 | tmpreg = htim->Instance->CCR2; |
| mbed_official | 354:e67efb2aab0e | 4117 | |
| mbed_official | 354:e67efb2aab0e | 4118 | break; |
| mbed_official | 354:e67efb2aab0e | 4119 | } |
| mbed_official | 354:e67efb2aab0e | 4120 | |
| mbed_official | 354:e67efb2aab0e | 4121 | case TIM_CHANNEL_3: |
| mbed_official | 354:e67efb2aab0e | 4122 | { |
| mbed_official | 354:e67efb2aab0e | 4123 | /* Check the parameters */ |
| mbed_official | 354:e67efb2aab0e | 4124 | assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); |
| mbed_official | 354:e67efb2aab0e | 4125 | |
| mbed_official | 354:e67efb2aab0e | 4126 | /* Return the capture 3 value */ |
| mbed_official | 354:e67efb2aab0e | 4127 | tmpreg = htim->Instance->CCR3; |
| mbed_official | 354:e67efb2aab0e | 4128 | |
| mbed_official | 354:e67efb2aab0e | 4129 | break; |
| mbed_official | 354:e67efb2aab0e | 4130 | } |
| mbed_official | 354:e67efb2aab0e | 4131 | |
| mbed_official | 354:e67efb2aab0e | 4132 | case TIM_CHANNEL_4: |
| mbed_official | 354:e67efb2aab0e | 4133 | { |
| mbed_official | 354:e67efb2aab0e | 4134 | /* Check the parameters */ |
| mbed_official | 354:e67efb2aab0e | 4135 | assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); |
| mbed_official | 354:e67efb2aab0e | 4136 | |
| mbed_official | 354:e67efb2aab0e | 4137 | /* Return the capture 4 value */ |
| mbed_official | 354:e67efb2aab0e | 4138 | tmpreg = htim->Instance->CCR4; |
| mbed_official | 354:e67efb2aab0e | 4139 | |
| mbed_official | 354:e67efb2aab0e | 4140 | break; |
| mbed_official | 354:e67efb2aab0e | 4141 | } |
| mbed_official | 354:e67efb2aab0e | 4142 | |
| mbed_official | 354:e67efb2aab0e | 4143 | default: |
| mbed_official | 354:e67efb2aab0e | 4144 | break; |
| mbed_official | 354:e67efb2aab0e | 4145 | } |
| mbed_official | 354:e67efb2aab0e | 4146 | |
| mbed_official | 354:e67efb2aab0e | 4147 | __HAL_UNLOCK(htim); |
| mbed_official | 354:e67efb2aab0e | 4148 | return tmpreg; |
| mbed_official | 354:e67efb2aab0e | 4149 | } |
| mbed_official | 354:e67efb2aab0e | 4150 | |
| mbed_official | 354:e67efb2aab0e | 4151 | /** |
| mbed_official | 354:e67efb2aab0e | 4152 | * @} |
| mbed_official | 354:e67efb2aab0e | 4153 | */ |
| mbed_official | 354:e67efb2aab0e | 4154 | |
| mbed_official | 354:e67efb2aab0e | 4155 | /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions |
| mbed_official | 354:e67efb2aab0e | 4156 | * @brief TIM Callbacks functions |
| mbed_official | 354:e67efb2aab0e | 4157 | * |
| mbed_official | 354:e67efb2aab0e | 4158 | @verbatim |
| mbed_official | 354:e67efb2aab0e | 4159 | ============================================================================== |
| mbed_official | 354:e67efb2aab0e | 4160 | ##### TIM Callbacks functions ##### |
| mbed_official | 354:e67efb2aab0e | 4161 | ============================================================================== |
| mbed_official | 354:e67efb2aab0e | 4162 | [..] |
| mbed_official | 354:e67efb2aab0e | 4163 | This section provides TIM callback functions: |
| mbed_official | 354:e67efb2aab0e | 4164 | (+) Timer Period elapsed callback |
| mbed_official | 354:e67efb2aab0e | 4165 | (+) Timer Output Compare callback |
| mbed_official | 354:e67efb2aab0e | 4166 | (+) Timer Input capture callback |
| mbed_official | 354:e67efb2aab0e | 4167 | (+) Timer Trigger callback |
| mbed_official | 354:e67efb2aab0e | 4168 | (+) Timer Error callback |
| mbed_official | 354:e67efb2aab0e | 4169 | |
| mbed_official | 354:e67efb2aab0e | 4170 | @endverbatim |
| mbed_official | 354:e67efb2aab0e | 4171 | * @{ |
| mbed_official | 354:e67efb2aab0e | 4172 | */ |
| mbed_official | 354:e67efb2aab0e | 4173 | |
| mbed_official | 354:e67efb2aab0e | 4174 | /** |
| mbed_official | 354:e67efb2aab0e | 4175 | * @brief Period elapsed callback in non blocking mode |
| mbed_official | 354:e67efb2aab0e | 4176 | * @param htim : TIM handle |
| mbed_official | 354:e67efb2aab0e | 4177 | * @retval None |
| mbed_official | 354:e67efb2aab0e | 4178 | */ |
| mbed_official | 354:e67efb2aab0e | 4179 | __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) |
| mbed_official | 354:e67efb2aab0e | 4180 | { |
| mbed_official | 354:e67efb2aab0e | 4181 | /* NOTE : This function Should not be modified, when the callback is needed, |
| mbed_official | 354:e67efb2aab0e | 4182 | the __HAL_TIM_PeriodElapsedCallback could be implemented in the user file |
| mbed_official | 354:e67efb2aab0e | 4183 | */ |
| mbed_official | 354:e67efb2aab0e | 4184 | |
| mbed_official | 354:e67efb2aab0e | 4185 | } |
| mbed_official | 354:e67efb2aab0e | 4186 | /** |
| mbed_official | 354:e67efb2aab0e | 4187 | * @brief Output Compare callback in non blocking mode |
| mbed_official | 354:e67efb2aab0e | 4188 | * @param htim : TIM OC handle |
| mbed_official | 354:e67efb2aab0e | 4189 | * @retval None |
| mbed_official | 354:e67efb2aab0e | 4190 | */ |
| mbed_official | 354:e67efb2aab0e | 4191 | __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) |
| mbed_official | 354:e67efb2aab0e | 4192 | { |
| mbed_official | 354:e67efb2aab0e | 4193 | /* NOTE : This function Should not be modified, when the callback is needed, |
| mbed_official | 354:e67efb2aab0e | 4194 | the __HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file |
| mbed_official | 354:e67efb2aab0e | 4195 | */ |
| mbed_official | 354:e67efb2aab0e | 4196 | } |
| mbed_official | 354:e67efb2aab0e | 4197 | /** |
| mbed_official | 354:e67efb2aab0e | 4198 | * @brief Input Capture callback in non blocking mode |
| mbed_official | 354:e67efb2aab0e | 4199 | * @param htim : TIM IC handle |
| mbed_official | 354:e67efb2aab0e | 4200 | * @retval None |
| mbed_official | 354:e67efb2aab0e | 4201 | */ |
| mbed_official | 354:e67efb2aab0e | 4202 | __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) |
| mbed_official | 354:e67efb2aab0e | 4203 | { |
| mbed_official | 354:e67efb2aab0e | 4204 | /* NOTE : This function Should not be modified, when the callback is needed, |
| mbed_official | 354:e67efb2aab0e | 4205 | the __HAL_TIM_IC_CaptureCallback could be implemented in the user file |
| mbed_official | 354:e67efb2aab0e | 4206 | */ |
| mbed_official | 354:e67efb2aab0e | 4207 | } |
| mbed_official | 354:e67efb2aab0e | 4208 | |
| mbed_official | 354:e67efb2aab0e | 4209 | /** |
| mbed_official | 354:e67efb2aab0e | 4210 | * @brief PWM Pulse finished callback in non blocking mode |
| mbed_official | 354:e67efb2aab0e | 4211 | * @param htim : TIM handle |
| mbed_official | 354:e67efb2aab0e | 4212 | * @retval None |
| mbed_official | 354:e67efb2aab0e | 4213 | */ |
| mbed_official | 354:e67efb2aab0e | 4214 | __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) |
| mbed_official | 354:e67efb2aab0e | 4215 | { |
| mbed_official | 354:e67efb2aab0e | 4216 | /* NOTE : This function Should not be modified, when the callback is needed, |
| mbed_official | 354:e67efb2aab0e | 4217 | the __HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file |
| mbed_official | 354:e67efb2aab0e | 4218 | */ |
| mbed_official | 354:e67efb2aab0e | 4219 | } |
| mbed_official | 354:e67efb2aab0e | 4220 | |
| mbed_official | 354:e67efb2aab0e | 4221 | /** |
| mbed_official | 354:e67efb2aab0e | 4222 | * @brief Hall Trigger detection callback in non blocking mode |
| mbed_official | 354:e67efb2aab0e | 4223 | * @param htim : TIM handle |
| mbed_official | 354:e67efb2aab0e | 4224 | * @retval None |
| mbed_official | 354:e67efb2aab0e | 4225 | */ |
| mbed_official | 354:e67efb2aab0e | 4226 | __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) |
| mbed_official | 354:e67efb2aab0e | 4227 | { |
| mbed_official | 354:e67efb2aab0e | 4228 | /* NOTE : This function Should not be modified, when the callback is needed, |
| mbed_official | 354:e67efb2aab0e | 4229 | the HAL_TIM_TriggerCallback could be implemented in the user file |
| mbed_official | 354:e67efb2aab0e | 4230 | */ |
| mbed_official | 354:e67efb2aab0e | 4231 | } |
| mbed_official | 354:e67efb2aab0e | 4232 | |
| mbed_official | 354:e67efb2aab0e | 4233 | /** |
| mbed_official | 354:e67efb2aab0e | 4234 | * @brief Timer error callback in non blocking mode |
| mbed_official | 354:e67efb2aab0e | 4235 | * @param htim : TIM handle |
| mbed_official | 354:e67efb2aab0e | 4236 | * @retval None |
| mbed_official | 354:e67efb2aab0e | 4237 | */ |
| mbed_official | 354:e67efb2aab0e | 4238 | __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim) |
| mbed_official | 354:e67efb2aab0e | 4239 | { |
| mbed_official | 354:e67efb2aab0e | 4240 | /* NOTE : This function Should not be modified, when the callback is needed, |
| mbed_official | 354:e67efb2aab0e | 4241 | the HAL_TIM_ErrorCallback could be implemented in the user file |
| mbed_official | 354:e67efb2aab0e | 4242 | */ |
| mbed_official | 354:e67efb2aab0e | 4243 | } |
| mbed_official | 354:e67efb2aab0e | 4244 | |
| mbed_official | 354:e67efb2aab0e | 4245 | /** |
| mbed_official | 354:e67efb2aab0e | 4246 | * @} |
| mbed_official | 354:e67efb2aab0e | 4247 | */ |
| mbed_official | 354:e67efb2aab0e | 4248 | |
| mbed_official | 354:e67efb2aab0e | 4249 | /** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions |
| mbed_official | 354:e67efb2aab0e | 4250 | * @brief Peripheral State functions |
| mbed_official | 354:e67efb2aab0e | 4251 | * |
| mbed_official | 354:e67efb2aab0e | 4252 | @verbatim |
| mbed_official | 354:e67efb2aab0e | 4253 | ============================================================================== |
| mbed_official | 354:e67efb2aab0e | 4254 | ##### Peripheral State functions ##### |
| mbed_official | 354:e67efb2aab0e | 4255 | ============================================================================== |
| mbed_official | 354:e67efb2aab0e | 4256 | [..] |
| mbed_official | 354:e67efb2aab0e | 4257 | This subsection permit to get in run-time the status of the peripheral |
| mbed_official | 354:e67efb2aab0e | 4258 | and the data flow. |
| mbed_official | 354:e67efb2aab0e | 4259 | |
| mbed_official | 354:e67efb2aab0e | 4260 | @endverbatim |
| mbed_official | 354:e67efb2aab0e | 4261 | * @{ |
| mbed_official | 354:e67efb2aab0e | 4262 | */ |
| mbed_official | 354:e67efb2aab0e | 4263 | |
| mbed_official | 354:e67efb2aab0e | 4264 | /** |
| mbed_official | 354:e67efb2aab0e | 4265 | * @brief Return the TIM Base state |
| mbed_official | 354:e67efb2aab0e | 4266 | * @param htim: TIM Base handle |
| mbed_official | 354:e67efb2aab0e | 4267 | * @retval HAL state |
| mbed_official | 354:e67efb2aab0e | 4268 | */ |
| mbed_official | 354:e67efb2aab0e | 4269 | HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim) |
| mbed_official | 354:e67efb2aab0e | 4270 | { |
| mbed_official | 354:e67efb2aab0e | 4271 | return htim->State; |
| mbed_official | 354:e67efb2aab0e | 4272 | } |
| mbed_official | 354:e67efb2aab0e | 4273 | |
| mbed_official | 354:e67efb2aab0e | 4274 | /** |
| mbed_official | 354:e67efb2aab0e | 4275 | * @brief Return the TIM OC state |
| mbed_official | 354:e67efb2aab0e | 4276 | * @param htim: TIM Ouput Compare handle |
| mbed_official | 354:e67efb2aab0e | 4277 | * @retval HAL state |
| mbed_official | 354:e67efb2aab0e | 4278 | */ |
| mbed_official | 354:e67efb2aab0e | 4279 | HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim) |
| mbed_official | 354:e67efb2aab0e | 4280 | { |
| mbed_official | 354:e67efb2aab0e | 4281 | return htim->State; |
| mbed_official | 354:e67efb2aab0e | 4282 | } |
| mbed_official | 354:e67efb2aab0e | 4283 | |
| mbed_official | 354:e67efb2aab0e | 4284 | /** |
| mbed_official | 354:e67efb2aab0e | 4285 | * @brief Return the TIM PWM state |
| mbed_official | 354:e67efb2aab0e | 4286 | * @param htim: TIM handle |
| mbed_official | 354:e67efb2aab0e | 4287 | * @retval HAL state |
| mbed_official | 354:e67efb2aab0e | 4288 | */ |
| mbed_official | 354:e67efb2aab0e | 4289 | HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim) |
| mbed_official | 354:e67efb2aab0e | 4290 | { |
| mbed_official | 354:e67efb2aab0e | 4291 | return htim->State; |
| mbed_official | 354:e67efb2aab0e | 4292 | } |
| mbed_official | 354:e67efb2aab0e | 4293 | |
| mbed_official | 354:e67efb2aab0e | 4294 | /** |
| mbed_official | 354:e67efb2aab0e | 4295 | * @brief Return the TIM Input Capture state |
| mbed_official | 354:e67efb2aab0e | 4296 | * @param htim: TIM IC handle |
| mbed_official | 354:e67efb2aab0e | 4297 | * @retval HAL state |
| mbed_official | 354:e67efb2aab0e | 4298 | */ |
| mbed_official | 354:e67efb2aab0e | 4299 | HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim) |
| mbed_official | 354:e67efb2aab0e | 4300 | { |
| mbed_official | 354:e67efb2aab0e | 4301 | return htim->State; |
| mbed_official | 354:e67efb2aab0e | 4302 | } |
| mbed_official | 354:e67efb2aab0e | 4303 | |
| mbed_official | 354:e67efb2aab0e | 4304 | /** |
| mbed_official | 354:e67efb2aab0e | 4305 | * @brief Return the TIM One Pulse Mode state |
| mbed_official | 354:e67efb2aab0e | 4306 | * @param htim: TIM OPM handle |
| mbed_official | 354:e67efb2aab0e | 4307 | * @retval HAL state |
| mbed_official | 354:e67efb2aab0e | 4308 | */ |
| mbed_official | 354:e67efb2aab0e | 4309 | HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim) |
| mbed_official | 354:e67efb2aab0e | 4310 | { |
| mbed_official | 354:e67efb2aab0e | 4311 | return htim->State; |
| mbed_official | 354:e67efb2aab0e | 4312 | } |
| mbed_official | 354:e67efb2aab0e | 4313 | |
| mbed_official | 354:e67efb2aab0e | 4314 | /** |
| mbed_official | 354:e67efb2aab0e | 4315 | * @brief Return the TIM Encoder Mode state |
| mbed_official | 354:e67efb2aab0e | 4316 | * @param htim: TIM Encoder handle |
| mbed_official | 354:e67efb2aab0e | 4317 | * @retval HAL state |
| mbed_official | 354:e67efb2aab0e | 4318 | */ |
| mbed_official | 354:e67efb2aab0e | 4319 | HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim) |
| mbed_official | 354:e67efb2aab0e | 4320 | { |
| mbed_official | 354:e67efb2aab0e | 4321 | return htim->State; |
| mbed_official | 354:e67efb2aab0e | 4322 | } |
| mbed_official | 354:e67efb2aab0e | 4323 | |
| mbed_official | 354:e67efb2aab0e | 4324 | /** |
| mbed_official | 354:e67efb2aab0e | 4325 | * @} |
| mbed_official | 354:e67efb2aab0e | 4326 | */ |
| mbed_official | 354:e67efb2aab0e | 4327 | |
| mbed_official | 354:e67efb2aab0e | 4328 | /** |
| mbed_official | 354:e67efb2aab0e | 4329 | * @} |
| mbed_official | 354:e67efb2aab0e | 4330 | */ |
| mbed_official | 354:e67efb2aab0e | 4331 | |
| mbed_official | 354:e67efb2aab0e | 4332 | |
| mbed_official | 354:e67efb2aab0e | 4333 | /** @addtogroup TIM_Private_Functions |
| mbed_official | 354:e67efb2aab0e | 4334 | * @{ |
| mbed_official | 354:e67efb2aab0e | 4335 | */ |
| mbed_official | 354:e67efb2aab0e | 4336 | |
| mbed_official | 354:e67efb2aab0e | 4337 | |
| mbed_official | 354:e67efb2aab0e | 4338 | /** |
| mbed_official | 354:e67efb2aab0e | 4339 | * @brief TIM DMA error callback |
| mbed_official | 354:e67efb2aab0e | 4340 | * @param hdma : pointer to DMA handle. |
| mbed_official | 354:e67efb2aab0e | 4341 | * @retval None |
| mbed_official | 354:e67efb2aab0e | 4342 | */ |
| mbed_official | 354:e67efb2aab0e | 4343 | static void TIM_DMAError(DMA_HandleTypeDef *hdma) |
| mbed_official | 354:e67efb2aab0e | 4344 | { |
| mbed_official | 354:e67efb2aab0e | 4345 | TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; |
| mbed_official | 354:e67efb2aab0e | 4346 | |
| mbed_official | 354:e67efb2aab0e | 4347 | htim->State= HAL_TIM_STATE_READY; |
| mbed_official | 354:e67efb2aab0e | 4348 | |
| mbed_official | 354:e67efb2aab0e | 4349 | HAL_TIM_ErrorCallback(htim); |
| mbed_official | 354:e67efb2aab0e | 4350 | } |
| mbed_official | 354:e67efb2aab0e | 4351 | |
| mbed_official | 354:e67efb2aab0e | 4352 | /** |
| mbed_official | 354:e67efb2aab0e | 4353 | * @brief TIM DMA Delay Pulse complete callback. |
| mbed_official | 354:e67efb2aab0e | 4354 | * @param hdma : pointer to DMA handle. |
| mbed_official | 354:e67efb2aab0e | 4355 | * @retval None |
| mbed_official | 354:e67efb2aab0e | 4356 | */ |
| mbed_official | 354:e67efb2aab0e | 4357 | static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma) |
| mbed_official | 354:e67efb2aab0e | 4358 | { |
| mbed_official | 354:e67efb2aab0e | 4359 | TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; |
| mbed_official | 354:e67efb2aab0e | 4360 | |
| mbed_official | 354:e67efb2aab0e | 4361 | htim->State= HAL_TIM_STATE_READY; |
| mbed_official | 354:e67efb2aab0e | 4362 | |
| mbed_official | 354:e67efb2aab0e | 4363 | if (hdma == htim->hdma[TIM_DMA_ID_CC1]) |
| mbed_official | 354:e67efb2aab0e | 4364 | { |
| mbed_official | 354:e67efb2aab0e | 4365 | htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; |
| mbed_official | 354:e67efb2aab0e | 4366 | } |
| mbed_official | 354:e67efb2aab0e | 4367 | else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) |
| mbed_official | 354:e67efb2aab0e | 4368 | { |
| mbed_official | 354:e67efb2aab0e | 4369 | htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; |
| mbed_official | 354:e67efb2aab0e | 4370 | } |
| mbed_official | 354:e67efb2aab0e | 4371 | else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) |
| mbed_official | 354:e67efb2aab0e | 4372 | { |
| mbed_official | 354:e67efb2aab0e | 4373 | htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; |
| mbed_official | 354:e67efb2aab0e | 4374 | } |
| mbed_official | 354:e67efb2aab0e | 4375 | else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) |
| mbed_official | 354:e67efb2aab0e | 4376 | { |
| mbed_official | 354:e67efb2aab0e | 4377 | htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; |
| mbed_official | 354:e67efb2aab0e | 4378 | } |
| mbed_official | 354:e67efb2aab0e | 4379 | |
| mbed_official | 354:e67efb2aab0e | 4380 | HAL_TIM_PWM_PulseFinishedCallback(htim); |
| mbed_official | 354:e67efb2aab0e | 4381 | |
| mbed_official | 354:e67efb2aab0e | 4382 | htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; |
| mbed_official | 354:e67efb2aab0e | 4383 | } |
| mbed_official | 354:e67efb2aab0e | 4384 | |
| mbed_official | 354:e67efb2aab0e | 4385 | /** |
| mbed_official | 354:e67efb2aab0e | 4386 | * @brief TIM DMA Capture complete callback. |
| mbed_official | 354:e67efb2aab0e | 4387 | * @param hdma : pointer to DMA handle. |
| mbed_official | 354:e67efb2aab0e | 4388 | * @retval None |
| mbed_official | 354:e67efb2aab0e | 4389 | */ |
| mbed_official | 354:e67efb2aab0e | 4390 | static void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma) |
| mbed_official | 354:e67efb2aab0e | 4391 | { |
| mbed_official | 354:e67efb2aab0e | 4392 | TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; |
| mbed_official | 354:e67efb2aab0e | 4393 | |
| mbed_official | 354:e67efb2aab0e | 4394 | htim->State= HAL_TIM_STATE_READY; |
| mbed_official | 354:e67efb2aab0e | 4395 | |
| mbed_official | 354:e67efb2aab0e | 4396 | if (hdma == htim->hdma[TIM_DMA_ID_CC1]) |
| mbed_official | 354:e67efb2aab0e | 4397 | { |
| mbed_official | 354:e67efb2aab0e | 4398 | htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; |
| mbed_official | 354:e67efb2aab0e | 4399 | } |
| mbed_official | 354:e67efb2aab0e | 4400 | else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) |
| mbed_official | 354:e67efb2aab0e | 4401 | { |
| mbed_official | 354:e67efb2aab0e | 4402 | htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; |
| mbed_official | 354:e67efb2aab0e | 4403 | } |
| mbed_official | 354:e67efb2aab0e | 4404 | else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) |
| mbed_official | 354:e67efb2aab0e | 4405 | { |
| mbed_official | 354:e67efb2aab0e | 4406 | htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; |
| mbed_official | 354:e67efb2aab0e | 4407 | } |
| mbed_official | 354:e67efb2aab0e | 4408 | else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) |
| mbed_official | 354:e67efb2aab0e | 4409 | { |
| mbed_official | 354:e67efb2aab0e | 4410 | htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; |
| mbed_official | 354:e67efb2aab0e | 4411 | } |
| mbed_official | 354:e67efb2aab0e | 4412 | |
| mbed_official | 354:e67efb2aab0e | 4413 | HAL_TIM_IC_CaptureCallback(htim); |
| mbed_official | 354:e67efb2aab0e | 4414 | |
| mbed_official | 354:e67efb2aab0e | 4415 | htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; |
| mbed_official | 354:e67efb2aab0e | 4416 | } |
| mbed_official | 354:e67efb2aab0e | 4417 | |
| mbed_official | 354:e67efb2aab0e | 4418 | /** |
| mbed_official | 354:e67efb2aab0e | 4419 | * @brief TIM DMA Period Elapse complete callback. |
| mbed_official | 354:e67efb2aab0e | 4420 | * @param hdma : pointer to DMA handle. |
| mbed_official | 354:e67efb2aab0e | 4421 | * @retval None |
| mbed_official | 354:e67efb2aab0e | 4422 | */ |
| mbed_official | 354:e67efb2aab0e | 4423 | static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma) |
| mbed_official | 354:e67efb2aab0e | 4424 | { |
| mbed_official | 354:e67efb2aab0e | 4425 | TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; |
| mbed_official | 354:e67efb2aab0e | 4426 | |
| mbed_official | 354:e67efb2aab0e | 4427 | htim->State= HAL_TIM_STATE_READY; |
| mbed_official | 354:e67efb2aab0e | 4428 | |
| mbed_official | 354:e67efb2aab0e | 4429 | HAL_TIM_PeriodElapsedCallback(htim); |
| mbed_official | 354:e67efb2aab0e | 4430 | } |
| mbed_official | 354:e67efb2aab0e | 4431 | |
| mbed_official | 354:e67efb2aab0e | 4432 | /** |
| mbed_official | 354:e67efb2aab0e | 4433 | * @brief TIM DMA Trigger callback. |
| mbed_official | 354:e67efb2aab0e | 4434 | * @param hdma : pointer to DMA handle. |
| mbed_official | 354:e67efb2aab0e | 4435 | * @retval None |
| mbed_official | 354:e67efb2aab0e | 4436 | */ |
| mbed_official | 354:e67efb2aab0e | 4437 | static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma) |
| mbed_official | 354:e67efb2aab0e | 4438 | { |
| mbed_official | 354:e67efb2aab0e | 4439 | TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; |
| mbed_official | 354:e67efb2aab0e | 4440 | |
| mbed_official | 354:e67efb2aab0e | 4441 | htim->State= HAL_TIM_STATE_READY; |
| mbed_official | 354:e67efb2aab0e | 4442 | |
| mbed_official | 354:e67efb2aab0e | 4443 | HAL_TIM_TriggerCallback(htim); |
| mbed_official | 354:e67efb2aab0e | 4444 | } |
| mbed_official | 354:e67efb2aab0e | 4445 | |
| mbed_official | 354:e67efb2aab0e | 4446 | /** |
| mbed_official | 354:e67efb2aab0e | 4447 | * @brief Time Base configuration |
| mbed_official | 354:e67efb2aab0e | 4448 | * @param TIMx: TIM periheral |
| mbed_official | 354:e67efb2aab0e | 4449 | * @param Structure: TIM Base configuration structure |
| mbed_official | 354:e67efb2aab0e | 4450 | * @retval None |
| mbed_official | 354:e67efb2aab0e | 4451 | */ |
| mbed_official | 354:e67efb2aab0e | 4452 | static void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) |
| mbed_official | 354:e67efb2aab0e | 4453 | { |
| mbed_official | 354:e67efb2aab0e | 4454 | uint32_t tmpcr1 = 0; |
| mbed_official | 354:e67efb2aab0e | 4455 | tmpcr1 = TIMx->CR1; |
| mbed_official | 354:e67efb2aab0e | 4456 | |
| mbed_official | 354:e67efb2aab0e | 4457 | /* Set TIM Time Base Unit parameters ---------------------------------------*/ |
| mbed_official | 354:e67efb2aab0e | 4458 | if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) |
| mbed_official | 354:e67efb2aab0e | 4459 | { |
| mbed_official | 354:e67efb2aab0e | 4460 | /* Select the Counter Mode */ |
| mbed_official | 354:e67efb2aab0e | 4461 | tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); |
| mbed_official | 354:e67efb2aab0e | 4462 | tmpcr1 |= Structure->CounterMode; |
| mbed_official | 354:e67efb2aab0e | 4463 | } |
| mbed_official | 354:e67efb2aab0e | 4464 | |
| mbed_official | 354:e67efb2aab0e | 4465 | if(IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) |
| mbed_official | 354:e67efb2aab0e | 4466 | { |
| mbed_official | 354:e67efb2aab0e | 4467 | /* Set the clock division */ |
| mbed_official | 354:e67efb2aab0e | 4468 | tmpcr1 &= ~TIM_CR1_CKD; |
| mbed_official | 354:e67efb2aab0e | 4469 | tmpcr1 |= (uint32_t)Structure->ClockDivision; |
| mbed_official | 354:e67efb2aab0e | 4470 | } |
| mbed_official | 354:e67efb2aab0e | 4471 | |
| mbed_official | 354:e67efb2aab0e | 4472 | TIMx->CR1 = tmpcr1; |
| mbed_official | 354:e67efb2aab0e | 4473 | |
| mbed_official | 354:e67efb2aab0e | 4474 | /* Set the Autoreload value */ |
| mbed_official | 354:e67efb2aab0e | 4475 | TIMx->ARR = (uint32_t)Structure->Period ; |
| mbed_official | 354:e67efb2aab0e | 4476 | |
| mbed_official | 354:e67efb2aab0e | 4477 | /* Set the Prescaler value */ |
| mbed_official | 354:e67efb2aab0e | 4478 | TIMx->PSC = (uint32_t)Structure->Prescaler; |
| mbed_official | 354:e67efb2aab0e | 4479 | |
| mbed_official | 354:e67efb2aab0e | 4480 | /* Generate an update event to reload the Prescaler |
| mbed_official | 354:e67efb2aab0e | 4481 | and the repetition counter(only for TIM1 and TIM8) value immediatly */ |
| mbed_official | 354:e67efb2aab0e | 4482 | TIMx->EGR = TIM_EGR_UG; |
| mbed_official | 354:e67efb2aab0e | 4483 | } |
| mbed_official | 354:e67efb2aab0e | 4484 | |
| mbed_official | 354:e67efb2aab0e | 4485 | /** |
| mbed_official | 354:e67efb2aab0e | 4486 | * @brief Time Ouput Compare 1 configuration |
| mbed_official | 354:e67efb2aab0e | 4487 | * @param TIMx to select the TIM peripheral |
| mbed_official | 354:e67efb2aab0e | 4488 | * @param OC_Config: The ouput configuration structure |
| mbed_official | 354:e67efb2aab0e | 4489 | * @retval None |
| mbed_official | 354:e67efb2aab0e | 4490 | */ |
| mbed_official | 354:e67efb2aab0e | 4491 | static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) |
| mbed_official | 354:e67efb2aab0e | 4492 | { |
| mbed_official | 354:e67efb2aab0e | 4493 | uint32_t tmpccmrx = 0; |
| mbed_official | 354:e67efb2aab0e | 4494 | uint32_t tmpccer = 0; |
| mbed_official | 354:e67efb2aab0e | 4495 | uint32_t tmpcr2 = 0; |
| mbed_official | 354:e67efb2aab0e | 4496 | |
| mbed_official | 354:e67efb2aab0e | 4497 | /* Disable the Channel 1: Reset the CC1E Bit */ |
| mbed_official | 354:e67efb2aab0e | 4498 | TIMx->CCER &= ~TIM_CCER_CC1E; |
| mbed_official | 354:e67efb2aab0e | 4499 | |
| mbed_official | 354:e67efb2aab0e | 4500 | /* Get the TIMx CCER register value */ |
| mbed_official | 354:e67efb2aab0e | 4501 | tmpccer = TIMx->CCER; |
| mbed_official | 354:e67efb2aab0e | 4502 | /* Get the TIMx CR2 register value */ |
| mbed_official | 354:e67efb2aab0e | 4503 | tmpcr2 = TIMx->CR2; |
| mbed_official | 354:e67efb2aab0e | 4504 | |
| mbed_official | 354:e67efb2aab0e | 4505 | /* Get the TIMx CCMR1 register value */ |
| mbed_official | 354:e67efb2aab0e | 4506 | tmpccmrx = TIMx->CCMR1; |
| mbed_official | 354:e67efb2aab0e | 4507 | |
| mbed_official | 354:e67efb2aab0e | 4508 | /* Reset the Output Compare Mode Bits */ |
| mbed_official | 354:e67efb2aab0e | 4509 | tmpccmrx &= ~TIM_CCMR1_OC1M; |
| mbed_official | 354:e67efb2aab0e | 4510 | tmpccmrx &= ~TIM_CCMR1_CC1S; |
| mbed_official | 354:e67efb2aab0e | 4511 | /* Select the Output Compare Mode */ |
| mbed_official | 354:e67efb2aab0e | 4512 | tmpccmrx |= OC_Config->OCMode; |
| mbed_official | 354:e67efb2aab0e | 4513 | |
| mbed_official | 354:e67efb2aab0e | 4514 | /* Reset the Output Polarity level */ |
| mbed_official | 354:e67efb2aab0e | 4515 | tmpccer &= ~TIM_CCER_CC1P; |
| mbed_official | 354:e67efb2aab0e | 4516 | /* Set the Output Compare Polarity */ |
| mbed_official | 354:e67efb2aab0e | 4517 | tmpccer |= OC_Config->OCPolarity; |
| mbed_official | 354:e67efb2aab0e | 4518 | |
| mbed_official | 354:e67efb2aab0e | 4519 | /* Write to TIMx CR2 */ |
| mbed_official | 354:e67efb2aab0e | 4520 | TIMx->CR2 = tmpcr2; |
| mbed_official | 354:e67efb2aab0e | 4521 | |
| mbed_official | 354:e67efb2aab0e | 4522 | /* Write to TIMx CCMR1 */ |
| mbed_official | 354:e67efb2aab0e | 4523 | TIMx->CCMR1 = tmpccmrx; |
| mbed_official | 354:e67efb2aab0e | 4524 | |
| mbed_official | 354:e67efb2aab0e | 4525 | /* Set the Capture Compare Register value */ |
| mbed_official | 354:e67efb2aab0e | 4526 | TIMx->CCR1 = OC_Config->Pulse; |
| mbed_official | 354:e67efb2aab0e | 4527 | |
| mbed_official | 354:e67efb2aab0e | 4528 | /* Write to TIMx CCER */ |
| mbed_official | 354:e67efb2aab0e | 4529 | TIMx->CCER = tmpccer; |
| mbed_official | 354:e67efb2aab0e | 4530 | } |
| mbed_official | 354:e67efb2aab0e | 4531 | |
| mbed_official | 354:e67efb2aab0e | 4532 | /** |
| mbed_official | 354:e67efb2aab0e | 4533 | * @brief Time Ouput Compare 2 configuration |
| mbed_official | 354:e67efb2aab0e | 4534 | * @param TIMx to select the TIM peripheral |
| mbed_official | 354:e67efb2aab0e | 4535 | * @param OC_Config: The ouput configuration structure |
| mbed_official | 354:e67efb2aab0e | 4536 | * @retval None |
| mbed_official | 354:e67efb2aab0e | 4537 | */ |
| mbed_official | 354:e67efb2aab0e | 4538 | static void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) |
| mbed_official | 354:e67efb2aab0e | 4539 | { |
| mbed_official | 354:e67efb2aab0e | 4540 | uint32_t tmpccmrx = 0; |
| mbed_official | 354:e67efb2aab0e | 4541 | uint32_t tmpccer = 0; |
| mbed_official | 354:e67efb2aab0e | 4542 | uint32_t tmpcr2 = 0; |
| mbed_official | 354:e67efb2aab0e | 4543 | |
| mbed_official | 354:e67efb2aab0e | 4544 | /* Disable the Channel 2: Reset the CC2E Bit */ |
| mbed_official | 354:e67efb2aab0e | 4545 | TIMx->CCER &= ~TIM_CCER_CC2E; |
| mbed_official | 354:e67efb2aab0e | 4546 | |
| mbed_official | 354:e67efb2aab0e | 4547 | /* Get the TIMx CCER register value */ |
| mbed_official | 354:e67efb2aab0e | 4548 | tmpccer = TIMx->CCER; |
| mbed_official | 354:e67efb2aab0e | 4549 | /* Get the TIMx CR2 register value */ |
| mbed_official | 354:e67efb2aab0e | 4550 | tmpcr2 = TIMx->CR2; |
| mbed_official | 354:e67efb2aab0e | 4551 | |
| mbed_official | 354:e67efb2aab0e | 4552 | /* Get the TIMx CCMR1 register value */ |
| mbed_official | 354:e67efb2aab0e | 4553 | tmpccmrx = TIMx->CCMR1; |
| mbed_official | 354:e67efb2aab0e | 4554 | |
| mbed_official | 354:e67efb2aab0e | 4555 | /* Reset the Output Compare mode and Capture/Compare selection Bits */ |
| mbed_official | 354:e67efb2aab0e | 4556 | tmpccmrx &= ~TIM_CCMR1_OC2M; |
| mbed_official | 354:e67efb2aab0e | 4557 | tmpccmrx &= ~TIM_CCMR1_CC2S; |
| mbed_official | 354:e67efb2aab0e | 4558 | |
| mbed_official | 354:e67efb2aab0e | 4559 | /* Select the Output Compare Mode */ |
| mbed_official | 354:e67efb2aab0e | 4560 | tmpccmrx |= (OC_Config->OCMode << 8); |
| mbed_official | 354:e67efb2aab0e | 4561 | |
| mbed_official | 354:e67efb2aab0e | 4562 | /* Reset the Output Polarity level */ |
| mbed_official | 354:e67efb2aab0e | 4563 | tmpccer &= ~TIM_CCER_CC2P; |
| mbed_official | 354:e67efb2aab0e | 4564 | /* Set the Output Compare Polarity */ |
| mbed_official | 354:e67efb2aab0e | 4565 | tmpccer |= (OC_Config->OCPolarity << 4); |
| mbed_official | 354:e67efb2aab0e | 4566 | |
| mbed_official | 354:e67efb2aab0e | 4567 | /* Write to TIMx CR2 */ |
| mbed_official | 354:e67efb2aab0e | 4568 | TIMx->CR2 = tmpcr2; |
| mbed_official | 354:e67efb2aab0e | 4569 | |
| mbed_official | 354:e67efb2aab0e | 4570 | /* Write to TIMx CCMR1 */ |
| mbed_official | 354:e67efb2aab0e | 4571 | TIMx->CCMR1 = tmpccmrx; |
| mbed_official | 354:e67efb2aab0e | 4572 | |
| mbed_official | 354:e67efb2aab0e | 4573 | /* Set the Capture Compare Register value */ |
| mbed_official | 354:e67efb2aab0e | 4574 | TIMx->CCR2 = OC_Config->Pulse; |
| mbed_official | 354:e67efb2aab0e | 4575 | |
| mbed_official | 354:e67efb2aab0e | 4576 | /* Write to TIMx CCER */ |
| mbed_official | 354:e67efb2aab0e | 4577 | TIMx->CCER = tmpccer; |
| mbed_official | 354:e67efb2aab0e | 4578 | } |
| mbed_official | 354:e67efb2aab0e | 4579 | |
| mbed_official | 354:e67efb2aab0e | 4580 | /** |
| mbed_official | 354:e67efb2aab0e | 4581 | * @brief Time Ouput Compare 3 configuration |
| mbed_official | 354:e67efb2aab0e | 4582 | * @param TIMx to select the TIM peripheral |
| mbed_official | 354:e67efb2aab0e | 4583 | * @param OC_Config: The ouput configuration structure |
| mbed_official | 354:e67efb2aab0e | 4584 | * @retval None |
| mbed_official | 354:e67efb2aab0e | 4585 | */ |
| mbed_official | 354:e67efb2aab0e | 4586 | static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) |
| mbed_official | 354:e67efb2aab0e | 4587 | { |
| mbed_official | 354:e67efb2aab0e | 4588 | uint32_t tmpccmrx = 0; |
| mbed_official | 354:e67efb2aab0e | 4589 | uint32_t tmpccer = 0; |
| mbed_official | 354:e67efb2aab0e | 4590 | uint32_t tmpcr2 = 0; |
| mbed_official | 354:e67efb2aab0e | 4591 | |
| mbed_official | 354:e67efb2aab0e | 4592 | /* Disable the Channel 3: Reset the CC2E Bit */ |
| mbed_official | 354:e67efb2aab0e | 4593 | TIMx->CCER &= ~TIM_CCER_CC3E; |
| mbed_official | 354:e67efb2aab0e | 4594 | |
| mbed_official | 354:e67efb2aab0e | 4595 | /* Get the TIMx CCER register value */ |
| mbed_official | 354:e67efb2aab0e | 4596 | tmpccer = TIMx->CCER; |
| mbed_official | 354:e67efb2aab0e | 4597 | /* Get the TIMx CR2 register value */ |
| mbed_official | 354:e67efb2aab0e | 4598 | tmpcr2 = TIMx->CR2; |
| mbed_official | 354:e67efb2aab0e | 4599 | |
| mbed_official | 354:e67efb2aab0e | 4600 | /* Get the TIMx CCMR2 register value */ |
| mbed_official | 354:e67efb2aab0e | 4601 | tmpccmrx = TIMx->CCMR2; |
| mbed_official | 354:e67efb2aab0e | 4602 | |
| mbed_official | 354:e67efb2aab0e | 4603 | /* Reset the Output Compare mode and Capture/Compare selection Bits */ |
| mbed_official | 354:e67efb2aab0e | 4604 | tmpccmrx &= ~TIM_CCMR2_OC3M; |
| mbed_official | 354:e67efb2aab0e | 4605 | tmpccmrx &= ~TIM_CCMR2_CC3S; |
| mbed_official | 354:e67efb2aab0e | 4606 | /* Select the Output Compare Mode */ |
| mbed_official | 354:e67efb2aab0e | 4607 | tmpccmrx |= OC_Config->OCMode; |
| mbed_official | 354:e67efb2aab0e | 4608 | |
| mbed_official | 354:e67efb2aab0e | 4609 | /* Reset the Output Polarity level */ |
| mbed_official | 354:e67efb2aab0e | 4610 | tmpccer &= ~TIM_CCER_CC3P; |
| mbed_official | 354:e67efb2aab0e | 4611 | /* Set the Output Compare Polarity */ |
| mbed_official | 354:e67efb2aab0e | 4612 | tmpccer |= (OC_Config->OCPolarity << 8); |
| mbed_official | 354:e67efb2aab0e | 4613 | |
| mbed_official | 354:e67efb2aab0e | 4614 | /* Write to TIMx CR2 */ |
| mbed_official | 354:e67efb2aab0e | 4615 | TIMx->CR2 = tmpcr2; |
| mbed_official | 354:e67efb2aab0e | 4616 | |
| mbed_official | 354:e67efb2aab0e | 4617 | /* Write to TIMx CCMR2 */ |
| mbed_official | 354:e67efb2aab0e | 4618 | TIMx->CCMR2 = tmpccmrx; |
| mbed_official | 354:e67efb2aab0e | 4619 | |
| mbed_official | 354:e67efb2aab0e | 4620 | /* Set the Capture Compare Register value */ |
| mbed_official | 354:e67efb2aab0e | 4621 | TIMx->CCR3 = OC_Config->Pulse; |
| mbed_official | 354:e67efb2aab0e | 4622 | |
| mbed_official | 354:e67efb2aab0e | 4623 | /* Write to TIMx CCER */ |
| mbed_official | 354:e67efb2aab0e | 4624 | TIMx->CCER = tmpccer; |
| mbed_official | 354:e67efb2aab0e | 4625 | } |
| mbed_official | 354:e67efb2aab0e | 4626 | |
| mbed_official | 354:e67efb2aab0e | 4627 | /** |
| mbed_official | 354:e67efb2aab0e | 4628 | * @brief Time Ouput Compare 4 configuration |
| mbed_official | 354:e67efb2aab0e | 4629 | * @param TIMx to select the TIM peripheral |
| mbed_official | 354:e67efb2aab0e | 4630 | * @param OC_Config: The ouput configuration structure |
| mbed_official | 354:e67efb2aab0e | 4631 | * @retval None |
| mbed_official | 354:e67efb2aab0e | 4632 | */ |
| mbed_official | 354:e67efb2aab0e | 4633 | static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) |
| mbed_official | 354:e67efb2aab0e | 4634 | { |
| mbed_official | 354:e67efb2aab0e | 4635 | uint32_t tmpccmrx = 0; |
| mbed_official | 354:e67efb2aab0e | 4636 | uint32_t tmpccer = 0; |
| mbed_official | 354:e67efb2aab0e | 4637 | uint32_t tmpcr2 = 0; |
| mbed_official | 354:e67efb2aab0e | 4638 | |
| mbed_official | 354:e67efb2aab0e | 4639 | /* Disable the Channel 4: Reset the CC4E Bit */ |
| mbed_official | 354:e67efb2aab0e | 4640 | TIMx->CCER &= ~TIM_CCER_CC4E; |
| mbed_official | 354:e67efb2aab0e | 4641 | |
| mbed_official | 354:e67efb2aab0e | 4642 | /* Get the TIMx CCER register value */ |
| mbed_official | 354:e67efb2aab0e | 4643 | tmpccer = TIMx->CCER; |
| mbed_official | 354:e67efb2aab0e | 4644 | /* Get the TIMx CR2 register value */ |
| mbed_official | 354:e67efb2aab0e | 4645 | tmpcr2 = TIMx->CR2; |
| mbed_official | 354:e67efb2aab0e | 4646 | |
| mbed_official | 354:e67efb2aab0e | 4647 | /* Get the TIMx CCMR2 register value */ |
| mbed_official | 354:e67efb2aab0e | 4648 | tmpccmrx = TIMx->CCMR2; |
| mbed_official | 354:e67efb2aab0e | 4649 | |
| mbed_official | 354:e67efb2aab0e | 4650 | /* Reset the Output Compare mode and Capture/Compare selection Bits */ |
| mbed_official | 354:e67efb2aab0e | 4651 | tmpccmrx &= ~TIM_CCMR2_OC4M; |
| mbed_official | 354:e67efb2aab0e | 4652 | tmpccmrx &= ~TIM_CCMR2_CC4S; |
| mbed_official | 354:e67efb2aab0e | 4653 | |
| mbed_official | 354:e67efb2aab0e | 4654 | /* Select the Output Compare Mode */ |
| mbed_official | 354:e67efb2aab0e | 4655 | tmpccmrx |= (OC_Config->OCMode << 8); |
| mbed_official | 354:e67efb2aab0e | 4656 | |
| mbed_official | 354:e67efb2aab0e | 4657 | /* Reset the Output Polarity level */ |
| mbed_official | 354:e67efb2aab0e | 4658 | tmpccer &= ~TIM_CCER_CC4P; |
| mbed_official | 354:e67efb2aab0e | 4659 | /* Set the Output Compare Polarity */ |
| mbed_official | 354:e67efb2aab0e | 4660 | tmpccer |= (OC_Config->OCPolarity << 12); |
| mbed_official | 354:e67efb2aab0e | 4661 | |
| mbed_official | 354:e67efb2aab0e | 4662 | /* Write to TIMx CR2 */ |
| mbed_official | 354:e67efb2aab0e | 4663 | TIMx->CR2 = tmpcr2; |
| mbed_official | 354:e67efb2aab0e | 4664 | |
| mbed_official | 354:e67efb2aab0e | 4665 | /* Write to TIMx CCMR2 */ |
| mbed_official | 354:e67efb2aab0e | 4666 | TIMx->CCMR2 = tmpccmrx; |
| mbed_official | 354:e67efb2aab0e | 4667 | |
| mbed_official | 354:e67efb2aab0e | 4668 | /* Set the Capture Compare Register value */ |
| mbed_official | 354:e67efb2aab0e | 4669 | TIMx->CCR4 = OC_Config->Pulse; |
| mbed_official | 354:e67efb2aab0e | 4670 | |
| mbed_official | 354:e67efb2aab0e | 4671 | /* Write to TIMx CCER */ |
| mbed_official | 354:e67efb2aab0e | 4672 | TIMx->CCER = tmpccer; |
| mbed_official | 354:e67efb2aab0e | 4673 | } |
| mbed_official | 354:e67efb2aab0e | 4674 | |
| mbed_official | 354:e67efb2aab0e | 4675 | /** |
| mbed_official | 354:e67efb2aab0e | 4676 | * @brief Configure the TI1 as Input. |
| mbed_official | 354:e67efb2aab0e | 4677 | * @param TIMx to select the TIM peripheral. |
| mbed_official | 354:e67efb2aab0e | 4678 | * @param TIM_ICPolarity : The Input Polarity. |
| mbed_official | 354:e67efb2aab0e | 4679 | * This parameter can be one of the following values: |
| mbed_official | 354:e67efb2aab0e | 4680 | * @arg TIM_ICPOLARITY_RISING |
| mbed_official | 354:e67efb2aab0e | 4681 | * @arg TIM_ICPOLARITY_FALLING |
| mbed_official | 354:e67efb2aab0e | 4682 | * @arg TIM_ICPOLARITY_BOTHEDGE |
| mbed_official | 354:e67efb2aab0e | 4683 | * @param TIM_ICSelection: specifies the input to be used. |
| mbed_official | 354:e67efb2aab0e | 4684 | * This parameter can be one of the following values: |
| mbed_official | 354:e67efb2aab0e | 4685 | * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1. |
| mbed_official | 354:e67efb2aab0e | 4686 | * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2. |
| mbed_official | 354:e67efb2aab0e | 4687 | * @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC. |
| mbed_official | 354:e67efb2aab0e | 4688 | * @param TIM_ICFilter: Specifies the Input Capture Filter. |
| mbed_official | 354:e67efb2aab0e | 4689 | * This parameter must be a value between 0x00 and 0x0F. |
| mbed_official | 354:e67efb2aab0e | 4690 | * @retval None |
| mbed_official | 354:e67efb2aab0e | 4691 | */ |
| mbed_official | 354:e67efb2aab0e | 4692 | static void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, |
| mbed_official | 354:e67efb2aab0e | 4693 | uint32_t TIM_ICFilter) |
| mbed_official | 354:e67efb2aab0e | 4694 | { |
| mbed_official | 354:e67efb2aab0e | 4695 | uint32_t tmpccmr1 = 0; |
| mbed_official | 354:e67efb2aab0e | 4696 | uint32_t tmpccer = 0; |
| mbed_official | 354:e67efb2aab0e | 4697 | |
| mbed_official | 354:e67efb2aab0e | 4698 | /* Disable the Channel 1: Reset the CC1E Bit */ |
| mbed_official | 354:e67efb2aab0e | 4699 | TIMx->CCER &= ~TIM_CCER_CC1E; |
| mbed_official | 354:e67efb2aab0e | 4700 | tmpccmr1 = TIMx->CCMR1; |
| mbed_official | 354:e67efb2aab0e | 4701 | tmpccer = TIMx->CCER; |
| mbed_official | 354:e67efb2aab0e | 4702 | |
| mbed_official | 354:e67efb2aab0e | 4703 | /* Select the Input */ |
| mbed_official | 354:e67efb2aab0e | 4704 | if(IS_TIM_CC2_INSTANCE(TIMx) != RESET) |
| mbed_official | 354:e67efb2aab0e | 4705 | { |
| mbed_official | 354:e67efb2aab0e | 4706 | tmpccmr1 &= ~TIM_CCMR1_CC1S; |
| mbed_official | 354:e67efb2aab0e | 4707 | tmpccmr1 |= TIM_ICSelection; |
| mbed_official | 354:e67efb2aab0e | 4708 | } |
| mbed_official | 354:e67efb2aab0e | 4709 | else |
| mbed_official | 354:e67efb2aab0e | 4710 | { |
| mbed_official | 354:e67efb2aab0e | 4711 | tmpccmr1 |= TIM_CCMR1_CC1S_0; |
| mbed_official | 354:e67efb2aab0e | 4712 | } |
| mbed_official | 354:e67efb2aab0e | 4713 | |
| mbed_official | 354:e67efb2aab0e | 4714 | /* Set the filter */ |
| mbed_official | 354:e67efb2aab0e | 4715 | tmpccmr1 &= ~TIM_CCMR1_IC1F; |
| mbed_official | 354:e67efb2aab0e | 4716 | tmpccmr1 |= (TIM_ICFilter << 4); |
| mbed_official | 354:e67efb2aab0e | 4717 | |
| mbed_official | 354:e67efb2aab0e | 4718 | /* Select the Polarity and set the CC1E Bit */ |
| mbed_official | 354:e67efb2aab0e | 4719 | tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); |
| mbed_official | 354:e67efb2aab0e | 4720 | tmpccer |= TIM_ICPolarity; |
| mbed_official | 354:e67efb2aab0e | 4721 | |
| mbed_official | 354:e67efb2aab0e | 4722 | /* Write to TIMx CCMR1 and CCER registers */ |
| mbed_official | 354:e67efb2aab0e | 4723 | TIMx->CCMR1 = tmpccmr1; |
| mbed_official | 354:e67efb2aab0e | 4724 | TIMx->CCER = tmpccer; |
| mbed_official | 354:e67efb2aab0e | 4725 | } |
| mbed_official | 354:e67efb2aab0e | 4726 | |
| mbed_official | 354:e67efb2aab0e | 4727 | /** |
| mbed_official | 354:e67efb2aab0e | 4728 | * @brief Configure the Polarity and Filter for TI1. |
| mbed_official | 354:e67efb2aab0e | 4729 | * @param TIMx to select the TIM peripheral. |
| mbed_official | 354:e67efb2aab0e | 4730 | * @param TIM_ICPolarity : The Input Polarity. |
| mbed_official | 354:e67efb2aab0e | 4731 | * This parameter can be one of the following values: |
| mbed_official | 354:e67efb2aab0e | 4732 | * @arg TIM_ICPOLARITY_RISING |
| mbed_official | 354:e67efb2aab0e | 4733 | * @arg TIM_ICPOLARITY_FALLING |
| mbed_official | 354:e67efb2aab0e | 4734 | * @arg TIM_ICPOLARITY_BOTHEDGE |
| mbed_official | 354:e67efb2aab0e | 4735 | * @param TIM_ICFilter: Specifies the Input Capture Filter. |
| mbed_official | 354:e67efb2aab0e | 4736 | * This parameter must be a value between 0x00 and 0x0F. |
| mbed_official | 354:e67efb2aab0e | 4737 | * @retval None |
| mbed_official | 354:e67efb2aab0e | 4738 | */ |
| mbed_official | 354:e67efb2aab0e | 4739 | static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) |
| mbed_official | 354:e67efb2aab0e | 4740 | { |
| mbed_official | 354:e67efb2aab0e | 4741 | uint32_t tmpccmr1 = 0; |
| mbed_official | 354:e67efb2aab0e | 4742 | uint32_t tmpccer = 0; |
| mbed_official | 354:e67efb2aab0e | 4743 | |
| mbed_official | 354:e67efb2aab0e | 4744 | /* Disable the Channel 1: Reset the CC1E Bit */ |
| mbed_official | 354:e67efb2aab0e | 4745 | tmpccer = TIMx->CCER; |
| mbed_official | 354:e67efb2aab0e | 4746 | TIMx->CCER &= ~TIM_CCER_CC1E; |
| mbed_official | 354:e67efb2aab0e | 4747 | tmpccmr1 = TIMx->CCMR1; |
| mbed_official | 354:e67efb2aab0e | 4748 | |
| mbed_official | 354:e67efb2aab0e | 4749 | /* Set the filter */ |
| mbed_official | 354:e67efb2aab0e | 4750 | tmpccmr1 &= ~TIM_CCMR1_IC1F; |
| mbed_official | 354:e67efb2aab0e | 4751 | tmpccmr1 |= (TIM_ICFilter << 4); |
| mbed_official | 354:e67efb2aab0e | 4752 | |
| mbed_official | 354:e67efb2aab0e | 4753 | /* Select the Polarity and set the CC1E Bit */ |
| mbed_official | 354:e67efb2aab0e | 4754 | tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); |
| mbed_official | 354:e67efb2aab0e | 4755 | tmpccer |= TIM_ICPolarity; |
| mbed_official | 354:e67efb2aab0e | 4756 | |
| mbed_official | 354:e67efb2aab0e | 4757 | /* Write to TIMx CCMR1 and CCER registers */ |
| mbed_official | 354:e67efb2aab0e | 4758 | TIMx->CCMR1 = tmpccmr1; |
| mbed_official | 354:e67efb2aab0e | 4759 | TIMx->CCER = tmpccer; |
| mbed_official | 354:e67efb2aab0e | 4760 | } |
| mbed_official | 354:e67efb2aab0e | 4761 | |
| mbed_official | 354:e67efb2aab0e | 4762 | /** |
| mbed_official | 354:e67efb2aab0e | 4763 | * @brief Configure the TI2 as Input. |
| mbed_official | 354:e67efb2aab0e | 4764 | * @param TIMx to select the TIM peripheral |
| mbed_official | 354:e67efb2aab0e | 4765 | * @param TIM_ICPolarity : The Input Polarity. |
| mbed_official | 354:e67efb2aab0e | 4766 | * This parameter can be one of the following values: |
| mbed_official | 354:e67efb2aab0e | 4767 | * @arg TIM_ICPOLARITY_RISING |
| mbed_official | 354:e67efb2aab0e | 4768 | * @arg TIM_ICPOLARITY_FALLING |
| mbed_official | 354:e67efb2aab0e | 4769 | * @arg TIM_ICPOLARITY_BOTHEDGE |
| mbed_official | 354:e67efb2aab0e | 4770 | * @param TIM_ICSelection: specifies the input to be used. |
| mbed_official | 354:e67efb2aab0e | 4771 | * This parameter can be one of the following values: |
| mbed_official | 354:e67efb2aab0e | 4772 | * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2. |
| mbed_official | 354:e67efb2aab0e | 4773 | * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1. |
| mbed_official | 354:e67efb2aab0e | 4774 | * @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC. |
| mbed_official | 354:e67efb2aab0e | 4775 | * @param TIM_ICFilter: Specifies the Input Capture Filter. |
| mbed_official | 354:e67efb2aab0e | 4776 | * This parameter must be a value between 0x00 and 0x0F. |
| mbed_official | 354:e67efb2aab0e | 4777 | * @retval None |
| mbed_official | 354:e67efb2aab0e | 4778 | */ |
| mbed_official | 354:e67efb2aab0e | 4779 | static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, |
| mbed_official | 354:e67efb2aab0e | 4780 | uint32_t TIM_ICFilter) |
| mbed_official | 354:e67efb2aab0e | 4781 | { |
| mbed_official | 354:e67efb2aab0e | 4782 | uint32_t tmpccmr1 = 0; |
| mbed_official | 354:e67efb2aab0e | 4783 | uint32_t tmpccer = 0; |
| mbed_official | 354:e67efb2aab0e | 4784 | |
| mbed_official | 354:e67efb2aab0e | 4785 | /* Disable the Channel 2: Reset the CC2E Bit */ |
| mbed_official | 354:e67efb2aab0e | 4786 | TIMx->CCER &= ~TIM_CCER_CC2E; |
| mbed_official | 354:e67efb2aab0e | 4787 | tmpccmr1 = TIMx->CCMR1; |
| mbed_official | 354:e67efb2aab0e | 4788 | tmpccer = TIMx->CCER; |
| mbed_official | 354:e67efb2aab0e | 4789 | |
| mbed_official | 354:e67efb2aab0e | 4790 | /* Select the Input */ |
| mbed_official | 354:e67efb2aab0e | 4791 | tmpccmr1 &= ~TIM_CCMR1_CC2S; |
| mbed_official | 354:e67efb2aab0e | 4792 | tmpccmr1 |= (TIM_ICSelection << 8); |
| mbed_official | 354:e67efb2aab0e | 4793 | |
| mbed_official | 354:e67efb2aab0e | 4794 | /* Set the filter */ |
| mbed_official | 354:e67efb2aab0e | 4795 | tmpccmr1 &= ~TIM_CCMR1_IC2F; |
| mbed_official | 354:e67efb2aab0e | 4796 | tmpccmr1 |= (TIM_ICFilter << 12); |
| mbed_official | 354:e67efb2aab0e | 4797 | |
| mbed_official | 354:e67efb2aab0e | 4798 | /* Select the Polarity and set the CC2E Bit */ |
| mbed_official | 354:e67efb2aab0e | 4799 | tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); |
| mbed_official | 354:e67efb2aab0e | 4800 | tmpccer |= (TIM_ICPolarity << 4); |
| mbed_official | 354:e67efb2aab0e | 4801 | |
| mbed_official | 354:e67efb2aab0e | 4802 | /* Write to TIMx CCMR1 and CCER registers */ |
| mbed_official | 354:e67efb2aab0e | 4803 | TIMx->CCMR1 = tmpccmr1 ; |
| mbed_official | 354:e67efb2aab0e | 4804 | TIMx->CCER = tmpccer; |
| mbed_official | 354:e67efb2aab0e | 4805 | } |
| mbed_official | 354:e67efb2aab0e | 4806 | |
| mbed_official | 354:e67efb2aab0e | 4807 | /** |
| mbed_official | 354:e67efb2aab0e | 4808 | * @brief Configure the Polarity and Filter for TI2. |
| mbed_official | 354:e67efb2aab0e | 4809 | * @param TIMx to select the TIM peripheral. |
| mbed_official | 354:e67efb2aab0e | 4810 | * @param TIM_ICPolarity : The Input Polarity. |
| mbed_official | 354:e67efb2aab0e | 4811 | * This parameter can be one of the following values: |
| mbed_official | 354:e67efb2aab0e | 4812 | * @arg TIM_ICPOLARITY_RISING |
| mbed_official | 354:e67efb2aab0e | 4813 | * @arg TIM_ICPOLARITY_FALLING |
| mbed_official | 354:e67efb2aab0e | 4814 | * @arg TIM_ICPOLARITY_BOTHEDGE |
| mbed_official | 354:e67efb2aab0e | 4815 | * @param TIM_ICFilter: Specifies the Input Capture Filter. |
| mbed_official | 354:e67efb2aab0e | 4816 | * This parameter must be a value between 0x00 and 0x0F. |
| mbed_official | 354:e67efb2aab0e | 4817 | * @retval None |
| mbed_official | 354:e67efb2aab0e | 4818 | */ |
| mbed_official | 354:e67efb2aab0e | 4819 | static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) |
| mbed_official | 354:e67efb2aab0e | 4820 | { |
| mbed_official | 354:e67efb2aab0e | 4821 | uint32_t tmpccmr1 = 0; |
| mbed_official | 354:e67efb2aab0e | 4822 | uint32_t tmpccer = 0; |
| mbed_official | 354:e67efb2aab0e | 4823 | |
| mbed_official | 354:e67efb2aab0e | 4824 | /* Disable the Channel 2: Reset the CC2E Bit */ |
| mbed_official | 354:e67efb2aab0e | 4825 | TIMx->CCER &= ~TIM_CCER_CC2E; |
| mbed_official | 354:e67efb2aab0e | 4826 | tmpccmr1 = TIMx->CCMR1; |
| mbed_official | 354:e67efb2aab0e | 4827 | tmpccer = TIMx->CCER; |
| mbed_official | 354:e67efb2aab0e | 4828 | |
| mbed_official | 354:e67efb2aab0e | 4829 | /* Set the filter */ |
| mbed_official | 354:e67efb2aab0e | 4830 | tmpccmr1 &= ~TIM_CCMR1_IC2F; |
| mbed_official | 354:e67efb2aab0e | 4831 | tmpccmr1 |= (TIM_ICFilter << 12); |
| mbed_official | 354:e67efb2aab0e | 4832 | |
| mbed_official | 354:e67efb2aab0e | 4833 | /* Select the Polarity and set the CC2E Bit */ |
| mbed_official | 354:e67efb2aab0e | 4834 | tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); |
| mbed_official | 354:e67efb2aab0e | 4835 | tmpccer |= (TIM_ICPolarity << 4); |
| mbed_official | 354:e67efb2aab0e | 4836 | |
| mbed_official | 354:e67efb2aab0e | 4837 | /* Write to TIMx CCMR1 and CCER registers */ |
| mbed_official | 354:e67efb2aab0e | 4838 | TIMx->CCMR1 = tmpccmr1 ; |
| mbed_official | 354:e67efb2aab0e | 4839 | TIMx->CCER = tmpccer; |
| mbed_official | 354:e67efb2aab0e | 4840 | } |
| mbed_official | 354:e67efb2aab0e | 4841 | |
| mbed_official | 354:e67efb2aab0e | 4842 | /** |
| mbed_official | 354:e67efb2aab0e | 4843 | * @brief Configure the TI3 as Input. |
| mbed_official | 354:e67efb2aab0e | 4844 | * @param TIMx to select the TIM peripheral |
| mbed_official | 354:e67efb2aab0e | 4845 | * @param TIM_ICPolarity : The Input Polarity. |
| mbed_official | 354:e67efb2aab0e | 4846 | * This parameter can be one of the following values: |
| mbed_official | 354:e67efb2aab0e | 4847 | * @arg TIM_ICPOLARITY_RISING |
| mbed_official | 354:e67efb2aab0e | 4848 | * @arg TIM_ICPOLARITY_FALLING |
| mbed_official | 354:e67efb2aab0e | 4849 | * @arg TIM_ICPOLARITY_BOTHEDGE |
| mbed_official | 354:e67efb2aab0e | 4850 | * @param TIM_ICSelection: specifies the input to be used. |
| mbed_official | 354:e67efb2aab0e | 4851 | * This parameter can be one of the following values: |
| mbed_official | 354:e67efb2aab0e | 4852 | * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3. |
| mbed_official | 354:e67efb2aab0e | 4853 | * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4. |
| mbed_official | 354:e67efb2aab0e | 4854 | * @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC. |
| mbed_official | 354:e67efb2aab0e | 4855 | * @param TIM_ICFilter: Specifies the Input Capture Filter. |
| mbed_official | 354:e67efb2aab0e | 4856 | * This parameter must be a value between 0x00 and 0x0F. |
| mbed_official | 354:e67efb2aab0e | 4857 | * @retval None |
| mbed_official | 354:e67efb2aab0e | 4858 | */ |
| mbed_official | 354:e67efb2aab0e | 4859 | static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, |
| mbed_official | 354:e67efb2aab0e | 4860 | uint32_t TIM_ICFilter) |
| mbed_official | 354:e67efb2aab0e | 4861 | { |
| mbed_official | 354:e67efb2aab0e | 4862 | uint32_t tmpccmr2 = 0; |
| mbed_official | 354:e67efb2aab0e | 4863 | uint32_t tmpccer = 0; |
| mbed_official | 354:e67efb2aab0e | 4864 | |
| mbed_official | 354:e67efb2aab0e | 4865 | /* Disable the Channel 3: Reset the CC3E Bit */ |
| mbed_official | 354:e67efb2aab0e | 4866 | TIMx->CCER &= ~TIM_CCER_CC3E; |
| mbed_official | 354:e67efb2aab0e | 4867 | tmpccmr2 = TIMx->CCMR2; |
| mbed_official | 354:e67efb2aab0e | 4868 | tmpccer = TIMx->CCER; |
| mbed_official | 354:e67efb2aab0e | 4869 | |
| mbed_official | 354:e67efb2aab0e | 4870 | /* Select the Input */ |
| mbed_official | 354:e67efb2aab0e | 4871 | tmpccmr2 &= ~TIM_CCMR2_CC3S; |
| mbed_official | 354:e67efb2aab0e | 4872 | tmpccmr2 |= TIM_ICSelection; |
| mbed_official | 354:e67efb2aab0e | 4873 | |
| mbed_official | 354:e67efb2aab0e | 4874 | /* Set the filter */ |
| mbed_official | 354:e67efb2aab0e | 4875 | tmpccmr2 &= ~TIM_CCMR2_IC3F; |
| mbed_official | 354:e67efb2aab0e | 4876 | tmpccmr2 |= (TIM_ICFilter << 4); |
| mbed_official | 354:e67efb2aab0e | 4877 | |
| mbed_official | 354:e67efb2aab0e | 4878 | /* Select the Polarity and set the CC3E Bit */ |
| mbed_official | 354:e67efb2aab0e | 4879 | tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP); |
| mbed_official | 354:e67efb2aab0e | 4880 | tmpccer |= (TIM_ICPolarity << 8); |
| mbed_official | 354:e67efb2aab0e | 4881 | |
| mbed_official | 354:e67efb2aab0e | 4882 | /* Write to TIMx CCMR2 and CCER registers */ |
| mbed_official | 354:e67efb2aab0e | 4883 | TIMx->CCMR2 = tmpccmr2; |
| mbed_official | 354:e67efb2aab0e | 4884 | TIMx->CCER = tmpccer; |
| mbed_official | 354:e67efb2aab0e | 4885 | } |
| mbed_official | 354:e67efb2aab0e | 4886 | |
| mbed_official | 354:e67efb2aab0e | 4887 | /** |
| mbed_official | 354:e67efb2aab0e | 4888 | * @brief Configure the TI4 as Input. |
| mbed_official | 354:e67efb2aab0e | 4889 | * @param TIMx to select the TIM peripheral |
| mbed_official | 354:e67efb2aab0e | 4890 | * @param TIM_ICPolarity : The Input Polarity. |
| mbed_official | 354:e67efb2aab0e | 4891 | * This parameter can be one of the following values: |
| mbed_official | 354:e67efb2aab0e | 4892 | * @arg TIM_ICPOLARITY_RISING |
| mbed_official | 354:e67efb2aab0e | 4893 | * @arg TIM_ICPOLARITY_FALLING |
| mbed_official | 354:e67efb2aab0e | 4894 | * @arg TIM_ICPOLARITY_BOTHEDGE |
| mbed_official | 354:e67efb2aab0e | 4895 | * @param TIM_ICSelection: specifies the input to be used. |
| mbed_official | 354:e67efb2aab0e | 4896 | * This parameter can be one of the following values: |
| mbed_official | 354:e67efb2aab0e | 4897 | * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4. |
| mbed_official | 354:e67efb2aab0e | 4898 | * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3. |
| mbed_official | 354:e67efb2aab0e | 4899 | * @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC. |
| mbed_official | 354:e67efb2aab0e | 4900 | * @param TIM_ICFilter: Specifies the Input Capture Filter. |
| mbed_official | 354:e67efb2aab0e | 4901 | * This parameter must be a value between 0x00 and 0x0F. |
| mbed_official | 354:e67efb2aab0e | 4902 | * @retval None |
| mbed_official | 354:e67efb2aab0e | 4903 | */ |
| mbed_official | 354:e67efb2aab0e | 4904 | static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, |
| mbed_official | 354:e67efb2aab0e | 4905 | uint32_t TIM_ICFilter) |
| mbed_official | 354:e67efb2aab0e | 4906 | { |
| mbed_official | 354:e67efb2aab0e | 4907 | uint32_t tmpccmr2 = 0; |
| mbed_official | 354:e67efb2aab0e | 4908 | uint32_t tmpccer = 0; |
| mbed_official | 354:e67efb2aab0e | 4909 | |
| mbed_official | 354:e67efb2aab0e | 4910 | /* Disable the Channel 4: Reset the CC4E Bit */ |
| mbed_official | 354:e67efb2aab0e | 4911 | TIMx->CCER &= ~TIM_CCER_CC4E; |
| mbed_official | 354:e67efb2aab0e | 4912 | tmpccmr2 = TIMx->CCMR2; |
| mbed_official | 354:e67efb2aab0e | 4913 | tmpccer = TIMx->CCER; |
| mbed_official | 354:e67efb2aab0e | 4914 | |
| mbed_official | 354:e67efb2aab0e | 4915 | /* Select the Input */ |
| mbed_official | 354:e67efb2aab0e | 4916 | tmpccmr2 &= ~TIM_CCMR2_CC4S; |
| mbed_official | 354:e67efb2aab0e | 4917 | tmpccmr2 |= (TIM_ICSelection << 8); |
| mbed_official | 354:e67efb2aab0e | 4918 | |
| mbed_official | 354:e67efb2aab0e | 4919 | /* Set the filter */ |
| mbed_official | 354:e67efb2aab0e | 4920 | tmpccmr2 &= ~TIM_CCMR2_IC4F; |
| mbed_official | 354:e67efb2aab0e | 4921 | tmpccmr2 |= (TIM_ICFilter << 12); |
| mbed_official | 354:e67efb2aab0e | 4922 | |
| mbed_official | 354:e67efb2aab0e | 4923 | /* Select the Polarity and set the CC4E Bit */ |
| mbed_official | 354:e67efb2aab0e | 4924 | tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP); |
| mbed_official | 354:e67efb2aab0e | 4925 | tmpccer |= (TIM_ICPolarity << 12); |
| mbed_official | 354:e67efb2aab0e | 4926 | |
| mbed_official | 354:e67efb2aab0e | 4927 | /* Write to TIMx CCMR2 and CCER registers */ |
| mbed_official | 354:e67efb2aab0e | 4928 | TIMx->CCMR2 = tmpccmr2; |
| mbed_official | 354:e67efb2aab0e | 4929 | TIMx->CCER = tmpccer ; |
| mbed_official | 354:e67efb2aab0e | 4930 | } |
| mbed_official | 354:e67efb2aab0e | 4931 | |
| mbed_official | 354:e67efb2aab0e | 4932 | /** |
| mbed_official | 354:e67efb2aab0e | 4933 | * @brief Selects the Input Trigger source |
| mbed_official | 354:e67efb2aab0e | 4934 | * @param TIMx to select the TIM peripheral |
| mbed_official | 354:e67efb2aab0e | 4935 | * @param InputTriggerSource: The Input Trigger source. |
| mbed_official | 354:e67efb2aab0e | 4936 | * This parameter can be one of the following values: |
| mbed_official | 354:e67efb2aab0e | 4937 | * @arg TIM_TS_ITR0: Internal Trigger 0 |
| mbed_official | 354:e67efb2aab0e | 4938 | * @arg TIM_TS_ITR1: Internal Trigger 1 |
| mbed_official | 354:e67efb2aab0e | 4939 | * @arg TIM_TS_ITR2: Internal Trigger 2 |
| mbed_official | 354:e67efb2aab0e | 4940 | * @arg TIM_TS_ITR3: Internal Trigger 3 |
| mbed_official | 354:e67efb2aab0e | 4941 | * @arg TIM_TS_TI1F_ED: TI1 Edge Detector |
| mbed_official | 354:e67efb2aab0e | 4942 | * @arg TIM_TS_TI1FP1: Filtered Timer Input 1 |
| mbed_official | 354:e67efb2aab0e | 4943 | * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 |
| mbed_official | 354:e67efb2aab0e | 4944 | * @arg TIM_TS_ETRF: External Trigger input |
| mbed_official | 354:e67efb2aab0e | 4945 | * @retval None |
| mbed_official | 354:e67efb2aab0e | 4946 | */ |
| mbed_official | 354:e67efb2aab0e | 4947 | static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t InputTriggerSource) |
| mbed_official | 354:e67efb2aab0e | 4948 | { |
| mbed_official | 354:e67efb2aab0e | 4949 | uint32_t tmpsmcr = 0; |
| mbed_official | 354:e67efb2aab0e | 4950 | |
| mbed_official | 354:e67efb2aab0e | 4951 | /* Get the TIMx SMCR register value */ |
| mbed_official | 354:e67efb2aab0e | 4952 | tmpsmcr = TIMx->SMCR; |
| mbed_official | 354:e67efb2aab0e | 4953 | /* Reset the TS Bits */ |
| mbed_official | 354:e67efb2aab0e | 4954 | tmpsmcr &= ~TIM_SMCR_TS; |
| mbed_official | 354:e67efb2aab0e | 4955 | /* Set the Input Trigger source and the slave mode*/ |
| mbed_official | 354:e67efb2aab0e | 4956 | tmpsmcr |= InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1; |
| mbed_official | 354:e67efb2aab0e | 4957 | /* Write to TIMx SMCR */ |
| mbed_official | 354:e67efb2aab0e | 4958 | TIMx->SMCR = tmpsmcr; |
| mbed_official | 354:e67efb2aab0e | 4959 | } |
| mbed_official | 354:e67efb2aab0e | 4960 | /** |
| mbed_official | 354:e67efb2aab0e | 4961 | * @brief Configures the TIMx External Trigger (ETR). |
| mbed_official | 354:e67efb2aab0e | 4962 | * @param TIMx to select the TIM peripheral |
| mbed_official | 354:e67efb2aab0e | 4963 | * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. |
| mbed_official | 354:e67efb2aab0e | 4964 | * This parameter can be one of the following values: |
| mbed_official | 354:e67efb2aab0e | 4965 | * @arg TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF. |
| mbed_official | 354:e67efb2aab0e | 4966 | * @arg TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2. |
| mbed_official | 354:e67efb2aab0e | 4967 | * @arg TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4. |
| mbed_official | 354:e67efb2aab0e | 4968 | * @arg TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8. |
| mbed_official | 354:e67efb2aab0e | 4969 | * @param TIM_ExtTRGPolarity: The external Trigger Polarity. |
| mbed_official | 354:e67efb2aab0e | 4970 | * This parameter can be one of the following values: |
| mbed_official | 354:e67efb2aab0e | 4971 | * @arg TIM_ETRPOLARITY_INVERTED: active low or falling edge active. |
| mbed_official | 354:e67efb2aab0e | 4972 | * @arg TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active. |
| mbed_official | 354:e67efb2aab0e | 4973 | * @param ExtTRGFilter: External Trigger Filter. |
| mbed_official | 354:e67efb2aab0e | 4974 | * This parameter must be a value between 0x00 and 0x0F |
| mbed_official | 354:e67efb2aab0e | 4975 | * @retval None |
| mbed_official | 354:e67efb2aab0e | 4976 | */ |
| mbed_official | 354:e67efb2aab0e | 4977 | static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler, |
| mbed_official | 354:e67efb2aab0e | 4978 | uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter) |
| mbed_official | 354:e67efb2aab0e | 4979 | { |
| mbed_official | 354:e67efb2aab0e | 4980 | uint32_t tmpsmcr = 0; |
| mbed_official | 354:e67efb2aab0e | 4981 | |
| mbed_official | 354:e67efb2aab0e | 4982 | tmpsmcr = TIMx->SMCR; |
| mbed_official | 354:e67efb2aab0e | 4983 | |
| mbed_official | 354:e67efb2aab0e | 4984 | /* Reset the ETR Bits */ |
| mbed_official | 354:e67efb2aab0e | 4985 | tmpsmcr &= (uint32_t)(~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP)); |
| mbed_official | 354:e67efb2aab0e | 4986 | |
| mbed_official | 354:e67efb2aab0e | 4987 | /* Set the Prescaler, the Filter value and the Polarity */ |
| mbed_official | 354:e67efb2aab0e | 4988 | tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8))); |
| mbed_official | 354:e67efb2aab0e | 4989 | |
| mbed_official | 354:e67efb2aab0e | 4990 | /* Write to TIMx SMCR */ |
| mbed_official | 354:e67efb2aab0e | 4991 | TIMx->SMCR = tmpsmcr; |
| mbed_official | 354:e67efb2aab0e | 4992 | } |
| mbed_official | 354:e67efb2aab0e | 4993 | |
| mbed_official | 354:e67efb2aab0e | 4994 | /** |
| mbed_official | 354:e67efb2aab0e | 4995 | * @brief Enables or disables the TIM Capture Compare Channel x. |
| mbed_official | 354:e67efb2aab0e | 4996 | * @param TIMx to select the TIM peripheral |
| mbed_official | 354:e67efb2aab0e | 4997 | * @param Channel: specifies the TIM Channel |
| mbed_official | 354:e67efb2aab0e | 4998 | * This parameter can be one of the following values: |
| mbed_official | 354:e67efb2aab0e | 4999 | * @arg TIM_CHANNEL_1: TIM Channel 1 |
| mbed_official | 354:e67efb2aab0e | 5000 | * @arg TIM_CHANNEL_2: TIM Channel 2 |
| mbed_official | 354:e67efb2aab0e | 5001 | * @arg TIM_CHANNEL_3: TIM Channel 3 |
| mbed_official | 354:e67efb2aab0e | 5002 | * @arg TIM_CHANNEL_4: TIM Channel 4 |
| mbed_official | 354:e67efb2aab0e | 5003 | * @param ChannelState: specifies the TIM Channel CCxE bit new state. |
| mbed_official | 354:e67efb2aab0e | 5004 | * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable. |
| mbed_official | 354:e67efb2aab0e | 5005 | * @retval None |
| mbed_official | 354:e67efb2aab0e | 5006 | */ |
| mbed_official | 354:e67efb2aab0e | 5007 | static void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState) |
| mbed_official | 354:e67efb2aab0e | 5008 | { |
| mbed_official | 354:e67efb2aab0e | 5009 | uint32_t tmp = 0; |
| mbed_official | 354:e67efb2aab0e | 5010 | |
| mbed_official | 354:e67efb2aab0e | 5011 | /* Check the parameters */ |
| mbed_official | 354:e67efb2aab0e | 5012 | assert_param(IS_TIM_CC1_INSTANCE(TIMx)); |
| mbed_official | 354:e67efb2aab0e | 5013 | assert_param(IS_TIM_CHANNELS(Channel)); |
| mbed_official | 354:e67efb2aab0e | 5014 | |
| mbed_official | 354:e67efb2aab0e | 5015 | tmp = (uint16_t)(TIM_CCER_CC1E << Channel); |
| mbed_official | 354:e67efb2aab0e | 5016 | |
| mbed_official | 354:e67efb2aab0e | 5017 | /* Reset the CCxE Bit */ |
| mbed_official | 354:e67efb2aab0e | 5018 | TIMx->CCER &= ~tmp; |
| mbed_official | 354:e67efb2aab0e | 5019 | |
| mbed_official | 354:e67efb2aab0e | 5020 | /* Set or reset the CCxE Bit */ |
| mbed_official | 354:e67efb2aab0e | 5021 | TIMx->CCER |= (uint32_t)(ChannelState << Channel); |
| mbed_official | 354:e67efb2aab0e | 5022 | } |
| mbed_official | 354:e67efb2aab0e | 5023 | |
| mbed_official | 354:e67efb2aab0e | 5024 | /** |
| mbed_official | 354:e67efb2aab0e | 5025 | * @} |
| mbed_official | 354:e67efb2aab0e | 5026 | */ |
| mbed_official | 354:e67efb2aab0e | 5027 | |
| mbed_official | 354:e67efb2aab0e | 5028 | #endif /* HAL_TIM_MODULE_ENABLED */ |
| mbed_official | 354:e67efb2aab0e | 5029 | |
| mbed_official | 354:e67efb2aab0e | 5030 | |
| mbed_official | 354:e67efb2aab0e | 5031 | |
| mbed_official | 354:e67efb2aab0e | 5032 | /** |
| mbed_official | 354:e67efb2aab0e | 5033 | * @} |
| mbed_official | 354:e67efb2aab0e | 5034 | */ |
| mbed_official | 354:e67efb2aab0e | 5035 | |
| mbed_official | 354:e67efb2aab0e | 5036 | /** |
| mbed_official | 354:e67efb2aab0e | 5037 | * @} |
| mbed_official | 354:e67efb2aab0e | 5038 | */ |
| mbed_official | 354:e67efb2aab0e | 5039 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
