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targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32SC151/system_stm32l1xx.c@579:53297373a894, 2015-07-01 (annotated)

Committer:: mbed_official
Date:: Wed Jul 01 09:45:11 2015 +0100
Revision:: 579:53297373a894
Parent:: 569:18c5cf67e74d

Synchronized with git revision d5b4d2ab9c47edb4dc5776e7177b0c2263459081

Full URL: https://github.com/mbedmicro/mbed/commit/d5b4d2ab9c47edb4dc5776e7177b0c2263459081/

Initial version of drivers for SAMR21

Who changed what in which revision?

User	Revision	Line number	New contents of line
mbed_official	569:18c5cf67e74d	1	/**
mbed_official	569:18c5cf67e74d	2	******************************************************************************
mbed_official	569:18c5cf67e74d	3	* @file system_stm32l1xx.c
mbed_official	569:18c5cf67e74d	4	* @author MCD Application Team
mbed_official	569:18c5cf67e74d	5	* @version V2.0.0
mbed_official	569:18c5cf67e74d	6	* @date 5-September-2014
mbed_official	569:18c5cf67e74d	7	* @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
mbed_official	569:18c5cf67e74d	8	*
mbed_official	569:18c5cf67e74d	9	* This file provides two functions and one global variable to be called from
mbed_official	569:18c5cf67e74d	10	* user application:
mbed_official	569:18c5cf67e74d	11	* - SystemInit(): This function is called at startup just after reset and
mbed_official	569:18c5cf67e74d	12	* before branch to main program. This call is made inside
mbed_official	569:18c5cf67e74d	13	* the "startup_stm32l1xx.s" file.
mbed_official	569:18c5cf67e74d	14	*
mbed_official	569:18c5cf67e74d	15	* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
mbed_official	569:18c5cf67e74d	16	* by the user application to setup the SysTick
mbed_official	569:18c5cf67e74d	17	* timer or configure other parameters.
mbed_official	569:18c5cf67e74d	18	*
mbed_official	569:18c5cf67e74d	19	* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
mbed_official	569:18c5cf67e74d	20	* be called whenever the core clock is changed
mbed_official	569:18c5cf67e74d	21	* during program execution.
mbed_official	569:18c5cf67e74d	22	*
mbed_official	569:18c5cf67e74d	23	* This file configures the system clock as follows:
mbed_official	569:18c5cf67e74d	24	*-----------------------------------------------------------------------------
mbed_official	569:18c5cf67e74d	25	* System clock source \| 1- PLL_HSE_EXTC \| 3- PLL_HSI
mbed_official	569:18c5cf67e74d	26	* \| (external 16 MHz clock) \| (internal 16 MHz)
mbed_official	569:18c5cf67e74d	27	* \| 2- PLL_HSE_XTAL \|
mbed_official	569:18c5cf67e74d	28	* \| (external 16 MHz xtal) \|
mbed_official	569:18c5cf67e74d	29	*-----------------------------------------------------------------------------
mbed_official	569:18c5cf67e74d	30	* SYSCLK(MHz) \| 32 \| 32
mbed_official	569:18c5cf67e74d	31	*-----------------------------------------------------------------------------
mbed_official	569:18c5cf67e74d	32	* AHBCLK (MHz) \| 32 \| 32
mbed_official	569:18c5cf67e74d	33	*-----------------------------------------------------------------------------
mbed_official	569:18c5cf67e74d	34	* APB1CLK (MHz) \| 32 \| 32
mbed_official	569:18c5cf67e74d	35	*-----------------------------------------------------------------------------
mbed_official	569:18c5cf67e74d	36	* APB2CLK (MHz) \| 32 \| 32
mbed_official	569:18c5cf67e74d	37	*-----------------------------------------------------------------------------
mbed_official	569:18c5cf67e74d	38	* USB capable (48 MHz precise clock) \| YES \| NO
mbed_official	569:18c5cf67e74d	39	*-----------------------------------------------------------------------------
mbed_official	569:18c5cf67e74d	40	******************************************************************************
mbed_official	569:18c5cf67e74d	41	* @attention
mbed_official	569:18c5cf67e74d	42	*
mbed_official	569:18c5cf67e74d	43	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
mbed_official	569:18c5cf67e74d	44	*
mbed_official	569:18c5cf67e74d	45	* Redistribution and use in source and binary forms, with or without modification,
mbed_official	569:18c5cf67e74d	46	* are permitted provided that the following conditions are met:
mbed_official	569:18c5cf67e74d	47	* 1. Redistributions of source code must retain the above copyright notice,
mbed_official	569:18c5cf67e74d	48	* this list of conditions and the following disclaimer.
mbed_official	569:18c5cf67e74d	49	* 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official	569:18c5cf67e74d	50	* this list of conditions and the following disclaimer in the documentation
mbed_official	569:18c5cf67e74d	51	* and/or other materials provided with the distribution.
mbed_official	569:18c5cf67e74d	52	* 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official	569:18c5cf67e74d	53	* may be used to endorse or promote products derived from this software
mbed_official	569:18c5cf67e74d	54	* without specific prior written permission.
mbed_official	569:18c5cf67e74d	55	*
mbed_official	569:18c5cf67e74d	56	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official	569:18c5cf67e74d	57	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official	569:18c5cf67e74d	58	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official	569:18c5cf67e74d	59	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official	569:18c5cf67e74d	60	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official	569:18c5cf67e74d	61	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official	569:18c5cf67e74d	62	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official	569:18c5cf67e74d	63	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official	569:18c5cf67e74d	64	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official	569:18c5cf67e74d	65	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official	569:18c5cf67e74d	66	*
mbed_official	569:18c5cf67e74d	67	******************************************************************************
mbed_official	569:18c5cf67e74d	68	*/
mbed_official	569:18c5cf67e74d	69
mbed_official	569:18c5cf67e74d	70	/** @addtogroup CMSIS
mbed_official	569:18c5cf67e74d	71	* @{
mbed_official	569:18c5cf67e74d	72	*/
mbed_official	569:18c5cf67e74d	73
mbed_official	569:18c5cf67e74d	74	/** @addtogroup stm32l1xx_system
mbed_official	569:18c5cf67e74d	75	* @{
mbed_official	569:18c5cf67e74d	76	*/
mbed_official	569:18c5cf67e74d	77
mbed_official	569:18c5cf67e74d	78	/** @addtogroup STM32L1xx_System_Private_Includes
mbed_official	569:18c5cf67e74d	79	* @{
mbed_official	569:18c5cf67e74d	80	*/
mbed_official	569:18c5cf67e74d	81
mbed_official	569:18c5cf67e74d	82	#include "stm32l1xx.h"
mbed_official	569:18c5cf67e74d	83	#include "hal_tick.h"
mbed_official	569:18c5cf67e74d	84
mbed_official	569:18c5cf67e74d	85	/**
mbed_official	569:18c5cf67e74d	86	* @}
mbed_official	569:18c5cf67e74d	87	*/
mbed_official	569:18c5cf67e74d	88
mbed_official	569:18c5cf67e74d	89	/** @addtogroup STM32L1xx_System_Private_TypesDefinitions
mbed_official	569:18c5cf67e74d	90	* @{
mbed_official	569:18c5cf67e74d	91	*/
mbed_official	569:18c5cf67e74d	92
mbed_official	569:18c5cf67e74d	93	/**
mbed_official	569:18c5cf67e74d	94	* @}
mbed_official	569:18c5cf67e74d	95	*/
mbed_official	569:18c5cf67e74d	96
mbed_official	569:18c5cf67e74d	97	/** @addtogroup STM32L1xx_System_Private_Defines
mbed_official	569:18c5cf67e74d	98	* @{
mbed_official	569:18c5cf67e74d	99	*/
mbed_official	569:18c5cf67e74d	100	#if !defined (HSE_VALUE)
mbed_official	569:18c5cf67e74d	101	#define HSE_VALUE ((uint32_t)16000000) /*!< Default value of the External oscillator in Hz.
mbed_official	569:18c5cf67e74d	102	This value can be provided and adapted by the user application. */
mbed_official	569:18c5cf67e74d	103	#endif /* HSE_VALUE */
mbed_official	569:18c5cf67e74d	104
mbed_official	569:18c5cf67e74d	105	#if !defined (HSI_VALUE)
mbed_official	569:18c5cf67e74d	106	#define HSI_VALUE ((uint32_t)16000000) /*!< Default value of the Internal oscillator in Hz.
mbed_official	569:18c5cf67e74d	107	This value can be provided and adapted by the user application. */
mbed_official	569:18c5cf67e74d	108	#endif /* HSI_VALUE */
mbed_official	569:18c5cf67e74d	109
mbed_official	569:18c5cf67e74d	110	/*!< Uncomment the following line if you need to use external SRAM mounted
mbed_official	569:18c5cf67e74d	111	on STM32L152D_EVAL board as data memory */
mbed_official	569:18c5cf67e74d	112	/* #define DATA_IN_ExtSRAM */
mbed_official	569:18c5cf67e74d	113
mbed_official	569:18c5cf67e74d	114	/*!< Uncomment the following line if you need to relocate your vector Table in
mbed_official	569:18c5cf67e74d	115	Internal SRAM. */
mbed_official	569:18c5cf67e74d	116	/* #define VECT_TAB_SRAM */
mbed_official	569:18c5cf67e74d	117	#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field.
mbed_official	569:18c5cf67e74d	118	This value must be a multiple of 0x200. */
mbed_official	569:18c5cf67e74d	119	/**
mbed_official	569:18c5cf67e74d	120	* @}
mbed_official	569:18c5cf67e74d	121	*/
mbed_official	569:18c5cf67e74d	122
mbed_official	569:18c5cf67e74d	123	/** @addtogroup STM32L1xx_System_Private_Macros
mbed_official	569:18c5cf67e74d	124	* @{
mbed_official	569:18c5cf67e74d	125	*/
mbed_official	569:18c5cf67e74d	126
mbed_official	569:18c5cf67e74d	127	/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
mbed_official	569:18c5cf67e74d	128	#define USE_PLL_HSE_EXTC (0) /* Use external clock */
mbed_official	569:18c5cf67e74d	129	#define USE_PLL_HSE_XTAL (1) /* Use external xtal */
mbed_official	569:18c5cf67e74d	130
mbed_official	569:18c5cf67e74d	131	/**
mbed_official	569:18c5cf67e74d	132	* @}
mbed_official	569:18c5cf67e74d	133	*/
mbed_official	569:18c5cf67e74d	134
mbed_official	569:18c5cf67e74d	135	/** @addtogroup STM32L1xx_System_Private_Variables
mbed_official	569:18c5cf67e74d	136	* @{
mbed_official	569:18c5cf67e74d	137	*/
mbed_official	569:18c5cf67e74d	138	/* This variable is updated in three ways:
mbed_official	569:18c5cf67e74d	139	1) by calling CMSIS function SystemCoreClockUpdate()
mbed_official	569:18c5cf67e74d	140	2) by calling HAL API function HAL_RCC_GetHCLKFreq()
mbed_official	569:18c5cf67e74d	141	3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
mbed_official	569:18c5cf67e74d	142	Note: If you use this function to configure the system clock; then there
mbed_official	569:18c5cf67e74d	143	is no need to call the 2 first functions listed above, since SystemCoreClock
mbed_official	569:18c5cf67e74d	144	variable is updated automatically.
mbed_official	569:18c5cf67e74d	145	*/
mbed_official	569:18c5cf67e74d	146	uint32_t SystemCoreClock = 32000000; /* Default with HSI. Will be updated if HSE is used */
mbed_official	569:18c5cf67e74d	147	const uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48};
mbed_official	569:18c5cf67e74d	148	const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
mbed_official	569:18c5cf67e74d	149
mbed_official	569:18c5cf67e74d	150	/**
mbed_official	569:18c5cf67e74d	151	* @}
mbed_official	569:18c5cf67e74d	152	*/
mbed_official	569:18c5cf67e74d	153
mbed_official	569:18c5cf67e74d	154	/** @addtogroup STM32L1xx_System_Private_FunctionPrototypes
mbed_official	569:18c5cf67e74d	155	* @{
mbed_official	569:18c5cf67e74d	156	*/
mbed_official	569:18c5cf67e74d	157
mbed_official	569:18c5cf67e74d	158	#if defined (STM32L151xD) \|\| defined (STM32L152xD) \|\| defined (STM32L162xD)
mbed_official	569:18c5cf67e74d	159	#ifdef DATA_IN_ExtSRAM
mbed_official	569:18c5cf67e74d	160	static void SystemInit_ExtMemCtl(void);
mbed_official	569:18c5cf67e74d	161	#endif /* DATA_IN_ExtSRAM */
mbed_official	569:18c5cf67e74d	162	#endif /* STM32L151xD \|\| STM32L152xD \|\| STM32L162xD */
mbed_official	569:18c5cf67e74d	163
mbed_official	569:18c5cf67e74d	164	#if (USE_PLL_HSE_XTAL != 0) \|\| (USE_PLL_HSE_EXTC != 0)
mbed_official	569:18c5cf67e74d	165	uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
mbed_official	569:18c5cf67e74d	166	#endif
mbed_official	569:18c5cf67e74d	167
mbed_official	569:18c5cf67e74d	168	uint8_t SetSysClock_PLL_HSI(void);
mbed_official	569:18c5cf67e74d	169
mbed_official	569:18c5cf67e74d	170	/**
mbed_official	569:18c5cf67e74d	171	* @}
mbed_official	569:18c5cf67e74d	172	*/
mbed_official	569:18c5cf67e74d	173
mbed_official	569:18c5cf67e74d	174	/** @addtogroup STM32L1xx_System_Private_Functions
mbed_official	569:18c5cf67e74d	175	* @{
mbed_official	569:18c5cf67e74d	176	*/
mbed_official	569:18c5cf67e74d	177
mbed_official	569:18c5cf67e74d	178	/**
mbed_official	569:18c5cf67e74d	179	* @brief Setup the microcontroller system.
mbed_official	569:18c5cf67e74d	180	* Initialize the Embedded Flash Interface, the PLL and update the
mbed_official	569:18c5cf67e74d	181	* SystemCoreClock variable.
mbed_official	569:18c5cf67e74d	182	* @param None
mbed_official	569:18c5cf67e74d	183	* @retval None
mbed_official	569:18c5cf67e74d	184	*/
mbed_official	569:18c5cf67e74d	185	void SystemInit (void)
mbed_official	569:18c5cf67e74d	186	{
mbed_official	569:18c5cf67e74d	187	/!< Set MSION bit /
mbed_official	569:18c5cf67e74d	188	RCC->CR \|= (uint32_t)0x00000100;
mbed_official	569:18c5cf67e74d	189
mbed_official	569:18c5cf67e74d	190	/!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits /
mbed_official	569:18c5cf67e74d	191	RCC->CFGR &= (uint32_t)0x88FFC00C;
mbed_official	569:18c5cf67e74d	192
mbed_official	569:18c5cf67e74d	193	/!< Reset HSION, HSEON, CSSON and PLLON bits /
mbed_official	569:18c5cf67e74d	194	RCC->CR &= (uint32_t)0xEEFEFFFE;
mbed_official	569:18c5cf67e74d	195
mbed_official	569:18c5cf67e74d	196	/!< Reset HSEBYP bit /
mbed_official	569:18c5cf67e74d	197	RCC->CR &= (uint32_t)0xFFFBFFFF;
mbed_official	569:18c5cf67e74d	198
mbed_official	569:18c5cf67e74d	199	/!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits /
mbed_official	569:18c5cf67e74d	200	RCC->CFGR &= (uint32_t)0xFF02FFFF;
mbed_official	569:18c5cf67e74d	201
mbed_official	569:18c5cf67e74d	202	/!< Disable all interrupts /
mbed_official	569:18c5cf67e74d	203	RCC->CIR = 0x00000000;
mbed_official	569:18c5cf67e74d	204
mbed_official	569:18c5cf67e74d	205	#ifdef DATA_IN_ExtSRAM
mbed_official	569:18c5cf67e74d	206	SystemInit_ExtMemCtl();
mbed_official	569:18c5cf67e74d	207	#endif /* DATA_IN_ExtSRAM */
mbed_official	569:18c5cf67e74d	208
mbed_official	569:18c5cf67e74d	209	#ifdef VECT_TAB_SRAM
mbed_official	569:18c5cf67e74d	210	SCB->VTOR = SRAM_BASE \| VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
mbed_official	569:18c5cf67e74d	211	#else
mbed_official	569:18c5cf67e74d	212	SCB->VTOR = FLASH_BASE \| VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
mbed_official	569:18c5cf67e74d	213	#endif
mbed_official	569:18c5cf67e74d	214
mbed_official	569:18c5cf67e74d	215	/* Configure the Cube driver */
mbed_official	569:18c5cf67e74d	216	SystemCoreClock = 16000000; // At this stage the HSI is used as system clock
mbed_official	569:18c5cf67e74d	217	HAL_Init();
mbed_official	569:18c5cf67e74d	218
mbed_official	569:18c5cf67e74d	219	/* Configure the System clock source, PLL Multiplier and Divider factors,
mbed_official	569:18c5cf67e74d	220	AHB/APBx prescalers and Flash settings */
mbed_official	569:18c5cf67e74d	221	SetSysClock();
mbed_official	569:18c5cf67e74d	222
mbed_official	569:18c5cf67e74d	223	/* Reset the timer to avoid issues after the RAM initialization */
mbed_official	569:18c5cf67e74d	224	TIM_MST_RESET_ON;
mbed_official	569:18c5cf67e74d	225	TIM_MST_RESET_OFF;
mbed_official	569:18c5cf67e74d	226	}
mbed_official	569:18c5cf67e74d	227
mbed_official	569:18c5cf67e74d	228	/**
mbed_official	569:18c5cf67e74d	229	* @brief Update SystemCoreClock according to Clock Register Values
mbed_official	569:18c5cf67e74d	230	* The SystemCoreClock variable contains the core clock (HCLK), it can
mbed_official	569:18c5cf67e74d	231	* be used by the user application to setup the SysTick timer or configure
mbed_official	569:18c5cf67e74d	232	* other parameters.
mbed_official	569:18c5cf67e74d	233	*
mbed_official	569:18c5cf67e74d	234	* @note Each time the core clock (HCLK) changes, this function must be called
mbed_official	569:18c5cf67e74d	235	* to update SystemCoreClock variable value. Otherwise, any configuration
mbed_official	569:18c5cf67e74d	236	* based on this variable will be incorrect.
mbed_official	569:18c5cf67e74d	237	*
mbed_official	569:18c5cf67e74d	238	* @note - The system frequency computed by this function is not the real
mbed_official	569:18c5cf67e74d	239	* frequency in the chip. It is calculated based on the predefined
mbed_official	569:18c5cf67e74d	240	* constant and the selected clock source:
mbed_official	569:18c5cf67e74d	241	*
mbed_official	569:18c5cf67e74d	242	* - If SYSCLK source is MSI, SystemCoreClock will contain the MSI
mbed_official	569:18c5cf67e74d	243	* value as defined by the MSI range.
mbed_official	569:18c5cf67e74d	244	*
mbed_official	569:18c5cf67e74d	245	* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
mbed_official	569:18c5cf67e74d	246	*
mbed_official	569:18c5cf67e74d	247	* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
mbed_official	569:18c5cf67e74d	248	*
mbed_official	569:18c5cf67e74d	249	* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
mbed_official	569:18c5cf67e74d	250	* or HSI_VALUE(*) multiplied/divided by the PLL factors.
mbed_official	569:18c5cf67e74d	251	*
mbed_official	569:18c5cf67e74d	252	* (*) HSI_VALUE is a constant defined in stm32l1xx.h file (default value
mbed_official	569:18c5cf67e74d	253	* 16 MHz) but the real value may vary depending on the variations
mbed_official	569:18c5cf67e74d	254	* in voltage and temperature.
mbed_official	569:18c5cf67e74d	255	*
mbed_official	569:18c5cf67e74d	256	* (**) HSE_VALUE is a constant defined in stm32l1xx.h file (default value
mbed_official	569:18c5cf67e74d	257	* 8 MHz), user has to ensure that HSE_VALUE is same as the real
mbed_official	569:18c5cf67e74d	258	* frequency of the crystal used. Otherwise, this function may
mbed_official	569:18c5cf67e74d	259	* have wrong result.
mbed_official	569:18c5cf67e74d	260	*
mbed_official	569:18c5cf67e74d	261	* - The result of this function could be not correct when using fractional
mbed_official	569:18c5cf67e74d	262	* value for HSE crystal.
mbed_official	569:18c5cf67e74d	263	* @param None
mbed_official	569:18c5cf67e74d	264	* @retval None
mbed_official	569:18c5cf67e74d	265	*/
mbed_official	569:18c5cf67e74d	266	void SystemCoreClockUpdate (void)
mbed_official	569:18c5cf67e74d	267	{
mbed_official	569:18c5cf67e74d	268	uint32_t tmp = 0, pllmul = 0, plldiv = 0, pllsource = 0, msirange = 0;
mbed_official	569:18c5cf67e74d	269
mbed_official	569:18c5cf67e74d	270	/* Get SYSCLK source -------------------------------------------------------*/
mbed_official	569:18c5cf67e74d	271	tmp = RCC->CFGR & RCC_CFGR_SWS;
mbed_official	569:18c5cf67e74d	272
mbed_official	569:18c5cf67e74d	273	switch (tmp)
mbed_official	569:18c5cf67e74d	274	{
mbed_official	569:18c5cf67e74d	275	case 0x00: /* MSI used as system clock */
mbed_official	569:18c5cf67e74d	276	msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;
mbed_official	569:18c5cf67e74d	277	SystemCoreClock = (32768 * (1 << (msirange + 1)));
mbed_official	569:18c5cf67e74d	278	break;
mbed_official	569:18c5cf67e74d	279	case 0x04: /* HSI used as system clock */
mbed_official	569:18c5cf67e74d	280	SystemCoreClock = HSI_VALUE;
mbed_official	569:18c5cf67e74d	281	break;
mbed_official	569:18c5cf67e74d	282	case 0x08: /* HSE used as system clock */
mbed_official	569:18c5cf67e74d	283	SystemCoreClock = HSE_VALUE;
mbed_official	569:18c5cf67e74d	284	break;
mbed_official	569:18c5cf67e74d	285	case 0x0C: /* PLL used as system clock */
mbed_official	569:18c5cf67e74d	286	/* Get PLL clock source and multiplication factor ----------------------*/
mbed_official	569:18c5cf67e74d	287	pllmul = RCC->CFGR & RCC_CFGR_PLLMUL;
mbed_official	569:18c5cf67e74d	288	plldiv = RCC->CFGR & RCC_CFGR_PLLDIV;
mbed_official	569:18c5cf67e74d	289	pllmul = PLLMulTable[(pllmul >> 18)];
mbed_official	569:18c5cf67e74d	290	plldiv = (plldiv >> 22) + 1;
mbed_official	569:18c5cf67e74d	291
mbed_official	569:18c5cf67e74d	292	pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
mbed_official	569:18c5cf67e74d	293
mbed_official	569:18c5cf67e74d	294	if (pllsource == 0x00)
mbed_official	569:18c5cf67e74d	295	{
mbed_official	569:18c5cf67e74d	296	/* HSI oscillator clock selected as PLL clock entry */
mbed_official	569:18c5cf67e74d	297	SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv);
mbed_official	569:18c5cf67e74d	298	}
mbed_official	569:18c5cf67e74d	299	else
mbed_official	569:18c5cf67e74d	300	{
mbed_official	569:18c5cf67e74d	301	/* HSE selected as PLL clock entry */
mbed_official	569:18c5cf67e74d	302	SystemCoreClock = (((HSE_VALUE) * pllmul) / plldiv);
mbed_official	569:18c5cf67e74d	303	}
mbed_official	569:18c5cf67e74d	304	break;
mbed_official	569:18c5cf67e74d	305	default: /* MSI used as system clock */
mbed_official	569:18c5cf67e74d	306	msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;
mbed_official	569:18c5cf67e74d	307	SystemCoreClock = (32768 * (1 << (msirange + 1)));
mbed_official	569:18c5cf67e74d	308	break;
mbed_official	569:18c5cf67e74d	309	}
mbed_official	569:18c5cf67e74d	310	/* Compute HCLK clock frequency --------------------------------------------*/
mbed_official	569:18c5cf67e74d	311	/* Get HCLK prescaler */
mbed_official	569:18c5cf67e74d	312	tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
mbed_official	569:18c5cf67e74d	313	/* HCLK clock frequency */
mbed_official	569:18c5cf67e74d	314	SystemCoreClock >>= tmp;
mbed_official	569:18c5cf67e74d	315	}
mbed_official	569:18c5cf67e74d	316
mbed_official	569:18c5cf67e74d	317	#if defined (STM32L151xD) \|\| defined (STM32L152xD) \|\| defined (STM32L162xD)
mbed_official	569:18c5cf67e74d	318	#ifdef DATA_IN_ExtSRAM
mbed_official	569:18c5cf67e74d	319	/**
mbed_official	569:18c5cf67e74d	320	* @brief Setup the external memory controller.
mbed_official	569:18c5cf67e74d	321	* Called in SystemInit() function before jump to main.
mbed_official	569:18c5cf67e74d	322	* This function configures the external SRAM mounted on STM32L152D_EVAL board
mbed_official	569:18c5cf67e74d	323	* This SRAM will be used as program data memory (including heap and stack).
mbed_official	569:18c5cf67e74d	324	* @param None
mbed_official	569:18c5cf67e74d	325	* @retval None
mbed_official	569:18c5cf67e74d	326	*/
mbed_official	569:18c5cf67e74d	327	void SystemInit_ExtMemCtl(void)
mbed_official	569:18c5cf67e74d	328	{
mbed_official	569:18c5cf67e74d	329	/-- GPIOs Configuration -----------------------------------------------------/
mbed_official	569:18c5cf67e74d	330	/*
mbed_official	569:18c5cf67e74d	331	+-------------------+--------------------+------------------+------------------+
mbed_official	569:18c5cf67e74d	332	+ SRAM pins assignment +
mbed_official	569:18c5cf67e74d	333	+-------------------+--------------------+------------------+------------------+
mbed_official	569:18c5cf67e74d	334	\| PD0 <-> FSMC_D2 \| PE0 <-> FSMC_NBL0 \| PF0 <-> FSMC_A0 \| PG0 <-> FSMC_A10 \|
mbed_official	569:18c5cf67e74d	335	\| PD1 <-> FSMC_D3 \| PE1 <-> FSMC_NBL1 \| PF1 <-> FSMC_A1 \| PG1 <-> FSMC_A11 \|
mbed_official	569:18c5cf67e74d	336	\| PD4 <-> FSMC_NOE \| PE7 <-> FSMC_D4 \| PF2 <-> FSMC_A2 \| PG2 <-> FSMC_A12 \|
mbed_official	569:18c5cf67e74d	337	\| PD5 <-> FSMC_NWE \| PE8 <-> FSMC_D5 \| PF3 <-> FSMC_A3 \| PG3 <-> FSMC_A13 \|
mbed_official	569:18c5cf67e74d	338	\| PD8 <-> FSMC_D13 \| PE9 <-> FSMC_D6 \| PF4 <-> FSMC_A4 \| PG4 <-> FSMC_A14 \|
mbed_official	569:18c5cf67e74d	339	\| PD9 <-> FSMC_D14 \| PE10 <-> FSMC_D7 \| PF5 <-> FSMC_A5 \| PG5 <-> FSMC_A15 \|
mbed_official	569:18c5cf67e74d	340	\| PD10 <-> FSMC_D15 \| PE11 <-> FSMC_D8 \| PF12 <-> FSMC_A6 \| PG10<-> FSMC_NE2 \|
mbed_official	569:18c5cf67e74d	341	\| PD11 <-> FSMC_A16 \| PE12 <-> FSMC_D9 \| PF13 <-> FSMC_A7 \|------------------+
mbed_official	569:18c5cf67e74d	342	\| PD12 <-> FSMC_A17 \| PE13 <-> FSMC_D10 \| PF14 <-> FSMC_A8 \|
mbed_official	569:18c5cf67e74d	343	\| PD13 <-> FSMC_A18 \| PE14 <-> FSMC_D11 \| PF15 <-> FSMC_A9 \|
mbed_official	569:18c5cf67e74d	344	\| PD14 <-> FSMC_D0 \| PE15 <-> FSMC_D12 \|------------------+
mbed_official	569:18c5cf67e74d	345	\| PD15 <-> FSMC_D1 \|--------------------+
mbed_official	569:18c5cf67e74d	346	+-------------------+
mbed_official	569:18c5cf67e74d	347	*/
mbed_official	569:18c5cf67e74d	348
mbed_official	569:18c5cf67e74d	349	/* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
mbed_official	569:18c5cf67e74d	350	RCC->AHBENR = 0x000080D8;
mbed_official	569:18c5cf67e74d	351
mbed_official	569:18c5cf67e74d	352	/* Connect PDx pins to FSMC Alternate function */
mbed_official	569:18c5cf67e74d	353	GPIOD->AFR[0] = 0x00CC00CC;
mbed_official	569:18c5cf67e74d	354	GPIOD->AFR[1] = 0xCCCCCCCC;
mbed_official	569:18c5cf67e74d	355	/* Configure PDx pins in Alternate function mode */
mbed_official	569:18c5cf67e74d	356	GPIOD->MODER = 0xAAAA0A0A;
mbed_official	569:18c5cf67e74d	357	/* Configure PDx pins speed to 40 MHz */
mbed_official	569:18c5cf67e74d	358	GPIOD->OSPEEDR = 0xFFFF0F0F;
mbed_official	569:18c5cf67e74d	359	/* Configure PDx pins Output type to push-pull */
mbed_official	569:18c5cf67e74d	360	GPIOD->OTYPER = 0x00000000;
mbed_official	569:18c5cf67e74d	361	/* No pull-up, pull-down for PDx pins */
mbed_official	569:18c5cf67e74d	362	GPIOD->PUPDR = 0x00000000;
mbed_official	569:18c5cf67e74d	363
mbed_official	569:18c5cf67e74d	364	/* Connect PEx pins to FSMC Alternate function */
mbed_official	569:18c5cf67e74d	365	GPIOE->AFR[0] = 0xC00000CC;
mbed_official	569:18c5cf67e74d	366	GPIOE->AFR[1] = 0xCCCCCCCC;
mbed_official	569:18c5cf67e74d	367	/* Configure PEx pins in Alternate function mode */
mbed_official	569:18c5cf67e74d	368	GPIOE->MODER = 0xAAAA800A;
mbed_official	569:18c5cf67e74d	369	/* Configure PEx pins speed to 40 MHz */
mbed_official	569:18c5cf67e74d	370	GPIOE->OSPEEDR = 0xFFFFC00F;
mbed_official	569:18c5cf67e74d	371	/* Configure PEx pins Output type to push-pull */
mbed_official	569:18c5cf67e74d	372	GPIOE->OTYPER = 0x00000000;
mbed_official	569:18c5cf67e74d	373	/* No pull-up, pull-down for PEx pins */
mbed_official	569:18c5cf67e74d	374	GPIOE->PUPDR = 0x00000000;
mbed_official	569:18c5cf67e74d	375
mbed_official	569:18c5cf67e74d	376	/* Connect PFx pins to FSMC Alternate function */
mbed_official	569:18c5cf67e74d	377	GPIOF->AFR[0] = 0x00CCCCCC;
mbed_official	569:18c5cf67e74d	378	GPIOF->AFR[1] = 0xCCCC0000;
mbed_official	569:18c5cf67e74d	379	/* Configure PFx pins in Alternate function mode */
mbed_official	569:18c5cf67e74d	380	GPIOF->MODER = 0xAA000AAA;
mbed_official	569:18c5cf67e74d	381	/* Configure PFx pins speed to 40 MHz */
mbed_official	569:18c5cf67e74d	382	GPIOF->OSPEEDR = 0xFF000FFF;
mbed_official	569:18c5cf67e74d	383	/* Configure PFx pins Output type to push-pull */
mbed_official	569:18c5cf67e74d	384	GPIOF->OTYPER = 0x00000000;
mbed_official	569:18c5cf67e74d	385	/* No pull-up, pull-down for PFx pins */
mbed_official	569:18c5cf67e74d	386	GPIOF->PUPDR = 0x00000000;
mbed_official	569:18c5cf67e74d	387
mbed_official	569:18c5cf67e74d	388	/* Connect PGx pins to FSMC Alternate function */
mbed_official	569:18c5cf67e74d	389	GPIOG->AFR[0] = 0x00CCCCCC;
mbed_official	569:18c5cf67e74d	390	GPIOG->AFR[1] = 0x00000C00;
mbed_official	569:18c5cf67e74d	391	/* Configure PGx pins in Alternate function mode */
mbed_official	569:18c5cf67e74d	392	GPIOG->MODER = 0x00200AAA;
mbed_official	569:18c5cf67e74d	393	/* Configure PGx pins speed to 40 MHz */
mbed_official	569:18c5cf67e74d	394	GPIOG->OSPEEDR = 0x00300FFF;
mbed_official	569:18c5cf67e74d	395	/* Configure PGx pins Output type to push-pull */
mbed_official	569:18c5cf67e74d	396	GPIOG->OTYPER = 0x00000000;
mbed_official	569:18c5cf67e74d	397	/* No pull-up, pull-down for PGx pins */
mbed_official	569:18c5cf67e74d	398	GPIOG->PUPDR = 0x00000000;
mbed_official	569:18c5cf67e74d	399
mbed_official	569:18c5cf67e74d	400	/-- FSMC Configuration ------------------------------------------------------/
mbed_official	569:18c5cf67e74d	401	/* Enable the FSMC interface clock */
mbed_official	569:18c5cf67e74d	402	RCC->AHBENR = 0x400080D8;
mbed_official	569:18c5cf67e74d	403
mbed_official	569:18c5cf67e74d	404	/* Configure and enable Bank1_SRAM3 */
mbed_official	569:18c5cf67e74d	405	FSMC_Bank1->BTCR[4] = 0x00001011;
mbed_official	569:18c5cf67e74d	406	FSMC_Bank1->BTCR[5] = 0x00000300;
mbed_official	569:18c5cf67e74d	407	FSMC_Bank1E->BWTR[4] = 0x0FFFFFFF;
mbed_official	569:18c5cf67e74d	408	/*
mbed_official	569:18c5cf67e74d	409	Bank1_SRAM3 is configured as follow:
mbed_official	569:18c5cf67e74d	410
mbed_official	569:18c5cf67e74d	411	p.FSMC_AddressSetupTime = 0;
mbed_official	569:18c5cf67e74d	412	p.FSMC_AddressHoldTime = 0;
mbed_official	569:18c5cf67e74d	413	p.FSMC_DataSetupTime = 3;
mbed_official	569:18c5cf67e74d	414	p.FSMC_BusTurnAroundDuration = 0;
mbed_official	569:18c5cf67e74d	415	p.FSMC_CLKDivision = 0;
mbed_official	569:18c5cf67e74d	416	p.FSMC_DataLatency = 0;
mbed_official	569:18c5cf67e74d	417	p.FSMC_AccessMode = FSMC_AccessMode_A;
mbed_official	569:18c5cf67e74d	418
mbed_official	569:18c5cf67e74d	419	FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM3;
mbed_official	569:18c5cf67e74d	420	FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
mbed_official	569:18c5cf67e74d	421	FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_SRAM;
mbed_official	569:18c5cf67e74d	422	FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
mbed_official	569:18c5cf67e74d	423	FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
mbed_official	569:18c5cf67e74d	424	FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
mbed_official	569:18c5cf67e74d	425	FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
mbed_official	569:18c5cf67e74d	426	FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
mbed_official	569:18c5cf67e74d	427	FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
mbed_official	569:18c5cf67e74d	428	FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
mbed_official	569:18c5cf67e74d	429	FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
mbed_official	569:18c5cf67e74d	430	FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
mbed_official	569:18c5cf67e74d	431	FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
mbed_official	569:18c5cf67e74d	432	FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
mbed_official	569:18c5cf67e74d	433	FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;
mbed_official	569:18c5cf67e74d	434
mbed_official	569:18c5cf67e74d	435	FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure);
mbed_official	569:18c5cf67e74d	436
mbed_official	569:18c5cf67e74d	437	FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM3, ENABLE);
mbed_official	569:18c5cf67e74d	438	*/
mbed_official	569:18c5cf67e74d	439
mbed_official	569:18c5cf67e74d	440	}
mbed_official	569:18c5cf67e74d	441	#endif /* DATA_IN_ExtSRAM */
mbed_official	569:18c5cf67e74d	442	#endif /* STM32L151xD \|\| STM32L152xD \|\| STM32L162xD */
mbed_official	569:18c5cf67e74d	443
mbed_official	569:18c5cf67e74d	444	/**
mbed_official	569:18c5cf67e74d	445	* @brief Configures the System clock source, PLL Multiplier and Divider factors,
mbed_official	569:18c5cf67e74d	446	* AHB/APBx prescalers and Flash settings
mbed_official	569:18c5cf67e74d	447	* @note This function should be called only once the RCC clock configuration
mbed_official	569:18c5cf67e74d	448	* is reset to the default reset state (done in SystemInit() function).
mbed_official	569:18c5cf67e74d	449	* @param None
mbed_official	569:18c5cf67e74d	450	* @retval None
mbed_official	569:18c5cf67e74d	451	*/
mbed_official	569:18c5cf67e74d	452	void SetSysClock(void)
mbed_official	569:18c5cf67e74d	453	{
mbed_official	569:18c5cf67e74d	454	/* 1- Try to start with HSE and external clock */
mbed_official	569:18c5cf67e74d	455	#if USE_PLL_HSE_EXTC != 0
mbed_official	569:18c5cf67e74d	456	if (SetSysClock_PLL_HSE(1) == 0)
mbed_official	569:18c5cf67e74d	457	#endif
mbed_official	569:18c5cf67e74d	458	{
mbed_official	569:18c5cf67e74d	459	/* 2- If fail try to start with HSE and external xtal */
mbed_official	569:18c5cf67e74d	460	#if USE_PLL_HSE_XTAL != 0
mbed_official	569:18c5cf67e74d	461	if (SetSysClock_PLL_HSE(0) == 0)
mbed_official	569:18c5cf67e74d	462	#endif
mbed_official	569:18c5cf67e74d	463	{
mbed_official	569:18c5cf67e74d	464	/* 3- If fail start with HSI clock */
mbed_official	569:18c5cf67e74d	465	if (SetSysClock_PLL_HSI() == 0)
mbed_official	569:18c5cf67e74d	466	{
mbed_official	569:18c5cf67e74d	467	while(1)
mbed_official	569:18c5cf67e74d	468	{
mbed_official	569:18c5cf67e74d	469	// [TODO] Put something here to tell the user that a problem occured...
mbed_official	569:18c5cf67e74d	470	}
mbed_official	569:18c5cf67e74d	471	}
mbed_official	569:18c5cf67e74d	472	}
mbed_official	569:18c5cf67e74d	473	}
mbed_official	569:18c5cf67e74d	474
mbed_official	569:18c5cf67e74d	475	/* Output clock on MCO1 pin(PA8) for debugging purpose */
mbed_official	569:18c5cf67e74d	476	//HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1);
mbed_official	569:18c5cf67e74d	477	}
mbed_official	569:18c5cf67e74d	478
mbed_official	569:18c5cf67e74d	479	#if (USE_PLL_HSE_XTAL != 0) \|\| (USE_PLL_HSE_EXTC != 0)
mbed_official	569:18c5cf67e74d	480	/******************************************************************************/
mbed_official	569:18c5cf67e74d	481	/* PLL (clocked by HSE) used as System clock source */
mbed_official	569:18c5cf67e74d	482	/******************************************************************************/
mbed_official	569:18c5cf67e74d	483	uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
mbed_official	569:18c5cf67e74d	484	{
mbed_official	569:18c5cf67e74d	485	RCC_ClkInitTypeDef RCC_ClkInitStruct;
mbed_official	569:18c5cf67e74d	486	RCC_OscInitTypeDef RCC_OscInitStruct;
mbed_official	569:18c5cf67e74d	487
mbed_official	569:18c5cf67e74d	488	/* Used to gain time after DeepSleep in case HSI is used */
mbed_official	569:18c5cf67e74d	489	if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
mbed_official	569:18c5cf67e74d	490	{
mbed_official	569:18c5cf67e74d	491	return 0;
mbed_official	569:18c5cf67e74d	492	}
mbed_official	569:18c5cf67e74d	493
mbed_official	569:18c5cf67e74d	494	/* The voltage scaling allows optimizing the power consumption when the device is
mbed_official	569:18c5cf67e74d	495	clocked below the maximum system frequency, to update the voltage scaling value
mbed_official	569:18c5cf67e74d	496	regarding system frequency refer to product datasheet. */
mbed_official	569:18c5cf67e74d	497	__PWR_CLK_ENABLE();
mbed_official	569:18c5cf67e74d	498	__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
mbed_official	569:18c5cf67e74d	499
mbed_official	569:18c5cf67e74d	500	/* Enable HSE and HSI48 oscillators and activate PLL with HSE as source */
mbed_official	569:18c5cf67e74d	501	RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE \| RCC_OSCILLATORTYPE_HSI;
mbed_official	569:18c5cf67e74d	502	if (bypass == 0)
mbed_official	569:18c5cf67e74d	503	{
mbed_official	569:18c5cf67e74d	504	RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 16 MHz xtal on OSC_IN/OSC_OUT */
mbed_official	569:18c5cf67e74d	505	}
mbed_official	569:18c5cf67e74d	506	else
mbed_official	569:18c5cf67e74d	507	{
mbed_official	569:18c5cf67e74d	508	RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 16 MHz clock on OSC_IN */
mbed_official	569:18c5cf67e74d	509	}
mbed_official	569:18c5cf67e74d	510	RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
mbed_official	569:18c5cf67e74d	511	// SYSCLK = 32 MHz ((16 MHz * 6) / 3)
mbed_official	569:18c5cf67e74d	512	// USBCLK = 48 MHz ((16 MHz * 6) / 2) --> USB OK
mbed_official	569:18c5cf67e74d	513	RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
mbed_official	569:18c5cf67e74d	514	RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
mbed_official	569:18c5cf67e74d	515	RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL6;
mbed_official	569:18c5cf67e74d	516	RCC_OscInitStruct.PLL.PLLDIV = RCC_PLL_DIV3;
mbed_official	569:18c5cf67e74d	517
mbed_official	569:18c5cf67e74d	518	if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
mbed_official	569:18c5cf67e74d	519	{
mbed_official	569:18c5cf67e74d	520	return 0; // FAIL
mbed_official	569:18c5cf67e74d	521	}
mbed_official	569:18c5cf67e74d	522
mbed_official	569:18c5cf67e74d	523	/* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
mbed_official	569:18c5cf67e74d	524	RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK \| RCC_CLOCKTYPE_HCLK \| RCC_CLOCKTYPE_PCLK1 \| RCC_CLOCKTYPE_PCLK2);
mbed_official	569:18c5cf67e74d	525	RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz
mbed_official	569:18c5cf67e74d	526	RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 32 MHz
mbed_official	569:18c5cf67e74d	527	RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 32 MHz
mbed_official	569:18c5cf67e74d	528	RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 32 MHz
mbed_official	569:18c5cf67e74d	529	if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
mbed_official	569:18c5cf67e74d	530	{
mbed_official	569:18c5cf67e74d	531	return 0; // FAIL
mbed_official	569:18c5cf67e74d	532	}
mbed_official	569:18c5cf67e74d	533
mbed_official	569:18c5cf67e74d	534	/* Output clock on MCO1 pin(PA8) for debugging purpose */
mbed_official	569:18c5cf67e74d	535	//if (bypass == 0)
mbed_official	569:18c5cf67e74d	536	//HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
mbed_official	569:18c5cf67e74d	537	//else
mbed_official	569:18c5cf67e74d	538	//HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
mbed_official	569:18c5cf67e74d	539
mbed_official	569:18c5cf67e74d	540	return 1; // OK
mbed_official	569:18c5cf67e74d	541	}
mbed_official	569:18c5cf67e74d	542	#endif
mbed_official	569:18c5cf67e74d	543
mbed_official	569:18c5cf67e74d	544	/******************************************************************************/
mbed_official	569:18c5cf67e74d	545	/* PLL (clocked by HSI) used as System clock source */
mbed_official	569:18c5cf67e74d	546	/******************************************************************************/
mbed_official	569:18c5cf67e74d	547	uint8_t SetSysClock_PLL_HSI(void)
mbed_official	569:18c5cf67e74d	548	{
mbed_official	569:18c5cf67e74d	549	RCC_ClkInitTypeDef RCC_ClkInitStruct;
mbed_official	569:18c5cf67e74d	550	RCC_OscInitTypeDef RCC_OscInitStruct;
mbed_official	569:18c5cf67e74d	551
mbed_official	569:18c5cf67e74d	552	/* The voltage scaling allows optimizing the power consumption when the device is
mbed_official	569:18c5cf67e74d	553	clocked below the maximum system frequency, to update the voltage scaling value
mbed_official	569:18c5cf67e74d	554	regarding system frequency refer to product datasheet. */
mbed_official	569:18c5cf67e74d	555	__PWR_CLK_ENABLE();
mbed_official	569:18c5cf67e74d	556	__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
mbed_official	569:18c5cf67e74d	557
mbed_official	569:18c5cf67e74d	558	/* Enable HSI oscillator and activate PLL with HSI as source */
mbed_official	569:18c5cf67e74d	559	RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI \| RCC_OSCILLATORTYPE_HSE;
mbed_official	569:18c5cf67e74d	560	RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
mbed_official	569:18c5cf67e74d	561	RCC_OscInitStruct.HSIState = RCC_HSI_ON;
mbed_official	569:18c5cf67e74d	562	// SYSCLK = 32 MHz ((16 MHz * 4) / 2)
mbed_official	569:18c5cf67e74d	563	// USBCLK = 64 MHz (16 MHz * 4) --> USB not possible
mbed_official	569:18c5cf67e74d	564	RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
mbed_official	569:18c5cf67e74d	565	RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
mbed_official	569:18c5cf67e74d	566	RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL4;
mbed_official	569:18c5cf67e74d	567	RCC_OscInitStruct.PLL.PLLDIV = RCC_PLL_DIV2;
mbed_official	569:18c5cf67e74d	568	if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
mbed_official	569:18c5cf67e74d	569	{
mbed_official	569:18c5cf67e74d	570	return 0; // FAIL
mbed_official	569:18c5cf67e74d	571	}
mbed_official	569:18c5cf67e74d	572
mbed_official	569:18c5cf67e74d	573	/* Poll VOSF bit of in PWR_CSR. Wait until it is reset to 0 */
mbed_official	569:18c5cf67e74d	574	while (__HAL_PWR_GET_FLAG(PWR_FLAG_VOS) != RESET) {};
mbed_official	569:18c5cf67e74d	575
mbed_official	569:18c5cf67e74d	576	/* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
mbed_official	569:18c5cf67e74d	577	RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK \| RCC_CLOCKTYPE_HCLK \| RCC_CLOCKTYPE_PCLK1 \| RCC_CLOCKTYPE_PCLK2);
mbed_official	569:18c5cf67e74d	578	RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz
mbed_official	569:18c5cf67e74d	579	RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 32 MHz
mbed_official	569:18c5cf67e74d	580	RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 32 MHz
mbed_official	569:18c5cf67e74d	581	RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 32 MHz
mbed_official	569:18c5cf67e74d	582	if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
mbed_official	569:18c5cf67e74d	583	{
mbed_official	569:18c5cf67e74d	584	return 0; // FAIL
mbed_official	569:18c5cf67e74d	585	}
mbed_official	569:18c5cf67e74d	586
mbed_official	569:18c5cf67e74d	587	/* Output clock on MCO1 pin(PA8) for debugging purpose */
mbed_official	569:18c5cf67e74d	588	//HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
mbed_official	569:18c5cf67e74d	589
mbed_official	569:18c5cf67e74d	590	return 1; // OK
mbed_official	569:18c5cf67e74d	591	}
mbed_official	569:18c5cf67e74d	592
mbed_official	569:18c5cf67e74d	593	/**
mbed_official	569:18c5cf67e74d	594	* @}
mbed_official	569:18c5cf67e74d	595	*/
mbed_official	569:18c5cf67e74d	596
mbed_official	569:18c5cf67e74d	597	/**
mbed_official	569:18c5cf67e74d	598	* @}
mbed_official	569:18c5cf67e74d	599	*/
mbed_official	569:18c5cf67e74d	600
mbed_official	569:18c5cf67e74d	601	/**
mbed_official	569:18c5cf67e74d	602	* @}
mbed_official	569:18c5cf67e74d	603	*/
mbed_official	569:18c5cf67e74d	604
mbed_official	569:18c5cf67e74d	605	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/