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Last commit 20 Feb 2019 by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32SC151/stm32l151xc.h@579:53297373a894, 2015-07-01 (annotated)

Committer:
mbed_official
Date:
Wed Jul 01 09:45:11 2015 +0100
Revision:
579:53297373a894
Parent:
569:18c5cf67e74d 
Synchronized with git revision d5b4d2ab9c47edb4dc5776e7177b0c2263459081



Full URL: https://github.com/mbedmicro/mbed/commit/d5b4d2ab9c47edb4dc5776e7177b0c2263459081/



Initial version of drivers for SAMR21

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 545:5112d5ae6723 1 /**
mbed_official 545:5112d5ae6723 2 ******************************************************************************
mbed_official 545:5112d5ae6723 3 * @file stm32l151xc.h
mbed_official 545:5112d5ae6723 4 * @author MCD Application Team
mbed_official 545:5112d5ae6723 5 * @version V2.0.0
mbed_official 545:5112d5ae6723 6 * @date 5-September-2014
mbed_official 545:5112d5ae6723 7 * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
mbed_official 545:5112d5ae6723 8 * This file contains all the peripheral register's definitions, bits
mbed_official 545:5112d5ae6723 9 * definitions and memory mapping for STM32L1xx devices.
mbed_official 545:5112d5ae6723 10 *
mbed_official 545:5112d5ae6723 11 * This file contains:
mbed_official 545:5112d5ae6723 12 * - Data structures and the address mapping for all peripherals
mbed_official 545:5112d5ae6723 13 * - Peripheral's registers declarations and bits definition
mbed_official 545:5112d5ae6723 14 * - Macros to access peripheral’s registers hardware
mbed_official 545:5112d5ae6723 15 *
mbed_official 545:5112d5ae6723 16 ******************************************************************************
mbed_official 545:5112d5ae6723 17 * @attention
mbed_official 545:5112d5ae6723 18 *
mbed_official 545:5112d5ae6723 19 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
mbed_official 545:5112d5ae6723 20 *
mbed_official 545:5112d5ae6723 21 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 545:5112d5ae6723 22 * are permitted provided that the following conditions are met:
mbed_official 545:5112d5ae6723 23 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 545:5112d5ae6723 24 * this list of conditions and the following disclaimer.
mbed_official 545:5112d5ae6723 25 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 545:5112d5ae6723 26 * this list of conditions and the following disclaimer in the documentation
mbed_official 545:5112d5ae6723 27 * and/or other materials provided with the distribution.
mbed_official 545:5112d5ae6723 28 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 545:5112d5ae6723 29 * may be used to endorse or promote products derived from this software
mbed_official 545:5112d5ae6723 30 * without specific prior written permission.
mbed_official 545:5112d5ae6723 31 *
mbed_official 545:5112d5ae6723 32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 545:5112d5ae6723 33 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 545:5112d5ae6723 34 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 545:5112d5ae6723 35 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 545:5112d5ae6723 36 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 545:5112d5ae6723 37 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 545:5112d5ae6723 38 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 545:5112d5ae6723 39 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 545:5112d5ae6723 40 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 545:5112d5ae6723 41 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 545:5112d5ae6723 42 *
mbed_official 545:5112d5ae6723 43 ******************************************************************************
mbed_official 545:5112d5ae6723 44 */
mbed_official 545:5112d5ae6723 45
mbed_official 545:5112d5ae6723 46 /** @addtogroup CMSIS
mbed_official 545:5112d5ae6723 47 * @{
mbed_official 545:5112d5ae6723 48 */
mbed_official 545:5112d5ae6723 49
mbed_official 545:5112d5ae6723 50 /** @addtogroup stm32l151xc
mbed_official 545:5112d5ae6723 51 * @{
mbed_official 545:5112d5ae6723 52 */
mbed_official 545:5112d5ae6723 53
mbed_official 545:5112d5ae6723 54 #ifndef __STM32L151xC_H
mbed_official 545:5112d5ae6723 55 #define __STM32L151xC_H
mbed_official 545:5112d5ae6723 56
mbed_official 545:5112d5ae6723 57 #ifdef __cplusplus
mbed_official 545:5112d5ae6723 58 extern "C" {
mbed_official 545:5112d5ae6723 59 #endif
mbed_official 545:5112d5ae6723 60
mbed_official 545:5112d5ae6723 61
mbed_official 545:5112d5ae6723 62 /** @addtogroup Configuration_section_for_CMSIS
mbed_official 545:5112d5ae6723 63 * @{
mbed_official 545:5112d5ae6723 64 */
mbed_official 545:5112d5ae6723 65 /**
mbed_official 545:5112d5ae6723 66 * @brief Configuration of the Cortex-M3 Processor and Core Peripherals
mbed_official 545:5112d5ae6723 67 */
mbed_official 545:5112d5ae6723 68 #define __CM3_REV 0x200 /*!< Cortex-M3 Revision r2p0 */
mbed_official 545:5112d5ae6723 69 #define __MPU_PRESENT 1 /*!< STM32L1xx provides MPU */
mbed_official 545:5112d5ae6723 70 #define __NVIC_PRIO_BITS 4 /*!< STM32L1xx uses 4 Bits for the Priority Levels */
mbed_official 545:5112d5ae6723 71 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
mbed_official 545:5112d5ae6723 72
mbed_official 545:5112d5ae6723 73 /**
mbed_official 545:5112d5ae6723 74 * @}
mbed_official 545:5112d5ae6723 75 */
mbed_official 545:5112d5ae6723 76
mbed_official 545:5112d5ae6723 77 /** @addtogroup Peripheral_interrupt_number_definition
mbed_official 545:5112d5ae6723 78 * @{
mbed_official 545:5112d5ae6723 79 */
mbed_official 545:5112d5ae6723 80
mbed_official 545:5112d5ae6723 81 /**
mbed_official 545:5112d5ae6723 82 * @brief STM32L1xx Interrupt Number Definition, according to the selected device
mbed_official 545:5112d5ae6723 83 * in @ref Library_configuration_section
mbed_official 545:5112d5ae6723 84 */
mbed_official 545:5112d5ae6723 85
mbed_official 545:5112d5ae6723 86 /*!< Interrupt Number Definition */
mbed_official 545:5112d5ae6723 87 typedef enum
mbed_official 545:5112d5ae6723 88 {
mbed_official 545:5112d5ae6723 89 /****** Cortex-M3 Processor Exceptions Numbers ******************************************************/
mbed_official 545:5112d5ae6723 90 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
mbed_official 545:5112d5ae6723 91 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
mbed_official 545:5112d5ae6723 92 BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
mbed_official 545:5112d5ae6723 93 UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
mbed_official 545:5112d5ae6723 94 SVC_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
mbed_official 545:5112d5ae6723 95 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
mbed_official 545:5112d5ae6723 96 PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
mbed_official 545:5112d5ae6723 97 SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
mbed_official 545:5112d5ae6723 98
mbed_official 545:5112d5ae6723 99 /****** STM32L specific Interrupt Numbers ***********************************************************/
mbed_official 545:5112d5ae6723 100 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
mbed_official 545:5112d5ae6723 101 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
mbed_official 545:5112d5ae6723 102 TAMPER_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
mbed_official 545:5112d5ae6723 103 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup Timer through EXTI Line Interrupt */
mbed_official 545:5112d5ae6723 104 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
mbed_official 545:5112d5ae6723 105 RCC_IRQn = 5, /*!< RCC global Interrupt */
mbed_official 545:5112d5ae6723 106 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
mbed_official 545:5112d5ae6723 107 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
mbed_official 545:5112d5ae6723 108 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
mbed_official 545:5112d5ae6723 109 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
mbed_official 545:5112d5ae6723 110 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
mbed_official 545:5112d5ae6723 111 DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */
mbed_official 545:5112d5ae6723 112 DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */
mbed_official 545:5112d5ae6723 113 DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */
mbed_official 545:5112d5ae6723 114 DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */
mbed_official 545:5112d5ae6723 115 DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */
mbed_official 545:5112d5ae6723 116 DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */
mbed_official 545:5112d5ae6723 117 DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */
mbed_official 545:5112d5ae6723 118 ADC1_IRQn = 18, /*!< ADC1 global Interrupt */
mbed_official 545:5112d5ae6723 119 USB_HP_IRQn = 19, /*!< USB High Priority Interrupt */
mbed_official 545:5112d5ae6723 120 USB_LP_IRQn = 20, /*!< USB Low Priority Interrupt */
mbed_official 545:5112d5ae6723 121 DAC_IRQn = 21, /*!< DAC Interrupt */
mbed_official 545:5112d5ae6723 122 COMP_IRQn = 22, /*!< Comparator through EXTI Line Interrupt */
mbed_official 545:5112d5ae6723 123 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
mbed_official 545:5112d5ae6723 124 TIM9_IRQn = 25, /*!< TIM9 global Interrupt */
mbed_official 545:5112d5ae6723 125 TIM10_IRQn = 26, /*!< TIM10 global Interrupt */
mbed_official 545:5112d5ae6723 126 TIM11_IRQn = 27, /*!< TIM11 global Interrupt */
mbed_official 545:5112d5ae6723 127 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
mbed_official 545:5112d5ae6723 128 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
mbed_official 545:5112d5ae6723 129 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
mbed_official 545:5112d5ae6723 130 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
mbed_official 545:5112d5ae6723 131 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
mbed_official 545:5112d5ae6723 132 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
mbed_official 545:5112d5ae6723 133 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
mbed_official 545:5112d5ae6723 134 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
mbed_official 545:5112d5ae6723 135 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
mbed_official 545:5112d5ae6723 136 USART1_IRQn = 37, /*!< USART1 global Interrupt */
mbed_official 545:5112d5ae6723 137 USART2_IRQn = 38, /*!< USART2 global Interrupt */
mbed_official 545:5112d5ae6723 138 USART3_IRQn = 39, /*!< USART3 global Interrupt */
mbed_official 545:5112d5ae6723 139 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
mbed_official 545:5112d5ae6723 140 RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
mbed_official 545:5112d5ae6723 141 USB_FS_WKUP_IRQn = 42, /*!< USB FS WakeUp from suspend through EXTI Line Interrupt */
mbed_official 545:5112d5ae6723 142 TIM6_IRQn = 43, /*!< TIM6 global Interrupt */
mbed_official 545:5112d5ae6723 143 TIM7_IRQn = 44, /*!< TIM7 global Interrupt */
mbed_official 545:5112d5ae6723 144 TIM5_IRQn = 46, /*!< TIM5 global Interrupt */
mbed_official 545:5112d5ae6723 145 SPI3_IRQn = 47, /*!< SPI3 global Interrupt */
mbed_official 545:5112d5ae6723 146 DMA2_Channel1_IRQn = 50, /*!< DMA2 Channel 1 global Interrupt */
mbed_official 545:5112d5ae6723 147 DMA2_Channel2_IRQn = 51, /*!< DMA2 Channel 2 global Interrupt */
mbed_official 545:5112d5ae6723 148 DMA2_Channel3_IRQn = 52, /*!< DMA2 Channel 3 global Interrupt */
mbed_official 545:5112d5ae6723 149 DMA2_Channel4_IRQn = 53, /*!< DMA2 Channel 4 global Interrupt */
mbed_official 545:5112d5ae6723 150 DMA2_Channel5_IRQn = 54, /*!< DMA2 Channel 5 global Interrupt */
mbed_official 545:5112d5ae6723 151 COMP_ACQ_IRQn = 56 /*!< Comparator Channel Acquisition global Interrupt */
mbed_official 545:5112d5ae6723 152 } IRQn_Type;
mbed_official 545:5112d5ae6723 153
mbed_official 545:5112d5ae6723 154 /**
mbed_official 545:5112d5ae6723 155 * @}
mbed_official 545:5112d5ae6723 156 */
mbed_official 545:5112d5ae6723 157
mbed_official 545:5112d5ae6723 158 #include "core_cm3.h"
mbed_official 545:5112d5ae6723 159 #include "system_stm32l1xx.h"
mbed_official 545:5112d5ae6723 160 #include <stdint.h>
mbed_official 545:5112d5ae6723 161
mbed_official 545:5112d5ae6723 162 /** @addtogroup Peripheral_registers_structures
mbed_official 545:5112d5ae6723 163 * @{
mbed_official 545:5112d5ae6723 164 */
mbed_official 545:5112d5ae6723 165
mbed_official 545:5112d5ae6723 166 /**
mbed_official 545:5112d5ae6723 167 * @brief Analog to Digital Converter
mbed_official 545:5112d5ae6723 168 */
mbed_official 545:5112d5ae6723 169
mbed_official 545:5112d5ae6723 170 typedef struct
mbed_official 545:5112d5ae6723 171 {
mbed_official 545:5112d5ae6723 172 __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
mbed_official 545:5112d5ae6723 173 __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
mbed_official 545:5112d5ae6723 174 __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
mbed_official 545:5112d5ae6723 175 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
mbed_official 545:5112d5ae6723 176 __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
mbed_official 545:5112d5ae6723 177 __IO uint32_t SMPR3; /*!< ADC sample time register 3, Address offset: 0x14 */
mbed_official 545:5112d5ae6723 178 __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x18 */
mbed_official 545:5112d5ae6723 179 __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x1C */
mbed_official 545:5112d5ae6723 180 __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x20 */
mbed_official 545:5112d5ae6723 181 __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x24 */
mbed_official 545:5112d5ae6723 182 __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x28 */
mbed_official 545:5112d5ae6723 183 __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x2C */
mbed_official 545:5112d5ae6723 184 __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */
mbed_official 545:5112d5ae6723 185 __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */
mbed_official 545:5112d5ae6723 186 __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */
mbed_official 545:5112d5ae6723 187 __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */
mbed_official 545:5112d5ae6723 188 __IO uint32_t SQR5; /*!< ADC regular sequence register 5, Address offset: 0x40 */
mbed_official 545:5112d5ae6723 189 __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x44 */
mbed_official 545:5112d5ae6723 190 __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x48 */
mbed_official 545:5112d5ae6723 191 __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x4C */
mbed_official 545:5112d5ae6723 192 __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x50 */
mbed_official 545:5112d5ae6723 193 __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x54 */
mbed_official 545:5112d5ae6723 194 __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x58 */
mbed_official 545:5112d5ae6723 195 uint32_t RESERVED; /*!< Reserved, Address offset: 0x5C */
mbed_official 545:5112d5ae6723 196 } ADC_TypeDef;
mbed_official 545:5112d5ae6723 197
mbed_official 545:5112d5ae6723 198 typedef struct
mbed_official 545:5112d5ae6723 199 {
mbed_official 545:5112d5ae6723 200 __IO uint32_t CSR; /*!< ADC common status register, Address offset: ADC1 base address + 0x300 */
mbed_official 545:5112d5ae6723 201 __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
mbed_official 545:5112d5ae6723 202 } ADC_Common_TypeDef;
mbed_official 545:5112d5ae6723 203
mbed_official 545:5112d5ae6723 204 /**
mbed_official 545:5112d5ae6723 205 * @brief Comparator
mbed_official 545:5112d5ae6723 206 */
mbed_official 545:5112d5ae6723 207
mbed_official 545:5112d5ae6723 208 typedef struct
mbed_official 545:5112d5ae6723 209 {
mbed_official 545:5112d5ae6723 210 __IO uint32_t CSR; /*!< COMP comparator control and status register, Address offset: 0x00 */
mbed_official 545:5112d5ae6723 211 } COMP_TypeDef;
mbed_official 545:5112d5ae6723 212
mbed_official 545:5112d5ae6723 213 /**
mbed_official 545:5112d5ae6723 214 * @brief CRC calculation unit
mbed_official 545:5112d5ae6723 215 */
mbed_official 545:5112d5ae6723 216
mbed_official 545:5112d5ae6723 217 typedef struct
mbed_official 545:5112d5ae6723 218 {
mbed_official 545:5112d5ae6723 219 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
mbed_official 545:5112d5ae6723 220 __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
mbed_official 545:5112d5ae6723 221 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
mbed_official 545:5112d5ae6723 222 } CRC_TypeDef;
mbed_official 545:5112d5ae6723 223
mbed_official 545:5112d5ae6723 224 /**
mbed_official 545:5112d5ae6723 225 * @brief Digital to Analog Converter
mbed_official 545:5112d5ae6723 226 */
mbed_official 545:5112d5ae6723 227
mbed_official 545:5112d5ae6723 228 typedef struct
mbed_official 545:5112d5ae6723 229 {
mbed_official 545:5112d5ae6723 230 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
mbed_official 545:5112d5ae6723 231 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
mbed_official 545:5112d5ae6723 232 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
mbed_official 545:5112d5ae6723 233 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
mbed_official 545:5112d5ae6723 234 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
mbed_official 545:5112d5ae6723 235 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
mbed_official 545:5112d5ae6723 236 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
mbed_official 545:5112d5ae6723 237 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
mbed_official 545:5112d5ae6723 238 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
mbed_official 545:5112d5ae6723 239 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
mbed_official 545:5112d5ae6723 240 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
mbed_official 545:5112d5ae6723 241 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
mbed_official 545:5112d5ae6723 242 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
mbed_official 545:5112d5ae6723 243 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
mbed_official 545:5112d5ae6723 244 } DAC_TypeDef;
mbed_official 545:5112d5ae6723 245
mbed_official 545:5112d5ae6723 246 /**
mbed_official 545:5112d5ae6723 247 * @brief Debug MCU
mbed_official 545:5112d5ae6723 248 */
mbed_official 545:5112d5ae6723 249
mbed_official 545:5112d5ae6723 250 typedef struct
mbed_official 545:5112d5ae6723 251 {
mbed_official 545:5112d5ae6723 252 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
mbed_official 545:5112d5ae6723 253 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
mbed_official 545:5112d5ae6723 254 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
mbed_official 545:5112d5ae6723 255 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
mbed_official 545:5112d5ae6723 256 }DBGMCU_TypeDef;
mbed_official 545:5112d5ae6723 257
mbed_official 545:5112d5ae6723 258 /**
mbed_official 545:5112d5ae6723 259 * @brief DMA Controller
mbed_official 545:5112d5ae6723 260 */
mbed_official 545:5112d5ae6723 261
mbed_official 545:5112d5ae6723 262 typedef struct
mbed_official 545:5112d5ae6723 263 {
mbed_official 545:5112d5ae6723 264 __IO uint32_t CCR; /*!< DMA channel x configuration register */
mbed_official 545:5112d5ae6723 265 __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
mbed_official 545:5112d5ae6723 266 __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
mbed_official 545:5112d5ae6723 267 __IO uint32_t CMAR; /*!< DMA channel x memory address register */
mbed_official 545:5112d5ae6723 268 } DMA_Channel_TypeDef;
mbed_official 545:5112d5ae6723 269
mbed_official 545:5112d5ae6723 270 typedef struct
mbed_official 545:5112d5ae6723 271 {
mbed_official 545:5112d5ae6723 272 __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
mbed_official 545:5112d5ae6723 273 __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
mbed_official 545:5112d5ae6723 274 } DMA_TypeDef;
mbed_official 545:5112d5ae6723 275
mbed_official 545:5112d5ae6723 276 /**
mbed_official 545:5112d5ae6723 277 * @brief External Interrupt/Event Controller
mbed_official 545:5112d5ae6723 278 */
mbed_official 545:5112d5ae6723 279
mbed_official 545:5112d5ae6723 280 typedef struct
mbed_official 545:5112d5ae6723 281 {
mbed_official 545:5112d5ae6723 282 __IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */
mbed_official 545:5112d5ae6723 283 __IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */
mbed_official 545:5112d5ae6723 284 __IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */
mbed_official 545:5112d5ae6723 285 __IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */
mbed_official 545:5112d5ae6723 286 __IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */
mbed_official 545:5112d5ae6723 287 __IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */
mbed_official 545:5112d5ae6723 288 } EXTI_TypeDef;
mbed_official 545:5112d5ae6723 289
mbed_official 545:5112d5ae6723 290 /**
mbed_official 545:5112d5ae6723 291 * @brief FLASH Registers
mbed_official 545:5112d5ae6723 292 */
mbed_official 545:5112d5ae6723 293 typedef struct
mbed_official 545:5112d5ae6723 294 {
mbed_official 545:5112d5ae6723 295 __IO uint32_t ACR; /*!< Access control register, Address offset: 0x00 */
mbed_official 545:5112d5ae6723 296 __IO uint32_t PECR; /*!< Program/erase control register, Address offset: 0x04 */
mbed_official 545:5112d5ae6723 297 __IO uint32_t PDKEYR; /*!< Power down key register, Address offset: 0x08 */
mbed_official 545:5112d5ae6723 298 __IO uint32_t PEKEYR; /*!< Program/erase key register, Address offset: 0x0c */
mbed_official 545:5112d5ae6723 299 __IO uint32_t PRGKEYR; /*!< Program memory key register, Address offset: 0x10 */
mbed_official 545:5112d5ae6723 300 __IO uint32_t OPTKEYR; /*!< Option byte key register, Address offset: 0x14 */
mbed_official 545:5112d5ae6723 301 __IO uint32_t SR; /*!< Status register, Address offset: 0x18 */
mbed_official 545:5112d5ae6723 302 __IO uint32_t OBR; /*!< Option byte register, Address offset: 0x1c */
mbed_official 545:5112d5ae6723 303 __IO uint32_t WRPR1; /*!< Write protection register 1, Address offset: 0x20 */
mbed_official 545:5112d5ae6723 304 uint32_t RESERVED[23]; /*!< Reserved, Address offset: 0x24 */
mbed_official 545:5112d5ae6723 305 __IO uint32_t WRPR2; /*!< Write protection register 2, Address offset: 0x80 */
mbed_official 545:5112d5ae6723 306 } FLASH_TypeDef;
mbed_official 545:5112d5ae6723 307
mbed_official 545:5112d5ae6723 308 /**
mbed_official 545:5112d5ae6723 309 * @brief Option Bytes Registers
mbed_official 545:5112d5ae6723 310 */
mbed_official 545:5112d5ae6723 311 typedef struct
mbed_official 545:5112d5ae6723 312 {
mbed_official 545:5112d5ae6723 313 __IO uint32_t RDP; /*!< Read protection register, Address offset: 0x00 */
mbed_official 545:5112d5ae6723 314 __IO uint32_t USER; /*!< user register, Address offset: 0x04 */
mbed_official 545:5112d5ae6723 315 __IO uint32_t WRP01; /*!< write protection register 0 1, Address offset: 0x08 */
mbed_official 545:5112d5ae6723 316 __IO uint32_t WRP23; /*!< write protection register 2 3, Address offset: 0x0C */
mbed_official 545:5112d5ae6723 317 __IO uint32_t WRP45; /*!< write protection register 4 5, Address offset: 0x10 */
mbed_official 545:5112d5ae6723 318 __IO uint32_t WRP67; /*!< write protection register 6 7, Address offset: 0x14 */
mbed_official 545:5112d5ae6723 319 } OB_TypeDef;
mbed_official 545:5112d5ae6723 320
mbed_official 545:5112d5ae6723 321 /**
mbed_official 545:5112d5ae6723 322 * @brief Operational Amplifier (OPAMP)
mbed_official 545:5112d5ae6723 323 */
mbed_official 545:5112d5ae6723 324 typedef struct
mbed_official 545:5112d5ae6723 325 {
mbed_official 545:5112d5ae6723 326 __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */
mbed_official 545:5112d5ae6723 327 __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */
mbed_official 545:5112d5ae6723 328 __IO uint32_t LPOTR; /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */
mbed_official 545:5112d5ae6723 329 } OPAMP_TypeDef;
mbed_official 545:5112d5ae6723 330
mbed_official 545:5112d5ae6723 331 /**
mbed_official 545:5112d5ae6723 332 * @brief General Purpose IO
mbed_official 545:5112d5ae6723 333 */
mbed_official 545:5112d5ae6723 334
mbed_official 545:5112d5ae6723 335 typedef struct
mbed_official 545:5112d5ae6723 336 {
mbed_official 545:5112d5ae6723 337 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
mbed_official 545:5112d5ae6723 338 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
mbed_official 545:5112d5ae6723 339 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
mbed_official 545:5112d5ae6723 340 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
mbed_official 545:5112d5ae6723 341 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
mbed_official 545:5112d5ae6723 342 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
mbed_official 545:5112d5ae6723 343 __IO uint32_t BSRR; /*!< GPIO port bit set/reset registerBSRR, Address offset: 0x18 */
mbed_official 545:5112d5ae6723 344 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
mbed_official 545:5112d5ae6723 345 __IO uint32_t AFR[2]; /*!< GPIO alternate function register, Address offset: 0x20-0x24 */
mbed_official 545:5112d5ae6723 346 __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
mbed_official 545:5112d5ae6723 347 } GPIO_TypeDef;
mbed_official 545:5112d5ae6723 348
mbed_official 545:5112d5ae6723 349 /**
mbed_official 545:5112d5ae6723 350 * @brief SysTem Configuration
mbed_official 545:5112d5ae6723 351 */
mbed_official 545:5112d5ae6723 352
mbed_official 545:5112d5ae6723 353 typedef struct
mbed_official 545:5112d5ae6723 354 {
mbed_official 545:5112d5ae6723 355 __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
mbed_official 545:5112d5ae6723 356 __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
mbed_official 545:5112d5ae6723 357 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
mbed_official 545:5112d5ae6723 358 } SYSCFG_TypeDef;
mbed_official 545:5112d5ae6723 359
mbed_official 545:5112d5ae6723 360 /**
mbed_official 545:5112d5ae6723 361 * @brief Inter-integrated Circuit Interface
mbed_official 545:5112d5ae6723 362 */
mbed_official 545:5112d5ae6723 363
mbed_official 545:5112d5ae6723 364 typedef struct
mbed_official 545:5112d5ae6723 365 {
mbed_official 545:5112d5ae6723 366 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
mbed_official 545:5112d5ae6723 367 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
mbed_official 545:5112d5ae6723 368 __IO uint32_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
mbed_official 545:5112d5ae6723 369 __IO uint32_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
mbed_official 545:5112d5ae6723 370 __IO uint32_t DR; /*!< I2C Data register, Address offset: 0x10 */
mbed_official 545:5112d5ae6723 371 __IO uint32_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
mbed_official 545:5112d5ae6723 372 __IO uint32_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
mbed_official 545:5112d5ae6723 373 __IO uint32_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
mbed_official 545:5112d5ae6723 374 __IO uint32_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
mbed_official 545:5112d5ae6723 375 } I2C_TypeDef;
mbed_official 545:5112d5ae6723 376
mbed_official 545:5112d5ae6723 377 /**
mbed_official 545:5112d5ae6723 378 * @brief Independent WATCHDOG
mbed_official 545:5112d5ae6723 379 */
mbed_official 545:5112d5ae6723 380
mbed_official 545:5112d5ae6723 381 typedef struct
mbed_official 545:5112d5ae6723 382 {
mbed_official 545:5112d5ae6723 383 __IO uint32_t KR; /*!< Key register, Address offset: 0x00 */
mbed_official 545:5112d5ae6723 384 __IO uint32_t PR; /*!< Prescaler register, Address offset: 0x04 */
mbed_official 545:5112d5ae6723 385 __IO uint32_t RLR; /*!< Reload register, Address offset: 0x08 */
mbed_official 545:5112d5ae6723 386 __IO uint32_t SR; /*!< Status register, Address offset: 0x0C */
mbed_official 545:5112d5ae6723 387 } IWDG_TypeDef;
mbed_official 545:5112d5ae6723 388
mbed_official 545:5112d5ae6723 389 /**
mbed_official 545:5112d5ae6723 390 * @brief Power Control
mbed_official 545:5112d5ae6723 391 */
mbed_official 545:5112d5ae6723 392
mbed_official 545:5112d5ae6723 393 typedef struct
mbed_official 545:5112d5ae6723 394 {
mbed_official 545:5112d5ae6723 395 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
mbed_official 545:5112d5ae6723 396 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
mbed_official 545:5112d5ae6723 397 } PWR_TypeDef;
mbed_official 545:5112d5ae6723 398
mbed_official 545:5112d5ae6723 399 /**
mbed_official 545:5112d5ae6723 400 * @brief Reset and Clock Control
mbed_official 545:5112d5ae6723 401 */
mbed_official 545:5112d5ae6723 402
mbed_official 545:5112d5ae6723 403 typedef struct
mbed_official 545:5112d5ae6723 404 {
mbed_official 545:5112d5ae6723 405 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
mbed_official 545:5112d5ae6723 406 __IO uint32_t ICSCR; /*!< RCC Internal clock sources calibration register, Address offset: 0x04 */
mbed_official 545:5112d5ae6723 407 __IO uint32_t CFGR; /*!< RCC Clock configuration register, Address offset: 0x08 */
mbed_official 545:5112d5ae6723 408 __IO uint32_t CIR; /*!< RCC Clock interrupt register, Address offset: 0x0C */
mbed_official 545:5112d5ae6723 409 __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x10 */
mbed_official 545:5112d5ae6723 410 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x14 */
mbed_official 545:5112d5ae6723 411 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x18 */
mbed_official 545:5112d5ae6723 412 __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock enable register, Address offset: 0x1C */
mbed_official 545:5112d5ae6723 413 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x20 */
mbed_official 545:5112d5ae6723 414 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x24 */
mbed_official 545:5112d5ae6723 415 __IO uint32_t AHBLPENR; /*!< RCC AHB peripheral clock enable in low power mode register, Address offset: 0x28 */
mbed_official 545:5112d5ae6723 416 __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x2C */
mbed_official 545:5112d5ae6723 417 __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x30 */
mbed_official 545:5112d5ae6723 418 __IO uint32_t CSR; /*!< RCC Control/status register, Address offset: 0x34 */
mbed_official 545:5112d5ae6723 419 } RCC_TypeDef;
mbed_official 545:5112d5ae6723 420
mbed_official 545:5112d5ae6723 421 /**
mbed_official 545:5112d5ae6723 422 * @brief Routing Interface
mbed_official 545:5112d5ae6723 423 */
mbed_official 545:5112d5ae6723 424
mbed_official 545:5112d5ae6723 425 typedef struct
mbed_official 545:5112d5ae6723 426 {
mbed_official 545:5112d5ae6723 427 __IO uint32_t ICR; /*!< RI input capture register, Address offset: 0x00 */
mbed_official 545:5112d5ae6723 428 __IO uint32_t ASCR1; /*!< RI analog switches control register, Address offset: 0x04 */
mbed_official 545:5112d5ae6723 429 __IO uint32_t ASCR2; /*!< RI analog switch control register 2, Address offset: 0x08 */
mbed_official 545:5112d5ae6723 430 __IO uint32_t HYSCR1; /*!< RI hysteresis control register, Address offset: 0x0C */
mbed_official 545:5112d5ae6723 431 __IO uint32_t HYSCR2; /*!< RI Hysteresis control register, Address offset: 0x10 */
mbed_official 545:5112d5ae6723 432 __IO uint32_t HYSCR3; /*!< RI Hysteresis control register, Address offset: 0x14 */
mbed_official 545:5112d5ae6723 433 uint32_t RESERVED1; /*!< Reserved, 0x18 */
mbed_official 545:5112d5ae6723 434 __IO uint32_t ASMR1; /*!< RI Analog switch mode register 1, Address offset: 0x1C */
mbed_official 545:5112d5ae6723 435 __IO uint32_t CMR1; /*!< RI Channel mask register 1, Address offset: 0x20 */
mbed_official 545:5112d5ae6723 436 __IO uint32_t CICR1; /*!< RI Channel Iden for capture register 1, Address offset: 0x24 */
mbed_official 545:5112d5ae6723 437 __IO uint32_t ASMR2; /*!< RI Analog switch mode register 2, Address offset: 0x28 */
mbed_official 545:5112d5ae6723 438 __IO uint32_t CMR2; /*!< RI Channel mask register 2, Address offset: 0x2C */
mbed_official 545:5112d5ae6723 439 __IO uint32_t CICR2; /*!< RI Channel Iden for capture register 2, Address offset: 0x30 */
mbed_official 545:5112d5ae6723 440 __IO uint32_t ASMR3; /*!< RI Analog switch mode register 3, Address offset: 0x34 */
mbed_official 545:5112d5ae6723 441 __IO uint32_t CMR3; /*!< RI Channel mask register 3, Address offset: 0x38 */
mbed_official 545:5112d5ae6723 442 __IO uint32_t CICR3; /*!< RI Channel Iden for capture register 3, Address offset: 0x3C */
mbed_official 545:5112d5ae6723 443 } RI_TypeDef;
mbed_official 545:5112d5ae6723 444
mbed_official 545:5112d5ae6723 445 /**
mbed_official 545:5112d5ae6723 446 * @brief Real-Time Clock
mbed_official 545:5112d5ae6723 447 */
mbed_official 545:5112d5ae6723 448 typedef struct
mbed_official 545:5112d5ae6723 449 {
mbed_official 545:5112d5ae6723 450 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
mbed_official 545:5112d5ae6723 451 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
mbed_official 545:5112d5ae6723 452 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
mbed_official 545:5112d5ae6723 453 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
mbed_official 545:5112d5ae6723 454 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
mbed_official 545:5112d5ae6723 455 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
mbed_official 545:5112d5ae6723 456 __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
mbed_official 545:5112d5ae6723 457 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
mbed_official 545:5112d5ae6723 458 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
mbed_official 545:5112d5ae6723 459 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
mbed_official 545:5112d5ae6723 460 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
mbed_official 545:5112d5ae6723 461 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
mbed_official 545:5112d5ae6723 462 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
mbed_official 545:5112d5ae6723 463 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
mbed_official 545:5112d5ae6723 464 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
mbed_official 545:5112d5ae6723 465 __IO uint32_t CALR; /*!< RRTC calibration register, Address offset: 0x3C */
mbed_official 545:5112d5ae6723 466 __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
mbed_official 545:5112d5ae6723 467 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
mbed_official 545:5112d5ae6723 468 __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */
mbed_official 545:5112d5ae6723 469 uint32_t RESERVED7; /*!< Reserved, 0x4C */
mbed_official 545:5112d5ae6723 470 __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
mbed_official 545:5112d5ae6723 471 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
mbed_official 545:5112d5ae6723 472 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
mbed_official 545:5112d5ae6723 473 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
mbed_official 545:5112d5ae6723 474 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
mbed_official 545:5112d5ae6723 475 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
mbed_official 545:5112d5ae6723 476 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
mbed_official 545:5112d5ae6723 477 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
mbed_official 545:5112d5ae6723 478 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
mbed_official 545:5112d5ae6723 479 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
mbed_official 545:5112d5ae6723 480 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
mbed_official 545:5112d5ae6723 481 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
mbed_official 545:5112d5ae6723 482 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
mbed_official 545:5112d5ae6723 483 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
mbed_official 545:5112d5ae6723 484 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
mbed_official 545:5112d5ae6723 485 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
mbed_official 545:5112d5ae6723 486 __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
mbed_official 545:5112d5ae6723 487 __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
mbed_official 545:5112d5ae6723 488 __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
mbed_official 545:5112d5ae6723 489 __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
mbed_official 545:5112d5ae6723 490 __IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */
mbed_official 545:5112d5ae6723 491 __IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */
mbed_official 545:5112d5ae6723 492 __IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */
mbed_official 545:5112d5ae6723 493 __IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */
mbed_official 545:5112d5ae6723 494 __IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */
mbed_official 545:5112d5ae6723 495 __IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */
mbed_official 545:5112d5ae6723 496 __IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */
mbed_official 545:5112d5ae6723 497 __IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */
mbed_official 545:5112d5ae6723 498 __IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */
mbed_official 545:5112d5ae6723 499 __IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */
mbed_official 545:5112d5ae6723 500 __IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */
mbed_official 545:5112d5ae6723 501 __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */
mbed_official 545:5112d5ae6723 502 } RTC_TypeDef;
mbed_official 545:5112d5ae6723 503
mbed_official 545:5112d5ae6723 504 /**
mbed_official 545:5112d5ae6723 505 * @brief Serial Peripheral Interface
mbed_official 545:5112d5ae6723 506 */
mbed_official 545:5112d5ae6723 507
mbed_official 545:5112d5ae6723 508 typedef struct
mbed_official 545:5112d5ae6723 509 {
mbed_official 545:5112d5ae6723 510 __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */
mbed_official 545:5112d5ae6723 511 __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
mbed_official 545:5112d5ae6723 512 __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
mbed_official 545:5112d5ae6723 513 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
mbed_official 545:5112d5ae6723 514 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
mbed_official 545:5112d5ae6723 515 __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */
mbed_official 545:5112d5ae6723 516 __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */
mbed_official 545:5112d5ae6723 517 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
mbed_official 545:5112d5ae6723 518 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
mbed_official 545:5112d5ae6723 519 } SPI_TypeDef;
mbed_official 545:5112d5ae6723 520
mbed_official 545:5112d5ae6723 521 /**
mbed_official 545:5112d5ae6723 522 * @brief TIM
mbed_official 545:5112d5ae6723 523 */
mbed_official 545:5112d5ae6723 524 typedef struct
mbed_official 545:5112d5ae6723 525 {
mbed_official 545:5112d5ae6723 526 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
mbed_official 545:5112d5ae6723 527 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
mbed_official 545:5112d5ae6723 528 __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */
mbed_official 545:5112d5ae6723 529 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
mbed_official 545:5112d5ae6723 530 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
mbed_official 545:5112d5ae6723 531 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
mbed_official 545:5112d5ae6723 532 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
mbed_official 545:5112d5ae6723 533 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
mbed_official 545:5112d5ae6723 534 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
mbed_official 545:5112d5ae6723 535 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
mbed_official 545:5112d5ae6723 536 __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
mbed_official 545:5112d5ae6723 537 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
mbed_official 545:5112d5ae6723 538 uint32_t RESERVED12; /*!< Reserved, 0x30 */
mbed_official 545:5112d5ae6723 539 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
mbed_official 545:5112d5ae6723 540 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
mbed_official 545:5112d5ae6723 541 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
mbed_official 545:5112d5ae6723 542 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
mbed_official 545:5112d5ae6723 543 uint32_t RESERVED17; /*!< Reserved, 0x44 */
mbed_official 545:5112d5ae6723 544 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
mbed_official 545:5112d5ae6723 545 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
mbed_official 545:5112d5ae6723 546 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
mbed_official 545:5112d5ae6723 547 } TIM_TypeDef;
mbed_official 545:5112d5ae6723 548 /**
mbed_official 545:5112d5ae6723 549 * @brief Universal Synchronous Asynchronous Receiver Transmitter
mbed_official 545:5112d5ae6723 550 */
mbed_official 545:5112d5ae6723 551
mbed_official 545:5112d5ae6723 552 typedef struct
mbed_official 545:5112d5ae6723 553 {
mbed_official 545:5112d5ae6723 554 __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
mbed_official 545:5112d5ae6723 555 __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
mbed_official 545:5112d5ae6723 556 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
mbed_official 545:5112d5ae6723 557 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
mbed_official 545:5112d5ae6723 558 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
mbed_official 545:5112d5ae6723 559 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
mbed_official 545:5112d5ae6723 560 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
mbed_official 545:5112d5ae6723 561 } USART_TypeDef;
mbed_official 545:5112d5ae6723 562
mbed_official 545:5112d5ae6723 563 /**
mbed_official 545:5112d5ae6723 564 * @brief Universal Serial Bus Full Speed Device
mbed_official 545:5112d5ae6723 565 */
mbed_official 545:5112d5ae6723 566
mbed_official 545:5112d5ae6723 567 typedef struct
mbed_official 545:5112d5ae6723 568 {
mbed_official 545:5112d5ae6723 569 __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */
mbed_official 545:5112d5ae6723 570 __IO uint16_t RESERVED0; /*!< Reserved */
mbed_official 545:5112d5ae6723 571 __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */
mbed_official 545:5112d5ae6723 572 __IO uint16_t RESERVED1; /*!< Reserved */
mbed_official 545:5112d5ae6723 573 __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */
mbed_official 545:5112d5ae6723 574 __IO uint16_t RESERVED2; /*!< Reserved */
mbed_official 545:5112d5ae6723 575 __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */
mbed_official 545:5112d5ae6723 576 __IO uint16_t RESERVED3; /*!< Reserved */
mbed_official 545:5112d5ae6723 577 __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */
mbed_official 545:5112d5ae6723 578 __IO uint16_t RESERVED4; /*!< Reserved */
mbed_official 545:5112d5ae6723 579 __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */
mbed_official 545:5112d5ae6723 580 __IO uint16_t RESERVED5; /*!< Reserved */
mbed_official 545:5112d5ae6723 581 __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */
mbed_official 545:5112d5ae6723 582 __IO uint16_t RESERVED6; /*!< Reserved */
mbed_official 545:5112d5ae6723 583 __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */
mbed_official 545:5112d5ae6723 584 __IO uint16_t RESERVED7[17]; /*!< Reserved */
mbed_official 545:5112d5ae6723 585 __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */
mbed_official 545:5112d5ae6723 586 __IO uint16_t RESERVED8; /*!< Reserved */
mbed_official 545:5112d5ae6723 587 __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */
mbed_official 545:5112d5ae6723 588 __IO uint16_t RESERVED9; /*!< Reserved */
mbed_official 545:5112d5ae6723 589 __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */
mbed_official 545:5112d5ae6723 590 __IO uint16_t RESERVEDA; /*!< Reserved */
mbed_official 545:5112d5ae6723 591 __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */
mbed_official 545:5112d5ae6723 592 __IO uint16_t RESERVEDB; /*!< Reserved */
mbed_official 545:5112d5ae6723 593 __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */
mbed_official 545:5112d5ae6723 594 __IO uint16_t RESERVEDC; /*!< Reserved */
mbed_official 545:5112d5ae6723 595 } USB_TypeDef;
mbed_official 545:5112d5ae6723 596
mbed_official 545:5112d5ae6723 597 /**
mbed_official 545:5112d5ae6723 598 * @brief Window WATCHDOG
mbed_official 545:5112d5ae6723 599 */
mbed_official 545:5112d5ae6723 600 typedef struct
mbed_official 545:5112d5ae6723 601 {
mbed_official 545:5112d5ae6723 602 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
mbed_official 545:5112d5ae6723 603 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
mbed_official 545:5112d5ae6723 604 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
mbed_official 545:5112d5ae6723 605 } WWDG_TypeDef;
mbed_official 545:5112d5ae6723 606
mbed_official 545:5112d5ae6723 607 /**
mbed_official 545:5112d5ae6723 608 * @brief Universal Serial Bus Full Speed Device
mbed_official 545:5112d5ae6723 609 */
mbed_official 545:5112d5ae6723 610 /**
mbed_official 545:5112d5ae6723 611 * @}
mbed_official 545:5112d5ae6723 612 */
mbed_official 545:5112d5ae6723 613
mbed_official 545:5112d5ae6723 614 /** @addtogroup Peripheral_memory_map
mbed_official 545:5112d5ae6723 615 * @{
mbed_official 545:5112d5ae6723 616 */
mbed_official 545:5112d5ae6723 617
mbed_official 545:5112d5ae6723 618 #define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
mbed_official 545:5112d5ae6723 619 #define FLASH_EEPROM_BASE ((uint32_t)(FLASH_BASE + 0x80000)) /*!< FLASH EEPROM base address in the alias region */
mbed_official 545:5112d5ae6723 620 #define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
mbed_official 545:5112d5ae6723 621 #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
mbed_official 545:5112d5ae6723 622 #define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */
mbed_official 545:5112d5ae6723 623 #define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
mbed_official 545:5112d5ae6723 624 #define FLASH_END ((uint32_t)0x0803FFFF) /*!< Program end FLASH address for Cat3 */
mbed_official 545:5112d5ae6723 625 #define FLASH_EEPROM_END ((uint32_t)0x08081FFF) /*!< FLASH EEPROM end address (8KB) */
mbed_official 545:5112d5ae6723 626
mbed_official 545:5112d5ae6723 627 /*!< Peripheral memory map */
mbed_official 545:5112d5ae6723 628 #define APB1PERIPH_BASE PERIPH_BASE
mbed_official 545:5112d5ae6723 629 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000)
mbed_official 545:5112d5ae6723 630 #define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000)
mbed_official 545:5112d5ae6723 631
mbed_official 545:5112d5ae6723 632 /*!< APB1 peripherals */
mbed_official 545:5112d5ae6723 633 #define TIM2_BASE (APB1PERIPH_BASE + 0x00000000)
mbed_official 545:5112d5ae6723 634 #define TIM3_BASE (APB1PERIPH_BASE + 0x00000400)
mbed_official 545:5112d5ae6723 635 #define TIM4_BASE (APB1PERIPH_BASE + 0x00000800)
mbed_official 545:5112d5ae6723 636 #define TIM5_BASE (APB1PERIPH_BASE + 0x00000C00)
mbed_official 545:5112d5ae6723 637 #define TIM6_BASE (APB1PERIPH_BASE + 0x00001000)
mbed_official 545:5112d5ae6723 638 #define TIM7_BASE (APB1PERIPH_BASE + 0x00001400)
mbed_official 545:5112d5ae6723 639 #define RTC_BASE (APB1PERIPH_BASE + 0x00002800)
mbed_official 545:5112d5ae6723 640 #define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00)
mbed_official 545:5112d5ae6723 641 #define IWDG_BASE (APB1PERIPH_BASE + 0x00003000)
mbed_official 545:5112d5ae6723 642 #define SPI2_BASE (APB1PERIPH_BASE + 0x00003800)
mbed_official 545:5112d5ae6723 643 #define SPI3_BASE (APB1PERIPH_BASE + 0x00003C00)
mbed_official 545:5112d5ae6723 644 #define USART2_BASE (APB1PERIPH_BASE + 0x00004400)
mbed_official 545:5112d5ae6723 645 #define USART3_BASE (APB1PERIPH_BASE + 0x00004800)
mbed_official 545:5112d5ae6723 646 #define I2C1_BASE (APB1PERIPH_BASE + 0x00005400)
mbed_official 545:5112d5ae6723 647 #define I2C2_BASE (APB1PERIPH_BASE + 0x00005800)
mbed_official 545:5112d5ae6723 648
mbed_official 545:5112d5ae6723 649 /* USB device FS */
mbed_official 545:5112d5ae6723 650 #define USB_BASE (APB1PERIPH_BASE + 0x00005C00) /*!< USB_IP Peripheral Registers base address */
mbed_official 545:5112d5ae6723 651 #define USB_PMAADDR (APB1PERIPH_BASE + 0x00006000) /*!< USB_IP Packet Memory Area base address */
mbed_official 545:5112d5ae6723 652
mbed_official 545:5112d5ae6723 653 /* USB device FS SRAM */
mbed_official 545:5112d5ae6723 654 #define PWR_BASE (APB1PERIPH_BASE + 0x00007000)
mbed_official 545:5112d5ae6723 655 #define DAC_BASE (APB1PERIPH_BASE + 0x00007400)
mbed_official 545:5112d5ae6723 656 #define COMP_BASE (APB1PERIPH_BASE + 0x00007C00)
mbed_official 545:5112d5ae6723 657 #define RI_BASE (APB1PERIPH_BASE + 0x00007C04)
mbed_official 545:5112d5ae6723 658 #define OPAMP_BASE (APB1PERIPH_BASE + 0x00007C5C)
mbed_official 545:5112d5ae6723 659
mbed_official 545:5112d5ae6723 660 /*!< APB2 peripherals */
mbed_official 545:5112d5ae6723 661 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x00000000)
mbed_official 545:5112d5ae6723 662 #define EXTI_BASE (APB2PERIPH_BASE + 0x00000400)
mbed_official 545:5112d5ae6723 663 #define TIM9_BASE (APB2PERIPH_BASE + 0x00000800)
mbed_official 545:5112d5ae6723 664 #define TIM10_BASE (APB2PERIPH_BASE + 0x00000C00)
mbed_official 545:5112d5ae6723 665 #define TIM11_BASE (APB2PERIPH_BASE + 0x00001000)
mbed_official 545:5112d5ae6723 666 #define ADC1_BASE (APB2PERIPH_BASE + 0x00002400)
mbed_official 545:5112d5ae6723 667 #define ADC_BASE (APB2PERIPH_BASE + 0x00002700)
mbed_official 545:5112d5ae6723 668 #define SPI1_BASE (APB2PERIPH_BASE + 0x00003000)
mbed_official 545:5112d5ae6723 669 #define USART1_BASE (APB2PERIPH_BASE + 0x00003800)
mbed_official 545:5112d5ae6723 670
mbed_official 545:5112d5ae6723 671 /*!< AHB peripherals */
mbed_official 545:5112d5ae6723 672 #define GPIOA_BASE (AHBPERIPH_BASE + 0x00000000)
mbed_official 545:5112d5ae6723 673 #define GPIOB_BASE (AHBPERIPH_BASE + 0x00000400)
mbed_official 545:5112d5ae6723 674 #define GPIOC_BASE (AHBPERIPH_BASE + 0x00000800)
mbed_official 545:5112d5ae6723 675 #define GPIOD_BASE (AHBPERIPH_BASE + 0x00000C00)
mbed_official 545:5112d5ae6723 676 #define GPIOE_BASE (AHBPERIPH_BASE + 0x00001000)
mbed_official 545:5112d5ae6723 677 #define GPIOH_BASE (AHBPERIPH_BASE + 0x00001400)
mbed_official 545:5112d5ae6723 678 #define CRC_BASE (AHBPERIPH_BASE + 0x00003000)
mbed_official 545:5112d5ae6723 679 #define RCC_BASE (AHBPERIPH_BASE + 0x00003800)
mbed_official 545:5112d5ae6723 680 #define FLASH_R_BASE (AHBPERIPH_BASE + 0x00003C00) /*!< FLASH registers base address */
mbed_official 545:5112d5ae6723 681 #define OB_BASE ((uint32_t)0x1FF80000) /*!< FLASH Option Bytes base address */
mbed_official 545:5112d5ae6723 682 #define DMA1_BASE (AHBPERIPH_BASE + 0x00006000)
mbed_official 545:5112d5ae6723 683 #define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008)
mbed_official 545:5112d5ae6723 684 #define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001C)
mbed_official 545:5112d5ae6723 685 #define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030)
mbed_official 545:5112d5ae6723 686 #define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044)
mbed_official 545:5112d5ae6723 687 #define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058)
mbed_official 545:5112d5ae6723 688 #define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006C)
mbed_official 545:5112d5ae6723 689 #define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080)
mbed_official 545:5112d5ae6723 690 #define DMA2_BASE (AHBPERIPH_BASE + 0x00006400)
mbed_official 545:5112d5ae6723 691 #define DMA2_Channel1_BASE (DMA2_BASE + 0x00000008)
mbed_official 545:5112d5ae6723 692 #define DMA2_Channel2_BASE (DMA2_BASE + 0x0000001C)
mbed_official 545:5112d5ae6723 693 #define DMA2_Channel3_BASE (DMA2_BASE + 0x00000030)
mbed_official 545:5112d5ae6723 694 #define DMA2_Channel4_BASE (DMA2_BASE + 0x00000044)
mbed_official 545:5112d5ae6723 695 #define DMA2_Channel5_BASE (DMA2_BASE + 0x00000058)
mbed_official 545:5112d5ae6723 696 #define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
mbed_official 545:5112d5ae6723 697
mbed_official 545:5112d5ae6723 698 /**
mbed_official 545:5112d5ae6723 699 * @}
mbed_official 545:5112d5ae6723 700 */
mbed_official 545:5112d5ae6723 701
mbed_official 545:5112d5ae6723 702 /** @addtogroup Peripheral_declaration
mbed_official 545:5112d5ae6723 703 * @{
mbed_official 545:5112d5ae6723 704 */
mbed_official 545:5112d5ae6723 705
mbed_official 545:5112d5ae6723 706 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
mbed_official 545:5112d5ae6723 707 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
mbed_official 545:5112d5ae6723 708 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
mbed_official 545:5112d5ae6723 709 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
mbed_official 545:5112d5ae6723 710 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
mbed_official 545:5112d5ae6723 711 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
mbed_official 545:5112d5ae6723 712 #define RTC ((RTC_TypeDef *) RTC_BASE)
mbed_official 545:5112d5ae6723 713 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
mbed_official 545:5112d5ae6723 714 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
mbed_official 545:5112d5ae6723 715 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
mbed_official 545:5112d5ae6723 716 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
mbed_official 545:5112d5ae6723 717 #define USART2 ((USART_TypeDef *) USART2_BASE)
mbed_official 545:5112d5ae6723 718 #define USART3 ((USART_TypeDef *) USART3_BASE)
mbed_official 545:5112d5ae6723 719 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
mbed_official 545:5112d5ae6723 720 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
mbed_official 545:5112d5ae6723 721 /* USB device FS */
mbed_official 545:5112d5ae6723 722 #define USB ((USB_TypeDef *) USB_BASE)
mbed_official 545:5112d5ae6723 723 /* USB device FS SRAM */
mbed_official 545:5112d5ae6723 724 #define PWR ((PWR_TypeDef *) PWR_BASE)
mbed_official 545:5112d5ae6723 725 #define DAC ((DAC_TypeDef *) DAC_BASE)
mbed_official 545:5112d5ae6723 726 #define COMP ((COMP_TypeDef *) COMP_BASE)
mbed_official 545:5112d5ae6723 727 #define COMP1 ((COMP_TypeDef *) COMP_BASE)
mbed_official 545:5112d5ae6723 728 #define COMP2 ((COMP_TypeDef *) (COMP_BASE + 0x00000001))
mbed_official 545:5112d5ae6723 729 #define RI ((RI_TypeDef *) RI_BASE)
mbed_official 545:5112d5ae6723 730 #define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
mbed_official 545:5112d5ae6723 731 #define OPAMP1 ((OPAMP_TypeDef *) OPAMP_BASE)
mbed_official 545:5112d5ae6723 732 #define OPAMP2 ((OPAMP_TypeDef *) (OPAMP_BASE + 0x00000001))
mbed_official 545:5112d5ae6723 733 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
mbed_official 545:5112d5ae6723 734 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
mbed_official 545:5112d5ae6723 735 #define TIM9 ((TIM_TypeDef *) TIM9_BASE)
mbed_official 545:5112d5ae6723 736 #define TIM10 ((TIM_TypeDef *) TIM10_BASE)
mbed_official 545:5112d5ae6723 737 #define TIM11 ((TIM_TypeDef *) TIM11_BASE)
mbed_official 545:5112d5ae6723 738 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
mbed_official 545:5112d5ae6723 739 #define ADC ((ADC_Common_TypeDef *) ADC_BASE)
mbed_official 545:5112d5ae6723 740 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
mbed_official 545:5112d5ae6723 741 #define USART1 ((USART_TypeDef *) USART1_BASE)
mbed_official 545:5112d5ae6723 742 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
mbed_official 545:5112d5ae6723 743 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
mbed_official 545:5112d5ae6723 744 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
mbed_official 545:5112d5ae6723 745 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
mbed_official 545:5112d5ae6723 746 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
mbed_official 545:5112d5ae6723 747 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
mbed_official 545:5112d5ae6723 748 #define CRC ((CRC_TypeDef *) CRC_BASE)
mbed_official 545:5112d5ae6723 749 #define RCC ((RCC_TypeDef *) RCC_BASE)
mbed_official 545:5112d5ae6723 750 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
mbed_official 545:5112d5ae6723 751 #define OB ((OB_TypeDef *) OB_BASE)
mbed_official 545:5112d5ae6723 752 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
mbed_official 545:5112d5ae6723 753 #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
mbed_official 545:5112d5ae6723 754 #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
mbed_official 545:5112d5ae6723 755 #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
mbed_official 545:5112d5ae6723 756 #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
mbed_official 545:5112d5ae6723 757 #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
mbed_official 545:5112d5ae6723 758 #define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
mbed_official 545:5112d5ae6723 759 #define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
mbed_official 545:5112d5ae6723 760 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
mbed_official 545:5112d5ae6723 761 #define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
mbed_official 545:5112d5ae6723 762 #define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
mbed_official 545:5112d5ae6723 763 #define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
mbed_official 545:5112d5ae6723 764 #define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
mbed_official 545:5112d5ae6723 765 #define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
mbed_official 545:5112d5ae6723 766 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
mbed_official 545:5112d5ae6723 767
mbed_official 545:5112d5ae6723 768 /**
mbed_official 545:5112d5ae6723 769 * @}
mbed_official 545:5112d5ae6723 770 */
mbed_official 545:5112d5ae6723 771
mbed_official 545:5112d5ae6723 772 /** @addtogroup Exported_constants
mbed_official 545:5112d5ae6723 773 * @{
mbed_official 545:5112d5ae6723 774 */
mbed_official 545:5112d5ae6723 775
mbed_official 545:5112d5ae6723 776 /** @addtogroup Peripheral_Registers_Bits_Definition
mbed_official 545:5112d5ae6723 777 * @{
mbed_official 545:5112d5ae6723 778 */
mbed_official 545:5112d5ae6723 779
mbed_official 545:5112d5ae6723 780 /******************************************************************************/
mbed_official 545:5112d5ae6723 781 /* Peripheral Registers Bits Definition */
mbed_official 545:5112d5ae6723 782 /******************************************************************************/
mbed_official 545:5112d5ae6723 783 /******************************************************************************/
mbed_official 545:5112d5ae6723 784 /* */
mbed_official 545:5112d5ae6723 785 /* Analog to Digital Converter (ADC) */
mbed_official 545:5112d5ae6723 786 /* */
mbed_official 545:5112d5ae6723 787 /******************************************************************************/
mbed_official 545:5112d5ae6723 788
mbed_official 545:5112d5ae6723 789 /******************** Bit definition for ADC_SR register ********************/
mbed_official 545:5112d5ae6723 790 #define ADC_SR_AWD ((uint32_t)0x00000001) /*!< Analog watchdog flag */
mbed_official 545:5112d5ae6723 791 #define ADC_SR_EOC ((uint32_t)0x00000002) /*!< End of conversion */
mbed_official 545:5112d5ae6723 792 #define ADC_SR_JEOC ((uint32_t)0x00000004) /*!< Injected channel end of conversion */
mbed_official 545:5112d5ae6723 793 #define ADC_SR_JSTRT ((uint32_t)0x00000008) /*!< Injected channel Start flag */
mbed_official 545:5112d5ae6723 794 #define ADC_SR_STRT ((uint32_t)0x00000010) /*!< Regular channel Start flag */
mbed_official 545:5112d5ae6723 795 #define ADC_SR_OVR ((uint32_t)0x00000020) /*!< Overrun flag */
mbed_official 545:5112d5ae6723 796 #define ADC_SR_ADONS ((uint32_t)0x00000040) /*!< ADC ON status */
mbed_official 545:5112d5ae6723 797 #define ADC_SR_RCNR ((uint32_t)0x00000100) /*!< Regular channel not ready flag */
mbed_official 545:5112d5ae6723 798 #define ADC_SR_JCNR ((uint32_t)0x00000200) /*!< Injected channel not ready flag */
mbed_official 545:5112d5ae6723 799
mbed_official 545:5112d5ae6723 800 /******************* Bit definition for ADC_CR1 register ********************/
mbed_official 545:5112d5ae6723 801 #define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
mbed_official 545:5112d5ae6723 802 #define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 803 #define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 804 #define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 805 #define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!< Bit 3 */
mbed_official 545:5112d5ae6723 806 #define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!< Bit 4 */
mbed_official 545:5112d5ae6723 807
mbed_official 545:5112d5ae6723 808 #define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!< Interrupt enable for EOC */
mbed_official 545:5112d5ae6723 809 #define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!< Analog Watchdog interrupt enable */
mbed_official 545:5112d5ae6723 810 #define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!< Interrupt enable for injected channels */
mbed_official 545:5112d5ae6723 811 #define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!< Scan mode */
mbed_official 545:5112d5ae6723 812 #define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!< Enable the watchdog on a single channel in scan mode */
mbed_official 545:5112d5ae6723 813 #define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!< Automatic injected group conversion */
mbed_official 545:5112d5ae6723 814 #define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!< Discontinuous mode on regular channels */
mbed_official 545:5112d5ae6723 815 #define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!< Discontinuous mode on injected channels */
mbed_official 545:5112d5ae6723 816
mbed_official 545:5112d5ae6723 817 #define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!< DISCNUM[2:0] bits (Discontinuous mode channel count) */
mbed_official 545:5112d5ae6723 818 #define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 819 #define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 820 #define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 821
mbed_official 545:5112d5ae6723 822 #define ADC_CR1_PDD ((uint32_t)0x00010000) /*!< Power Down during Delay phase */
mbed_official 545:5112d5ae6723 823 #define ADC_CR1_PDI ((uint32_t)0x00020000) /*!< Power Down during Idle phase */
mbed_official 545:5112d5ae6723 824
mbed_official 545:5112d5ae6723 825 #define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!< Analog watchdog enable on injected channels */
mbed_official 545:5112d5ae6723 826 #define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!< Analog watchdog enable on regular channels */
mbed_official 545:5112d5ae6723 827
mbed_official 545:5112d5ae6723 828 #define ADC_CR1_RES ((uint32_t)0x03000000) /*!< RES[1:0] bits (Resolution) */
mbed_official 545:5112d5ae6723 829 #define ADC_CR1_RES_0 ((uint32_t)0x01000000) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 830 #define ADC_CR1_RES_1 ((uint32_t)0x02000000) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 831
mbed_official 545:5112d5ae6723 832 #define ADC_CR1_OVRIE ((uint32_t)0x04000000) /*!< Overrun interrupt enable */
mbed_official 545:5112d5ae6723 833
mbed_official 545:5112d5ae6723 834 /******************* Bit definition for ADC_CR2 register ********************/
mbed_official 545:5112d5ae6723 835 #define ADC_CR2_ADON ((uint32_t)0x00000001) /*!< A/D Converter ON / OFF */
mbed_official 545:5112d5ae6723 836 #define ADC_CR2_CONT ((uint32_t)0x00000002) /*!< Continuous Conversion */
mbed_official 545:5112d5ae6723 837 #define ADC_CR2_CFG ((uint32_t)0x00000004) /*!< ADC Configuration */
mbed_official 545:5112d5ae6723 838
mbed_official 545:5112d5ae6723 839 #define ADC_CR2_DELS ((uint32_t)0x00000070) /*!< DELS[2:0] bits (Delay selection) */
mbed_official 545:5112d5ae6723 840 #define ADC_CR2_DELS_0 ((uint32_t)0x00000010) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 841 #define ADC_CR2_DELS_1 ((uint32_t)0x00000020) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 842 #define ADC_CR2_DELS_2 ((uint32_t)0x00000040) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 843
mbed_official 545:5112d5ae6723 844 #define ADC_CR2_DMA ((uint32_t)0x00000100) /*!< Direct Memory access mode */
mbed_official 545:5112d5ae6723 845 #define ADC_CR2_DDS ((uint32_t)0x00000200) /*!< DMA disable selection (Single ADC) */
mbed_official 545:5112d5ae6723 846 #define ADC_CR2_EOCS ((uint32_t)0x00000400) /*!< End of conversion selection */
mbed_official 545:5112d5ae6723 847 #define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!< Data Alignment */
mbed_official 545:5112d5ae6723 848
mbed_official 545:5112d5ae6723 849 #define ADC_CR2_JEXTSEL ((uint32_t)0x000F0000) /*!< JEXTSEL[3:0] bits (External event select for injected group) */
mbed_official 545:5112d5ae6723 850 #define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00010000) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 851 #define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00020000) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 852 #define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00040000) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 853 #define ADC_CR2_JEXTSEL_3 ((uint32_t)0x00080000) /*!< Bit 3 */
mbed_official 545:5112d5ae6723 854
mbed_official 545:5112d5ae6723 855 #define ADC_CR2_JEXTEN ((uint32_t)0x00300000) /*!< JEXTEN[1:0] bits (External Trigger Conversion mode for injected channels) */
mbed_official 545:5112d5ae6723 856 #define ADC_CR2_JEXTEN_0 ((uint32_t)0x00100000) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 857 #define ADC_CR2_JEXTEN_1 ((uint32_t)0x00200000) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 858
mbed_official 545:5112d5ae6723 859 #define ADC_CR2_JSWSTART ((uint32_t)0x00400000) /*!< Start Conversion of injected channels */
mbed_official 545:5112d5ae6723 860
mbed_official 545:5112d5ae6723 861 #define ADC_CR2_EXTSEL ((uint32_t)0x0F000000) /*!< EXTSEL[3:0] bits (External Event Select for regular group) */
mbed_official 545:5112d5ae6723 862 #define ADC_CR2_EXTSEL_0 ((uint32_t)0x01000000) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 863 #define ADC_CR2_EXTSEL_1 ((uint32_t)0x02000000) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 864 #define ADC_CR2_EXTSEL_2 ((uint32_t)0x04000000) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 865 #define ADC_CR2_EXTSEL_3 ((uint32_t)0x08000000) /*!< Bit 3 */
mbed_official 545:5112d5ae6723 866
mbed_official 545:5112d5ae6723 867 #define ADC_CR2_EXTEN ((uint32_t)0x30000000) /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */
mbed_official 545:5112d5ae6723 868 #define ADC_CR2_EXTEN_0 ((uint32_t)0x10000000) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 869 #define ADC_CR2_EXTEN_1 ((uint32_t)0x20000000) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 870
mbed_official 545:5112d5ae6723 871 #define ADC_CR2_SWSTART ((uint32_t)0x40000000) /*!< Start Conversion of regular channels */
mbed_official 545:5112d5ae6723 872
mbed_official 545:5112d5ae6723 873 /****************** Bit definition for ADC_SMPR1 register *******************/
mbed_official 545:5112d5ae6723 874 #define ADC_SMPR1_SMP20 ((uint32_t)0x00000007) /*!< SMP20[2:0] bits (Channel 20 Sample time selection) */
mbed_official 545:5112d5ae6723 875 #define ADC_SMPR1_SMP20_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 876 #define ADC_SMPR1_SMP20_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 877 #define ADC_SMPR1_SMP20_2 ((uint32_t)0x00000004) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 878
mbed_official 545:5112d5ae6723 879 #define ADC_SMPR1_SMP21 ((uint32_t)0x00000038) /*!< SMP21[2:0] bits (Channel 21 Sample time selection) */
mbed_official 545:5112d5ae6723 880 #define ADC_SMPR1_SMP21_0 ((uint32_t)0x00000008) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 881 #define ADC_SMPR1_SMP21_1 ((uint32_t)0x00000010) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 882 #define ADC_SMPR1_SMP21_2 ((uint32_t)0x00000020) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 883
mbed_official 545:5112d5ae6723 884 #define ADC_SMPR1_SMP22 ((uint32_t)0x000001C0) /*!< SMP22[2:0] bits (Channel 22 Sample time selection) */
mbed_official 545:5112d5ae6723 885 #define ADC_SMPR1_SMP22_0 ((uint32_t)0x00000040) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 886 #define ADC_SMPR1_SMP22_1 ((uint32_t)0x00000080) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 887 #define ADC_SMPR1_SMP22_2 ((uint32_t)0x00000100) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 888
mbed_official 545:5112d5ae6723 889 #define ADC_SMPR1_SMP23 ((uint32_t)0x00000E00) /*!< SMP23[2:0] bits (Channel 23 Sample time selection) */
mbed_official 545:5112d5ae6723 890 #define ADC_SMPR1_SMP23_0 ((uint32_t)0x00000200) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 891 #define ADC_SMPR1_SMP23_1 ((uint32_t)0x00000400) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 892 #define ADC_SMPR1_SMP23_2 ((uint32_t)0x00000800) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 893
mbed_official 545:5112d5ae6723 894 #define ADC_SMPR1_SMP24 ((uint32_t)0x00007000) /*!< SMP24[2:0] bits (Channel 24 Sample time selection) */
mbed_official 545:5112d5ae6723 895 #define ADC_SMPR1_SMP24_0 ((uint32_t)0x00001000) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 896 #define ADC_SMPR1_SMP24_1 ((uint32_t)0x00002000) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 897 #define ADC_SMPR1_SMP24_2 ((uint32_t)0x00004000) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 898
mbed_official 545:5112d5ae6723 899 #define ADC_SMPR1_SMP25 ((uint32_t)0x00038000) /*!< SMP25[2:0] bits (Channel 25 Sample time selection) */
mbed_official 545:5112d5ae6723 900 #define ADC_SMPR1_SMP25_0 ((uint32_t)0x00008000) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 901 #define ADC_SMPR1_SMP25_1 ((uint32_t)0x00010000) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 902 #define ADC_SMPR1_SMP25_2 ((uint32_t)0x00020000) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 903
mbed_official 545:5112d5ae6723 904 #define ADC_SMPR1_SMP26 ((uint32_t)0x001C0000) /*!< SMP26[2:0] bits (Channel 26 Sample time selection) */
mbed_official 545:5112d5ae6723 905 #define ADC_SMPR1_SMP26_0 ((uint32_t)0x00040000) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 906 #define ADC_SMPR1_SMP26_1 ((uint32_t)0x00080000) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 907 #define ADC_SMPR1_SMP26_2 ((uint32_t)0x00100000) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 908
mbed_official 545:5112d5ae6723 909 #define ADC_SMPR1_SMP27 ((uint32_t)0x00E00000) /*!< SMP27[2:0] bits (Channel 27 Sample time selection) */
mbed_official 545:5112d5ae6723 910 #define ADC_SMPR1_SMP27_0 ((uint32_t)0x00200000) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 911 #define ADC_SMPR1_SMP27_1 ((uint32_t)0x00400000) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 912 #define ADC_SMPR1_SMP27_2 ((uint32_t)0x00800000) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 913
mbed_official 545:5112d5ae6723 914 #define ADC_SMPR1_SMP28 ((uint32_t)0x07000000) /*!< SMP28[2:0] bits (Channel 28 Sample time selection) */
mbed_official 545:5112d5ae6723 915 #define ADC_SMPR1_SMP28_0 ((uint32_t)0x01000000) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 916 #define ADC_SMPR1_SMP28_1 ((uint32_t)0x02000000) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 917 #define ADC_SMPR1_SMP28_2 ((uint32_t)0x04000000) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 918
mbed_official 545:5112d5ae6723 919 #define ADC_SMPR1_SMP29 ((uint32_t)0x38000000) /*!< SMP29[2:0] bits (Channel 29 Sample time selection) */
mbed_official 545:5112d5ae6723 920 #define ADC_SMPR1_SMP29_0 ((uint32_t)0x08000000) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 921 #define ADC_SMPR1_SMP29_1 ((uint32_t)0x10000000) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 922 #define ADC_SMPR1_SMP29_2 ((uint32_t)0x20000000) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 923
mbed_official 545:5112d5ae6723 924 /****************** Bit definition for ADC_SMPR2 register *******************/
mbed_official 545:5112d5ae6723 925 #define ADC_SMPR2_SMP10 ((uint32_t)0x00000007) /*!< SMP10[2:0] bits (Channel 10 Sample time selection) */
mbed_official 545:5112d5ae6723 926 #define ADC_SMPR2_SMP10_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 927 #define ADC_SMPR2_SMP10_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 928 #define ADC_SMPR2_SMP10_2 ((uint32_t)0x00000004) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 929
mbed_official 545:5112d5ae6723 930 #define ADC_SMPR2_SMP11 ((uint32_t)0x00000038) /*!< SMP11[2:0] bits (Channel 11 Sample time selection) */
mbed_official 545:5112d5ae6723 931 #define ADC_SMPR2_SMP11_0 ((uint32_t)0x00000008) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 932 #define ADC_SMPR2_SMP11_1 ((uint32_t)0x00000010) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 933 #define ADC_SMPR2_SMP11_2 ((uint32_t)0x00000020) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 934
mbed_official 545:5112d5ae6723 935 #define ADC_SMPR2_SMP12 ((uint32_t)0x000001C0) /*!< SMP12[2:0] bits (Channel 12 Sample time selection) */
mbed_official 545:5112d5ae6723 936 #define ADC_SMPR2_SMP12_0 ((uint32_t)0x00000040) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 937 #define ADC_SMPR2_SMP12_1 ((uint32_t)0x00000080) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 938 #define ADC_SMPR2_SMP12_2 ((uint32_t)0x00000100) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 939
mbed_official 545:5112d5ae6723 940 #define ADC_SMPR2_SMP13 ((uint32_t)0x00000E00) /*!< SMP13[2:0] bits (Channel 13 Sample time selection) */
mbed_official 545:5112d5ae6723 941 #define ADC_SMPR2_SMP13_0 ((uint32_t)0x00000200) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 942 #define ADC_SMPR2_SMP13_1 ((uint32_t)0x00000400) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 943 #define ADC_SMPR2_SMP13_2 ((uint32_t)0x00000800) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 944
mbed_official 545:5112d5ae6723 945 #define ADC_SMPR2_SMP14 ((uint32_t)0x00007000) /*!< SMP14[2:0] bits (Channel 14 Sample time selection) */
mbed_official 545:5112d5ae6723 946 #define ADC_SMPR2_SMP14_0 ((uint32_t)0x00001000) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 947 #define ADC_SMPR2_SMP14_1 ((uint32_t)0x00002000) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 948 #define ADC_SMPR2_SMP14_2 ((uint32_t)0x00004000) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 949
mbed_official 545:5112d5ae6723 950 #define ADC_SMPR2_SMP15 ((uint32_t)0x00038000) /*!< SMP15[2:0] bits (Channel 5 Sample time selection) */
mbed_official 545:5112d5ae6723 951 #define ADC_SMPR2_SMP15_0 ((uint32_t)0x00008000) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 952 #define ADC_SMPR2_SMP15_1 ((uint32_t)0x00010000) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 953 #define ADC_SMPR2_SMP15_2 ((uint32_t)0x00020000) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 954
mbed_official 545:5112d5ae6723 955 #define ADC_SMPR2_SMP16 ((uint32_t)0x001C0000) /*!< SMP16[2:0] bits (Channel 16 Sample time selection) */
mbed_official 545:5112d5ae6723 956 #define ADC_SMPR2_SMP16_0 ((uint32_t)0x00040000) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 957 #define ADC_SMPR2_SMP16_1 ((uint32_t)0x00080000) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 958 #define ADC_SMPR2_SMP16_2 ((uint32_t)0x00100000) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 959
mbed_official 545:5112d5ae6723 960 #define ADC_SMPR2_SMP17 ((uint32_t)0x00E00000) /*!< SMP17[2:0] bits (Channel 17 Sample time selection) */
mbed_official 545:5112d5ae6723 961 #define ADC_SMPR2_SMP17_0 ((uint32_t)0x00200000) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 962 #define ADC_SMPR2_SMP17_1 ((uint32_t)0x00400000) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 963 #define ADC_SMPR2_SMP17_2 ((uint32_t)0x00800000) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 964
mbed_official 545:5112d5ae6723 965 #define ADC_SMPR2_SMP18 ((uint32_t)0x07000000) /*!< SMP18[2:0] bits (Channel 18 Sample time selection) */
mbed_official 545:5112d5ae6723 966 #define ADC_SMPR2_SMP18_0 ((uint32_t)0x01000000) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 967 #define ADC_SMPR2_SMP18_1 ((uint32_t)0x02000000) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 968 #define ADC_SMPR2_SMP18_2 ((uint32_t)0x04000000) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 969
mbed_official 545:5112d5ae6723 970 #define ADC_SMPR2_SMP19 ((uint32_t)0x38000000) /*!< SMP19[2:0] bits (Channel 19 Sample time selection) */
mbed_official 545:5112d5ae6723 971 #define ADC_SMPR2_SMP19_0 ((uint32_t)0x08000000) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 972 #define ADC_SMPR2_SMP19_1 ((uint32_t)0x10000000) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 973 #define ADC_SMPR2_SMP19_2 ((uint32_t)0x20000000) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 974
mbed_official 545:5112d5ae6723 975 /****************** Bit definition for ADC_SMPR3 register *******************/
mbed_official 545:5112d5ae6723 976 #define ADC_SMPR3_SMP0 ((uint32_t)0x00000007) /*!< SMP0[2:0] bits (Channel 0 Sample time selection) */
mbed_official 545:5112d5ae6723 977 #define ADC_SMPR3_SMP0_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 978 #define ADC_SMPR3_SMP0_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 979 #define ADC_SMPR3_SMP0_2 ((uint32_t)0x00000004) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 980
mbed_official 545:5112d5ae6723 981 #define ADC_SMPR3_SMP1 ((uint32_t)0x00000038) /*!< SMP1[2:0] bits (Channel 1 Sample time selection) */
mbed_official 545:5112d5ae6723 982 #define ADC_SMPR3_SMP1_0 ((uint32_t)0x00000008) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 983 #define ADC_SMPR3_SMP1_1 ((uint32_t)0x00000010) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 984 #define ADC_SMPR3_SMP1_2 ((uint32_t)0x00000020) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 985
mbed_official 545:5112d5ae6723 986 #define ADC_SMPR3_SMP2 ((uint32_t)0x000001C0) /*!< SMP2[2:0] bits (Channel 2 Sample time selection) */
mbed_official 545:5112d5ae6723 987 #define ADC_SMPR3_SMP2_0 ((uint32_t)0x00000040) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 988 #define ADC_SMPR3_SMP2_1 ((uint32_t)0x00000080) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 989 #define ADC_SMPR3_SMP2_2 ((uint32_t)0x00000100) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 990
mbed_official 545:5112d5ae6723 991 #define ADC_SMPR3_SMP3 ((uint32_t)0x00000E00) /*!< SMP3[2:0] bits (Channel 3 Sample time selection) */
mbed_official 545:5112d5ae6723 992 #define ADC_SMPR3_SMP3_0 ((uint32_t)0x00000200) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 993 #define ADC_SMPR3_SMP3_1 ((uint32_t)0x00000400) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 994 #define ADC_SMPR3_SMP3_2 ((uint32_t)0x00000800) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 995
mbed_official 545:5112d5ae6723 996 #define ADC_SMPR3_SMP4 ((uint32_t)0x00007000) /*!< SMP4[2:0] bits (Channel 4 Sample time selection) */
mbed_official 545:5112d5ae6723 997 #define ADC_SMPR3_SMP4_0 ((uint32_t)0x00001000) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 998 #define ADC_SMPR3_SMP4_1 ((uint32_t)0x00002000) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 999 #define ADC_SMPR3_SMP4_2 ((uint32_t)0x00004000) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 1000
mbed_official 545:5112d5ae6723 1001 #define ADC_SMPR3_SMP5 ((uint32_t)0x00038000) /*!< SMP5[2:0] bits (Channel 5 Sample time selection) */
mbed_official 545:5112d5ae6723 1002 #define ADC_SMPR3_SMP5_0 ((uint32_t)0x00008000) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 1003 #define ADC_SMPR3_SMP5_1 ((uint32_t)0x00010000) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 1004 #define ADC_SMPR3_SMP5_2 ((uint32_t)0x00020000) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 1005
mbed_official 545:5112d5ae6723 1006 #define ADC_SMPR3_SMP6 ((uint32_t)0x001C0000) /*!< SMP6[2:0] bits (Channel 6 Sample time selection) */
mbed_official 545:5112d5ae6723 1007 #define ADC_SMPR3_SMP6_0 ((uint32_t)0x00040000) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 1008 #define ADC_SMPR3_SMP6_1 ((uint32_t)0x00080000) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 1009 #define ADC_SMPR3_SMP6_2 ((uint32_t)0x00100000) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 1010
mbed_official 545:5112d5ae6723 1011 #define ADC_SMPR3_SMP7 ((uint32_t)0x00E00000) /*!< SMP7[2:0] bits (Channel 7 Sample time selection) */
mbed_official 545:5112d5ae6723 1012 #define ADC_SMPR3_SMP7_0 ((uint32_t)0x00200000) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 1013 #define ADC_SMPR3_SMP7_1 ((uint32_t)0x00400000) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 1014 #define ADC_SMPR3_SMP7_2 ((uint32_t)0x00800000) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 1015
mbed_official 545:5112d5ae6723 1016 #define ADC_SMPR3_SMP8 ((uint32_t)0x07000000) /*!< SMP8[2:0] bits (Channel 8 Sample time selection) */
mbed_official 545:5112d5ae6723 1017 #define ADC_SMPR3_SMP8_0 ((uint32_t)0x01000000) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 1018 #define ADC_SMPR3_SMP8_1 ((uint32_t)0x02000000) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 1019 #define ADC_SMPR3_SMP8_2 ((uint32_t)0x04000000) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 1020
mbed_official 545:5112d5ae6723 1021 #define ADC_SMPR3_SMP9 ((uint32_t)0x38000000) /*!< SMP9[2:0] bits (Channel 9 Sample time selection) */
mbed_official 545:5112d5ae6723 1022 #define ADC_SMPR3_SMP9_0 ((uint32_t)0x08000000) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 1023 #define ADC_SMPR3_SMP9_1 ((uint32_t)0x10000000) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 1024 #define ADC_SMPR3_SMP9_2 ((uint32_t)0x20000000) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 1025
mbed_official 545:5112d5ae6723 1026 /****************** Bit definition for ADC_JOFR1 register *******************/
mbed_official 545:5112d5ae6723 1027 #define ADC_JOFR1_JOFFSET1 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 1 */
mbed_official 545:5112d5ae6723 1028
mbed_official 545:5112d5ae6723 1029 /****************** Bit definition for ADC_JOFR2 register *******************/
mbed_official 545:5112d5ae6723 1030 #define ADC_JOFR2_JOFFSET2 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 2 */
mbed_official 545:5112d5ae6723 1031
mbed_official 545:5112d5ae6723 1032 /****************** Bit definition for ADC_JOFR3 register *******************/
mbed_official 545:5112d5ae6723 1033 #define ADC_JOFR3_JOFFSET3 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 3 */
mbed_official 545:5112d5ae6723 1034
mbed_official 545:5112d5ae6723 1035 /****************** Bit definition for ADC_JOFR4 register *******************/
mbed_official 545:5112d5ae6723 1036 #define ADC_JOFR4_JOFFSET4 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 4 */
mbed_official 545:5112d5ae6723 1037
mbed_official 545:5112d5ae6723 1038 /******************* Bit definition for ADC_HTR register ********************/
mbed_official 545:5112d5ae6723 1039 #define ADC_HTR_HT ((uint32_t)0x00000FFF) /*!< Analog watchdog high threshold */
mbed_official 545:5112d5ae6723 1040
mbed_official 545:5112d5ae6723 1041 /******************* Bit definition for ADC_LTR register ********************/
mbed_official 545:5112d5ae6723 1042 #define ADC_LTR_LT ((uint32_t)0x00000FFF) /*!< Analog watchdog low threshold */
mbed_official 545:5112d5ae6723 1043
mbed_official 545:5112d5ae6723 1044 /******************* Bit definition for ADC_SQR1 register *******************/
mbed_official 545:5112d5ae6723 1045 #define ADC_SQR1_L ((uint32_t)0x01F00000) /*!< L[4:0] bits (Regular channel sequence length) */
mbed_official 545:5112d5ae6723 1046 #define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 1047 #define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 1048 #define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 1049 #define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!< Bit 3 */
mbed_official 545:5112d5ae6723 1050 #define ADC_SQR1_L_4 ((uint32_t)0x01000000) /*!< Bit 4 */
mbed_official 545:5112d5ae6723 1051
mbed_official 545:5112d5ae6723 1052 #define ADC_SQR1_SQ28 ((uint32_t)0x000F8000) /*!< SQ28[4:0] bits (25th conversion in regular sequence) */
mbed_official 545:5112d5ae6723 1053 #define ADC_SQR1_SQ28_0 ((uint32_t)0x00008000) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 1054 #define ADC_SQR1_SQ28_1 ((uint32_t)0x00010000) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 1055 #define ADC_SQR1_SQ28_2 ((uint32_t)0x00020000) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 1056 #define ADC_SQR1_SQ28_3 ((uint32_t)0x00040000) /*!< Bit 3 */
mbed_official 545:5112d5ae6723 1057 #define ADC_SQR1_SQ28_4 ((uint32_t)0x00080000) /*!< Bit 4 */
mbed_official 545:5112d5ae6723 1058
mbed_official 545:5112d5ae6723 1059 #define ADC_SQR1_SQ27 ((uint32_t)0x00007C00) /*!< SQ27[4:0] bits (27th conversion in regular sequence) */
mbed_official 545:5112d5ae6723 1060 #define ADC_SQR1_SQ27_0 ((uint32_t)0x00000400) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 1061 #define ADC_SQR1_SQ27_1 ((uint32_t)0x00000800) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 1062 #define ADC_SQR1_SQ27_2 ((uint32_t)0x00001000) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 1063 #define ADC_SQR1_SQ27_3 ((uint32_t)0x00002000) /*!< Bit 3 */
mbed_official 545:5112d5ae6723 1064 #define ADC_SQR1_SQ27_4 ((uint32_t)0x00004000) /*!< Bit 4 */
mbed_official 545:5112d5ae6723 1065
mbed_official 545:5112d5ae6723 1066 #define ADC_SQR1_SQ26 ((uint32_t)0x000003E0) /*!< SQ26[4:0] bits (26th conversion in regular sequence) */
mbed_official 545:5112d5ae6723 1067 #define ADC_SQR1_SQ26_0 ((uint32_t)0x00000020) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 1068 #define ADC_SQR1_SQ26_1 ((uint32_t)0x00000040) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 1069 #define ADC_SQR1_SQ26_2 ((uint32_t)0x00000080) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 1070 #define ADC_SQR1_SQ26_3 ((uint32_t)0x00000100) /*!< Bit 3 */
mbed_official 545:5112d5ae6723 1071 #define ADC_SQR1_SQ26_4 ((uint32_t)0x00000200) /*!< Bit 4 */
mbed_official 545:5112d5ae6723 1072
mbed_official 545:5112d5ae6723 1073 #define ADC_SQR1_SQ25 ((uint32_t)0x0000001F) /*!< SQ25[4:0] bits (25th conversion in regular sequence) */
mbed_official 545:5112d5ae6723 1074 #define ADC_SQR1_SQ25_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 1075 #define ADC_SQR1_SQ25_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 1076 #define ADC_SQR1_SQ25_2 ((uint32_t)0x00000004) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 1077 #define ADC_SQR1_SQ25_3 ((uint32_t)0x00000008) /*!< Bit 3 */
mbed_official 545:5112d5ae6723 1078 #define ADC_SQR1_SQ25_4 ((uint32_t)0x00000010) /*!< Bit 4 */
mbed_official 545:5112d5ae6723 1079
mbed_official 545:5112d5ae6723 1080 /******************* Bit definition for ADC_SQR2 register *******************/
mbed_official 545:5112d5ae6723 1081 #define ADC_SQR2_SQ19 ((uint32_t)0x0000001F) /*!< SQ19[4:0] bits (19th conversion in regular sequence) */
mbed_official 545:5112d5ae6723 1082 #define ADC_SQR2_SQ19_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 1083 #define ADC_SQR2_SQ19_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 1084 #define ADC_SQR2_SQ19_2 ((uint32_t)0x00000004) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 1085 #define ADC_SQR2_SQ19_3 ((uint32_t)0x00000008) /*!< Bit 3 */
mbed_official 545:5112d5ae6723 1086 #define ADC_SQR2_SQ19_4 ((uint32_t)0x00000010) /*!< Bit 4 */
mbed_official 545:5112d5ae6723 1087
mbed_official 545:5112d5ae6723 1088 #define ADC_SQR2_SQ20 ((uint32_t)0x000003E0) /*!< SQ20[4:0] bits (20th conversion in regular sequence) */
mbed_official 545:5112d5ae6723 1089 #define ADC_SQR2_SQ20_0 ((uint32_t)0x00000020) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 1090 #define ADC_SQR2_SQ20_1 ((uint32_t)0x00000040) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 1091 #define ADC_SQR2_SQ20_2 ((uint32_t)0x00000080) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 1092 #define ADC_SQR2_SQ20_3 ((uint32_t)0x00000100) /*!< Bit 3 */
mbed_official 545:5112d5ae6723 1093 #define ADC_SQR2_SQ20_4 ((uint32_t)0x00000200) /*!< Bit 4 */
mbed_official 545:5112d5ae6723 1094
mbed_official 545:5112d5ae6723 1095 #define ADC_SQR2_SQ21 ((uint32_t)0x00007C00) /*!< SQ21[4:0] bits (21th conversion in regular sequence) */
mbed_official 545:5112d5ae6723 1096 #define ADC_SQR2_SQ21_0 ((uint32_t)0x00000400) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 1097 #define ADC_SQR2_SQ21_1 ((uint32_t)0x00000800) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 1098 #define ADC_SQR2_SQ21_2 ((uint32_t)0x00001000) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 1099 #define ADC_SQR2_SQ21_3 ((uint32_t)0x00002000) /*!< Bit 3 */
mbed_official 545:5112d5ae6723 1100 #define ADC_SQR2_SQ21_4 ((uint32_t)0x00004000) /*!< Bit 4 */
mbed_official 545:5112d5ae6723 1101
mbed_official 545:5112d5ae6723 1102 #define ADC_SQR2_SQ22 ((uint32_t)0x000F8000) /*!< SQ22[4:0] bits (22th conversion in regular sequence) */
mbed_official 545:5112d5ae6723 1103 #define ADC_SQR2_SQ22_0 ((uint32_t)0x00008000) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 1104 #define ADC_SQR2_SQ22_1 ((uint32_t)0x00010000) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 1105 #define ADC_SQR2_SQ22_2 ((uint32_t)0x00020000) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 1106 #define ADC_SQR2_SQ22_3 ((uint32_t)0x00040000) /*!< Bit 3 */
mbed_official 545:5112d5ae6723 1107 #define ADC_SQR2_SQ22_4 ((uint32_t)0x00080000) /*!< Bit 4 */
mbed_official 545:5112d5ae6723 1108
mbed_official 545:5112d5ae6723 1109 #define ADC_SQR2_SQ23 ((uint32_t)0x01F00000) /*!< SQ23[4:0] bits (23th conversion in regular sequence) */
mbed_official 545:5112d5ae6723 1110 #define ADC_SQR2_SQ23_0 ((uint32_t)0x00100000) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 1111 #define ADC_SQR2_SQ23_1 ((uint32_t)0x00200000) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 1112 #define ADC_SQR2_SQ23_2 ((uint32_t)0x00400000) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 1113 #define ADC_SQR2_SQ23_3 ((uint32_t)0x00800000) /*!< Bit 3 */
mbed_official 545:5112d5ae6723 1114 #define ADC_SQR2_SQ23_4 ((uint32_t)0x01000000) /*!< Bit 4 */
mbed_official 545:5112d5ae6723 1115
mbed_official 545:5112d5ae6723 1116 #define ADC_SQR2_SQ24 ((uint32_t)0x3E000000) /*!< SQ24[4:0] bits (24th conversion in regular sequence) */
mbed_official 545:5112d5ae6723 1117 #define ADC_SQR2_SQ24_0 ((uint32_t)0x02000000) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 1118 #define ADC_SQR2_SQ24_1 ((uint32_t)0x04000000) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 1119 #define ADC_SQR2_SQ24_2 ((uint32_t)0x08000000) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 1120 #define ADC_SQR2_SQ24_3 ((uint32_t)0x10000000) /*!< Bit 3 */
mbed_official 545:5112d5ae6723 1121 #define ADC_SQR2_SQ24_4 ((uint32_t)0x20000000) /*!< Bit 4 */
mbed_official 545:5112d5ae6723 1122
mbed_official 545:5112d5ae6723 1123 /******************* Bit definition for ADC_SQR3 register *******************/
mbed_official 545:5112d5ae6723 1124 #define ADC_SQR3_SQ13 ((uint32_t)0x0000001F) /*!< SQ13[4:0] bits (13th conversion in regular sequence) */
mbed_official 545:5112d5ae6723 1125 #define ADC_SQR3_SQ13_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 1126 #define ADC_SQR3_SQ13_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 1127 #define ADC_SQR3_SQ13_2 ((uint32_t)0x00000004) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 1128 #define ADC_SQR3_SQ13_3 ((uint32_t)0x00000008) /*!< Bit 3 */
mbed_official 545:5112d5ae6723 1129 #define ADC_SQR3_SQ13_4 ((uint32_t)0x00000010) /*!< Bit 4 */
mbed_official 545:5112d5ae6723 1130
mbed_official 545:5112d5ae6723 1131 #define ADC_SQR3_SQ14 ((uint32_t)0x000003E0) /*!< SQ14[4:0] bits (14th conversion in regular sequence) */
mbed_official 545:5112d5ae6723 1132 #define ADC_SQR3_SQ14_0 ((uint32_t)0x00000020) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 1133 #define ADC_SQR3_SQ14_1 ((uint32_t)0x00000040) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 1134 #define ADC_SQR3_SQ14_2 ((uint32_t)0x00000080) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 1135 #define ADC_SQR3_SQ14_3 ((uint32_t)0x00000100) /*!< Bit 3 */
mbed_official 545:5112d5ae6723 1136 #define ADC_SQR3_SQ14_4 ((uint32_t)0x00000200) /*!< Bit 4 */
mbed_official 545:5112d5ae6723 1137
mbed_official 545:5112d5ae6723 1138 #define ADC_SQR3_SQ15 ((uint32_t)0x00007C00) /*!< SQ15[4:0] bits (15th conversion in regular sequence) */
mbed_official 545:5112d5ae6723 1139 #define ADC_SQR3_SQ15_0 ((uint32_t)0x00000400) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 1140 #define ADC_SQR3_SQ15_1 ((uint32_t)0x00000800) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 1141 #define ADC_SQR3_SQ15_2 ((uint32_t)0x00001000) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 1142 #define ADC_SQR3_SQ15_3 ((uint32_t)0x00002000) /*!< Bit 3 */
mbed_official 545:5112d5ae6723 1143 #define ADC_SQR3_SQ15_4 ((uint32_t)0x00004000) /*!< Bit 4 */
mbed_official 545:5112d5ae6723 1144
mbed_official 545:5112d5ae6723 1145 #define ADC_SQR3_SQ16 ((uint32_t)0x000F8000) /*!< SQ16[4:0] bits (16th conversion in regular sequence) */
mbed_official 545:5112d5ae6723 1146 #define ADC_SQR3_SQ16_0 ((uint32_t)0x00008000) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 1147 #define ADC_SQR3_SQ16_1 ((uint32_t)0x00010000) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 1148 #define ADC_SQR3_SQ16_2 ((uint32_t)0x00020000) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 1149 #define ADC_SQR3_SQ16_3 ((uint32_t)0x00040000) /*!< Bit 3 */
mbed_official 545:5112d5ae6723 1150 #define ADC_SQR3_SQ16_4 ((uint32_t)0x00080000) /*!< Bit 4 */
mbed_official 545:5112d5ae6723 1151
mbed_official 545:5112d5ae6723 1152 #define ADC_SQR3_SQ17 ((uint32_t)0x01F00000) /*!< SQ17[4:0] bits (17th conversion in regular sequence) */
mbed_official 545:5112d5ae6723 1153 #define ADC_SQR3_SQ17_0 ((uint32_t)0x00100000) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 1154 #define ADC_SQR3_SQ17_1 ((uint32_t)0x00200000) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 1155 #define ADC_SQR3_SQ17_2 ((uint32_t)0x00400000) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 1156 #define ADC_SQR3_SQ17_3 ((uint32_t)0x00800000) /*!< Bit 3 */
mbed_official 545:5112d5ae6723 1157 #define ADC_SQR3_SQ17_4 ((uint32_t)0x01000000) /*!< Bit 4 */
mbed_official 545:5112d5ae6723 1158
mbed_official 545:5112d5ae6723 1159 #define ADC_SQR3_SQ18 ((uint32_t)0x3E000000) /*!< SQ18[4:0] bits (18th conversion in regular sequence) */
mbed_official 545:5112d5ae6723 1160 #define ADC_SQR3_SQ18_0 ((uint32_t)0x02000000) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 1161 #define ADC_SQR3_SQ18_1 ((uint32_t)0x04000000) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 1162 #define ADC_SQR3_SQ18_2 ((uint32_t)0x08000000) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 1163 #define ADC_SQR3_SQ18_3 ((uint32_t)0x10000000) /*!< Bit 3 */
mbed_official 545:5112d5ae6723 1164 #define ADC_SQR3_SQ18_4 ((uint32_t)0x20000000) /*!< Bit 4 */
mbed_official 545:5112d5ae6723 1165
mbed_official 545:5112d5ae6723 1166 /******************* Bit definition for ADC_SQR4 register *******************/
mbed_official 545:5112d5ae6723 1167 #define ADC_SQR4_SQ7 ((uint32_t)0x0000001F) /*!< SQ7[4:0] bits (7th conversion in regular sequence) */
mbed_official 545:5112d5ae6723 1168 #define ADC_SQR4_SQ7_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 1169 #define ADC_SQR4_SQ7_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 1170 #define ADC_SQR4_SQ7_2 ((uint32_t)0x00000004) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 1171 #define ADC_SQR4_SQ7_3 ((uint32_t)0x00000008) /*!< Bit 3 */
mbed_official 545:5112d5ae6723 1172 #define ADC_SQR4_SQ7_4 ((uint32_t)0x00000010) /*!< Bit 4 */
mbed_official 545:5112d5ae6723 1173
mbed_official 545:5112d5ae6723 1174 #define ADC_SQR4_SQ8 ((uint32_t)0x000003E0) /*!< SQ8[4:0] bits (8th conversion in regular sequence) */
mbed_official 545:5112d5ae6723 1175 #define ADC_SQR4_SQ8_0 ((uint32_t)0x00000020) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 1176 #define ADC_SQR4_SQ8_1 ((uint32_t)0x00000040) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 1177 #define ADC_SQR4_SQ8_2 ((uint32_t)0x00000080) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 1178 #define ADC_SQR4_SQ8_3 ((uint32_t)0x00000100) /*!< Bit 3 */
mbed_official 545:5112d5ae6723 1179 #define ADC_SQR4_SQ8_4 ((uint32_t)0x00000200) /*!< Bit 4 */
mbed_official 545:5112d5ae6723 1180
mbed_official 545:5112d5ae6723 1181 #define ADC_SQR4_SQ9 ((uint32_t)0x00007C00) /*!< SQ9[4:0] bits (9th conversion in regular sequence) */
mbed_official 545:5112d5ae6723 1182 #define ADC_SQR4_SQ9_0 ((uint32_t)0x00000400) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 1183 #define ADC_SQR4_SQ9_1 ((uint32_t)0x00000800) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 1184 #define ADC_SQR4_SQ9_2 ((uint32_t)0x00001000) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 1185 #define ADC_SQR4_SQ9_3 ((uint32_t)0x00002000) /*!< Bit 3 */
mbed_official 545:5112d5ae6723 1186 #define ADC_SQR4_SQ9_4 ((uint32_t)0x00004000) /*!< Bit 4 */
mbed_official 545:5112d5ae6723 1187
mbed_official 545:5112d5ae6723 1188 #define ADC_SQR4_SQ10 ((uint32_t)0x000F8000) /*!< SQ10[4:0] bits (10th conversion in regular sequence) */
mbed_official 545:5112d5ae6723 1189 #define ADC_SQR4_SQ10_0 ((uint32_t)0x00008000) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 1190 #define ADC_SQR4_SQ10_1 ((uint32_t)0x00010000) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 1191 #define ADC_SQR4_SQ10_2 ((uint32_t)0x00020000) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 1192 #define ADC_SQR4_SQ10_3 ((uint32_t)0x00040000) /*!< Bit 3 */
mbed_official 545:5112d5ae6723 1193 #define ADC_SQR4_SQ10_4 ((uint32_t)0x00080000) /*!< Bit 4 */
mbed_official 545:5112d5ae6723 1194
mbed_official 545:5112d5ae6723 1195 #define ADC_SQR4_SQ11 ((uint32_t)0x01F00000) /*!< SQ11[4:0] bits (11th conversion in regular sequence) */
mbed_official 545:5112d5ae6723 1196 #define ADC_SQR4_SQ11_0 ((uint32_t)0x00100000) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 1197 #define ADC_SQR4_SQ11_1 ((uint32_t)0x00200000) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 1198 #define ADC_SQR4_SQ11_2 ((uint32_t)0x00400000) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 1199 #define ADC_SQR4_SQ11_3 ((uint32_t)0x00800000) /*!< Bit 3 */
mbed_official 545:5112d5ae6723 1200 #define ADC_SQR4_SQ11_4 ((uint32_t)0x01000000) /*!< Bit 4 */
mbed_official 545:5112d5ae6723 1201
mbed_official 545:5112d5ae6723 1202 #define ADC_SQR4_SQ12 ((uint32_t)0x3E000000) /*!< SQ12[4:0] bits (12th conversion in regular sequence) */
mbed_official 545:5112d5ae6723 1203 #define ADC_SQR4_SQ12_0 ((uint32_t)0x02000000) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 1204 #define ADC_SQR4_SQ12_1 ((uint32_t)0x04000000) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 1205 #define ADC_SQR4_SQ12_2 ((uint32_t)0x08000000) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 1206 #define ADC_SQR4_SQ12_3 ((uint32_t)0x10000000) /*!< Bit 3 */
mbed_official 545:5112d5ae6723 1207 #define ADC_SQR4_SQ12_4 ((uint32_t)0x20000000) /*!< Bit 4 */
mbed_official 545:5112d5ae6723 1208
mbed_official 545:5112d5ae6723 1209 /******************* Bit definition for ADC_SQR5 register *******************/
mbed_official 545:5112d5ae6723 1210 #define ADC_SQR5_SQ1 ((uint32_t)0x0000001F) /*!< SQ1[4:0] bits (1st conversion in regular sequence) */
mbed_official 545:5112d5ae6723 1211 #define ADC_SQR5_SQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 1212 #define ADC_SQR5_SQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 1213 #define ADC_SQR5_SQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 1214 #define ADC_SQR5_SQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */
mbed_official 545:5112d5ae6723 1215 #define ADC_SQR5_SQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */
mbed_official 545:5112d5ae6723 1216
mbed_official 545:5112d5ae6723 1217 #define ADC_SQR5_SQ2 ((uint32_t)0x000003E0) /*!< SQ2[4:0] bits (2nd conversion in regular sequence) */
mbed_official 545:5112d5ae6723 1218 #define ADC_SQR5_SQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 1219 #define ADC_SQR5_SQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 1220 #define ADC_SQR5_SQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 1221 #define ADC_SQR5_SQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */
mbed_official 545:5112d5ae6723 1222 #define ADC_SQR5_SQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */
mbed_official 545:5112d5ae6723 1223
mbed_official 545:5112d5ae6723 1224 #define ADC_SQR5_SQ3 ((uint32_t)0x00007C00) /*!< SQ3[4:0] bits (3rd conversion in regular sequence) */
mbed_official 545:5112d5ae6723 1225 #define ADC_SQR5_SQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 1226 #define ADC_SQR5_SQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 1227 #define ADC_SQR5_SQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 1228 #define ADC_SQR5_SQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */
mbed_official 545:5112d5ae6723 1229 #define ADC_SQR5_SQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */
mbed_official 545:5112d5ae6723 1230
mbed_official 545:5112d5ae6723 1231 #define ADC_SQR5_SQ4 ((uint32_t)0x000F8000) /*!< SQ4[4:0] bits (4th conversion in regular sequence) */
mbed_official 545:5112d5ae6723 1232 #define ADC_SQR5_SQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 1233 #define ADC_SQR5_SQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 1234 #define ADC_SQR5_SQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 1235 #define ADC_SQR5_SQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */
mbed_official 545:5112d5ae6723 1236 #define ADC_SQR5_SQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */
mbed_official 545:5112d5ae6723 1237
mbed_official 545:5112d5ae6723 1238 #define ADC_SQR5_SQ5 ((uint32_t)0x01F00000) /*!< SQ5[4:0] bits (5th conversion in regular sequence) */
mbed_official 545:5112d5ae6723 1239 #define ADC_SQR5_SQ5_0 ((uint32_t)0x00100000) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 1240 #define ADC_SQR5_SQ5_1 ((uint32_t)0x00200000) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 1241 #define ADC_SQR5_SQ5_2 ((uint32_t)0x00400000) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 1242 #define ADC_SQR5_SQ5_3 ((uint32_t)0x00800000) /*!< Bit 3 */
mbed_official 545:5112d5ae6723 1243 #define ADC_SQR5_SQ5_4 ((uint32_t)0x01000000) /*!< Bit 4 */
mbed_official 545:5112d5ae6723 1244
mbed_official 545:5112d5ae6723 1245 #define ADC_SQR5_SQ6 ((uint32_t)0x3E000000) /*!< SQ6[4:0] bits (6th conversion in regular sequence) */
mbed_official 545:5112d5ae6723 1246 #define ADC_SQR5_SQ6_0 ((uint32_t)0x02000000) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 1247 #define ADC_SQR5_SQ6_1 ((uint32_t)0x04000000) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 1248 #define ADC_SQR5_SQ6_2 ((uint32_t)0x08000000) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 1249 #define ADC_SQR5_SQ6_3 ((uint32_t)0x10000000) /*!< Bit 3 */
mbed_official 545:5112d5ae6723 1250 #define ADC_SQR5_SQ6_4 ((uint32_t)0x20000000) /*!< Bit 4 */
mbed_official 545:5112d5ae6723 1251
mbed_official 545:5112d5ae6723 1252
mbed_official 545:5112d5ae6723 1253 /******************* Bit definition for ADC_JSQR register *******************/
mbed_official 545:5112d5ae6723 1254 #define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!< JSQ1[4:0] bits (1st conversion in injected sequence) */
mbed_official 545:5112d5ae6723 1255 #define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 1256 #define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 1257 #define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 1258 #define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */
mbed_official 545:5112d5ae6723 1259 #define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */
mbed_official 545:5112d5ae6723 1260
mbed_official 545:5112d5ae6723 1261 #define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!< JSQ2[4:0] bits (2nd conversion in injected sequence) */
mbed_official 545:5112d5ae6723 1262 #define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 1263 #define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 1264 #define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 1265 #define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */
mbed_official 545:5112d5ae6723 1266 #define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */
mbed_official 545:5112d5ae6723 1267
mbed_official 545:5112d5ae6723 1268 #define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!< JSQ3[4:0] bits (3rd conversion in injected sequence) */
mbed_official 545:5112d5ae6723 1269 #define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 1270 #define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 1271 #define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 1272 #define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */
mbed_official 545:5112d5ae6723 1273 #define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */
mbed_official 545:5112d5ae6723 1274
mbed_official 545:5112d5ae6723 1275 #define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!< JSQ4[4:0] bits (4th conversion in injected sequence) */
mbed_official 545:5112d5ae6723 1276 #define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 1277 #define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 1278 #define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 1279 #define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */
mbed_official 545:5112d5ae6723 1280 #define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */
mbed_official 545:5112d5ae6723 1281
mbed_official 545:5112d5ae6723 1282 #define ADC_JSQR_JL ((uint32_t)0x00300000) /*!< JL[1:0] bits (Injected Sequence length) */
mbed_official 545:5112d5ae6723 1283 #define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 1284 #define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 1285
mbed_official 545:5112d5ae6723 1286 /******************* Bit definition for ADC_JDR1 register *******************/
mbed_official 545:5112d5ae6723 1287 #define ADC_JDR1_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */
mbed_official 545:5112d5ae6723 1288
mbed_official 545:5112d5ae6723 1289 /******************* Bit definition for ADC_JDR2 register *******************/
mbed_official 545:5112d5ae6723 1290 #define ADC_JDR2_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */
mbed_official 545:5112d5ae6723 1291
mbed_official 545:5112d5ae6723 1292 /******************* Bit definition for ADC_JDR3 register *******************/
mbed_official 545:5112d5ae6723 1293 #define ADC_JDR3_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */
mbed_official 545:5112d5ae6723 1294
mbed_official 545:5112d5ae6723 1295 /******************* Bit definition for ADC_JDR4 register *******************/
mbed_official 545:5112d5ae6723 1296 #define ADC_JDR4_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */
mbed_official 545:5112d5ae6723 1297
mbed_official 545:5112d5ae6723 1298 /******************** Bit definition for ADC_DR register ********************/
mbed_official 545:5112d5ae6723 1299 #define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!< Regular data */
mbed_official 545:5112d5ae6723 1300
mbed_official 545:5112d5ae6723 1301 /******************* Bit definition for ADC_CSR register ********************/
mbed_official 545:5112d5ae6723 1302 #define ADC_CSR_AWD1 ((uint32_t)0x00000001) /*!< ADC1 Analog watchdog flag */
mbed_official 545:5112d5ae6723 1303 #define ADC_CSR_EOC1 ((uint32_t)0x00000002) /*!< ADC1 End of conversion */
mbed_official 545:5112d5ae6723 1304 #define ADC_CSR_JEOC1 ((uint32_t)0x00000004) /*!< ADC1 Injected channel end of conversion */
mbed_official 545:5112d5ae6723 1305 #define ADC_CSR_JSTRT1 ((uint32_t)0x00000008) /*!< ADC1 Injected channel Start flag */
mbed_official 545:5112d5ae6723 1306 #define ADC_CSR_STRT1 ((uint32_t)0x00000010) /*!< ADC1 Regular channel Start flag */
mbed_official 545:5112d5ae6723 1307 #define ADC_CSR_OVR1 ((uint32_t)0x00000020) /*!< ADC1 overrun flag */
mbed_official 545:5112d5ae6723 1308 #define ADC_CSR_ADONS1 ((uint32_t)0x00000040) /*!< ADON status of ADC1 */
mbed_official 545:5112d5ae6723 1309
mbed_official 545:5112d5ae6723 1310 /******************* Bit definition for ADC_CCR register ********************/
mbed_official 545:5112d5ae6723 1311 #define ADC_CCR_ADCPRE ((uint32_t)0x00030000) /*!< ADC prescaler*/
mbed_official 545:5112d5ae6723 1312 #define ADC_CCR_ADCPRE_0 ((uint32_t)0x00010000) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 1313 #define ADC_CCR_ADCPRE_1 ((uint32_t)0x00020000) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 1314 #define ADC_CCR_TSVREFE ((uint32_t)0x00800000) /*!< Temperature Sensor and VREFINT Enable */
mbed_official 545:5112d5ae6723 1315
mbed_official 545:5112d5ae6723 1316 /******************************************************************************/
mbed_official 545:5112d5ae6723 1317 /* */
mbed_official 545:5112d5ae6723 1318 /* Analog Comparators (COMP) */
mbed_official 545:5112d5ae6723 1319 /* */
mbed_official 545:5112d5ae6723 1320 /******************************************************************************/
mbed_official 545:5112d5ae6723 1321
mbed_official 545:5112d5ae6723 1322 /****************** Bit definition for COMP_CSR register ********************/
mbed_official 545:5112d5ae6723 1323 #define COMP_CSR_10KPU ((uint32_t)0x00000001) /*!< 10K pull-up resistor */
mbed_official 545:5112d5ae6723 1324 #define COMP_CSR_400KPU ((uint32_t)0x00000002) /*!< 400K pull-up resistor */
mbed_official 545:5112d5ae6723 1325 #define COMP_CSR_10KPD ((uint32_t)0x00000004) /*!< 10K pull-down resistor */
mbed_official 545:5112d5ae6723 1326 #define COMP_CSR_400KPD ((uint32_t)0x00000008) /*!< 400K pull-down resistor */
mbed_official 545:5112d5ae6723 1327 #define COMP_CSR_CMP1EN ((uint32_t)0x00000010) /*!< Comparator 1 enable */
mbed_official 545:5112d5ae6723 1328 #define COMP_CSR_CMP1OUT ((uint32_t)0x00000080) /*!< Comparator 1 output */
mbed_official 545:5112d5ae6723 1329
mbed_official 545:5112d5ae6723 1330 #define COMP_CSR_SPEED ((uint32_t)0x00001000) /*!< Comparator 2 speed */
mbed_official 545:5112d5ae6723 1331 #define COMP_CSR_CMP2OUT ((uint32_t)0x00002000) /*!< Comparator 2 ouput */
mbed_official 545:5112d5ae6723 1332 #define COMP_CSR_VREFOUTEN ((uint32_t)0x00010000) /*!< Comparator Vref Enable */
mbed_official 545:5112d5ae6723 1333 #define COMP_CSR_WNDWE ((uint32_t)0x00020000) /*!< Window mode enable */
mbed_official 545:5112d5ae6723 1334 #define COMP_CSR_INSEL ((uint32_t)0x001C0000) /*!< INSEL[2:0] Inversion input Selection */
mbed_official 545:5112d5ae6723 1335 #define COMP_CSR_INSEL_0 ((uint32_t)0x00040000) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 1336 #define COMP_CSR_INSEL_1 ((uint32_t)0x00080000) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 1337 #define COMP_CSR_INSEL_2 ((uint32_t)0x00100000) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 1338 #define COMP_CSR_OUTSEL ((uint32_t)0x00E00000) /*!< OUTSEL[2:0] comparator 2 output redirection */
mbed_official 545:5112d5ae6723 1339 #define COMP_CSR_OUTSEL_0 ((uint32_t)0x00200000) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 1340 #define COMP_CSR_OUTSEL_1 ((uint32_t)0x00400000) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 1341 #define COMP_CSR_OUTSEL_2 ((uint32_t)0x00800000) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 1342
mbed_official 545:5112d5ae6723 1343 #define COMP_CSR_FCH3 ((uint32_t)0x04000000) /*!< Bit 26 */
mbed_official 545:5112d5ae6723 1344 #define COMP_CSR_FCH8 ((uint32_t)0x08000000) /*!< Bit 27 */
mbed_official 545:5112d5ae6723 1345 #define COMP_CSR_RCH13 ((uint32_t)0x10000000) /*!< Bit 28 */
mbed_official 545:5112d5ae6723 1346
mbed_official 545:5112d5ae6723 1347 #define COMP_CSR_CAIE ((uint32_t)0x20000000) /*!< Bit 29 */
mbed_official 545:5112d5ae6723 1348 #define COMP_CSR_CAIF ((uint32_t)0x40000000) /*!< Bit 30 */
mbed_official 545:5112d5ae6723 1349 #define COMP_CSR_TSUSP ((uint32_t)0x80000000) /*!< Bit 31 */
mbed_official 545:5112d5ae6723 1350
mbed_official 545:5112d5ae6723 1351 /******************************************************************************/
mbed_official 545:5112d5ae6723 1352 /* */
mbed_official 545:5112d5ae6723 1353 /* Operational Amplifier (OPAMP) */
mbed_official 545:5112d5ae6723 1354 /* */
mbed_official 545:5112d5ae6723 1355 /******************************************************************************/
mbed_official 545:5112d5ae6723 1356 /******************* Bit definition for OPAMP_CSR register ******************/
mbed_official 545:5112d5ae6723 1357 #define OPAMP_CSR_OPA1PD ((uint32_t)0x00000001) /*!< OPAMP1 disable */
mbed_official 545:5112d5ae6723 1358 #define OPAMP_CSR_S3SEL1 ((uint32_t)0x00000002) /*!< Switch 3 for OPAMP1 Enable */
mbed_official 545:5112d5ae6723 1359 #define OPAMP_CSR_S4SEL1 ((uint32_t)0x00000004) /*!< Switch 4 for OPAMP1 Enable */
mbed_official 545:5112d5ae6723 1360 #define OPAMP_CSR_S5SEL1 ((uint32_t)0x00000008) /*!< Switch 5 for OPAMP1 Enable */
mbed_official 545:5112d5ae6723 1361 #define OPAMP_CSR_S6SEL1 ((uint32_t)0x00000010) /*!< Switch 6 for OPAMP1 Enable */
mbed_official 545:5112d5ae6723 1362 #define OPAMP_CSR_OPA1CAL_L ((uint32_t)0x00000020) /*!< OPAMP1 Offset calibration for P differential pair */
mbed_official 545:5112d5ae6723 1363 #define OPAMP_CSR_OPA1CAL_H ((uint32_t)0x00000040) /*!< OPAMP1 Offset calibration for N differential pair */
mbed_official 545:5112d5ae6723 1364 #define OPAMP_CSR_OPA1LPM ((uint32_t)0x00000080) /*!< OPAMP1 Low power enable */
mbed_official 545:5112d5ae6723 1365 #define OPAMP_CSR_OPA2PD ((uint32_t)0x00000100) /*!< OPAMP2 disable */
mbed_official 545:5112d5ae6723 1366 #define OPAMP_CSR_S3SEL2 ((uint32_t)0x00000200) /*!< Switch 3 for OPAMP2 Enable */
mbed_official 545:5112d5ae6723 1367 #define OPAMP_CSR_S4SEL2 ((uint32_t)0x00000400) /*!< Switch 4 for OPAMP2 Enable */
mbed_official 545:5112d5ae6723 1368 #define OPAMP_CSR_S5SEL2 ((uint32_t)0x00000800) /*!< Switch 5 for OPAMP2 Enable */
mbed_official 545:5112d5ae6723 1369 #define OPAMP_CSR_S6SEL2 ((uint32_t)0x00001000) /*!< Switch 6 for OPAMP2 Enable */
mbed_official 545:5112d5ae6723 1370 #define OPAMP_CSR_OPA2CAL_L ((uint32_t)0x00002000) /*!< OPAMP2 Offset calibration for P differential pair */
mbed_official 545:5112d5ae6723 1371 #define OPAMP_CSR_OPA2CAL_H ((uint32_t)0x00004000) /*!< OPAMP2 Offset calibration for N differential pair */
mbed_official 545:5112d5ae6723 1372 #define OPAMP_CSR_OPA2LPM ((uint32_t)0x00008000) /*!< OPAMP2 Low power enable */
mbed_official 545:5112d5ae6723 1373 #define OPAMP_CSR_ANAWSEL1 ((uint32_t)0x01000000) /*!< Switch ANA Enable for OPAMP1 */
mbed_official 545:5112d5ae6723 1374 #define OPAMP_CSR_ANAWSEL2 ((uint32_t)0x02000000) /*!< Switch ANA Enable for OPAMP2 */
mbed_official 545:5112d5ae6723 1375 #define OPAMP_CSR_S7SEL2 ((uint32_t)0x08000000) /*!< Switch 7 for OPAMP2 Enable */
mbed_official 545:5112d5ae6723 1376 #define OPAMP_CSR_AOP_RANGE ((uint32_t)0x10000000) /*!< Power range selection */
mbed_official 545:5112d5ae6723 1377 #define OPAMP_CSR_OPA1CALOUT ((uint32_t)0x20000000) /*!< OPAMP1 calibration output */
mbed_official 545:5112d5ae6723 1378 #define OPAMP_CSR_OPA2CALOUT ((uint32_t)0x40000000) /*!< OPAMP2 calibration output */
mbed_official 545:5112d5ae6723 1379
mbed_official 545:5112d5ae6723 1380 /******************* Bit definition for OPAMP_OTR register ******************/
mbed_official 545:5112d5ae6723 1381 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW ((uint32_t)0x0000001F) /*!< Offset trim for transistors differential pair PMOS of OPAMP1 */
mbed_official 545:5112d5ae6723 1382 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH ((uint32_t)0x000003E0) /*!< Offset trim for transistors differential pair NMOS of OPAMP1 */
mbed_official 545:5112d5ae6723 1383 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW ((uint32_t)0x00007C00) /*!< Offset trim for transistors differential pair PMOS of OPAMP2 */
mbed_official 545:5112d5ae6723 1384 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH ((uint32_t)0x000F8000) /*!< Offset trim for transistors differential pair NMOS of OPAMP2 */
mbed_official 545:5112d5ae6723 1385 #define OPAMP_OTR_OT_USER ((uint32_t)0x80000000) /*!< Switch to OPAMP offset user trimmed values */
mbed_official 545:5112d5ae6723 1386
mbed_official 545:5112d5ae6723 1387 /******************* Bit definition for OPAMP_LPOTR register ****************/
mbed_official 545:5112d5ae6723 1388 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW ((uint32_t)0x0000001F) /*!< Offset trim for transistors differential pair PMOS of OPAMP1 */
mbed_official 545:5112d5ae6723 1389 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH ((uint32_t)0x000003E0) /*!< Offset trim for transistors differential pair NMOS of OPAMP1 */
mbed_official 545:5112d5ae6723 1390 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW ((uint32_t)0x00007C00) /*!< Offset trim for transistors differential pair PMOS of OPAMP2 */
mbed_official 545:5112d5ae6723 1391 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH ((uint32_t)0x000F8000) /*!< Offset trim for transistors differential pair NMOS of OPAMP2 */
mbed_official 545:5112d5ae6723 1392
mbed_official 545:5112d5ae6723 1393 /******************************************************************************/
mbed_official 545:5112d5ae6723 1394 /* */
mbed_official 545:5112d5ae6723 1395 /* CRC calculation unit (CRC) */
mbed_official 545:5112d5ae6723 1396 /* */
mbed_official 545:5112d5ae6723 1397 /******************************************************************************/
mbed_official 545:5112d5ae6723 1398
mbed_official 545:5112d5ae6723 1399 /******************* Bit definition for CRC_DR register *********************/
mbed_official 545:5112d5ae6723 1400 #define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
mbed_official 545:5112d5ae6723 1401
mbed_official 545:5112d5ae6723 1402 /******************* Bit definition for CRC_IDR register ********************/
mbed_official 545:5112d5ae6723 1403 #define CRC_IDR_IDR ((uint32_t)0x000000FF) /*!< General-purpose 8-bit data register bits */
mbed_official 545:5112d5ae6723 1404
mbed_official 545:5112d5ae6723 1405 /******************** Bit definition for CRC_CR register ********************/
mbed_official 545:5112d5ae6723 1406 #define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET bit */
mbed_official 545:5112d5ae6723 1407
mbed_official 545:5112d5ae6723 1408 /******************************************************************************/
mbed_official 545:5112d5ae6723 1409 /* */
mbed_official 545:5112d5ae6723 1410 /* Digital to Analog Converter (DAC) */
mbed_official 545:5112d5ae6723 1411 /* */
mbed_official 545:5112d5ae6723 1412 /******************************************************************************/
mbed_official 545:5112d5ae6723 1413
mbed_official 545:5112d5ae6723 1414 /******************** Bit definition for DAC_CR register ********************/
mbed_official 545:5112d5ae6723 1415 #define DAC_CR_EN1 ((uint32_t)0x00000001) /*!<DAC channel1 enable */
mbed_official 545:5112d5ae6723 1416 #define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!<DAC channel1 output buffer disable */
mbed_official 545:5112d5ae6723 1417 #define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!<DAC channel1 Trigger enable */
mbed_official 545:5112d5ae6723 1418
mbed_official 545:5112d5ae6723 1419 #define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
mbed_official 545:5112d5ae6723 1420 #define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!<Bit 0 */
mbed_official 545:5112d5ae6723 1421 #define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!<Bit 1 */
mbed_official 545:5112d5ae6723 1422 #define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!<Bit 2 */
mbed_official 545:5112d5ae6723 1423
mbed_official 545:5112d5ae6723 1424 #define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
mbed_official 545:5112d5ae6723 1425 #define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!<Bit 0 */
mbed_official 545:5112d5ae6723 1426 #define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!<Bit 1 */
mbed_official 545:5112d5ae6723 1427
mbed_official 545:5112d5ae6723 1428 #define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
mbed_official 545:5112d5ae6723 1429 #define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 545:5112d5ae6723 1430 #define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 545:5112d5ae6723 1431 #define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 545:5112d5ae6723 1432 #define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 545:5112d5ae6723 1433
mbed_official 545:5112d5ae6723 1434 #define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!<DAC channel1 DMA enable */
mbed_official 545:5112d5ae6723 1435 #define DAC_CR_DMAUDRIE1 ((uint32_t)0x00002000) /*!<DAC channel1 DMA Interrupt enable */
mbed_official 545:5112d5ae6723 1436 #define DAC_CR_EN2 ((uint32_t)0x00010000) /*!<DAC channel2 enable */
mbed_official 545:5112d5ae6723 1437 #define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!<DAC channel2 output buffer disable */
mbed_official 545:5112d5ae6723 1438 #define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!<DAC channel2 Trigger enable */
mbed_official 545:5112d5ae6723 1439
mbed_official 545:5112d5ae6723 1440 #define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
mbed_official 545:5112d5ae6723 1441 #define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!<Bit 0 */
mbed_official 545:5112d5ae6723 1442 #define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!<Bit 1 */
mbed_official 545:5112d5ae6723 1443 #define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!<Bit 2 */
mbed_official 545:5112d5ae6723 1444
mbed_official 545:5112d5ae6723 1445 #define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
mbed_official 545:5112d5ae6723 1446 #define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!<Bit 0 */
mbed_official 545:5112d5ae6723 1447 #define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!<Bit 1 */
mbed_official 545:5112d5ae6723 1448
mbed_official 545:5112d5ae6723 1449 #define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
mbed_official 545:5112d5ae6723 1450 #define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 545:5112d5ae6723 1451 #define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 545:5112d5ae6723 1452 #define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 545:5112d5ae6723 1453 #define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
mbed_official 545:5112d5ae6723 1454
mbed_official 545:5112d5ae6723 1455 #define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!<DAC channel2 DMA enabled */
mbed_official 545:5112d5ae6723 1456 #define DAC_CR_DMAUDRIE2 ((uint32_t)0x20000000) /*!<DAC channel2 DMA underrun interrupt enable */
mbed_official 545:5112d5ae6723 1457 /***************** Bit definition for DAC_SWTRIGR register ******************/
mbed_official 545:5112d5ae6723 1458 #define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x00000001) /*!<DAC channel1 software trigger */
mbed_official 545:5112d5ae6723 1459 #define DAC_SWTRIGR_SWTRIG2 ((uint32_t)0x00000002) /*!<DAC channel2 software trigger */
mbed_official 545:5112d5ae6723 1460
mbed_official 545:5112d5ae6723 1461 /***************** Bit definition for DAC_DHR12R1 register ******************/
mbed_official 545:5112d5ae6723 1462 #define DAC_DHR12R1_DACC1DHR ((uint32_t)0x00000FFF) /*!<DAC channel1 12-bit Right aligned data */
mbed_official 545:5112d5ae6723 1463
mbed_official 545:5112d5ae6723 1464 /***************** Bit definition for DAC_DHR12L1 register ******************/
mbed_official 545:5112d5ae6723 1465 #define DAC_DHR12L1_DACC1DHR ((uint32_t)0x0000FFF0) /*!<DAC channel1 12-bit Left aligned data */
mbed_official 545:5112d5ae6723 1466
mbed_official 545:5112d5ae6723 1467 /****************** Bit definition for DAC_DHR8R1 register ******************/
mbed_official 545:5112d5ae6723 1468 #define DAC_DHR8R1_DACC1DHR ((uint32_t)0x000000FF) /*!<DAC channel1 8-bit Right aligned data */
mbed_official 545:5112d5ae6723 1469
mbed_official 545:5112d5ae6723 1470 /***************** Bit definition for DAC_DHR12R2 register ******************/
mbed_official 545:5112d5ae6723 1471 #define DAC_DHR12R2_DACC2DHR ((uint32_t)0x00000FFF) /*!<DAC channel2 12-bit Right aligned data */
mbed_official 545:5112d5ae6723 1472
mbed_official 545:5112d5ae6723 1473 /***************** Bit definition for DAC_DHR12L2 register ******************/
mbed_official 545:5112d5ae6723 1474 #define DAC_DHR12L2_DACC2DHR ((uint32_t)0x0000FFF0) /*!<DAC channel2 12-bit Left aligned data */
mbed_official 545:5112d5ae6723 1475
mbed_official 545:5112d5ae6723 1476 /****************** Bit definition for DAC_DHR8R2 register ******************/
mbed_official 545:5112d5ae6723 1477 #define DAC_DHR8R2_DACC2DHR ((uint32_t)0x000000FF) /*!<DAC channel2 8-bit Right aligned data */
mbed_official 545:5112d5ae6723 1478
mbed_official 545:5112d5ae6723 1479 /***************** Bit definition for DAC_DHR12RD register ******************/
mbed_official 545:5112d5ae6723 1480 #define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!<DAC channel1 12-bit Right aligned data */
mbed_official 545:5112d5ae6723 1481 #define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!<DAC channel2 12-bit Right aligned data */
mbed_official 545:5112d5ae6723 1482
mbed_official 545:5112d5ae6723 1483 /***************** Bit definition for DAC_DHR12LD register ******************/
mbed_official 545:5112d5ae6723 1484 #define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!<DAC channel1 12-bit Left aligned data */
mbed_official 545:5112d5ae6723 1485 #define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!<DAC channel2 12-bit Left aligned data */
mbed_official 545:5112d5ae6723 1486
mbed_official 545:5112d5ae6723 1487 /****************** Bit definition for DAC_DHR8RD register ******************/
mbed_official 545:5112d5ae6723 1488 #define DAC_DHR8RD_DACC1DHR ((uint32_t)0x000000FF) /*!<DAC channel1 8-bit Right aligned data */
mbed_official 545:5112d5ae6723 1489 #define DAC_DHR8RD_DACC2DHR ((uint32_t)0x0000FF00) /*!<DAC channel2 8-bit Right aligned data */
mbed_official 545:5112d5ae6723 1490
mbed_official 545:5112d5ae6723 1491 /******************* Bit definition for DAC_DOR1 register *******************/
mbed_official 545:5112d5ae6723 1492 #define DAC_DOR1_DACC1DOR ((uint32_t)0x00000FFF) /*!<DAC channel1 data output */
mbed_official 545:5112d5ae6723 1493
mbed_official 545:5112d5ae6723 1494 /******************* Bit definition for DAC_DOR2 register *******************/
mbed_official 545:5112d5ae6723 1495 #define DAC_DOR2_DACC2DOR ((uint_t)0x00000FFF) /*!<DAC channel2 data output */
mbed_official 545:5112d5ae6723 1496
mbed_official 545:5112d5ae6723 1497 /******************** Bit definition for DAC_SR register ********************/
mbed_official 545:5112d5ae6723 1498 #define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!<DAC channel1 DMA underrun flag */
mbed_official 545:5112d5ae6723 1499 #define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!<DAC channel2 DMA underrun flag */
mbed_official 545:5112d5ae6723 1500
mbed_official 545:5112d5ae6723 1501 /******************************************************************************/
mbed_official 545:5112d5ae6723 1502 /* */
mbed_official 545:5112d5ae6723 1503 /* Debug MCU (DBGMCU) */
mbed_official 545:5112d5ae6723 1504 /* */
mbed_official 545:5112d5ae6723 1505 /******************************************************************************/
mbed_official 545:5112d5ae6723 1506
mbed_official 545:5112d5ae6723 1507 /**************** Bit definition for DBGMCU_IDCODE register *****************/
mbed_official 545:5112d5ae6723 1508 #define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) /*!< Device Identifier */
mbed_official 545:5112d5ae6723 1509
mbed_official 545:5112d5ae6723 1510 #define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) /*!< REV_ID[15:0] bits (Revision Identifier) */
mbed_official 545:5112d5ae6723 1511 #define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 1512 #define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 1513 #define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 1514 #define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) /*!< Bit 3 */
mbed_official 545:5112d5ae6723 1515 #define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) /*!< Bit 4 */
mbed_official 545:5112d5ae6723 1516 #define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) /*!< Bit 5 */
mbed_official 545:5112d5ae6723 1517 #define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) /*!< Bit 6 */
mbed_official 545:5112d5ae6723 1518 #define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) /*!< Bit 7 */
mbed_official 545:5112d5ae6723 1519 #define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) /*!< Bit 8 */
mbed_official 545:5112d5ae6723 1520 #define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) /*!< Bit 9 */
mbed_official 545:5112d5ae6723 1521 #define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) /*!< Bit 10 */
mbed_official 545:5112d5ae6723 1522 #define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) /*!< Bit 11 */
mbed_official 545:5112d5ae6723 1523 #define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) /*!< Bit 12 */
mbed_official 545:5112d5ae6723 1524 #define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) /*!< Bit 13 */
mbed_official 545:5112d5ae6723 1525 #define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) /*!< Bit 14 */
mbed_official 545:5112d5ae6723 1526 #define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) /*!< Bit 15 */
mbed_official 545:5112d5ae6723 1527
mbed_official 545:5112d5ae6723 1528 /****************** Bit definition for DBGMCU_CR register *******************/
mbed_official 545:5112d5ae6723 1529 #define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001) /*!< Debug Sleep Mode */
mbed_official 545:5112d5ae6723 1530 #define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) /*!< Debug Stop Mode */
mbed_official 545:5112d5ae6723 1531 #define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) /*!< Debug Standby mode */
mbed_official 545:5112d5ae6723 1532 #define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020) /*!< Trace Pin Assignment Control */
mbed_official 545:5112d5ae6723 1533
mbed_official 545:5112d5ae6723 1534 #define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0) /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */
mbed_official 545:5112d5ae6723 1535 #define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 1536 #define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 1537
mbed_official 545:5112d5ae6723 1538 /****************** Bit definition for DBGMCU_APB1_FZ register **************/
mbed_official 545:5112d5ae6723 1539
mbed_official 545:5112d5ae6723 1540 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001) /*!< TIM2 counter stopped when core is halted */
mbed_official 545:5112d5ae6723 1541 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002) /*!< TIM3 counter stopped when core is halted */
mbed_official 545:5112d5ae6723 1542 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP ((uint32_t)0x00000004) /*!< TIM4 counter stopped when core is halted */
mbed_official 545:5112d5ae6723 1543 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP ((uint32_t)0x00000008) /*!< TIM5 counter stopped when core is halted */
mbed_official 545:5112d5ae6723 1544 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010) /*!< TIM6 counter stopped when core is halted */
mbed_official 545:5112d5ae6723 1545 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020) /*!< TIM7 counter stopped when core is halted */
mbed_official 545:5112d5ae6723 1546 #define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400) /*!< RTC Counter stopped when Core is halted */
mbed_official 545:5112d5ae6723 1547 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800) /*!< Debug Window Watchdog stopped when Core is halted */
mbed_official 545:5112d5ae6723 1548 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000) /*!< Debug Independent Watchdog stopped when Core is halted */
mbed_official 545:5112d5ae6723 1549 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000) /*!< SMBUS timeout mode stopped when Core is halted */
mbed_official 545:5112d5ae6723 1550 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000) /*!< SMBUS timeout mode stopped when Core is halted */
mbed_official 545:5112d5ae6723 1551
mbed_official 545:5112d5ae6723 1552 /****************** Bit definition for DBGMCU_APB2_FZ register **************/
mbed_official 545:5112d5ae6723 1553
mbed_official 545:5112d5ae6723 1554 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP ((uint32_t)0x00000004) /*!< TIM9 counter stopped when core is halted */
mbed_official 545:5112d5ae6723 1555 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP ((uint32_t)0x00000008) /*!< TIM10 counter stopped when core is halted */
mbed_official 545:5112d5ae6723 1556 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP ((uint32_t)0x00000010) /*!< TIM11 counter stopped when core is halted */
mbed_official 545:5112d5ae6723 1557
mbed_official 545:5112d5ae6723 1558 /******************************************************************************/
mbed_official 545:5112d5ae6723 1559 /* */
mbed_official 545:5112d5ae6723 1560 /* DMA Controller (DMA) */
mbed_official 545:5112d5ae6723 1561 /* */
mbed_official 545:5112d5ae6723 1562 /******************************************************************************/
mbed_official 545:5112d5ae6723 1563
mbed_official 545:5112d5ae6723 1564 /******************* Bit definition for DMA_ISR register ********************/
mbed_official 545:5112d5ae6723 1565 #define DMA_ISR_GIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */
mbed_official 545:5112d5ae6723 1566 #define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */
mbed_official 545:5112d5ae6723 1567 #define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */
mbed_official 545:5112d5ae6723 1568 #define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */
mbed_official 545:5112d5ae6723 1569 #define DMA_ISR_GIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */
mbed_official 545:5112d5ae6723 1570 #define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */
mbed_official 545:5112d5ae6723 1571 #define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */
mbed_official 545:5112d5ae6723 1572 #define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */
mbed_official 545:5112d5ae6723 1573 #define DMA_ISR_GIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */
mbed_official 545:5112d5ae6723 1574 #define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */
mbed_official 545:5112d5ae6723 1575 #define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */
mbed_official 545:5112d5ae6723 1576 #define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */
mbed_official 545:5112d5ae6723 1577 #define DMA_ISR_GIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */
mbed_official 545:5112d5ae6723 1578 #define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */
mbed_official 545:5112d5ae6723 1579 #define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */
mbed_official 545:5112d5ae6723 1580 #define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */
mbed_official 545:5112d5ae6723 1581 #define DMA_ISR_GIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */
mbed_official 545:5112d5ae6723 1582 #define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */
mbed_official 545:5112d5ae6723 1583 #define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */
mbed_official 545:5112d5ae6723 1584 #define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */
mbed_official 545:5112d5ae6723 1585 #define DMA_ISR_GIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt flag */
mbed_official 545:5112d5ae6723 1586 #define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete flag */
mbed_official 545:5112d5ae6723 1587 #define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer flag */
mbed_official 545:5112d5ae6723 1588 #define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error flag */
mbed_official 545:5112d5ae6723 1589 #define DMA_ISR_GIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt flag */
mbed_official 545:5112d5ae6723 1590 #define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete flag */
mbed_official 545:5112d5ae6723 1591 #define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer flag */
mbed_official 545:5112d5ae6723 1592 #define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error flag */
mbed_official 545:5112d5ae6723 1593
mbed_official 545:5112d5ae6723 1594 /******************* Bit definition for DMA_IFCR register *******************/
mbed_official 545:5112d5ae6723 1595 #define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clear */
mbed_official 545:5112d5ae6723 1596 #define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */
mbed_official 545:5112d5ae6723 1597 #define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */
mbed_official 545:5112d5ae6723 1598 #define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */
mbed_official 545:5112d5ae6723 1599 #define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */
mbed_official 545:5112d5ae6723 1600 #define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */
mbed_official 545:5112d5ae6723 1601 #define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */
mbed_official 545:5112d5ae6723 1602 #define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */
mbed_official 545:5112d5ae6723 1603 #define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */
mbed_official 545:5112d5ae6723 1604 #define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */
mbed_official 545:5112d5ae6723 1605 #define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */
mbed_official 545:5112d5ae6723 1606 #define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */
mbed_official 545:5112d5ae6723 1607 #define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */
mbed_official 545:5112d5ae6723 1608 #define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */
mbed_official 545:5112d5ae6723 1609 #define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */
mbed_official 545:5112d5ae6723 1610 #define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */
mbed_official 545:5112d5ae6723 1611 #define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */
mbed_official 545:5112d5ae6723 1612 #define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */
mbed_official 545:5112d5ae6723 1613 #define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */
mbed_official 545:5112d5ae6723 1614 #define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */
mbed_official 545:5112d5ae6723 1615 #define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt clear */
mbed_official 545:5112d5ae6723 1616 #define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete clear */
mbed_official 545:5112d5ae6723 1617 #define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer clear */
mbed_official 545:5112d5ae6723 1618 #define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error clear */
mbed_official 545:5112d5ae6723 1619 #define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt clear */
mbed_official 545:5112d5ae6723 1620 #define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete clear */
mbed_official 545:5112d5ae6723 1621 #define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer clear */
mbed_official 545:5112d5ae6723 1622 #define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error clear */
mbed_official 545:5112d5ae6723 1623
mbed_official 545:5112d5ae6723 1624 /******************* Bit definition for DMA_CCR register *******************/
mbed_official 545:5112d5ae6723 1625 #define DMA_CCR_EN ((uint32_t)0x00000001) /*!< Channel enable*/
mbed_official 545:5112d5ae6723 1626 #define DMA_CCR_TCIE ((uint32_t)0x00000002) /*!< Transfer complete interrupt enable */
mbed_official 545:5112d5ae6723 1627 #define DMA_CCR_HTIE ((uint32_t)0x00000004) /*!< Half Transfer interrupt enable */
mbed_official 545:5112d5ae6723 1628 #define DMA_CCR_TEIE ((uint32_t)0x00000008) /*!< Transfer error interrupt enable */
mbed_official 545:5112d5ae6723 1629 #define DMA_CCR_DIR ((uint32_t)0x00000010) /*!< Data transfer direction */
mbed_official 545:5112d5ae6723 1630 #define DMA_CCR_CIRC ((uint32_t)0x00000020) /*!< Circular mode */
mbed_official 545:5112d5ae6723 1631 #define DMA_CCR_PINC ((uint32_t)0x00000040) /*!< Peripheral increment mode */
mbed_official 545:5112d5ae6723 1632 #define DMA_CCR_MINC ((uint32_t)0x00000080) /*!< Memory increment mode */
mbed_official 545:5112d5ae6723 1633
mbed_official 545:5112d5ae6723 1634 #define DMA_CCR_PSIZE ((uint32_t)0x00000300) /*!< PSIZE[1:0] bits (Peripheral size) */
mbed_official 545:5112d5ae6723 1635 #define DMA_CCR_PSIZE_0 ((uint32_t)0x00000100) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 1636 #define DMA_CCR_PSIZE_1 ((uint32_t)0x00000200) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 1637
mbed_official 545:5112d5ae6723 1638 #define DMA_CCR_MSIZE ((uint32_t)0x00000C00) /*!< MSIZE[1:0] bits (Memory size) */
mbed_official 545:5112d5ae6723 1639 #define DMA_CCR_MSIZE_0 ((uint32_t)0x00000400) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 1640 #define DMA_CCR_MSIZE_1 ((uint32_t)0x00000800) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 1641
mbed_official 545:5112d5ae6723 1642 #define DMA_CCR_PL ((uint32_t)0x00003000) /*!< PL[1:0] bits(Channel Priority level) */
mbed_official 545:5112d5ae6723 1643 #define DMA_CCR_PL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 1644 #define DMA_CCR_PL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 1645
mbed_official 545:5112d5ae6723 1646 #define DMA_CCR_MEM2MEM ((uint32_t)0x00004000) /*!< Memory to memory mode */
mbed_official 545:5112d5ae6723 1647
mbed_official 545:5112d5ae6723 1648 /****************** Bit definition for DMA_CNDTR1 register ******************/
mbed_official 545:5112d5ae6723 1649 #define DMA_CNDTR1_NDT ((uint32_t)0x0000FFFF) /*!< Number of data to Transfer */
mbed_official 545:5112d5ae6723 1650
mbed_official 545:5112d5ae6723 1651 /****************** Bit definition for DMA_CNDTR2 register ******************/
mbed_official 545:5112d5ae6723 1652 #define DMA_CNDTR2_NDT ((uint32_t)0x0000FFFF) /*!< Number of data to Transfer */
mbed_official 545:5112d5ae6723 1653
mbed_official 545:5112d5ae6723 1654 /****************** Bit definition for DMA_CNDTR3 register ******************/
mbed_official 545:5112d5ae6723 1655 #define DMA_CNDTR3_NDT ((uint32_t)0x0000FFFF) /*!< Number of data to Transfer */
mbed_official 545:5112d5ae6723 1656
mbed_official 545:5112d5ae6723 1657 /****************** Bit definition for DMA_CNDTR4 register ******************/
mbed_official 545:5112d5ae6723 1658 #define DMA_CNDTR4_NDT ((uint32_t)0x0000FFFF) /*!< Number of data to Transfer */
mbed_official 545:5112d5ae6723 1659
mbed_official 545:5112d5ae6723 1660 /****************** Bit definition for DMA_CNDTR5 register ******************/
mbed_official 545:5112d5ae6723 1661 #define DMA_CNDTR5_NDT ((uint32_t)0x0000FFFF) /*!< Number of data to Transfer */
mbed_official 545:5112d5ae6723 1662
mbed_official 545:5112d5ae6723 1663 /****************** Bit definition for DMA_CNDTR6 register ******************/
mbed_official 545:5112d5ae6723 1664 #define DMA_CNDTR6_NDT ((uint32_t)0x0000FFFF) /*!< Number of data to Transfer */
mbed_official 545:5112d5ae6723 1665
mbed_official 545:5112d5ae6723 1666 /****************** Bit definition for DMA_CNDTR7 register ******************/
mbed_official 545:5112d5ae6723 1667 #define DMA_CNDTR7_NDT ((uint32_t)0x0000FFFF) /*!< Number of data to Transfer */
mbed_official 545:5112d5ae6723 1668
mbed_official 545:5112d5ae6723 1669 /****************** Bit definition for DMA_CPAR1 register *******************/
mbed_official 545:5112d5ae6723 1670 #define DMA_CPAR1_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
mbed_official 545:5112d5ae6723 1671
mbed_official 545:5112d5ae6723 1672 /****************** Bit definition for DMA_CPAR2 register *******************/
mbed_official 545:5112d5ae6723 1673 #define DMA_CPAR2_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
mbed_official 545:5112d5ae6723 1674
mbed_official 545:5112d5ae6723 1675 /****************** Bit definition for DMA_CPAR3 register *******************/
mbed_official 545:5112d5ae6723 1676 #define DMA_CPAR3_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
mbed_official 545:5112d5ae6723 1677
mbed_official 545:5112d5ae6723 1678
mbed_official 545:5112d5ae6723 1679 /****************** Bit definition for DMA_CPAR4 register *******************/
mbed_official 545:5112d5ae6723 1680 #define DMA_CPAR4_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
mbed_official 545:5112d5ae6723 1681
mbed_official 545:5112d5ae6723 1682 /****************** Bit definition for DMA_CPAR5 register *******************/
mbed_official 545:5112d5ae6723 1683 #define DMA_CPAR5_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
mbed_official 545:5112d5ae6723 1684
mbed_official 545:5112d5ae6723 1685 /****************** Bit definition for DMA_CPAR6 register *******************/
mbed_official 545:5112d5ae6723 1686 #define DMA_CPAR6_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
mbed_official 545:5112d5ae6723 1687
mbed_official 545:5112d5ae6723 1688
mbed_official 545:5112d5ae6723 1689 /****************** Bit definition for DMA_CPAR7 register *******************/
mbed_official 545:5112d5ae6723 1690 #define DMA_CPAR7_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
mbed_official 545:5112d5ae6723 1691
mbed_official 545:5112d5ae6723 1692 /****************** Bit definition for DMA_CMAR1 register *******************/
mbed_official 545:5112d5ae6723 1693 #define DMA_CMAR1_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
mbed_official 545:5112d5ae6723 1694
mbed_official 545:5112d5ae6723 1695 /****************** Bit definition for DMA_CMAR2 register *******************/
mbed_official 545:5112d5ae6723 1696 #define DMA_CMAR2_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
mbed_official 545:5112d5ae6723 1697
mbed_official 545:5112d5ae6723 1698 /****************** Bit definition for DMA_CMAR3 register *******************/
mbed_official 545:5112d5ae6723 1699 #define DMA_CMAR3_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
mbed_official 545:5112d5ae6723 1700
mbed_official 545:5112d5ae6723 1701
mbed_official 545:5112d5ae6723 1702 /****************** Bit definition for DMA_CMAR4 register *******************/
mbed_official 545:5112d5ae6723 1703 #define DMA_CMAR4_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
mbed_official 545:5112d5ae6723 1704
mbed_official 545:5112d5ae6723 1705 /****************** Bit definition for DMA_CMAR5 register *******************/
mbed_official 545:5112d5ae6723 1706 #define DMA_CMAR5_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
mbed_official 545:5112d5ae6723 1707
mbed_official 545:5112d5ae6723 1708 /****************** Bit definition for DMA_CMAR6 register *******************/
mbed_official 545:5112d5ae6723 1709 #define DMA_CMAR6_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
mbed_official 545:5112d5ae6723 1710
mbed_official 545:5112d5ae6723 1711 /****************** Bit definition for DMA_CMAR7 register *******************/
mbed_official 545:5112d5ae6723 1712 #define DMA_CMAR7_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
mbed_official 545:5112d5ae6723 1713
mbed_official 545:5112d5ae6723 1714 /******************************************************************************/
mbed_official 545:5112d5ae6723 1715 /* */
mbed_official 545:5112d5ae6723 1716 /* External Interrupt/Event Controller (EXTI) */
mbed_official 545:5112d5ae6723 1717 /* */
mbed_official 545:5112d5ae6723 1718 /******************************************************************************/
mbed_official 545:5112d5ae6723 1719
mbed_official 545:5112d5ae6723 1720 /******************* Bit definition for EXTI_IMR register *******************/
mbed_official 545:5112d5ae6723 1721 #define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
mbed_official 545:5112d5ae6723 1722 #define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
mbed_official 545:5112d5ae6723 1723 #define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
mbed_official 545:5112d5ae6723 1724 #define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
mbed_official 545:5112d5ae6723 1725 #define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
mbed_official 545:5112d5ae6723 1726 #define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
mbed_official 545:5112d5ae6723 1727 #define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
mbed_official 545:5112d5ae6723 1728 #define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
mbed_official 545:5112d5ae6723 1729 #define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
mbed_official 545:5112d5ae6723 1730 #define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
mbed_official 545:5112d5ae6723 1731 #define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
mbed_official 545:5112d5ae6723 1732 #define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
mbed_official 545:5112d5ae6723 1733 #define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
mbed_official 545:5112d5ae6723 1734 #define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
mbed_official 545:5112d5ae6723 1735 #define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
mbed_official 545:5112d5ae6723 1736 #define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
mbed_official 545:5112d5ae6723 1737 #define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
mbed_official 545:5112d5ae6723 1738 #define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
mbed_official 545:5112d5ae6723 1739 #define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
mbed_official 545:5112d5ae6723 1740 #define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
mbed_official 545:5112d5ae6723 1741 #define EXTI_IMR_MR20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */
mbed_official 545:5112d5ae6723 1742 #define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */
mbed_official 545:5112d5ae6723 1743 #define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */
mbed_official 545:5112d5ae6723 1744 #define EXTI_IMR_MR23 ((uint32_t)0x00800000) /*!< Interrupt Mask on line 23 */
mbed_official 545:5112d5ae6723 1745
mbed_official 545:5112d5ae6723 1746 /******************* Bit definition for EXTI_EMR register *******************/
mbed_official 545:5112d5ae6723 1747 #define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
mbed_official 545:5112d5ae6723 1748 #define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
mbed_official 545:5112d5ae6723 1749 #define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
mbed_official 545:5112d5ae6723 1750 #define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
mbed_official 545:5112d5ae6723 1751 #define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
mbed_official 545:5112d5ae6723 1752 #define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
mbed_official 545:5112d5ae6723 1753 #define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
mbed_official 545:5112d5ae6723 1754 #define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
mbed_official 545:5112d5ae6723 1755 #define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
mbed_official 545:5112d5ae6723 1756 #define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
mbed_official 545:5112d5ae6723 1757 #define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
mbed_official 545:5112d5ae6723 1758 #define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
mbed_official 545:5112d5ae6723 1759 #define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
mbed_official 545:5112d5ae6723 1760 #define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
mbed_official 545:5112d5ae6723 1761 #define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
mbed_official 545:5112d5ae6723 1762 #define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
mbed_official 545:5112d5ae6723 1763 #define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
mbed_official 545:5112d5ae6723 1764 #define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
mbed_official 545:5112d5ae6723 1765 #define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
mbed_official 545:5112d5ae6723 1766 #define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
mbed_official 545:5112d5ae6723 1767 #define EXTI_EMR_MR20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */
mbed_official 545:5112d5ae6723 1768 #define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */
mbed_official 545:5112d5ae6723 1769 #define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */
mbed_official 545:5112d5ae6723 1770 #define EXTI_EMR_MR23 ((uint32_t)0x00800000) /*!< Event Mask on line 23 */
mbed_official 545:5112d5ae6723 1771
mbed_official 545:5112d5ae6723 1772 /****************** Bit definition for EXTI_RTSR register *******************/
mbed_official 545:5112d5ae6723 1773 #define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
mbed_official 545:5112d5ae6723 1774 #define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
mbed_official 545:5112d5ae6723 1775 #define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
mbed_official 545:5112d5ae6723 1776 #define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
mbed_official 545:5112d5ae6723 1777 #define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
mbed_official 545:5112d5ae6723 1778 #define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
mbed_official 545:5112d5ae6723 1779 #define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
mbed_official 545:5112d5ae6723 1780 #define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
mbed_official 545:5112d5ae6723 1781 #define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
mbed_official 545:5112d5ae6723 1782 #define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
mbed_official 545:5112d5ae6723 1783 #define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
mbed_official 545:5112d5ae6723 1784 #define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
mbed_official 545:5112d5ae6723 1785 #define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
mbed_official 545:5112d5ae6723 1786 #define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
mbed_official 545:5112d5ae6723 1787 #define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
mbed_official 545:5112d5ae6723 1788 #define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
mbed_official 545:5112d5ae6723 1789 #define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
mbed_official 545:5112d5ae6723 1790 #define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
mbed_official 545:5112d5ae6723 1791 #define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
mbed_official 545:5112d5ae6723 1792 #define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
mbed_official 545:5112d5ae6723 1793 #define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
mbed_official 545:5112d5ae6723 1794 #define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
mbed_official 545:5112d5ae6723 1795 #define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
mbed_official 545:5112d5ae6723 1796 #define EXTI_RTSR_TR23 ((uint32_t)0x00800000) /*!< Rising trigger event configuration bit of line 23 */
mbed_official 545:5112d5ae6723 1797
mbed_official 545:5112d5ae6723 1798 /****************** Bit definition for EXTI_FTSR register *******************/
mbed_official 545:5112d5ae6723 1799 #define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
mbed_official 545:5112d5ae6723 1800 #define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
mbed_official 545:5112d5ae6723 1801 #define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
mbed_official 545:5112d5ae6723 1802 #define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
mbed_official 545:5112d5ae6723 1803 #define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
mbed_official 545:5112d5ae6723 1804 #define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
mbed_official 545:5112d5ae6723 1805 #define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
mbed_official 545:5112d5ae6723 1806 #define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
mbed_official 545:5112d5ae6723 1807 #define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
mbed_official 545:5112d5ae6723 1808 #define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
mbed_official 545:5112d5ae6723 1809 #define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
mbed_official 545:5112d5ae6723 1810 #define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
mbed_official 545:5112d5ae6723 1811 #define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
mbed_official 545:5112d5ae6723 1812 #define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
mbed_official 545:5112d5ae6723 1813 #define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
mbed_official 545:5112d5ae6723 1814 #define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
mbed_official 545:5112d5ae6723 1815 #define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
mbed_official 545:5112d5ae6723 1816 #define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
mbed_official 545:5112d5ae6723 1817 #define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
mbed_official 545:5112d5ae6723 1818 #define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
mbed_official 545:5112d5ae6723 1819 #define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
mbed_official 545:5112d5ae6723 1820 #define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
mbed_official 545:5112d5ae6723 1821 #define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
mbed_official 545:5112d5ae6723 1822 #define EXTI_FTSR_TR23 ((uint32_t)0x00800000) /*!< Falling trigger event configuration bit of line 23 */
mbed_official 545:5112d5ae6723 1823
mbed_official 545:5112d5ae6723 1824 /****************** Bit definition for EXTI_SWIER register ******************/
mbed_official 545:5112d5ae6723 1825 #define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
mbed_official 545:5112d5ae6723 1826 #define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
mbed_official 545:5112d5ae6723 1827 #define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
mbed_official 545:5112d5ae6723 1828 #define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
mbed_official 545:5112d5ae6723 1829 #define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
mbed_official 545:5112d5ae6723 1830 #define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
mbed_official 545:5112d5ae6723 1831 #define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
mbed_official 545:5112d5ae6723 1832 #define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
mbed_official 545:5112d5ae6723 1833 #define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
mbed_official 545:5112d5ae6723 1834 #define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
mbed_official 545:5112d5ae6723 1835 #define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
mbed_official 545:5112d5ae6723 1836 #define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
mbed_official 545:5112d5ae6723 1837 #define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
mbed_official 545:5112d5ae6723 1838 #define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
mbed_official 545:5112d5ae6723 1839 #define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
mbed_official 545:5112d5ae6723 1840 #define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
mbed_official 545:5112d5ae6723 1841 #define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
mbed_official 545:5112d5ae6723 1842 #define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
mbed_official 545:5112d5ae6723 1843 #define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
mbed_official 545:5112d5ae6723 1844 #define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
mbed_official 545:5112d5ae6723 1845 #define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
mbed_official 545:5112d5ae6723 1846 #define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
mbed_official 545:5112d5ae6723 1847 #define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
mbed_official 545:5112d5ae6723 1848 #define EXTI_SWIER_SWIER23 ((uint32_t)0x00800000) /*!< Software Interrupt on line 23 */
mbed_official 545:5112d5ae6723 1849
mbed_official 545:5112d5ae6723 1850 /******************* Bit definition for EXTI_PR register ********************/
mbed_official 545:5112d5ae6723 1851 #define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit 0 */
mbed_official 545:5112d5ae6723 1852 #define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit 1 */
mbed_official 545:5112d5ae6723 1853 #define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit 2 */
mbed_official 545:5112d5ae6723 1854 #define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit 3 */
mbed_official 545:5112d5ae6723 1855 #define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit 4 */
mbed_official 545:5112d5ae6723 1856 #define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit 5 */
mbed_official 545:5112d5ae6723 1857 #define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit 6 */
mbed_official 545:5112d5ae6723 1858 #define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit 7 */
mbed_official 545:5112d5ae6723 1859 #define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit 8 */
mbed_official 545:5112d5ae6723 1860 #define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit 9 */
mbed_official 545:5112d5ae6723 1861 #define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit 10 */
mbed_official 545:5112d5ae6723 1862 #define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit 11 */
mbed_official 545:5112d5ae6723 1863 #define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit 12 */
mbed_official 545:5112d5ae6723 1864 #define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit 13 */
mbed_official 545:5112d5ae6723 1865 #define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit 14 */
mbed_official 545:5112d5ae6723 1866 #define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit 15 */
mbed_official 545:5112d5ae6723 1867 #define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit 16 */
mbed_official 545:5112d5ae6723 1868 #define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit 17 */
mbed_official 545:5112d5ae6723 1869 #define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit 18 */
mbed_official 545:5112d5ae6723 1870 #define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit 19 */
mbed_official 545:5112d5ae6723 1871 #define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit 20 */
mbed_official 545:5112d5ae6723 1872 #define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit 21 */
mbed_official 545:5112d5ae6723 1873 #define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit 22 */
mbed_official 545:5112d5ae6723 1874 #define EXTI_PR_PR23 ((uint32_t)0x00800000) /*!< Pending bit 23 */
mbed_official 545:5112d5ae6723 1875
mbed_official 545:5112d5ae6723 1876 /******************************************************************************/
mbed_official 545:5112d5ae6723 1877 /* */
mbed_official 545:5112d5ae6723 1878 /* FLASH, DATA EEPROM and Option Bytes Registers */
mbed_official 545:5112d5ae6723 1879 /* (FLASH, DATA_EEPROM, OB) */
mbed_official 545:5112d5ae6723 1880 /* */
mbed_official 545:5112d5ae6723 1881 /******************************************************************************/
mbed_official 545:5112d5ae6723 1882
mbed_official 545:5112d5ae6723 1883 /******************* Bit definition for FLASH_ACR register ******************/
mbed_official 545:5112d5ae6723 1884 #define FLASH_ACR_LATENCY ((uint32_t)0x00000001) /*!< Latency */
mbed_official 545:5112d5ae6723 1885 #define FLASH_ACR_PRFTEN ((uint32_t)0x00000002) /*!< Prefetch Buffer Enable */
mbed_official 545:5112d5ae6723 1886 #define FLASH_ACR_ACC64 ((uint32_t)0x00000004) /*!< Access 64 bits */
mbed_official 545:5112d5ae6723 1887 #define FLASH_ACR_SLEEP_PD ((uint32_t)0x00000008) /*!< Flash mode during sleep mode */
mbed_official 545:5112d5ae6723 1888 #define FLASH_ACR_RUN_PD ((uint32_t)0x00000010) /*!< Flash mode during RUN mode */
mbed_official 545:5112d5ae6723 1889
mbed_official 545:5112d5ae6723 1890 /******************* Bit definition for FLASH_PECR register ******************/
mbed_official 545:5112d5ae6723 1891 #define FLASH_PECR_PELOCK ((uint32_t)0x00000001) /*!< FLASH_PECR and Flash data Lock */
mbed_official 545:5112d5ae6723 1892 #define FLASH_PECR_PRGLOCK ((uint32_t)0x00000002) /*!< Program matrix Lock */
mbed_official 545:5112d5ae6723 1893 #define FLASH_PECR_OPTLOCK ((uint32_t)0x00000004) /*!< Option byte matrix Lock */
mbed_official 545:5112d5ae6723 1894 #define FLASH_PECR_PROG ((uint32_t)0x00000008) /*!< Program matrix selection */
mbed_official 545:5112d5ae6723 1895 #define FLASH_PECR_DATA ((uint32_t)0x00000010) /*!< Data matrix selection */
mbed_official 545:5112d5ae6723 1896 #define FLASH_PECR_FTDW ((uint32_t)0x00000100) /*!< Fixed Time Data write for Word/Half Word/Byte programming */
mbed_official 545:5112d5ae6723 1897 #define FLASH_PECR_ERASE ((uint32_t)0x00000200) /*!< Page erasing mode */
mbed_official 545:5112d5ae6723 1898 #define FLASH_PECR_FPRG ((uint32_t)0x00000400) /*!< Fast Page/Half Page programming mode */
mbed_official 545:5112d5ae6723 1899 #define FLASH_PECR_EOPIE ((uint32_t)0x00010000) /*!< End of programming interrupt */
mbed_official 545:5112d5ae6723 1900 #define FLASH_PECR_ERRIE ((uint32_t)0x00020000) /*!< Error interrupt */
mbed_official 545:5112d5ae6723 1901 #define FLASH_PECR_OBL_LAUNCH ((uint32_t)0x00040000) /*!< Launch the option byte loading */
mbed_official 545:5112d5ae6723 1902
mbed_official 545:5112d5ae6723 1903 /****************** Bit definition for FLASH_PDKEYR register ******************/
mbed_official 545:5112d5ae6723 1904 #define FLASH_PDKEYR_PDKEYR ((uint32_t)0xFFFFFFFF) /*!< FLASH_PEC and data matrix Key */
mbed_official 545:5112d5ae6723 1905
mbed_official 545:5112d5ae6723 1906 /****************** Bit definition for FLASH_PEKEYR register ******************/
mbed_official 545:5112d5ae6723 1907 #define FLASH_PEKEYR_PEKEYR ((uint32_t)0xFFFFFFFF) /*!< FLASH_PEC and data matrix Key */
mbed_official 545:5112d5ae6723 1908
mbed_official 545:5112d5ae6723 1909 /****************** Bit definition for FLASH_PRGKEYR register ******************/
mbed_official 545:5112d5ae6723 1910 #define FLASH_PRGKEYR_PRGKEYR ((uint32_t)0xFFFFFFFF) /*!< Program matrix Key */
mbed_official 545:5112d5ae6723 1911
mbed_official 545:5112d5ae6723 1912 /****************** Bit definition for FLASH_OPTKEYR register ******************/
mbed_official 545:5112d5ae6723 1913 #define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!< Option bytes matrix Key */
mbed_official 545:5112d5ae6723 1914
mbed_official 545:5112d5ae6723 1915 /****************** Bit definition for FLASH_SR register *******************/
mbed_official 545:5112d5ae6723 1916 #define FLASH_SR_BSY ((uint32_t)0x00000001) /*!< Busy */
mbed_official 545:5112d5ae6723 1917 #define FLASH_SR_EOP ((uint32_t)0x00000002) /*!< End Of Programming*/
mbed_official 545:5112d5ae6723 1918 #define FLASH_SR_ENDHV ((uint32_t)0x00000004) /*!< End of high voltage */
mbed_official 545:5112d5ae6723 1919 #define FLASH_SR_READY ((uint32_t)0x00000008) /*!< Flash ready after low power mode */
mbed_official 545:5112d5ae6723 1920
mbed_official 545:5112d5ae6723 1921 #define FLASH_SR_WRPERR ((uint32_t)0x00000100) /*!< Write protected error */
mbed_official 545:5112d5ae6723 1922 #define FLASH_SR_PGAERR ((uint32_t)0x00000200) /*!< Programming Alignment Error */
mbed_official 545:5112d5ae6723 1923 #define FLASH_SR_SIZERR ((uint32_t)0x00000400) /*!< Size error */
mbed_official 545:5112d5ae6723 1924 #define FLASH_SR_OPTVERR ((uint32_t)0x00000800) /*!< Option validity error */
mbed_official 545:5112d5ae6723 1925 #define FLASH_SR_OPTVERRUSR ((uint32_t)0x00001000) /*!< Option User validity error */
mbed_official 545:5112d5ae6723 1926 #define FLASH_SR_RDERR ((uint32_t)0x00002000) /*!< Read protected error */
mbed_official 545:5112d5ae6723 1927
mbed_official 545:5112d5ae6723 1928 /****************** Bit definition for FLASH_OBR register *******************/
mbed_official 545:5112d5ae6723 1929 #define FLASH_OBR_RDPRT ((uint32_t)0x000000FF) /*!< Read Protection */
mbed_official 545:5112d5ae6723 1930 #define FLASH_OBR_SPRMOD ((uint32_t)0x00000100) /*!< Selection of protection mode of WPRi bits */
mbed_official 545:5112d5ae6723 1931 #define FLASH_OBR_BOR_LEV ((uint32_t)0x000F0000) /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/
mbed_official 545:5112d5ae6723 1932 #define FLASH_OBR_USER ((uint32_t)0x00700000) /*!< User Option Bytes */
mbed_official 545:5112d5ae6723 1933 #define FLASH_OBR_IWDG_SW ((uint32_t)0x00100000) /*!< IWDG_SW */
mbed_official 545:5112d5ae6723 1934 #define FLASH_OBR_nRST_STOP ((uint32_t)0x00200000) /*!< nRST_STOP */
mbed_official 545:5112d5ae6723 1935 #define FLASH_OBR_nRST_STDBY ((uint32_t)0x00400000) /*!< nRST_STDBY */
mbed_official 545:5112d5ae6723 1936
mbed_official 545:5112d5ae6723 1937 /****************** Bit definition for FLASH_WRPR register ******************/
mbed_official 545:5112d5ae6723 1938 #define FLASH_WRPR1_WRP ((uint32_t)0xFFFFFFFF) /*!< Write Protect */
mbed_official 545:5112d5ae6723 1939 #define FLASH_WRPR2_WRP ((uint32_t)0xFFFFFFFF) /*!< Write Protect */
mbed_official 545:5112d5ae6723 1940
mbed_official 545:5112d5ae6723 1941 /******************************************************************************/
mbed_official 545:5112d5ae6723 1942 /* */
mbed_official 545:5112d5ae6723 1943 /* General Purpose I/O */
mbed_official 545:5112d5ae6723 1944 /* */
mbed_official 545:5112d5ae6723 1945 /******************************************************************************/
mbed_official 545:5112d5ae6723 1946 /****************** Bits definition for GPIO_MODER register *****************/
mbed_official 545:5112d5ae6723 1947 #define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
mbed_official 545:5112d5ae6723 1948 #define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
mbed_official 545:5112d5ae6723 1949 #define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
mbed_official 545:5112d5ae6723 1950
mbed_official 545:5112d5ae6723 1951 #define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
mbed_official 545:5112d5ae6723 1952 #define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
mbed_official 545:5112d5ae6723 1953 #define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
mbed_official 545:5112d5ae6723 1954
mbed_official 545:5112d5ae6723 1955 #define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
mbed_official 545:5112d5ae6723 1956 #define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
mbed_official 545:5112d5ae6723 1957 #define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
mbed_official 545:5112d5ae6723 1958
mbed_official 545:5112d5ae6723 1959 #define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
mbed_official 545:5112d5ae6723 1960 #define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
mbed_official 545:5112d5ae6723 1961 #define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
mbed_official 545:5112d5ae6723 1962
mbed_official 545:5112d5ae6723 1963 #define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
mbed_official 545:5112d5ae6723 1964 #define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
mbed_official 545:5112d5ae6723 1965 #define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
mbed_official 545:5112d5ae6723 1966
mbed_official 545:5112d5ae6723 1967 #define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
mbed_official 545:5112d5ae6723 1968 #define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
mbed_official 545:5112d5ae6723 1969 #define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
mbed_official 545:5112d5ae6723 1970
mbed_official 545:5112d5ae6723 1971 #define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
mbed_official 545:5112d5ae6723 1972 #define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
mbed_official 545:5112d5ae6723 1973 #define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
mbed_official 545:5112d5ae6723 1974
mbed_official 545:5112d5ae6723 1975 #define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
mbed_official 545:5112d5ae6723 1976 #define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
mbed_official 545:5112d5ae6723 1977 #define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
mbed_official 545:5112d5ae6723 1978
mbed_official 545:5112d5ae6723 1979 #define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
mbed_official 545:5112d5ae6723 1980 #define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
mbed_official 545:5112d5ae6723 1981 #define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
mbed_official 545:5112d5ae6723 1982
mbed_official 545:5112d5ae6723 1983 #define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
mbed_official 545:5112d5ae6723 1984 #define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
mbed_official 545:5112d5ae6723 1985 #define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
mbed_official 545:5112d5ae6723 1986
mbed_official 545:5112d5ae6723 1987 #define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
mbed_official 545:5112d5ae6723 1988 #define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
mbed_official 545:5112d5ae6723 1989 #define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
mbed_official 545:5112d5ae6723 1990
mbed_official 545:5112d5ae6723 1991 #define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
mbed_official 545:5112d5ae6723 1992 #define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
mbed_official 545:5112d5ae6723 1993 #define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
mbed_official 545:5112d5ae6723 1994
mbed_official 545:5112d5ae6723 1995 #define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
mbed_official 545:5112d5ae6723 1996 #define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
mbed_official 545:5112d5ae6723 1997 #define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
mbed_official 545:5112d5ae6723 1998
mbed_official 545:5112d5ae6723 1999 #define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
mbed_official 545:5112d5ae6723 2000 #define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
mbed_official 545:5112d5ae6723 2001 #define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
mbed_official 545:5112d5ae6723 2002
mbed_official 545:5112d5ae6723 2003 #define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
mbed_official 545:5112d5ae6723 2004 #define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
mbed_official 545:5112d5ae6723 2005 #define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
mbed_official 545:5112d5ae6723 2006
mbed_official 545:5112d5ae6723 2007 #define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
mbed_official 545:5112d5ae6723 2008 #define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
mbed_official 545:5112d5ae6723 2009 #define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
mbed_official 545:5112d5ae6723 2010
mbed_official 545:5112d5ae6723 2011 /****************** Bits definition for GPIO_OTYPER register ****************/
mbed_official 545:5112d5ae6723 2012 #define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
mbed_official 545:5112d5ae6723 2013 #define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
mbed_official 545:5112d5ae6723 2014 #define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
mbed_official 545:5112d5ae6723 2015 #define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
mbed_official 545:5112d5ae6723 2016 #define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
mbed_official 545:5112d5ae6723 2017 #define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
mbed_official 545:5112d5ae6723 2018 #define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
mbed_official 545:5112d5ae6723 2019 #define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
mbed_official 545:5112d5ae6723 2020 #define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
mbed_official 545:5112d5ae6723 2021 #define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
mbed_official 545:5112d5ae6723 2022 #define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
mbed_official 545:5112d5ae6723 2023 #define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
mbed_official 545:5112d5ae6723 2024 #define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
mbed_official 545:5112d5ae6723 2025 #define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
mbed_official 545:5112d5ae6723 2026 #define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
mbed_official 545:5112d5ae6723 2027 #define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
mbed_official 545:5112d5ae6723 2028
mbed_official 545:5112d5ae6723 2029 /****************** Bits definition for GPIO_OSPEEDR register ***************/
mbed_official 545:5112d5ae6723 2030 #define GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003)
mbed_official 545:5112d5ae6723 2031 #define GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001)
mbed_official 545:5112d5ae6723 2032 #define GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002)
mbed_official 545:5112d5ae6723 2033
mbed_official 545:5112d5ae6723 2034 #define GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C)
mbed_official 545:5112d5ae6723 2035 #define GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004)
mbed_official 545:5112d5ae6723 2036 #define GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008)
mbed_official 545:5112d5ae6723 2037
mbed_official 545:5112d5ae6723 2038 #define GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030)
mbed_official 545:5112d5ae6723 2039 #define GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010)
mbed_official 545:5112d5ae6723 2040 #define GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020)
mbed_official 545:5112d5ae6723 2041
mbed_official 545:5112d5ae6723 2042 #define GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0)
mbed_official 545:5112d5ae6723 2043 #define GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040)
mbed_official 545:5112d5ae6723 2044 #define GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080)
mbed_official 545:5112d5ae6723 2045
mbed_official 545:5112d5ae6723 2046 #define GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300)
mbed_official 545:5112d5ae6723 2047 #define GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100)
mbed_official 545:5112d5ae6723 2048 #define GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200)
mbed_official 545:5112d5ae6723 2049
mbed_official 545:5112d5ae6723 2050 #define GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00)
mbed_official 545:5112d5ae6723 2051 #define GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400)
mbed_official 545:5112d5ae6723 2052 #define GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800)
mbed_official 545:5112d5ae6723 2053
mbed_official 545:5112d5ae6723 2054 #define GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000)
mbed_official 545:5112d5ae6723 2055 #define GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000)
mbed_official 545:5112d5ae6723 2056 #define GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000)
mbed_official 545:5112d5ae6723 2057
mbed_official 545:5112d5ae6723 2058 #define GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000)
mbed_official 545:5112d5ae6723 2059 #define GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000)
mbed_official 545:5112d5ae6723 2060 #define GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000)
mbed_official 545:5112d5ae6723 2061
mbed_official 545:5112d5ae6723 2062 #define GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000)
mbed_official 545:5112d5ae6723 2063 #define GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000)
mbed_official 545:5112d5ae6723 2064 #define GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000)
mbed_official 545:5112d5ae6723 2065
mbed_official 545:5112d5ae6723 2066 #define GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000)
mbed_official 545:5112d5ae6723 2067 #define GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000)
mbed_official 545:5112d5ae6723 2068 #define GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000)
mbed_official 545:5112d5ae6723 2069
mbed_official 545:5112d5ae6723 2070 #define GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000)
mbed_official 545:5112d5ae6723 2071 #define GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000)
mbed_official 545:5112d5ae6723 2072 #define GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000)
mbed_official 545:5112d5ae6723 2073
mbed_official 545:5112d5ae6723 2074 #define GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000)
mbed_official 545:5112d5ae6723 2075 #define GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000)
mbed_official 545:5112d5ae6723 2076 #define GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000)
mbed_official 545:5112d5ae6723 2077
mbed_official 545:5112d5ae6723 2078 #define GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000)
mbed_official 545:5112d5ae6723 2079 #define GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000)
mbed_official 545:5112d5ae6723 2080 #define GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000)
mbed_official 545:5112d5ae6723 2081
mbed_official 545:5112d5ae6723 2082 #define GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000)
mbed_official 545:5112d5ae6723 2083 #define GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000)
mbed_official 545:5112d5ae6723 2084 #define GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000)
mbed_official 545:5112d5ae6723 2085
mbed_official 545:5112d5ae6723 2086 #define GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000)
mbed_official 545:5112d5ae6723 2087 #define GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000)
mbed_official 545:5112d5ae6723 2088 #define GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000)
mbed_official 545:5112d5ae6723 2089
mbed_official 545:5112d5ae6723 2090 #define GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000)
mbed_official 545:5112d5ae6723 2091 #define GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000)
mbed_official 545:5112d5ae6723 2092 #define GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000)
mbed_official 545:5112d5ae6723 2093
mbed_official 545:5112d5ae6723 2094 /****************** Bits definition for GPIO_PUPDR register *****************/
mbed_official 545:5112d5ae6723 2095 #define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
mbed_official 545:5112d5ae6723 2096 #define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
mbed_official 545:5112d5ae6723 2097 #define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
mbed_official 545:5112d5ae6723 2098
mbed_official 545:5112d5ae6723 2099 #define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
mbed_official 545:5112d5ae6723 2100 #define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
mbed_official 545:5112d5ae6723 2101 #define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
mbed_official 545:5112d5ae6723 2102
mbed_official 545:5112d5ae6723 2103 #define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
mbed_official 545:5112d5ae6723 2104 #define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
mbed_official 545:5112d5ae6723 2105 #define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
mbed_official 545:5112d5ae6723 2106
mbed_official 545:5112d5ae6723 2107 #define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
mbed_official 545:5112d5ae6723 2108 #define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
mbed_official 545:5112d5ae6723 2109 #define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
mbed_official 545:5112d5ae6723 2110
mbed_official 545:5112d5ae6723 2111 #define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
mbed_official 545:5112d5ae6723 2112 #define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
mbed_official 545:5112d5ae6723 2113 #define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
mbed_official 545:5112d5ae6723 2114
mbed_official 545:5112d5ae6723 2115 #define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
mbed_official 545:5112d5ae6723 2116 #define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
mbed_official 545:5112d5ae6723 2117 #define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
mbed_official 545:5112d5ae6723 2118
mbed_official 545:5112d5ae6723 2119 #define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
mbed_official 545:5112d5ae6723 2120 #define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
mbed_official 545:5112d5ae6723 2121 #define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
mbed_official 545:5112d5ae6723 2122
mbed_official 545:5112d5ae6723 2123 #define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
mbed_official 545:5112d5ae6723 2124 #define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
mbed_official 545:5112d5ae6723 2125 #define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
mbed_official 545:5112d5ae6723 2126
mbed_official 545:5112d5ae6723 2127 #define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
mbed_official 545:5112d5ae6723 2128 #define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
mbed_official 545:5112d5ae6723 2129 #define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
mbed_official 545:5112d5ae6723 2130
mbed_official 545:5112d5ae6723 2131 #define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
mbed_official 545:5112d5ae6723 2132 #define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
mbed_official 545:5112d5ae6723 2133 #define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
mbed_official 545:5112d5ae6723 2134
mbed_official 545:5112d5ae6723 2135 #define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
mbed_official 545:5112d5ae6723 2136 #define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
mbed_official 545:5112d5ae6723 2137 #define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
mbed_official 545:5112d5ae6723 2138
mbed_official 545:5112d5ae6723 2139 #define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
mbed_official 545:5112d5ae6723 2140 #define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
mbed_official 545:5112d5ae6723 2141 #define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
mbed_official 545:5112d5ae6723 2142
mbed_official 545:5112d5ae6723 2143 #define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
mbed_official 545:5112d5ae6723 2144 #define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
mbed_official 545:5112d5ae6723 2145 #define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
mbed_official 545:5112d5ae6723 2146
mbed_official 545:5112d5ae6723 2147 #define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
mbed_official 545:5112d5ae6723 2148 #define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
mbed_official 545:5112d5ae6723 2149 #define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
mbed_official 545:5112d5ae6723 2150
mbed_official 545:5112d5ae6723 2151 #define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
mbed_official 545:5112d5ae6723 2152 #define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
mbed_official 545:5112d5ae6723 2153 #define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
mbed_official 545:5112d5ae6723 2154 #define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
mbed_official 545:5112d5ae6723 2155 #define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
mbed_official 545:5112d5ae6723 2156 #define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
mbed_official 545:5112d5ae6723 2157
mbed_official 545:5112d5ae6723 2158 /****************** Bits definition for GPIO_IDR register *******************/
mbed_official 545:5112d5ae6723 2159 #define GPIO_IDR_IDR_0 ((uint32_t)0x00000001)
mbed_official 545:5112d5ae6723 2160 #define GPIO_IDR_IDR_1 ((uint32_t)0x00000002)
mbed_official 545:5112d5ae6723 2161 #define GPIO_IDR_IDR_2 ((uint32_t)0x00000004)
mbed_official 545:5112d5ae6723 2162 #define GPIO_IDR_IDR_3 ((uint32_t)0x00000008)
mbed_official 545:5112d5ae6723 2163 #define GPIO_IDR_IDR_4 ((uint32_t)0x00000010)
mbed_official 545:5112d5ae6723 2164 #define GPIO_IDR_IDR_5 ((uint32_t)0x00000020)
mbed_official 545:5112d5ae6723 2165 #define GPIO_IDR_IDR_6 ((uint32_t)0x00000040)
mbed_official 545:5112d5ae6723 2166 #define GPIO_IDR_IDR_7 ((uint32_t)0x00000080)
mbed_official 545:5112d5ae6723 2167 #define GPIO_IDR_IDR_8 ((uint32_t)0x00000100)
mbed_official 545:5112d5ae6723 2168 #define GPIO_IDR_IDR_9 ((uint32_t)0x00000200)
mbed_official 545:5112d5ae6723 2169 #define GPIO_IDR_IDR_10 ((uint32_t)0x00000400)
mbed_official 545:5112d5ae6723 2170 #define GPIO_IDR_IDR_11 ((uint32_t)0x00000800)
mbed_official 545:5112d5ae6723 2171 #define GPIO_IDR_IDR_12 ((uint32_t)0x00001000)
mbed_official 545:5112d5ae6723 2172 #define GPIO_IDR_IDR_13 ((uint32_t)0x00002000)
mbed_official 545:5112d5ae6723 2173 #define GPIO_IDR_IDR_14 ((uint32_t)0x00004000)
mbed_official 545:5112d5ae6723 2174 #define GPIO_IDR_IDR_15 ((uint32_t)0x00008000)
mbed_official 545:5112d5ae6723 2175
mbed_official 545:5112d5ae6723 2176 /****************** Bits definition for GPIO_ODR register *******************/
mbed_official 545:5112d5ae6723 2177 #define GPIO_ODR_ODR_0 ((uint32_t)0x00000001)
mbed_official 545:5112d5ae6723 2178 #define GPIO_ODR_ODR_1 ((uint32_t)0x00000002)
mbed_official 545:5112d5ae6723 2179 #define GPIO_ODR_ODR_2 ((uint32_t)0x00000004)
mbed_official 545:5112d5ae6723 2180 #define GPIO_ODR_ODR_3 ((uint32_t)0x00000008)
mbed_official 545:5112d5ae6723 2181 #define GPIO_ODR_ODR_4 ((uint32_t)0x00000010)
mbed_official 545:5112d5ae6723 2182 #define GPIO_ODR_ODR_5 ((uint32_t)0x00000020)
mbed_official 545:5112d5ae6723 2183 #define GPIO_ODR_ODR_6 ((uint32_t)0x00000040)
mbed_official 545:5112d5ae6723 2184 #define GPIO_ODR_ODR_7 ((uint32_t)0x00000080)
mbed_official 545:5112d5ae6723 2185 #define GPIO_ODR_ODR_8 ((uint32_t)0x00000100)
mbed_official 545:5112d5ae6723 2186 #define GPIO_ODR_ODR_9 ((uint32_t)0x00000200)
mbed_official 545:5112d5ae6723 2187 #define GPIO_ODR_ODR_10 ((uint32_t)0x00000400)
mbed_official 545:5112d5ae6723 2188 #define GPIO_ODR_ODR_11 ((uint32_t)0x00000800)
mbed_official 545:5112d5ae6723 2189 #define GPIO_ODR_ODR_12 ((uint32_t)0x00001000)
mbed_official 545:5112d5ae6723 2190 #define GPIO_ODR_ODR_13 ((uint32_t)0x00002000)
mbed_official 545:5112d5ae6723 2191 #define GPIO_ODR_ODR_14 ((uint32_t)0x00004000)
mbed_official 545:5112d5ae6723 2192 #define GPIO_ODR_ODR_15 ((uint32_t)0x00008000)
mbed_official 545:5112d5ae6723 2193
mbed_official 545:5112d5ae6723 2194 /****************** Bits definition for GPIO_BSRR register ******************/
mbed_official 545:5112d5ae6723 2195 #define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
mbed_official 545:5112d5ae6723 2196 #define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
mbed_official 545:5112d5ae6723 2197 #define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
mbed_official 545:5112d5ae6723 2198 #define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
mbed_official 545:5112d5ae6723 2199 #define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
mbed_official 545:5112d5ae6723 2200 #define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
mbed_official 545:5112d5ae6723 2201 #define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
mbed_official 545:5112d5ae6723 2202 #define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
mbed_official 545:5112d5ae6723 2203 #define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
mbed_official 545:5112d5ae6723 2204 #define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
mbed_official 545:5112d5ae6723 2205 #define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
mbed_official 545:5112d5ae6723 2206 #define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
mbed_official 545:5112d5ae6723 2207 #define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
mbed_official 545:5112d5ae6723 2208 #define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
mbed_official 545:5112d5ae6723 2209 #define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
mbed_official 545:5112d5ae6723 2210 #define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
mbed_official 545:5112d5ae6723 2211 #define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
mbed_official 545:5112d5ae6723 2212 #define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
mbed_official 545:5112d5ae6723 2213 #define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
mbed_official 545:5112d5ae6723 2214 #define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
mbed_official 545:5112d5ae6723 2215 #define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
mbed_official 545:5112d5ae6723 2216 #define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
mbed_official 545:5112d5ae6723 2217 #define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
mbed_official 545:5112d5ae6723 2218 #define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
mbed_official 545:5112d5ae6723 2219 #define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
mbed_official 545:5112d5ae6723 2220 #define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
mbed_official 545:5112d5ae6723 2221 #define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
mbed_official 545:5112d5ae6723 2222 #define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
mbed_official 545:5112d5ae6723 2223 #define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
mbed_official 545:5112d5ae6723 2224 #define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
mbed_official 545:5112d5ae6723 2225 #define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
mbed_official 545:5112d5ae6723 2226 #define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
mbed_official 545:5112d5ae6723 2227
mbed_official 545:5112d5ae6723 2228 /****************** Bit definition for GPIO_LCKR register ********************/
mbed_official 545:5112d5ae6723 2229 #define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
mbed_official 545:5112d5ae6723 2230 #define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
mbed_official 545:5112d5ae6723 2231 #define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
mbed_official 545:5112d5ae6723 2232 #define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
mbed_official 545:5112d5ae6723 2233 #define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
mbed_official 545:5112d5ae6723 2234 #define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
mbed_official 545:5112d5ae6723 2235 #define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
mbed_official 545:5112d5ae6723 2236 #define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
mbed_official 545:5112d5ae6723 2237 #define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
mbed_official 545:5112d5ae6723 2238 #define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
mbed_official 545:5112d5ae6723 2239 #define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
mbed_official 545:5112d5ae6723 2240 #define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
mbed_official 545:5112d5ae6723 2241 #define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
mbed_official 545:5112d5ae6723 2242 #define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
mbed_official 545:5112d5ae6723 2243 #define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
mbed_official 545:5112d5ae6723 2244 #define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
mbed_official 545:5112d5ae6723 2245 #define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
mbed_official 545:5112d5ae6723 2246
mbed_official 545:5112d5ae6723 2247 /****************** Bit definition for GPIO_AFRL register ********************/
mbed_official 545:5112d5ae6723 2248 #define GPIO_AFRL_AFRL0 ((uint32_t)0x0000000F)
mbed_official 545:5112d5ae6723 2249 #define GPIO_AFRL_AFRL1 ((uint32_t)0x000000F0)
mbed_official 545:5112d5ae6723 2250 #define GPIO_AFRL_AFRL2 ((uint32_t)0x00000F00)
mbed_official 545:5112d5ae6723 2251 #define GPIO_AFRL_AFRL3 ((uint32_t)0x0000F000)
mbed_official 545:5112d5ae6723 2252 #define GPIO_AFRL_AFRL4 ((uint32_t)0x000F0000)
mbed_official 545:5112d5ae6723 2253 #define GPIO_AFRL_AFRL5 ((uint32_t)0x00F00000)
mbed_official 545:5112d5ae6723 2254 #define GPIO_AFRL_AFRL6 ((uint32_t)0x0F000000)
mbed_official 545:5112d5ae6723 2255 #define GPIO_AFRL_AFRL7 ((uint32_t)0xF0000000)
mbed_official 545:5112d5ae6723 2256
mbed_official 545:5112d5ae6723 2257 /****************** Bit definition for GPIO_AFRH register ********************/
mbed_official 545:5112d5ae6723 2258 #define GPIO_AFRH_AFRH0 ((uint32_t)0x0000000F)
mbed_official 545:5112d5ae6723 2259 #define GPIO_AFRH_AFRH1 ((uint32_t)0x000000F0)
mbed_official 545:5112d5ae6723 2260 #define GPIO_AFRH_AFRH2 ((uint32_t)0x00000F00)
mbed_official 545:5112d5ae6723 2261 #define GPIO_AFRH_AFRH3 ((uint32_t)0x0000F000)
mbed_official 545:5112d5ae6723 2262 #define GPIO_AFRH_AFRH4 ((uint32_t)0x000F0000)
mbed_official 545:5112d5ae6723 2263 #define GPIO_AFRH_AFRH5 ((uint32_t)0x00F00000)
mbed_official 545:5112d5ae6723 2264 #define GPIO_AFRH_AFRH6 ((uint32_t)0x0F000000)
mbed_official 545:5112d5ae6723 2265 #define GPIO_AFRH_AFRH7 ((uint32_t)0xF0000000)
mbed_official 545:5112d5ae6723 2266
mbed_official 545:5112d5ae6723 2267 /****************** Bit definition for GPIO_BRR register *********************/
mbed_official 545:5112d5ae6723 2268 #define GPIO_BRR_BR_0 ((uint32_t)0x00000001)
mbed_official 545:5112d5ae6723 2269 #define GPIO_BRR_BR_1 ((uint32_t)0x00000002)
mbed_official 545:5112d5ae6723 2270 #define GPIO_BRR_BR_2 ((uint32_t)0x00000004)
mbed_official 545:5112d5ae6723 2271 #define GPIO_BRR_BR_3 ((uint32_t)0x00000008)
mbed_official 545:5112d5ae6723 2272 #define GPIO_BRR_BR_4 ((uint32_t)0x00000010)
mbed_official 545:5112d5ae6723 2273 #define GPIO_BRR_BR_5 ((uint32_t)0x00000020)
mbed_official 545:5112d5ae6723 2274 #define GPIO_BRR_BR_6 ((uint32_t)0x00000040)
mbed_official 545:5112d5ae6723 2275 #define GPIO_BRR_BR_7 ((uint32_t)0x00000080)
mbed_official 545:5112d5ae6723 2276 #define GPIO_BRR_BR_8 ((uint32_t)0x00000100)
mbed_official 545:5112d5ae6723 2277 #define GPIO_BRR_BR_9 ((uint32_t)0x00000200)
mbed_official 545:5112d5ae6723 2278 #define GPIO_BRR_BR_10 ((uint32_t)0x00000400)
mbed_official 545:5112d5ae6723 2279 #define GPIO_BRR_BR_11 ((uint32_t)0x00000800)
mbed_official 545:5112d5ae6723 2280 #define GPIO_BRR_BR_12 ((uint32_t)0x00001000)
mbed_official 545:5112d5ae6723 2281 #define GPIO_BRR_BR_13 ((uint32_t)0x00002000)
mbed_official 545:5112d5ae6723 2282 #define GPIO_BRR_BR_14 ((uint32_t)0x00004000)
mbed_official 545:5112d5ae6723 2283 #define GPIO_BRR_BR_15 ((uint32_t)0x00008000)
mbed_official 545:5112d5ae6723 2284
mbed_official 545:5112d5ae6723 2285
mbed_official 545:5112d5ae6723 2286 /******************************************************************************/
mbed_official 545:5112d5ae6723 2287 /* */
mbed_official 545:5112d5ae6723 2288 /* Inter-integrated Circuit Interface (I2C) */
mbed_official 545:5112d5ae6723 2289 /* */
mbed_official 545:5112d5ae6723 2290 /******************************************************************************/
mbed_official 545:5112d5ae6723 2291
mbed_official 545:5112d5ae6723 2292 /******************* Bit definition for I2C_CR1 register ********************/
mbed_official 545:5112d5ae6723 2293 #define I2C_CR1_PE ((uint32_t)0x00000001) /*!< Peripheral Enable */
mbed_official 545:5112d5ae6723 2294 #define I2C_CR1_SMBUS ((uint32_t)0x00000002) /*!< SMBus Mode */
mbed_official 545:5112d5ae6723 2295 #define I2C_CR1_SMBTYPE ((uint32_t)0x00000008) /*!< SMBus Type */
mbed_official 545:5112d5ae6723 2296 #define I2C_CR1_ENARP ((uint32_t)0x00000010) /*!< ARP Enable */
mbed_official 545:5112d5ae6723 2297 #define I2C_CR1_ENPEC ((uint32_t)0x00000020) /*!< PEC Enable */
mbed_official 545:5112d5ae6723 2298 #define I2C_CR1_ENGC ((uint32_t)0x00000040) /*!< General Call Enable */
mbed_official 545:5112d5ae6723 2299 #define I2C_CR1_NOSTRETCH ((uint32_t)0x00000080) /*!< Clock Stretching Disable (Slave mode) */
mbed_official 545:5112d5ae6723 2300 #define I2C_CR1_START ((uint32_t)0x00000100) /*!< Start Generation */
mbed_official 545:5112d5ae6723 2301 #define I2C_CR1_STOP ((uint32_t)0x00000200) /*!< Stop Generation */
mbed_official 545:5112d5ae6723 2302 #define I2C_CR1_ACK ((uint32_t)0x00000400) /*!< Acknowledge Enable */
mbed_official 545:5112d5ae6723 2303 #define I2C_CR1_POS ((uint32_t)0x00000800) /*!< Acknowledge/PEC Position (for data reception) */
mbed_official 545:5112d5ae6723 2304 #define I2C_CR1_PEC ((uint32_t)0x00001000) /*!< Packet Error Checking */
mbed_official 545:5112d5ae6723 2305 #define I2C_CR1_ALERT ((uint32_t)0x00002000) /*!< SMBus Alert */
mbed_official 545:5112d5ae6723 2306 #define I2C_CR1_SWRST ((uint32_t)0x00008000) /*!< Software Reset */
mbed_official 545:5112d5ae6723 2307
mbed_official 545:5112d5ae6723 2308 /******************* Bit definition for I2C_CR2 register ********************/
mbed_official 545:5112d5ae6723 2309 #define I2C_CR2_FREQ ((uint32_t)0x0000003F) /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */
mbed_official 545:5112d5ae6723 2310 #define I2C_CR2_FREQ_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 2311 #define I2C_CR2_FREQ_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 2312 #define I2C_CR2_FREQ_2 ((uint32_t)0x00000004) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 2313 #define I2C_CR2_FREQ_3 ((uint32_t)0x00000008) /*!< Bit 3 */
mbed_official 545:5112d5ae6723 2314 #define I2C_CR2_FREQ_4 ((uint32_t)0x00000010) /*!< Bit 4 */
mbed_official 545:5112d5ae6723 2315 #define I2C_CR2_FREQ_5 ((uint32_t)0x00000020) /*!< Bit 5 */
mbed_official 545:5112d5ae6723 2316
mbed_official 545:5112d5ae6723 2317 #define I2C_CR2_ITERREN ((uint32_t)0x00000100) /*!< Error Interrupt Enable */
mbed_official 545:5112d5ae6723 2318 #define I2C_CR2_ITEVTEN ((uint32_t)0x00000200) /*!< Event Interrupt Enable */
mbed_official 545:5112d5ae6723 2319 #define I2C_CR2_ITBUFEN ((uint32_t)0x00000400) /*!< Buffer Interrupt Enable */
mbed_official 545:5112d5ae6723 2320 #define I2C_CR2_DMAEN ((uint32_t)0x00000800) /*!< DMA Requests Enable */
mbed_official 545:5112d5ae6723 2321 #define I2C_CR2_LAST ((uint32_t)0x00001000) /*!< DMA Last Transfer */
mbed_official 545:5112d5ae6723 2322
mbed_official 545:5112d5ae6723 2323 /******************* Bit definition for I2C_OAR1 register *******************/
mbed_official 545:5112d5ae6723 2324 #define I2C_OAR1_ADD1_7 ((uint32_t)0x000000FE) /*!< Interface Address */
mbed_official 545:5112d5ae6723 2325 #define I2C_OAR1_ADD8_9 ((uint32_t)0x00000300) /*!< Interface Address */
mbed_official 545:5112d5ae6723 2326
mbed_official 545:5112d5ae6723 2327 #define I2C_OAR1_ADD0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 2328 #define I2C_OAR1_ADD1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 2329 #define I2C_OAR1_ADD2 ((uint32_t)0x00000004) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 2330 #define I2C_OAR1_ADD3 ((uint32_t)0x00000008) /*!< Bit 3 */
mbed_official 545:5112d5ae6723 2331 #define I2C_OAR1_ADD4 ((uint32_t)0x00000010) /*!< Bit 4 */
mbed_official 545:5112d5ae6723 2332 #define I2C_OAR1_ADD5 ((uint32_t)0x00000020) /*!< Bit 5 */
mbed_official 545:5112d5ae6723 2333 #define I2C_OAR1_ADD6 ((uint32_t)0x00000040) /*!< Bit 6 */
mbed_official 545:5112d5ae6723 2334 #define I2C_OAR1_ADD7 ((uint32_t)0x00000080) /*!< Bit 7 */
mbed_official 545:5112d5ae6723 2335 #define I2C_OAR1_ADD8 ((uint32_t)0x00000100) /*!< Bit 8 */
mbed_official 545:5112d5ae6723 2336 #define I2C_OAR1_ADD9 ((uint32_t)0x00000200) /*!< Bit 9 */
mbed_official 545:5112d5ae6723 2337
mbed_official 545:5112d5ae6723 2338 #define I2C_OAR1_ADDMODE ((uint32_t)0x00008000) /*!< Addressing Mode (Slave mode) */
mbed_official 545:5112d5ae6723 2339
mbed_official 545:5112d5ae6723 2340 /******************* Bit definition for I2C_OAR2 register *******************/
mbed_official 545:5112d5ae6723 2341 #define I2C_OAR2_ENDUAL ((uint32_t)0x00000001) /*!< Dual addressing mode enable */
mbed_official 545:5112d5ae6723 2342 #define I2C_OAR2_ADD2 ((uint32_t)0x000000FE) /*!< Interface address */
mbed_official 545:5112d5ae6723 2343
mbed_official 545:5112d5ae6723 2344 /******************** Bit definition for I2C_DR register ********************/
mbed_official 545:5112d5ae6723 2345 #define I2C_DR_DR ((uint32_t)0x000000FF) /*!< 8-bit Data Register */
mbed_official 545:5112d5ae6723 2346
mbed_official 545:5112d5ae6723 2347 /******************* Bit definition for I2C_SR1 register ********************/
mbed_official 545:5112d5ae6723 2348 #define I2C_SR1_SB ((uint32_t)0x00000001) /*!< Start Bit (Master mode) */
mbed_official 545:5112d5ae6723 2349 #define I2C_SR1_ADDR ((uint32_t)0x00000002) /*!< Address sent (master mode)/matched (slave mode) */
mbed_official 545:5112d5ae6723 2350 #define I2C_SR1_BTF ((uint32_t)0x00000004) /*!< Byte Transfer Finished */
mbed_official 545:5112d5ae6723 2351 #define I2C_SR1_ADD10 ((uint32_t)0x00000008) /*!< 10-bit header sent (Master mode) */
mbed_official 545:5112d5ae6723 2352 #define I2C_SR1_STOPF ((uint32_t)0x00000010) /*!< Stop detection (Slave mode) */
mbed_official 545:5112d5ae6723 2353 #define I2C_SR1_RXNE ((uint32_t)0x00000040) /*!< Data Register not Empty (receivers) */
mbed_official 545:5112d5ae6723 2354 #define I2C_SR1_TXE ((uint32_t)0x00000080) /*!< Data Register Empty (transmitters) */
mbed_official 545:5112d5ae6723 2355 #define I2C_SR1_BERR ((uint32_t)0x00000100) /*!< Bus Error */
mbed_official 545:5112d5ae6723 2356 #define I2C_SR1_ARLO ((uint32_t)0x00000200) /*!< Arbitration Lost (master mode) */
mbed_official 545:5112d5ae6723 2357 #define I2C_SR1_AF ((uint32_t)0x00000400) /*!< Acknowledge Failure */
mbed_official 545:5112d5ae6723 2358 #define I2C_SR1_OVR ((uint32_t)0x00000800) /*!< Overrun/Underrun */
mbed_official 545:5112d5ae6723 2359 #define I2C_SR1_PECERR ((uint32_t)0x00001000) /*!< PEC Error in reception */
mbed_official 545:5112d5ae6723 2360 #define I2C_SR1_TIMEOUT ((uint32_t)0x00004000) /*!< Timeout or Tlow Error */
mbed_official 545:5112d5ae6723 2361 #define I2C_SR1_SMBALERT ((uint32_t)0x00008000) /*!< SMBus Alert */
mbed_official 545:5112d5ae6723 2362
mbed_official 545:5112d5ae6723 2363 /******************* Bit definition for I2C_SR2 register ********************/
mbed_official 545:5112d5ae6723 2364 #define I2C_SR2_MSL ((uint32_t)0x00000001) /*!< Master/Slave */
mbed_official 545:5112d5ae6723 2365 #define I2C_SR2_BUSY ((uint32_t)0x00000002) /*!< Bus Busy */
mbed_official 545:5112d5ae6723 2366 #define I2C_SR2_TRA ((uint32_t)0x00000004) /*!< Transmitter/Receiver */
mbed_official 545:5112d5ae6723 2367 #define I2C_SR2_GENCALL ((uint32_t)0x00000010) /*!< General Call Address (Slave mode) */
mbed_official 545:5112d5ae6723 2368 #define I2C_SR2_SMBDEFAULT ((uint32_t)0x00000020) /*!< SMBus Device Default Address (Slave mode) */
mbed_official 545:5112d5ae6723 2369 #define I2C_SR2_SMBHOST ((uint32_t)0x00000040) /*!< SMBus Host Header (Slave mode) */
mbed_official 545:5112d5ae6723 2370 #define I2C_SR2_DUALF ((uint32_t)0x00000080) /*!< Dual Flag (Slave mode) */
mbed_official 545:5112d5ae6723 2371 #define I2C_SR2_PEC ((uint32_t)0x0000FF00) /*!< Packet Error Checking Register */
mbed_official 545:5112d5ae6723 2372
mbed_official 545:5112d5ae6723 2373 /******************* Bit definition for I2C_CCR register ********************/
mbed_official 545:5112d5ae6723 2374 #define I2C_CCR_CCR ((uint32_t)0x00000FFF) /*!< Clock Control Register in Fast/Standard mode (Master mode) */
mbed_official 545:5112d5ae6723 2375 #define I2C_CCR_DUTY ((uint32_t)0x00004000) /*!< Fast Mode Duty Cycle */
mbed_official 545:5112d5ae6723 2376 #define I2C_CCR_FS ((uint32_t)0x00008000) /*!< I2C Master Mode Selection */
mbed_official 545:5112d5ae6723 2377
mbed_official 545:5112d5ae6723 2378 /****************** Bit definition for I2C_TRISE register *******************/
mbed_official 545:5112d5ae6723 2379 #define I2C_TRISE_TRISE ((uint32_t)0x0000003F) /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */
mbed_official 545:5112d5ae6723 2380
mbed_official 545:5112d5ae6723 2381 /******************************************************************************/
mbed_official 545:5112d5ae6723 2382 /* */
mbed_official 545:5112d5ae6723 2383 /* Independent WATCHDOG (IWDG) */
mbed_official 545:5112d5ae6723 2384 /* */
mbed_official 545:5112d5ae6723 2385 /******************************************************************************/
mbed_official 545:5112d5ae6723 2386
mbed_official 545:5112d5ae6723 2387 /******************* Bit definition for IWDG_KR register ********************/
mbed_official 545:5112d5ae6723 2388 #define IWDG_KR_KEY ((uint32_t)0x0000FFFF) /*!< Key value (write only, read 0000h) */
mbed_official 545:5112d5ae6723 2389
mbed_official 545:5112d5ae6723 2390 /******************* Bit definition for IWDG_PR register ********************/
mbed_official 545:5112d5ae6723 2391 #define IWDG_PR_PR ((uint32_t)0x00000007) /*!< PR[2:0] (Prescaler divider) */
mbed_official 545:5112d5ae6723 2392 #define IWDG_PR_PR_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 2393 #define IWDG_PR_PR_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 2394 #define IWDG_PR_PR_2 ((uint32_t)0x00000004) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 2395
mbed_official 545:5112d5ae6723 2396 /******************* Bit definition for IWDG_RLR register *******************/
mbed_official 545:5112d5ae6723 2397 #define IWDG_RLR_RL ((uint32_t)0x00000FFF) /*!< Watchdog counter reload value */
mbed_official 545:5112d5ae6723 2398
mbed_official 545:5112d5ae6723 2399 /******************* Bit definition for IWDG_SR register ********************/
mbed_official 545:5112d5ae6723 2400 #define IWDG_SR_PVU ((uint32_t)0x00000001) /*!< Watchdog prescaler value update */
mbed_official 545:5112d5ae6723 2401 #define IWDG_SR_RVU ((uint32_t)0x00000002) /*!< Watchdog counter reload value update */
mbed_official 545:5112d5ae6723 2402
mbed_official 545:5112d5ae6723 2403 /******************************************************************************/
mbed_official 545:5112d5ae6723 2404 /* */
mbed_official 545:5112d5ae6723 2405 /* Power Control (PWR) */
mbed_official 545:5112d5ae6723 2406 /* */
mbed_official 545:5112d5ae6723 2407 /******************************************************************************/
mbed_official 545:5112d5ae6723 2408
mbed_official 545:5112d5ae6723 2409 /******************** Bit definition for PWR_CR register ********************/
mbed_official 545:5112d5ae6723 2410 #define PWR_CR_LPSDSR ((uint32_t)0x00000001) /*!< Low-power deepsleep/sleep/low power run */
mbed_official 545:5112d5ae6723 2411 #define PWR_CR_PDDS ((uint32_t)0x00000002) /*!< Power Down Deepsleep */
mbed_official 545:5112d5ae6723 2412 #define PWR_CR_CWUF ((uint32_t)0x00000004) /*!< Clear Wakeup Flag */
mbed_official 545:5112d5ae6723 2413 #define PWR_CR_CSBF ((uint32_t)0x00000008) /*!< Clear Standby Flag */
mbed_official 545:5112d5ae6723 2414 #define PWR_CR_PVDE ((uint32_t)0x00000010) /*!< Power Voltage Detector Enable */
mbed_official 545:5112d5ae6723 2415
mbed_official 545:5112d5ae6723 2416 #define PWR_CR_PLS ((uint32_t)0x000000E0) /*!< PLS[2:0] bits (PVD Level Selection) */
mbed_official 545:5112d5ae6723 2417 #define PWR_CR_PLS_0 ((uint32_t)0x00000020) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 2418 #define PWR_CR_PLS_1 ((uint32_t)0x00000040) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 2419 #define PWR_CR_PLS_2 ((uint32_t)0x00000080) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 2420
mbed_official 545:5112d5ae6723 2421 /*!< PVD level configuration */
mbed_official 545:5112d5ae6723 2422 #define PWR_CR_PLS_LEV0 ((uint32_t)0x00000000) /*!< PVD level 0 */
mbed_official 545:5112d5ae6723 2423 #define PWR_CR_PLS_LEV1 ((uint32_t)0x00000020) /*!< PVD level 1 */
mbed_official 545:5112d5ae6723 2424 #define PWR_CR_PLS_LEV2 ((uint32_t)0x00000040) /*!< PVD level 2 */
mbed_official 545:5112d5ae6723 2425 #define PWR_CR_PLS_LEV3 ((uint32_t)0x00000060) /*!< PVD level 3 */
mbed_official 545:5112d5ae6723 2426 #define PWR_CR_PLS_LEV4 ((uint32_t)0x00000080) /*!< PVD level 4 */
mbed_official 545:5112d5ae6723 2427 #define PWR_CR_PLS_LEV5 ((uint32_t)0x000000A0) /*!< PVD level 5 */
mbed_official 545:5112d5ae6723 2428 #define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0) /*!< PVD level 6 */
mbed_official 545:5112d5ae6723 2429 #define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0) /*!< PVD level 7 */
mbed_official 545:5112d5ae6723 2430
mbed_official 545:5112d5ae6723 2431 #define PWR_CR_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */
mbed_official 545:5112d5ae6723 2432 #define PWR_CR_ULP ((uint32_t)0x00000200) /*!< Ultra Low Power mode */
mbed_official 545:5112d5ae6723 2433 #define PWR_CR_FWU ((uint32_t)0x00000400) /*!< Fast wakeup */
mbed_official 545:5112d5ae6723 2434
mbed_official 545:5112d5ae6723 2435 #define PWR_CR_VOS ((uint32_t)0x00001800) /*!< VOS[1:0] bits (Voltage scaling range selection) */
mbed_official 545:5112d5ae6723 2436 #define PWR_CR_VOS_0 ((uint32_t)0x00000800) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 2437 #define PWR_CR_VOS_1 ((uint32_t)0x00001000) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 2438 #define PWR_CR_LPRUN ((uint32_t)0x00004000) /*!< Low power run mode */
mbed_official 545:5112d5ae6723 2439
mbed_official 545:5112d5ae6723 2440 /******************* Bit definition for PWR_CSR register ********************/
mbed_official 545:5112d5ae6723 2441 #define PWR_CSR_WUF ((uint32_t)0x00000001) /*!< Wakeup Flag */
mbed_official 545:5112d5ae6723 2442 #define PWR_CSR_SBF ((uint32_t)0x00000002) /*!< Standby Flag */
mbed_official 545:5112d5ae6723 2443 #define PWR_CSR_PVDO ((uint32_t)0x00000004) /*!< PVD Output */
mbed_official 545:5112d5ae6723 2444 #define PWR_CSR_VREFINTRDYF ((uint32_t)0x00000008) /*!< Internal voltage reference (VREFINT) ready flag */
mbed_official 545:5112d5ae6723 2445 #define PWR_CSR_VOSF ((uint32_t)0x00000010) /*!< Voltage Scaling select flag */
mbed_official 545:5112d5ae6723 2446 #define PWR_CSR_REGLPF ((uint32_t)0x00000020) /*!< Regulator LP flag */
mbed_official 545:5112d5ae6723 2447
mbed_official 545:5112d5ae6723 2448 #define PWR_CSR_EWUP1 ((uint32_t)0x00000100) /*!< Enable WKUP pin 1 */
mbed_official 545:5112d5ae6723 2449 #define PWR_CSR_EWUP2 ((uint32_t)0x00000200) /*!< Enable WKUP pin 2 */
mbed_official 545:5112d5ae6723 2450 #define PWR_CSR_EWUP3 ((uint32_t)0x00000400) /*!< Enable WKUP pin 3 */
mbed_official 545:5112d5ae6723 2451
mbed_official 545:5112d5ae6723 2452 /******************************************************************************/
mbed_official 545:5112d5ae6723 2453 /* */
mbed_official 545:5112d5ae6723 2454 /* Reset and Clock Control (RCC) */
mbed_official 545:5112d5ae6723 2455 /* */
mbed_official 545:5112d5ae6723 2456 /******************************************************************************/
mbed_official 545:5112d5ae6723 2457 /******************** Bit definition for RCC_CR register ********************/
mbed_official 545:5112d5ae6723 2458 #define RCC_CR_HSION ((uint32_t)0x00000001) /*!< Internal High Speed clock enable */
mbed_official 545:5112d5ae6723 2459 #define RCC_CR_HSIRDY ((uint32_t)0x00000002) /*!< Internal High Speed clock ready flag */
mbed_official 545:5112d5ae6723 2460
mbed_official 545:5112d5ae6723 2461 #define RCC_CR_MSION ((uint32_t)0x00000100) /*!< Internal Multi Speed clock enable */
mbed_official 545:5112d5ae6723 2462 #define RCC_CR_MSIRDY ((uint32_t)0x00000200) /*!< Internal Multi Speed clock ready flag */
mbed_official 545:5112d5ae6723 2463
mbed_official 545:5112d5ae6723 2464 #define RCC_CR_HSEON ((uint32_t)0x00010000) /*!< External High Speed clock enable */
mbed_official 545:5112d5ae6723 2465 #define RCC_CR_HSERDY ((uint32_t)0x00020000) /*!< External High Speed clock ready flag */
mbed_official 545:5112d5ae6723 2466 #define RCC_CR_HSEBYP ((uint32_t)0x00040000) /*!< External High Speed clock Bypass */
mbed_official 545:5112d5ae6723 2467
mbed_official 545:5112d5ae6723 2468 #define RCC_CR_PLLON ((uint32_t)0x01000000) /*!< PLL enable */
mbed_official 545:5112d5ae6723 2469 #define RCC_CR_PLLRDY ((uint32_t)0x02000000) /*!< PLL clock ready flag */
mbed_official 545:5112d5ae6723 2470 #define RCC_CR_CSSON ((uint32_t)0x10000000) /*!< Clock Security System enable */
mbed_official 545:5112d5ae6723 2471
mbed_official 545:5112d5ae6723 2472 #define RCC_CR_RTCPRE ((uint32_t)0x60000000) /*!< RTC Prescaler */
mbed_official 545:5112d5ae6723 2473 #define RCC_CR_RTCPRE_0 ((uint32_t)0x20000000) /*!< Bit0 */
mbed_official 545:5112d5ae6723 2474 #define RCC_CR_RTCPRE_1 ((uint32_t)0x40000000) /*!< Bit1 */
mbed_official 545:5112d5ae6723 2475
mbed_official 545:5112d5ae6723 2476 /******************** Bit definition for RCC_ICSCR register *****************/
mbed_official 545:5112d5ae6723 2477 #define RCC_ICSCR_HSICAL ((uint32_t)0x000000FF) /*!< Internal High Speed clock Calibration */
mbed_official 545:5112d5ae6723 2478 #define RCC_ICSCR_HSITRIM ((uint32_t)0x00001F00) /*!< Internal High Speed clock trimming */
mbed_official 545:5112d5ae6723 2479
mbed_official 545:5112d5ae6723 2480 #define RCC_ICSCR_MSIRANGE ((uint32_t)0x0000E000) /*!< Internal Multi Speed clock Range */
mbed_official 545:5112d5ae6723 2481 #define RCC_ICSCR_MSIRANGE_0 ((uint32_t)0x00000000) /*!< Internal Multi Speed clock Range 65.536 KHz */
mbed_official 545:5112d5ae6723 2482 #define RCC_ICSCR_MSIRANGE_1 ((uint32_t)0x00002000) /*!< Internal Multi Speed clock Range 131.072 KHz */
mbed_official 545:5112d5ae6723 2483 #define RCC_ICSCR_MSIRANGE_2 ((uint32_t)0x00004000) /*!< Internal Multi Speed clock Range 262.144 KHz */
mbed_official 545:5112d5ae6723 2484 #define RCC_ICSCR_MSIRANGE_3 ((uint32_t)0x00006000) /*!< Internal Multi Speed clock Range 524.288 KHz */
mbed_official 545:5112d5ae6723 2485 #define RCC_ICSCR_MSIRANGE_4 ((uint32_t)0x00008000) /*!< Internal Multi Speed clock Range 1.048 MHz */
mbed_official 545:5112d5ae6723 2486 #define RCC_ICSCR_MSIRANGE_5 ((uint32_t)0x0000A000) /*!< Internal Multi Speed clock Range 2.097 MHz */
mbed_official 545:5112d5ae6723 2487 #define RCC_ICSCR_MSIRANGE_6 ((uint32_t)0x0000C000) /*!< Internal Multi Speed clock Range 4.194 MHz */
mbed_official 545:5112d5ae6723 2488 #define RCC_ICSCR_MSICAL ((uint32_t)0x00FF0000) /*!< Internal Multi Speed clock Calibration */
mbed_official 545:5112d5ae6723 2489 #define RCC_ICSCR_MSITRIM ((uint32_t)0xFF000000) /*!< Internal Multi Speed clock trimming */
mbed_official 545:5112d5ae6723 2490
mbed_official 545:5112d5ae6723 2491 /******************** Bit definition for RCC_CFGR register ******************/
mbed_official 545:5112d5ae6723 2492 #define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
mbed_official 545:5112d5ae6723 2493 #define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 2494 #define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 2495
mbed_official 545:5112d5ae6723 2496 /*!< SW configuration */
mbed_official 545:5112d5ae6723 2497 #define RCC_CFGR_SW_MSI ((uint32_t)0x00000000) /*!< MSI selected as system clock */
mbed_official 545:5112d5ae6723 2498 #define RCC_CFGR_SW_HSI ((uint32_t)0x00000001) /*!< HSI selected as system clock */
mbed_official 545:5112d5ae6723 2499 #define RCC_CFGR_SW_HSE ((uint32_t)0x00000002) /*!< HSE selected as system clock */
mbed_official 545:5112d5ae6723 2500 #define RCC_CFGR_SW_PLL ((uint32_t)0x00000003) /*!< PLL selected as system clock */
mbed_official 545:5112d5ae6723 2501
mbed_official 545:5112d5ae6723 2502 #define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
mbed_official 545:5112d5ae6723 2503 #define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 2504 #define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 2505
mbed_official 545:5112d5ae6723 2506 /*!< SWS configuration */
mbed_official 545:5112d5ae6723 2507 #define RCC_CFGR_SWS_MSI ((uint32_t)0x00000000) /*!< MSI oscillator used as system clock */
mbed_official 545:5112d5ae6723 2508 #define RCC_CFGR_SWS_HSI ((uint32_t)0x00000004) /*!< HSI oscillator used as system clock */
mbed_official 545:5112d5ae6723 2509 #define RCC_CFGR_SWS_HSE ((uint32_t)0x00000008) /*!< HSE oscillator used as system clock */
mbed_official 545:5112d5ae6723 2510 #define RCC_CFGR_SWS_PLL ((uint32_t)0x0000000C) /*!< PLL used as system clock */
mbed_official 545:5112d5ae6723 2511
mbed_official 545:5112d5ae6723 2512 #define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
mbed_official 545:5112d5ae6723 2513 #define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 2514 #define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 2515 #define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 2516 #define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
mbed_official 545:5112d5ae6723 2517
mbed_official 545:5112d5ae6723 2518 /*!< HPRE configuration */
mbed_official 545:5112d5ae6723 2519 #define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
mbed_official 545:5112d5ae6723 2520 #define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
mbed_official 545:5112d5ae6723 2521 #define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
mbed_official 545:5112d5ae6723 2522 #define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
mbed_official 545:5112d5ae6723 2523 #define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
mbed_official 545:5112d5ae6723 2524 #define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
mbed_official 545:5112d5ae6723 2525 #define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
mbed_official 545:5112d5ae6723 2526 #define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
mbed_official 545:5112d5ae6723 2527 #define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
mbed_official 545:5112d5ae6723 2528
mbed_official 545:5112d5ae6723 2529 #define RCC_CFGR_PPRE1 ((uint32_t)0x00000700) /*!< PRE1[2:0] bits (APB1 prescaler) */
mbed_official 545:5112d5ae6723 2530 #define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 2531 #define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 2532 #define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 2533
mbed_official 545:5112d5ae6723 2534 /*!< PPRE1 configuration */
mbed_official 545:5112d5ae6723 2535 #define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
mbed_official 545:5112d5ae6723 2536 #define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */
mbed_official 545:5112d5ae6723 2537 #define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */
mbed_official 545:5112d5ae6723 2538 #define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */
mbed_official 545:5112d5ae6723 2539 #define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */
mbed_official 545:5112d5ae6723 2540
mbed_official 545:5112d5ae6723 2541 #define RCC_CFGR_PPRE2 ((uint32_t)0x00003800) /*!< PRE2[2:0] bits (APB2 prescaler) */
mbed_official 545:5112d5ae6723 2542 #define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 2543 #define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 2544 #define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 2545
mbed_official 545:5112d5ae6723 2546 /*!< PPRE2 configuration */
mbed_official 545:5112d5ae6723 2547 #define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
mbed_official 545:5112d5ae6723 2548 #define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */
mbed_official 545:5112d5ae6723 2549 #define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */
mbed_official 545:5112d5ae6723 2550 #define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */
mbed_official 545:5112d5ae6723 2551 #define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */
mbed_official 545:5112d5ae6723 2552
mbed_official 545:5112d5ae6723 2553 /*!< PLL entry clock source*/
mbed_official 545:5112d5ae6723 2554 #define RCC_CFGR_PLLSRC ((uint32_t)0x00010000) /*!< PLL entry clock source */
mbed_official 545:5112d5ae6723 2555
mbed_official 545:5112d5ae6723 2556 #define RCC_CFGR_PLLSRC_HSI ((uint32_t)0x00000000) /*!< HSI as PLL entry clock source */
mbed_official 545:5112d5ae6723 2557 #define RCC_CFGR_PLLSRC_HSE ((uint32_t)0x00010000) /*!< HSE as PLL entry clock source */
mbed_official 545:5112d5ae6723 2558
mbed_official 545:5112d5ae6723 2559
mbed_official 545:5112d5ae6723 2560 /*!< PLLMUL configuration */
mbed_official 545:5112d5ae6723 2561 #define RCC_CFGR_PLLMUL ((uint32_t)0x003C0000) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
mbed_official 545:5112d5ae6723 2562 #define RCC_CFGR_PLLMUL_0 ((uint32_t)0x00040000) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 2563 #define RCC_CFGR_PLLMUL_1 ((uint32_t)0x00080000) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 2564 #define RCC_CFGR_PLLMUL_2 ((uint32_t)0x00100000) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 2565 #define RCC_CFGR_PLLMUL_3 ((uint32_t)0x00200000) /*!< Bit 3 */
mbed_official 545:5112d5ae6723 2566
mbed_official 545:5112d5ae6723 2567 /*!< PLLMUL configuration */
mbed_official 545:5112d5ae6723 2568 #define RCC_CFGR_PLLMUL3 ((uint32_t)0x00000000) /*!< PLL input clock * 3 */
mbed_official 545:5112d5ae6723 2569 #define RCC_CFGR_PLLMUL4 ((uint32_t)0x00040000) /*!< PLL input clock * 4 */
mbed_official 545:5112d5ae6723 2570 #define RCC_CFGR_PLLMUL6 ((uint32_t)0x00080000) /*!< PLL input clock * 6 */
mbed_official 545:5112d5ae6723 2571 #define RCC_CFGR_PLLMUL8 ((uint32_t)0x000C0000) /*!< PLL input clock * 8 */
mbed_official 545:5112d5ae6723 2572 #define RCC_CFGR_PLLMUL12 ((uint32_t)0x00100000) /*!< PLL input clock * 12 */
mbed_official 545:5112d5ae6723 2573 #define RCC_CFGR_PLLMUL16 ((uint32_t)0x00140000) /*!< PLL input clock * 16 */
mbed_official 545:5112d5ae6723 2574 #define RCC_CFGR_PLLMUL24 ((uint32_t)0x00180000) /*!< PLL input clock * 24 */
mbed_official 545:5112d5ae6723 2575 #define RCC_CFGR_PLLMUL32 ((uint32_t)0x001C0000) /*!< PLL input clock * 32 */
mbed_official 545:5112d5ae6723 2576 #define RCC_CFGR_PLLMUL48 ((uint32_t)0x00200000) /*!< PLL input clock * 48 */
mbed_official 545:5112d5ae6723 2577
mbed_official 545:5112d5ae6723 2578 /*!< PLLDIV configuration */
mbed_official 545:5112d5ae6723 2579 #define RCC_CFGR_PLLDIV ((uint32_t)0x00C00000) /*!< PLLDIV[1:0] bits (PLL Output Division) */
mbed_official 545:5112d5ae6723 2580 #define RCC_CFGR_PLLDIV_0 ((uint32_t)0x00400000) /*!< Bit0 */
mbed_official 545:5112d5ae6723 2581 #define RCC_CFGR_PLLDIV_1 ((uint32_t)0x00800000) /*!< Bit1 */
mbed_official 545:5112d5ae6723 2582
mbed_official 545:5112d5ae6723 2583
mbed_official 545:5112d5ae6723 2584 /*!< PLLDIV configuration */
mbed_official 545:5112d5ae6723 2585 #define RCC_CFGR_PLLDIV1 ((uint32_t)0x00000000) /*!< PLL clock output = CKVCO / 1 */
mbed_official 545:5112d5ae6723 2586 #define RCC_CFGR_PLLDIV2 ((uint32_t)0x00400000) /*!< PLL clock output = CKVCO / 2 */
mbed_official 545:5112d5ae6723 2587 #define RCC_CFGR_PLLDIV3 ((uint32_t)0x00800000) /*!< PLL clock output = CKVCO / 3 */
mbed_official 545:5112d5ae6723 2588 #define RCC_CFGR_PLLDIV4 ((uint32_t)0x00C00000) /*!< PLL clock output = CKVCO / 4 */
mbed_official 545:5112d5ae6723 2589
mbed_official 545:5112d5ae6723 2590
mbed_official 545:5112d5ae6723 2591 #define RCC_CFGR_MCOSEL ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */
mbed_official 545:5112d5ae6723 2592 #define RCC_CFGR_MCOSEL_0 ((uint32_t)0x01000000) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 2593 #define RCC_CFGR_MCOSEL_1 ((uint32_t)0x02000000) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 2594 #define RCC_CFGR_MCOSEL_2 ((uint32_t)0x04000000) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 2595
mbed_official 545:5112d5ae6723 2596 /*!< MCO configuration */
mbed_official 545:5112d5ae6723 2597 #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
mbed_official 545:5112d5ae6723 2598 #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x01000000) /*!< System clock selected */
mbed_official 545:5112d5ae6723 2599 #define RCC_CFGR_MCO_HSI ((uint32_t)0x02000000) /*!< Internal 16 MHz RC oscillator clock selected */
mbed_official 545:5112d5ae6723 2600 #define RCC_CFGR_MCO_MSI ((uint32_t)0x03000000) /*!< Internal Medium Speed RC oscillator clock selected */
mbed_official 545:5112d5ae6723 2601 #define RCC_CFGR_MCO_HSE ((uint32_t)0x04000000) /*!< External 1-25 MHz oscillator clock selected */
mbed_official 545:5112d5ae6723 2602 #define RCC_CFGR_MCO_PLL ((uint32_t)0x05000000) /*!< PLL clock divided */
mbed_official 545:5112d5ae6723 2603 #define RCC_CFGR_MCO_LSI ((uint32_t)0x06000000) /*!< LSI selected */
mbed_official 545:5112d5ae6723 2604 #define RCC_CFGR_MCO_LSE ((uint32_t)0x07000000) /*!< LSE selected */
mbed_official 545:5112d5ae6723 2605
mbed_official 545:5112d5ae6723 2606 #define RCC_CFGR_MCOPRE ((uint32_t)0x70000000) /*!< MCOPRE[2:0] bits (Microcontroller Clock Output Prescaler) */
mbed_official 545:5112d5ae6723 2607 #define RCC_CFGR_MCOPRE_0 ((uint32_t)0x10000000) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 2608 #define RCC_CFGR_MCOPRE_1 ((uint32_t)0x20000000) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 2609 #define RCC_CFGR_MCOPRE_2 ((uint32_t)0x40000000) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 2610
mbed_official 545:5112d5ae6723 2611 /*!< MCO Prescaler configuration */
mbed_official 545:5112d5ae6723 2612 #define RCC_CFGR_MCO_DIV1 ((uint32_t)0x00000000) /*!< MCO Clock divided by 1 */
mbed_official 545:5112d5ae6723 2613 #define RCC_CFGR_MCO_DIV2 ((uint32_t)0x10000000) /*!< MCO Clock divided by 2 */
mbed_official 545:5112d5ae6723 2614 #define RCC_CFGR_MCO_DIV4 ((uint32_t)0x20000000) /*!< MCO Clock divided by 4 */
mbed_official 545:5112d5ae6723 2615 #define RCC_CFGR_MCO_DIV8 ((uint32_t)0x30000000) /*!< MCO Clock divided by 8 */
mbed_official 545:5112d5ae6723 2616 #define RCC_CFGR_MCO_DIV16 ((uint32_t)0x40000000) /*!< MCO Clock divided by 16 */
mbed_official 545:5112d5ae6723 2617
mbed_official 545:5112d5ae6723 2618 /*!<****************** Bit definition for RCC_CIR register ********************/
mbed_official 545:5112d5ae6723 2619 #define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */
mbed_official 545:5112d5ae6723 2620 #define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */
mbed_official 545:5112d5ae6723 2621 #define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */
mbed_official 545:5112d5ae6723 2622 #define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */
mbed_official 545:5112d5ae6723 2623 #define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */
mbed_official 545:5112d5ae6723 2624 #define RCC_CIR_MSIRDYF ((uint32_t)0x00000020) /*!< MSI Ready Interrupt flag */
mbed_official 545:5112d5ae6723 2625 #define RCC_CIR_LSECSS ((uint32_t)0x00000040) /*!< LSE CSS Interrupt flag */
mbed_official 545:5112d5ae6723 2626 #define RCC_CIR_CSSF ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */
mbed_official 545:5112d5ae6723 2627
mbed_official 545:5112d5ae6723 2628 #define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */
mbed_official 545:5112d5ae6723 2629 #define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */
mbed_official 545:5112d5ae6723 2630 #define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */
mbed_official 545:5112d5ae6723 2631 #define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */
mbed_official 545:5112d5ae6723 2632 #define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */
mbed_official 545:5112d5ae6723 2633 #define RCC_CIR_MSIRDYIE ((uint32_t)0x00002000) /*!< MSI Ready Interrupt Enable */
mbed_official 545:5112d5ae6723 2634 #define RCC_CIR_LSECSSIE ((uint32_t)0x00004000) /*!< LSE CSS Interrupt Enable */
mbed_official 545:5112d5ae6723 2635
mbed_official 545:5112d5ae6723 2636 #define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */
mbed_official 545:5112d5ae6723 2637 #define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */
mbed_official 545:5112d5ae6723 2638 #define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */
mbed_official 545:5112d5ae6723 2639 #define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */
mbed_official 545:5112d5ae6723 2640 #define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */
mbed_official 545:5112d5ae6723 2641 #define RCC_CIR_MSIRDYC ((uint32_t)0x00200000) /*!< MSI Ready Interrupt Clear */
mbed_official 545:5112d5ae6723 2642 #define RCC_CIR_LSECSSC ((uint32_t)0x00400000) /*!< LSE CSS Interrupt Clear */
mbed_official 545:5112d5ae6723 2643 #define RCC_CIR_CSSC ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */
mbed_official 545:5112d5ae6723 2644
mbed_official 545:5112d5ae6723 2645 /***************** Bit definition for RCC_AHBRSTR register ******************/
mbed_official 545:5112d5ae6723 2646 #define RCC_AHBRSTR_GPIOARST ((uint32_t)0x00000001) /*!< GPIO port A reset */
mbed_official 545:5112d5ae6723 2647 #define RCC_AHBRSTR_GPIOBRST ((uint32_t)0x00000002) /*!< GPIO port B reset */
mbed_official 545:5112d5ae6723 2648 #define RCC_AHBRSTR_GPIOCRST ((uint32_t)0x00000004) /*!< GPIO port C reset */
mbed_official 545:5112d5ae6723 2649 #define RCC_AHBRSTR_GPIODRST ((uint32_t)0x00000008) /*!< GPIO port D reset */
mbed_official 545:5112d5ae6723 2650 #define RCC_AHBRSTR_GPIOERST ((uint32_t)0x00000010) /*!< GPIO port E reset */
mbed_official 545:5112d5ae6723 2651 #define RCC_AHBRSTR_GPIOHRST ((uint32_t)0x00000020) /*!< GPIO port H reset */
mbed_official 545:5112d5ae6723 2652 #define RCC_AHBRSTR_CRCRST ((uint32_t)0x00001000) /*!< CRC reset */
mbed_official 545:5112d5ae6723 2653 #define RCC_AHBRSTR_FLITFRST ((uint32_t)0x00008000) /*!< FLITF reset */
mbed_official 545:5112d5ae6723 2654 #define RCC_AHBRSTR_DMA1RST ((uint32_t)0x01000000) /*!< DMA1 reset */
mbed_official 545:5112d5ae6723 2655 #define RCC_AHBRSTR_DMA2RST ((uint32_t)0x02000000) /*!< DMA2 reset */
mbed_official 545:5112d5ae6723 2656
mbed_official 545:5112d5ae6723 2657 /***************** Bit definition for RCC_APB2RSTR register *****************/
mbed_official 545:5112d5ae6723 2658 #define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00000001) /*!< System Configuration SYSCFG reset */
mbed_official 545:5112d5ae6723 2659 #define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00000004) /*!< TIM9 reset */
mbed_official 545:5112d5ae6723 2660 #define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00000008) /*!< TIM10 reset */
mbed_official 545:5112d5ae6723 2661 #define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00000010) /*!< TIM11 reset */
mbed_official 545:5112d5ae6723 2662 #define RCC_APB2RSTR_ADC1RST ((uint32_t)0x00000200) /*!< ADC1 reset */
mbed_official 545:5112d5ae6723 2663 #define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /*!< SPI1 reset */
mbed_official 545:5112d5ae6723 2664 #define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /*!< USART1 reset */
mbed_official 545:5112d5ae6723 2665
mbed_official 545:5112d5ae6723 2666 /***************** Bit definition for RCC_APB1RSTR register *****************/
mbed_official 545:5112d5ae6723 2667 #define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 reset */
mbed_official 545:5112d5ae6723 2668 #define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /*!< Timer 3 reset */
mbed_official 545:5112d5ae6723 2669 #define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) /*!< Timer 4 reset */
mbed_official 545:5112d5ae6723 2670 #define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008) /*!< Timer 5 reset */
mbed_official 545:5112d5ae6723 2671 #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */
mbed_official 545:5112d5ae6723 2672 #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */
mbed_official 545:5112d5ae6723 2673 #define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog reset */
mbed_official 545:5112d5ae6723 2674 #define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /*!< SPI 2 reset */
mbed_official 545:5112d5ae6723 2675 #define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) /*!< SPI 3 reset */
mbed_official 545:5112d5ae6723 2676 #define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /*!< USART 2 reset */
mbed_official 545:5112d5ae6723 2677 #define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /*!< USART 3 reset */
mbed_official 545:5112d5ae6723 2678 #define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 reset */
mbed_official 545:5112d5ae6723 2679 #define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 reset */
mbed_official 545:5112d5ae6723 2680 #define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) /*!< USB reset */
mbed_official 545:5112d5ae6723 2681 #define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< Power interface reset */
mbed_official 545:5112d5ae6723 2682 #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC interface reset */
mbed_official 545:5112d5ae6723 2683 #define RCC_APB1RSTR_COMPRST ((uint32_t)0x80000000) /*!< Comparator interface reset */
mbed_official 545:5112d5ae6723 2684
mbed_official 545:5112d5ae6723 2685 /****************** Bit definition for RCC_AHBENR register ******************/
mbed_official 545:5112d5ae6723 2686 #define RCC_AHBENR_GPIOAEN ((uint32_t)0x00000001) /*!< GPIO port A clock enable */
mbed_official 545:5112d5ae6723 2687 #define RCC_AHBENR_GPIOBEN ((uint32_t)0x00000002) /*!< GPIO port B clock enable */
mbed_official 545:5112d5ae6723 2688 #define RCC_AHBENR_GPIOCEN ((uint32_t)0x00000004) /*!< GPIO port C clock enable */
mbed_official 545:5112d5ae6723 2689 #define RCC_AHBENR_GPIODEN ((uint32_t)0x00000008) /*!< GPIO port D clock enable */
mbed_official 545:5112d5ae6723 2690 #define RCC_AHBENR_GPIOEEN ((uint32_t)0x00000010) /*!< GPIO port E clock enable */
mbed_official 545:5112d5ae6723 2691 #define RCC_AHBENR_GPIOHEN ((uint32_t)0x00000020) /*!< GPIO port H clock enable */
mbed_official 545:5112d5ae6723 2692 #define RCC_AHBENR_CRCEN ((uint32_t)0x00001000) /*!< CRC clock enable */
mbed_official 545:5112d5ae6723 2693 #define RCC_AHBENR_FLITFEN ((uint32_t)0x00008000) /*!< FLITF clock enable (has effect only when
mbed_official 545:5112d5ae6723 2694 the Flash memory is in power down mode) */
mbed_official 545:5112d5ae6723 2695 #define RCC_AHBENR_DMA1EN ((uint32_t)0x01000000) /*!< DMA1 clock enable */
mbed_official 545:5112d5ae6723 2696 #define RCC_AHBENR_DMA2EN ((uint32_t)0x02000000) /*!< DMA2 clock enable */
mbed_official 545:5112d5ae6723 2697
mbed_official 545:5112d5ae6723 2698 /****************** Bit definition for RCC_APB2ENR register *****************/
mbed_official 545:5112d5ae6723 2699 #define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00000001) /*!< System Configuration SYSCFG clock enable */
mbed_official 545:5112d5ae6723 2700 #define RCC_APB2ENR_TIM9EN ((uint32_t)0x00000004) /*!< TIM9 interface clock enable */
mbed_official 545:5112d5ae6723 2701 #define RCC_APB2ENR_TIM10EN ((uint32_t)0x00000008) /*!< TIM10 interface clock enable */
mbed_official 545:5112d5ae6723 2702 #define RCC_APB2ENR_TIM11EN ((uint32_t)0x00000010) /*!< TIM11 Timer clock enable */
mbed_official 545:5112d5ae6723 2703 #define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000200) /*!< ADC1 clock enable */
mbed_official 545:5112d5ae6723 2704 #define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /*!< SPI1 clock enable */
mbed_official 545:5112d5ae6723 2705 #define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable */
mbed_official 545:5112d5ae6723 2706
mbed_official 545:5112d5ae6723 2707 /***************** Bit definition for RCC_APB1ENR register ******************/
mbed_official 545:5112d5ae6723 2708 #define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enabled*/
mbed_official 545:5112d5ae6723 2709 #define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /*!< Timer 3 clock enable */
mbed_official 545:5112d5ae6723 2710 #define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) /*!< Timer 4 clock enable */
mbed_official 545:5112d5ae6723 2711 #define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008) /*!< Timer 5 clock enable */
mbed_official 545:5112d5ae6723 2712 #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */
mbed_official 545:5112d5ae6723 2713 #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */
mbed_official 545:5112d5ae6723 2714 #define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */
mbed_official 545:5112d5ae6723 2715 #define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /*!< SPI 2 clock enable */
mbed_official 545:5112d5ae6723 2716 #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) /*!< SPI 3 clock enable */
mbed_official 545:5112d5ae6723 2717 #define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /*!< USART 2 clock enable */
mbed_official 545:5112d5ae6723 2718 #define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /*!< USART 3 clock enable */
mbed_official 545:5112d5ae6723 2719 #define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C 1 clock enable */
mbed_official 545:5112d5ae6723 2720 #define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /*!< I2C 2 clock enable */
mbed_official 545:5112d5ae6723 2721 #define RCC_APB1ENR_USBEN ((uint32_t)0x00800000) /*!< USB clock enable */
mbed_official 545:5112d5ae6723 2722 #define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< Power interface clock enable */
mbed_official 545:5112d5ae6723 2723 #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC interface clock enable */
mbed_official 545:5112d5ae6723 2724 #define RCC_APB1ENR_COMPEN ((uint32_t)0x80000000) /*!< Comparator interface clock enable */
mbed_official 545:5112d5ae6723 2725
mbed_official 545:5112d5ae6723 2726 /****************** Bit definition for RCC_AHBLPENR register ****************/
mbed_official 545:5112d5ae6723 2727 #define RCC_AHBLPENR_GPIOALPEN ((uint32_t)0x00000001) /*!< GPIO port A clock enabled in sleep mode */
mbed_official 545:5112d5ae6723 2728 #define RCC_AHBLPENR_GPIOBLPEN ((uint32_t)0x00000002) /*!< GPIO port B clock enabled in sleep mode */
mbed_official 545:5112d5ae6723 2729 #define RCC_AHBLPENR_GPIOCLPEN ((uint32_t)0x00000004) /*!< GPIO port C clock enabled in sleep mode */
mbed_official 545:5112d5ae6723 2730 #define RCC_AHBLPENR_GPIODLPEN ((uint32_t)0x00000008) /*!< GPIO port D clock enabled in sleep mode */
mbed_official 545:5112d5ae6723 2731 #define RCC_AHBLPENR_GPIOELPEN ((uint32_t)0x00000010) /*!< GPIO port E clock enabled in sleep mode */
mbed_official 545:5112d5ae6723 2732 #define RCC_AHBLPENR_GPIOHLPEN ((uint32_t)0x00000020) /*!< GPIO port H clock enabled in sleep mode */
mbed_official 545:5112d5ae6723 2733 #define RCC_AHBLPENR_CRCLPEN ((uint32_t)0x00001000) /*!< CRC clock enabled in sleep mode */
mbed_official 545:5112d5ae6723 2734 #define RCC_AHBLPENR_FLITFLPEN ((uint32_t)0x00008000) /*!< Flash Interface clock enabled in sleep mode
mbed_official 545:5112d5ae6723 2735 (has effect only when the Flash memory is
mbed_official 545:5112d5ae6723 2736 in power down mode) */
mbed_official 545:5112d5ae6723 2737 #define RCC_AHBLPENR_SRAMLPEN ((uint32_t)0x00010000) /*!< SRAM clock enabled in sleep mode */
mbed_official 545:5112d5ae6723 2738 #define RCC_AHBLPENR_DMA1LPEN ((uint32_t)0x01000000) /*!< DMA1 clock enabled in sleep mode */
mbed_official 545:5112d5ae6723 2739 #define RCC_AHBLPENR_DMA2LPEN ((uint32_t)0x02000000) /*!< DMA2 clock enabled in sleep mode */
mbed_official 545:5112d5ae6723 2740
mbed_official 545:5112d5ae6723 2741 /****************** Bit definition for RCC_APB2LPENR register ***************/
mbed_official 545:5112d5ae6723 2742 #define RCC_APB2LPENR_SYSCFGLPEN ((uint32_t)0x00000001) /*!< System Configuration SYSCFG clock enabled in sleep mode */
mbed_official 545:5112d5ae6723 2743 #define RCC_APB2LPENR_TIM9LPEN ((uint32_t)0x00000004) /*!< TIM9 interface clock enabled in sleep mode */
mbed_official 545:5112d5ae6723 2744 #define RCC_APB2LPENR_TIM10LPEN ((uint32_t)0x00000008) /*!< TIM10 interface clock enabled in sleep mode */
mbed_official 545:5112d5ae6723 2745 #define RCC_APB2LPENR_TIM11LPEN ((uint32_t)0x00000010) /*!< TIM11 Timer clock enabled in sleep mode */
mbed_official 545:5112d5ae6723 2746 #define RCC_APB2LPENR_ADC1LPEN ((uint32_t)0x00000200) /*!< ADC1 clock enabled in sleep mode */
mbed_official 545:5112d5ae6723 2747 #define RCC_APB2LPENR_SPI1LPEN ((uint32_t)0x00001000) /*!< SPI1 clock enabled in sleep mode */
mbed_official 545:5112d5ae6723 2748 #define RCC_APB2LPENR_USART1LPEN ((uint32_t)0x00004000) /*!< USART1 clock enabled in sleep mode */
mbed_official 545:5112d5ae6723 2749
mbed_official 545:5112d5ae6723 2750 /***************** Bit definition for RCC_APB1LPENR register ****************/
mbed_official 545:5112d5ae6723 2751 #define RCC_APB1LPENR_TIM2LPEN ((uint32_t)0x00000001) /*!< Timer 2 clock enabled in sleep mode */
mbed_official 545:5112d5ae6723 2752 #define RCC_APB1LPENR_TIM3LPEN ((uint32_t)0x00000002) /*!< Timer 3 clock enabled in sleep mode */
mbed_official 545:5112d5ae6723 2753 #define RCC_APB1LPENR_TIM4LPEN ((uint32_t)0x00000004) /*!< Timer 4 clock enabled in sleep mode */
mbed_official 545:5112d5ae6723 2754 #define RCC_APB1LPENR_TIM5LPEN ((uint32_t)0x00000008) /*!< Timer 5 clock enabled in sleep mode */
mbed_official 545:5112d5ae6723 2755 #define RCC_APB1LPENR_TIM6LPEN ((uint32_t)0x00000010) /*!< Timer 6 clock enabled in sleep mode */
mbed_official 545:5112d5ae6723 2756 #define RCC_APB1LPENR_TIM7LPEN ((uint32_t)0x00000020) /*!< Timer 7 clock enabled in sleep mode */
mbed_official 545:5112d5ae6723 2757 #define RCC_APB1LPENR_WWDGLPEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enabled in sleep mode */
mbed_official 545:5112d5ae6723 2758 #define RCC_APB1LPENR_SPI2LPEN ((uint32_t)0x00004000) /*!< SPI 2 clock enabled in sleep mode */
mbed_official 545:5112d5ae6723 2759 #define RCC_APB1LPENR_SPI3LPEN ((uint32_t)0x00008000) /*!< SPI 3 clock enabled in sleep mode */
mbed_official 545:5112d5ae6723 2760 #define RCC_APB1LPENR_USART2LPEN ((uint32_t)0x00020000) /*!< USART 2 clock enabled in sleep mode */
mbed_official 545:5112d5ae6723 2761 #define RCC_APB1LPENR_USART3LPEN ((uint32_t)0x00040000) /*!< USART 3 clock enabled in sleep mode */
mbed_official 545:5112d5ae6723 2762 #define RCC_APB1LPENR_I2C1LPEN ((uint32_t)0x00200000) /*!< I2C 1 clock enabled in sleep mode */
mbed_official 545:5112d5ae6723 2763 #define RCC_APB1LPENR_I2C2LPEN ((uint32_t)0x00400000) /*!< I2C 2 clock enabled in sleep mode */
mbed_official 545:5112d5ae6723 2764 #define RCC_APB1LPENR_USBLPEN ((uint32_t)0x00800000) /*!< USB clock enabled in sleep mode */
mbed_official 545:5112d5ae6723 2765 #define RCC_APB1LPENR_PWRLPEN ((uint32_t)0x10000000) /*!< Power interface clock enabled in sleep mode */
mbed_official 545:5112d5ae6723 2766 #define RCC_APB1LPENR_DACLPEN ((uint32_t)0x20000000) /*!< DAC interface clock enabled in sleep mode */
mbed_official 545:5112d5ae6723 2767 #define RCC_APB1LPENR_COMPLPEN ((uint32_t)0x80000000) /*!< Comparator interface clock enabled in sleep mode*/
mbed_official 545:5112d5ae6723 2768
mbed_official 545:5112d5ae6723 2769 /******************* Bit definition for RCC_CSR register ********************/
mbed_official 545:5112d5ae6723 2770 #define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */
mbed_official 545:5112d5ae6723 2771 #define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */
mbed_official 545:5112d5ae6723 2772
mbed_official 545:5112d5ae6723 2773 #define RCC_CSR_LSEON ((uint32_t)0x00000100) /*!< External Low Speed oscillator enable */
mbed_official 545:5112d5ae6723 2774 #define RCC_CSR_LSERDY ((uint32_t)0x00000200) /*!< External Low Speed oscillator Ready */
mbed_official 545:5112d5ae6723 2775 #define RCC_CSR_LSEBYP ((uint32_t)0x00000400) /*!< External Low Speed oscillator Bypass */
mbed_official 545:5112d5ae6723 2776
mbed_official 545:5112d5ae6723 2777 #define RCC_CSR_LSECSSON ((uint32_t)0x00000800) /*!< External Low Speed oscillator CSS Enable */
mbed_official 545:5112d5ae6723 2778 #define RCC_CSR_LSECSSD ((uint32_t)0x00001000) /*!< External Low Speed oscillator CSS Detected */
mbed_official 545:5112d5ae6723 2779
mbed_official 545:5112d5ae6723 2780 #define RCC_CSR_RTCSEL ((uint32_t)0x00030000) /*!< RTCSEL[1:0] bits (RTC clock source selection) */
mbed_official 545:5112d5ae6723 2781 #define RCC_CSR_RTCSEL_0 ((uint32_t)0x00010000) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 2782 #define RCC_CSR_RTCSEL_1 ((uint32_t)0x00020000) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 2783
mbed_official 545:5112d5ae6723 2784 /*!< RTC congiguration */
mbed_official 545:5112d5ae6723 2785 #define RCC_CSR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
mbed_official 545:5112d5ae6723 2786 #define RCC_CSR_RTCSEL_LSE ((uint32_t)0x00010000) /*!< LSE oscillator clock used as RTC clock */
mbed_official 545:5112d5ae6723 2787 #define RCC_CSR_RTCSEL_LSI ((uint32_t)0x00020000) /*!< LSI oscillator clock used as RTC clock */
mbed_official 545:5112d5ae6723 2788 #define RCC_CSR_RTCSEL_HSE ((uint32_t)0x00030000) /*!< HSE oscillator clock divided by 2, 4, 8 or 16 by RTCPRE used as RTC clock */
mbed_official 545:5112d5ae6723 2789
mbed_official 545:5112d5ae6723 2790 #define RCC_CSR_RTCEN ((uint32_t)0x00400000) /*!< RTC clock enable */
mbed_official 545:5112d5ae6723 2791 #define RCC_CSR_RTCRST ((uint32_t)0x00800000) /*!< RTC reset */
mbed_official 545:5112d5ae6723 2792
mbed_official 545:5112d5ae6723 2793 #define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */
mbed_official 545:5112d5ae6723 2794 #define RCC_CSR_OBLRSTF ((uint32_t)0x02000000) /*!< Option Bytes Loader reset flag */
mbed_official 545:5112d5ae6723 2795 #define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */
mbed_official 545:5112d5ae6723 2796 #define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /*!< POR/PDR reset flag */
mbed_official 545:5112d5ae6723 2797 #define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */
mbed_official 545:5112d5ae6723 2798 #define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */
mbed_official 545:5112d5ae6723 2799 #define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */
mbed_official 545:5112d5ae6723 2800 #define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */
mbed_official 545:5112d5ae6723 2801
mbed_official 545:5112d5ae6723 2802 /******************************************************************************/
mbed_official 545:5112d5ae6723 2803 /* */
mbed_official 545:5112d5ae6723 2804 /* Real-Time Clock (RTC) */
mbed_official 545:5112d5ae6723 2805 /* */
mbed_official 545:5112d5ae6723 2806 /******************************************************************************/
mbed_official 545:5112d5ae6723 2807 /******************** Bits definition for RTC_TR register *******************/
mbed_official 545:5112d5ae6723 2808 #define RTC_TR_PM ((uint32_t)0x00400000)
mbed_official 545:5112d5ae6723 2809 #define RTC_TR_HT ((uint32_t)0x00300000)
mbed_official 545:5112d5ae6723 2810 #define RTC_TR_HT_0 ((uint32_t)0x00100000)
mbed_official 545:5112d5ae6723 2811 #define RTC_TR_HT_1 ((uint32_t)0x00200000)
mbed_official 545:5112d5ae6723 2812 #define RTC_TR_HU ((uint32_t)0x000F0000)
mbed_official 545:5112d5ae6723 2813 #define RTC_TR_HU_0 ((uint32_t)0x00010000)
mbed_official 545:5112d5ae6723 2814 #define RTC_TR_HU_1 ((uint32_t)0x00020000)
mbed_official 545:5112d5ae6723 2815 #define RTC_TR_HU_2 ((uint32_t)0x00040000)
mbed_official 545:5112d5ae6723 2816 #define RTC_TR_HU_3 ((uint32_t)0x00080000)
mbed_official 545:5112d5ae6723 2817 #define RTC_TR_MNT ((uint32_t)0x00007000)
mbed_official 545:5112d5ae6723 2818 #define RTC_TR_MNT_0 ((uint32_t)0x00001000)
mbed_official 545:5112d5ae6723 2819 #define RTC_TR_MNT_1 ((uint32_t)0x00002000)
mbed_official 545:5112d5ae6723 2820 #define RTC_TR_MNT_2 ((uint32_t)0x00004000)
mbed_official 545:5112d5ae6723 2821 #define RTC_TR_MNU ((uint32_t)0x00000F00)
mbed_official 545:5112d5ae6723 2822 #define RTC_TR_MNU_0 ((uint32_t)0x00000100)
mbed_official 545:5112d5ae6723 2823 #define RTC_TR_MNU_1 ((uint32_t)0x00000200)
mbed_official 545:5112d5ae6723 2824 #define RTC_TR_MNU_2 ((uint32_t)0x00000400)
mbed_official 545:5112d5ae6723 2825 #define RTC_TR_MNU_3 ((uint32_t)0x00000800)
mbed_official 545:5112d5ae6723 2826 #define RTC_TR_ST ((uint32_t)0x00000070)
mbed_official 545:5112d5ae6723 2827 #define RTC_TR_ST_0 ((uint32_t)0x00000010)
mbed_official 545:5112d5ae6723 2828 #define RTC_TR_ST_1 ((uint32_t)0x00000020)
mbed_official 545:5112d5ae6723 2829 #define RTC_TR_ST_2 ((uint32_t)0x00000040)
mbed_official 545:5112d5ae6723 2830 #define RTC_TR_SU ((uint32_t)0x0000000F)
mbed_official 545:5112d5ae6723 2831 #define RTC_TR_SU_0 ((uint32_t)0x00000001)
mbed_official 545:5112d5ae6723 2832 #define RTC_TR_SU_1 ((uint32_t)0x00000002)
mbed_official 545:5112d5ae6723 2833 #define RTC_TR_SU_2 ((uint32_t)0x00000004)
mbed_official 545:5112d5ae6723 2834 #define RTC_TR_SU_3 ((uint32_t)0x00000008)
mbed_official 545:5112d5ae6723 2835
mbed_official 545:5112d5ae6723 2836 /******************** Bits definition for RTC_DR register *******************/
mbed_official 545:5112d5ae6723 2837 #define RTC_DR_YT ((uint32_t)0x00F00000)
mbed_official 545:5112d5ae6723 2838 #define RTC_DR_YT_0 ((uint32_t)0x00100000)
mbed_official 545:5112d5ae6723 2839 #define RTC_DR_YT_1 ((uint32_t)0x00200000)
mbed_official 545:5112d5ae6723 2840 #define RTC_DR_YT_2 ((uint32_t)0x00400000)
mbed_official 545:5112d5ae6723 2841 #define RTC_DR_YT_3 ((uint32_t)0x00800000)
mbed_official 545:5112d5ae6723 2842 #define RTC_DR_YU ((uint32_t)0x000F0000)
mbed_official 545:5112d5ae6723 2843 #define RTC_DR_YU_0 ((uint32_t)0x00010000)
mbed_official 545:5112d5ae6723 2844 #define RTC_DR_YU_1 ((uint32_t)0x00020000)
mbed_official 545:5112d5ae6723 2845 #define RTC_DR_YU_2 ((uint32_t)0x00040000)
mbed_official 545:5112d5ae6723 2846 #define RTC_DR_YU_3 ((uint32_t)0x00080000)
mbed_official 545:5112d5ae6723 2847 #define RTC_DR_WDU ((uint32_t)0x0000E000)
mbed_official 545:5112d5ae6723 2848 #define RTC_DR_WDU_0 ((uint32_t)0x00002000)
mbed_official 545:5112d5ae6723 2849 #define RTC_DR_WDU_1 ((uint32_t)0x00004000)
mbed_official 545:5112d5ae6723 2850 #define RTC_DR_WDU_2 ((uint32_t)0x00008000)
mbed_official 545:5112d5ae6723 2851 #define RTC_DR_MT ((uint32_t)0x00001000)
mbed_official 545:5112d5ae6723 2852 #define RTC_DR_MU ((uint32_t)0x00000F00)
mbed_official 545:5112d5ae6723 2853 #define RTC_DR_MU_0 ((uint32_t)0x00000100)
mbed_official 545:5112d5ae6723 2854 #define RTC_DR_MU_1 ((uint32_t)0x00000200)
mbed_official 545:5112d5ae6723 2855 #define RTC_DR_MU_2 ((uint32_t)0x00000400)
mbed_official 545:5112d5ae6723 2856 #define RTC_DR_MU_3 ((uint32_t)0x00000800)
mbed_official 545:5112d5ae6723 2857 #define RTC_DR_DT ((uint32_t)0x00000030)
mbed_official 545:5112d5ae6723 2858 #define RTC_DR_DT_0 ((uint32_t)0x00000010)
mbed_official 545:5112d5ae6723 2859 #define RTC_DR_DT_1 ((uint32_t)0x00000020)
mbed_official 545:5112d5ae6723 2860 #define RTC_DR_DU ((uint32_t)0x0000000F)
mbed_official 545:5112d5ae6723 2861 #define RTC_DR_DU_0 ((uint32_t)0x00000001)
mbed_official 545:5112d5ae6723 2862 #define RTC_DR_DU_1 ((uint32_t)0x00000002)
mbed_official 545:5112d5ae6723 2863 #define RTC_DR_DU_2 ((uint32_t)0x00000004)
mbed_official 545:5112d5ae6723 2864 #define RTC_DR_DU_3 ((uint32_t)0x00000008)
mbed_official 545:5112d5ae6723 2865
mbed_official 545:5112d5ae6723 2866 /******************** Bits definition for RTC_CR register *******************/
mbed_official 545:5112d5ae6723 2867 #define RTC_CR_COE ((uint32_t)0x00800000)
mbed_official 545:5112d5ae6723 2868 #define RTC_CR_OSEL ((uint32_t)0x00600000)
mbed_official 545:5112d5ae6723 2869 #define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
mbed_official 545:5112d5ae6723 2870 #define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
mbed_official 545:5112d5ae6723 2871 #define RTC_CR_POL ((uint32_t)0x00100000)
mbed_official 545:5112d5ae6723 2872 #define RTC_CR_COSEL ((uint32_t)0x00080000)
mbed_official 545:5112d5ae6723 2873 #define RTC_CR_BCK ((uint32_t)0x00040000)
mbed_official 545:5112d5ae6723 2874 #define RTC_CR_SUB1H ((uint32_t)0x00020000)
mbed_official 545:5112d5ae6723 2875 #define RTC_CR_ADD1H ((uint32_t)0x00010000)
mbed_official 545:5112d5ae6723 2876 #define RTC_CR_TSIE ((uint32_t)0x00008000)
mbed_official 545:5112d5ae6723 2877 #define RTC_CR_WUTIE ((uint32_t)0x00004000)
mbed_official 545:5112d5ae6723 2878 #define RTC_CR_ALRBIE ((uint32_t)0x00002000)
mbed_official 545:5112d5ae6723 2879 #define RTC_CR_ALRAIE ((uint32_t)0x00001000)
mbed_official 545:5112d5ae6723 2880 #define RTC_CR_TSE ((uint32_t)0x00000800)
mbed_official 545:5112d5ae6723 2881 #define RTC_CR_WUTE ((uint32_t)0x00000400)
mbed_official 545:5112d5ae6723 2882 #define RTC_CR_ALRBE ((uint32_t)0x00000200)
mbed_official 545:5112d5ae6723 2883 #define RTC_CR_ALRAE ((uint32_t)0x00000100)
mbed_official 545:5112d5ae6723 2884 #define RTC_CR_DCE ((uint32_t)0x00000080)
mbed_official 545:5112d5ae6723 2885 #define RTC_CR_FMT ((uint32_t)0x00000040)
mbed_official 545:5112d5ae6723 2886 #define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
mbed_official 545:5112d5ae6723 2887 #define RTC_CR_REFCKON ((uint32_t)0x00000010)
mbed_official 545:5112d5ae6723 2888 #define RTC_CR_TSEDGE ((uint32_t)0x00000008)
mbed_official 545:5112d5ae6723 2889 #define RTC_CR_WUCKSEL ((uint32_t)0x00000007)
mbed_official 545:5112d5ae6723 2890 #define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001)
mbed_official 545:5112d5ae6723 2891 #define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002)
mbed_official 545:5112d5ae6723 2892 #define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004)
mbed_official 545:5112d5ae6723 2893
mbed_official 545:5112d5ae6723 2894 /******************** Bits definition for RTC_ISR register ******************/
mbed_official 545:5112d5ae6723 2895 #define RTC_ISR_RECALPF ((uint32_t)0x00010000)
mbed_official 545:5112d5ae6723 2896 #define RTC_ISR_TAMP3F ((uint32_t)0x00008000)
mbed_official 545:5112d5ae6723 2897 #define RTC_ISR_TAMP2F ((uint32_t)0x00004000)
mbed_official 545:5112d5ae6723 2898 #define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
mbed_official 545:5112d5ae6723 2899 #define RTC_ISR_TSOVF ((uint32_t)0x00001000)
mbed_official 545:5112d5ae6723 2900 #define RTC_ISR_TSF ((uint32_t)0x00000800)
mbed_official 545:5112d5ae6723 2901 #define RTC_ISR_WUTF ((uint32_t)0x00000400)
mbed_official 545:5112d5ae6723 2902 #define RTC_ISR_ALRBF ((uint32_t)0x00000200)
mbed_official 545:5112d5ae6723 2903 #define RTC_ISR_ALRAF ((uint32_t)0x00000100)
mbed_official 545:5112d5ae6723 2904 #define RTC_ISR_INIT ((uint32_t)0x00000080)
mbed_official 545:5112d5ae6723 2905 #define RTC_ISR_INITF ((uint32_t)0x00000040)
mbed_official 545:5112d5ae6723 2906 #define RTC_ISR_RSF ((uint32_t)0x00000020)
mbed_official 545:5112d5ae6723 2907 #define RTC_ISR_INITS ((uint32_t)0x00000010)
mbed_official 545:5112d5ae6723 2908 #define RTC_ISR_SHPF ((uint32_t)0x00000008)
mbed_official 545:5112d5ae6723 2909 #define RTC_ISR_WUTWF ((uint32_t)0x00000004)
mbed_official 545:5112d5ae6723 2910 #define RTC_ISR_ALRBWF ((uint32_t)0x00000002)
mbed_official 545:5112d5ae6723 2911 #define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
mbed_official 545:5112d5ae6723 2912
mbed_official 545:5112d5ae6723 2913 /******************** Bits definition for RTC_PRER register *****************/
mbed_official 545:5112d5ae6723 2914 #define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
mbed_official 545:5112d5ae6723 2915 #define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF)
mbed_official 545:5112d5ae6723 2916
mbed_official 545:5112d5ae6723 2917 /******************** Bits definition for RTC_WUTR register *****************/
mbed_official 545:5112d5ae6723 2918 #define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
mbed_official 545:5112d5ae6723 2919
mbed_official 545:5112d5ae6723 2920 /******************** Bits definition for RTC_CALIBR register ***************/
mbed_official 545:5112d5ae6723 2921 #define RTC_CALIBR_DCS ((uint32_t)0x00000080)
mbed_official 545:5112d5ae6723 2922 #define RTC_CALIBR_DC ((uint32_t)0x0000001F)
mbed_official 545:5112d5ae6723 2923
mbed_official 545:5112d5ae6723 2924 /******************** Bits definition for RTC_ALRMAR register ***************/
mbed_official 545:5112d5ae6723 2925 #define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
mbed_official 545:5112d5ae6723 2926 #define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
mbed_official 545:5112d5ae6723 2927 #define RTC_ALRMAR_DT ((uint32_t)0x30000000)
mbed_official 545:5112d5ae6723 2928 #define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
mbed_official 545:5112d5ae6723 2929 #define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
mbed_official 545:5112d5ae6723 2930 #define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
mbed_official 545:5112d5ae6723 2931 #define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
mbed_official 545:5112d5ae6723 2932 #define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
mbed_official 545:5112d5ae6723 2933 #define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
mbed_official 545:5112d5ae6723 2934 #define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
mbed_official 545:5112d5ae6723 2935 #define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
mbed_official 545:5112d5ae6723 2936 #define RTC_ALRMAR_PM ((uint32_t)0x00400000)
mbed_official 545:5112d5ae6723 2937 #define RTC_ALRMAR_HT ((uint32_t)0x00300000)
mbed_official 545:5112d5ae6723 2938 #define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
mbed_official 545:5112d5ae6723 2939 #define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
mbed_official 545:5112d5ae6723 2940 #define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
mbed_official 545:5112d5ae6723 2941 #define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
mbed_official 545:5112d5ae6723 2942 #define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
mbed_official 545:5112d5ae6723 2943 #define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
mbed_official 545:5112d5ae6723 2944 #define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
mbed_official 545:5112d5ae6723 2945 #define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
mbed_official 545:5112d5ae6723 2946 #define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
mbed_official 545:5112d5ae6723 2947 #define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
mbed_official 545:5112d5ae6723 2948 #define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
mbed_official 545:5112d5ae6723 2949 #define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
mbed_official 545:5112d5ae6723 2950 #define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
mbed_official 545:5112d5ae6723 2951 #define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
mbed_official 545:5112d5ae6723 2952 #define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
mbed_official 545:5112d5ae6723 2953 #define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
mbed_official 545:5112d5ae6723 2954 #define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
mbed_official 545:5112d5ae6723 2955 #define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
mbed_official 545:5112d5ae6723 2956 #define RTC_ALRMAR_ST ((uint32_t)0x00000070)
mbed_official 545:5112d5ae6723 2957 #define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
mbed_official 545:5112d5ae6723 2958 #define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
mbed_official 545:5112d5ae6723 2959 #define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
mbed_official 545:5112d5ae6723 2960 #define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
mbed_official 545:5112d5ae6723 2961 #define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
mbed_official 545:5112d5ae6723 2962 #define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
mbed_official 545:5112d5ae6723 2963 #define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
mbed_official 545:5112d5ae6723 2964 #define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
mbed_official 545:5112d5ae6723 2965
mbed_official 545:5112d5ae6723 2966 /******************** Bits definition for RTC_ALRMBR register ***************/
mbed_official 545:5112d5ae6723 2967 #define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000)
mbed_official 545:5112d5ae6723 2968 #define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000)
mbed_official 545:5112d5ae6723 2969 #define RTC_ALRMBR_DT ((uint32_t)0x30000000)
mbed_official 545:5112d5ae6723 2970 #define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000)
mbed_official 545:5112d5ae6723 2971 #define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000)
mbed_official 545:5112d5ae6723 2972 #define RTC_ALRMBR_DU ((uint32_t)0x0F000000)
mbed_official 545:5112d5ae6723 2973 #define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000)
mbed_official 545:5112d5ae6723 2974 #define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000)
mbed_official 545:5112d5ae6723 2975 #define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000)
mbed_official 545:5112d5ae6723 2976 #define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000)
mbed_official 545:5112d5ae6723 2977 #define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000)
mbed_official 545:5112d5ae6723 2978 #define RTC_ALRMBR_PM ((uint32_t)0x00400000)
mbed_official 545:5112d5ae6723 2979 #define RTC_ALRMBR_HT ((uint32_t)0x00300000)
mbed_official 545:5112d5ae6723 2980 #define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000)
mbed_official 545:5112d5ae6723 2981 #define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000)
mbed_official 545:5112d5ae6723 2982 #define RTC_ALRMBR_HU ((uint32_t)0x000F0000)
mbed_official 545:5112d5ae6723 2983 #define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000)
mbed_official 545:5112d5ae6723 2984 #define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000)
mbed_official 545:5112d5ae6723 2985 #define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000)
mbed_official 545:5112d5ae6723 2986 #define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000)
mbed_official 545:5112d5ae6723 2987 #define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000)
mbed_official 545:5112d5ae6723 2988 #define RTC_ALRMBR_MNT ((uint32_t)0x00007000)
mbed_official 545:5112d5ae6723 2989 #define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000)
mbed_official 545:5112d5ae6723 2990 #define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000)
mbed_official 545:5112d5ae6723 2991 #define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000)
mbed_official 545:5112d5ae6723 2992 #define RTC_ALRMBR_MNU ((uint32_t)0x00000F00)
mbed_official 545:5112d5ae6723 2993 #define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100)
mbed_official 545:5112d5ae6723 2994 #define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200)
mbed_official 545:5112d5ae6723 2995 #define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400)
mbed_official 545:5112d5ae6723 2996 #define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800)
mbed_official 545:5112d5ae6723 2997 #define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080)
mbed_official 545:5112d5ae6723 2998 #define RTC_ALRMBR_ST ((uint32_t)0x00000070)
mbed_official 545:5112d5ae6723 2999 #define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010)
mbed_official 545:5112d5ae6723 3000 #define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020)
mbed_official 545:5112d5ae6723 3001 #define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040)
mbed_official 545:5112d5ae6723 3002 #define RTC_ALRMBR_SU ((uint32_t)0x0000000F)
mbed_official 545:5112d5ae6723 3003 #define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001)
mbed_official 545:5112d5ae6723 3004 #define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002)
mbed_official 545:5112d5ae6723 3005 #define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004)
mbed_official 545:5112d5ae6723 3006 #define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008)
mbed_official 545:5112d5ae6723 3007
mbed_official 545:5112d5ae6723 3008 /******************** Bits definition for RTC_WPR register ******************/
mbed_official 545:5112d5ae6723 3009 #define RTC_WPR_KEY ((uint32_t)0x000000FF)
mbed_official 545:5112d5ae6723 3010
mbed_official 545:5112d5ae6723 3011 /******************** Bits definition for RTC_SSR register ******************/
mbed_official 545:5112d5ae6723 3012 #define RTC_SSR_SS ((uint32_t)0x0000FFFF)
mbed_official 545:5112d5ae6723 3013
mbed_official 545:5112d5ae6723 3014 /******************** Bits definition for RTC_SHIFTR register ***************/
mbed_official 545:5112d5ae6723 3015 #define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
mbed_official 545:5112d5ae6723 3016 #define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
mbed_official 545:5112d5ae6723 3017
mbed_official 545:5112d5ae6723 3018 /******************** Bits definition for RTC_TSTR register *****************/
mbed_official 545:5112d5ae6723 3019 #define RTC_TSTR_PM ((uint32_t)0x00400000)
mbed_official 545:5112d5ae6723 3020 #define RTC_TSTR_HT ((uint32_t)0x00300000)
mbed_official 545:5112d5ae6723 3021 #define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
mbed_official 545:5112d5ae6723 3022 #define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
mbed_official 545:5112d5ae6723 3023 #define RTC_TSTR_HU ((uint32_t)0x000F0000)
mbed_official 545:5112d5ae6723 3024 #define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
mbed_official 545:5112d5ae6723 3025 #define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
mbed_official 545:5112d5ae6723 3026 #define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
mbed_official 545:5112d5ae6723 3027 #define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
mbed_official 545:5112d5ae6723 3028 #define RTC_TSTR_MNT ((uint32_t)0x00007000)
mbed_official 545:5112d5ae6723 3029 #define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
mbed_official 545:5112d5ae6723 3030 #define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
mbed_official 545:5112d5ae6723 3031 #define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
mbed_official 545:5112d5ae6723 3032 #define RTC_TSTR_MNU ((uint32_t)0x00000F00)
mbed_official 545:5112d5ae6723 3033 #define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
mbed_official 545:5112d5ae6723 3034 #define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
mbed_official 545:5112d5ae6723 3035 #define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
mbed_official 545:5112d5ae6723 3036 #define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
mbed_official 545:5112d5ae6723 3037 #define RTC_TSTR_ST ((uint32_t)0x00000070)
mbed_official 545:5112d5ae6723 3038 #define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
mbed_official 545:5112d5ae6723 3039 #define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
mbed_official 545:5112d5ae6723 3040 #define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
mbed_official 545:5112d5ae6723 3041 #define RTC_TSTR_SU ((uint32_t)0x0000000F)
mbed_official 545:5112d5ae6723 3042 #define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
mbed_official 545:5112d5ae6723 3043 #define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
mbed_official 545:5112d5ae6723 3044 #define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
mbed_official 545:5112d5ae6723 3045 #define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
mbed_official 545:5112d5ae6723 3046
mbed_official 545:5112d5ae6723 3047 /******************** Bits definition for RTC_TSDR register *****************/
mbed_official 545:5112d5ae6723 3048 #define RTC_TSDR_WDU ((uint32_t)0x0000E000)
mbed_official 545:5112d5ae6723 3049 #define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
mbed_official 545:5112d5ae6723 3050 #define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
mbed_official 545:5112d5ae6723 3051 #define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
mbed_official 545:5112d5ae6723 3052 #define RTC_TSDR_MT ((uint32_t)0x00001000)
mbed_official 545:5112d5ae6723 3053 #define RTC_TSDR_MU ((uint32_t)0x00000F00)
mbed_official 545:5112d5ae6723 3054 #define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
mbed_official 545:5112d5ae6723 3055 #define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
mbed_official 545:5112d5ae6723 3056 #define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
mbed_official 545:5112d5ae6723 3057 #define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
mbed_official 545:5112d5ae6723 3058 #define RTC_TSDR_DT ((uint32_t)0x00000030)
mbed_official 545:5112d5ae6723 3059 #define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
mbed_official 545:5112d5ae6723 3060 #define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
mbed_official 545:5112d5ae6723 3061 #define RTC_TSDR_DU ((uint32_t)0x0000000F)
mbed_official 545:5112d5ae6723 3062 #define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
mbed_official 545:5112d5ae6723 3063 #define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
mbed_official 545:5112d5ae6723 3064 #define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
mbed_official 545:5112d5ae6723 3065 #define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
mbed_official 545:5112d5ae6723 3066
mbed_official 545:5112d5ae6723 3067 /******************** Bits definition for RTC_TSSSR register ****************/
mbed_official 545:5112d5ae6723 3068 #define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)
mbed_official 545:5112d5ae6723 3069
mbed_official 545:5112d5ae6723 3070 /******************** Bits definition for RTC_CAL register *****************/
mbed_official 545:5112d5ae6723 3071 #define RTC_CALR_CALP ((uint32_t)0x00008000)
mbed_official 545:5112d5ae6723 3072 #define RTC_CALR_CALW8 ((uint32_t)0x00004000)
mbed_official 545:5112d5ae6723 3073 #define RTC_CALR_CALW16 ((uint32_t)0x00002000)
mbed_official 545:5112d5ae6723 3074 #define RTC_CALR_CALM ((uint32_t)0x000001FF)
mbed_official 545:5112d5ae6723 3075 #define RTC_CALR_CALM_0 ((uint32_t)0x00000001)
mbed_official 545:5112d5ae6723 3076 #define RTC_CALR_CALM_1 ((uint32_t)0x00000002)
mbed_official 545:5112d5ae6723 3077 #define RTC_CALR_CALM_2 ((uint32_t)0x00000004)
mbed_official 545:5112d5ae6723 3078 #define RTC_CALR_CALM_3 ((uint32_t)0x00000008)
mbed_official 545:5112d5ae6723 3079 #define RTC_CALR_CALM_4 ((uint32_t)0x00000010)
mbed_official 545:5112d5ae6723 3080 #define RTC_CALR_CALM_5 ((uint32_t)0x00000020)
mbed_official 545:5112d5ae6723 3081 #define RTC_CALR_CALM_6 ((uint32_t)0x00000040)
mbed_official 545:5112d5ae6723 3082 #define RTC_CALR_CALM_7 ((uint32_t)0x00000080)
mbed_official 545:5112d5ae6723 3083 #define RTC_CALR_CALM_8 ((uint32_t)0x00000100)
mbed_official 545:5112d5ae6723 3084
mbed_official 545:5112d5ae6723 3085 /******************** Bits definition for RTC_TAFCR register ****************/
mbed_official 545:5112d5ae6723 3086 #define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)
mbed_official 545:5112d5ae6723 3087 #define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)
mbed_official 545:5112d5ae6723 3088 #define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)
mbed_official 545:5112d5ae6723 3089 #define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)
mbed_official 545:5112d5ae6723 3090 #define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)
mbed_official 545:5112d5ae6723 3091 #define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)
mbed_official 545:5112d5ae6723 3092 #define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)
mbed_official 545:5112d5ae6723 3093 #define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)
mbed_official 545:5112d5ae6723 3094 #define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)
mbed_official 545:5112d5ae6723 3095 #define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)
mbed_official 545:5112d5ae6723 3096 #define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)
mbed_official 545:5112d5ae6723 3097 #define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)
mbed_official 545:5112d5ae6723 3098 #define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)
mbed_official 545:5112d5ae6723 3099 #define RTC_TAFCR_TAMP3TRG ((uint32_t)0x00000040)
mbed_official 545:5112d5ae6723 3100 #define RTC_TAFCR_TAMP3E ((uint32_t)0x00000020)
mbed_official 545:5112d5ae6723 3101 #define RTC_TAFCR_TAMP2TRG ((uint32_t)0x00000010)
mbed_official 545:5112d5ae6723 3102 #define RTC_TAFCR_TAMP2E ((uint32_t)0x00000008)
mbed_official 545:5112d5ae6723 3103 #define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)
mbed_official 545:5112d5ae6723 3104 #define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)
mbed_official 545:5112d5ae6723 3105 #define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)
mbed_official 545:5112d5ae6723 3106
mbed_official 545:5112d5ae6723 3107 /******************** Bits definition for RTC_ALRMASSR register *************/
mbed_official 545:5112d5ae6723 3108 #define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
mbed_official 545:5112d5ae6723 3109 #define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
mbed_official 545:5112d5ae6723 3110 #define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
mbed_official 545:5112d5ae6723 3111 #define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
mbed_official 545:5112d5ae6723 3112 #define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
mbed_official 545:5112d5ae6723 3113 #define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
mbed_official 545:5112d5ae6723 3114
mbed_official 545:5112d5ae6723 3115 /******************** Bits definition for RTC_ALRMBSSR register *************/
mbed_official 545:5112d5ae6723 3116 #define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000)
mbed_official 545:5112d5ae6723 3117 #define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000)
mbed_official 545:5112d5ae6723 3118 #define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000)
mbed_official 545:5112d5ae6723 3119 #define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000)
mbed_official 545:5112d5ae6723 3120 #define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000)
mbed_official 545:5112d5ae6723 3121 #define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFF)
mbed_official 545:5112d5ae6723 3122
mbed_official 545:5112d5ae6723 3123 /******************** Bits definition for RTC_BKP0R register ****************/
mbed_official 545:5112d5ae6723 3124 #define RTC_BKP0R ((uint32_t)0xFFFFFFFF)
mbed_official 545:5112d5ae6723 3125
mbed_official 545:5112d5ae6723 3126 /******************** Bits definition for RTC_BKP1R register ****************/
mbed_official 545:5112d5ae6723 3127 #define RTC_BKP1R ((uint32_t)0xFFFFFFFF)
mbed_official 545:5112d5ae6723 3128
mbed_official 545:5112d5ae6723 3129 /******************** Bits definition for RTC_BKP2R register ****************/
mbed_official 545:5112d5ae6723 3130 #define RTC_BKP2R ((uint32_t)0xFFFFFFFF)
mbed_official 545:5112d5ae6723 3131
mbed_official 545:5112d5ae6723 3132 /******************** Bits definition for RTC_BKP3R register ****************/
mbed_official 545:5112d5ae6723 3133 #define RTC_BKP3R ((uint32_t)0xFFFFFFFF)
mbed_official 545:5112d5ae6723 3134
mbed_official 545:5112d5ae6723 3135 /******************** Bits definition for RTC_BKP4R register ****************/
mbed_official 545:5112d5ae6723 3136 #define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
mbed_official 545:5112d5ae6723 3137
mbed_official 545:5112d5ae6723 3138 /******************** Bits definition for RTC_BKP5R register ****************/
mbed_official 545:5112d5ae6723 3139 #define RTC_BKP5R ((uint32_t)0xFFFFFFFF)
mbed_official 545:5112d5ae6723 3140
mbed_official 545:5112d5ae6723 3141 /******************** Bits definition for RTC_BKP6R register ****************/
mbed_official 545:5112d5ae6723 3142 #define RTC_BKP6R ((uint32_t)0xFFFFFFFF)
mbed_official 545:5112d5ae6723 3143
mbed_official 545:5112d5ae6723 3144 /******************** Bits definition for RTC_BKP7R register ****************/
mbed_official 545:5112d5ae6723 3145 #define RTC_BKP7R ((uint32_t)0xFFFFFFFF)
mbed_official 545:5112d5ae6723 3146
mbed_official 545:5112d5ae6723 3147 /******************** Bits definition for RTC_BKP8R register ****************/
mbed_official 545:5112d5ae6723 3148 #define RTC_BKP8R ((uint32_t)0xFFFFFFFF)
mbed_official 545:5112d5ae6723 3149
mbed_official 545:5112d5ae6723 3150 /******************** Bits definition for RTC_BKP9R register ****************/
mbed_official 545:5112d5ae6723 3151 #define RTC_BKP9R ((uint32_t)0xFFFFFFFF)
mbed_official 545:5112d5ae6723 3152
mbed_official 545:5112d5ae6723 3153 /******************** Bits definition for RTC_BKP10R register ***************/
mbed_official 545:5112d5ae6723 3154 #define RTC_BKP10R ((uint32_t)0xFFFFFFFF)
mbed_official 545:5112d5ae6723 3155
mbed_official 545:5112d5ae6723 3156 /******************** Bits definition for RTC_BKP11R register ***************/
mbed_official 545:5112d5ae6723 3157 #define RTC_BKP11R ((uint32_t)0xFFFFFFFF)
mbed_official 545:5112d5ae6723 3158
mbed_official 545:5112d5ae6723 3159 /******************** Bits definition for RTC_BKP12R register ***************/
mbed_official 545:5112d5ae6723 3160 #define RTC_BKP12R ((uint32_t)0xFFFFFFFF)
mbed_official 545:5112d5ae6723 3161
mbed_official 545:5112d5ae6723 3162 /******************** Bits definition for RTC_BKP13R register ***************/
mbed_official 545:5112d5ae6723 3163 #define RTC_BKP13R ((uint32_t)0xFFFFFFFF)
mbed_official 545:5112d5ae6723 3164
mbed_official 545:5112d5ae6723 3165 /******************** Bits definition for RTC_BKP14R register ***************/
mbed_official 545:5112d5ae6723 3166 #define RTC_BKP14R ((uint32_t)0xFFFFFFFF)
mbed_official 545:5112d5ae6723 3167
mbed_official 545:5112d5ae6723 3168 /******************** Bits definition for RTC_BKP15R register ***************/
mbed_official 545:5112d5ae6723 3169 #define RTC_BKP15R ((uint32_t)0xFFFFFFFF)
mbed_official 545:5112d5ae6723 3170
mbed_official 545:5112d5ae6723 3171 /******************** Bits definition for RTC_BKP16R register ***************/
mbed_official 545:5112d5ae6723 3172 #define RTC_BKP16R ((uint32_t)0xFFFFFFFF)
mbed_official 545:5112d5ae6723 3173
mbed_official 545:5112d5ae6723 3174 /******************** Bits definition for RTC_BKP17R register ***************/
mbed_official 545:5112d5ae6723 3175 #define RTC_BKP17R ((uint32_t)0xFFFFFFFF)
mbed_official 545:5112d5ae6723 3176
mbed_official 545:5112d5ae6723 3177 /******************** Bits definition for RTC_BKP18R register ***************/
mbed_official 545:5112d5ae6723 3178 #define RTC_BKP18R ((uint32_t)0xFFFFFFFF)
mbed_official 545:5112d5ae6723 3179
mbed_official 545:5112d5ae6723 3180 /******************** Bits definition for RTC_BKP19R register ***************/
mbed_official 545:5112d5ae6723 3181 #define RTC_BKP19R ((uint32_t)0xFFFFFFFF)
mbed_official 545:5112d5ae6723 3182
mbed_official 545:5112d5ae6723 3183 /******************** Bits definition for RTC_BKP20R register ***************/
mbed_official 545:5112d5ae6723 3184 #define RTC_BKP20R ((uint32_t)0xFFFFFFFF)
mbed_official 545:5112d5ae6723 3185
mbed_official 545:5112d5ae6723 3186 /******************** Bits definition for RTC_BKP21R register ***************/
mbed_official 545:5112d5ae6723 3187 #define RTC_BKP21R ((uint32_t)0xFFFFFFFF)
mbed_official 545:5112d5ae6723 3188
mbed_official 545:5112d5ae6723 3189 /******************** Bits definition for RTC_BKP22R register ***************/
mbed_official 545:5112d5ae6723 3190 #define RTC_BKP22R ((uint32_t)0xFFFFFFFF)
mbed_official 545:5112d5ae6723 3191
mbed_official 545:5112d5ae6723 3192 /******************** Bits definition for RTC_BKP23R register ***************/
mbed_official 545:5112d5ae6723 3193 #define RTC_BKP23R ((uint32_t)0xFFFFFFFF)
mbed_official 545:5112d5ae6723 3194
mbed_official 545:5112d5ae6723 3195 /******************** Bits definition for RTC_BKP24R register ***************/
mbed_official 545:5112d5ae6723 3196 #define RTC_BKP24R ((uint32_t)0xFFFFFFFF)
mbed_official 545:5112d5ae6723 3197
mbed_official 545:5112d5ae6723 3198 /******************** Bits definition for RTC_BKP25R register ***************/
mbed_official 545:5112d5ae6723 3199 #define RTC_BKP25R ((uint32_t)0xFFFFFFFF)
mbed_official 545:5112d5ae6723 3200
mbed_official 545:5112d5ae6723 3201 /******************** Bits definition for RTC_BKP26R register ***************/
mbed_official 545:5112d5ae6723 3202 #define RTC_BKP26R ((uint32_t)0xFFFFFFFF)
mbed_official 545:5112d5ae6723 3203
mbed_official 545:5112d5ae6723 3204 /******************** Bits definition for RTC_BKP27R register ***************/
mbed_official 545:5112d5ae6723 3205 #define RTC_BKP27R ((uint32_t)0xFFFFFFFF)
mbed_official 545:5112d5ae6723 3206
mbed_official 545:5112d5ae6723 3207 /******************** Bits definition for RTC_BKP28R register ***************/
mbed_official 545:5112d5ae6723 3208 #define RTC_BKP28R ((uint32_t)0xFFFFFFFF)
mbed_official 545:5112d5ae6723 3209
mbed_official 545:5112d5ae6723 3210 /******************** Bits definition for RTC_BKP29R register ***************/
mbed_official 545:5112d5ae6723 3211 #define RTC_BKP29R ((uint32_t)0xFFFFFFFF)
mbed_official 545:5112d5ae6723 3212
mbed_official 545:5112d5ae6723 3213 /******************** Bits definition for RTC_BKP30R register ***************/
mbed_official 545:5112d5ae6723 3214 #define RTC_BKP30R ((uint32_t)0xFFFFFFFF)
mbed_official 545:5112d5ae6723 3215
mbed_official 545:5112d5ae6723 3216 /******************** Bits definition for RTC_BKP31R register ***************/
mbed_official 545:5112d5ae6723 3217 #define RTC_BKP31R ((uint32_t)0xFFFFFFFF)
mbed_official 545:5112d5ae6723 3218
mbed_official 545:5112d5ae6723 3219 /******************** Number of backup registers ******************************/
mbed_official 545:5112d5ae6723 3220 #define RTC_BKP_NUMBER 32
mbed_official 545:5112d5ae6723 3221
mbed_official 545:5112d5ae6723 3222 /******************************************************************************/
mbed_official 545:5112d5ae6723 3223 /* */
mbed_official 545:5112d5ae6723 3224 /* Serial Peripheral Interface (SPI) */
mbed_official 545:5112d5ae6723 3225 /* */
mbed_official 545:5112d5ae6723 3226 /******************************************************************************/
mbed_official 545:5112d5ae6723 3227
mbed_official 545:5112d5ae6723 3228 /******************* Bit definition for SPI_CR1 register ********************/
mbed_official 545:5112d5ae6723 3229 #define SPI_CR1_CPHA ((uint32_t)0x00000001) /*!< Clock Phase */
mbed_official 545:5112d5ae6723 3230 #define SPI_CR1_CPOL ((uint32_t)0x00000002) /*!< Clock Polarity */
mbed_official 545:5112d5ae6723 3231 #define SPI_CR1_MSTR ((uint32_t)0x00000004) /*!< Master Selection */
mbed_official 545:5112d5ae6723 3232
mbed_official 545:5112d5ae6723 3233 #define SPI_CR1_BR ((uint32_t)0x00000038) /*!< BR[2:0] bits (Baud Rate Control) */
mbed_official 545:5112d5ae6723 3234 #define SPI_CR1_BR_0 ((uint32_t)0x00000008) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 3235 #define SPI_CR1_BR_1 ((uint32_t)0x00000010) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 3236 #define SPI_CR1_BR_2 ((uint32_t)0x00000020) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 3237
mbed_official 545:5112d5ae6723 3238 #define SPI_CR1_SPE ((uint32_t)0x00000040) /*!< SPI Enable */
mbed_official 545:5112d5ae6723 3239 #define SPI_CR1_LSBFIRST ((uint32_t)0x00000080) /*!< Frame Format */
mbed_official 545:5112d5ae6723 3240 #define SPI_CR1_SSI ((uint32_t)0x00000100) /*!< Internal slave select */
mbed_official 545:5112d5ae6723 3241 #define SPI_CR1_SSM ((uint32_t)0x00000200) /*!< Software slave management */
mbed_official 545:5112d5ae6723 3242 #define SPI_CR1_RXONLY ((uint32_t)0x00000400) /*!< Receive only */
mbed_official 545:5112d5ae6723 3243 #define SPI_CR1_DFF ((uint32_t)0x00000800) /*!< Data Frame Format */
mbed_official 545:5112d5ae6723 3244 #define SPI_CR1_CRCNEXT ((uint32_t)0x00001000) /*!< Transmit CRC next */
mbed_official 545:5112d5ae6723 3245 #define SPI_CR1_CRCEN ((uint32_t)0x00002000) /*!< Hardware CRC calculation enable */
mbed_official 545:5112d5ae6723 3246 #define SPI_CR1_BIDIOE ((uint32_t)0x00004000) /*!< Output enable in bidirectional mode */
mbed_official 545:5112d5ae6723 3247 #define SPI_CR1_BIDIMODE ((uint32_t)0x00008000) /*!< Bidirectional data mode enable */
mbed_official 545:5112d5ae6723 3248
mbed_official 545:5112d5ae6723 3249 /******************* Bit definition for SPI_CR2 register ********************/
mbed_official 545:5112d5ae6723 3250 #define SPI_CR2_RXDMAEN ((uint32_t)0x00000001) /*!< Rx Buffer DMA Enable */
mbed_official 545:5112d5ae6723 3251 #define SPI_CR2_TXDMAEN ((uint32_t)0x00000002) /*!< Tx Buffer DMA Enable */
mbed_official 545:5112d5ae6723 3252 #define SPI_CR2_SSOE ((uint32_t)0x00000004) /*!< SS Output Enable */
mbed_official 545:5112d5ae6723 3253 #define SPI_CR2_FRF ((uint32_t)0x00000010) /*!< Frame format */
mbed_official 545:5112d5ae6723 3254 #define SPI_CR2_ERRIE ((uint32_t)0x00000020) /*!< Error Interrupt Enable */
mbed_official 545:5112d5ae6723 3255 #define SPI_CR2_RXNEIE ((uint32_t)0x00000040) /*!< RX buffer Not Empty Interrupt Enable */
mbed_official 545:5112d5ae6723 3256 #define SPI_CR2_TXEIE ((uint32_t)0x00000080) /*!< Tx buffer Empty Interrupt Enable */
mbed_official 545:5112d5ae6723 3257
mbed_official 545:5112d5ae6723 3258 /******************** Bit definition for SPI_SR register ********************/
mbed_official 545:5112d5ae6723 3259 #define SPI_SR_RXNE ((uint32_t)0x00000001) /*!< Receive buffer Not Empty */
mbed_official 545:5112d5ae6723 3260 #define SPI_SR_TXE ((uint32_t)0x00000002) /*!< Transmit buffer Empty */
mbed_official 545:5112d5ae6723 3261 #define SPI_SR_CHSIDE ((uint32_t)0x00000004) /*!< Channel side */
mbed_official 545:5112d5ae6723 3262 #define SPI_SR_UDR ((uint32_t)0x00000008) /*!< Underrun flag */
mbed_official 545:5112d5ae6723 3263 #define SPI_SR_CRCERR ((uint32_t)0x00000010) /*!< CRC Error flag */
mbed_official 545:5112d5ae6723 3264 #define SPI_SR_MODF ((uint32_t)0x00000020) /*!< Mode fault */
mbed_official 545:5112d5ae6723 3265 #define SPI_SR_OVR ((uint32_t)0x00000040) /*!< Overrun flag */
mbed_official 545:5112d5ae6723 3266 #define SPI_SR_BSY ((uint32_t)0x00000080) /*!< Busy flag */
mbed_official 545:5112d5ae6723 3267 #define SPI_SR_FRE ((uint32_t)0x00000100) /*!<Frame format error flag */
mbed_official 545:5112d5ae6723 3268
mbed_official 545:5112d5ae6723 3269 /******************** Bit definition for SPI_DR register ********************/
mbed_official 545:5112d5ae6723 3270 #define SPI_DR_DR ((uint32_t)0x0000FFFF) /*!< Data Register */
mbed_official 545:5112d5ae6723 3271
mbed_official 545:5112d5ae6723 3272 /******************* Bit definition for SPI_CRCPR register ******************/
mbed_official 545:5112d5ae6723 3273 #define SPI_CRCPR_CRCPOLY ((uint32_t)0x0000FFFF) /*!< CRC polynomial register */
mbed_official 545:5112d5ae6723 3274
mbed_official 545:5112d5ae6723 3275 /****************** Bit definition for SPI_RXCRCR register ******************/
mbed_official 545:5112d5ae6723 3276 #define SPI_RXCRCR_RXCRC ((uint32_t)0x0000FFFF) /*!< Rx CRC Register */
mbed_official 545:5112d5ae6723 3277
mbed_official 545:5112d5ae6723 3278 /****************** Bit definition for SPI_TXCRCR register ******************/
mbed_official 545:5112d5ae6723 3279 #define SPI_TXCRCR_TXCRC ((uint32_t)0x0000FFFF) /*!< Tx CRC Register */
mbed_official 545:5112d5ae6723 3280
mbed_official 545:5112d5ae6723 3281 /****************** Bit definition for SPI_I2SCFGR register *****************/
mbed_official 545:5112d5ae6723 3282 #define SPI_I2SCFGR_CHLEN ((uint32_t)0x00000001) /*!<Channel length (number of bits per audio channel) */
mbed_official 545:5112d5ae6723 3283
mbed_official 545:5112d5ae6723 3284 #define SPI_I2SCFGR_DATLEN ((uint32_t)0x00000006) /*!<DATLEN[1:0] bits (Data length to be transferred) */
mbed_official 545:5112d5ae6723 3285 #define SPI_I2SCFGR_DATLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */
mbed_official 545:5112d5ae6723 3286 #define SPI_I2SCFGR_DATLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */
mbed_official 545:5112d5ae6723 3287
mbed_official 545:5112d5ae6723 3288 #define SPI_I2SCFGR_CKPOL ((uint32_t)0x00000008) /*!<steady state clock polarity */
mbed_official 545:5112d5ae6723 3289
mbed_official 545:5112d5ae6723 3290 #define SPI_I2SCFGR_I2SSTD ((uint32_t)0x00000030) /*!<I2SSTD[1:0] bits (I2S standard selection) */
mbed_official 545:5112d5ae6723 3291 #define SPI_I2SCFGR_I2SSTD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 545:5112d5ae6723 3292 #define SPI_I2SCFGR_I2SSTD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 545:5112d5ae6723 3293
mbed_official 545:5112d5ae6723 3294 #define SPI_I2SCFGR_PCMSYNC ((uint32_t)0x00000080) /*!<PCM frame synchronization */
mbed_official 545:5112d5ae6723 3295
mbed_official 545:5112d5ae6723 3296 #define SPI_I2SCFGR_I2SCFG ((uint32_t)0x00000300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */
mbed_official 545:5112d5ae6723 3297 #define SPI_I2SCFGR_I2SCFG_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 545:5112d5ae6723 3298 #define SPI_I2SCFGR_I2SCFG_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 545:5112d5ae6723 3299
mbed_official 545:5112d5ae6723 3300 #define SPI_I2SCFGR_I2SE ((uint32_t)0x00000400) /*!<I2S Enable */
mbed_official 545:5112d5ae6723 3301 #define SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) /*!<I2S mode selection */
mbed_official 545:5112d5ae6723 3302
mbed_official 545:5112d5ae6723 3303 /****************** Bit definition for SPI_I2SPR register *******************/
mbed_official 545:5112d5ae6723 3304 #define SPI_I2SPR_I2SDIV ((uint32_t)0x000000FF) /*!<I2S Linear prescaler */
mbed_official 545:5112d5ae6723 3305 #define SPI_I2SPR_ODD ((uint32_t)0x00000100) /*!<Odd factor for the prescaler */
mbed_official 545:5112d5ae6723 3306 #define SPI_I2SPR_MCKOE ((uint32_t)0x00000200) /*!<Master Clock Output Enable */
mbed_official 545:5112d5ae6723 3307
mbed_official 545:5112d5ae6723 3308 /******************************************************************************/
mbed_official 545:5112d5ae6723 3309 /* */
mbed_official 545:5112d5ae6723 3310 /* System Configuration (SYSCFG) */
mbed_official 545:5112d5ae6723 3311 /* */
mbed_official 545:5112d5ae6723 3312 /******************************************************************************/
mbed_official 545:5112d5ae6723 3313 /***************** Bit definition for SYSCFG_MEMRMP register ****************/
mbed_official 545:5112d5ae6723 3314 #define SYSCFG_MEMRMP_MEM_MODE ((uint32_t)0x00000003) /*!< SYSCFG_Memory Remap Config */
mbed_official 545:5112d5ae6723 3315 #define SYSCFG_MEMRMP_MEM_MODE_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 3316 #define SYSCFG_MEMRMP_MEM_MODE_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 3317 #define SYSCFG_MEMRMP_BOOT_MODE ((uint32_t)0x00000300) /*!< Boot mode Config */
mbed_official 545:5112d5ae6723 3318 #define SYSCFG_MEMRMP_BOOT_MODE_0 ((uint32_t)0x00000100) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 3319 #define SYSCFG_MEMRMP_BOOT_MODE_1 ((uint32_t)0x00000200) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 3320
mbed_official 545:5112d5ae6723 3321 /***************** Bit definition for SYSCFG_PMC register *******************/
mbed_official 545:5112d5ae6723 3322 #define SYSCFG_PMC_USB_PU ((uint32_t)0x00000001) /*!< SYSCFG PMC */
mbed_official 545:5112d5ae6723 3323
mbed_official 545:5112d5ae6723 3324 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
mbed_official 545:5112d5ae6723 3325 #define SYSCFG_EXTICR1_EXTI0 ((uint32_t)0x0000000F) /*!< EXTI 0 configuration */
mbed_official 545:5112d5ae6723 3326 #define SYSCFG_EXTICR1_EXTI1 ((uint32_t)0x000000F0) /*!< EXTI 1 configuration */
mbed_official 545:5112d5ae6723 3327 #define SYSCFG_EXTICR1_EXTI2 ((uint32_t)0x00000F00) /*!< EXTI 2 configuration */
mbed_official 545:5112d5ae6723 3328 #define SYSCFG_EXTICR1_EXTI3 ((uint32_t)0x0000F000) /*!< EXTI 3 configuration */
mbed_official 545:5112d5ae6723 3329
mbed_official 545:5112d5ae6723 3330 /**
mbed_official 545:5112d5ae6723 3331 * @brief EXTI0 configuration
mbed_official 545:5112d5ae6723 3332 */
mbed_official 545:5112d5ae6723 3333 #define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!< PA[0] pin */
mbed_official 545:5112d5ae6723 3334 #define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /*!< PB[0] pin */
mbed_official 545:5112d5ae6723 3335 #define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /*!< PC[0] pin */
mbed_official 545:5112d5ae6723 3336 #define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /*!< PD[0] pin */
mbed_official 545:5112d5ae6723 3337 #define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) /*!< PE[0] pin */
mbed_official 545:5112d5ae6723 3338 #define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x00000005) /*!< PH[0] pin */
mbed_official 545:5112d5ae6723 3339 #define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x00000006) /*!< PF[0] pin */
mbed_official 545:5112d5ae6723 3340 #define SYSCFG_EXTICR1_EXTI0_PG ((uint32_t)0x00000007) /*!< PG[0] pin */
mbed_official 545:5112d5ae6723 3341
mbed_official 545:5112d5ae6723 3342 /**
mbed_official 545:5112d5ae6723 3343 * @brief EXTI1 configuration
mbed_official 545:5112d5ae6723 3344 */
mbed_official 545:5112d5ae6723 3345 #define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!< PA[1] pin */
mbed_official 545:5112d5ae6723 3346 #define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /*!< PB[1] pin */
mbed_official 545:5112d5ae6723 3347 #define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /*!< PC[1] pin */
mbed_official 545:5112d5ae6723 3348 #define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /*!< PD[1] pin */
mbed_official 545:5112d5ae6723 3349 #define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) /*!< PE[1] pin */
mbed_official 545:5112d5ae6723 3350 #define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x00000050) /*!< PH[1] pin */
mbed_official 545:5112d5ae6723 3351 #define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x00000060) /*!< PF[1] pin */
mbed_official 545:5112d5ae6723 3352 #define SYSCFG_EXTICR1_EXTI1_PG ((uint32_t)0x00000070) /*!< PG[1] pin */
mbed_official 545:5112d5ae6723 3353
mbed_official 545:5112d5ae6723 3354 /**
mbed_official 545:5112d5ae6723 3355 * @brief EXTI2 configuration
mbed_official 545:5112d5ae6723 3356 */
mbed_official 545:5112d5ae6723 3357 #define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!< PA[2] pin */
mbed_official 545:5112d5ae6723 3358 #define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /*!< PB[2] pin */
mbed_official 545:5112d5ae6723 3359 #define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /*!< PC[2] pin */
mbed_official 545:5112d5ae6723 3360 #define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /*!< PD[2] pin */
mbed_official 545:5112d5ae6723 3361 #define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) /*!< PE[2] pin */
mbed_official 545:5112d5ae6723 3362 #define SYSCFG_EXTICR1_EXTI2_PH ((uint32_t)0x00000500) /*!< PH[2] pin */
mbed_official 545:5112d5ae6723 3363 #define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x00000600) /*!< PF[2] pin */
mbed_official 545:5112d5ae6723 3364 #define SYSCFG_EXTICR1_EXTI2_PG ((uint32_t)0x00000700) /*!< PG[2] pin */
mbed_official 545:5112d5ae6723 3365
mbed_official 545:5112d5ae6723 3366 /**
mbed_official 545:5112d5ae6723 3367 * @brief EXTI3 configuration
mbed_official 545:5112d5ae6723 3368 */
mbed_official 545:5112d5ae6723 3369 #define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!< PA[3] pin */
mbed_official 545:5112d5ae6723 3370 #define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /*!< PB[3] pin */
mbed_official 545:5112d5ae6723 3371 #define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /*!< PC[3] pin */
mbed_official 545:5112d5ae6723 3372 #define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /*!< PD[3] pin */
mbed_official 545:5112d5ae6723 3373 #define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) /*!< PE[3] pin */
mbed_official 545:5112d5ae6723 3374 #define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x00003000) /*!< PF[3] pin */
mbed_official 545:5112d5ae6723 3375 #define SYSCFG_EXTICR1_EXTI3_PG ((uint32_t)0x00004000) /*!< PG[3] pin */
mbed_official 545:5112d5ae6723 3376
mbed_official 545:5112d5ae6723 3377 /***************** Bit definition for SYSCFG_EXTICR2 register *****************/
mbed_official 545:5112d5ae6723 3378 #define SYSCFG_EXTICR2_EXTI4 ((uint32_t)0x0000000F) /*!< EXTI 4 configuration */
mbed_official 545:5112d5ae6723 3379 #define SYSCFG_EXTICR2_EXTI5 ((uint32_t)0x000000F0) /*!< EXTI 5 configuration */
mbed_official 545:5112d5ae6723 3380 #define SYSCFG_EXTICR2_EXTI6 ((uint32_t)0x00000F00) /*!< EXTI 6 configuration */
mbed_official 545:5112d5ae6723 3381 #define SYSCFG_EXTICR2_EXTI7 ((uint32_t)0x0000F000) /*!< EXTI 7 configuration */
mbed_official 545:5112d5ae6723 3382
mbed_official 545:5112d5ae6723 3383 /**
mbed_official 545:5112d5ae6723 3384 * @brief EXTI4 configuration
mbed_official 545:5112d5ae6723 3385 */
mbed_official 545:5112d5ae6723 3386 #define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!< PA[4] pin */
mbed_official 545:5112d5ae6723 3387 #define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /*!< PB[4] pin */
mbed_official 545:5112d5ae6723 3388 #define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /*!< PC[4] pin */
mbed_official 545:5112d5ae6723 3389 #define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /*!< PD[4] pin */
mbed_official 545:5112d5ae6723 3390 #define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) /*!< PE[4] pin */
mbed_official 545:5112d5ae6723 3391 #define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x00000006) /*!< PF[4] pin */
mbed_official 545:5112d5ae6723 3392 #define SYSCFG_EXTICR2_EXTI4_PG ((uint32_t)0x00000007) /*!< PG[4] pin */
mbed_official 545:5112d5ae6723 3393
mbed_official 545:5112d5ae6723 3394 /**
mbed_official 545:5112d5ae6723 3395 * @brief EXTI5 configuration
mbed_official 545:5112d5ae6723 3396 */
mbed_official 545:5112d5ae6723 3397 #define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!< PA[5] pin */
mbed_official 545:5112d5ae6723 3398 #define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /*!< PB[5] pin */
mbed_official 545:5112d5ae6723 3399 #define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /*!< PC[5] pin */
mbed_official 545:5112d5ae6723 3400 #define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /*!< PD[5] pin */
mbed_official 545:5112d5ae6723 3401 #define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) /*!< PE[5] pin */
mbed_official 545:5112d5ae6723 3402 #define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x00000060) /*!< PF[5] pin */
mbed_official 545:5112d5ae6723 3403 #define SYSCFG_EXTICR2_EXTI5_PG ((uint32_t)0x00000070) /*!< PG[5] pin */
mbed_official 545:5112d5ae6723 3404
mbed_official 545:5112d5ae6723 3405 /**
mbed_official 545:5112d5ae6723 3406 * @brief EXTI6 configuration
mbed_official 545:5112d5ae6723 3407 */
mbed_official 545:5112d5ae6723 3408 #define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!< PA[6] pin */
mbed_official 545:5112d5ae6723 3409 #define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /*!< PB[6] pin */
mbed_official 545:5112d5ae6723 3410 #define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /*!< PC[6] pin */
mbed_official 545:5112d5ae6723 3411 #define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /*!< PD[6] pin */
mbed_official 545:5112d5ae6723 3412 #define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) /*!< PE[6] pin */
mbed_official 545:5112d5ae6723 3413 #define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x00000600) /*!< PF[6] pin */
mbed_official 545:5112d5ae6723 3414 #define SYSCFG_EXTICR2_EXTI6_PG ((uint32_t)0x00000700) /*!< PG[6] pin */
mbed_official 545:5112d5ae6723 3415
mbed_official 545:5112d5ae6723 3416 /**
mbed_official 545:5112d5ae6723 3417 * @brief EXTI7 configuration
mbed_official 545:5112d5ae6723 3418 */
mbed_official 545:5112d5ae6723 3419 #define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!< PA[7] pin */
mbed_official 545:5112d5ae6723 3420 #define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /*!< PB[7] pin */
mbed_official 545:5112d5ae6723 3421 #define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /*!< PC[7] pin */
mbed_official 545:5112d5ae6723 3422 #define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /*!< PD[7] pin */
mbed_official 545:5112d5ae6723 3423 #define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) /*!< PE[7] pin */
mbed_official 545:5112d5ae6723 3424 #define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x00006000) /*!< PF[7] pin */
mbed_official 545:5112d5ae6723 3425 #define SYSCFG_EXTICR2_EXTI7_PG ((uint32_t)0x00007000) /*!< PG[7] pin */
mbed_official 545:5112d5ae6723 3426
mbed_official 545:5112d5ae6723 3427 /***************** Bit definition for SYSCFG_EXTICR3 register *****************/
mbed_official 545:5112d5ae6723 3428 #define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x0000000F) /*!< EXTI 8 configuration */
mbed_official 545:5112d5ae6723 3429 #define SYSCFG_EXTICR3_EXTI9 ((uint32_t)0x000000F0) /*!< EXTI 9 configuration */
mbed_official 545:5112d5ae6723 3430 #define SYSCFG_EXTICR3_EXTI10 ((uint32_t)0x00000F00) /*!< EXTI 10 configuration */
mbed_official 545:5112d5ae6723 3431 #define SYSCFG_EXTICR3_EXTI11 ((uint32_t)0x0000F000) /*!< EXTI 11 configuration */
mbed_official 545:5112d5ae6723 3432
mbed_official 545:5112d5ae6723 3433 /**
mbed_official 545:5112d5ae6723 3434 * @brief EXTI8 configuration
mbed_official 545:5112d5ae6723 3435 */
mbed_official 545:5112d5ae6723 3436 #define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!< PA[8] pin */
mbed_official 545:5112d5ae6723 3437 #define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /*!< PB[8] pin */
mbed_official 545:5112d5ae6723 3438 #define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /*!< PC[8] pin */
mbed_official 545:5112d5ae6723 3439 #define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /*!< PD[8] pin */
mbed_official 545:5112d5ae6723 3440 #define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) /*!< PE[8] pin */
mbed_official 545:5112d5ae6723 3441 #define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x00000006) /*!< PF[8] pin */
mbed_official 545:5112d5ae6723 3442 #define SYSCFG_EXTICR3_EXTI8_PG ((uint32_t)0x00000007) /*!< PG[8] pin */
mbed_official 545:5112d5ae6723 3443
mbed_official 545:5112d5ae6723 3444 /**
mbed_official 545:5112d5ae6723 3445 * @brief EXTI9 configuration
mbed_official 545:5112d5ae6723 3446 */
mbed_official 545:5112d5ae6723 3447 #define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!< PA[9] pin */
mbed_official 545:5112d5ae6723 3448 #define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /*!< PB[9] pin */
mbed_official 545:5112d5ae6723 3449 #define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /*!< PC[9] pin */
mbed_official 545:5112d5ae6723 3450 #define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /*!< PD[9] pin */
mbed_official 545:5112d5ae6723 3451 #define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) /*!< PE[9] pin */
mbed_official 545:5112d5ae6723 3452 #define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x00000060) /*!< PF[9] pin */
mbed_official 545:5112d5ae6723 3453 #define SYSCFG_EXTICR3_EXTI9_PG ((uint32_t)0x00000070) /*!< PG[9] pin */
mbed_official 545:5112d5ae6723 3454
mbed_official 545:5112d5ae6723 3455 /**
mbed_official 545:5112d5ae6723 3456 * @brief EXTI10 configuration
mbed_official 545:5112d5ae6723 3457 */
mbed_official 545:5112d5ae6723 3458 #define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!< PA[10] pin */
mbed_official 545:5112d5ae6723 3459 #define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /*!< PB[10] pin */
mbed_official 545:5112d5ae6723 3460 #define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /*!< PC[10] pin */
mbed_official 545:5112d5ae6723 3461 #define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /*!< PD[10] pin */
mbed_official 545:5112d5ae6723 3462 #define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) /*!< PE[10] pin */
mbed_official 545:5112d5ae6723 3463 #define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x00000600) /*!< PF[10] pin */
mbed_official 545:5112d5ae6723 3464 #define SYSCFG_EXTICR3_EXTI10_PG ((uint32_t)0x00000700) /*!< PG[10] pin */
mbed_official 545:5112d5ae6723 3465
mbed_official 545:5112d5ae6723 3466 /**
mbed_official 545:5112d5ae6723 3467 * @brief EXTI11 configuration
mbed_official 545:5112d5ae6723 3468 */
mbed_official 545:5112d5ae6723 3469 #define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!< PA[11] pin */
mbed_official 545:5112d5ae6723 3470 #define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /*!< PB[11] pin */
mbed_official 545:5112d5ae6723 3471 #define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /*!< PC[11] pin */
mbed_official 545:5112d5ae6723 3472 #define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /*!< PD[11] pin */
mbed_official 545:5112d5ae6723 3473 #define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) /*!< PE[11] pin */
mbed_official 545:5112d5ae6723 3474 #define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x00006000) /*!< PF[11] pin */
mbed_official 545:5112d5ae6723 3475 #define SYSCFG_EXTICR3_EXTI11_PG ((uint32_t)0x00007000) /*!< PG[11] pin */
mbed_official 545:5112d5ae6723 3476
mbed_official 545:5112d5ae6723 3477 /***************** Bit definition for SYSCFG_EXTICR4 register *****************/
mbed_official 545:5112d5ae6723 3478 #define SYSCFG_EXTICR4_EXTI12 ((uint32_t)0x0000000F) /*!< EXTI 12 configuration */
mbed_official 545:5112d5ae6723 3479 #define SYSCFG_EXTICR4_EXTI13 ((uint32_t)0x000000F0) /*!< EXTI 13 configuration */
mbed_official 545:5112d5ae6723 3480 #define SYSCFG_EXTICR4_EXTI14 ((uint32_t)0x00000F00) /*!< EXTI 14 configuration */
mbed_official 545:5112d5ae6723 3481 #define SYSCFG_EXTICR4_EXTI15 ((uint32_t)0x0000F000) /*!< EXTI 15 configuration */
mbed_official 545:5112d5ae6723 3482
mbed_official 545:5112d5ae6723 3483 /**
mbed_official 545:5112d5ae6723 3484 * @brief EXTI12 configuration
mbed_official 545:5112d5ae6723 3485 */
mbed_official 545:5112d5ae6723 3486 #define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!< PA[12] pin */
mbed_official 545:5112d5ae6723 3487 #define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /*!< PB[12] pin */
mbed_official 545:5112d5ae6723 3488 #define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /*!< PC[12] pin */
mbed_official 545:5112d5ae6723 3489 #define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /*!< PD[12] pin */
mbed_official 545:5112d5ae6723 3490 #define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) /*!< PE[12] pin */
mbed_official 545:5112d5ae6723 3491 #define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x00000006) /*!< PF[12] pin */
mbed_official 545:5112d5ae6723 3492 #define SYSCFG_EXTICR4_EXTI12_PG ((uint32_t)0x00000007) /*!< PG[12] pin */
mbed_official 545:5112d5ae6723 3493
mbed_official 545:5112d5ae6723 3494 /**
mbed_official 545:5112d5ae6723 3495 * @brief EXTI13 configuration
mbed_official 545:5112d5ae6723 3496 */
mbed_official 545:5112d5ae6723 3497 #define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!< PA[13] pin */
mbed_official 545:5112d5ae6723 3498 #define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /*!< PB[13] pin */
mbed_official 545:5112d5ae6723 3499 #define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /*!< PC[13] pin */
mbed_official 545:5112d5ae6723 3500 #define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /*!< PD[13] pin */
mbed_official 545:5112d5ae6723 3501 #define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) /*!< PE[13] pin */
mbed_official 545:5112d5ae6723 3502 #define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x00000060) /*!< PF[13] pin */
mbed_official 545:5112d5ae6723 3503 #define SYSCFG_EXTICR4_EXTI13_PG ((uint32_t)0x00000070) /*!< PG[13] pin */
mbed_official 545:5112d5ae6723 3504
mbed_official 545:5112d5ae6723 3505 /**
mbed_official 545:5112d5ae6723 3506 * @brief EXTI14 configuration
mbed_official 545:5112d5ae6723 3507 */
mbed_official 545:5112d5ae6723 3508 #define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!< PA[14] pin */
mbed_official 545:5112d5ae6723 3509 #define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /*!< PB[14] pin */
mbed_official 545:5112d5ae6723 3510 #define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /*!< PC[14] pin */
mbed_official 545:5112d5ae6723 3511 #define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /*!< PD[14] pin */
mbed_official 545:5112d5ae6723 3512 #define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) /*!< PE[14] pin */
mbed_official 545:5112d5ae6723 3513 #define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x00000600) /*!< PF[14] pin */
mbed_official 545:5112d5ae6723 3514 #define SYSCFG_EXTICR4_EXTI14_PG ((uint32_t)0x00000700) /*!< PG[14] pin */
mbed_official 545:5112d5ae6723 3515
mbed_official 545:5112d5ae6723 3516 /**
mbed_official 545:5112d5ae6723 3517 * @brief EXTI15 configuration
mbed_official 545:5112d5ae6723 3518 */
mbed_official 545:5112d5ae6723 3519 #define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!< PA[15] pin */
mbed_official 545:5112d5ae6723 3520 #define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /*!< PB[15] pin */
mbed_official 545:5112d5ae6723 3521 #define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /*!< PC[15] pin */
mbed_official 545:5112d5ae6723 3522 #define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!< PD[15] pin */
mbed_official 545:5112d5ae6723 3523 #define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /*!< PE[15] pin */
mbed_official 545:5112d5ae6723 3524 #define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x00006000) /*!< PF[15] pin */
mbed_official 545:5112d5ae6723 3525 #define SYSCFG_EXTICR4_EXTI15_PG ((uint32_t)0x00007000) /*!< PG[15] pin */
mbed_official 545:5112d5ae6723 3526
mbed_official 545:5112d5ae6723 3527 /******************************************************************************/
mbed_official 545:5112d5ae6723 3528 /* */
mbed_official 545:5112d5ae6723 3529 /* Routing Interface (RI) */
mbed_official 545:5112d5ae6723 3530 /* */
mbed_official 545:5112d5ae6723 3531 /******************************************************************************/
mbed_official 545:5112d5ae6723 3532
mbed_official 545:5112d5ae6723 3533 /******************** Bit definition for RI_ICR register ********************/
mbed_official 545:5112d5ae6723 3534 #define RI_ICR_IC1OS ((uint32_t)0x0000000F) /*!< IC1OS[3:0] bits (Input Capture 1 select bits) */
mbed_official 545:5112d5ae6723 3535 #define RI_ICR_IC1OS_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 3536 #define RI_ICR_IC1OS_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 3537 #define RI_ICR_IC1OS_2 ((uint32_t)0x00000004) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 3538 #define RI_ICR_IC1OS_3 ((uint32_t)0x00000008) /*!< Bit 3 */
mbed_official 545:5112d5ae6723 3539
mbed_official 545:5112d5ae6723 3540 #define RI_ICR_IC2OS ((uint32_t)0x000000F0) /*!< IC2OS[3:0] bits (Input Capture 2 select bits) */
mbed_official 545:5112d5ae6723 3541 #define RI_ICR_IC2OS_0 ((uint32_t)0x00000010) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 3542 #define RI_ICR_IC2OS_1 ((uint32_t)0x00000020) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 3543 #define RI_ICR_IC2OS_2 ((uint32_t)0x00000040) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 3544 #define RI_ICR_IC2OS_3 ((uint32_t)0x00000080) /*!< Bit 3 */
mbed_official 545:5112d5ae6723 3545
mbed_official 545:5112d5ae6723 3546 #define RI_ICR_IC3OS ((uint32_t)0x00000F00) /*!< IC3OS[3:0] bits (Input Capture 3 select bits) */
mbed_official 545:5112d5ae6723 3547 #define RI_ICR_IC3OS_0 ((uint32_t)0x00000100) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 3548 #define RI_ICR_IC3OS_1 ((uint32_t)0x00000200) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 3549 #define RI_ICR_IC3OS_2 ((uint32_t)0x00000400) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 3550 #define RI_ICR_IC3OS_3 ((uint32_t)0x00000800) /*!< Bit 3 */
mbed_official 545:5112d5ae6723 3551
mbed_official 545:5112d5ae6723 3552 #define RI_ICR_IC4OS ((uint32_t)0x0000F000) /*!< IC4OS[3:0] bits (Input Capture 4 select bits) */
mbed_official 545:5112d5ae6723 3553 #define RI_ICR_IC4OS_0 ((uint32_t)0x00001000) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 3554 #define RI_ICR_IC4OS_1 ((uint32_t)0x00002000) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 3555 #define RI_ICR_IC4OS_2 ((uint32_t)0x00004000) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 3556 #define RI_ICR_IC4OS_3 ((uint32_t)0x00008000) /*!< Bit 3 */
mbed_official 545:5112d5ae6723 3557
mbed_official 545:5112d5ae6723 3558 #define RI_ICR_TIM ((uint32_t)0x00030000) /*!< TIM[3:0] bits (Timers select bits) */
mbed_official 545:5112d5ae6723 3559 #define RI_ICR_TIM_0 ((uint32_t)0x00010000) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 3560 #define RI_ICR_TIM_1 ((uint32_t)0x00020000) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 3561
mbed_official 545:5112d5ae6723 3562 #define RI_ICR_IC1 ((uint32_t)0x00040000) /*!< Input capture 1 */
mbed_official 545:5112d5ae6723 3563 #define RI_ICR_IC2 ((uint32_t)0x00080000) /*!< Input capture 2 */
mbed_official 545:5112d5ae6723 3564 #define RI_ICR_IC3 ((uint32_t)0x00100000) /*!< Input capture 3 */
mbed_official 545:5112d5ae6723 3565 #define RI_ICR_IC4 ((uint32_t)0x00200000) /*!< Input capture 4 */
mbed_official 545:5112d5ae6723 3566
mbed_official 545:5112d5ae6723 3567 /******************** Bit definition for RI_ASCR1 register ********************/
mbed_official 545:5112d5ae6723 3568 #define RI_ASCR1_CH ((uint32_t)0x7BFDFFFF) /*!< AS_CH[25:18] & AS_CH[15:0] bits ( Analog switches selection bits) */
mbed_official 545:5112d5ae6723 3569 #define RI_ASCR1_CH_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 3570 #define RI_ASCR1_CH_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 3571 #define RI_ASCR1_CH_2 ((uint32_t)0x00000004) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 3572 #define RI_ASCR1_CH_3 ((uint32_t)0x00000008) /*!< Bit 3 */
mbed_official 545:5112d5ae6723 3573 #define RI_ASCR1_CH_4 ((uint32_t)0x00000010) /*!< Bit 4 */
mbed_official 545:5112d5ae6723 3574 #define RI_ASCR1_CH_5 ((uint32_t)0x00000020) /*!< Bit 5 */
mbed_official 545:5112d5ae6723 3575 #define RI_ASCR1_CH_6 ((uint32_t)0x00000040) /*!< Bit 6 */
mbed_official 545:5112d5ae6723 3576 #define RI_ASCR1_CH_7 ((uint32_t)0x00000080) /*!< Bit 7 */
mbed_official 545:5112d5ae6723 3577 #define RI_ASCR1_CH_8 ((uint32_t)0x00000100) /*!< Bit 8 */
mbed_official 545:5112d5ae6723 3578 #define RI_ASCR1_CH_9 ((uint32_t)0x00000200) /*!< Bit 9 */
mbed_official 545:5112d5ae6723 3579 #define RI_ASCR1_CH_10 ((uint32_t)0x00000400) /*!< Bit 10 */
mbed_official 545:5112d5ae6723 3580 #define RI_ASCR1_CH_11 ((uint32_t)0x00000800) /*!< Bit 11 */
mbed_official 545:5112d5ae6723 3581 #define RI_ASCR1_CH_12 ((uint32_t)0x00001000) /*!< Bit 12 */
mbed_official 545:5112d5ae6723 3582 #define RI_ASCR1_CH_13 ((uint32_t)0x00002000) /*!< Bit 13 */
mbed_official 545:5112d5ae6723 3583 #define RI_ASCR1_CH_14 ((uint32_t)0x00004000) /*!< Bit 14 */
mbed_official 545:5112d5ae6723 3584 #define RI_ASCR1_CH_15 ((uint32_t)0x00008000) /*!< Bit 15 */
mbed_official 545:5112d5ae6723 3585 #define RI_ASCR1_CH_31 ((uint32_t)0x00010000) /*!< Bit 16 */
mbed_official 545:5112d5ae6723 3586 #define RI_ASCR1_CH_18 ((uint32_t)0x00040000) /*!< Bit 18 */
mbed_official 545:5112d5ae6723 3587 #define RI_ASCR1_CH_19 ((uint32_t)0x00080000) /*!< Bit 19 */
mbed_official 545:5112d5ae6723 3588 #define RI_ASCR1_CH_20 ((uint32_t)0x00100000) /*!< Bit 20 */
mbed_official 545:5112d5ae6723 3589 #define RI_ASCR1_CH_21 ((uint32_t)0x00200000) /*!< Bit 21 */
mbed_official 545:5112d5ae6723 3590 #define RI_ASCR1_CH_22 ((uint32_t)0x00400000) /*!< Bit 22 */
mbed_official 545:5112d5ae6723 3591 #define RI_ASCR1_CH_23 ((uint32_t)0x00800000) /*!< Bit 23 */
mbed_official 545:5112d5ae6723 3592 #define RI_ASCR1_CH_24 ((uint32_t)0x01000000) /*!< Bit 24 */
mbed_official 545:5112d5ae6723 3593 #define RI_ASCR1_CH_25 ((uint32_t)0x02000000) /*!< Bit 25 */
mbed_official 545:5112d5ae6723 3594 #define RI_ASCR1_VCOMP ((uint32_t)0x04000000) /*!< ADC analog switch selection for internal node to COMP1 */
mbed_official 545:5112d5ae6723 3595 #define RI_ASCR1_CH_27 ((uint32_t)0x00400000) /*!< Bit 27 */
mbed_official 545:5112d5ae6723 3596 #define RI_ASCR1_CH_28 ((uint32_t)0x00800000) /*!< Bit 28 */
mbed_official 545:5112d5ae6723 3597 #define RI_ASCR1_CH_29 ((uint32_t)0x01000000) /*!< Bit 29 */
mbed_official 545:5112d5ae6723 3598 #define RI_ASCR1_CH_30 ((uint32_t)0x02000000) /*!< Bit 30 */
mbed_official 545:5112d5ae6723 3599 #define RI_ASCR1_SCM ((uint32_t)0x80000000) /*!< I/O Switch control mode */
mbed_official 545:5112d5ae6723 3600
mbed_official 545:5112d5ae6723 3601 /******************** Bit definition for RI_ASCR2 register ********************/
mbed_official 545:5112d5ae6723 3602 #define RI_ASCR2_GR10_1 ((uint32_t)0x00000001) /*!< GR10-1 selection bit */
mbed_official 545:5112d5ae6723 3603 #define RI_ASCR2_GR10_2 ((uint32_t)0x00000002) /*!< GR10-2 selection bit */
mbed_official 545:5112d5ae6723 3604 #define RI_ASCR2_GR10_3 ((uint32_t)0x00000004) /*!< GR10-3 selection bit */
mbed_official 545:5112d5ae6723 3605 #define RI_ASCR2_GR10_4 ((uint32_t)0x00000008) /*!< GR10-4 selection bit */
mbed_official 545:5112d5ae6723 3606 #define RI_ASCR2_GR6_1 ((uint32_t)0x00000010) /*!< GR6-1 selection bit */
mbed_official 545:5112d5ae6723 3607 #define RI_ASCR2_GR6_2 ((uint32_t)0x00000020) /*!< GR6-2 selection bit */
mbed_official 545:5112d5ae6723 3608 #define RI_ASCR2_GR5_1 ((uint32_t)0x00000040) /*!< GR5-1 selection bit */
mbed_official 545:5112d5ae6723 3609 #define RI_ASCR2_GR5_2 ((uint32_t)0x00000080) /*!< GR5-2 selection bit */
mbed_official 545:5112d5ae6723 3610 #define RI_ASCR2_GR5_3 ((uint32_t)0x00000100) /*!< GR5-3 selection bit */
mbed_official 545:5112d5ae6723 3611 #define RI_ASCR2_GR4_1 ((uint32_t)0x00000200) /*!< GR4-1 selection bit */
mbed_official 545:5112d5ae6723 3612 #define RI_ASCR2_GR4_2 ((uint32_t)0x00000400) /*!< GR4-2 selection bit */
mbed_official 545:5112d5ae6723 3613 #define RI_ASCR2_GR4_3 ((uint32_t)0x00000800) /*!< GR4-3 selection bit */
mbed_official 545:5112d5ae6723 3614 #define RI_ASCR2_GR4_4 ((uint32_t)0x00008000) /*!< GR4-4 selection bit */
mbed_official 545:5112d5ae6723 3615 #define RI_ASCR2_CH0b ((uint32_t)0x00010000) /*!< CH0b selection bit */
mbed_official 545:5112d5ae6723 3616 #define RI_ASCR2_GR6_3 ((uint32_t)0x08000000) /*!< GR6-3 selection bit */
mbed_official 545:5112d5ae6723 3617 #define RI_ASCR2_GR6_4 ((uint32_t)0x10000000) /*!< GR6-4 selection bit */
mbed_official 545:5112d5ae6723 3618
mbed_official 545:5112d5ae6723 3619 /******************** Bit definition for RI_HYSCR1 register ********************/
mbed_official 545:5112d5ae6723 3620 #define RI_HYSCR1_PA ((uint32_t)0x0000FFFF) /*!< PA[15:0] Port A Hysteresis selection */
mbed_official 545:5112d5ae6723 3621 #define RI_HYSCR1_PA_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 3622 #define RI_HYSCR1_PA_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 3623 #define RI_HYSCR1_PA_2 ((uint32_t)0x00000004) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 3624 #define RI_HYSCR1_PA_3 ((uint32_t)0x00000008) /*!< Bit 3 */
mbed_official 545:5112d5ae6723 3625 #define RI_HYSCR1_PA_4 ((uint32_t)0x00000010) /*!< Bit 4 */
mbed_official 545:5112d5ae6723 3626 #define RI_HYSCR1_PA_5 ((uint32_t)0x00000020) /*!< Bit 5 */
mbed_official 545:5112d5ae6723 3627 #define RI_HYSCR1_PA_6 ((uint32_t)0x00000040) /*!< Bit 6 */
mbed_official 545:5112d5ae6723 3628 #define RI_HYSCR1_PA_7 ((uint32_t)0x00000080) /*!< Bit 7 */
mbed_official 545:5112d5ae6723 3629 #define RI_HYSCR1_PA_8 ((uint32_t)0x00000100) /*!< Bit 8 */
mbed_official 545:5112d5ae6723 3630 #define RI_HYSCR1_PA_9 ((uint32_t)0x00000200) /*!< Bit 9 */
mbed_official 545:5112d5ae6723 3631 #define RI_HYSCR1_PA_10 ((uint32_t)0x00000400) /*!< Bit 10 */
mbed_official 545:5112d5ae6723 3632 #define RI_HYSCR1_PA_11 ((uint32_t)0x00000800) /*!< Bit 11 */
mbed_official 545:5112d5ae6723 3633 #define RI_HYSCR1_PA_12 ((uint32_t)0x00001000) /*!< Bit 12 */
mbed_official 545:5112d5ae6723 3634 #define RI_HYSCR1_PA_13 ((uint32_t)0x00002000) /*!< Bit 13 */
mbed_official 545:5112d5ae6723 3635 #define RI_HYSCR1_PA_14 ((uint32_t)0x00004000) /*!< Bit 14 */
mbed_official 545:5112d5ae6723 3636 #define RI_HYSCR1_PA_15 ((uint32_t)0x00008000) /*!< Bit 15 */
mbed_official 545:5112d5ae6723 3637
mbed_official 545:5112d5ae6723 3638 #define RI_HYSCR1_PB ((uint32_t)0xFFFF0000) /*!< PB[15:0] Port B Hysteresis selection */
mbed_official 545:5112d5ae6723 3639 #define RI_HYSCR1_PB_0 ((uint32_t)0x00010000) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 3640 #define RI_HYSCR1_PB_1 ((uint32_t)0x00020000) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 3641 #define RI_HYSCR1_PB_2 ((uint32_t)0x00040000) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 3642 #define RI_HYSCR1_PB_3 ((uint32_t)0x00080000) /*!< Bit 3 */
mbed_official 545:5112d5ae6723 3643 #define RI_HYSCR1_PB_4 ((uint32_t)0x00100000) /*!< Bit 4 */
mbed_official 545:5112d5ae6723 3644 #define RI_HYSCR1_PB_5 ((uint32_t)0x00200000) /*!< Bit 5 */
mbed_official 545:5112d5ae6723 3645 #define RI_HYSCR1_PB_6 ((uint32_t)0x00400000) /*!< Bit 6 */
mbed_official 545:5112d5ae6723 3646 #define RI_HYSCR1_PB_7 ((uint32_t)0x00800000) /*!< Bit 7 */
mbed_official 545:5112d5ae6723 3647 #define RI_HYSCR1_PB_8 ((uint32_t)0x01000000) /*!< Bit 8 */
mbed_official 545:5112d5ae6723 3648 #define RI_HYSCR1_PB_9 ((uint32_t)0x02000000) /*!< Bit 9 */
mbed_official 545:5112d5ae6723 3649 #define RI_HYSCR1_PB_10 ((uint32_t)0x04000000) /*!< Bit 10 */
mbed_official 545:5112d5ae6723 3650 #define RI_HYSCR1_PB_11 ((uint32_t)0x08000000) /*!< Bit 11 */
mbed_official 545:5112d5ae6723 3651 #define RI_HYSCR1_PB_12 ((uint32_t)0x10000000) /*!< Bit 12 */
mbed_official 545:5112d5ae6723 3652 #define RI_HYSCR1_PB_13 ((uint32_t)0x20000000) /*!< Bit 13 */
mbed_official 545:5112d5ae6723 3653 #define RI_HYSCR1_PB_14 ((uint32_t)0x40000000) /*!< Bit 14 */
mbed_official 545:5112d5ae6723 3654 #define RI_HYSCR1_PB_15 ((uint32_t)0x80000000) /*!< Bit 15 */
mbed_official 545:5112d5ae6723 3655
mbed_official 545:5112d5ae6723 3656 /******************** Bit definition for RI_HYSCR2 register ********************/
mbed_official 545:5112d5ae6723 3657 #define RI_HYSCR2_PC ((uint32_t)0x0000FFFF) /*!< PC[15:0] Port C Hysteresis selection */
mbed_official 545:5112d5ae6723 3658 #define RI_HYSCR2_PC_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 3659 #define RI_HYSCR2_PC_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 3660 #define RI_HYSCR2_PC_2 ((uint32_t)0x00000004) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 3661 #define RI_HYSCR2_PC_3 ((uint32_t)0x00000008) /*!< Bit 3 */
mbed_official 545:5112d5ae6723 3662 #define RI_HYSCR2_PC_4 ((uint32_t)0x00000010) /*!< Bit 4 */
mbed_official 545:5112d5ae6723 3663 #define RI_HYSCR2_PC_5 ((uint32_t)0x00000020) /*!< Bit 5 */
mbed_official 545:5112d5ae6723 3664 #define RI_HYSCR2_PC_6 ((uint32_t)0x00000040) /*!< Bit 6 */
mbed_official 545:5112d5ae6723 3665 #define RI_HYSCR2_PC_7 ((uint32_t)0x00000080) /*!< Bit 7 */
mbed_official 545:5112d5ae6723 3666 #define RI_HYSCR2_PC_8 ((uint32_t)0x00000100) /*!< Bit 8 */
mbed_official 545:5112d5ae6723 3667 #define RI_HYSCR2_PC_9 ((uint32_t)0x00000200) /*!< Bit 9 */
mbed_official 545:5112d5ae6723 3668 #define RI_HYSCR2_PC_10 ((uint32_t)0x00000400) /*!< Bit 10 */
mbed_official 545:5112d5ae6723 3669 #define RI_HYSCR2_PC_11 ((uint32_t)0x00000800) /*!< Bit 11 */
mbed_official 545:5112d5ae6723 3670 #define RI_HYSCR2_PC_12 ((uint32_t)0x00001000) /*!< Bit 12 */
mbed_official 545:5112d5ae6723 3671 #define RI_HYSCR2_PC_13 ((uint32_t)0x00002000) /*!< Bit 13 */
mbed_official 545:5112d5ae6723 3672 #define RI_HYSCR2_PC_14 ((uint32_t)0x00004000) /*!< Bit 14 */
mbed_official 545:5112d5ae6723 3673 #define RI_HYSCR2_PC_15 ((uint32_t)0x00008000) /*!< Bit 15 */
mbed_official 545:5112d5ae6723 3674
mbed_official 545:5112d5ae6723 3675 #define RI_HYSCR2_PD ((uint32_t)0xFFFF0000) /*!< PD[15:0] Port D Hysteresis selection */
mbed_official 545:5112d5ae6723 3676 #define RI_HYSCR2_PD_0 ((uint32_t)0x00010000) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 3677 #define RI_HYSCR2_PD_1 ((uint32_t)0x00020000) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 3678 #define RI_HYSCR2_PD_2 ((uint32_t)0x00040000) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 3679 #define RI_HYSCR2_PD_3 ((uint32_t)0x00080000) /*!< Bit 3 */
mbed_official 545:5112d5ae6723 3680 #define RI_HYSCR2_PD_4 ((uint32_t)0x00100000) /*!< Bit 4 */
mbed_official 545:5112d5ae6723 3681 #define RI_HYSCR2_PD_5 ((uint32_t)0x00200000) /*!< Bit 5 */
mbed_official 545:5112d5ae6723 3682 #define RI_HYSCR2_PD_6 ((uint32_t)0x00400000) /*!< Bit 6 */
mbed_official 545:5112d5ae6723 3683 #define RI_HYSCR2_PD_7 ((uint32_t)0x00800000) /*!< Bit 7 */
mbed_official 545:5112d5ae6723 3684 #define RI_HYSCR2_PD_8 ((uint32_t)0x01000000) /*!< Bit 8 */
mbed_official 545:5112d5ae6723 3685 #define RI_HYSCR2_PD_9 ((uint32_t)0x02000000) /*!< Bit 9 */
mbed_official 545:5112d5ae6723 3686 #define RI_HYSCR2_PD_10 ((uint32_t)0x04000000) /*!< Bit 10 */
mbed_official 545:5112d5ae6723 3687 #define RI_HYSCR2_PD_11 ((uint32_t)0x08000000) /*!< Bit 11 */
mbed_official 545:5112d5ae6723 3688 #define RI_HYSCR2_PD_12 ((uint32_t)0x10000000) /*!< Bit 12 */
mbed_official 545:5112d5ae6723 3689 #define RI_HYSCR2_PD_13 ((uint32_t)0x20000000) /*!< Bit 13 */
mbed_official 545:5112d5ae6723 3690 #define RI_HYSCR2_PD_14 ((uint32_t)0x40000000) /*!< Bit 14 */
mbed_official 545:5112d5ae6723 3691 #define RI_HYSCR2_PD_15 ((uint32_t)0x80000000) /*!< Bit 15 */
mbed_official 545:5112d5ae6723 3692
mbed_official 545:5112d5ae6723 3693 /******************** Bit definition for RI_HYSCR3 register ********************/
mbed_official 545:5112d5ae6723 3694 #define RI_HYSCR3_PE ((uint32_t)0x0000FFFF) /*!< PE[15:0] Port E Hysteresis selection */
mbed_official 545:5112d5ae6723 3695 #define RI_HYSCR3_PE_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 3696 #define RI_HYSCR3_PE_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 3697 #define RI_HYSCR3_PE_2 ((uint32_t)0x00000004) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 3698 #define RI_HYSCR3_PE_3 ((uint32_t)0x00000008) /*!< Bit 3 */
mbed_official 545:5112d5ae6723 3699 #define RI_HYSCR3_PE_4 ((uint32_t)0x00000010) /*!< Bit 4 */
mbed_official 545:5112d5ae6723 3700 #define RI_HYSCR3_PE_5 ((uint32_t)0x00000020) /*!< Bit 5 */
mbed_official 545:5112d5ae6723 3701 #define RI_HYSCR3_PE_6 ((uint32_t)0x00000040) /*!< Bit 6 */
mbed_official 545:5112d5ae6723 3702 #define RI_HYSCR3_PE_7 ((uint32_t)0x00000080) /*!< Bit 7 */
mbed_official 545:5112d5ae6723 3703 #define RI_HYSCR3_PE_8 ((uint32_t)0x00000100) /*!< Bit 8 */
mbed_official 545:5112d5ae6723 3704 #define RI_HYSCR3_PE_9 ((uint32_t)0x00000200) /*!< Bit 9 */
mbed_official 545:5112d5ae6723 3705 #define RI_HYSCR3_PE_10 ((uint32_t)0x00000400) /*!< Bit 10 */
mbed_official 545:5112d5ae6723 3706 #define RI_HYSCR3_PE_11 ((uint32_t)0x00000800) /*!< Bit 11 */
mbed_official 545:5112d5ae6723 3707 #define RI_HYSCR3_PE_12 ((uint32_t)0x00001000) /*!< Bit 12 */
mbed_official 545:5112d5ae6723 3708 #define RI_HYSCR3_PE_13 ((uint32_t)0x00002000) /*!< Bit 13 */
mbed_official 545:5112d5ae6723 3709 #define RI_HYSCR3_PE_14 ((uint32_t)0x00004000) /*!< Bit 14 */
mbed_official 545:5112d5ae6723 3710 #define RI_HYSCR3_PE_15 ((uint32_t)0x00008000) /*!< Bit 15 */
mbed_official 545:5112d5ae6723 3711
mbed_official 545:5112d5ae6723 3712 /******************** Bit definition for RI_ASMR1 register ********************/
mbed_official 545:5112d5ae6723 3713 #define RI_ASMR1_PA ((uint32_t)0x0000FFFF) /*!< PA[15:0] Port A selection*/
mbed_official 545:5112d5ae6723 3714 #define RI_ASMR1_PA_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 3715 #define RI_ASMR1_PA_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 3716 #define RI_ASMR1_PA_2 ((uint32_t)0x00000004) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 3717 #define RI_ASMR1_PA_3 ((uint32_t)0x00000008) /*!< Bit 3 */
mbed_official 545:5112d5ae6723 3718 #define RI_ASMR1_PA_4 ((uint32_t)0x00000010) /*!< Bit 4 */
mbed_official 545:5112d5ae6723 3719 #define RI_ASMR1_PA_5 ((uint32_t)0x00000020) /*!< Bit 5 */
mbed_official 545:5112d5ae6723 3720 #define RI_ASMR1_PA_6 ((uint32_t)0x00000040) /*!< Bit 6 */
mbed_official 545:5112d5ae6723 3721 #define RI_ASMR1_PA_7 ((uint32_t)0x00000080) /*!< Bit 7 */
mbed_official 545:5112d5ae6723 3722 #define RI_ASMR1_PA_8 ((uint32_t)0x00000100) /*!< Bit 8 */
mbed_official 545:5112d5ae6723 3723 #define RI_ASMR1_PA_9 ((uint32_t)0x00000200) /*!< Bit 9 */
mbed_official 545:5112d5ae6723 3724 #define RI_ASMR1_PA_10 ((uint32_t)0x00000400) /*!< Bit 10 */
mbed_official 545:5112d5ae6723 3725 #define RI_ASMR1_PA_11 ((uint32_t)0x00000800) /*!< Bit 11 */
mbed_official 545:5112d5ae6723 3726 #define RI_ASMR1_PA_12 ((uint32_t)0x00001000) /*!< Bit 12 */
mbed_official 545:5112d5ae6723 3727 #define RI_ASMR1_PA_13 ((uint32_t)0x00002000) /*!< Bit 13 */
mbed_official 545:5112d5ae6723 3728 #define RI_ASMR1_PA_14 ((uint32_t)0x00004000) /*!< Bit 14 */
mbed_official 545:5112d5ae6723 3729 #define RI_ASMR1_PA_15 ((uint32_t)0x00008000) /*!< Bit 15 */
mbed_official 545:5112d5ae6723 3730
mbed_official 545:5112d5ae6723 3731 /******************** Bit definition for RI_CMR1 register ********************/
mbed_official 545:5112d5ae6723 3732 #define RI_CMR1_PA ((uint32_t)0x0000FFFF) /*!< PA[15:0] Port A selection*/
mbed_official 545:5112d5ae6723 3733 #define RI_CMR1_PA_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 3734 #define RI_CMR1_PA_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 3735 #define RI_CMR1_PA_2 ((uint32_t)0x00000004) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 3736 #define RI_CMR1_PA_3 ((uint32_t)0x00000008) /*!< Bit 3 */
mbed_official 545:5112d5ae6723 3737 #define RI_CMR1_PA_4 ((uint32_t)0x00000010) /*!< Bit 4 */
mbed_official 545:5112d5ae6723 3738 #define RI_CMR1_PA_5 ((uint32_t)0x00000020) /*!< Bit 5 */
mbed_official 545:5112d5ae6723 3739 #define RI_CMR1_PA_6 ((uint32_t)0x00000040) /*!< Bit 6 */
mbed_official 545:5112d5ae6723 3740 #define RI_CMR1_PA_7 ((uint32_t)0x00000080) /*!< Bit 7 */
mbed_official 545:5112d5ae6723 3741 #define RI_CMR1_PA_8 ((uint32_t)0x00000100) /*!< Bit 8 */
mbed_official 545:5112d5ae6723 3742 #define RI_CMR1_PA_9 ((uint32_t)0x00000200) /*!< Bit 9 */
mbed_official 545:5112d5ae6723 3743 #define RI_CMR1_PA_10 ((uint32_t)0x00000400) /*!< Bit 10 */
mbed_official 545:5112d5ae6723 3744 #define RI_CMR1_PA_11 ((uint32_t)0x00000800) /*!< Bit 11 */
mbed_official 545:5112d5ae6723 3745 #define RI_CMR1_PA_12 ((uint32_t)0x00001000) /*!< Bit 12 */
mbed_official 545:5112d5ae6723 3746 #define RI_CMR1_PA_13 ((uint32_t)0x00002000) /*!< Bit 13 */
mbed_official 545:5112d5ae6723 3747 #define RI_CMR1_PA_14 ((uint32_t)0x00004000) /*!< Bit 14 */
mbed_official 545:5112d5ae6723 3748 #define RI_CMR1_PA_15 ((uint32_t)0x00008000) /*!< Bit 15 */
mbed_official 545:5112d5ae6723 3749
mbed_official 545:5112d5ae6723 3750 /******************** Bit definition for RI_CICR1 register ********************/
mbed_official 545:5112d5ae6723 3751 #define RI_CICR1_PA ((uint32_t)0x0000FFFF) /*!< PA[15:0] Port A selection*/
mbed_official 545:5112d5ae6723 3752 #define RI_CICR1_PA_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 3753 #define RI_CICR1_PA_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 3754 #define RI_CICR1_PA_2 ((uint32_t)0x00000004) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 3755 #define RI_CICR1_PA_3 ((uint32_t)0x00000008) /*!< Bit 3 */
mbed_official 545:5112d5ae6723 3756 #define RI_CICR1_PA_4 ((uint32_t)0x00000010) /*!< Bit 4 */
mbed_official 545:5112d5ae6723 3757 #define RI_CICR1_PA_5 ((uint32_t)0x00000020) /*!< Bit 5 */
mbed_official 545:5112d5ae6723 3758 #define RI_CICR1_PA_6 ((uint32_t)0x00000040) /*!< Bit 6 */
mbed_official 545:5112d5ae6723 3759 #define RI_CICR1_PA_7 ((uint32_t)0x00000080) /*!< Bit 7 */
mbed_official 545:5112d5ae6723 3760 #define RI_CICR1_PA_8 ((uint32_t)0x00000100) /*!< Bit 8 */
mbed_official 545:5112d5ae6723 3761 #define RI_CICR1_PA_9 ((uint32_t)0x00000200) /*!< Bit 9 */
mbed_official 545:5112d5ae6723 3762 #define RI_CICR1_PA_10 ((uint32_t)0x00000400) /*!< Bit 10 */
mbed_official 545:5112d5ae6723 3763 #define RI_CICR1_PA_11 ((uint32_t)0x00000800) /*!< Bit 11 */
mbed_official 545:5112d5ae6723 3764 #define RI_CICR1_PA_12 ((uint32_t)0x00001000) /*!< Bit 12 */
mbed_official 545:5112d5ae6723 3765 #define RI_CICR1_PA_13 ((uint32_t)0x00002000) /*!< Bit 13 */
mbed_official 545:5112d5ae6723 3766 #define RI_CICR1_PA_14 ((uint32_t)0x00004000) /*!< Bit 14 */
mbed_official 545:5112d5ae6723 3767 #define RI_CICR1_PA_15 ((uint32_t)0x00008000) /*!< Bit 15 */
mbed_official 545:5112d5ae6723 3768
mbed_official 545:5112d5ae6723 3769 /******************** Bit definition for RI_ASMR2 register ********************/
mbed_official 545:5112d5ae6723 3770 #define RI_ASMR2_PB ((uint32_t)0x0000FFFF) /*!< PB[15:0] Port B selection */
mbed_official 545:5112d5ae6723 3771 #define RI_ASMR2_PB_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 3772 #define RI_ASMR2_PB_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 3773 #define RI_ASMR2_PB_2 ((uint32_t)0x00000004) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 3774 #define RI_ASMR2_PB_3 ((uint32_t)0x00000008) /*!< Bit 3 */
mbed_official 545:5112d5ae6723 3775 #define RI_ASMR2_PB_4 ((uint32_t)0x00000010) /*!< Bit 4 */
mbed_official 545:5112d5ae6723 3776 #define RI_ASMR2_PB_5 ((uint32_t)0x00000020) /*!< Bit 5 */
mbed_official 545:5112d5ae6723 3777 #define RI_ASMR2_PB_6 ((uint32_t)0x00000040) /*!< Bit 6 */
mbed_official 545:5112d5ae6723 3778 #define RI_ASMR2_PB_7 ((uint32_t)0x00000080) /*!< Bit 7 */
mbed_official 545:5112d5ae6723 3779 #define RI_ASMR2_PB_8 ((uint32_t)0x00000100) /*!< Bit 8 */
mbed_official 545:5112d5ae6723 3780 #define RI_ASMR2_PB_9 ((uint32_t)0x00000200) /*!< Bit 9 */
mbed_official 545:5112d5ae6723 3781 #define RI_ASMR2_PB_10 ((uint32_t)0x00000400) /*!< Bit 10 */
mbed_official 545:5112d5ae6723 3782 #define RI_ASMR2_PB_11 ((uint32_t)0x00000800) /*!< Bit 11 */
mbed_official 545:5112d5ae6723 3783 #define RI_ASMR2_PB_12 ((uint32_t)0x00001000) /*!< Bit 12 */
mbed_official 545:5112d5ae6723 3784 #define RI_ASMR2_PB_13 ((uint32_t)0x00002000) /*!< Bit 13 */
mbed_official 545:5112d5ae6723 3785 #define RI_ASMR2_PB_14 ((uint32_t)0x00004000) /*!< Bit 14 */
mbed_official 545:5112d5ae6723 3786 #define RI_ASMR2_PB_15 ((uint32_t)0x00008000) /*!< Bit 15 */
mbed_official 545:5112d5ae6723 3787
mbed_official 545:5112d5ae6723 3788 /******************** Bit definition for RI_CMR2 register ********************/
mbed_official 545:5112d5ae6723 3789 #define RI_CMR2_PB ((uint32_t)0x0000FFFF) /*!< PB[15:0] Port B selection */
mbed_official 545:5112d5ae6723 3790 #define RI_CMR2_PB_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 3791 #define RI_CMR2_PB_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 3792 #define RI_CMR2_PB_2 ((uint32_t)0x00000004) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 3793 #define RI_CMR2_PB_3 ((uint32_t)0x00000008) /*!< Bit 3 */
mbed_official 545:5112d5ae6723 3794 #define RI_CMR2_PB_4 ((uint32_t)0x00000010) /*!< Bit 4 */
mbed_official 545:5112d5ae6723 3795 #define RI_CMR2_PB_5 ((uint32_t)0x00000020) /*!< Bit 5 */
mbed_official 545:5112d5ae6723 3796 #define RI_CMR2_PB_6 ((uint32_t)0x00000040) /*!< Bit 6 */
mbed_official 545:5112d5ae6723 3797 #define RI_CMR2_PB_7 ((uint32_t)0x00000080) /*!< Bit 7 */
mbed_official 545:5112d5ae6723 3798 #define RI_CMR2_PB_8 ((uint32_t)0x00000100) /*!< Bit 8 */
mbed_official 545:5112d5ae6723 3799 #define RI_CMR2_PB_9 ((uint32_t)0x00000200) /*!< Bit 9 */
mbed_official 545:5112d5ae6723 3800 #define RI_CMR2_PB_10 ((uint32_t)0x00000400) /*!< Bit 10 */
mbed_official 545:5112d5ae6723 3801 #define RI_CMR2_PB_11 ((uint32_t)0x00000800) /*!< Bit 11 */
mbed_official 545:5112d5ae6723 3802 #define RI_CMR2_PB_12 ((uint32_t)0x00001000) /*!< Bit 12 */
mbed_official 545:5112d5ae6723 3803 #define RI_CMR2_PB_13 ((uint32_t)0x00002000) /*!< Bit 13 */
mbed_official 545:5112d5ae6723 3804 #define RI_CMR2_PB_14 ((uint32_t)0x00004000) /*!< Bit 14 */
mbed_official 545:5112d5ae6723 3805 #define RI_CMR2_PB_15 ((uint32_t)0x00008000) /*!< Bit 15 */
mbed_official 545:5112d5ae6723 3806
mbed_official 545:5112d5ae6723 3807 /******************** Bit definition for RI_CICR2 register ********************/
mbed_official 545:5112d5ae6723 3808 #define RI_CICR2_PB ((uint32_t)0x0000FFFF) /*!< PB[15:0] Port B selection */
mbed_official 545:5112d5ae6723 3809 #define RI_CICR2_PB_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 3810 #define RI_CICR2_PB_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 3811 #define RI_CICR2_PB_2 ((uint32_t)0x00000004) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 3812 #define RI_CICR2_PB_3 ((uint32_t)0x00000008) /*!< Bit 3 */
mbed_official 545:5112d5ae6723 3813 #define RI_CICR2_PB_4 ((uint32_t)0x00000010) /*!< Bit 4 */
mbed_official 545:5112d5ae6723 3814 #define RI_CICR2_PB_5 ((uint32_t)0x00000020) /*!< Bit 5 */
mbed_official 545:5112d5ae6723 3815 #define RI_CICR2_PB_6 ((uint32_t)0x00000040) /*!< Bit 6 */
mbed_official 545:5112d5ae6723 3816 #define RI_CICR2_PB_7 ((uint32_t)0x00000080) /*!< Bit 7 */
mbed_official 545:5112d5ae6723 3817 #define RI_CICR2_PB_8 ((uint32_t)0x00000100) /*!< Bit 8 */
mbed_official 545:5112d5ae6723 3818 #define RI_CICR2_PB_9 ((uint32_t)0x00000200) /*!< Bit 9 */
mbed_official 545:5112d5ae6723 3819 #define RI_CICR2_PB_10 ((uint32_t)0x00000400) /*!< Bit 10 */
mbed_official 545:5112d5ae6723 3820 #define RI_CICR2_PB_11 ((uint32_t)0x00000800) /*!< Bit 11 */
mbed_official 545:5112d5ae6723 3821 #define RI_CICR2_PB_12 ((uint32_t)0x00001000) /*!< Bit 12 */
mbed_official 545:5112d5ae6723 3822 #define RI_CICR2_PB_13 ((uint32_t)0x00002000) /*!< Bit 13 */
mbed_official 545:5112d5ae6723 3823 #define RI_CICR2_PB_14 ((uint32_t)0x00004000) /*!< Bit 14 */
mbed_official 545:5112d5ae6723 3824 #define RI_CICR2_PB_15 ((uint32_t)0x00008000) /*!< Bit 15 */
mbed_official 545:5112d5ae6723 3825
mbed_official 545:5112d5ae6723 3826 /******************** Bit definition for RI_ASMR3 register ********************/
mbed_official 545:5112d5ae6723 3827 #define RI_ASMR3_PC ((uint32_t)0x0000FFFF) /*!< PC[15:0] Port C selection */
mbed_official 545:5112d5ae6723 3828 #define RI_ASMR3_PC_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 3829 #define RI_ASMR3_PC_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 3830 #define RI_ASMR3_PC_2 ((uint32_t)0x00000004) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 3831 #define RI_ASMR3_PC_3 ((uint32_t)0x00000008) /*!< Bit 3 */
mbed_official 545:5112d5ae6723 3832 #define RI_ASMR3_PC_4 ((uint32_t)0x00000010) /*!< Bit 4 */
mbed_official 545:5112d5ae6723 3833 #define RI_ASMR3_PC_5 ((uint32_t)0x00000020) /*!< Bit 5 */
mbed_official 545:5112d5ae6723 3834 #define RI_ASMR3_PC_6 ((uint32_t)0x00000040) /*!< Bit 6 */
mbed_official 545:5112d5ae6723 3835 #define RI_ASMR3_PC_7 ((uint32_t)0x00000080) /*!< Bit 7 */
mbed_official 545:5112d5ae6723 3836 #define RI_ASMR3_PC_8 ((uint32_t)0x00000100) /*!< Bit 8 */
mbed_official 545:5112d5ae6723 3837 #define RI_ASMR3_PC_9 ((uint32_t)0x00000200) /*!< Bit 9 */
mbed_official 545:5112d5ae6723 3838 #define RI_ASMR3_PC_10 ((uint32_t)0x00000400) /*!< Bit 10 */
mbed_official 545:5112d5ae6723 3839 #define RI_ASMR3_PC_11 ((uint32_t)0x00000800) /*!< Bit 11 */
mbed_official 545:5112d5ae6723 3840 #define RI_ASMR3_PC_12 ((uint32_t)0x00001000) /*!< Bit 12 */
mbed_official 545:5112d5ae6723 3841 #define RI_ASMR3_PC_13 ((uint32_t)0x00002000) /*!< Bit 13 */
mbed_official 545:5112d5ae6723 3842 #define RI_ASMR3_PC_14 ((uint32_t)0x00004000) /*!< Bit 14 */
mbed_official 545:5112d5ae6723 3843 #define RI_ASMR3_PC_15 ((uint32_t)0x00008000) /*!< Bit 15 */
mbed_official 545:5112d5ae6723 3844
mbed_official 545:5112d5ae6723 3845 /******************** Bit definition for RI_CMR3 register ********************/
mbed_official 545:5112d5ae6723 3846 #define RI_CMR3_PC ((uint32_t)0x0000FFFF) /*!< PC[15:0] Port C selection */
mbed_official 545:5112d5ae6723 3847 #define RI_CMR3_PC_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 3848 #define RI_CMR3_PC_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 3849 #define RI_CMR3_PC_2 ((uint32_t)0x00000004) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 3850 #define RI_CMR3_PC_3 ((uint32_t)0x00000008) /*!< Bit 3 */
mbed_official 545:5112d5ae6723 3851 #define RI_CMR3_PC_4 ((uint32_t)0x00000010) /*!< Bit 4 */
mbed_official 545:5112d5ae6723 3852 #define RI_CMR3_PC_5 ((uint32_t)0x00000020) /*!< Bit 5 */
mbed_official 545:5112d5ae6723 3853 #define RI_CMR3_PC_6 ((uint32_t)0x00000040) /*!< Bit 6 */
mbed_official 545:5112d5ae6723 3854 #define RI_CMR3_PC_7 ((uint32_t)0x00000080) /*!< Bit 7 */
mbed_official 545:5112d5ae6723 3855 #define RI_CMR3_PC_8 ((uint32_t)0x00000100) /*!< Bit 8 */
mbed_official 545:5112d5ae6723 3856 #define RI_CMR3_PC_9 ((uint32_t)0x00000200) /*!< Bit 9 */
mbed_official 545:5112d5ae6723 3857 #define RI_CMR3_PC_10 ((uint32_t)0x00000400) /*!< Bit 10 */
mbed_official 545:5112d5ae6723 3858 #define RI_CMR3_PC_11 ((uint32_t)0x00000800) /*!< Bit 11 */
mbed_official 545:5112d5ae6723 3859 #define RI_CMR3_PC_12 ((uint32_t)0x00001000) /*!< Bit 12 */
mbed_official 545:5112d5ae6723 3860 #define RI_CMR3_PC_13 ((uint32_t)0x00002000) /*!< Bit 13 */
mbed_official 545:5112d5ae6723 3861 #define RI_CMR3_PC_14 ((uint32_t)0x00004000) /*!< Bit 14 */
mbed_official 545:5112d5ae6723 3862 #define RI_CMR3_PC_15 ((uint32_t)0x00008000) /*!< Bit 15 */
mbed_official 545:5112d5ae6723 3863
mbed_official 545:5112d5ae6723 3864 /******************** Bit definition for RI_CICR3 register ********************/
mbed_official 545:5112d5ae6723 3865 #define RI_CICR3_PC ((uint32_t)0x0000FFFF) /*!< PC[15:0] Port C selection */
mbed_official 545:5112d5ae6723 3866 #define RI_CICR3_PC_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 3867 #define RI_CICR3_PC_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 3868 #define RI_CICR3_PC_2 ((uint32_t)0x00000004) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 3869 #define RI_CICR3_PC_3 ((uint32_t)0x00000008) /*!< Bit 3 */
mbed_official 545:5112d5ae6723 3870 #define RI_CICR3_PC_4 ((uint32_t)0x00000010) /*!< Bit 4 */
mbed_official 545:5112d5ae6723 3871 #define RI_CICR3_PC_5 ((uint32_t)0x00000020) /*!< Bit 5 */
mbed_official 545:5112d5ae6723 3872 #define RI_CICR3_PC_6 ((uint32_t)0x00000040) /*!< Bit 6 */
mbed_official 545:5112d5ae6723 3873 #define RI_CICR3_PC_7 ((uint32_t)0x00000080) /*!< Bit 7 */
mbed_official 545:5112d5ae6723 3874 #define RI_CICR3_PC_8 ((uint32_t)0x00000100) /*!< Bit 8 */
mbed_official 545:5112d5ae6723 3875 #define RI_CICR3_PC_9 ((uint32_t)0x00000200) /*!< Bit 9 */
mbed_official 545:5112d5ae6723 3876 #define RI_CICR3_PC_10 ((uint32_t)0x00000400) /*!< Bit 10 */
mbed_official 545:5112d5ae6723 3877 #define RI_CICR3_PC_11 ((uint32_t)0x00000800) /*!< Bit 11 */
mbed_official 545:5112d5ae6723 3878 #define RI_CICR3_PC_12 ((uint32_t)0x00001000) /*!< Bit 12 */
mbed_official 545:5112d5ae6723 3879 #define RI_CICR3_PC_13 ((uint32_t)0x00002000) /*!< Bit 13 */
mbed_official 545:5112d5ae6723 3880 #define RI_CICR3_PC_14 ((uint32_t)0x00004000) /*!< Bit 14 */
mbed_official 545:5112d5ae6723 3881 #define RI_CICR3_PC_15 ((uint32_t)0x00008000) /*!< Bit 15 */
mbed_official 545:5112d5ae6723 3882
mbed_official 545:5112d5ae6723 3883 /******************************************************************************/
mbed_official 545:5112d5ae6723 3884 /* */
mbed_official 545:5112d5ae6723 3885 /* Timers (TIM) */
mbed_official 545:5112d5ae6723 3886 /* */
mbed_official 545:5112d5ae6723 3887 /******************************************************************************/
mbed_official 545:5112d5ae6723 3888
mbed_official 545:5112d5ae6723 3889 /******************* Bit definition for TIM_CR1 register ********************/
mbed_official 545:5112d5ae6723 3890 #define TIM_CR1_CEN ((uint32_t)0x00000001) /*!<Counter enable */
mbed_official 545:5112d5ae6723 3891 #define TIM_CR1_UDIS ((uint32_t)0x00000002) /*!<Update disable */
mbed_official 545:5112d5ae6723 3892 #define TIM_CR1_URS ((uint32_t)0x00000004) /*!<Update request source */
mbed_official 545:5112d5ae6723 3893 #define TIM_CR1_OPM ((uint32_t)0x00000008) /*!<One pulse mode */
mbed_official 545:5112d5ae6723 3894 #define TIM_CR1_DIR ((uint32_t)0x00000010) /*!<Direction */
mbed_official 545:5112d5ae6723 3895
mbed_official 545:5112d5ae6723 3896 #define TIM_CR1_CMS ((uint32_t)0x00000060) /*!<CMS[1:0] bits (Center-aligned mode selection) */
mbed_official 545:5112d5ae6723 3897 #define TIM_CR1_CMS_0 ((uint32_t)0x00000020) /*!<Bit 0 */
mbed_official 545:5112d5ae6723 3898 #define TIM_CR1_CMS_1 ((uint32_t)0x00000040) /*!<Bit 1 */
mbed_official 545:5112d5ae6723 3899
mbed_official 545:5112d5ae6723 3900 #define TIM_CR1_ARPE ((uint32_t)0x00000080) /*!<Auto-reload preload enable */
mbed_official 545:5112d5ae6723 3901
mbed_official 545:5112d5ae6723 3902 #define TIM_CR1_CKD ((uint32_t)0x00000300) /*!<CKD[1:0] bits (clock division) */
mbed_official 545:5112d5ae6723 3903 #define TIM_CR1_CKD_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 545:5112d5ae6723 3904 #define TIM_CR1_CKD_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 545:5112d5ae6723 3905
mbed_official 545:5112d5ae6723 3906 /******************* Bit definition for TIM_CR2 register ********************/
mbed_official 545:5112d5ae6723 3907 #define TIM_CR2_CCDS ((uint32_t)0x00000008) /*!<Capture/Compare DMA Selection */
mbed_official 545:5112d5ae6723 3908
mbed_official 545:5112d5ae6723 3909 #define TIM_CR2_MMS ((uint32_t)0x00000070) /*!<MMS[2:0] bits (Master Mode Selection) */
mbed_official 545:5112d5ae6723 3910 #define TIM_CR2_MMS_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 545:5112d5ae6723 3911 #define TIM_CR2_MMS_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 545:5112d5ae6723 3912 #define TIM_CR2_MMS_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 545:5112d5ae6723 3913
mbed_official 545:5112d5ae6723 3914 #define TIM_CR2_TI1S ((uint32_t)0x00000080) /*!<TI1 Selection */
mbed_official 545:5112d5ae6723 3915
mbed_official 545:5112d5ae6723 3916 /******************* Bit definition for TIM_SMCR register *******************/
mbed_official 545:5112d5ae6723 3917 #define TIM_SMCR_SMS ((uint32_t)0x00000007) /*!<SMS[2:0] bits (Slave mode selection) */
mbed_official 545:5112d5ae6723 3918 #define TIM_SMCR_SMS_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 545:5112d5ae6723 3919 #define TIM_SMCR_SMS_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 545:5112d5ae6723 3920 #define TIM_SMCR_SMS_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 545:5112d5ae6723 3921
mbed_official 545:5112d5ae6723 3922 #define TIM_SMCR_OCCS ((uint32_t)0x00000008) /*!< OCREF clear selection */
mbed_official 545:5112d5ae6723 3923
mbed_official 545:5112d5ae6723 3924 #define TIM_SMCR_TS ((uint32_t)0x00000070) /*!<TS[2:0] bits (Trigger selection) */
mbed_official 545:5112d5ae6723 3925 #define TIM_SMCR_TS_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 545:5112d5ae6723 3926 #define TIM_SMCR_TS_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 545:5112d5ae6723 3927 #define TIM_SMCR_TS_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 545:5112d5ae6723 3928
mbed_official 545:5112d5ae6723 3929 #define TIM_SMCR_MSM ((uint32_t)0x00000080) /*!<Master/slave mode */
mbed_official 545:5112d5ae6723 3930
mbed_official 545:5112d5ae6723 3931 #define TIM_SMCR_ETF ((uint32_t)0x00000F00) /*!<ETF[3:0] bits (External trigger filter) */
mbed_official 545:5112d5ae6723 3932 #define TIM_SMCR_ETF_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 545:5112d5ae6723 3933 #define TIM_SMCR_ETF_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 545:5112d5ae6723 3934 #define TIM_SMCR_ETF_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 545:5112d5ae6723 3935 #define TIM_SMCR_ETF_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 545:5112d5ae6723 3936
mbed_official 545:5112d5ae6723 3937 #define TIM_SMCR_ETPS ((uint32_t)0x00003000) /*!<ETPS[1:0] bits (External trigger prescaler) */
mbed_official 545:5112d5ae6723 3938 #define TIM_SMCR_ETPS_0 ((uint32_t)0x00001000) /*!<Bit 0 */
mbed_official 545:5112d5ae6723 3939 #define TIM_SMCR_ETPS_1 ((uint32_t)0x00002000) /*!<Bit 1 */
mbed_official 545:5112d5ae6723 3940
mbed_official 545:5112d5ae6723 3941 #define TIM_SMCR_ECE ((uint32_t)0x00004000) /*!<External clock enable */
mbed_official 545:5112d5ae6723 3942 #define TIM_SMCR_ETP ((uint32_t)0x00008000) /*!<External trigger polarity */
mbed_official 545:5112d5ae6723 3943
mbed_official 545:5112d5ae6723 3944 /******************* Bit definition for TIM_DIER register *******************/
mbed_official 545:5112d5ae6723 3945 #define TIM_DIER_UIE ((uint32_t)0x00000001) /*!<Update interrupt enable */
mbed_official 545:5112d5ae6723 3946 #define TIM_DIER_CC1IE ((uint32_t)0x00000002) /*!<Capture/Compare 1 interrupt enable */
mbed_official 545:5112d5ae6723 3947 #define TIM_DIER_CC2IE ((uint32_t)0x00000004) /*!<Capture/Compare 2 interrupt enable */
mbed_official 545:5112d5ae6723 3948 #define TIM_DIER_CC3IE ((uint32_t)0x00000008) /*!<Capture/Compare 3 interrupt enable */
mbed_official 545:5112d5ae6723 3949 #define TIM_DIER_CC4IE ((uint32_t)0x00000010) /*!<Capture/Compare 4 interrupt enable */
mbed_official 545:5112d5ae6723 3950 #define TIM_DIER_TIE ((uint32_t)0x00000040) /*!<Trigger interrupt enable */
mbed_official 545:5112d5ae6723 3951 #define TIM_DIER_UDE ((uint32_t)0x00000100) /*!<Update DMA request enable */
mbed_official 545:5112d5ae6723 3952 #define TIM_DIER_CC1DE ((uint32_t)0x00000200) /*!<Capture/Compare 1 DMA request enable */
mbed_official 545:5112d5ae6723 3953 #define TIM_DIER_CC2DE ((uint32_t)0x00000400) /*!<Capture/Compare 2 DMA request enable */
mbed_official 545:5112d5ae6723 3954 #define TIM_DIER_CC3DE ((uint32_t)0x00000800) /*!<Capture/Compare 3 DMA request enable */
mbed_official 545:5112d5ae6723 3955 #define TIM_DIER_CC4DE ((uint32_t)0x00001000) /*!<Capture/Compare 4 DMA request enable */
mbed_official 545:5112d5ae6723 3956 #define TIM_DIER_COMDE ((uint16_t)0x2000) /*!<COM DMA request enable */
mbed_official 545:5112d5ae6723 3957 #define TIM_DIER_TDE ((uint32_t)0x00004000) /*!<Trigger DMA request enable */
mbed_official 545:5112d5ae6723 3958
mbed_official 545:5112d5ae6723 3959 /******************** Bit definition for TIM_SR register ********************/
mbed_official 545:5112d5ae6723 3960 #define TIM_SR_UIF ((uint32_t)0x00000001) /*!<Update interrupt Flag */
mbed_official 545:5112d5ae6723 3961 #define TIM_SR_CC1IF ((uint32_t)0x00000002) /*!<Capture/Compare 1 interrupt Flag */
mbed_official 545:5112d5ae6723 3962 #define TIM_SR_CC2IF ((uint32_t)0x00000004) /*!<Capture/Compare 2 interrupt Flag */
mbed_official 545:5112d5ae6723 3963 #define TIM_SR_CC3IF ((uint32_t)0x00000008) /*!<Capture/Compare 3 interrupt Flag */
mbed_official 545:5112d5ae6723 3964 #define TIM_SR_CC4IF ((uint32_t)0x00000010) /*!<Capture/Compare 4 interrupt Flag */
mbed_official 545:5112d5ae6723 3965 #define TIM_SR_TIF ((uint32_t)0x00000040) /*!<Trigger interrupt Flag */
mbed_official 545:5112d5ae6723 3966 #define TIM_SR_CC1OF ((uint32_t)0x00000200) /*!<Capture/Compare 1 Overcapture Flag */
mbed_official 545:5112d5ae6723 3967 #define TIM_SR_CC2OF ((uint32_t)0x00000400) /*!<Capture/Compare 2 Overcapture Flag */
mbed_official 545:5112d5ae6723 3968 #define TIM_SR_CC3OF ((uint32_t)0x00000800) /*!<Capture/Compare 3 Overcapture Flag */
mbed_official 545:5112d5ae6723 3969 #define TIM_SR_CC4OF ((uint32_t)0x00001000) /*!<Capture/Compare 4 Overcapture Flag */
mbed_official 545:5112d5ae6723 3970
mbed_official 545:5112d5ae6723 3971 /******************* Bit definition for TIM_EGR register ********************/
mbed_official 545:5112d5ae6723 3972 #define TIM_EGR_UG ((uint32_t)0x00000001) /*!<Update Generation */
mbed_official 545:5112d5ae6723 3973 #define TIM_EGR_CC1G ((uint32_t)0x00000002) /*!<Capture/Compare 1 Generation */
mbed_official 545:5112d5ae6723 3974 #define TIM_EGR_CC2G ((uint32_t)0x00000004) /*!<Capture/Compare 2 Generation */
mbed_official 545:5112d5ae6723 3975 #define TIM_EGR_CC3G ((uint32_t)0x00000008) /*!<Capture/Compare 3 Generation */
mbed_official 545:5112d5ae6723 3976 #define TIM_EGR_CC4G ((uint32_t)0x00000010) /*!<Capture/Compare 4 Generation */
mbed_official 545:5112d5ae6723 3977 #define TIM_EGR_TG ((uint32_t)0x00000040) /*!<Trigger Generation */
mbed_official 545:5112d5ae6723 3978
mbed_official 545:5112d5ae6723 3979 /****************** Bit definition for TIM_CCMR1 register *******************/
mbed_official 545:5112d5ae6723 3980 #define TIM_CCMR1_CC1S ((uint32_t)0x00000003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
mbed_official 545:5112d5ae6723 3981 #define TIM_CCMR1_CC1S_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 545:5112d5ae6723 3982 #define TIM_CCMR1_CC1S_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 545:5112d5ae6723 3983
mbed_official 545:5112d5ae6723 3984 #define TIM_CCMR1_OC1FE ((uint32_t)0x00000004) /*!<Output Compare 1 Fast enable */
mbed_official 545:5112d5ae6723 3985 #define TIM_CCMR1_OC1PE ((uint32_t)0x00000008) /*!<Output Compare 1 Preload enable */
mbed_official 545:5112d5ae6723 3986
mbed_official 545:5112d5ae6723 3987 #define TIM_CCMR1_OC1M ((uint32_t)0x00000070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
mbed_official 545:5112d5ae6723 3988 #define TIM_CCMR1_OC1M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 545:5112d5ae6723 3989 #define TIM_CCMR1_OC1M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 545:5112d5ae6723 3990 #define TIM_CCMR1_OC1M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 545:5112d5ae6723 3991
mbed_official 545:5112d5ae6723 3992 #define TIM_CCMR1_OC1CE ((uint32_t)0x00000080) /*!<Output Compare 1Clear Enable */
mbed_official 545:5112d5ae6723 3993
mbed_official 545:5112d5ae6723 3994 #define TIM_CCMR1_CC2S ((uint32_t)0x00000300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
mbed_official 545:5112d5ae6723 3995 #define TIM_CCMR1_CC2S_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 545:5112d5ae6723 3996 #define TIM_CCMR1_CC2S_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 545:5112d5ae6723 3997
mbed_official 545:5112d5ae6723 3998 #define TIM_CCMR1_OC2FE ((uint32_t)0x00000400) /*!<Output Compare 2 Fast enable */
mbed_official 545:5112d5ae6723 3999 #define TIM_CCMR1_OC2PE ((uint32_t)0x00000800) /*!<Output Compare 2 Preload enable */
mbed_official 545:5112d5ae6723 4000
mbed_official 545:5112d5ae6723 4001 #define TIM_CCMR1_OC2M ((uint32_t)0x00007000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
mbed_official 545:5112d5ae6723 4002 #define TIM_CCMR1_OC2M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
mbed_official 545:5112d5ae6723 4003 #define TIM_CCMR1_OC2M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
mbed_official 545:5112d5ae6723 4004 #define TIM_CCMR1_OC2M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
mbed_official 545:5112d5ae6723 4005
mbed_official 545:5112d5ae6723 4006 #define TIM_CCMR1_OC2CE ((uint32_t)0x00008000) /*!<Output Compare 2 Clear Enable */
mbed_official 545:5112d5ae6723 4007
mbed_official 545:5112d5ae6723 4008 /*----------------------------------------------------------------------------*/
mbed_official 545:5112d5ae6723 4009
mbed_official 545:5112d5ae6723 4010 #define TIM_CCMR1_IC1PSC ((uint32_t)0x0000000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
mbed_official 545:5112d5ae6723 4011 #define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x00000004) /*!<Bit 0 */
mbed_official 545:5112d5ae6723 4012 #define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x00000008) /*!<Bit 1 */
mbed_official 545:5112d5ae6723 4013
mbed_official 545:5112d5ae6723 4014 #define TIM_CCMR1_IC1F ((uint32_t)0x000000F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
mbed_official 545:5112d5ae6723 4015 #define TIM_CCMR1_IC1F_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 545:5112d5ae6723 4016 #define TIM_CCMR1_IC1F_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 545:5112d5ae6723 4017 #define TIM_CCMR1_IC1F_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 545:5112d5ae6723 4018 #define TIM_CCMR1_IC1F_3 ((uint32_t)0x00000080) /*!<Bit 3 */
mbed_official 545:5112d5ae6723 4019
mbed_official 545:5112d5ae6723 4020 #define TIM_CCMR1_IC2PSC ((uint32_t)0x00000C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
mbed_official 545:5112d5ae6723 4021 #define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x00000400) /*!<Bit 0 */
mbed_official 545:5112d5ae6723 4022 #define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x00000800) /*!<Bit 1 */
mbed_official 545:5112d5ae6723 4023
mbed_official 545:5112d5ae6723 4024 #define TIM_CCMR1_IC2F ((uint32_t)0x0000F000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
mbed_official 545:5112d5ae6723 4025 #define TIM_CCMR1_IC2F_0 ((uint32_t)0x00001000) /*!<Bit 0 */
mbed_official 545:5112d5ae6723 4026 #define TIM_CCMR1_IC2F_1 ((uint32_t)0x00002000) /*!<Bit 1 */
mbed_official 545:5112d5ae6723 4027 #define TIM_CCMR1_IC2F_2 ((uint32_t)0x00004000) /*!<Bit 2 */
mbed_official 545:5112d5ae6723 4028 #define TIM_CCMR1_IC2F_3 ((uint32_t)0x00008000) /*!<Bit 3 */
mbed_official 545:5112d5ae6723 4029
mbed_official 545:5112d5ae6723 4030 /****************** Bit definition for TIM_CCMR2 register *******************/
mbed_official 545:5112d5ae6723 4031 #define TIM_CCMR2_CC3S ((uint32_t)0x00000003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
mbed_official 545:5112d5ae6723 4032 #define TIM_CCMR2_CC3S_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 545:5112d5ae6723 4033 #define TIM_CCMR2_CC3S_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 545:5112d5ae6723 4034
mbed_official 545:5112d5ae6723 4035 #define TIM_CCMR2_OC3FE ((uint32_t)0x00000004) /*!<Output Compare 3 Fast enable */
mbed_official 545:5112d5ae6723 4036 #define TIM_CCMR2_OC3PE ((uint32_t)0x00000008) /*!<Output Compare 3 Preload enable */
mbed_official 545:5112d5ae6723 4037
mbed_official 545:5112d5ae6723 4038 #define TIM_CCMR2_OC3M ((uint32_t)0x00000070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
mbed_official 545:5112d5ae6723 4039 #define TIM_CCMR2_OC3M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 545:5112d5ae6723 4040 #define TIM_CCMR2_OC3M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 545:5112d5ae6723 4041 #define TIM_CCMR2_OC3M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 545:5112d5ae6723 4042
mbed_official 545:5112d5ae6723 4043 #define TIM_CCMR2_OC3CE ((uint32_t)0x00000080) /*!<Output Compare 3 Clear Enable */
mbed_official 545:5112d5ae6723 4044
mbed_official 545:5112d5ae6723 4045 #define TIM_CCMR2_CC4S ((uint32_t)0x00000300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
mbed_official 545:5112d5ae6723 4046 #define TIM_CCMR2_CC4S_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 545:5112d5ae6723 4047 #define TIM_CCMR2_CC4S_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 545:5112d5ae6723 4048
mbed_official 545:5112d5ae6723 4049 #define TIM_CCMR2_OC4FE ((uint32_t)0x00000400) /*!<Output Compare 4 Fast enable */
mbed_official 545:5112d5ae6723 4050 #define TIM_CCMR2_OC4PE ((uint32_t)0x00000800) /*!<Output Compare 4 Preload enable */
mbed_official 545:5112d5ae6723 4051
mbed_official 545:5112d5ae6723 4052 #define TIM_CCMR2_OC4M ((uint32_t)0x00007000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
mbed_official 545:5112d5ae6723 4053 #define TIM_CCMR2_OC4M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
mbed_official 545:5112d5ae6723 4054 #define TIM_CCMR2_OC4M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
mbed_official 545:5112d5ae6723 4055 #define TIM_CCMR2_OC4M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
mbed_official 545:5112d5ae6723 4056
mbed_official 545:5112d5ae6723 4057 #define TIM_CCMR2_OC4CE ((uint32_t)0x00008000) /*!<Output Compare 4 Clear Enable */
mbed_official 545:5112d5ae6723 4058
mbed_official 545:5112d5ae6723 4059 /*----------------------------------------------------------------------------*/
mbed_official 545:5112d5ae6723 4060
mbed_official 545:5112d5ae6723 4061 #define TIM_CCMR2_IC3PSC ((uint32_t)0x0000000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
mbed_official 545:5112d5ae6723 4062 #define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x00000004) /*!<Bit 0 */
mbed_official 545:5112d5ae6723 4063 #define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x00000008) /*!<Bit 1 */
mbed_official 545:5112d5ae6723 4064
mbed_official 545:5112d5ae6723 4065 #define TIM_CCMR2_IC3F ((uint32_t)0x000000F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
mbed_official 545:5112d5ae6723 4066 #define TIM_CCMR2_IC3F_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 545:5112d5ae6723 4067 #define TIM_CCMR2_IC3F_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 545:5112d5ae6723 4068 #define TIM_CCMR2_IC3F_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 545:5112d5ae6723 4069 #define TIM_CCMR2_IC3F_3 ((uint32_t)0x00000080) /*!<Bit 3 */
mbed_official 545:5112d5ae6723 4070
mbed_official 545:5112d5ae6723 4071 #define TIM_CCMR2_IC4PSC ((uint32_t)0x00000C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
mbed_official 545:5112d5ae6723 4072 #define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x00000400) /*!<Bit 0 */
mbed_official 545:5112d5ae6723 4073 #define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x00000800) /*!<Bit 1 */
mbed_official 545:5112d5ae6723 4074
mbed_official 545:5112d5ae6723 4075 #define TIM_CCMR2_IC4F ((uint32_t)0x0000F000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
mbed_official 545:5112d5ae6723 4076 #define TIM_CCMR2_IC4F_0 ((uint32_t)0x00001000) /*!<Bit 0 */
mbed_official 545:5112d5ae6723 4077 #define TIM_CCMR2_IC4F_1 ((uint32_t)0x00002000) /*!<Bit 1 */
mbed_official 545:5112d5ae6723 4078 #define TIM_CCMR2_IC4F_2 ((uint32_t)0x00004000) /*!<Bit 2 */
mbed_official 545:5112d5ae6723 4079 #define TIM_CCMR2_IC4F_3 ((uint32_t)0x00008000) /*!<Bit 3 */
mbed_official 545:5112d5ae6723 4080
mbed_official 545:5112d5ae6723 4081 /******************* Bit definition for TIM_CCER register *******************/
mbed_official 545:5112d5ae6723 4082 #define TIM_CCER_CC1E ((uint32_t)0x00000001) /*!<Capture/Compare 1 output enable */
mbed_official 545:5112d5ae6723 4083 #define TIM_CCER_CC1P ((uint32_t)0x00000002) /*!<Capture/Compare 1 output Polarity */
mbed_official 545:5112d5ae6723 4084 #define TIM_CCER_CC1NP ((uint32_t)0x00000008) /*!<Capture/Compare 1 Complementary output Polarity */
mbed_official 545:5112d5ae6723 4085 #define TIM_CCER_CC2E ((uint32_t)0x00000010) /*!<Capture/Compare 2 output enable */
mbed_official 545:5112d5ae6723 4086 #define TIM_CCER_CC2P ((uint32_t)0x00000020) /*!<Capture/Compare 2 output Polarity */
mbed_official 545:5112d5ae6723 4087 #define TIM_CCER_CC2NP ((uint32_t)0x00000080) /*!<Capture/Compare 2 Complementary output Polarity */
mbed_official 545:5112d5ae6723 4088 #define TIM_CCER_CC3E ((uint32_t)0x00000100) /*!<Capture/Compare 3 output enable */
mbed_official 545:5112d5ae6723 4089 #define TIM_CCER_CC3P ((uint32_t)0x00000200) /*!<Capture/Compare 3 output Polarity */
mbed_official 545:5112d5ae6723 4090 #define TIM_CCER_CC3NP ((uint32_t)0x00000800) /*!<Capture/Compare 3 Complementary output Polarity */
mbed_official 545:5112d5ae6723 4091 #define TIM_CCER_CC4E ((uint32_t)0x00001000) /*!<Capture/Compare 4 output enable */
mbed_official 545:5112d5ae6723 4092 #define TIM_CCER_CC4P ((uint32_t)0x00002000) /*!<Capture/Compare 4 output Polarity */
mbed_official 545:5112d5ae6723 4093 #define TIM_CCER_CC4NP ((uint32_t)0x00008000) /*!<Capture/Compare 4 Complementary output Polarity */
mbed_official 545:5112d5ae6723 4094
mbed_official 545:5112d5ae6723 4095 /******************* Bit definition for TIM_CNT register ********************/
mbed_official 545:5112d5ae6723 4096 #define TIM_CNT_CNT ((uint32_t)0x0000FFFF) /*!<Counter Value */
mbed_official 545:5112d5ae6723 4097
mbed_official 545:5112d5ae6723 4098 /******************* Bit definition for TIM_PSC register ********************/
mbed_official 545:5112d5ae6723 4099 #define TIM_PSC_PSC ((uint32_t)0x0000FFFF) /*!<Prescaler Value */
mbed_official 545:5112d5ae6723 4100
mbed_official 545:5112d5ae6723 4101 /******************* Bit definition for TIM_ARR register ********************/
mbed_official 545:5112d5ae6723 4102 #define TIM_ARR_ARR ((uint32_t)0x0000FFFF) /*!<actual auto-reload Value */
mbed_official 545:5112d5ae6723 4103
mbed_official 545:5112d5ae6723 4104 /******************* Bit definition for TIM_CCR1 register *******************/
mbed_official 545:5112d5ae6723 4105 #define TIM_CCR1_CCR1 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 1 Value */
mbed_official 545:5112d5ae6723 4106
mbed_official 545:5112d5ae6723 4107 /******************* Bit definition for TIM_CCR2 register *******************/
mbed_official 545:5112d5ae6723 4108 #define TIM_CCR2_CCR2 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 2 Value */
mbed_official 545:5112d5ae6723 4109
mbed_official 545:5112d5ae6723 4110 /******************* Bit definition for TIM_CCR3 register *******************/
mbed_official 545:5112d5ae6723 4111 #define TIM_CCR3_CCR3 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 3 Value */
mbed_official 545:5112d5ae6723 4112
mbed_official 545:5112d5ae6723 4113 /******************* Bit definition for TIM_CCR4 register *******************/
mbed_official 545:5112d5ae6723 4114 #define TIM_CCR4_CCR4 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 4 Value */
mbed_official 545:5112d5ae6723 4115
mbed_official 545:5112d5ae6723 4116 /******************* Bit definition for TIM_DCR register ********************/
mbed_official 545:5112d5ae6723 4117 #define TIM_DCR_DBA ((uint32_t)0x0000001F) /*!<DBA[4:0] bits (DMA Base Address) */
mbed_official 545:5112d5ae6723 4118 #define TIM_DCR_DBA_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 545:5112d5ae6723 4119 #define TIM_DCR_DBA_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 545:5112d5ae6723 4120 #define TIM_DCR_DBA_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 545:5112d5ae6723 4121 #define TIM_DCR_DBA_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 545:5112d5ae6723 4122 #define TIM_DCR_DBA_4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 545:5112d5ae6723 4123
mbed_official 545:5112d5ae6723 4124 #define TIM_DCR_DBL ((uint32_t)0x00001F00) /*!<DBL[4:0] bits (DMA Burst Length) */
mbed_official 545:5112d5ae6723 4125 #define TIM_DCR_DBL_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 545:5112d5ae6723 4126 #define TIM_DCR_DBL_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 545:5112d5ae6723 4127 #define TIM_DCR_DBL_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 545:5112d5ae6723 4128 #define TIM_DCR_DBL_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 545:5112d5ae6723 4129 #define TIM_DCR_DBL_4 ((uint32_t)0x00001000) /*!<Bit 4 */
mbed_official 545:5112d5ae6723 4130
mbed_official 545:5112d5ae6723 4131 /******************* Bit definition for TIM_DMAR register *******************/
mbed_official 545:5112d5ae6723 4132 #define TIM_DMAR_DMAB ((uint32_t)0x0000FFFF) /*!<DMA register for burst accesses */
mbed_official 545:5112d5ae6723 4133
mbed_official 545:5112d5ae6723 4134 /******************* Bit definition for TIM_OR register *********************/
mbed_official 545:5112d5ae6723 4135 #define TIM_OR_TI1RMP ((uint32_t)0x00000003) /*!<TI1_RMP[1:0] bits (TIM Input 1 remap) */
mbed_official 545:5112d5ae6723 4136 #define TIM_OR_TI1RMP_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 545:5112d5ae6723 4137 #define TIM_OR_TI1RMP_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 545:5112d5ae6723 4138
mbed_official 545:5112d5ae6723 4139 #define TIM_OR_ETR_RMP ((uint32_t)0x00000004) /*!<ETR_RMP bit (TIM10/11 ETR remap)*/
mbed_official 545:5112d5ae6723 4140 #define TIM_OR_TI1_RMP_RI ((uint32_t)0x00000008) /*!<TI1_RMP_RI bit (TIM10/11 Input 1 remap for Routing interface) */
mbed_official 545:5112d5ae6723 4141
mbed_official 545:5112d5ae6723 4142 /*----------------------------------------------------------------------------*/
mbed_official 545:5112d5ae6723 4143 #define TIM9_OR_ITR1_RMP ((uint32_t)0x00000004) /*!<ITR1_RMP bit (TIM9 Internal trigger 1 remap) */
mbed_official 545:5112d5ae6723 4144
mbed_official 545:5112d5ae6723 4145 /*----------------------------------------------------------------------------*/
mbed_official 545:5112d5ae6723 4146 #define TIM2_OR_ITR1_RMP ((uint32_t)0x00000001) /*!<ITR1_RMP bit (TIM2 Internal trigger 1 remap) */
mbed_official 545:5112d5ae6723 4147
mbed_official 545:5112d5ae6723 4148 /*----------------------------------------------------------------------------*/
mbed_official 545:5112d5ae6723 4149 #define TIM3_OR_ITR2_RMP ((uint32_t)0x00000001) /*!<ITR2_RMP bit (TIM3 Internal trigger 2 remap) */
mbed_official 545:5112d5ae6723 4150
mbed_official 545:5112d5ae6723 4151 /*----------------------------------------------------------------------------*/
mbed_official 545:5112d5ae6723 4152
mbed_official 545:5112d5ae6723 4153
mbed_official 545:5112d5ae6723 4154 /******************************************************************************/
mbed_official 545:5112d5ae6723 4155 /* */
mbed_official 545:5112d5ae6723 4156 /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
mbed_official 545:5112d5ae6723 4157 /* */
mbed_official 545:5112d5ae6723 4158 /******************************************************************************/
mbed_official 545:5112d5ae6723 4159
mbed_official 545:5112d5ae6723 4160 /******************* Bit definition for USART_SR register *******************/
mbed_official 545:5112d5ae6723 4161 #define USART_SR_PE ((uint32_t)0x00000001) /*!< Parity Error */
mbed_official 545:5112d5ae6723 4162 #define USART_SR_FE ((uint32_t)0x00000002) /*!< Framing Error */
mbed_official 545:5112d5ae6723 4163 #define USART_SR_NE ((uint32_t)0x00000004) /*!< Noise Error Flag */
mbed_official 545:5112d5ae6723 4164 #define USART_SR_ORE ((uint32_t)0x00000008) /*!< OverRun Error */
mbed_official 545:5112d5ae6723 4165 #define USART_SR_IDLE ((uint32_t)0x00000010) /*!< IDLE line detected */
mbed_official 545:5112d5ae6723 4166 #define USART_SR_RXNE ((uint32_t)0x00000020) /*!< Read Data Register Not Empty */
mbed_official 545:5112d5ae6723 4167 #define USART_SR_TC ((uint32_t)0x00000040) /*!< Transmission Complete */
mbed_official 545:5112d5ae6723 4168 #define USART_SR_TXE ((uint32_t)0x00000080) /*!< Transmit Data Register Empty */
mbed_official 545:5112d5ae6723 4169 #define USART_SR_LBD ((uint32_t)0x00000100) /*!< LIN Break Detection Flag */
mbed_official 545:5112d5ae6723 4170 #define USART_SR_CTS ((uint32_t)0x00000200) /*!< CTS Flag */
mbed_official 545:5112d5ae6723 4171
mbed_official 545:5112d5ae6723 4172 /******************* Bit definition for USART_DR register *******************/
mbed_official 545:5112d5ae6723 4173 #define USART_DR_DR ((uint32_t)0x000001FF) /*!< Data value */
mbed_official 545:5112d5ae6723 4174
mbed_official 545:5112d5ae6723 4175 /****************** Bit definition for USART_BRR register *******************/
mbed_official 545:5112d5ae6723 4176 #define USART_BRR_DIV_FRACTION ((uint32_t)0x0000000F) /*!< Fraction of USARTDIV */
mbed_official 545:5112d5ae6723 4177 #define USART_BRR_DIV_MANTISSA ((uint32_t)0x0000FFF0) /*!< Mantissa of USARTDIV */
mbed_official 545:5112d5ae6723 4178
mbed_official 545:5112d5ae6723 4179 /****************** Bit definition for USART_CR1 register *******************/
mbed_official 545:5112d5ae6723 4180 #define USART_CR1_SBK ((uint32_t)0x00000001) /*!< Send Break */
mbed_official 545:5112d5ae6723 4181 #define USART_CR1_RWU ((uint32_t)0x00000002) /*!< Receiver wakeup */
mbed_official 545:5112d5ae6723 4182 #define USART_CR1_RE ((uint32_t)0x00000004) /*!< Receiver Enable */
mbed_official 545:5112d5ae6723 4183 #define USART_CR1_TE ((uint32_t)0x00000008) /*!< Transmitter Enable */
mbed_official 545:5112d5ae6723 4184 #define USART_CR1_IDLEIE ((uint32_t)0x00000010) /*!< IDLE Interrupt Enable */
mbed_official 545:5112d5ae6723 4185 #define USART_CR1_RXNEIE ((uint32_t)0x00000020) /*!< RXNE Interrupt Enable */
mbed_official 545:5112d5ae6723 4186 #define USART_CR1_TCIE ((uint32_t)0x00000040) /*!< Transmission Complete Interrupt Enable */
mbed_official 545:5112d5ae6723 4187 #define USART_CR1_TXEIE ((uint32_t)0x00000080) /*!< PE Interrupt Enable */
mbed_official 545:5112d5ae6723 4188 #define USART_CR1_PEIE ((uint32_t)0x00000100) /*!< PE Interrupt Enable */
mbed_official 545:5112d5ae6723 4189 #define USART_CR1_PS ((uint32_t)0x00000200) /*!< Parity Selection */
mbed_official 545:5112d5ae6723 4190 #define USART_CR1_PCE ((uint32_t)0x00000400) /*!< Parity Control Enable */
mbed_official 545:5112d5ae6723 4191 #define USART_CR1_WAKE ((uint32_t)0x00000800) /*!< Wakeup method */
mbed_official 545:5112d5ae6723 4192 #define USART_CR1_M ((uint32_t)0x00001000) /*!< Word length */
mbed_official 545:5112d5ae6723 4193 #define USART_CR1_UE ((uint32_t)0x00002000) /*!< USART Enable */
mbed_official 545:5112d5ae6723 4194 #define USART_CR1_OVER8 ((uint32_t)0x00008000) /*!< Oversampling by 8-bit mode */
mbed_official 545:5112d5ae6723 4195
mbed_official 545:5112d5ae6723 4196 /****************** Bit definition for USART_CR2 register *******************/
mbed_official 545:5112d5ae6723 4197 #define USART_CR2_ADD ((uint32_t)0x0000000F) /*!< Address of the USART node */
mbed_official 545:5112d5ae6723 4198 #define USART_CR2_LBDL ((uint32_t)0x00000020) /*!< LIN Break Detection Length */
mbed_official 545:5112d5ae6723 4199 #define USART_CR2_LBDIE ((uint32_t)0x00000040) /*!< LIN Break Detection Interrupt Enable */
mbed_official 545:5112d5ae6723 4200 #define USART_CR2_LBCL ((uint32_t)0x00000100) /*!< Last Bit Clock pulse */
mbed_official 545:5112d5ae6723 4201 #define USART_CR2_CPHA ((uint32_t)0x00000200) /*!< Clock Phase */
mbed_official 545:5112d5ae6723 4202 #define USART_CR2_CPOL ((uint32_t)0x00000400) /*!< Clock Polarity */
mbed_official 545:5112d5ae6723 4203 #define USART_CR2_CLKEN ((uint32_t)0x00000800) /*!< Clock Enable */
mbed_official 545:5112d5ae6723 4204
mbed_official 545:5112d5ae6723 4205 #define USART_CR2_STOP ((uint32_t)0x00003000) /*!< STOP[1:0] bits (STOP bits) */
mbed_official 545:5112d5ae6723 4206 #define USART_CR2_STOP_0 ((uint32_t)0x00001000) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 4207 #define USART_CR2_STOP_1 ((uint32_t)0x00002000) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 4208
mbed_official 545:5112d5ae6723 4209 #define USART_CR2_LINEN ((uint32_t)0x00004000) /*!< LIN mode enable */
mbed_official 545:5112d5ae6723 4210
mbed_official 545:5112d5ae6723 4211 /****************** Bit definition for USART_CR3 register *******************/
mbed_official 545:5112d5ae6723 4212 #define USART_CR3_EIE ((uint32_t)0x00000001) /*!< Error Interrupt Enable */
mbed_official 545:5112d5ae6723 4213 #define USART_CR3_IREN ((uint32_t)0x00000002) /*!< IrDA mode Enable */
mbed_official 545:5112d5ae6723 4214 #define USART_CR3_IRLP ((uint32_t)0x00000004) /*!< IrDA Low-Power */
mbed_official 545:5112d5ae6723 4215 #define USART_CR3_HDSEL ((uint32_t)0x00000008) /*!< Half-Duplex Selection */
mbed_official 545:5112d5ae6723 4216 #define USART_CR3_NACK ((uint32_t)0x00000010) /*!< Smartcard NACK enable */
mbed_official 545:5112d5ae6723 4217 #define USART_CR3_SCEN ((uint32_t)0x00000020) /*!< Smartcard mode enable */
mbed_official 545:5112d5ae6723 4218 #define USART_CR3_DMAR ((uint32_t)0x00000040) /*!< DMA Enable Receiver */
mbed_official 545:5112d5ae6723 4219 #define USART_CR3_DMAT ((uint32_t)0x00000080) /*!< DMA Enable Transmitter */
mbed_official 545:5112d5ae6723 4220 #define USART_CR3_RTSE ((uint32_t)0x00000100) /*!< RTS Enable */
mbed_official 545:5112d5ae6723 4221 #define USART_CR3_CTSE ((uint32_t)0x00000200) /*!< CTS Enable */
mbed_official 545:5112d5ae6723 4222 #define USART_CR3_CTSIE ((uint32_t)0x00000400) /*!< CTS Interrupt Enable */
mbed_official 545:5112d5ae6723 4223 #define USART_CR3_ONEBIT ((uint32_t)0x00000800) /*!< One sample bit method enable */
mbed_official 545:5112d5ae6723 4224
mbed_official 545:5112d5ae6723 4225 /****************** Bit definition for USART_GTPR register ******************/
mbed_official 545:5112d5ae6723 4226 #define USART_GTPR_PSC ((uint32_t)0x000000FF) /*!< PSC[7:0] bits (Prescaler value) */
mbed_official 545:5112d5ae6723 4227 #define USART_GTPR_PSC_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 4228 #define USART_GTPR_PSC_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 4229 #define USART_GTPR_PSC_2 ((uint32_t)0x00000004) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 4230 #define USART_GTPR_PSC_3 ((uint32_t)0x00000008) /*!< Bit 3 */
mbed_official 545:5112d5ae6723 4231 #define USART_GTPR_PSC_4 ((uint32_t)0x00000010) /*!< Bit 4 */
mbed_official 545:5112d5ae6723 4232 #define USART_GTPR_PSC_5 ((uint32_t)0x00000020) /*!< Bit 5 */
mbed_official 545:5112d5ae6723 4233 #define USART_GTPR_PSC_6 ((uint32_t)0x00000040) /*!< Bit 6 */
mbed_official 545:5112d5ae6723 4234 #define USART_GTPR_PSC_7 ((uint32_t)0x00000080) /*!< Bit 7 */
mbed_official 545:5112d5ae6723 4235
mbed_official 545:5112d5ae6723 4236 #define USART_GTPR_GT ((uint32_t)0x0000FF00) /*!< Guard time value */
mbed_official 545:5112d5ae6723 4237
mbed_official 545:5112d5ae6723 4238 /******************************************************************************/
mbed_official 545:5112d5ae6723 4239 /* */
mbed_official 545:5112d5ae6723 4240 /* Universal Serial Bus (USB) */
mbed_official 545:5112d5ae6723 4241 /* */
mbed_official 545:5112d5ae6723 4242 /******************************************************************************/
mbed_official 545:5112d5ae6723 4243
mbed_official 545:5112d5ae6723 4244 /*!<Endpoint-specific registers */
mbed_official 545:5112d5ae6723 4245
mbed_official 545:5112d5ae6723 4246 #define USB_EP0R USB_BASE /*!< endpoint 0 register address */
mbed_official 545:5112d5ae6723 4247 #define USB_EP1R (USB_BASE + 0x00000004) /*!< endpoint 1 register address */
mbed_official 545:5112d5ae6723 4248 #define USB_EP2R (USB_BASE + 0x00000008) /*!< endpoint 2 register address */
mbed_official 545:5112d5ae6723 4249 #define USB_EP3R (USB_BASE + 0x0000000C) /*!< endpoint 3 register address */
mbed_official 545:5112d5ae6723 4250 #define USB_EP4R (USB_BASE + 0x00000010) /*!< endpoint 4 register address */
mbed_official 545:5112d5ae6723 4251 #define USB_EP5R (USB_BASE + 0x00000014) /*!< endpoint 5 register address */
mbed_official 545:5112d5ae6723 4252 #define USB_EP6R (USB_BASE + 0x00000018) /*!< endpoint 6 register address */
mbed_official 545:5112d5ae6723 4253 #define USB_EP7R (USB_BASE + 0x0000001C) /*!< endpoint 7 register address */
mbed_official 545:5112d5ae6723 4254
mbed_official 545:5112d5ae6723 4255 /* bit positions */
mbed_official 545:5112d5ae6723 4256 #define USB_EP_CTR_RX ((uint32_t)0x00008000) /*!< EndPoint Correct TRansfer RX */
mbed_official 545:5112d5ae6723 4257 #define USB_EP_DTOG_RX ((uint32_t)0x00004000) /*!< EndPoint Data TOGGLE RX */
mbed_official 545:5112d5ae6723 4258 #define USB_EPRX_STAT ((uint32_t)0x00003000) /*!< EndPoint RX STATus bit field */
mbed_official 545:5112d5ae6723 4259 #define USB_EP_SETUP ((uint32_t)0x00000800) /*!< EndPoint SETUP */
mbed_official 545:5112d5ae6723 4260 #define USB_EP_T_FIELD ((uint32_t)0x00000600) /*!< EndPoint TYPE */
mbed_official 545:5112d5ae6723 4261 #define USB_EP_KIND ((uint32_t)0x00000100) /*!< EndPoint KIND */
mbed_official 545:5112d5ae6723 4262 #define USB_EP_CTR_TX ((uint32_t)0x00000080) /*!< EndPoint Correct TRansfer TX */
mbed_official 545:5112d5ae6723 4263 #define USB_EP_DTOG_TX ((uint32_t)0x00000040) /*!< EndPoint Data TOGGLE TX */
mbed_official 545:5112d5ae6723 4264 #define USB_EPTX_STAT ((uint32_t)0x00000030) /*!< EndPoint TX STATus bit field */
mbed_official 545:5112d5ae6723 4265 #define USB_EPADDR_FIELD ((uint32_t)0x0000000F) /*!< EndPoint ADDRess FIELD */
mbed_official 545:5112d5ae6723 4266
mbed_official 545:5112d5ae6723 4267 /* EndPoint REGister MASK (no toggle fields) */
mbed_official 545:5112d5ae6723 4268 #define USB_EPREG_MASK (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
mbed_official 545:5112d5ae6723 4269 /*!< EP_TYPE[1:0] EndPoint TYPE */
mbed_official 545:5112d5ae6723 4270 #define USB_EP_TYPE_MASK ((uint32_t)0x00000600) /*!< EndPoint TYPE Mask */
mbed_official 545:5112d5ae6723 4271 #define USB_EP_BULK ((uint32_t)0x00000000) /*!< EndPoint BULK */
mbed_official 545:5112d5ae6723 4272 #define USB_EP_CONTROL ((uint32_t)0x00000200) /*!< EndPoint CONTROL */
mbed_official 545:5112d5ae6723 4273 #define USB_EP_ISOCHRONOUS ((uint32_t)0x00000400) /*!< EndPoint ISOCHRONOUS */
mbed_official 545:5112d5ae6723 4274 #define USB_EP_INTERRUPT ((uint32_t)0x00000600) /*!< EndPoint INTERRUPT */
mbed_official 545:5112d5ae6723 4275 #define USB_EP_T_MASK (~USB_EP_T_FIELD & USB_EPREG_MASK)
mbed_official 545:5112d5ae6723 4276
mbed_official 545:5112d5ae6723 4277 #define USB_EPKIND_MASK (~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
mbed_official 545:5112d5ae6723 4278 /*!< STAT_TX[1:0] STATus for TX transfer */
mbed_official 545:5112d5ae6723 4279 #define USB_EP_TX_DIS ((uint32_t)0x00000000) /*!< EndPoint TX DISabled */
mbed_official 545:5112d5ae6723 4280 #define USB_EP_TX_STALL ((uint32_t)0x00000010) /*!< EndPoint TX STALLed */
mbed_official 545:5112d5ae6723 4281 #define USB_EP_TX_NAK ((uint32_t)0x00000020) /*!< EndPoint TX NAKed */
mbed_official 545:5112d5ae6723 4282 #define USB_EP_TX_VALID ((uint32_t)0x00000030) /*!< EndPoint TX VALID */
mbed_official 545:5112d5ae6723 4283 #define USB_EPTX_DTOG1 ((uint32_t)0x00000010) /*!< EndPoint TX Data TOGgle bit1 */
mbed_official 545:5112d5ae6723 4284 #define USB_EPTX_DTOG2 ((uint32_t)0x00000020) /*!< EndPoint TX Data TOGgle bit2 */
mbed_official 545:5112d5ae6723 4285 #define USB_EPTX_DTOGMASK (USB_EPTX_STAT|USB_EPREG_MASK)
mbed_official 545:5112d5ae6723 4286 /*!< STAT_RX[1:0] STATus for RX transfer */
mbed_official 545:5112d5ae6723 4287 #define USB_EP_RX_DIS ((uint32_t)0x00000000) /*!< EndPoint RX DISabled */
mbed_official 545:5112d5ae6723 4288 #define USB_EP_RX_STALL ((uint32_t)0x00001000) /*!< EndPoint RX STALLed */
mbed_official 545:5112d5ae6723 4289 #define USB_EP_RX_NAK ((uint32_t)0x00002000) /*!< EndPoint RX NAKed */
mbed_official 545:5112d5ae6723 4290 #define USB_EP_RX_VALID ((uint32_t)0x00003000) /*!< EndPoint RX VALID */
mbed_official 545:5112d5ae6723 4291 #define USB_EPRX_DTOG1 ((uint32_t)0x00001000) /*!< EndPoint RX Data TOGgle bit1 */
mbed_official 545:5112d5ae6723 4292 #define USB_EPRX_DTOG2 ((uint32_t)0x00002000) /*!< EndPoint RX Data TOGgle bit1 */
mbed_official 545:5112d5ae6723 4293 #define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK)
mbed_official 545:5112d5ae6723 4294
mbed_official 545:5112d5ae6723 4295 /******************* Bit definition for USB_EP0R register *******************/
mbed_official 545:5112d5ae6723 4296 #define USB_EP0R_EA ((uint32_t)0x0000000F) /*!<Endpoint Address */
mbed_official 545:5112d5ae6723 4297
mbed_official 545:5112d5ae6723 4298 #define USB_EP0R_STAT_TX ((uint32_t)0x00000030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
mbed_official 545:5112d5ae6723 4299 #define USB_EP0R_STAT_TX_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 545:5112d5ae6723 4300 #define USB_EP0R_STAT_TX_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 545:5112d5ae6723 4301
mbed_official 545:5112d5ae6723 4302 #define USB_EP0R_DTOG_TX ((uint32_t)0x00000040) /*!<Data Toggle, for transmission transfers */
mbed_official 545:5112d5ae6723 4303 #define USB_EP0R_CTR_TX ((uint32_t)0x00000080) /*!<Correct Transfer for transmission */
mbed_official 545:5112d5ae6723 4304 #define USB_EP0R_EP_KIND ((uint32_t)0x00000100) /*!<Endpoint Kind */
mbed_official 545:5112d5ae6723 4305
mbed_official 545:5112d5ae6723 4306 #define USB_EP0R_EP_TYPE ((uint32_t)0x00000600) /*!<EP_TYPE[1:0] bits (Endpoint type) */
mbed_official 545:5112d5ae6723 4307 #define USB_EP0R_EP_TYPE_0 ((uint32_t)0x00000200) /*!<Bit 0 */
mbed_official 545:5112d5ae6723 4308 #define USB_EP0R_EP_TYPE_1 ((uint32_t)0x00000400) /*!<Bit 1 */
mbed_official 545:5112d5ae6723 4309
mbed_official 545:5112d5ae6723 4310 #define USB_EP0R_SETUP ((uint32_t)0x00000800) /*!<Setup transaction completed */
mbed_official 545:5112d5ae6723 4311
mbed_official 545:5112d5ae6723 4312 #define USB_EP0R_STAT_RX ((uint32_t)0x00003000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
mbed_official 545:5112d5ae6723 4313 #define USB_EP0R_STAT_RX_0 ((uint32_t)0x00001000) /*!<Bit 0 */
mbed_official 545:5112d5ae6723 4314 #define USB_EP0R_STAT_RX_1 ((uint32_t)0x00002000) /*!<Bit 1 */
mbed_official 545:5112d5ae6723 4315
mbed_official 545:5112d5ae6723 4316 #define USB_EP0R_DTOG_RX ((uint32_t)0x00004000) /*!<Data Toggle, for reception transfers */
mbed_official 545:5112d5ae6723 4317 #define USB_EP0R_CTR_RX ((uint32_t)0x00008000) /*!<Correct Transfer for reception */
mbed_official 545:5112d5ae6723 4318
mbed_official 545:5112d5ae6723 4319 /******************* Bit definition for USB_EP1R register *******************/
mbed_official 545:5112d5ae6723 4320 #define USB_EP1R_EA ((uint32_t)0x0000000F) /*!<Endpoint Address */
mbed_official 545:5112d5ae6723 4321
mbed_official 545:5112d5ae6723 4322 #define USB_EP1R_STAT_TX ((uint32_t)0x00000030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
mbed_official 545:5112d5ae6723 4323 #define USB_EP1R_STAT_TX_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 545:5112d5ae6723 4324 #define USB_EP1R_STAT_TX_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 545:5112d5ae6723 4325
mbed_official 545:5112d5ae6723 4326 #define USB_EP1R_DTOG_TX ((uint32_t)0x00000040) /*!<Data Toggle, for transmission transfers */
mbed_official 545:5112d5ae6723 4327 #define USB_EP1R_CTR_TX ((uint32_t)0x00000080) /*!<Correct Transfer for transmission */
mbed_official 545:5112d5ae6723 4328 #define USB_EP1R_EP_KIND ((uint32_t)0x00000100) /*!<Endpoint Kind */
mbed_official 545:5112d5ae6723 4329
mbed_official 545:5112d5ae6723 4330 #define USB_EP1R_EP_TYPE ((uint32_t)0x00000600) /*!<EP_TYPE[1:0] bits (Endpoint type) */
mbed_official 545:5112d5ae6723 4331 #define USB_EP1R_EP_TYPE_0 ((uint32_t)0x00000200) /*!<Bit 0 */
mbed_official 545:5112d5ae6723 4332 #define USB_EP1R_EP_TYPE_1 ((uint32_t)0x00000400) /*!<Bit 1 */
mbed_official 545:5112d5ae6723 4333
mbed_official 545:5112d5ae6723 4334 #define USB_EP1R_SETUP ((uint32_t)0x00000800) /*!<Setup transaction completed */
mbed_official 545:5112d5ae6723 4335
mbed_official 545:5112d5ae6723 4336 #define USB_EP1R_STAT_RX ((uint32_t)0x00003000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
mbed_official 545:5112d5ae6723 4337 #define USB_EP1R_STAT_RX_0 ((uint32_t)0x00001000) /*!<Bit 0 */
mbed_official 545:5112d5ae6723 4338 #define USB_EP1R_STAT_RX_1 ((uint32_t)0x00002000) /*!<Bit 1 */
mbed_official 545:5112d5ae6723 4339
mbed_official 545:5112d5ae6723 4340 #define USB_EP1R_DTOG_RX ((uint32_t)0x00004000) /*!<Data Toggle, for reception transfers */
mbed_official 545:5112d5ae6723 4341 #define USB_EP1R_CTR_RX ((uint32_t)0x00008000) /*!<Correct Transfer for reception */
mbed_official 545:5112d5ae6723 4342
mbed_official 545:5112d5ae6723 4343 /******************* Bit definition for USB_EP2R register *******************/
mbed_official 545:5112d5ae6723 4344 #define USB_EP2R_EA ((uint32_t)0x0000000F) /*!<Endpoint Address */
mbed_official 545:5112d5ae6723 4345
mbed_official 545:5112d5ae6723 4346 #define USB_EP2R_STAT_TX ((uint32_t)0x00000030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
mbed_official 545:5112d5ae6723 4347 #define USB_EP2R_STAT_TX_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 545:5112d5ae6723 4348 #define USB_EP2R_STAT_TX_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 545:5112d5ae6723 4349
mbed_official 545:5112d5ae6723 4350 #define USB_EP2R_DTOG_TX ((uint32_t)0x00000040) /*!<Data Toggle, for transmission transfers */
mbed_official 545:5112d5ae6723 4351 #define USB_EP2R_CTR_TX ((uint32_t)0x00000080) /*!<Correct Transfer for transmission */
mbed_official 545:5112d5ae6723 4352 #define USB_EP2R_EP_KIND ((uint32_t)0x00000100) /*!<Endpoint Kind */
mbed_official 545:5112d5ae6723 4353
mbed_official 545:5112d5ae6723 4354 #define USB_EP2R_EP_TYPE ((uint32_t)0x00000600) /*!<EP_TYPE[1:0] bits (Endpoint type) */
mbed_official 545:5112d5ae6723 4355 #define USB_EP2R_EP_TYPE_0 ((uint32_t)0x00000200) /*!<Bit 0 */
mbed_official 545:5112d5ae6723 4356 #define USB_EP2R_EP_TYPE_1 ((uint32_t)0x00000400) /*!<Bit 1 */
mbed_official 545:5112d5ae6723 4357
mbed_official 545:5112d5ae6723 4358 #define USB_EP2R_SETUP ((uint32_t)0x00000800) /*!<Setup transaction completed */
mbed_official 545:5112d5ae6723 4359
mbed_official 545:5112d5ae6723 4360 #define USB_EP2R_STAT_RX ((uint32_t)0x00003000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
mbed_official 545:5112d5ae6723 4361 #define USB_EP2R_STAT_RX_0 ((uint32_t)0x00001000) /*!<Bit 0 */
mbed_official 545:5112d5ae6723 4362 #define USB_EP2R_STAT_RX_1 ((uint32_t)0x00002000) /*!<Bit 1 */
mbed_official 545:5112d5ae6723 4363
mbed_official 545:5112d5ae6723 4364 #define USB_EP2R_DTOG_RX ((uint32_t)0x00004000) /*!<Data Toggle, for reception transfers */
mbed_official 545:5112d5ae6723 4365 #define USB_EP2R_CTR_RX ((uint32_t)0x00008000) /*!<Correct Transfer for reception */
mbed_official 545:5112d5ae6723 4366
mbed_official 545:5112d5ae6723 4367 /******************* Bit definition for USB_EP3R register *******************/
mbed_official 545:5112d5ae6723 4368 #define USB_EP3R_EA ((uint32_t)0x0000000F) /*!<Endpoint Address */
mbed_official 545:5112d5ae6723 4369
mbed_official 545:5112d5ae6723 4370 #define USB_EP3R_STAT_TX ((uint32_t)0x00000030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
mbed_official 545:5112d5ae6723 4371 #define USB_EP3R_STAT_TX_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 545:5112d5ae6723 4372 #define USB_EP3R_STAT_TX_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 545:5112d5ae6723 4373
mbed_official 545:5112d5ae6723 4374 #define USB_EP3R_DTOG_TX ((uint32_t)0x00000040) /*!<Data Toggle, for transmission transfers */
mbed_official 545:5112d5ae6723 4375 #define USB_EP3R_CTR_TX ((uint32_t)0x00000080) /*!<Correct Transfer for transmission */
mbed_official 545:5112d5ae6723 4376 #define USB_EP3R_EP_KIND ((uint32_t)0x00000100) /*!<Endpoint Kind */
mbed_official 545:5112d5ae6723 4377
mbed_official 545:5112d5ae6723 4378 #define USB_EP3R_EP_TYPE ((uint32_t)0x00000600) /*!<EP_TYPE[1:0] bits (Endpoint type) */
mbed_official 545:5112d5ae6723 4379 #define USB_EP3R_EP_TYPE_0 ((uint32_t)0x00000200) /*!<Bit 0 */
mbed_official 545:5112d5ae6723 4380 #define USB_EP3R_EP_TYPE_1 ((uint32_t)0x00000400) /*!<Bit 1 */
mbed_official 545:5112d5ae6723 4381
mbed_official 545:5112d5ae6723 4382 #define USB_EP3R_SETUP ((uint32_t)0x00000800) /*!<Setup transaction completed */
mbed_official 545:5112d5ae6723 4383
mbed_official 545:5112d5ae6723 4384 #define USB_EP3R_STAT_RX ((uint32_t)0x00003000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
mbed_official 545:5112d5ae6723 4385 #define USB_EP3R_STAT_RX_0 ((uint32_t)0x00001000) /*!<Bit 0 */
mbed_official 545:5112d5ae6723 4386 #define USB_EP3R_STAT_RX_1 ((uint32_t)0x00002000) /*!<Bit 1 */
mbed_official 545:5112d5ae6723 4387
mbed_official 545:5112d5ae6723 4388 #define USB_EP3R_DTOG_RX ((uint32_t)0x00004000) /*!<Data Toggle, for reception transfers */
mbed_official 545:5112d5ae6723 4389 #define USB_EP3R_CTR_RX ((uint32_t)0x00008000) /*!<Correct Transfer for reception */
mbed_official 545:5112d5ae6723 4390
mbed_official 545:5112d5ae6723 4391 /******************* Bit definition for USB_EP4R register *******************/
mbed_official 545:5112d5ae6723 4392 #define USB_EP4R_EA ((uint32_t)0x0000000F) /*!<Endpoint Address */
mbed_official 545:5112d5ae6723 4393
mbed_official 545:5112d5ae6723 4394 #define USB_EP4R_STAT_TX ((uint32_t)0x00000030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
mbed_official 545:5112d5ae6723 4395 #define USB_EP4R_STAT_TX_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 545:5112d5ae6723 4396 #define USB_EP4R_STAT_TX_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 545:5112d5ae6723 4397
mbed_official 545:5112d5ae6723 4398 #define USB_EP4R_DTOG_TX ((uint32_t)0x00000040) /*!<Data Toggle, for transmission transfers */
mbed_official 545:5112d5ae6723 4399 #define USB_EP4R_CTR_TX ((uint32_t)0x00000080) /*!<Correct Transfer for transmission */
mbed_official 545:5112d5ae6723 4400 #define USB_EP4R_EP_KIND ((uint32_t)0x00000100) /*!<Endpoint Kind */
mbed_official 545:5112d5ae6723 4401
mbed_official 545:5112d5ae6723 4402 #define USB_EP4R_EP_TYPE ((uint32_t)0x00000600) /*!<EP_TYPE[1:0] bits (Endpoint type) */
mbed_official 545:5112d5ae6723 4403 #define USB_EP4R_EP_TYPE_0 ((uint32_t)0x00000200) /*!<Bit 0 */
mbed_official 545:5112d5ae6723 4404 #define USB_EP4R_EP_TYPE_1 ((uint32_t)0x00000400) /*!<Bit 1 */
mbed_official 545:5112d5ae6723 4405
mbed_official 545:5112d5ae6723 4406 #define USB_EP4R_SETUP ((uint32_t)0x00000800) /*!<Setup transaction completed */
mbed_official 545:5112d5ae6723 4407
mbed_official 545:5112d5ae6723 4408 #define USB_EP4R_STAT_RX ((uint32_t)0x00003000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
mbed_official 545:5112d5ae6723 4409 #define USB_EP4R_STAT_RX_0 ((uint32_t)0x00001000) /*!<Bit 0 */
mbed_official 545:5112d5ae6723 4410 #define USB_EP4R_STAT_RX_1 ((uint32_t)0x00002000) /*!<Bit 1 */
mbed_official 545:5112d5ae6723 4411
mbed_official 545:5112d5ae6723 4412 #define USB_EP4R_DTOG_RX ((uint32_t)0x00004000) /*!<Data Toggle, for reception transfers */
mbed_official 545:5112d5ae6723 4413 #define USB_EP4R_CTR_RX ((uint32_t)0x00008000) /*!<Correct Transfer for reception */
mbed_official 545:5112d5ae6723 4414
mbed_official 545:5112d5ae6723 4415 /******************* Bit definition for USB_EP5R register *******************/
mbed_official 545:5112d5ae6723 4416 #define USB_EP5R_EA ((uint32_t)0x0000000F) /*!<Endpoint Address */
mbed_official 545:5112d5ae6723 4417
mbed_official 545:5112d5ae6723 4418 #define USB_EP5R_STAT_TX ((uint32_t)0x00000030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
mbed_official 545:5112d5ae6723 4419 #define USB_EP5R_STAT_TX_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 545:5112d5ae6723 4420 #define USB_EP5R_STAT_TX_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 545:5112d5ae6723 4421
mbed_official 545:5112d5ae6723 4422 #define USB_EP5R_DTOG_TX ((uint32_t)0x00000040) /*!<Data Toggle, for transmission transfers */
mbed_official 545:5112d5ae6723 4423 #define USB_EP5R_CTR_TX ((uint32_t)0x00000080) /*!<Correct Transfer for transmission */
mbed_official 545:5112d5ae6723 4424 #define USB_EP5R_EP_KIND ((uint32_t)0x00000100) /*!<Endpoint Kind */
mbed_official 545:5112d5ae6723 4425
mbed_official 545:5112d5ae6723 4426 #define USB_EP5R_EP_TYPE ((uint32_t)0x00000600) /*!<EP_TYPE[1:0] bits (Endpoint type) */
mbed_official 545:5112d5ae6723 4427 #define USB_EP5R_EP_TYPE_0 ((uint32_t)0x00000200) /*!<Bit 0 */
mbed_official 545:5112d5ae6723 4428 #define USB_EP5R_EP_TYPE_1 ((uint32_t)0x00000400) /*!<Bit 1 */
mbed_official 545:5112d5ae6723 4429
mbed_official 545:5112d5ae6723 4430 #define USB_EP5R_SETUP ((uint32_t)0x00000800) /*!<Setup transaction completed */
mbed_official 545:5112d5ae6723 4431
mbed_official 545:5112d5ae6723 4432 #define USB_EP5R_STAT_RX ((uint32_t)0x00003000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
mbed_official 545:5112d5ae6723 4433 #define USB_EP5R_STAT_RX_0 ((uint32_t)0x00001000) /*!<Bit 0 */
mbed_official 545:5112d5ae6723 4434 #define USB_EP5R_STAT_RX_1 ((uint32_t)0x00002000) /*!<Bit 1 */
mbed_official 545:5112d5ae6723 4435
mbed_official 545:5112d5ae6723 4436 #define USB_EP5R_DTOG_RX ((uint32_t)0x00004000) /*!<Data Toggle, for reception transfers */
mbed_official 545:5112d5ae6723 4437 #define USB_EP5R_CTR_RX ((uint32_t)0x00008000) /*!<Correct Transfer for reception */
mbed_official 545:5112d5ae6723 4438
mbed_official 545:5112d5ae6723 4439 /******************* Bit definition for USB_EP6R register *******************/
mbed_official 545:5112d5ae6723 4440 #define USB_EP6R_EA ((uint32_t)0x0000000F) /*!<Endpoint Address */
mbed_official 545:5112d5ae6723 4441
mbed_official 545:5112d5ae6723 4442 #define USB_EP6R_STAT_TX ((uint32_t)0x00000030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
mbed_official 545:5112d5ae6723 4443 #define USB_EP6R_STAT_TX_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 545:5112d5ae6723 4444 #define USB_EP6R_STAT_TX_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 545:5112d5ae6723 4445
mbed_official 545:5112d5ae6723 4446 #define USB_EP6R_DTOG_TX ((uint32_t)0x00000040) /*!<Data Toggle, for transmission transfers */
mbed_official 545:5112d5ae6723 4447 #define USB_EP6R_CTR_TX ((uint32_t)0x00000080) /*!<Correct Transfer for transmission */
mbed_official 545:5112d5ae6723 4448 #define USB_EP6R_EP_KIND ((uint32_t)0x00000100) /*!<Endpoint Kind */
mbed_official 545:5112d5ae6723 4449
mbed_official 545:5112d5ae6723 4450 #define USB_EP6R_EP_TYPE ((uint32_t)0x00000600) /*!<EP_TYPE[1:0] bits (Endpoint type) */
mbed_official 545:5112d5ae6723 4451 #define USB_EP6R_EP_TYPE_0 ((uint32_t)0x00000200) /*!<Bit 0 */
mbed_official 545:5112d5ae6723 4452 #define USB_EP6R_EP_TYPE_1 ((uint32_t)0x00000400) /*!<Bit 1 */
mbed_official 545:5112d5ae6723 4453
mbed_official 545:5112d5ae6723 4454 #define USB_EP6R_SETUP ((uint32_t)0x00000800) /*!<Setup transaction completed */
mbed_official 545:5112d5ae6723 4455
mbed_official 545:5112d5ae6723 4456 #define USB_EP6R_STAT_RX ((uint32_t)0x00003000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
mbed_official 545:5112d5ae6723 4457 #define USB_EP6R_STAT_RX_0 ((uint32_t)0x00001000) /*!<Bit 0 */
mbed_official 545:5112d5ae6723 4458 #define USB_EP6R_STAT_RX_1 ((uint32_t)0x00002000) /*!<Bit 1 */
mbed_official 545:5112d5ae6723 4459
mbed_official 545:5112d5ae6723 4460 #define USB_EP6R_DTOG_RX ((uint32_t)0x00004000) /*!<Data Toggle, for reception transfers */
mbed_official 545:5112d5ae6723 4461 #define USB_EP6R_CTR_RX ((uint32_t)0x00008000) /*!<Correct Transfer for reception */
mbed_official 545:5112d5ae6723 4462
mbed_official 545:5112d5ae6723 4463 /******************* Bit definition for USB_EP7R register *******************/
mbed_official 545:5112d5ae6723 4464 #define USB_EP7R_EA ((uint32_t)0x0000000F) /*!<Endpoint Address */
mbed_official 545:5112d5ae6723 4465
mbed_official 545:5112d5ae6723 4466 #define USB_EP7R_STAT_TX ((uint32_t)0x00000030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
mbed_official 545:5112d5ae6723 4467 #define USB_EP7R_STAT_TX_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 545:5112d5ae6723 4468 #define USB_EP7R_STAT_TX_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 545:5112d5ae6723 4469
mbed_official 545:5112d5ae6723 4470 #define USB_EP7R_DTOG_TX ((uint32_t)0x00000040) /*!<Data Toggle, for transmission transfers */
mbed_official 545:5112d5ae6723 4471 #define USB_EP7R_CTR_TX ((uint32_t)0x00000080) /*!<Correct Transfer for transmission */
mbed_official 545:5112d5ae6723 4472 #define USB_EP7R_EP_KIND ((uint32_t)0x00000100) /*!<Endpoint Kind */
mbed_official 545:5112d5ae6723 4473
mbed_official 545:5112d5ae6723 4474 #define USB_EP7R_EP_TYPE ((uint32_t)0x00000600) /*!<EP_TYPE[1:0] bits (Endpoint type) */
mbed_official 545:5112d5ae6723 4475 #define USB_EP7R_EP_TYPE_0 ((uint32_t)0x00000200) /*!<Bit 0 */
mbed_official 545:5112d5ae6723 4476 #define USB_EP7R_EP_TYPE_1 ((uint32_t)0x00000400) /*!<Bit 1 */
mbed_official 545:5112d5ae6723 4477
mbed_official 545:5112d5ae6723 4478 #define USB_EP7R_SETUP ((uint32_t)0x00000800) /*!<Setup transaction completed */
mbed_official 545:5112d5ae6723 4479
mbed_official 545:5112d5ae6723 4480 #define USB_EP7R_STAT_RX ((uint32_t)0x00003000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
mbed_official 545:5112d5ae6723 4481 #define USB_EP7R_STAT_RX_0 ((uint32_t)0x00001000) /*!<Bit 0 */
mbed_official 545:5112d5ae6723 4482 #define USB_EP7R_STAT_RX_1 ((uint32_t)0x00002000) /*!<Bit 1 */
mbed_official 545:5112d5ae6723 4483
mbed_official 545:5112d5ae6723 4484 #define USB_EP7R_DTOG_RX ((uint32_t)0x00004000) /*!<Data Toggle, for reception transfers */
mbed_official 545:5112d5ae6723 4485 #define USB_EP7R_CTR_RX ((uint32_t)0x00008000) /*!<Correct Transfer for reception */
mbed_official 545:5112d5ae6723 4486
mbed_official 545:5112d5ae6723 4487 /*!<Common registers */
mbed_official 545:5112d5ae6723 4488
mbed_official 545:5112d5ae6723 4489 #define USB_CNTR (USB_BASE + 0x00000040) /*!< Control register */
mbed_official 545:5112d5ae6723 4490 #define USB_ISTR (USB_BASE + 0x00000044) /*!< Interrupt status register */
mbed_official 545:5112d5ae6723 4491 #define USB_FNR (USB_BASE + 0x00000048) /*!< Frame number register */
mbed_official 545:5112d5ae6723 4492 #define USB_DADDR (USB_BASE + 0x0000004C) /*!< Device address register */
mbed_official 545:5112d5ae6723 4493 #define USB_BTABLE (USB_BASE + 0x00000050) /*!< Buffer Table address register */
mbed_official 545:5112d5ae6723 4494
mbed_official 545:5112d5ae6723 4495
mbed_official 545:5112d5ae6723 4496
mbed_official 545:5112d5ae6723 4497 /******************* Bit definition for USB_CNTR register *******************/
mbed_official 545:5112d5ae6723 4498 #define USB_CNTR_FRES ((uint32_t)0x00000001) /*!<Force USB Reset */
mbed_official 545:5112d5ae6723 4499 #define USB_CNTR_PDWN ((uint32_t)0x00000002) /*!<Power down */
mbed_official 545:5112d5ae6723 4500 #define USB_CNTR_LP_MODE ((uint32_t)0x00000004) /*!<Low-power mode */
mbed_official 545:5112d5ae6723 4501 #define USB_CNTR_FSUSP ((uint32_t)0x00000008) /*!<Force suspend */
mbed_official 545:5112d5ae6723 4502 #define USB_CNTR_RESUME ((uint32_t)0x00000010) /*!<Resume request */
mbed_official 545:5112d5ae6723 4503 #define USB_CNTR_ESOFM ((uint32_t)0x00000100) /*!<Expected Start Of Frame Interrupt Mask */
mbed_official 545:5112d5ae6723 4504 #define USB_CNTR_SOFM ((uint32_t)0x00000200) /*!<Start Of Frame Interrupt Mask */
mbed_official 545:5112d5ae6723 4505 #define USB_CNTR_RESETM ((uint32_t)0x00000400) /*!<RESET Interrupt Mask */
mbed_official 545:5112d5ae6723 4506 #define USB_CNTR_SUSPM ((uint32_t)0x00000800) /*!<Suspend mode Interrupt Mask */
mbed_official 545:5112d5ae6723 4507 #define USB_CNTR_WKUPM ((uint32_t)0x00001000) /*!<Wakeup Interrupt Mask */
mbed_official 545:5112d5ae6723 4508 #define USB_CNTR_ERRM ((uint32_t)0x00002000) /*!<Error Interrupt Mask */
mbed_official 545:5112d5ae6723 4509 #define USB_CNTR_PMAOVRM ((uint32_t)0x00004000) /*!<Packet Memory Area Over / Underrun Interrupt Mask */
mbed_official 545:5112d5ae6723 4510 #define USB_CNTR_CTRM ((uint32_t)0x00008000) /*!<Correct Transfer Interrupt Mask */
mbed_official 545:5112d5ae6723 4511
mbed_official 545:5112d5ae6723 4512 /******************* Bit definition for USB_ISTR register *******************/
mbed_official 545:5112d5ae6723 4513 #define USB_ISTR_EP_ID ((uint32_t)0x0000000F) /*!<Endpoint Identifier */
mbed_official 545:5112d5ae6723 4514 #define USB_ISTR_DIR ((uint32_t)0x00000010) /*!<Direction of transaction */
mbed_official 545:5112d5ae6723 4515 #define USB_ISTR_ESOF ((uint32_t)0x00000100) /*!<Expected Start Of Frame */
mbed_official 545:5112d5ae6723 4516 #define USB_ISTR_SOF ((uint32_t)0x00000200) /*!<Start Of Frame */
mbed_official 545:5112d5ae6723 4517 #define USB_ISTR_RESET ((uint32_t)0x00000400) /*!<USB RESET request */
mbed_official 545:5112d5ae6723 4518 #define USB_ISTR_SUSP ((uint32_t)0x00000800) /*!<Suspend mode request */
mbed_official 545:5112d5ae6723 4519 #define USB_ISTR_WKUP ((uint32_t)0x00001000) /*!<Wake up */
mbed_official 545:5112d5ae6723 4520 #define USB_ISTR_ERR ((uint32_t)0x00002000) /*!<Error */
mbed_official 545:5112d5ae6723 4521 #define USB_ISTR_PMAOVRM ((uint32_t)0x00004000) /*!<Packet Memory Area Over / Underrun */
mbed_official 545:5112d5ae6723 4522 #define USB_ISTR_CTR ((uint32_t)0x00008000) /*!<Correct Transfer */
mbed_official 545:5112d5ae6723 4523
mbed_official 545:5112d5ae6723 4524 #define USB_CLR_CTR (~USB_ISTR_CTR) /*!< clear Correct TRansfer bit */
mbed_official 545:5112d5ae6723 4525 #define USB_CLR_PMAOVRM (~USB_ISTR_PMAOVR) /*!< clear DMA OVeR/underrun bit*/
mbed_official 545:5112d5ae6723 4526 #define USB_CLR_ERR (~USB_ISTR_ERR) /*!< clear ERRor bit */
mbed_official 545:5112d5ae6723 4527 #define USB_CLR_WKUP (~USB_ISTR_WKUP) /*!< clear WaKe UP bit */
mbed_official 545:5112d5ae6723 4528 #define USB_CLR_SUSP (~USB_ISTR_SUSP) /*!< clear SUSPend bit */
mbed_official 545:5112d5ae6723 4529 #define USB_CLR_RESET (~USB_ISTR_RESET) /*!< clear RESET bit */
mbed_official 545:5112d5ae6723 4530 #define USB_CLR_SOF (~USB_ISTR_SOF) /*!< clear Start Of Frame bit */
mbed_official 545:5112d5ae6723 4531 #define USB_CLR_ESOF (~USB_ISTR_ESOF) /*!< clear Expected Start Of Frame bit */
mbed_official 545:5112d5ae6723 4532
mbed_official 545:5112d5ae6723 4533
mbed_official 545:5112d5ae6723 4534 /******************* Bit definition for USB_FNR register ********************/
mbed_official 545:5112d5ae6723 4535 #define USB_FNR_FN ((uint32_t)0x000007FF) /*!<Frame Number */
mbed_official 545:5112d5ae6723 4536 #define USB_FNR_LSOF ((uint32_t)0x00001800) /*!<Lost SOF */
mbed_official 545:5112d5ae6723 4537 #define USB_FNR_LCK ((uint32_t)0x00002000) /*!<Locked */
mbed_official 545:5112d5ae6723 4538 #define USB_FNR_RXDM ((uint32_t)0x00004000) /*!<Receive Data - Line Status */
mbed_official 545:5112d5ae6723 4539 #define USB_FNR_RXDP ((uint32_t)0x00008000) /*!<Receive Data + Line Status */
mbed_official 545:5112d5ae6723 4540
mbed_official 545:5112d5ae6723 4541 /****************** Bit definition for USB_DADDR register *******************/
mbed_official 545:5112d5ae6723 4542 #define USB_DADDR_ADD ((uint32_t)0x0000007F) /*!<ADD[6:0] bits (Device Address) */
mbed_official 545:5112d5ae6723 4543 #define USB_DADDR_ADD0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 545:5112d5ae6723 4544 #define USB_DADDR_ADD1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 545:5112d5ae6723 4545 #define USB_DADDR_ADD2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 545:5112d5ae6723 4546 #define USB_DADDR_ADD3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 545:5112d5ae6723 4547 #define USB_DADDR_ADD4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 545:5112d5ae6723 4548 #define USB_DADDR_ADD5 ((uint32_t)0x00000020) /*!<Bit 5 */
mbed_official 545:5112d5ae6723 4549 #define USB_DADDR_ADD6 ((uint32_t)0x00000040) /*!<Bit 6 */
mbed_official 545:5112d5ae6723 4550
mbed_official 545:5112d5ae6723 4551 #define USB_DADDR_EF ((uint32_t)0x00000080) /*!<Enable Function */
mbed_official 545:5112d5ae6723 4552
mbed_official 545:5112d5ae6723 4553 /****************** Bit definition for USB_BTABLE register ******************/
mbed_official 545:5112d5ae6723 4554 #define USB_BTABLE_BTABLE ((uint32_t)0x0000FFF8) /*!<Buffer Table */
mbed_official 545:5112d5ae6723 4555
mbed_official 545:5112d5ae6723 4556 /*!< Buffer descriptor table */
mbed_official 545:5112d5ae6723 4557 /***************** Bit definition for USB_ADDR0_TX register *****************/
mbed_official 545:5112d5ae6723 4558 #define USB_ADDR0_TX_ADDR0_TX ((uint32_t)0x0000FFFE) /*!< Transmission Buffer Address 0 */
mbed_official 545:5112d5ae6723 4559
mbed_official 545:5112d5ae6723 4560 /***************** Bit definition for USB_ADDR1_TX register *****************/
mbed_official 545:5112d5ae6723 4561 #define USB_ADDR1_TX_ADDR1_TX ((uint32_t)0x0000FFFE) /*!< Transmission Buffer Address 1 */
mbed_official 545:5112d5ae6723 4562
mbed_official 545:5112d5ae6723 4563 /***************** Bit definition for USB_ADDR2_TX register *****************/
mbed_official 545:5112d5ae6723 4564 #define USB_ADDR2_TX_ADDR2_TX ((uint32_t)0x0000FFFE) /*!< Transmission Buffer Address 2 */
mbed_official 545:5112d5ae6723 4565
mbed_official 545:5112d5ae6723 4566 /***************** Bit definition for USB_ADDR3_TX register *****************/
mbed_official 545:5112d5ae6723 4567 #define USB_ADDR3_TX_ADDR3_TX ((uint32_t)0x0000FFFE) /*!< Transmission Buffer Address 3 */
mbed_official 545:5112d5ae6723 4568
mbed_official 545:5112d5ae6723 4569 /***************** Bit definition for USB_ADDR4_TX register *****************/
mbed_official 545:5112d5ae6723 4570 #define USB_ADDR4_TX_ADDR4_TX ((uint32_t)0x0000FFFE) /*!< Transmission Buffer Address 4 */
mbed_official 545:5112d5ae6723 4571
mbed_official 545:5112d5ae6723 4572 /***************** Bit definition for USB_ADDR5_TX register *****************/
mbed_official 545:5112d5ae6723 4573 #define USB_ADDR5_TX_ADDR5_TX ((uint32_t)0x0000FFFE) /*!< Transmission Buffer Address 5 */
mbed_official 545:5112d5ae6723 4574
mbed_official 545:5112d5ae6723 4575 /***************** Bit definition for USB_ADDR6_TX register *****************/
mbed_official 545:5112d5ae6723 4576 #define USB_ADDR6_TX_ADDR6_TX ((uint32_t)0x0000FFFE) /*!< Transmission Buffer Address 6 */
mbed_official 545:5112d5ae6723 4577
mbed_official 545:5112d5ae6723 4578 /***************** Bit definition for USB_ADDR7_TX register *****************/
mbed_official 545:5112d5ae6723 4579 #define USB_ADDR7_TX_ADDR7_TX ((uint32_t)0x0000FFFE) /*!< Transmission Buffer Address 7 */
mbed_official 545:5112d5ae6723 4580
mbed_official 545:5112d5ae6723 4581 /*----------------------------------------------------------------------------*/
mbed_official 545:5112d5ae6723 4582
mbed_official 545:5112d5ae6723 4583 /***************** Bit definition for USB_COUNT0_TX register ****************/
mbed_official 545:5112d5ae6723 4584 #define USB_COUNT0_TX_COUNT0_TX ((uint32_t)0x000003FF) /*!< Transmission Byte Count 0 */
mbed_official 545:5112d5ae6723 4585
mbed_official 545:5112d5ae6723 4586 /***************** Bit definition for USB_COUNT1_TX register ****************/
mbed_official 545:5112d5ae6723 4587 #define USB_COUNT1_TX_COUNT1_TX ((uint32_t)0x000003FF) /*!< Transmission Byte Count 1 */
mbed_official 545:5112d5ae6723 4588
mbed_official 545:5112d5ae6723 4589 /***************** Bit definition for USB_COUNT2_TX register ****************/
mbed_official 545:5112d5ae6723 4590 #define USB_COUNT2_TX_COUNT2_TX ((uint32_t)0x000003FF) /*!< Transmission Byte Count 2 */
mbed_official 545:5112d5ae6723 4591
mbed_official 545:5112d5ae6723 4592 /***************** Bit definition for USB_COUNT3_TX register ****************/
mbed_official 545:5112d5ae6723 4593 #define USB_COUNT3_TX_COUNT3_TX ((uint32_t)0x000003FF) /*!< Transmission Byte Count 3 */
mbed_official 545:5112d5ae6723 4594
mbed_official 545:5112d5ae6723 4595 /***************** Bit definition for USB_COUNT4_TX register ****************/
mbed_official 545:5112d5ae6723 4596 #define USB_COUNT4_TX_COUNT4_TX ((uint32_t)0x000003FF) /*!< Transmission Byte Count 4 */
mbed_official 545:5112d5ae6723 4597
mbed_official 545:5112d5ae6723 4598 /***************** Bit definition for USB_COUNT5_TX register ****************/
mbed_official 545:5112d5ae6723 4599 #define USB_COUNT5_TX_COUNT5_TX ((uint32_t)0x000003FF) /*!< Transmission Byte Count 5 */
mbed_official 545:5112d5ae6723 4600
mbed_official 545:5112d5ae6723 4601 /***************** Bit definition for USB_COUNT6_TX register ****************/
mbed_official 545:5112d5ae6723 4602 #define USB_COUNT6_TX_COUNT6_TX ((uint32_t)0x000003FF) /*!< Transmission Byte Count 6 */
mbed_official 545:5112d5ae6723 4603
mbed_official 545:5112d5ae6723 4604 /***************** Bit definition for USB_COUNT7_TX register ****************/
mbed_official 545:5112d5ae6723 4605 #define USB_COUNT7_TX_COUNT7_TX ((uint32_t)0x000003FF) /*!< Transmission Byte Count 7 */
mbed_official 545:5112d5ae6723 4606
mbed_official 545:5112d5ae6723 4607 /*----------------------------------------------------------------------------*/
mbed_official 545:5112d5ae6723 4608
mbed_official 545:5112d5ae6723 4609 /**************** Bit definition for USB_COUNT0_TX_0 register ***************/
mbed_official 545:5112d5ae6723 4610 #define USB_COUNT0_TX_0_COUNT0_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 0 (low) */
mbed_official 545:5112d5ae6723 4611
mbed_official 545:5112d5ae6723 4612 /**************** Bit definition for USB_COUNT0_TX_1 register ***************/
mbed_official 545:5112d5ae6723 4613 #define USB_COUNT0_TX_1_COUNT0_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 0 (high) */
mbed_official 545:5112d5ae6723 4614
mbed_official 545:5112d5ae6723 4615 /**************** Bit definition for USB_COUNT1_TX_0 register ***************/
mbed_official 545:5112d5ae6723 4616 #define USB_COUNT1_TX_0_COUNT1_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 1 (low) */
mbed_official 545:5112d5ae6723 4617
mbed_official 545:5112d5ae6723 4618 /**************** Bit definition for USB_COUNT1_TX_1 register ***************/
mbed_official 545:5112d5ae6723 4619 #define USB_COUNT1_TX_1_COUNT1_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 1 (high) */
mbed_official 545:5112d5ae6723 4620
mbed_official 545:5112d5ae6723 4621 /**************** Bit definition for USB_COUNT2_TX_0 register ***************/
mbed_official 545:5112d5ae6723 4622 #define USB_COUNT2_TX_0_COUNT2_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 2 (low) */
mbed_official 545:5112d5ae6723 4623
mbed_official 545:5112d5ae6723 4624 /**************** Bit definition for USB_COUNT2_TX_1 register ***************/
mbed_official 545:5112d5ae6723 4625 #define USB_COUNT2_TX_1_COUNT2_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 2 (high) */
mbed_official 545:5112d5ae6723 4626
mbed_official 545:5112d5ae6723 4627 /**************** Bit definition for USB_COUNT3_TX_0 register ***************/
mbed_official 545:5112d5ae6723 4628 #define USB_COUNT3_TX_0_COUNT3_TX_0 ((uint32_t)0x0000000003FF) /*!< Transmission Byte Count 3 (low) */
mbed_official 545:5112d5ae6723 4629
mbed_official 545:5112d5ae6723 4630 /**************** Bit definition for USB_COUNT3_TX_1 register ***************/
mbed_official 545:5112d5ae6723 4631 #define USB_COUNT3_TX_1_COUNT3_TX_1 ((uint32_t)0x000003FF0000) /*!< Transmission Byte Count 3 (high) */
mbed_official 545:5112d5ae6723 4632
mbed_official 545:5112d5ae6723 4633 /**************** Bit definition for USB_COUNT4_TX_0 register ***************/
mbed_official 545:5112d5ae6723 4634 #define USB_COUNT4_TX_0_COUNT4_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 4 (low) */
mbed_official 545:5112d5ae6723 4635
mbed_official 545:5112d5ae6723 4636 /**************** Bit definition for USB_COUNT4_TX_1 register ***************/
mbed_official 545:5112d5ae6723 4637 #define USB_COUNT4_TX_1_COUNT4_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 4 (high) */
mbed_official 545:5112d5ae6723 4638
mbed_official 545:5112d5ae6723 4639 /**************** Bit definition for USB_COUNT5_TX_0 register ***************/
mbed_official 545:5112d5ae6723 4640 #define USB_COUNT5_TX_0_COUNT5_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 5 (low) */
mbed_official 545:5112d5ae6723 4641
mbed_official 545:5112d5ae6723 4642 /**************** Bit definition for USB_COUNT5_TX_1 register ***************/
mbed_official 545:5112d5ae6723 4643 #define USB_COUNT5_TX_1_COUNT5_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 5 (high) */
mbed_official 545:5112d5ae6723 4644
mbed_official 545:5112d5ae6723 4645 /**************** Bit definition for USB_COUNT6_TX_0 register ***************/
mbed_official 545:5112d5ae6723 4646 #define USB_COUNT6_TX_0_COUNT6_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 6 (low) */
mbed_official 545:5112d5ae6723 4647
mbed_official 545:5112d5ae6723 4648 /**************** Bit definition for USB_COUNT6_TX_1 register ***************/
mbed_official 545:5112d5ae6723 4649 #define USB_COUNT6_TX_1_COUNT6_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 6 (high) */
mbed_official 545:5112d5ae6723 4650
mbed_official 545:5112d5ae6723 4651 /**************** Bit definition for USB_COUNT7_TX_0 register ***************/
mbed_official 545:5112d5ae6723 4652 #define USB_COUNT7_TX_0_COUNT7_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 7 (low) */
mbed_official 545:5112d5ae6723 4653
mbed_official 545:5112d5ae6723 4654 /**************** Bit definition for USB_COUNT7_TX_1 register ***************/
mbed_official 545:5112d5ae6723 4655 #define USB_COUNT7_TX_1_COUNT7_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 7 (high) */
mbed_official 545:5112d5ae6723 4656
mbed_official 545:5112d5ae6723 4657 /*----------------------------------------------------------------------------*/
mbed_official 545:5112d5ae6723 4658
mbed_official 545:5112d5ae6723 4659 /***************** Bit definition for USB_ADDR0_RX register *****************/
mbed_official 545:5112d5ae6723 4660 #define USB_ADDR0_RX_ADDR0_RX ((uint32_t)0x0000FFFE) /*!< Reception Buffer Address 0 */
mbed_official 545:5112d5ae6723 4661
mbed_official 545:5112d5ae6723 4662 /***************** Bit definition for USB_ADDR1_RX register *****************/
mbed_official 545:5112d5ae6723 4663 #define USB_ADDR1_RX_ADDR1_RX ((uint32_t)0x0000FFFE) /*!< Reception Buffer Address 1 */
mbed_official 545:5112d5ae6723 4664
mbed_official 545:5112d5ae6723 4665 /***************** Bit definition for USB_ADDR2_RX register *****************/
mbed_official 545:5112d5ae6723 4666 #define USB_ADDR2_RX_ADDR2_RX ((uint32_t)0x0000FFFE) /*!< Reception Buffer Address 2 */
mbed_official 545:5112d5ae6723 4667
mbed_official 545:5112d5ae6723 4668 /***************** Bit definition for USB_ADDR3_RX register *****************/
mbed_official 545:5112d5ae6723 4669 #define USB_ADDR3_RX_ADDR3_RX ((uint32_t)0x0000FFFE) /*!< Reception Buffer Address 3 */
mbed_official 545:5112d5ae6723 4670
mbed_official 545:5112d5ae6723 4671 /***************** Bit definition for USB_ADDR4_RX register *****************/
mbed_official 545:5112d5ae6723 4672 #define USB_ADDR4_RX_ADDR4_RX ((uint32_t)0x0000FFFE) /*!< Reception Buffer Address 4 */
mbed_official 545:5112d5ae6723 4673
mbed_official 545:5112d5ae6723 4674 /***************** Bit definition for USB_ADDR5_RX register *****************/
mbed_official 545:5112d5ae6723 4675 #define USB_ADDR5_RX_ADDR5_RX ((uint32_t)0x0000FFFE) /*!< Reception Buffer Address 5 */
mbed_official 545:5112d5ae6723 4676
mbed_official 545:5112d5ae6723 4677 /***************** Bit definition for USB_ADDR6_RX register *****************/
mbed_official 545:5112d5ae6723 4678 #define USB_ADDR6_RX_ADDR6_RX ((uint32_t)0x0000FFFE) /*!< Reception Buffer Address 6 */
mbed_official 545:5112d5ae6723 4679
mbed_official 545:5112d5ae6723 4680 /***************** Bit definition for USB_ADDR7_RX register *****************/
mbed_official 545:5112d5ae6723 4681 #define USB_ADDR7_RX_ADDR7_RX ((uint32_t)0x0000FFFE) /*!< Reception Buffer Address 7 */
mbed_official 545:5112d5ae6723 4682
mbed_official 545:5112d5ae6723 4683 /*----------------------------------------------------------------------------*/
mbed_official 545:5112d5ae6723 4684
mbed_official 545:5112d5ae6723 4685 /***************** Bit definition for USB_COUNT0_RX register ****************/
mbed_official 545:5112d5ae6723 4686 #define USB_COUNT0_RX_COUNT0_RX ((uint32_t)0x000003FF) /*!< Reception Byte Count */
mbed_official 545:5112d5ae6723 4687
mbed_official 545:5112d5ae6723 4688 #define USB_COUNT0_RX_NUM_BLOCK ((uint32_t)0x00007C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
mbed_official 545:5112d5ae6723 4689 #define USB_COUNT0_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 4690 #define USB_COUNT0_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 4691 #define USB_COUNT0_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 4692 #define USB_COUNT0_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) /*!< Bit 3 */
mbed_official 545:5112d5ae6723 4693 #define USB_COUNT0_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) /*!< Bit 4 */
mbed_official 545:5112d5ae6723 4694
mbed_official 545:5112d5ae6723 4695 #define USB_COUNT0_RX_BLSIZE ((uint32_t)0x00008000) /*!< BLock SIZE */
mbed_official 545:5112d5ae6723 4696
mbed_official 545:5112d5ae6723 4697 /***************** Bit definition for USB_COUNT1_RX register ****************/
mbed_official 545:5112d5ae6723 4698 #define USB_COUNT1_RX_COUNT1_RX ((uint32_t)0x000003FF) /*!< Reception Byte Count */
mbed_official 545:5112d5ae6723 4699
mbed_official 545:5112d5ae6723 4700 #define USB_COUNT1_RX_NUM_BLOCK ((uint32_t)0x00007C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
mbed_official 545:5112d5ae6723 4701 #define USB_COUNT1_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 4702 #define USB_COUNT1_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 4703 #define USB_COUNT1_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 4704 #define USB_COUNT1_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) /*!< Bit 3 */
mbed_official 545:5112d5ae6723 4705 #define USB_COUNT1_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) /*!< Bit 4 */
mbed_official 545:5112d5ae6723 4706
mbed_official 545:5112d5ae6723 4707 #define USB_COUNT1_RX_BLSIZE ((uint32_t)0x00008000) /*!< BLock SIZE */
mbed_official 545:5112d5ae6723 4708
mbed_official 545:5112d5ae6723 4709 /***************** Bit definition for USB_COUNT2_RX register ****************/
mbed_official 545:5112d5ae6723 4710 #define USB_COUNT2_RX_COUNT2_RX ((uint32_t)0x000003FF) /*!< Reception Byte Count */
mbed_official 545:5112d5ae6723 4711
mbed_official 545:5112d5ae6723 4712 #define USB_COUNT2_RX_NUM_BLOCK ((uint32_t)0x00007C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
mbed_official 545:5112d5ae6723 4713 #define USB_COUNT2_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 4714 #define USB_COUNT2_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 4715 #define USB_COUNT2_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 4716 #define USB_COUNT2_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) /*!< Bit 3 */
mbed_official 545:5112d5ae6723 4717 #define USB_COUNT2_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) /*!< Bit 4 */
mbed_official 545:5112d5ae6723 4718
mbed_official 545:5112d5ae6723 4719 #define USB_COUNT2_RX_BLSIZE ((uint32_t)0x00008000) /*!< BLock SIZE */
mbed_official 545:5112d5ae6723 4720
mbed_official 545:5112d5ae6723 4721 /***************** Bit definition for USB_COUNT3_RX register ****************/
mbed_official 545:5112d5ae6723 4722 #define USB_COUNT3_RX_COUNT3_RX ((uint32_t)0x000003FF) /*!< Reception Byte Count */
mbed_official 545:5112d5ae6723 4723
mbed_official 545:5112d5ae6723 4724 #define USB_COUNT3_RX_NUM_BLOCK ((uint32_t)0x00007C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
mbed_official 545:5112d5ae6723 4725 #define USB_COUNT3_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 4726 #define USB_COUNT3_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 4727 #define USB_COUNT3_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 4728 #define USB_COUNT3_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) /*!< Bit 3 */
mbed_official 545:5112d5ae6723 4729 #define USB_COUNT3_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) /*!< Bit 4 */
mbed_official 545:5112d5ae6723 4730
mbed_official 545:5112d5ae6723 4731 #define USB_COUNT3_RX_BLSIZE ((uint32_t)0x00008000) /*!< BLock SIZE */
mbed_official 545:5112d5ae6723 4732
mbed_official 545:5112d5ae6723 4733 /***************** Bit definition for USB_COUNT4_RX register ****************/
mbed_official 545:5112d5ae6723 4734 #define USB_COUNT4_RX_COUNT4_RX ((uint32_t)0x000003FF) /*!< Reception Byte Count */
mbed_official 545:5112d5ae6723 4735
mbed_official 545:5112d5ae6723 4736 #define USB_COUNT4_RX_NUM_BLOCK ((uint32_t)0x00007C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
mbed_official 545:5112d5ae6723 4737 #define USB_COUNT4_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 4738 #define USB_COUNT4_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 4739 #define USB_COUNT4_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 4740 #define USB_COUNT4_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) /*!< Bit 3 */
mbed_official 545:5112d5ae6723 4741 #define USB_COUNT4_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) /*!< Bit 4 */
mbed_official 545:5112d5ae6723 4742
mbed_official 545:5112d5ae6723 4743 #define USB_COUNT4_RX_BLSIZE ((uint32_t)0x00008000) /*!< BLock SIZE */
mbed_official 545:5112d5ae6723 4744
mbed_official 545:5112d5ae6723 4745 /***************** Bit definition for USB_COUNT5_RX register ****************/
mbed_official 545:5112d5ae6723 4746 #define USB_COUNT5_RX_COUNT5_RX ((uint32_t)0x000003FF) /*!< Reception Byte Count */
mbed_official 545:5112d5ae6723 4747
mbed_official 545:5112d5ae6723 4748 #define USB_COUNT5_RX_NUM_BLOCK ((uint32_t)0x00007C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
mbed_official 545:5112d5ae6723 4749 #define USB_COUNT5_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 4750 #define USB_COUNT5_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 4751 #define USB_COUNT5_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 4752 #define USB_COUNT5_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) /*!< Bit 3 */
mbed_official 545:5112d5ae6723 4753 #define USB_COUNT5_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) /*!< Bit 4 */
mbed_official 545:5112d5ae6723 4754
mbed_official 545:5112d5ae6723 4755 #define USB_COUNT5_RX_BLSIZE ((uint32_t)0x00008000) /*!< BLock SIZE */
mbed_official 545:5112d5ae6723 4756
mbed_official 545:5112d5ae6723 4757 /***************** Bit definition for USB_COUNT6_RX register ****************/
mbed_official 545:5112d5ae6723 4758 #define USB_COUNT6_RX_COUNT6_RX ((uint32_t)0x000003FF) /*!< Reception Byte Count */
mbed_official 545:5112d5ae6723 4759
mbed_official 545:5112d5ae6723 4760 #define USB_COUNT6_RX_NUM_BLOCK ((uint32_t)0x00007C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
mbed_official 545:5112d5ae6723 4761 #define USB_COUNT6_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 4762 #define USB_COUNT6_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 4763 #define USB_COUNT6_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 4764 #define USB_COUNT6_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) /*!< Bit 3 */
mbed_official 545:5112d5ae6723 4765 #define USB_COUNT6_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) /*!< Bit 4 */
mbed_official 545:5112d5ae6723 4766
mbed_official 545:5112d5ae6723 4767 #define USB_COUNT6_RX_BLSIZE ((uint32_t)0x00008000) /*!< BLock SIZE */
mbed_official 545:5112d5ae6723 4768
mbed_official 545:5112d5ae6723 4769 /***************** Bit definition for USB_COUNT7_RX register ****************/
mbed_official 545:5112d5ae6723 4770 #define USB_COUNT7_RX_COUNT7_RX ((uint32_t)0x000003FF) /*!< Reception Byte Count */
mbed_official 545:5112d5ae6723 4771
mbed_official 545:5112d5ae6723 4772 #define USB_COUNT7_RX_NUM_BLOCK ((uint32_t)0x00007C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
mbed_official 545:5112d5ae6723 4773 #define USB_COUNT7_RX_NUM_BLOCK_0 ((uint32_t)0x00000400) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 4774 #define USB_COUNT7_RX_NUM_BLOCK_1 ((uint32_t)0x00000800) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 4775 #define USB_COUNT7_RX_NUM_BLOCK_2 ((uint32_t)0x00001000) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 4776 #define USB_COUNT7_RX_NUM_BLOCK_3 ((uint32_t)0x00002000) /*!< Bit 3 */
mbed_official 545:5112d5ae6723 4777 #define USB_COUNT7_RX_NUM_BLOCK_4 ((uint32_t)0x00004000) /*!< Bit 4 */
mbed_official 545:5112d5ae6723 4778
mbed_official 545:5112d5ae6723 4779 #define USB_COUNT7_RX_BLSIZE ((uint32_t)0x00008000) /*!< BLock SIZE */
mbed_official 545:5112d5ae6723 4780
mbed_official 545:5112d5ae6723 4781 /*----------------------------------------------------------------------------*/
mbed_official 545:5112d5ae6723 4782
mbed_official 545:5112d5ae6723 4783 /**************** Bit definition for USB_COUNT0_RX_0 register ***************/
mbed_official 545:5112d5ae6723 4784 #define USB_COUNT0_RX_0_COUNT0_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
mbed_official 545:5112d5ae6723 4785
mbed_official 545:5112d5ae6723 4786 #define USB_COUNT0_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
mbed_official 545:5112d5ae6723 4787 #define USB_COUNT0_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 4788 #define USB_COUNT0_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 4789 #define USB_COUNT0_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 4790 #define USB_COUNT0_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
mbed_official 545:5112d5ae6723 4791 #define USB_COUNT0_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
mbed_official 545:5112d5ae6723 4792
mbed_official 545:5112d5ae6723 4793 #define USB_COUNT0_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
mbed_official 545:5112d5ae6723 4794
mbed_official 545:5112d5ae6723 4795 /**************** Bit definition for USB_COUNT0_RX_1 register ***************/
mbed_official 545:5112d5ae6723 4796 #define USB_COUNT0_RX_1_COUNT0_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
mbed_official 545:5112d5ae6723 4797
mbed_official 545:5112d5ae6723 4798 #define USB_COUNT0_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
mbed_official 545:5112d5ae6723 4799 #define USB_COUNT0_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 4800 #define USB_COUNT0_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 4801 #define USB_COUNT0_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 4802 #define USB_COUNT0_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
mbed_official 545:5112d5ae6723 4803 #define USB_COUNT0_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
mbed_official 545:5112d5ae6723 4804
mbed_official 545:5112d5ae6723 4805 #define USB_COUNT0_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
mbed_official 545:5112d5ae6723 4806
mbed_official 545:5112d5ae6723 4807 /**************** Bit definition for USB_COUNT1_RX_0 register ***************/
mbed_official 545:5112d5ae6723 4808 #define USB_COUNT1_RX_0_COUNT1_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
mbed_official 545:5112d5ae6723 4809
mbed_official 545:5112d5ae6723 4810 #define USB_COUNT1_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
mbed_official 545:5112d5ae6723 4811 #define USB_COUNT1_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 4812 #define USB_COUNT1_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 4813 #define USB_COUNT1_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 4814 #define USB_COUNT1_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
mbed_official 545:5112d5ae6723 4815 #define USB_COUNT1_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
mbed_official 545:5112d5ae6723 4816
mbed_official 545:5112d5ae6723 4817 #define USB_COUNT1_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
mbed_official 545:5112d5ae6723 4818
mbed_official 545:5112d5ae6723 4819 /**************** Bit definition for USB_COUNT1_RX_1 register ***************/
mbed_official 545:5112d5ae6723 4820 #define USB_COUNT1_RX_1_COUNT1_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
mbed_official 545:5112d5ae6723 4821
mbed_official 545:5112d5ae6723 4822 #define USB_COUNT1_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
mbed_official 545:5112d5ae6723 4823 #define USB_COUNT1_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 4824 #define USB_COUNT1_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 4825 #define USB_COUNT1_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 4826 #define USB_COUNT1_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
mbed_official 545:5112d5ae6723 4827 #define USB_COUNT1_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
mbed_official 545:5112d5ae6723 4828
mbed_official 545:5112d5ae6723 4829 #define USB_COUNT1_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
mbed_official 545:5112d5ae6723 4830
mbed_official 545:5112d5ae6723 4831 /**************** Bit definition for USB_COUNT2_RX_0 register ***************/
mbed_official 545:5112d5ae6723 4832 #define USB_COUNT2_RX_0_COUNT2_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
mbed_official 545:5112d5ae6723 4833
mbed_official 545:5112d5ae6723 4834 #define USB_COUNT2_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
mbed_official 545:5112d5ae6723 4835 #define USB_COUNT2_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 4836 #define USB_COUNT2_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 4837 #define USB_COUNT2_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 4838 #define USB_COUNT2_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
mbed_official 545:5112d5ae6723 4839 #define USB_COUNT2_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
mbed_official 545:5112d5ae6723 4840
mbed_official 545:5112d5ae6723 4841 #define USB_COUNT2_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
mbed_official 545:5112d5ae6723 4842
mbed_official 545:5112d5ae6723 4843 /**************** Bit definition for USB_COUNT2_RX_1 register ***************/
mbed_official 545:5112d5ae6723 4844 #define USB_COUNT2_RX_1_COUNT2_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
mbed_official 545:5112d5ae6723 4845
mbed_official 545:5112d5ae6723 4846 #define USB_COUNT2_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
mbed_official 545:5112d5ae6723 4847 #define USB_COUNT2_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 4848 #define USB_COUNT2_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 4849 #define USB_COUNT2_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 4850 #define USB_COUNT2_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
mbed_official 545:5112d5ae6723 4851 #define USB_COUNT2_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
mbed_official 545:5112d5ae6723 4852
mbed_official 545:5112d5ae6723 4853 #define USB_COUNT2_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
mbed_official 545:5112d5ae6723 4854
mbed_official 545:5112d5ae6723 4855 /**************** Bit definition for USB_COUNT3_RX_0 register ***************/
mbed_official 545:5112d5ae6723 4856 #define USB_COUNT3_RX_0_COUNT3_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
mbed_official 545:5112d5ae6723 4857
mbed_official 545:5112d5ae6723 4858 #define USB_COUNT3_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
mbed_official 545:5112d5ae6723 4859 #define USB_COUNT3_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 4860 #define USB_COUNT3_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 4861 #define USB_COUNT3_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 4862 #define USB_COUNT3_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
mbed_official 545:5112d5ae6723 4863 #define USB_COUNT3_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
mbed_official 545:5112d5ae6723 4864
mbed_official 545:5112d5ae6723 4865 #define USB_COUNT3_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
mbed_official 545:5112d5ae6723 4866
mbed_official 545:5112d5ae6723 4867 /**************** Bit definition for USB_COUNT3_RX_1 register ***************/
mbed_official 545:5112d5ae6723 4868 #define USB_COUNT3_RX_1_COUNT3_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
mbed_official 545:5112d5ae6723 4869
mbed_official 545:5112d5ae6723 4870 #define USB_COUNT3_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
mbed_official 545:5112d5ae6723 4871 #define USB_COUNT3_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 4872 #define USB_COUNT3_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 4873 #define USB_COUNT3_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 4874 #define USB_COUNT3_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
mbed_official 545:5112d5ae6723 4875 #define USB_COUNT3_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
mbed_official 545:5112d5ae6723 4876
mbed_official 545:5112d5ae6723 4877 #define USB_COUNT3_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
mbed_official 545:5112d5ae6723 4878
mbed_official 545:5112d5ae6723 4879 /**************** Bit definition for USB_COUNT4_RX_0 register ***************/
mbed_official 545:5112d5ae6723 4880 #define USB_COUNT4_RX_0_COUNT4_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
mbed_official 545:5112d5ae6723 4881
mbed_official 545:5112d5ae6723 4882 #define USB_COUNT4_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
mbed_official 545:5112d5ae6723 4883 #define USB_COUNT4_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 4884 #define USB_COUNT4_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 4885 #define USB_COUNT4_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 4886 #define USB_COUNT4_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
mbed_official 545:5112d5ae6723 4887 #define USB_COUNT4_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
mbed_official 545:5112d5ae6723 4888
mbed_official 545:5112d5ae6723 4889 #define USB_COUNT4_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
mbed_official 545:5112d5ae6723 4890
mbed_official 545:5112d5ae6723 4891 /**************** Bit definition for USB_COUNT4_RX_1 register ***************/
mbed_official 545:5112d5ae6723 4892 #define USB_COUNT4_RX_1_COUNT4_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
mbed_official 545:5112d5ae6723 4893
mbed_official 545:5112d5ae6723 4894 #define USB_COUNT4_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
mbed_official 545:5112d5ae6723 4895 #define USB_COUNT4_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 4896 #define USB_COUNT4_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 4897 #define USB_COUNT4_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 4898 #define USB_COUNT4_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
mbed_official 545:5112d5ae6723 4899 #define USB_COUNT4_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
mbed_official 545:5112d5ae6723 4900
mbed_official 545:5112d5ae6723 4901 #define USB_COUNT4_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
mbed_official 545:5112d5ae6723 4902
mbed_official 545:5112d5ae6723 4903 /**************** Bit definition for USB_COUNT5_RX_0 register ***************/
mbed_official 545:5112d5ae6723 4904 #define USB_COUNT5_RX_0_COUNT5_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
mbed_official 545:5112d5ae6723 4905
mbed_official 545:5112d5ae6723 4906 #define USB_COUNT5_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
mbed_official 545:5112d5ae6723 4907 #define USB_COUNT5_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 4908 #define USB_COUNT5_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 4909 #define USB_COUNT5_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 4910 #define USB_COUNT5_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
mbed_official 545:5112d5ae6723 4911 #define USB_COUNT5_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
mbed_official 545:5112d5ae6723 4912
mbed_official 545:5112d5ae6723 4913 #define USB_COUNT5_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
mbed_official 545:5112d5ae6723 4914
mbed_official 545:5112d5ae6723 4915 /**************** Bit definition for USB_COUNT5_RX_1 register ***************/
mbed_official 545:5112d5ae6723 4916 #define USB_COUNT5_RX_1_COUNT5_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
mbed_official 545:5112d5ae6723 4917
mbed_official 545:5112d5ae6723 4918 #define USB_COUNT5_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
mbed_official 545:5112d5ae6723 4919 #define USB_COUNT5_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 4920 #define USB_COUNT5_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 4921 #define USB_COUNT5_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 4922 #define USB_COUNT5_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
mbed_official 545:5112d5ae6723 4923 #define USB_COUNT5_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
mbed_official 545:5112d5ae6723 4924
mbed_official 545:5112d5ae6723 4925 #define USB_COUNT5_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
mbed_official 545:5112d5ae6723 4926
mbed_official 545:5112d5ae6723 4927 /*************** Bit definition for USB_COUNT6_RX_0 register ***************/
mbed_official 545:5112d5ae6723 4928 #define USB_COUNT6_RX_0_COUNT6_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
mbed_official 545:5112d5ae6723 4929
mbed_official 545:5112d5ae6723 4930 #define USB_COUNT6_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
mbed_official 545:5112d5ae6723 4931 #define USB_COUNT6_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 4932 #define USB_COUNT6_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 4933 #define USB_COUNT6_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 4934 #define USB_COUNT6_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
mbed_official 545:5112d5ae6723 4935 #define USB_COUNT6_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
mbed_official 545:5112d5ae6723 4936
mbed_official 545:5112d5ae6723 4937 #define USB_COUNT6_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
mbed_official 545:5112d5ae6723 4938
mbed_official 545:5112d5ae6723 4939 /**************** Bit definition for USB_COUNT6_RX_1 register ***************/
mbed_official 545:5112d5ae6723 4940 #define USB_COUNT6_RX_1_COUNT6_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
mbed_official 545:5112d5ae6723 4941
mbed_official 545:5112d5ae6723 4942 #define USB_COUNT6_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
mbed_official 545:5112d5ae6723 4943 #define USB_COUNT6_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 4944 #define USB_COUNT6_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 4945 #define USB_COUNT6_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 4946 #define USB_COUNT6_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
mbed_official 545:5112d5ae6723 4947 #define USB_COUNT6_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
mbed_official 545:5112d5ae6723 4948
mbed_official 545:5112d5ae6723 4949 #define USB_COUNT6_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
mbed_official 545:5112d5ae6723 4950
mbed_official 545:5112d5ae6723 4951 /*************** Bit definition for USB_COUNT7_RX_0 register ****************/
mbed_official 545:5112d5ae6723 4952 #define USB_COUNT7_RX_0_COUNT7_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
mbed_official 545:5112d5ae6723 4953
mbed_official 545:5112d5ae6723 4954 #define USB_COUNT7_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
mbed_official 545:5112d5ae6723 4955 #define USB_COUNT7_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 4956 #define USB_COUNT7_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 4957 #define USB_COUNT7_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 4958 #define USB_COUNT7_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
mbed_official 545:5112d5ae6723 4959 #define USB_COUNT7_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
mbed_official 545:5112d5ae6723 4960
mbed_official 545:5112d5ae6723 4961 #define USB_COUNT7_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
mbed_official 545:5112d5ae6723 4962
mbed_official 545:5112d5ae6723 4963 /*************** Bit definition for USB_COUNT7_RX_1 register ****************/
mbed_official 545:5112d5ae6723 4964 #define USB_COUNT7_RX_1_COUNT7_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
mbed_official 545:5112d5ae6723 4965
mbed_official 545:5112d5ae6723 4966 #define USB_COUNT7_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
mbed_official 545:5112d5ae6723 4967 #define USB_COUNT7_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 4968 #define USB_COUNT7_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 4969 #define USB_COUNT7_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 4970 #define USB_COUNT7_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
mbed_official 545:5112d5ae6723 4971 #define USB_COUNT7_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
mbed_official 545:5112d5ae6723 4972
mbed_official 545:5112d5ae6723 4973 #define USB_COUNT7_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
mbed_official 545:5112d5ae6723 4974
mbed_official 545:5112d5ae6723 4975 /******************************************************************************/
mbed_official 545:5112d5ae6723 4976 /* */
mbed_official 545:5112d5ae6723 4977 /* Window WATCHDOG (WWDG) */
mbed_official 545:5112d5ae6723 4978 /* */
mbed_official 545:5112d5ae6723 4979 /******************************************************************************/
mbed_official 545:5112d5ae6723 4980
mbed_official 545:5112d5ae6723 4981 /******************* Bit definition for WWDG_CR register ********************/
mbed_official 545:5112d5ae6723 4982 #define WWDG_CR_T ((uint32_t)0x0000007F) /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
mbed_official 545:5112d5ae6723 4983 #define WWDG_CR_T0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 4984 #define WWDG_CR_T1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 4985 #define WWDG_CR_T2 ((uint32_t)0x00000004) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 4986 #define WWDG_CR_T3 ((uint32_t)0x00000008) /*!< Bit 3 */
mbed_official 545:5112d5ae6723 4987 #define WWDG_CR_T4 ((uint32_t)0x00000010) /*!< Bit 4 */
mbed_official 545:5112d5ae6723 4988 #define WWDG_CR_T5 ((uint32_t)0x00000020) /*!< Bit 5 */
mbed_official 545:5112d5ae6723 4989 #define WWDG_CR_T6 ((uint32_t)0x00000040) /*!< Bit 6 */
mbed_official 545:5112d5ae6723 4990
mbed_official 545:5112d5ae6723 4991 #define WWDG_CR_WDGA ((uint32_t)0x00000080) /*!< Activation bit */
mbed_official 545:5112d5ae6723 4992
mbed_official 545:5112d5ae6723 4993 /******************* Bit definition for WWDG_CFR register *******************/
mbed_official 545:5112d5ae6723 4994 #define WWDG_CFR_W ((uint32_t)0x0000007F) /*!< W[6:0] bits (7-bit window value) */
mbed_official 545:5112d5ae6723 4995 #define WWDG_CFR_W0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 4996 #define WWDG_CFR_W1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 4997 #define WWDG_CFR_W2 ((uint32_t)0x00000004) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 4998 #define WWDG_CFR_W3 ((uint32_t)0x00000008) /*!< Bit 3 */
mbed_official 545:5112d5ae6723 4999 #define WWDG_CFR_W4 ((uint32_t)0x00000010) /*!< Bit 4 */
mbed_official 545:5112d5ae6723 5000 #define WWDG_CFR_W5 ((uint32_t)0x00000020) /*!< Bit 5 */
mbed_official 545:5112d5ae6723 5001 #define WWDG_CFR_W6 ((uint32_t)0x00000040) /*!< Bit 6 */
mbed_official 545:5112d5ae6723 5002
mbed_official 545:5112d5ae6723 5003 #define WWDG_CFR_WDGTB ((uint32_t)0x00000180) /*!< WDGTB[1:0] bits (Timer Base) */
mbed_official 545:5112d5ae6723 5004 #define WWDG_CFR_WDGTB0 ((uint32_t)0x00000080) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 5005 #define WWDG_CFR_WDGTB1 ((uint32_t)0x00000100) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 5006
mbed_official 545:5112d5ae6723 5007 #define WWDG_CFR_EWI ((uint32_t)0x00000200) /*!< Early Wakeup Interrupt */
mbed_official 545:5112d5ae6723 5008
mbed_official 545:5112d5ae6723 5009 /******************* Bit definition for WWDG_SR register ********************/
mbed_official 545:5112d5ae6723 5010 #define WWDG_SR_EWIF ((uint32_t)0x00000001) /*!< Early Wakeup Interrupt Flag */
mbed_official 545:5112d5ae6723 5011
mbed_official 545:5112d5ae6723 5012 /******************************************************************************/
mbed_official 545:5112d5ae6723 5013 /* */
mbed_official 545:5112d5ae6723 5014 /* SystemTick (SysTick) */
mbed_official 545:5112d5ae6723 5015 /* */
mbed_official 545:5112d5ae6723 5016 /******************************************************************************/
mbed_official 545:5112d5ae6723 5017
mbed_official 545:5112d5ae6723 5018 /***************** Bit definition for SysTick_CTRL register *****************/
mbed_official 545:5112d5ae6723 5019 #define SysTick_CTRL_ENABLE ((uint32_t)0x00000001) /*!< Counter enable */
mbed_official 545:5112d5ae6723 5020 #define SysTick_CTRL_TICKINT ((uint32_t)0x00000002) /*!< Counting down to 0 pends the SysTick handler */
mbed_official 545:5112d5ae6723 5021 #define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) /*!< Clock source */
mbed_official 545:5112d5ae6723 5022 #define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) /*!< Count Flag */
mbed_official 545:5112d5ae6723 5023
mbed_official 545:5112d5ae6723 5024 /***************** Bit definition for SysTick_LOAD register *****************/
mbed_official 545:5112d5ae6723 5025 #define SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */
mbed_official 545:5112d5ae6723 5026
mbed_official 545:5112d5ae6723 5027 /***************** Bit definition for SysTick_VAL register ******************/
mbed_official 545:5112d5ae6723 5028 #define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) /*!< Current value at the time the register is accessed */
mbed_official 545:5112d5ae6723 5029
mbed_official 545:5112d5ae6723 5030 /***************** Bit definition for SysTick_CALIB register ****************/
mbed_official 545:5112d5ae6723 5031 #define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) /*!< Reload value to use for 10ms timing */
mbed_official 545:5112d5ae6723 5032 #define SysTick_CALIB_SKEW ((uint32_t)0x40000000) /*!< Calibration value is not exactly 10 ms */
mbed_official 545:5112d5ae6723 5033 #define SysTick_CALIB_NOREF ((uint32_t)0x80000000) /*!< The reference clock is not provided */
mbed_official 545:5112d5ae6723 5034
mbed_official 545:5112d5ae6723 5035 /******************************************************************************/
mbed_official 545:5112d5ae6723 5036 /* */
mbed_official 545:5112d5ae6723 5037 /* Nested Vectored Interrupt Controller (NVIC) */
mbed_official 545:5112d5ae6723 5038 /* */
mbed_official 545:5112d5ae6723 5039 /******************************************************************************/
mbed_official 545:5112d5ae6723 5040
mbed_official 545:5112d5ae6723 5041 /****************** Bit definition for NVIC_ISER register *******************/
mbed_official 545:5112d5ae6723 5042 #define NVIC_ISER_SETENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt set enable bits */
mbed_official 545:5112d5ae6723 5043 #define NVIC_ISER_SETENA_0 ((uint32_t)0x00000001) /*!< bit 0 */
mbed_official 545:5112d5ae6723 5044 #define NVIC_ISER_SETENA_1 ((uint32_t)0x00000002) /*!< bit 1 */
mbed_official 545:5112d5ae6723 5045 #define NVIC_ISER_SETENA_2 ((uint32_t)0x00000004) /*!< bit 2 */
mbed_official 545:5112d5ae6723 5046 #define NVIC_ISER_SETENA_3 ((uint32_t)0x00000008) /*!< bit 3 */
mbed_official 545:5112d5ae6723 5047 #define NVIC_ISER_SETENA_4 ((uint32_t)0x00000010) /*!< bit 4 */
mbed_official 545:5112d5ae6723 5048 #define NVIC_ISER_SETENA_5 ((uint32_t)0x00000020) /*!< bit 5 */
mbed_official 545:5112d5ae6723 5049 #define NVIC_ISER_SETENA_6 ((uint32_t)0x00000040) /*!< bit 6 */
mbed_official 545:5112d5ae6723 5050 #define NVIC_ISER_SETENA_7 ((uint32_t)0x00000080) /*!< bit 7 */
mbed_official 545:5112d5ae6723 5051 #define NVIC_ISER_SETENA_8 ((uint32_t)0x00000100) /*!< bit 8 */
mbed_official 545:5112d5ae6723 5052 #define NVIC_ISER_SETENA_9 ((uint32_t)0x00000200) /*!< bit 9 */
mbed_official 545:5112d5ae6723 5053 #define NVIC_ISER_SETENA_10 ((uint32_t)0x00000400) /*!< bit 10 */
mbed_official 545:5112d5ae6723 5054 #define NVIC_ISER_SETENA_11 ((uint32_t)0x00000800) /*!< bit 11 */
mbed_official 545:5112d5ae6723 5055 #define NVIC_ISER_SETENA_12 ((uint32_t)0x00001000) /*!< bit 12 */
mbed_official 545:5112d5ae6723 5056 #define NVIC_ISER_SETENA_13 ((uint32_t)0x00002000) /*!< bit 13 */
mbed_official 545:5112d5ae6723 5057 #define NVIC_ISER_SETENA_14 ((uint32_t)0x00004000) /*!< bit 14 */
mbed_official 545:5112d5ae6723 5058 #define NVIC_ISER_SETENA_15 ((uint32_t)0x00008000) /*!< bit 15 */
mbed_official 545:5112d5ae6723 5059 #define NVIC_ISER_SETENA_16 ((uint32_t)0x00010000) /*!< bit 16 */
mbed_official 545:5112d5ae6723 5060 #define NVIC_ISER_SETENA_17 ((uint32_t)0x00020000) /*!< bit 17 */
mbed_official 545:5112d5ae6723 5061 #define NVIC_ISER_SETENA_18 ((uint32_t)0x00040000) /*!< bit 18 */
mbed_official 545:5112d5ae6723 5062 #define NVIC_ISER_SETENA_19 ((uint32_t)0x00080000) /*!< bit 19 */
mbed_official 545:5112d5ae6723 5063 #define NVIC_ISER_SETENA_20 ((uint32_t)0x00100000) /*!< bit 20 */
mbed_official 545:5112d5ae6723 5064 #define NVIC_ISER_SETENA_21 ((uint32_t)0x00200000) /*!< bit 21 */
mbed_official 545:5112d5ae6723 5065 #define NVIC_ISER_SETENA_22 ((uint32_t)0x00400000) /*!< bit 22 */
mbed_official 545:5112d5ae6723 5066 #define NVIC_ISER_SETENA_23 ((uint32_t)0x00800000) /*!< bit 23 */
mbed_official 545:5112d5ae6723 5067 #define NVIC_ISER_SETENA_24 ((uint32_t)0x01000000) /*!< bit 24 */
mbed_official 545:5112d5ae6723 5068 #define NVIC_ISER_SETENA_25 ((uint32_t)0x02000000) /*!< bit 25 */
mbed_official 545:5112d5ae6723 5069 #define NVIC_ISER_SETENA_26 ((uint32_t)0x04000000) /*!< bit 26 */
mbed_official 545:5112d5ae6723 5070 #define NVIC_ISER_SETENA_27 ((uint32_t)0x08000000) /*!< bit 27 */
mbed_official 545:5112d5ae6723 5071 #define NVIC_ISER_SETENA_28 ((uint32_t)0x10000000) /*!< bit 28 */
mbed_official 545:5112d5ae6723 5072 #define NVIC_ISER_SETENA_29 ((uint32_t)0x20000000) /*!< bit 29 */
mbed_official 545:5112d5ae6723 5073 #define NVIC_ISER_SETENA_30 ((uint32_t)0x40000000) /*!< bit 30 */
mbed_official 545:5112d5ae6723 5074 #define NVIC_ISER_SETENA_31 ((uint32_t)0x80000000) /*!< bit 31 */
mbed_official 545:5112d5ae6723 5075
mbed_official 545:5112d5ae6723 5076 /****************** Bit definition for NVIC_ICER register *******************/
mbed_official 545:5112d5ae6723 5077 #define NVIC_ICER_CLRENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-enable bits */
mbed_official 545:5112d5ae6723 5078 #define NVIC_ICER_CLRENA_0 ((uint32_t)0x00000001) /*!< bit 0 */
mbed_official 545:5112d5ae6723 5079 #define NVIC_ICER_CLRENA_1 ((uint32_t)0x00000002) /*!< bit 1 */
mbed_official 545:5112d5ae6723 5080 #define NVIC_ICER_CLRENA_2 ((uint32_t)0x00000004) /*!< bit 2 */
mbed_official 545:5112d5ae6723 5081 #define NVIC_ICER_CLRENA_3 ((uint32_t)0x00000008) /*!< bit 3 */
mbed_official 545:5112d5ae6723 5082 #define NVIC_ICER_CLRENA_4 ((uint32_t)0x00000010) /*!< bit 4 */
mbed_official 545:5112d5ae6723 5083 #define NVIC_ICER_CLRENA_5 ((uint32_t)0x00000020) /*!< bit 5 */
mbed_official 545:5112d5ae6723 5084 #define NVIC_ICER_CLRENA_6 ((uint32_t)0x00000040) /*!< bit 6 */
mbed_official 545:5112d5ae6723 5085 #define NVIC_ICER_CLRENA_7 ((uint32_t)0x00000080) /*!< bit 7 */
mbed_official 545:5112d5ae6723 5086 #define NVIC_ICER_CLRENA_8 ((uint32_t)0x00000100) /*!< bit 8 */
mbed_official 545:5112d5ae6723 5087 #define NVIC_ICER_CLRENA_9 ((uint32_t)0x00000200) /*!< bit 9 */
mbed_official 545:5112d5ae6723 5088 #define NVIC_ICER_CLRENA_10 ((uint32_t)0x00000400) /*!< bit 10 */
mbed_official 545:5112d5ae6723 5089 #define NVIC_ICER_CLRENA_11 ((uint32_t)0x00000800) /*!< bit 11 */
mbed_official 545:5112d5ae6723 5090 #define NVIC_ICER_CLRENA_12 ((uint32_t)0x00001000) /*!< bit 12 */
mbed_official 545:5112d5ae6723 5091 #define NVIC_ICER_CLRENA_13 ((uint32_t)0x00002000) /*!< bit 13 */
mbed_official 545:5112d5ae6723 5092 #define NVIC_ICER_CLRENA_14 ((uint32_t)0x00004000) /*!< bit 14 */
mbed_official 545:5112d5ae6723 5093 #define NVIC_ICER_CLRENA_15 ((uint32_t)0x00008000) /*!< bit 15 */
mbed_official 545:5112d5ae6723 5094 #define NVIC_ICER_CLRENA_16 ((uint32_t)0x00010000) /*!< bit 16 */
mbed_official 545:5112d5ae6723 5095 #define NVIC_ICER_CLRENA_17 ((uint32_t)0x00020000) /*!< bit 17 */
mbed_official 545:5112d5ae6723 5096 #define NVIC_ICER_CLRENA_18 ((uint32_t)0x00040000) /*!< bit 18 */
mbed_official 545:5112d5ae6723 5097 #define NVIC_ICER_CLRENA_19 ((uint32_t)0x00080000) /*!< bit 19 */
mbed_official 545:5112d5ae6723 5098 #define NVIC_ICER_CLRENA_20 ((uint32_t)0x00100000) /*!< bit 20 */
mbed_official 545:5112d5ae6723 5099 #define NVIC_ICER_CLRENA_21 ((uint32_t)0x00200000) /*!< bit 21 */
mbed_official 545:5112d5ae6723 5100 #define NVIC_ICER_CLRENA_22 ((uint32_t)0x00400000) /*!< bit 22 */
mbed_official 545:5112d5ae6723 5101 #define NVIC_ICER_CLRENA_23 ((uint32_t)0x00800000) /*!< bit 23 */
mbed_official 545:5112d5ae6723 5102 #define NVIC_ICER_CLRENA_24 ((uint32_t)0x01000000) /*!< bit 24 */
mbed_official 545:5112d5ae6723 5103 #define NVIC_ICER_CLRENA_25 ((uint32_t)0x02000000) /*!< bit 25 */
mbed_official 545:5112d5ae6723 5104 #define NVIC_ICER_CLRENA_26 ((uint32_t)0x04000000) /*!< bit 26 */
mbed_official 545:5112d5ae6723 5105 #define NVIC_ICER_CLRENA_27 ((uint32_t)0x08000000) /*!< bit 27 */
mbed_official 545:5112d5ae6723 5106 #define NVIC_ICER_CLRENA_28 ((uint32_t)0x10000000) /*!< bit 28 */
mbed_official 545:5112d5ae6723 5107 #define NVIC_ICER_CLRENA_29 ((uint32_t)0x20000000) /*!< bit 29 */
mbed_official 545:5112d5ae6723 5108 #define NVIC_ICER_CLRENA_30 ((uint32_t)0x40000000) /*!< bit 30 */
mbed_official 545:5112d5ae6723 5109 #define NVIC_ICER_CLRENA_31 ((uint32_t)0x80000000) /*!< bit 31 */
mbed_official 545:5112d5ae6723 5110
mbed_official 545:5112d5ae6723 5111 /****************** Bit definition for NVIC_ISPR register *******************/
mbed_official 545:5112d5ae6723 5112 #define NVIC_ISPR_SETPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt set-pending bits */
mbed_official 545:5112d5ae6723 5113 #define NVIC_ISPR_SETPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */
mbed_official 545:5112d5ae6723 5114 #define NVIC_ISPR_SETPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */
mbed_official 545:5112d5ae6723 5115 #define NVIC_ISPR_SETPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */
mbed_official 545:5112d5ae6723 5116 #define NVIC_ISPR_SETPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */
mbed_official 545:5112d5ae6723 5117 #define NVIC_ISPR_SETPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */
mbed_official 545:5112d5ae6723 5118 #define NVIC_ISPR_SETPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */
mbed_official 545:5112d5ae6723 5119 #define NVIC_ISPR_SETPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */
mbed_official 545:5112d5ae6723 5120 #define NVIC_ISPR_SETPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */
mbed_official 545:5112d5ae6723 5121 #define NVIC_ISPR_SETPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */
mbed_official 545:5112d5ae6723 5122 #define NVIC_ISPR_SETPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */
mbed_official 545:5112d5ae6723 5123 #define NVIC_ISPR_SETPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */
mbed_official 545:5112d5ae6723 5124 #define NVIC_ISPR_SETPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */
mbed_official 545:5112d5ae6723 5125 #define NVIC_ISPR_SETPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */
mbed_official 545:5112d5ae6723 5126 #define NVIC_ISPR_SETPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */
mbed_official 545:5112d5ae6723 5127 #define NVIC_ISPR_SETPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */
mbed_official 545:5112d5ae6723 5128 #define NVIC_ISPR_SETPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */
mbed_official 545:5112d5ae6723 5129 #define NVIC_ISPR_SETPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */
mbed_official 545:5112d5ae6723 5130 #define NVIC_ISPR_SETPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */
mbed_official 545:5112d5ae6723 5131 #define NVIC_ISPR_SETPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */
mbed_official 545:5112d5ae6723 5132 #define NVIC_ISPR_SETPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */
mbed_official 545:5112d5ae6723 5133 #define NVIC_ISPR_SETPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */
mbed_official 545:5112d5ae6723 5134 #define NVIC_ISPR_SETPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */
mbed_official 545:5112d5ae6723 5135 #define NVIC_ISPR_SETPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */
mbed_official 545:5112d5ae6723 5136 #define NVIC_ISPR_SETPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */
mbed_official 545:5112d5ae6723 5137 #define NVIC_ISPR_SETPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */
mbed_official 545:5112d5ae6723 5138 #define NVIC_ISPR_SETPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */
mbed_official 545:5112d5ae6723 5139 #define NVIC_ISPR_SETPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */
mbed_official 545:5112d5ae6723 5140 #define NVIC_ISPR_SETPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */
mbed_official 545:5112d5ae6723 5141 #define NVIC_ISPR_SETPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */
mbed_official 545:5112d5ae6723 5142 #define NVIC_ISPR_SETPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */
mbed_official 545:5112d5ae6723 5143 #define NVIC_ISPR_SETPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */
mbed_official 545:5112d5ae6723 5144 #define NVIC_ISPR_SETPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */
mbed_official 545:5112d5ae6723 5145
mbed_official 545:5112d5ae6723 5146 /****************** Bit definition for NVIC_ICPR register *******************/
mbed_official 545:5112d5ae6723 5147 #define NVIC_ICPR_CLRPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-pending bits */
mbed_official 545:5112d5ae6723 5148 #define NVIC_ICPR_CLRPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */
mbed_official 545:5112d5ae6723 5149 #define NVIC_ICPR_CLRPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */
mbed_official 545:5112d5ae6723 5150 #define NVIC_ICPR_CLRPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */
mbed_official 545:5112d5ae6723 5151 #define NVIC_ICPR_CLRPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */
mbed_official 545:5112d5ae6723 5152 #define NVIC_ICPR_CLRPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */
mbed_official 545:5112d5ae6723 5153 #define NVIC_ICPR_CLRPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */
mbed_official 545:5112d5ae6723 5154 #define NVIC_ICPR_CLRPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */
mbed_official 545:5112d5ae6723 5155 #define NVIC_ICPR_CLRPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */
mbed_official 545:5112d5ae6723 5156 #define NVIC_ICPR_CLRPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */
mbed_official 545:5112d5ae6723 5157 #define NVIC_ICPR_CLRPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */
mbed_official 545:5112d5ae6723 5158 #define NVIC_ICPR_CLRPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */
mbed_official 545:5112d5ae6723 5159 #define NVIC_ICPR_CLRPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */
mbed_official 545:5112d5ae6723 5160 #define NVIC_ICPR_CLRPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */
mbed_official 545:5112d5ae6723 5161 #define NVIC_ICPR_CLRPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */
mbed_official 545:5112d5ae6723 5162 #define NVIC_ICPR_CLRPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */
mbed_official 545:5112d5ae6723 5163 #define NVIC_ICPR_CLRPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */
mbed_official 545:5112d5ae6723 5164 #define NVIC_ICPR_CLRPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */
mbed_official 545:5112d5ae6723 5165 #define NVIC_ICPR_CLRPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */
mbed_official 545:5112d5ae6723 5166 #define NVIC_ICPR_CLRPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */
mbed_official 545:5112d5ae6723 5167 #define NVIC_ICPR_CLRPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */
mbed_official 545:5112d5ae6723 5168 #define NVIC_ICPR_CLRPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */
mbed_official 545:5112d5ae6723 5169 #define NVIC_ICPR_CLRPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */
mbed_official 545:5112d5ae6723 5170 #define NVIC_ICPR_CLRPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */
mbed_official 545:5112d5ae6723 5171 #define NVIC_ICPR_CLRPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */
mbed_official 545:5112d5ae6723 5172 #define NVIC_ICPR_CLRPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */
mbed_official 545:5112d5ae6723 5173 #define NVIC_ICPR_CLRPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */
mbed_official 545:5112d5ae6723 5174 #define NVIC_ICPR_CLRPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */
mbed_official 545:5112d5ae6723 5175 #define NVIC_ICPR_CLRPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */
mbed_official 545:5112d5ae6723 5176 #define NVIC_ICPR_CLRPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */
mbed_official 545:5112d5ae6723 5177 #define NVIC_ICPR_CLRPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */
mbed_official 545:5112d5ae6723 5178 #define NVIC_ICPR_CLRPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */
mbed_official 545:5112d5ae6723 5179 #define NVIC_ICPR_CLRPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */
mbed_official 545:5112d5ae6723 5180
mbed_official 545:5112d5ae6723 5181 /****************** Bit definition for NVIC_IABR register *******************/
mbed_official 545:5112d5ae6723 5182 #define NVIC_IABR_ACTIVE ((uint32_t)0xFFFFFFFF) /*!< Interrupt active flags */
mbed_official 545:5112d5ae6723 5183 #define NVIC_IABR_ACTIVE_0 ((uint32_t)0x00000001) /*!< bit 0 */
mbed_official 545:5112d5ae6723 5184 #define NVIC_IABR_ACTIVE_1 ((uint32_t)0x00000002) /*!< bit 1 */
mbed_official 545:5112d5ae6723 5185 #define NVIC_IABR_ACTIVE_2 ((uint32_t)0x00000004) /*!< bit 2 */
mbed_official 545:5112d5ae6723 5186 #define NVIC_IABR_ACTIVE_3 ((uint32_t)0x00000008) /*!< bit 3 */
mbed_official 545:5112d5ae6723 5187 #define NVIC_IABR_ACTIVE_4 ((uint32_t)0x00000010) /*!< bit 4 */
mbed_official 545:5112d5ae6723 5188 #define NVIC_IABR_ACTIVE_5 ((uint32_t)0x00000020) /*!< bit 5 */
mbed_official 545:5112d5ae6723 5189 #define NVIC_IABR_ACTIVE_6 ((uint32_t)0x00000040) /*!< bit 6 */
mbed_official 545:5112d5ae6723 5190 #define NVIC_IABR_ACTIVE_7 ((uint32_t)0x00000080) /*!< bit 7 */
mbed_official 545:5112d5ae6723 5191 #define NVIC_IABR_ACTIVE_8 ((uint32_t)0x00000100) /*!< bit 8 */
mbed_official 545:5112d5ae6723 5192 #define NVIC_IABR_ACTIVE_9 ((uint32_t)0x00000200) /*!< bit 9 */
mbed_official 545:5112d5ae6723 5193 #define NVIC_IABR_ACTIVE_10 ((uint32_t)0x00000400) /*!< bit 10 */
mbed_official 545:5112d5ae6723 5194 #define NVIC_IABR_ACTIVE_11 ((uint32_t)0x00000800) /*!< bit 11 */
mbed_official 545:5112d5ae6723 5195 #define NVIC_IABR_ACTIVE_12 ((uint32_t)0x00001000) /*!< bit 12 */
mbed_official 545:5112d5ae6723 5196 #define NVIC_IABR_ACTIVE_13 ((uint32_t)0x00002000) /*!< bit 13 */
mbed_official 545:5112d5ae6723 5197 #define NVIC_IABR_ACTIVE_14 ((uint32_t)0x00004000) /*!< bit 14 */
mbed_official 545:5112d5ae6723 5198 #define NVIC_IABR_ACTIVE_15 ((uint32_t)0x00008000) /*!< bit 15 */
mbed_official 545:5112d5ae6723 5199 #define NVIC_IABR_ACTIVE_16 ((uint32_t)0x00010000) /*!< bit 16 */
mbed_official 545:5112d5ae6723 5200 #define NVIC_IABR_ACTIVE_17 ((uint32_t)0x00020000) /*!< bit 17 */
mbed_official 545:5112d5ae6723 5201 #define NVIC_IABR_ACTIVE_18 ((uint32_t)0x00040000) /*!< bit 18 */
mbed_official 545:5112d5ae6723 5202 #define NVIC_IABR_ACTIVE_19 ((uint32_t)0x00080000) /*!< bit 19 */
mbed_official 545:5112d5ae6723 5203 #define NVIC_IABR_ACTIVE_20 ((uint32_t)0x00100000) /*!< bit 20 */
mbed_official 545:5112d5ae6723 5204 #define NVIC_IABR_ACTIVE_21 ((uint32_t)0x00200000) /*!< bit 21 */
mbed_official 545:5112d5ae6723 5205 #define NVIC_IABR_ACTIVE_22 ((uint32_t)0x00400000) /*!< bit 22 */
mbed_official 545:5112d5ae6723 5206 #define NVIC_IABR_ACTIVE_23 ((uint32_t)0x00800000) /*!< bit 23 */
mbed_official 545:5112d5ae6723 5207 #define NVIC_IABR_ACTIVE_24 ((uint32_t)0x01000000) /*!< bit 24 */
mbed_official 545:5112d5ae6723 5208 #define NVIC_IABR_ACTIVE_25 ((uint32_t)0x02000000) /*!< bit 25 */
mbed_official 545:5112d5ae6723 5209 #define NVIC_IABR_ACTIVE_26 ((uint32_t)0x04000000) /*!< bit 26 */
mbed_official 545:5112d5ae6723 5210 #define NVIC_IABR_ACTIVE_27 ((uint32_t)0x08000000) /*!< bit 27 */
mbed_official 545:5112d5ae6723 5211 #define NVIC_IABR_ACTIVE_28 ((uint32_t)0x10000000) /*!< bit 28 */
mbed_official 545:5112d5ae6723 5212 #define NVIC_IABR_ACTIVE_29 ((uint32_t)0x20000000) /*!< bit 29 */
mbed_official 545:5112d5ae6723 5213 #define NVIC_IABR_ACTIVE_30 ((uint32_t)0x40000000) /*!< bit 30 */
mbed_official 545:5112d5ae6723 5214 #define NVIC_IABR_ACTIVE_31 ((uint32_t)0x80000000) /*!< bit 31 */
mbed_official 545:5112d5ae6723 5215
mbed_official 545:5112d5ae6723 5216 /****************** Bit definition for NVIC_PRI0 register *******************/
mbed_official 545:5112d5ae6723 5217 #define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) /*!< Priority of interrupt 0 */
mbed_official 545:5112d5ae6723 5218 #define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 1 */
mbed_official 545:5112d5ae6723 5219 #define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 2 */
mbed_official 545:5112d5ae6723 5220 #define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) /*!< Priority of interrupt 3 */
mbed_official 545:5112d5ae6723 5221
mbed_official 545:5112d5ae6723 5222 /****************** Bit definition for NVIC_PRI1 register *******************/
mbed_official 545:5112d5ae6723 5223 #define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) /*!< Priority of interrupt 4 */
mbed_official 545:5112d5ae6723 5224 #define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 5 */
mbed_official 545:5112d5ae6723 5225 #define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 6 */
mbed_official 545:5112d5ae6723 5226 #define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) /*!< Priority of interrupt 7 */
mbed_official 545:5112d5ae6723 5227
mbed_official 545:5112d5ae6723 5228 /****************** Bit definition for NVIC_PRI2 register *******************/
mbed_official 545:5112d5ae6723 5229 #define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) /*!< Priority of interrupt 8 */
mbed_official 545:5112d5ae6723 5230 #define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 9 */
mbed_official 545:5112d5ae6723 5231 #define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 10 */
mbed_official 545:5112d5ae6723 5232 #define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) /*!< Priority of interrupt 11 */
mbed_official 545:5112d5ae6723 5233
mbed_official 545:5112d5ae6723 5234 /****************** Bit definition for NVIC_PRI3 register *******************/
mbed_official 545:5112d5ae6723 5235 #define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) /*!< Priority of interrupt 12 */
mbed_official 545:5112d5ae6723 5236 #define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 13 */
mbed_official 545:5112d5ae6723 5237 #define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 14 */
mbed_official 545:5112d5ae6723 5238 #define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) /*!< Priority of interrupt 15 */
mbed_official 545:5112d5ae6723 5239
mbed_official 545:5112d5ae6723 5240 /****************** Bit definition for NVIC_PRI4 register *******************/
mbed_official 545:5112d5ae6723 5241 #define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) /*!< Priority of interrupt 16 */
mbed_official 545:5112d5ae6723 5242 #define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 17 */
mbed_official 545:5112d5ae6723 5243 #define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 18 */
mbed_official 545:5112d5ae6723 5244 #define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) /*!< Priority of interrupt 19 */
mbed_official 545:5112d5ae6723 5245
mbed_official 545:5112d5ae6723 5246 /****************** Bit definition for NVIC_PRI5 register *******************/
mbed_official 545:5112d5ae6723 5247 #define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) /*!< Priority of interrupt 20 */
mbed_official 545:5112d5ae6723 5248 #define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 21 */
mbed_official 545:5112d5ae6723 5249 #define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 22 */
mbed_official 545:5112d5ae6723 5250 #define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) /*!< Priority of interrupt 23 */
mbed_official 545:5112d5ae6723 5251
mbed_official 545:5112d5ae6723 5252 /****************** Bit definition for NVIC_PRI6 register *******************/
mbed_official 545:5112d5ae6723 5253 #define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) /*!< Priority of interrupt 24 */
mbed_official 545:5112d5ae6723 5254 #define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 25 */
mbed_official 545:5112d5ae6723 5255 #define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 26 */
mbed_official 545:5112d5ae6723 5256 #define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) /*!< Priority of interrupt 27 */
mbed_official 545:5112d5ae6723 5257
mbed_official 545:5112d5ae6723 5258 /****************** Bit definition for NVIC_PRI7 register *******************/
mbed_official 545:5112d5ae6723 5259 #define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) /*!< Priority of interrupt 28 */
mbed_official 545:5112d5ae6723 5260 #define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 29 */
mbed_official 545:5112d5ae6723 5261 #define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 30 */
mbed_official 545:5112d5ae6723 5262 #define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) /*!< Priority of interrupt 31 */
mbed_official 545:5112d5ae6723 5263
mbed_official 545:5112d5ae6723 5264 /****************** Bit definition for SCB_CPUID register *******************/
mbed_official 545:5112d5ae6723 5265 #define SCB_CPUID_REVISION ((uint32_t)0x0000000F) /*!< Implementation defined revision number */
mbed_official 545:5112d5ae6723 5266 #define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) /*!< Number of processor within family */
mbed_official 545:5112d5ae6723 5267 #define SCB_CPUID_Constant ((uint32_t)0x000F0000) /*!< Reads as 0x0F */
mbed_official 545:5112d5ae6723 5268 #define SCB_CPUID_VARIANT ((uint32_t)0x00F00000) /*!< Implementation defined variant number */
mbed_official 545:5112d5ae6723 5269 #define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) /*!< Implementer code. ARM is 0x41 */
mbed_official 545:5112d5ae6723 5270
mbed_official 545:5112d5ae6723 5271 /******************* Bit definition for SCB_ICSR register *******************/
mbed_official 545:5112d5ae6723 5272 #define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) /*!< Active ISR number field */
mbed_official 545:5112d5ae6723 5273 #define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */
mbed_official 545:5112d5ae6723 5274 #define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) /*!< Pending ISR number field */
mbed_official 545:5112d5ae6723 5275 #define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) /*!< Interrupt pending flag */
mbed_official 545:5112d5ae6723 5276 #define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) /*!< It indicates that a pending interrupt becomes active in the next running cycle */
mbed_official 545:5112d5ae6723 5277 #define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) /*!< Clear pending SysTick bit */
mbed_official 545:5112d5ae6723 5278 #define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) /*!< Set pending SysTick bit */
mbed_official 545:5112d5ae6723 5279 #define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) /*!< Clear pending pendSV bit */
mbed_official 545:5112d5ae6723 5280 #define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) /*!< Set pending pendSV bit */
mbed_official 545:5112d5ae6723 5281 #define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) /*!< Set pending NMI bit */
mbed_official 545:5112d5ae6723 5282
mbed_official 545:5112d5ae6723 5283 /******************* Bit definition for SCB_VTOR register *******************/
mbed_official 545:5112d5ae6723 5284 #define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) /*!< Vector table base offset field */
mbed_official 545:5112d5ae6723 5285 #define SCB_VTOR_TBLBASE ((uint32_t)0x20000000) /*!< Table base in code(0) or RAM(1) */
mbed_official 545:5112d5ae6723 5286
mbed_official 545:5112d5ae6723 5287 /*!<***************** Bit definition for SCB_AIRCR register *******************/
mbed_official 545:5112d5ae6723 5288 #define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) /*!< System Reset bit */
mbed_official 545:5112d5ae6723 5289 #define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) /*!< Clear active vector bit */
mbed_official 545:5112d5ae6723 5290 #define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) /*!< Requests chip control logic to generate a reset */
mbed_official 545:5112d5ae6723 5291
mbed_official 545:5112d5ae6723 5292 #define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) /*!< PRIGROUP[2:0] bits (Priority group) */
mbed_official 545:5112d5ae6723 5293 #define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) /*!< Bit 0 */
mbed_official 545:5112d5ae6723 5294 #define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) /*!< Bit 1 */
mbed_official 545:5112d5ae6723 5295 #define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) /*!< Bit 2 */
mbed_official 545:5112d5ae6723 5296
mbed_official 545:5112d5ae6723 5297 /* prority group configuration */
mbed_official 545:5112d5ae6723 5298 #define SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */
mbed_official 545:5112d5ae6723 5299 #define SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */
mbed_official 545:5112d5ae6723 5300 #define SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */
mbed_official 545:5112d5ae6723 5301 #define SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */
mbed_official 545:5112d5ae6723 5302 #define SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */
mbed_official 545:5112d5ae6723 5303 #define SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */
mbed_official 545:5112d5ae6723 5304 #define SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */
mbed_official 545:5112d5ae6723 5305 #define SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */
mbed_official 545:5112d5ae6723 5306
mbed_official 545:5112d5ae6723 5307 #define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) /*!< Data endianness bit */
mbed_official 545:5112d5ae6723 5308 #define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */
mbed_official 545:5112d5ae6723 5309
mbed_official 545:5112d5ae6723 5310 /******************* Bit definition for SCB_SCR register ********************/
mbed_official 545:5112d5ae6723 5311 #define SCB_SCR_SLEEPONEXIT ((uint32_t)0x00000002) /*!< Sleep on exit bit */
mbed_official 545:5112d5ae6723 5312 #define SCB_SCR_SLEEPDEEP ((uint32_t)0x00000004) /*!< Sleep deep bit */
mbed_official 545:5112d5ae6723 5313 #define SCB_SCR_SEVONPEND ((uint32_t)0x00000010) /*!< Wake up from WFE */
mbed_official 545:5112d5ae6723 5314
mbed_official 545:5112d5ae6723 5315 /******************** Bit definition for SCB_CCR register *******************/
mbed_official 545:5112d5ae6723 5316 #define SCB_CCR_NONBASETHRDENA ((uint32_t)0x00000001) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */
mbed_official 545:5112d5ae6723 5317 #define SCB_CCR_USERSETMPEND ((uint32_t)0x00000002) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */
mbed_official 545:5112d5ae6723 5318 #define SCB_CCR_UNALIGN_TRP ((uint32_t)0x00000008) /*!< Trap for unaligned access */
mbed_official 545:5112d5ae6723 5319 #define SCB_CCR_DIV_0_TRP ((uint32_t)0x00000010) /*!< Trap on Divide by 0 */
mbed_official 545:5112d5ae6723 5320 #define SCB_CCR_BFHFNMIGN ((uint32_t)0x00000100) /*!< Handlers running at priority -1 and -2 */
mbed_official 545:5112d5ae6723 5321 #define SCB_CCR_STKALIGN ((uint32_t)0x00000200) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */
mbed_official 545:5112d5ae6723 5322
mbed_official 545:5112d5ae6723 5323 /******************* Bit definition for SCB_SHPR register ********************/
mbed_official 545:5112d5ae6723 5324 #define SCB_SHPR_PRI_N ((uint32_t)0x000000FF) /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */
mbed_official 545:5112d5ae6723 5325 #define SCB_SHPR_PRI_N1 ((uint32_t)0x0000FF00) /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */
mbed_official 545:5112d5ae6723 5326 #define SCB_SHPR_PRI_N2 ((uint32_t)0x00FF0000) /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */
mbed_official 545:5112d5ae6723 5327 #define SCB_SHPR_PRI_N3 ((uint32_t)0xFF000000) /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */
mbed_official 545:5112d5ae6723 5328
mbed_official 545:5112d5ae6723 5329 /****************** Bit definition for SCB_SHCSR register *******************/
mbed_official 545:5112d5ae6723 5330 #define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) /*!< MemManage is active */
mbed_official 545:5112d5ae6723 5331 #define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) /*!< BusFault is active */
mbed_official 545:5112d5ae6723 5332 #define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) /*!< UsageFault is active */
mbed_official 545:5112d5ae6723 5333 #define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) /*!< SVCall is active */
mbed_official 545:5112d5ae6723 5334 #define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) /*!< Monitor is active */
mbed_official 545:5112d5ae6723 5335 #define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) /*!< PendSV is active */
mbed_official 545:5112d5ae6723 5336 #define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) /*!< SysTick is active */
mbed_official 545:5112d5ae6723 5337 #define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) /*!< Usage Fault is pended */
mbed_official 545:5112d5ae6723 5338 #define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) /*!< MemManage is pended */
mbed_official 545:5112d5ae6723 5339 #define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) /*!< Bus Fault is pended */
mbed_official 545:5112d5ae6723 5340 #define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) /*!< SVCall is pended */
mbed_official 545:5112d5ae6723 5341 #define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) /*!< MemManage enable */
mbed_official 545:5112d5ae6723 5342 #define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) /*!< Bus Fault enable */
mbed_official 545:5112d5ae6723 5343 #define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) /*!< UsageFault enable */
mbed_official 545:5112d5ae6723 5344
mbed_official 545:5112d5ae6723 5345 /******************* Bit definition for SCB_CFSR register *******************/
mbed_official 545:5112d5ae6723 5346 /*!< MFSR */
mbed_official 545:5112d5ae6723 5347 #define SCB_CFSR_IACCVIOL ((uint32_t)0x00000001) /*!< Instruction access violation */
mbed_official 545:5112d5ae6723 5348 #define SCB_CFSR_DACCVIOL ((uint32_t)0x00000002) /*!< Data access violation */
mbed_official 545:5112d5ae6723 5349 #define SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008) /*!< Unstacking error */
mbed_official 545:5112d5ae6723 5350 #define SCB_CFSR_MSTKERR ((uint32_t)0x00000010) /*!< Stacking error */
mbed_official 545:5112d5ae6723 5351 #define SCB_CFSR_MMARVALID ((uint32_t)0x00000080) /*!< Memory Manage Address Register address valid flag */
mbed_official 545:5112d5ae6723 5352 /*!< BFSR */
mbed_official 545:5112d5ae6723 5353 #define SCB_CFSR_IBUSERR ((uint32_t)0x00000100) /*!< Instruction bus error flag */
mbed_official 545:5112d5ae6723 5354 #define SCB_CFSR_PRECISERR ((uint32_t)0x00000200) /*!< Precise data bus error */
mbed_official 545:5112d5ae6723 5355 #define SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400) /*!< Imprecise data bus error */
mbed_official 545:5112d5ae6723 5356 #define SCB_CFSR_UNSTKERR ((uint32_t)0x00000800) /*!< Unstacking error */
mbed_official 545:5112d5ae6723 5357 #define SCB_CFSR_STKERR ((uint32_t)0x00001000) /*!< Stacking error */
mbed_official 545:5112d5ae6723 5358 #define SCB_CFSR_BFARVALID ((uint32_t)0x00008000) /*!< Bus Fault Address Register address valid flag */
mbed_official 545:5112d5ae6723 5359 /*!< UFSR */
mbed_official 545:5112d5ae6723 5360 #define SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) /*!< The processor attempt to excecute an undefined instruction */
mbed_official 545:5112d5ae6723 5361 #define SCB_CFSR_INVSTATE ((uint32_t)0x00020000) /*!< Invalid combination of EPSR and instruction */
mbed_official 545:5112d5ae6723 5362 #define SCB_CFSR_INVPC ((uint32_t)0x00040000) /*!< Attempt to load EXC_RETURN into pc illegally */
mbed_official 545:5112d5ae6723 5363 #define SCB_CFSR_NOCP ((uint32_t)0x00080000) /*!< Attempt to use a coprocessor instruction */
mbed_official 545:5112d5ae6723 5364 #define SCB_CFSR_UNALIGNED ((uint32_t)0x01000000) /*!< Fault occurs when there is an attempt to make an unaligned memory access */
mbed_official 545:5112d5ae6723 5365 #define SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000) /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */
mbed_official 545:5112d5ae6723 5366
mbed_official 545:5112d5ae6723 5367 /******************* Bit definition for SCB_HFSR register *******************/
mbed_official 545:5112d5ae6723 5368 #define SCB_HFSR_VECTTBL ((uint32_t)0x00000002) /*!< Fault occures because of vector table read on exception processing */
mbed_official 545:5112d5ae6723 5369 #define SCB_HFSR_FORCED ((uint32_t)0x40000000) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */
mbed_official 545:5112d5ae6723 5370 #define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) /*!< Fault related to debug */
mbed_official 545:5112d5ae6723 5371
mbed_official 545:5112d5ae6723 5372 /******************* Bit definition for SCB_DFSR register *******************/
mbed_official 545:5112d5ae6723 5373 #define SCB_DFSR_HALTED ((uint32_t)0x00000001) /*!< Halt request flag */
mbed_official 545:5112d5ae6723 5374 #define SCB_DFSR_BKPT ((uint32_t)0x00000002) /*!< BKPT flag */
mbed_official 545:5112d5ae6723 5375 #define SCB_DFSR_DWTTRAP ((uint32_t)0x00000004) /*!< Data Watchpoint and Trace (DWT) flag */
mbed_official 545:5112d5ae6723 5376 #define SCB_DFSR_VCATCH ((uint32_t)0x00000008) /*!< Vector catch flag */
mbed_official 545:5112d5ae6723 5377 #define SCB_DFSR_EXTERNAL ((uint32_t)0x00000010) /*!< External debug request flag */
mbed_official 545:5112d5ae6723 5378
mbed_official 545:5112d5ae6723 5379 /******************* Bit definition for SCB_MMFAR register ******************/
mbed_official 545:5112d5ae6723 5380 #define SCB_MMFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Mem Manage fault address field */
mbed_official 545:5112d5ae6723 5381
mbed_official 545:5112d5ae6723 5382 /******************* Bit definition for SCB_BFAR register *******************/
mbed_official 545:5112d5ae6723 5383 #define SCB_BFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Bus fault address field */
mbed_official 545:5112d5ae6723 5384
mbed_official 545:5112d5ae6723 5385 /******************* Bit definition for SCB_afsr register *******************/
mbed_official 545:5112d5ae6723 5386 #define SCB_AFSR_IMPDEF ((uint32_t)0xFFFFFFFF) /*!< Implementation defined */
mbed_official 545:5112d5ae6723 5387 /**
mbed_official 545:5112d5ae6723 5388 * @}
mbed_official 545:5112d5ae6723 5389 */
mbed_official 545:5112d5ae6723 5390
mbed_official 545:5112d5ae6723 5391 /**
mbed_official 545:5112d5ae6723 5392 * @}
mbed_official 545:5112d5ae6723 5393 */
mbed_official 545:5112d5ae6723 5394 /** @addtogroup Exported_macro
mbed_official 545:5112d5ae6723 5395 * @{
mbed_official 545:5112d5ae6723 5396 */
mbed_official 545:5112d5ae6723 5397
mbed_official 545:5112d5ae6723 5398 /****************************** ADC Instances *********************************/
mbed_official 545:5112d5ae6723 5399 #define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
mbed_official 545:5112d5ae6723 5400
mbed_official 545:5112d5ae6723 5401 /******************************** COMP Instances ******************************/
mbed_official 545:5112d5ae6723 5402 #define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
mbed_official 545:5112d5ae6723 5403 ((INSTANCE) == COMP2))
mbed_official 545:5112d5ae6723 5404
mbed_official 545:5112d5ae6723 5405 /****************************** CRC Instances *********************************/
mbed_official 545:5112d5ae6723 5406 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
mbed_official 545:5112d5ae6723 5407
mbed_official 545:5112d5ae6723 5408 /****************************** DAC Instances *********************************/
mbed_official 545:5112d5ae6723 5409 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
mbed_official 545:5112d5ae6723 5410
mbed_official 545:5112d5ae6723 5411 /****************************** DMA Instances *********************************/
mbed_official 545:5112d5ae6723 5412 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
mbed_official 545:5112d5ae6723 5413 ((INSTANCE) == DMA1_Channel2) || \
mbed_official 545:5112d5ae6723 5414 ((INSTANCE) == DMA1_Channel3) || \
mbed_official 545:5112d5ae6723 5415 ((INSTANCE) == DMA1_Channel4) || \
mbed_official 545:5112d5ae6723 5416 ((INSTANCE) == DMA1_Channel5) || \
mbed_official 545:5112d5ae6723 5417 ((INSTANCE) == DMA1_Channel6) || \
mbed_official 545:5112d5ae6723 5418 ((INSTANCE) == DMA1_Channel7) || \
mbed_official 545:5112d5ae6723 5419 ((INSTANCE) == DMA2_Channel1) || \
mbed_official 545:5112d5ae6723 5420 ((INSTANCE) == DMA2_Channel2) || \
mbed_official 545:5112d5ae6723 5421 ((INSTANCE) == DMA2_Channel3) || \
mbed_official 545:5112d5ae6723 5422 ((INSTANCE) == DMA2_Channel4) || \
mbed_official 545:5112d5ae6723 5423 ((INSTANCE) == DMA2_Channel5))
mbed_official 545:5112d5ae6723 5424
mbed_official 545:5112d5ae6723 5425 /******************************* GPIO Instances *******************************/
mbed_official 545:5112d5ae6723 5426 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
mbed_official 545:5112d5ae6723 5427 ((INSTANCE) == GPIOB) || \
mbed_official 545:5112d5ae6723 5428 ((INSTANCE) == GPIOC) || \
mbed_official 545:5112d5ae6723 5429 ((INSTANCE) == GPIOD) || \
mbed_official 545:5112d5ae6723 5430 ((INSTANCE) == GPIOE) || \
mbed_official 545:5112d5ae6723 5431 ((INSTANCE) == GPIOH))
mbed_official 545:5112d5ae6723 5432
mbed_official 545:5112d5ae6723 5433 /**************************** GPIO Lock Instances *****************************/
mbed_official 545:5112d5ae6723 5434 /* On L1, all GPIO Bank support the Lock mechanism */
mbed_official 545:5112d5ae6723 5435 #define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
mbed_official 545:5112d5ae6723 5436
mbed_official 545:5112d5ae6723 5437 /******************************** I2C Instances *******************************/
mbed_official 545:5112d5ae6723 5438 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
mbed_official 545:5112d5ae6723 5439 ((INSTANCE) == I2C2))
mbed_official 545:5112d5ae6723 5440
mbed_official 545:5112d5ae6723 5441 #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
mbed_official 545:5112d5ae6723 5442 ((INSTANCE) == SPI2) || \
mbed_official 545:5112d5ae6723 5443 ((INSTANCE) == SPI3))
mbed_official 545:5112d5ae6723 5444 /****************************** IWDG Instances ********************************/
mbed_official 545:5112d5ae6723 5445 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
mbed_official 545:5112d5ae6723 5446
mbed_official 545:5112d5ae6723 5447 /****************************** OPAMP Instances *******************************/
mbed_official 545:5112d5ae6723 5448 #define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \
mbed_official 545:5112d5ae6723 5449 ((INSTANCE) == OPAMP2))
mbed_official 545:5112d5ae6723 5450
mbed_official 545:5112d5ae6723 5451 /****************************** RTC Instances *********************************/
mbed_official 545:5112d5ae6723 5452 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
mbed_official 545:5112d5ae6723 5453
mbed_official 545:5112d5ae6723 5454 /******************************** SPI Instances *******************************/
mbed_official 545:5112d5ae6723 5455 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
mbed_official 545:5112d5ae6723 5456 ((INSTANCE) == SPI2) || \
mbed_official 545:5112d5ae6723 5457 ((INSTANCE) == SPI3))
mbed_official 545:5112d5ae6723 5458
mbed_official 545:5112d5ae6723 5459 /****************************** TIM Instances *********************************/
mbed_official 545:5112d5ae6723 5460 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
mbed_official 545:5112d5ae6723 5461 ((INSTANCE) == TIM3) || \
mbed_official 545:5112d5ae6723 5462 ((INSTANCE) == TIM4) || \
mbed_official 545:5112d5ae6723 5463 ((INSTANCE) == TIM5) || \
mbed_official 545:5112d5ae6723 5464 ((INSTANCE) == TIM6) || \
mbed_official 545:5112d5ae6723 5465 ((INSTANCE) == TIM7) || \
mbed_official 545:5112d5ae6723 5466 ((INSTANCE) == TIM9) || \
mbed_official 545:5112d5ae6723 5467 ((INSTANCE) == TIM10) || \
mbed_official 545:5112d5ae6723 5468 ((INSTANCE) == TIM11))
mbed_official 545:5112d5ae6723 5469
mbed_official 545:5112d5ae6723 5470 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
mbed_official 545:5112d5ae6723 5471 ((INSTANCE) == TIM3) || \
mbed_official 545:5112d5ae6723 5472 ((INSTANCE) == TIM4) || \
mbed_official 545:5112d5ae6723 5473 ((INSTANCE) == TIM5) || \
mbed_official 545:5112d5ae6723 5474 ((INSTANCE) == TIM9) || \
mbed_official 545:5112d5ae6723 5475 ((INSTANCE) == TIM10) || \
mbed_official 545:5112d5ae6723 5476 ((INSTANCE) == TIM11))
mbed_official 545:5112d5ae6723 5477
mbed_official 545:5112d5ae6723 5478 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
mbed_official 545:5112d5ae6723 5479 ((INSTANCE) == TIM3) || \
mbed_official 545:5112d5ae6723 5480 ((INSTANCE) == TIM4) || \
mbed_official 545:5112d5ae6723 5481 ((INSTANCE) == TIM5) || \
mbed_official 545:5112d5ae6723 5482 ((INSTANCE) == TIM9))
mbed_official 545:5112d5ae6723 5483
mbed_official 545:5112d5ae6723 5484 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
mbed_official 545:5112d5ae6723 5485 ((INSTANCE) == TIM3) || \
mbed_official 545:5112d5ae6723 5486 ((INSTANCE) == TIM4) || \
mbed_official 545:5112d5ae6723 5487 ((INSTANCE) == TIM5))
mbed_official 545:5112d5ae6723 5488
mbed_official 545:5112d5ae6723 5489 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
mbed_official 545:5112d5ae6723 5490 ((INSTANCE) == TIM3) || \
mbed_official 545:5112d5ae6723 5491 ((INSTANCE) == TIM4) || \
mbed_official 545:5112d5ae6723 5492 ((INSTANCE) == TIM5))
mbed_official 545:5112d5ae6723 5493
mbed_official 545:5112d5ae6723 5494 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
mbed_official 545:5112d5ae6723 5495 ((INSTANCE) == TIM3) || \
mbed_official 545:5112d5ae6723 5496 ((INSTANCE) == TIM4) || \
mbed_official 545:5112d5ae6723 5497 ((INSTANCE) == TIM5) || \
mbed_official 545:5112d5ae6723 5498 ((INSTANCE) == TIM9))
mbed_official 545:5112d5ae6723 5499
mbed_official 545:5112d5ae6723 5500 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
mbed_official 545:5112d5ae6723 5501 ((INSTANCE) == TIM3) || \
mbed_official 545:5112d5ae6723 5502 ((INSTANCE) == TIM4) || \
mbed_official 545:5112d5ae6723 5503 ((INSTANCE) == TIM5) || \
mbed_official 545:5112d5ae6723 5504 ((INSTANCE) == TIM9) || \
mbed_official 545:5112d5ae6723 5505 ((INSTANCE) == TIM10) || \
mbed_official 545:5112d5ae6723 5506 ((INSTANCE) == TIM11))
mbed_official 545:5112d5ae6723 5507
mbed_official 545:5112d5ae6723 5508 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
mbed_official 545:5112d5ae6723 5509 ((INSTANCE) == TIM3) || \
mbed_official 545:5112d5ae6723 5510 ((INSTANCE) == TIM4) || \
mbed_official 545:5112d5ae6723 5511 ((INSTANCE) == TIM5) || \
mbed_official 545:5112d5ae6723 5512 ((INSTANCE) == TIM9))
mbed_official 545:5112d5ae6723 5513
mbed_official 545:5112d5ae6723 5514 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
mbed_official 545:5112d5ae6723 5515 ((INSTANCE) == TIM3) || \
mbed_official 545:5112d5ae6723 5516 ((INSTANCE) == TIM4) || \
mbed_official 545:5112d5ae6723 5517 ((INSTANCE) == TIM5) || \
mbed_official 545:5112d5ae6723 5518 ((INSTANCE) == TIM9))
mbed_official 545:5112d5ae6723 5519
mbed_official 545:5112d5ae6723 5520 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
mbed_official 545:5112d5ae6723 5521 ((INSTANCE) == TIM3) || \
mbed_official 545:5112d5ae6723 5522 ((INSTANCE) == TIM4))
mbed_official 545:5112d5ae6723 5523
mbed_official 545:5112d5ae6723 5524 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
mbed_official 545:5112d5ae6723 5525 ((INSTANCE) == TIM3) || \
mbed_official 545:5112d5ae6723 5526 ((INSTANCE) == TIM4) || \
mbed_official 545:5112d5ae6723 5527 ((INSTANCE) == TIM5))
mbed_official 545:5112d5ae6723 5528
mbed_official 545:5112d5ae6723 5529 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
mbed_official 545:5112d5ae6723 5530 ((INSTANCE) == TIM3) || \
mbed_official 545:5112d5ae6723 5531 ((INSTANCE) == TIM4) || \
mbed_official 545:5112d5ae6723 5532 ((INSTANCE) == TIM5) || \
mbed_official 545:5112d5ae6723 5533 ((INSTANCE) == TIM6) || \
mbed_official 545:5112d5ae6723 5534 ((INSTANCE) == TIM7) || \
mbed_official 545:5112d5ae6723 5535 ((INSTANCE) == TIM9))
mbed_official 545:5112d5ae6723 5536
mbed_official 545:5112d5ae6723 5537 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
mbed_official 545:5112d5ae6723 5538 ((INSTANCE) == TIM3) || \
mbed_official 545:5112d5ae6723 5539 ((INSTANCE) == TIM4) || \
mbed_official 545:5112d5ae6723 5540 ((INSTANCE) == TIM5) || \
mbed_official 545:5112d5ae6723 5541 ((INSTANCE) == TIM9))
mbed_official 545:5112d5ae6723 5542
mbed_official 545:5112d5ae6723 5543 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) ((INSTANCE) == TIM5)
mbed_official 545:5112d5ae6723 5544
mbed_official 545:5112d5ae6723 5545 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
mbed_official 545:5112d5ae6723 5546 ((INSTANCE) == TIM3) || \
mbed_official 545:5112d5ae6723 5547 ((INSTANCE) == TIM4) || \
mbed_official 545:5112d5ae6723 5548 ((INSTANCE) == TIM5))
mbed_official 545:5112d5ae6723 5549
mbed_official 545:5112d5ae6723 5550 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
mbed_official 545:5112d5ae6723 5551 ((((INSTANCE) == TIM2) && \
mbed_official 545:5112d5ae6723 5552 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 545:5112d5ae6723 5553 ((CHANNEL) == TIM_CHANNEL_2) || \
mbed_official 545:5112d5ae6723 5554 ((CHANNEL) == TIM_CHANNEL_3) || \
mbed_official 545:5112d5ae6723 5555 ((CHANNEL) == TIM_CHANNEL_4))) \
mbed_official 545:5112d5ae6723 5556 || \
mbed_official 545:5112d5ae6723 5557 (((INSTANCE) == TIM3) && \
mbed_official 545:5112d5ae6723 5558 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 545:5112d5ae6723 5559 ((CHANNEL) == TIM_CHANNEL_2) || \
mbed_official 545:5112d5ae6723 5560 ((CHANNEL) == TIM_CHANNEL_3) || \
mbed_official 545:5112d5ae6723 5561 ((CHANNEL) == TIM_CHANNEL_4))) \
mbed_official 545:5112d5ae6723 5562 || \
mbed_official 545:5112d5ae6723 5563 (((INSTANCE) == TIM4) && \
mbed_official 545:5112d5ae6723 5564 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 545:5112d5ae6723 5565 ((CHANNEL) == TIM_CHANNEL_2) || \
mbed_official 545:5112d5ae6723 5566 ((CHANNEL) == TIM_CHANNEL_3) || \
mbed_official 545:5112d5ae6723 5567 ((CHANNEL) == TIM_CHANNEL_4))) \
mbed_official 545:5112d5ae6723 5568 || \
mbed_official 545:5112d5ae6723 5569 (((INSTANCE) == TIM5) && \
mbed_official 545:5112d5ae6723 5570 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 545:5112d5ae6723 5571 ((CHANNEL) == TIM_CHANNEL_2) || \
mbed_official 545:5112d5ae6723 5572 ((CHANNEL) == TIM_CHANNEL_3) || \
mbed_official 545:5112d5ae6723 5573 ((CHANNEL) == TIM_CHANNEL_4))) \
mbed_official 545:5112d5ae6723 5574 || \
mbed_official 545:5112d5ae6723 5575 (((INSTANCE) == TIM9) && \
mbed_official 545:5112d5ae6723 5576 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 545:5112d5ae6723 5577 ((CHANNEL) == TIM_CHANNEL_2))) \
mbed_official 545:5112d5ae6723 5578 || \
mbed_official 545:5112d5ae6723 5579 (((INSTANCE) == TIM10) && \
mbed_official 545:5112d5ae6723 5580 (((CHANNEL) == TIM_CHANNEL_1))) \
mbed_official 545:5112d5ae6723 5581 || \
mbed_official 545:5112d5ae6723 5582 (((INSTANCE) == TIM11) && \
mbed_official 545:5112d5ae6723 5583 (((CHANNEL) == TIM_CHANNEL_1))))
mbed_official 545:5112d5ae6723 5584
mbed_official 545:5112d5ae6723 5585 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
mbed_official 545:5112d5ae6723 5586 ((INSTANCE) == TIM3) || \
mbed_official 545:5112d5ae6723 5587 ((INSTANCE) == TIM4) || \
mbed_official 545:5112d5ae6723 5588 ((INSTANCE) == TIM5) || \
mbed_official 545:5112d5ae6723 5589 ((INSTANCE) == TIM9) || \
mbed_official 545:5112d5ae6723 5590 ((INSTANCE) == TIM10) || \
mbed_official 545:5112d5ae6723 5591 ((INSTANCE) == TIM11))
mbed_official 545:5112d5ae6723 5592
mbed_official 545:5112d5ae6723 5593 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
mbed_official 545:5112d5ae6723 5594 ((INSTANCE) == TIM3) || \
mbed_official 545:5112d5ae6723 5595 ((INSTANCE) == TIM4) || \
mbed_official 545:5112d5ae6723 5596 ((INSTANCE) == TIM5) || \
mbed_official 545:5112d5ae6723 5597 ((INSTANCE) == TIM6) || \
mbed_official 545:5112d5ae6723 5598 ((INSTANCE) == TIM7))
mbed_official 545:5112d5ae6723 5599
mbed_official 545:5112d5ae6723 5600 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
mbed_official 545:5112d5ae6723 5601 ((INSTANCE) == TIM3) || \
mbed_official 545:5112d5ae6723 5602 ((INSTANCE) == TIM4) || \
mbed_official 545:5112d5ae6723 5603 ((INSTANCE) == TIM5))
mbed_official 545:5112d5ae6723 5604
mbed_official 545:5112d5ae6723 5605 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
mbed_official 545:5112d5ae6723 5606 ((INSTANCE) == TIM3) || \
mbed_official 545:5112d5ae6723 5607 ((INSTANCE) == TIM4) || \
mbed_official 545:5112d5ae6723 5608 ((INSTANCE) == TIM5) || \
mbed_official 545:5112d5ae6723 5609 ((INSTANCE) == TIM9))
mbed_official 545:5112d5ae6723 5610
mbed_official 545:5112d5ae6723 5611 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
mbed_official 545:5112d5ae6723 5612 ((INSTANCE) == TIM3) || \
mbed_official 545:5112d5ae6723 5613 ((INSTANCE) == TIM4) || \
mbed_official 545:5112d5ae6723 5614 ((INSTANCE) == TIM5) || \
mbed_official 545:5112d5ae6723 5615 ((INSTANCE) == TIM9))
mbed_official 545:5112d5ae6723 5616
mbed_official 545:5112d5ae6723 5617 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
mbed_official 545:5112d5ae6723 5618 ((INSTANCE) == TIM3) || \
mbed_official 545:5112d5ae6723 5619 ((INSTANCE) == TIM9) || \
mbed_official 545:5112d5ae6723 5620 ((INSTANCE) == TIM10) || \
mbed_official 545:5112d5ae6723 5621 ((INSTANCE) == TIM11))
mbed_official 545:5112d5ae6723 5622
mbed_official 545:5112d5ae6723 5623 /******************** USART Instances : Synchronous mode **********************/
mbed_official 545:5112d5ae6723 5624 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 545:5112d5ae6723 5625 ((INSTANCE) == USART2) || \
mbed_official 545:5112d5ae6723 5626 ((INSTANCE) == USART3))
mbed_official 545:5112d5ae6723 5627
mbed_official 545:5112d5ae6723 5628 /******************** UART Instances : Asynchronous mode **********************/
mbed_official 545:5112d5ae6723 5629 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 545:5112d5ae6723 5630 ((INSTANCE) == USART2) || \
mbed_official 545:5112d5ae6723 5631 ((INSTANCE) == USART3))
mbed_official 545:5112d5ae6723 5632
mbed_official 545:5112d5ae6723 5633 /******************** UART Instances : Half-Duplex mode **********************/
mbed_official 545:5112d5ae6723 5634 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 545:5112d5ae6723 5635 ((INSTANCE) == USART2) || \
mbed_official 545:5112d5ae6723 5636 ((INSTANCE) == USART3))
mbed_official 545:5112d5ae6723 5637
mbed_official 545:5112d5ae6723 5638 /******************** UART Instances : LIN mode **********************/
mbed_official 545:5112d5ae6723 5639 #define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 545:5112d5ae6723 5640 ((INSTANCE) == USART2) || \
mbed_official 545:5112d5ae6723 5641 ((INSTANCE) == USART3))
mbed_official 545:5112d5ae6723 5642
mbed_official 545:5112d5ae6723 5643 /****************** UART Instances : Hardware Flow control ********************/
mbed_official 545:5112d5ae6723 5644 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 545:5112d5ae6723 5645 ((INSTANCE) == USART2) || \
mbed_official 545:5112d5ae6723 5646 ((INSTANCE) == USART3))
mbed_official 545:5112d5ae6723 5647
mbed_official 545:5112d5ae6723 5648 /********************* UART Instances : Smard card mode ***********************/
mbed_official 545:5112d5ae6723 5649 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 545:5112d5ae6723 5650 ((INSTANCE) == USART2) || \
mbed_official 545:5112d5ae6723 5651 ((INSTANCE) == USART3))
mbed_official 545:5112d5ae6723 5652
mbed_official 545:5112d5ae6723 5653 /*********************** UART Instances : IRDA mode ***************************/
mbed_official 545:5112d5ae6723 5654 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 545:5112d5ae6723 5655 ((INSTANCE) == USART2) || \
mbed_official 545:5112d5ae6723 5656 ((INSTANCE) == USART3))
mbed_official 545:5112d5ae6723 5657
mbed_official 545:5112d5ae6723 5658 /***************** UART Instances : Multi-Processor mode **********************/
mbed_official 545:5112d5ae6723 5659 #define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 545:5112d5ae6723 5660 ((INSTANCE) == USART2) || \
mbed_official 545:5112d5ae6723 5661 ((INSTANCE) == USART3))
mbed_official 545:5112d5ae6723 5662
mbed_official 545:5112d5ae6723 5663 /****************************** WWDG Instances ********************************/
mbed_official 545:5112d5ae6723 5664 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
mbed_official 545:5112d5ae6723 5665
mbed_official 545:5112d5ae6723 5666 /****************************** USB Instances ********************************/
mbed_official 545:5112d5ae6723 5667 #define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
mbed_official 545:5112d5ae6723 5668
mbed_official 545:5112d5ae6723 5669 /**
mbed_official 545:5112d5ae6723 5670 * @}
mbed_official 545:5112d5ae6723 5671 */
mbed_official 545:5112d5ae6723 5672
mbed_official 545:5112d5ae6723 5673 /******************************************************************************/
mbed_official 545:5112d5ae6723 5674 /* For a painless codes migration between the STM32L1xx device product */
mbed_official 545:5112d5ae6723 5675 /* lines, the aliases defined below are put in place to overcome the */
mbed_official 545:5112d5ae6723 5676 /* differences in the interrupt handlers and IRQn definitions. */
mbed_official 545:5112d5ae6723 5677 /* No need to update developed interrupt code when moving across */
mbed_official 545:5112d5ae6723 5678 /* product lines within the same STM32L1 Family */
mbed_official 545:5112d5ae6723 5679 /******************************************************************************/
mbed_official 545:5112d5ae6723 5680
mbed_official 545:5112d5ae6723 5681 /* Aliases for __IRQn */
mbed_official 545:5112d5ae6723 5682
mbed_official 545:5112d5ae6723 5683 /* Aliases for __IRQHandler */
mbed_official 545:5112d5ae6723 5684
mbed_official 545:5112d5ae6723 5685 /**
mbed_official 545:5112d5ae6723 5686 * @}
mbed_official 545:5112d5ae6723 5687 */
mbed_official 545:5112d5ae6723 5688
mbed_official 545:5112d5ae6723 5689 /**
mbed_official 545:5112d5ae6723 5690 * @}
mbed_official 545:5112d5ae6723 5691 */
mbed_official 545:5112d5ae6723 5692
mbed_official 545:5112d5ae6723 5693 #ifdef __cplusplus
mbed_official 545:5112d5ae6723 5694 }
mbed_official 545:5112d5ae6723 5695 #endif /* __cplusplus */
mbed_official 545:5112d5ae6723 5696
mbed_official 545:5112d5ae6723 5697 #endif /* __STM32L151xC_H */
mbed_official 545:5112d5ae6723 5698
mbed_official 545:5112d5ae6723 5699
mbed_official 545:5112d5ae6723 5700
mbed_official 545:5112d5ae6723 5701 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/