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targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/system_stm32l1xx.c@579:53297373a894, 2015-07-01 (annotated)

Committer:: mbed_official
Date:: Wed Jul 01 09:45:11 2015 +0100
Revision:: 579:53297373a894
Parent:: 394:83f921546702

Synchronized with git revision d5b4d2ab9c47edb4dc5776e7177b0c2263459081

Full URL: https://github.com/mbedmicro/mbed/commit/d5b4d2ab9c47edb4dc5776e7177b0c2263459081/

Initial version of drivers for SAMR21

Who changed what in which revision?

User	Revision	Line number	New contents of line
mbed_official	76:aeb1df146756	1	/**
mbed_official	76:aeb1df146756	2	******************************************************************************
mbed_official	76:aeb1df146756	3	* @file system_stm32l1xx.c
mbed_official	76:aeb1df146756	4	* @author MCD Application Team
mbed_official	354:e67efb2aab0e	5	* @version V2.0.0
mbed_official	354:e67efb2aab0e	6	* @date 5-September-2014
mbed_official	76:aeb1df146756	7	* @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
mbed_official	354:e67efb2aab0e	8	*
mbed_official	354:e67efb2aab0e	9	* This file provides two functions and one global variable to be called from
mbed_official	354:e67efb2aab0e	10	* user application:
mbed_official	354:e67efb2aab0e	11	* - SystemInit(): This function is called at startup just after reset and
mbed_official	76:aeb1df146756	12	* before branch to main program. This call is made inside
mbed_official	354:e67efb2aab0e	13	* the "startup_stm32l1xx.s" file.
mbed_official	354:e67efb2aab0e	14	*
mbed_official	76:aeb1df146756	15	* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
mbed_official	76:aeb1df146756	16	* by the user application to setup the SysTick
mbed_official	76:aeb1df146756	17	* timer or configure other parameters.
mbed_official	76:aeb1df146756	18	*
mbed_official	76:aeb1df146756	19	* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
mbed_official	76:aeb1df146756	20	* be called whenever the core clock is changed
mbed_official	354:e67efb2aab0e	21	* during program execution.
mbed_official	139:e3413eddde57	22	*
mbed_official	354:e67efb2aab0e	23	* This file configures the system clock as follows:
mbed_official	139:e3413eddde57	24	*-----------------------------------------------------------------------------
mbed_official	139:e3413eddde57	25	* System clock source \| 1- PLL_HSE_EXTC \| 3- PLL_HSI
mbed_official	139:e3413eddde57	26	* \| (external 8 MHz clock) \| (internal 16 MHz)
mbed_official	139:e3413eddde57	27	* \| 2- PLL_HSE_XTAL \|
mbed_official	139:e3413eddde57	28	* \| (external 8 MHz xtal) \|
mbed_official	139:e3413eddde57	29	*-----------------------------------------------------------------------------
mbed_official	139:e3413eddde57	30	* SYSCLK(MHz) \| 24 \| 32
mbed_official	139:e3413eddde57	31	*-----------------------------------------------------------------------------
mbed_official	139:e3413eddde57	32	* AHBCLK (MHz) \| 24 \| 32
mbed_official	139:e3413eddde57	33	*-----------------------------------------------------------------------------
mbed_official	139:e3413eddde57	34	* APB1CLK (MHz) \| 24 \| 32
mbed_official	139:e3413eddde57	35	*-----------------------------------------------------------------------------
mbed_official	139:e3413eddde57	36	* APB2CLK (MHz) \| 24 \| 32
mbed_official	139:e3413eddde57	37	*-----------------------------------------------------------------------------
mbed_official	139:e3413eddde57	38	* USB capable (48 MHz precise clock) \| YES \| NO
mbed_official	354:e67efb2aab0e	39	*-----------------------------------------------------------------------------
mbed_official	139:e3413eddde57	40	******************************************************************************
mbed_official	76:aeb1df146756	41	* @attention
mbed_official	76:aeb1df146756	42	*
mbed_official	106:ced8cbb51063	43	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
mbed_official	76:aeb1df146756	44	*
mbed_official	106:ced8cbb51063	45	* Redistribution and use in source and binary forms, with or without modification,
mbed_official	106:ced8cbb51063	46	* are permitted provided that the following conditions are met:
mbed_official	106:ced8cbb51063	47	* 1. Redistributions of source code must retain the above copyright notice,
mbed_official	106:ced8cbb51063	48	* this list of conditions and the following disclaimer.
mbed_official	106:ced8cbb51063	49	* 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official	106:ced8cbb51063	50	* this list of conditions and the following disclaimer in the documentation
mbed_official	106:ced8cbb51063	51	* and/or other materials provided with the distribution.
mbed_official	106:ced8cbb51063	52	* 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official	106:ced8cbb51063	53	* may be used to endorse or promote products derived from this software
mbed_official	106:ced8cbb51063	54	* without specific prior written permission.
mbed_official	76:aeb1df146756	55	*
mbed_official	106:ced8cbb51063	56	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official	106:ced8cbb51063	57	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official	106:ced8cbb51063	58	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official	106:ced8cbb51063	59	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official	106:ced8cbb51063	60	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official	106:ced8cbb51063	61	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official	106:ced8cbb51063	62	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official	106:ced8cbb51063	63	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official	106:ced8cbb51063	64	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official	106:ced8cbb51063	65	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official	76:aeb1df146756	66	*
mbed_official	76:aeb1df146756	67	******************************************************************************
mbed_official	76:aeb1df146756	68	*/
mbed_official	76:aeb1df146756	69
mbed_official	76:aeb1df146756	70	/** @addtogroup CMSIS
mbed_official	76:aeb1df146756	71	* @{
mbed_official	76:aeb1df146756	72	*/
mbed_official	76:aeb1df146756	73
mbed_official	76:aeb1df146756	74	/** @addtogroup stm32l1xx_system
mbed_official	76:aeb1df146756	75	* @{
mbed_official	76:aeb1df146756	76	*/
mbed_official	76:aeb1df146756	77
mbed_official	76:aeb1df146756	78	/** @addtogroup STM32L1xx_System_Private_Includes
mbed_official	76:aeb1df146756	79	* @{
mbed_official	76:aeb1df146756	80	*/
mbed_official	76:aeb1df146756	81
mbed_official	76:aeb1df146756	82	#include "stm32l1xx.h"
mbed_official	354:e67efb2aab0e	83	#include "hal_tick.h"
mbed_official	76:aeb1df146756	84
mbed_official	76:aeb1df146756	85	/**
mbed_official	76:aeb1df146756	86	* @}
mbed_official	76:aeb1df146756	87	*/
mbed_official	76:aeb1df146756	88
mbed_official	76:aeb1df146756	89	/** @addtogroup STM32L1xx_System_Private_TypesDefinitions
mbed_official	76:aeb1df146756	90	* @{
mbed_official	76:aeb1df146756	91	*/
mbed_official	76:aeb1df146756	92
mbed_official	76:aeb1df146756	93	/**
mbed_official	76:aeb1df146756	94	* @}
mbed_official	76:aeb1df146756	95	*/
mbed_official	76:aeb1df146756	96
mbed_official	76:aeb1df146756	97	/** @addtogroup STM32L1xx_System_Private_Defines
mbed_official	76:aeb1df146756	98	* @{
mbed_official	76:aeb1df146756	99	*/
mbed_official	354:e67efb2aab0e	100	#if !defined (HSE_VALUE)
mbed_official	354:e67efb2aab0e	101	#define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz.
mbed_official	354:e67efb2aab0e	102	This value can be provided and adapted by the user application. */
mbed_official	354:e67efb2aab0e	103	#endif /* HSE_VALUE */
mbed_official	76:aeb1df146756	104
mbed_official	354:e67efb2aab0e	105	#if !defined (HSI_VALUE)
mbed_official	354:e67efb2aab0e	106	#define HSI_VALUE ((uint32_t)16000000) /*!< Default value of the Internal oscillator in Hz.
mbed_official	354:e67efb2aab0e	107	This value can be provided and adapted by the user application. */
mbed_official	354:e67efb2aab0e	108	#endif /* HSI_VALUE */
mbed_official	354:e67efb2aab0e	109
mbed_official	354:e67efb2aab0e	110	/*!< Uncomment the following line if you need to use external SRAM mounted
mbed_official	354:e67efb2aab0e	111	on STM32L152D_EVAL board as data memory */
mbed_official	354:e67efb2aab0e	112	/* #define DATA_IN_ExtSRAM */
mbed_official	354:e67efb2aab0e	113
mbed_official	76:aeb1df146756	114	/*!< Uncomment the following line if you need to relocate your vector Table in
mbed_official	76:aeb1df146756	115	Internal SRAM. */
mbed_official	76:aeb1df146756	116	/* #define VECT_TAB_SRAM */
mbed_official	76:aeb1df146756	117	#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field.
mbed_official	76:aeb1df146756	118	This value must be a multiple of 0x200. */
mbed_official	76:aeb1df146756	119	/**
mbed_official	76:aeb1df146756	120	* @}
mbed_official	76:aeb1df146756	121	*/
mbed_official	76:aeb1df146756	122
mbed_official	76:aeb1df146756	123	/** @addtogroup STM32L1xx_System_Private_Macros
mbed_official	76:aeb1df146756	124	* @{
mbed_official	76:aeb1df146756	125	*/
mbed_official	76:aeb1df146756	126
mbed_official	139:e3413eddde57	127	/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
mbed_official	139:e3413eddde57	128	#define USE_PLL_HSE_EXTC (1) /* Use external clock */
mbed_official	139:e3413eddde57	129	#define USE_PLL_HSE_XTAL (1) /* Use external xtal */
mbed_official	139:e3413eddde57	130
mbed_official	76:aeb1df146756	131	/**
mbed_official	76:aeb1df146756	132	* @}
mbed_official	76:aeb1df146756	133	*/
mbed_official	76:aeb1df146756	134
mbed_official	76:aeb1df146756	135	/** @addtogroup STM32L1xx_System_Private_Variables
mbed_official	76:aeb1df146756	136	* @{
mbed_official	76:aeb1df146756	137	*/
mbed_official	354:e67efb2aab0e	138	/* This variable is updated in three ways:
mbed_official	354:e67efb2aab0e	139	1) by calling CMSIS function SystemCoreClockUpdate()
mbed_official	354:e67efb2aab0e	140	2) by calling HAL API function HAL_RCC_GetHCLKFreq()
mbed_official	354:e67efb2aab0e	141	3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
mbed_official	354:e67efb2aab0e	142	Note: If you use this function to configure the system clock; then there
mbed_official	354:e67efb2aab0e	143	is no need to call the 2 first functions listed above, since SystemCoreClock
mbed_official	354:e67efb2aab0e	144	variable is updated automatically.
mbed_official	354:e67efb2aab0e	145	*/
mbed_official	139:e3413eddde57	146	uint32_t SystemCoreClock = 32000000; /* Default with HSI. Will be updated if HSE is used */
mbed_official	354:e67efb2aab0e	147	const uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48};
mbed_official	354:e67efb2aab0e	148	const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
mbed_official	76:aeb1df146756	149
mbed_official	76:aeb1df146756	150	/**
mbed_official	76:aeb1df146756	151	* @}
mbed_official	76:aeb1df146756	152	*/
mbed_official	76:aeb1df146756	153
mbed_official	76:aeb1df146756	154	/** @addtogroup STM32L1xx_System_Private_FunctionPrototypes
mbed_official	76:aeb1df146756	155	* @{
mbed_official	76:aeb1df146756	156	*/
mbed_official	76:aeb1df146756	157
mbed_official	354:e67efb2aab0e	158	#if defined (STM32L151xD) \|\| defined (STM32L152xD) \|\| defined (STM32L162xD)
mbed_official	354:e67efb2aab0e	159	#ifdef DATA_IN_ExtSRAM
mbed_official	354:e67efb2aab0e	160	static void SystemInit_ExtMemCtl(void);
mbed_official	354:e67efb2aab0e	161	#endif /* DATA_IN_ExtSRAM */
mbed_official	354:e67efb2aab0e	162	#endif /* STM32L151xD \|\| STM32L152xD \|\| STM32L162xD */
mbed_official	76:aeb1df146756	163
mbed_official	139:e3413eddde57	164	#if (USE_PLL_HSE_XTAL != 0) \|\| (USE_PLL_HSE_EXTC != 0)
mbed_official	139:e3413eddde57	165	uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
mbed_official	139:e3413eddde57	166	#endif
mbed_official	139:e3413eddde57	167
mbed_official	139:e3413eddde57	168	uint8_t SetSysClock_PLL_HSI(void);
mbed_official	139:e3413eddde57	169
mbed_official	76:aeb1df146756	170	/**
mbed_official	76:aeb1df146756	171	* @}
mbed_official	76:aeb1df146756	172	*/
mbed_official	76:aeb1df146756	173
mbed_official	76:aeb1df146756	174	/** @addtogroup STM32L1xx_System_Private_Functions
mbed_official	76:aeb1df146756	175	* @{
mbed_official	76:aeb1df146756	176	*/
mbed_official	76:aeb1df146756	177
mbed_official	76:aeb1df146756	178	/**
mbed_official	76:aeb1df146756	179	* @brief Setup the microcontroller system.
mbed_official	76:aeb1df146756	180	* Initialize the Embedded Flash Interface, the PLL and update the
mbed_official	76:aeb1df146756	181	* SystemCoreClock variable.
mbed_official	76:aeb1df146756	182	* @param None
mbed_official	76:aeb1df146756	183	* @retval None
mbed_official	76:aeb1df146756	184	*/
mbed_official	76:aeb1df146756	185	void SystemInit (void)
mbed_official	76:aeb1df146756	186	{
mbed_official	76:aeb1df146756	187	/!< Set MSION bit /
mbed_official	76:aeb1df146756	188	RCC->CR \|= (uint32_t)0x00000100;
mbed_official	76:aeb1df146756	189
mbed_official	76:aeb1df146756	190	/!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits /
mbed_official	76:aeb1df146756	191	RCC->CFGR &= (uint32_t)0x88FFC00C;
mbed_official	76:aeb1df146756	192
mbed_official	76:aeb1df146756	193	/!< Reset HSION, HSEON, CSSON and PLLON bits /
mbed_official	76:aeb1df146756	194	RCC->CR &= (uint32_t)0xEEFEFFFE;
mbed_official	76:aeb1df146756	195
mbed_official	76:aeb1df146756	196	/!< Reset HSEBYP bit /
mbed_official	76:aeb1df146756	197	RCC->CR &= (uint32_t)0xFFFBFFFF;
mbed_official	76:aeb1df146756	198
mbed_official	76:aeb1df146756	199	/!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits /
mbed_official	76:aeb1df146756	200	RCC->CFGR &= (uint32_t)0xFF02FFFF;
mbed_official	76:aeb1df146756	201
mbed_official	76:aeb1df146756	202	/!< Disable all interrupts /
mbed_official	76:aeb1df146756	203	RCC->CIR = 0x00000000;
mbed_official	76:aeb1df146756	204
mbed_official	354:e67efb2aab0e	205	#ifdef DATA_IN_ExtSRAM
mbed_official	354:e67efb2aab0e	206	SystemInit_ExtMemCtl();
mbed_official	354:e67efb2aab0e	207	#endif /* DATA_IN_ExtSRAM */
mbed_official	354:e67efb2aab0e	208
mbed_official	354:e67efb2aab0e	209	#ifdef VECT_TAB_SRAM
mbed_official	354:e67efb2aab0e	210	SCB->VTOR = SRAM_BASE \| VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
mbed_official	354:e67efb2aab0e	211	#else
mbed_official	354:e67efb2aab0e	212	SCB->VTOR = FLASH_BASE \| VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
mbed_official	354:e67efb2aab0e	213	#endif
mbed_official	354:e67efb2aab0e	214
mbed_official	354:e67efb2aab0e	215	/* Configure the Cube driver */
mbed_official	354:e67efb2aab0e	216	SystemCoreClock = 16000000; // At this stage the HSI is used as system clock
mbed_official	354:e67efb2aab0e	217	HAL_Init();
mbed_official	354:e67efb2aab0e	218
mbed_official	354:e67efb2aab0e	219	/* Configure the System clock source, PLL Multiplier and Divider factors,
mbed_official	139:e3413eddde57	220	AHB/APBx prescalers and Flash settings */
mbed_official	76:aeb1df146756	221	SetSysClock();
mbed_official	354:e67efb2aab0e	222
mbed_official	354:e67efb2aab0e	223	/* Reset the timer to avoid issues after the RAM initialization */
mbed_official	354:e67efb2aab0e	224	TIM_MST_RESET_ON;
mbed_official	354:e67efb2aab0e	225	TIM_MST_RESET_OFF;
mbed_official	76:aeb1df146756	226	}
mbed_official	76:aeb1df146756	227
mbed_official	76:aeb1df146756	228	/**
mbed_official	354:e67efb2aab0e	229	* @brief Update SystemCoreClock according to Clock Register Values
mbed_official	76:aeb1df146756	230	* The SystemCoreClock variable contains the core clock (HCLK), it can
mbed_official	76:aeb1df146756	231	* be used by the user application to setup the SysTick timer or configure
mbed_official	76:aeb1df146756	232	* other parameters.
mbed_official	76:aeb1df146756	233	*
mbed_official	76:aeb1df146756	234	* @note Each time the core clock (HCLK) changes, this function must be called
mbed_official	76:aeb1df146756	235	* to update SystemCoreClock variable value. Otherwise, any configuration
mbed_official	76:aeb1df146756	236	* based on this variable will be incorrect.
mbed_official	76:aeb1df146756	237	*
mbed_official	76:aeb1df146756	238	* @note - The system frequency computed by this function is not the real
mbed_official	76:aeb1df146756	239	* frequency in the chip. It is calculated based on the predefined
mbed_official	76:aeb1df146756	240	* constant and the selected clock source:
mbed_official	76:aeb1df146756	241	*
mbed_official	76:aeb1df146756	242	* - If SYSCLK source is MSI, SystemCoreClock will contain the MSI
mbed_official	76:aeb1df146756	243	* value as defined by the MSI range.
mbed_official	76:aeb1df146756	244	*
mbed_official	76:aeb1df146756	245	* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
mbed_official	76:aeb1df146756	246	*
mbed_official	76:aeb1df146756	247	* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
mbed_official	76:aeb1df146756	248	*
mbed_official	354:e67efb2aab0e	249	* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
mbed_official	76:aeb1df146756	250	* or HSI_VALUE(*) multiplied/divided by the PLL factors.
mbed_official	76:aeb1df146756	251	*
mbed_official	76:aeb1df146756	252	* (*) HSI_VALUE is a constant defined in stm32l1xx.h file (default value
mbed_official	76:aeb1df146756	253	* 16 MHz) but the real value may vary depending on the variations
mbed_official	76:aeb1df146756	254	* in voltage and temperature.
mbed_official	76:aeb1df146756	255	*
mbed_official	76:aeb1df146756	256	* (**) HSE_VALUE is a constant defined in stm32l1xx.h file (default value
mbed_official	76:aeb1df146756	257	* 8 MHz), user has to ensure that HSE_VALUE is same as the real
mbed_official	76:aeb1df146756	258	* frequency of the crystal used. Otherwise, this function may
mbed_official	76:aeb1df146756	259	* have wrong result.
mbed_official	76:aeb1df146756	260	*
mbed_official	76:aeb1df146756	261	* - The result of this function could be not correct when using fractional
mbed_official	354:e67efb2aab0e	262	* value for HSE crystal.
mbed_official	76:aeb1df146756	263	* @param None
mbed_official	76:aeb1df146756	264	* @retval None
mbed_official	76:aeb1df146756	265	*/
mbed_official	76:aeb1df146756	266	void SystemCoreClockUpdate (void)
mbed_official	76:aeb1df146756	267	{
mbed_official	76:aeb1df146756	268	uint32_t tmp = 0, pllmul = 0, plldiv = 0, pllsource = 0, msirange = 0;
mbed_official	76:aeb1df146756	269
mbed_official	76:aeb1df146756	270	/* Get SYSCLK source -------------------------------------------------------*/
mbed_official	76:aeb1df146756	271	tmp = RCC->CFGR & RCC_CFGR_SWS;
mbed_official	76:aeb1df146756	272
mbed_official	76:aeb1df146756	273	switch (tmp)
mbed_official	76:aeb1df146756	274	{
mbed_official	76:aeb1df146756	275	case 0x00: /* MSI used as system clock */
mbed_official	76:aeb1df146756	276	msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;
mbed_official	76:aeb1df146756	277	SystemCoreClock = (32768 * (1 << (msirange + 1)));
mbed_official	76:aeb1df146756	278	break;
mbed_official	76:aeb1df146756	279	case 0x04: /* HSI used as system clock */
mbed_official	76:aeb1df146756	280	SystemCoreClock = HSI_VALUE;
mbed_official	76:aeb1df146756	281	break;
mbed_official	76:aeb1df146756	282	case 0x08: /* HSE used as system clock */
mbed_official	76:aeb1df146756	283	SystemCoreClock = HSE_VALUE;
mbed_official	76:aeb1df146756	284	break;
mbed_official	76:aeb1df146756	285	case 0x0C: /* PLL used as system clock */
mbed_official	76:aeb1df146756	286	/* Get PLL clock source and multiplication factor ----------------------*/
mbed_official	76:aeb1df146756	287	pllmul = RCC->CFGR & RCC_CFGR_PLLMUL;
mbed_official	76:aeb1df146756	288	plldiv = RCC->CFGR & RCC_CFGR_PLLDIV;
mbed_official	76:aeb1df146756	289	pllmul = PLLMulTable[(pllmul >> 18)];
mbed_official	76:aeb1df146756	290	plldiv = (plldiv >> 22) + 1;
mbed_official	76:aeb1df146756	291
mbed_official	76:aeb1df146756	292	pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
mbed_official	76:aeb1df146756	293
mbed_official	76:aeb1df146756	294	if (pllsource == 0x00)
mbed_official	76:aeb1df146756	295	{
mbed_official	76:aeb1df146756	296	/* HSI oscillator clock selected as PLL clock entry */
mbed_official	76:aeb1df146756	297	SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv);
mbed_official	76:aeb1df146756	298	}
mbed_official	76:aeb1df146756	299	else
mbed_official	76:aeb1df146756	300	{
mbed_official	76:aeb1df146756	301	/* HSE selected as PLL clock entry */
mbed_official	76:aeb1df146756	302	SystemCoreClock = (((HSE_VALUE) * pllmul) / plldiv);
mbed_official	76:aeb1df146756	303	}
mbed_official	76:aeb1df146756	304	break;
mbed_official	76:aeb1df146756	305	default: /* MSI used as system clock */
mbed_official	76:aeb1df146756	306	msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;
mbed_official	76:aeb1df146756	307	SystemCoreClock = (32768 * (1 << (msirange + 1)));
mbed_official	76:aeb1df146756	308	break;
mbed_official	76:aeb1df146756	309	}
mbed_official	76:aeb1df146756	310	/* Compute HCLK clock frequency --------------------------------------------*/
mbed_official	76:aeb1df146756	311	/* Get HCLK prescaler */
mbed_official	76:aeb1df146756	312	tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
mbed_official	76:aeb1df146756	313	/* HCLK clock frequency */
mbed_official	76:aeb1df146756	314	SystemCoreClock >>= tmp;
mbed_official	76:aeb1df146756	315	}
mbed_official	76:aeb1df146756	316
mbed_official	354:e67efb2aab0e	317	#if defined (STM32L151xD) \|\| defined (STM32L152xD) \|\| defined (STM32L162xD)
mbed_official	354:e67efb2aab0e	318	#ifdef DATA_IN_ExtSRAM
mbed_official	354:e67efb2aab0e	319	/**
mbed_official	354:e67efb2aab0e	320	* @brief Setup the external memory controller.
mbed_official	354:e67efb2aab0e	321	* Called in SystemInit() function before jump to main.
mbed_official	354:e67efb2aab0e	322	* This function configures the external SRAM mounted on STM32L152D_EVAL board
mbed_official	354:e67efb2aab0e	323	* This SRAM will be used as program data memory (including heap and stack).
mbed_official	354:e67efb2aab0e	324	* @param None
mbed_official	354:e67efb2aab0e	325	* @retval None
mbed_official	354:e67efb2aab0e	326	*/
mbed_official	354:e67efb2aab0e	327	void SystemInit_ExtMemCtl(void)
mbed_official	354:e67efb2aab0e	328	{
mbed_official	354:e67efb2aab0e	329	/-- GPIOs Configuration -----------------------------------------------------/
mbed_official	354:e67efb2aab0e	330	/*
mbed_official	354:e67efb2aab0e	331	+-------------------+--------------------+------------------+------------------+
mbed_official	354:e67efb2aab0e	332	+ SRAM pins assignment +
mbed_official	354:e67efb2aab0e	333	+-------------------+--------------------+------------------+------------------+
mbed_official	354:e67efb2aab0e	334	\| PD0 <-> FSMC_D2 \| PE0 <-> FSMC_NBL0 \| PF0 <-> FSMC_A0 \| PG0 <-> FSMC_A10 \|
mbed_official	354:e67efb2aab0e	335	\| PD1 <-> FSMC_D3 \| PE1 <-> FSMC_NBL1 \| PF1 <-> FSMC_A1 \| PG1 <-> FSMC_A11 \|
mbed_official	354:e67efb2aab0e	336	\| PD4 <-> FSMC_NOE \| PE7 <-> FSMC_D4 \| PF2 <-> FSMC_A2 \| PG2 <-> FSMC_A12 \|
mbed_official	354:e67efb2aab0e	337	\| PD5 <-> FSMC_NWE \| PE8 <-> FSMC_D5 \| PF3 <-> FSMC_A3 \| PG3 <-> FSMC_A13 \|
mbed_official	354:e67efb2aab0e	338	\| PD8 <-> FSMC_D13 \| PE9 <-> FSMC_D6 \| PF4 <-> FSMC_A4 \| PG4 <-> FSMC_A14 \|
mbed_official	354:e67efb2aab0e	339	\| PD9 <-> FSMC_D14 \| PE10 <-> FSMC_D7 \| PF5 <-> FSMC_A5 \| PG5 <-> FSMC_A15 \|
mbed_official	354:e67efb2aab0e	340	\| PD10 <-> FSMC_D15 \| PE11 <-> FSMC_D8 \| PF12 <-> FSMC_A6 \| PG10<-> FSMC_NE2 \|
mbed_official	354:e67efb2aab0e	341	\| PD11 <-> FSMC_A16 \| PE12 <-> FSMC_D9 \| PF13 <-> FSMC_A7 \|------------------+
mbed_official	354:e67efb2aab0e	342	\| PD12 <-> FSMC_A17 \| PE13 <-> FSMC_D10 \| PF14 <-> FSMC_A8 \|
mbed_official	354:e67efb2aab0e	343	\| PD13 <-> FSMC_A18 \| PE14 <-> FSMC_D11 \| PF15 <-> FSMC_A9 \|
mbed_official	354:e67efb2aab0e	344	\| PD14 <-> FSMC_D0 \| PE15 <-> FSMC_D12 \|------------------+
mbed_official	354:e67efb2aab0e	345	\| PD15 <-> FSMC_D1 \|--------------------+
mbed_official	354:e67efb2aab0e	346	+-------------------+
mbed_official	354:e67efb2aab0e	347	*/
mbed_official	354:e67efb2aab0e	348
mbed_official	354:e67efb2aab0e	349	/* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
mbed_official	354:e67efb2aab0e	350	RCC->AHBENR = 0x000080D8;
mbed_official	354:e67efb2aab0e	351
mbed_official	354:e67efb2aab0e	352	/* Connect PDx pins to FSMC Alternate function */
mbed_official	354:e67efb2aab0e	353	GPIOD->AFR[0] = 0x00CC00CC;
mbed_official	354:e67efb2aab0e	354	GPIOD->AFR[1] = 0xCCCCCCCC;
mbed_official	354:e67efb2aab0e	355	/* Configure PDx pins in Alternate function mode */
mbed_official	354:e67efb2aab0e	356	GPIOD->MODER = 0xAAAA0A0A;
mbed_official	354:e67efb2aab0e	357	/* Configure PDx pins speed to 40 MHz */
mbed_official	354:e67efb2aab0e	358	GPIOD->OSPEEDR = 0xFFFF0F0F;
mbed_official	354:e67efb2aab0e	359	/* Configure PDx pins Output type to push-pull */
mbed_official	354:e67efb2aab0e	360	GPIOD->OTYPER = 0x00000000;
mbed_official	354:e67efb2aab0e	361	/* No pull-up, pull-down for PDx pins */
mbed_official	354:e67efb2aab0e	362	GPIOD->PUPDR = 0x00000000;
mbed_official	354:e67efb2aab0e	363
mbed_official	354:e67efb2aab0e	364	/* Connect PEx pins to FSMC Alternate function */
mbed_official	354:e67efb2aab0e	365	GPIOE->AFR[0] = 0xC00000CC;
mbed_official	354:e67efb2aab0e	366	GPIOE->AFR[1] = 0xCCCCCCCC;
mbed_official	354:e67efb2aab0e	367	/* Configure PEx pins in Alternate function mode */
mbed_official	354:e67efb2aab0e	368	GPIOE->MODER = 0xAAAA800A;
mbed_official	354:e67efb2aab0e	369	/* Configure PEx pins speed to 40 MHz */
mbed_official	354:e67efb2aab0e	370	GPIOE->OSPEEDR = 0xFFFFC00F;
mbed_official	354:e67efb2aab0e	371	/* Configure PEx pins Output type to push-pull */
mbed_official	354:e67efb2aab0e	372	GPIOE->OTYPER = 0x00000000;
mbed_official	354:e67efb2aab0e	373	/* No pull-up, pull-down for PEx pins */
mbed_official	354:e67efb2aab0e	374	GPIOE->PUPDR = 0x00000000;
mbed_official	354:e67efb2aab0e	375
mbed_official	354:e67efb2aab0e	376	/* Connect PFx pins to FSMC Alternate function */
mbed_official	354:e67efb2aab0e	377	GPIOF->AFR[0] = 0x00CCCCCC;
mbed_official	354:e67efb2aab0e	378	GPIOF->AFR[1] = 0xCCCC0000;
mbed_official	354:e67efb2aab0e	379	/* Configure PFx pins in Alternate function mode */
mbed_official	354:e67efb2aab0e	380	GPIOF->MODER = 0xAA000AAA;
mbed_official	354:e67efb2aab0e	381	/* Configure PFx pins speed to 40 MHz */
mbed_official	354:e67efb2aab0e	382	GPIOF->OSPEEDR = 0xFF000FFF;
mbed_official	354:e67efb2aab0e	383	/* Configure PFx pins Output type to push-pull */
mbed_official	354:e67efb2aab0e	384	GPIOF->OTYPER = 0x00000000;
mbed_official	354:e67efb2aab0e	385	/* No pull-up, pull-down for PFx pins */
mbed_official	354:e67efb2aab0e	386	GPIOF->PUPDR = 0x00000000;
mbed_official	354:e67efb2aab0e	387
mbed_official	354:e67efb2aab0e	388	/* Connect PGx pins to FSMC Alternate function */
mbed_official	354:e67efb2aab0e	389	GPIOG->AFR[0] = 0x00CCCCCC;
mbed_official	354:e67efb2aab0e	390	GPIOG->AFR[1] = 0x00000C00;
mbed_official	354:e67efb2aab0e	391	/* Configure PGx pins in Alternate function mode */
mbed_official	354:e67efb2aab0e	392	GPIOG->MODER = 0x00200AAA;
mbed_official	354:e67efb2aab0e	393	/* Configure PGx pins speed to 40 MHz */
mbed_official	354:e67efb2aab0e	394	GPIOG->OSPEEDR = 0x00300FFF;
mbed_official	354:e67efb2aab0e	395	/* Configure PGx pins Output type to push-pull */
mbed_official	354:e67efb2aab0e	396	GPIOG->OTYPER = 0x00000000;
mbed_official	354:e67efb2aab0e	397	/* No pull-up, pull-down for PGx pins */
mbed_official	354:e67efb2aab0e	398	GPIOG->PUPDR = 0x00000000;
mbed_official	354:e67efb2aab0e	399
mbed_official	354:e67efb2aab0e	400	/-- FSMC Configuration ------------------------------------------------------/
mbed_official	354:e67efb2aab0e	401	/* Enable the FSMC interface clock */
mbed_official	354:e67efb2aab0e	402	RCC->AHBENR = 0x400080D8;
mbed_official	354:e67efb2aab0e	403
mbed_official	354:e67efb2aab0e	404	/* Configure and enable Bank1_SRAM3 */
mbed_official	354:e67efb2aab0e	405	FSMC_Bank1->BTCR[4] = 0x00001011;
mbed_official	354:e67efb2aab0e	406	FSMC_Bank1->BTCR[5] = 0x00000300;
mbed_official	354:e67efb2aab0e	407	FSMC_Bank1E->BWTR[4] = 0x0FFFFFFF;
mbed_official	354:e67efb2aab0e	408	/*
mbed_official	354:e67efb2aab0e	409	Bank1_SRAM3 is configured as follow:
mbed_official	354:e67efb2aab0e	410
mbed_official	354:e67efb2aab0e	411	p.FSMC_AddressSetupTime = 0;
mbed_official	354:e67efb2aab0e	412	p.FSMC_AddressHoldTime = 0;
mbed_official	354:e67efb2aab0e	413	p.FSMC_DataSetupTime = 3;
mbed_official	354:e67efb2aab0e	414	p.FSMC_BusTurnAroundDuration = 0;
mbed_official	354:e67efb2aab0e	415	p.FSMC_CLKDivision = 0;
mbed_official	354:e67efb2aab0e	416	p.FSMC_DataLatency = 0;
mbed_official	354:e67efb2aab0e	417	p.FSMC_AccessMode = FSMC_AccessMode_A;
mbed_official	354:e67efb2aab0e	418
mbed_official	354:e67efb2aab0e	419	FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM3;
mbed_official	354:e67efb2aab0e	420	FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
mbed_official	354:e67efb2aab0e	421	FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_SRAM;
mbed_official	354:e67efb2aab0e	422	FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
mbed_official	354:e67efb2aab0e	423	FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
mbed_official	354:e67efb2aab0e	424	FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
mbed_official	354:e67efb2aab0e	425	FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
mbed_official	354:e67efb2aab0e	426	FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
mbed_official	354:e67efb2aab0e	427	FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
mbed_official	354:e67efb2aab0e	428	FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
mbed_official	354:e67efb2aab0e	429	FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
mbed_official	354:e67efb2aab0e	430	FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
mbed_official	354:e67efb2aab0e	431	FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
mbed_official	354:e67efb2aab0e	432	FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
mbed_official	354:e67efb2aab0e	433	FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;
mbed_official	354:e67efb2aab0e	434
mbed_official	354:e67efb2aab0e	435	FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure);
mbed_official	354:e67efb2aab0e	436
mbed_official	354:e67efb2aab0e	437	FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM3, ENABLE);
mbed_official	354:e67efb2aab0e	438	*/
mbed_official	354:e67efb2aab0e	439
mbed_official	354:e67efb2aab0e	440	}
mbed_official	354:e67efb2aab0e	441	#endif /* DATA_IN_ExtSRAM */
mbed_official	354:e67efb2aab0e	442	#endif /* STM32L151xD \|\| STM32L152xD \|\| STM32L162xD */
mbed_official	354:e67efb2aab0e	443
mbed_official	76:aeb1df146756	444	/**
mbed_official	139:e3413eddde57	445	* @brief Configures the System clock source, PLL Multiplier and Divider factors,
mbed_official	139:e3413eddde57	446	* AHB/APBx prescalers and Flash settings
mbed_official	76:aeb1df146756	447	* @note This function should be called only once the RCC clock configuration
mbed_official	76:aeb1df146756	448	* is reset to the default reset state (done in SystemInit() function).
mbed_official	76:aeb1df146756	449	* @param None
mbed_official	76:aeb1df146756	450	* @retval None
mbed_official	76:aeb1df146756	451	*/
mbed_official	129:0182c99221bc	452	void SetSysClock(void)
mbed_official	76:aeb1df146756	453	{
mbed_official	139:e3413eddde57	454	/* 1- Try to start with HSE and external clock */
mbed_official	139:e3413eddde57	455	#if USE_PLL_HSE_EXTC != 0
mbed_official	139:e3413eddde57	456	if (SetSysClock_PLL_HSE(1) == 0)
mbed_official	139:e3413eddde57	457	#endif
mbed_official	139:e3413eddde57	458	{
mbed_official	139:e3413eddde57	459	/* 2- If fail try to start with HSE and external xtal */
mbed_official	139:e3413eddde57	460	#if USE_PLL_HSE_XTAL != 0
mbed_official	139:e3413eddde57	461	if (SetSysClock_PLL_HSE(0) == 0)
mbed_official	139:e3413eddde57	462	#endif
mbed_official	139:e3413eddde57	463	{
mbed_official	139:e3413eddde57	464	/* 3- If fail start with HSI clock */
mbed_official	139:e3413eddde57	465	if (SetSysClock_PLL_HSI() == 0)
mbed_official	139:e3413eddde57	466	{
mbed_official	139:e3413eddde57	467	while(1)
mbed_official	139:e3413eddde57	468	{
mbed_official	139:e3413eddde57	469	// [TODO] Put something here to tell the user that a problem occured...
mbed_official	139:e3413eddde57	470	}
mbed_official	139:e3413eddde57	471	}
mbed_official	139:e3413eddde57	472	}
mbed_official	139:e3413eddde57	473	}
mbed_official	76:aeb1df146756	474
mbed_official	354:e67efb2aab0e	475	/* Output clock on MCO1 pin(PA8) for debugging purpose */
mbed_official	354:e67efb2aab0e	476	//HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1);
mbed_official	139:e3413eddde57	477	}
mbed_official	139:e3413eddde57	478
mbed_official	139:e3413eddde57	479	#if (USE_PLL_HSE_XTAL != 0) \|\| (USE_PLL_HSE_EXTC != 0)
mbed_official	139:e3413eddde57	480	/******************************************************************************/
mbed_official	139:e3413eddde57	481	/* PLL (clocked by HSE) used as System clock source */
mbed_official	139:e3413eddde57	482	/******************************************************************************/
mbed_official	139:e3413eddde57	483	uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
mbed_official	139:e3413eddde57	484	{
mbed_official	354:e67efb2aab0e	485	RCC_ClkInitTypeDef RCC_ClkInitStruct;
mbed_official	354:e67efb2aab0e	486	RCC_OscInitTypeDef RCC_OscInitStruct;
mbed_official	139:e3413eddde57	487
mbed_official	354:e67efb2aab0e	488	/* Used to gain time after DeepSleep in case HSI is used */
mbed_official	354:e67efb2aab0e	489	if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
mbed_official	76:aeb1df146756	490	{
mbed_official	354:e67efb2aab0e	491	return 0;
mbed_official	354:e67efb2aab0e	492	}
mbed_official	354:e67efb2aab0e	493
mbed_official	354:e67efb2aab0e	494	/* The voltage scaling allows optimizing the power consumption when the device is
mbed_official	354:e67efb2aab0e	495	clocked below the maximum system frequency, to update the voltage scaling value
mbed_official	354:e67efb2aab0e	496	regarding system frequency refer to product datasheet. */
mbed_official	354:e67efb2aab0e	497	__PWR_CLK_ENABLE();
mbed_official	354:e67efb2aab0e	498	__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
mbed_official	354:e67efb2aab0e	499
mbed_official	354:e67efb2aab0e	500	/* Enable HSE and HSI48 oscillators and activate PLL with HSE as source */
mbed_official	354:e67efb2aab0e	501	RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE \| RCC_OSCILLATORTYPE_HSI;
mbed_official	354:e67efb2aab0e	502	if (bypass == 0)
mbed_official	354:e67efb2aab0e	503	{
mbed_official	354:e67efb2aab0e	504	RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */
mbed_official	76:aeb1df146756	505	}
mbed_official	76:aeb1df146756	506	else
mbed_official	76:aeb1df146756	507	{
mbed_official	354:e67efb2aab0e	508	RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
mbed_official	76:aeb1df146756	509	}
mbed_official	354:e67efb2aab0e	510	RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
mbed_official	354:e67efb2aab0e	511	// SYSCLK = 24 MHz ((8 MHz * 6) / 2)
mbed_official	354:e67efb2aab0e	512	// USBCLK = 48 MHz (8 MHz * 6) --> USB OK
mbed_official	354:e67efb2aab0e	513	RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
mbed_official	354:e67efb2aab0e	514	RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
mbed_official	354:e67efb2aab0e	515	RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL6;
mbed_official	354:e67efb2aab0e	516	RCC_OscInitStruct.PLL.PLLDIV = RCC_PLL_DIV2;
mbed_official	354:e67efb2aab0e	517	if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
mbed_official	76:aeb1df146756	518	{
mbed_official	139:e3413eddde57	519	return 0; // FAIL
mbed_official	139:e3413eddde57	520	}
mbed_official	354:e67efb2aab0e	521
mbed_official	354:e67efb2aab0e	522	/* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
mbed_official	354:e67efb2aab0e	523	RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK \| RCC_CLOCKTYPE_HCLK \| RCC_CLOCKTYPE_PCLK1 \| RCC_CLOCKTYPE_PCLK2);
mbed_official	354:e67efb2aab0e	524	RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 24 MHz
mbed_official	354:e67efb2aab0e	525	RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 24 MHz
mbed_official	354:e67efb2aab0e	526	RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 24 MHz
mbed_official	354:e67efb2aab0e	527	RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 24 MHz
mbed_official	354:e67efb2aab0e	528	if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
mbed_official	354:e67efb2aab0e	529	{
mbed_official	354:e67efb2aab0e	530	return 0; // FAIL
mbed_official	354:e67efb2aab0e	531	}
mbed_official	354:e67efb2aab0e	532
mbed_official	354:e67efb2aab0e	533	/* Output clock on MCO1 pin(PA8) for debugging purpose */
mbed_official	354:e67efb2aab0e	534	//if (bypass == 0)
mbed_official	354:e67efb2aab0e	535	//HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
mbed_official	354:e67efb2aab0e	536	//else
mbed_official	354:e67efb2aab0e	537	//HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
mbed_official	354:e67efb2aab0e	538
mbed_official	354:e67efb2aab0e	539	return 1; // OK
mbed_official	139:e3413eddde57	540	}
mbed_official	139:e3413eddde57	541	#endif
mbed_official	139:e3413eddde57	542
mbed_official	139:e3413eddde57	543	/******************************************************************************/
mbed_official	139:e3413eddde57	544	/* PLL (clocked by HSI) used as System clock source */
mbed_official	139:e3413eddde57	545	/******************************************************************************/
mbed_official	139:e3413eddde57	546	uint8_t SetSysClock_PLL_HSI(void)
mbed_official	139:e3413eddde57	547	{
mbed_official	354:e67efb2aab0e	548	RCC_ClkInitTypeDef RCC_ClkInitStruct;
mbed_official	354:e67efb2aab0e	549	RCC_OscInitTypeDef RCC_OscInitStruct;
mbed_official	139:e3413eddde57	550
mbed_official	354:e67efb2aab0e	551	/* The voltage scaling allows optimizing the power consumption when the device is
mbed_official	354:e67efb2aab0e	552	clocked below the maximum system frequency, to update the voltage scaling value
mbed_official	354:e67efb2aab0e	553	regarding system frequency refer to product datasheet. */
mbed_official	354:e67efb2aab0e	554	__PWR_CLK_ENABLE();
mbed_official	354:e67efb2aab0e	555	__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
mbed_official	354:e67efb2aab0e	556
mbed_official	354:e67efb2aab0e	557	/* Enable HSI oscillator and activate PLL with HSI as source */
mbed_official	354:e67efb2aab0e	558	RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI \| RCC_OSCILLATORTYPE_HSE;
mbed_official	354:e67efb2aab0e	559	RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
mbed_official	354:e67efb2aab0e	560	RCC_OscInitStruct.HSIState = RCC_HSI_ON;
mbed_official	354:e67efb2aab0e	561	// SYSCLK = 32 MHz ((16 MHz * 4) / 2)
mbed_official	354:e67efb2aab0e	562	// USBCLK = 64 MHz (16 MHz * 4) --> USB not possible
mbed_official	354:e67efb2aab0e	563	RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
mbed_official	354:e67efb2aab0e	564	RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
mbed_official	354:e67efb2aab0e	565	RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL4;
mbed_official	354:e67efb2aab0e	566	RCC_OscInitStruct.PLL.PLLDIV = RCC_PLL_DIV2;
mbed_official	354:e67efb2aab0e	567	if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
mbed_official	139:e3413eddde57	568	{
mbed_official	139:e3413eddde57	569	return 0; // FAIL
mbed_official	76:aeb1df146756	570	}
mbed_official	354:e67efb2aab0e	571
mbed_official	354:e67efb2aab0e	572	/* Poll VOSF bit of in PWR_CSR. Wait until it is reset to 0 */
mbed_official	354:e67efb2aab0e	573	while (__HAL_PWR_GET_FLAG(PWR_FLAG_VOS) != RESET) {};
mbed_official	354:e67efb2aab0e	574
mbed_official	354:e67efb2aab0e	575	/* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
mbed_official	354:e67efb2aab0e	576	RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK \| RCC_CLOCKTYPE_HCLK \| RCC_CLOCKTYPE_PCLK1 \| RCC_CLOCKTYPE_PCLK2);
mbed_official	354:e67efb2aab0e	577	RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz
mbed_official	354:e67efb2aab0e	578	RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 32 MHz
mbed_official	354:e67efb2aab0e	579	RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 32 MHz
mbed_official	354:e67efb2aab0e	580	RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 32 MHz
mbed_official	354:e67efb2aab0e	581	if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
mbed_official	354:e67efb2aab0e	582	{
mbed_official	354:e67efb2aab0e	583	return 0; // FAIL
mbed_official	354:e67efb2aab0e	584	}
mbed_official	354:e67efb2aab0e	585
mbed_official	354:e67efb2aab0e	586	/* Output clock on MCO1 pin(PA8) for debugging purpose */
mbed_official	354:e67efb2aab0e	587	//HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
mbed_official	354:e67efb2aab0e	588
mbed_official	354:e67efb2aab0e	589	return 1; // OK
mbed_official	76:aeb1df146756	590	}
mbed_official	76:aeb1df146756	591
mbed_official	76:aeb1df146756	592	/**
mbed_official	76:aeb1df146756	593	* @}
mbed_official	76:aeb1df146756	594	*/
mbed_official	76:aeb1df146756	595
mbed_official	76:aeb1df146756	596	/**
mbed_official	76:aeb1df146756	597	* @}
mbed_official	76:aeb1df146756	598	*/
mbed_official	76:aeb1df146756	599
mbed_official	76:aeb1df146756	600	/**
mbed_official	76:aeb1df146756	601	* @}
mbed_official	76:aeb1df146756	602	*/
mbed_official	76:aeb1df146756	603
mbed_official	354:e67efb2aab0e	604	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/