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targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/system_stm32l1xx.c@579:53297373a894, 2015-07-01 (annotated)

Committer:: mbed_official
Date:: Wed Jul 01 09:45:11 2015 +0100
Revision:: 579:53297373a894
Parent:: 522:aee49fe30179

Synchronized with git revision d5b4d2ab9c47edb4dc5776e7177b0c2263459081

Full URL: https://github.com/mbedmicro/mbed/commit/d5b4d2ab9c47edb4dc5776e7177b0c2263459081/

Initial version of drivers for SAMR21

Who changed what in which revision?

User	Revision	Line number	New contents of line
mbed_official	522:aee49fe30179	1	/**
mbed_official	522:aee49fe30179	2	******************************************************************************
mbed_official	522:aee49fe30179	3	* @file system_stm32l1xx.c
mbed_official	522:aee49fe30179	4	* @author MCD Application Team
mbed_official	522:aee49fe30179	5	* @version V2.0.0
mbed_official	522:aee49fe30179	6	* @date 5-September-2014
mbed_official	522:aee49fe30179	7	* @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
mbed_official	522:aee49fe30179	8	*
mbed_official	522:aee49fe30179	9	* This file provides two functions and one global variable to be called from
mbed_official	522:aee49fe30179	10	* user application:
mbed_official	522:aee49fe30179	11	* - SystemInit(): This function is called at startup just after reset and
mbed_official	522:aee49fe30179	12	* before branch to main program. This call is made inside
mbed_official	522:aee49fe30179	13	* the "startup_stm32l1xx.s" file.
mbed_official	522:aee49fe30179	14	*
mbed_official	522:aee49fe30179	15	* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
mbed_official	522:aee49fe30179	16	* by the user application to setup the SysTick
mbed_official	522:aee49fe30179	17	* timer or configure other parameters.
mbed_official	522:aee49fe30179	18	*
mbed_official	522:aee49fe30179	19	* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
mbed_official	522:aee49fe30179	20	* be called whenever the core clock is changed
mbed_official	522:aee49fe30179	21	* during program execution.
mbed_official	522:aee49fe30179	22	*
mbed_official	522:aee49fe30179	23	* This file configures the system clock as follows:
mbed_official	522:aee49fe30179	24	*-----------------------------------------------------------------------------
mbed_official	522:aee49fe30179	25	* System clock source \| 1- PLL_HSE_EXTC \| 3- PLL_HSI
mbed_official	522:aee49fe30179	26	* \| (external 8 MHz clock) \| (internal 16 MHz)
mbed_official	522:aee49fe30179	27	* \| 2- PLL_HSE_XTAL \|
mbed_official	522:aee49fe30179	28	* \| (external 8 MHz xtal) \|
mbed_official	522:aee49fe30179	29	*-----------------------------------------------------------------------------
mbed_official	522:aee49fe30179	30	* SYSCLK(MHz) \| 24 \| 32
mbed_official	522:aee49fe30179	31	*-----------------------------------------------------------------------------
mbed_official	522:aee49fe30179	32	* AHBCLK (MHz) \| 24 \| 32
mbed_official	522:aee49fe30179	33	*-----------------------------------------------------------------------------
mbed_official	522:aee49fe30179	34	* APB1CLK (MHz) \| 24 \| 32
mbed_official	522:aee49fe30179	35	*-----------------------------------------------------------------------------
mbed_official	522:aee49fe30179	36	* APB2CLK (MHz) \| 24 \| 32
mbed_official	522:aee49fe30179	37	*-----------------------------------------------------------------------------
mbed_official	522:aee49fe30179	38	* USB capable (48 MHz precise clock) \| YES \| NO
mbed_official	522:aee49fe30179	39	*-----------------------------------------------------------------------------
mbed_official	522:aee49fe30179	40	******************************************************************************
mbed_official	522:aee49fe30179	41	* @attention
mbed_official	522:aee49fe30179	42	*
mbed_official	522:aee49fe30179	43	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
mbed_official	522:aee49fe30179	44	*
mbed_official	522:aee49fe30179	45	* Redistribution and use in source and binary forms, with or without modification,
mbed_official	522:aee49fe30179	46	* are permitted provided that the following conditions are met:
mbed_official	522:aee49fe30179	47	* 1. Redistributions of source code must retain the above copyright notice,
mbed_official	522:aee49fe30179	48	* this list of conditions and the following disclaimer.
mbed_official	522:aee49fe30179	49	* 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official	522:aee49fe30179	50	* this list of conditions and the following disclaimer in the documentation
mbed_official	522:aee49fe30179	51	* and/or other materials provided with the distribution.
mbed_official	522:aee49fe30179	52	* 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official	522:aee49fe30179	53	* may be used to endorse or promote products derived from this software
mbed_official	522:aee49fe30179	54	* without specific prior written permission.
mbed_official	522:aee49fe30179	55	*
mbed_official	522:aee49fe30179	56	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official	522:aee49fe30179	57	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official	522:aee49fe30179	58	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official	522:aee49fe30179	59	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official	522:aee49fe30179	60	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official	522:aee49fe30179	61	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official	522:aee49fe30179	62	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official	522:aee49fe30179	63	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official	522:aee49fe30179	64	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official	522:aee49fe30179	65	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official	522:aee49fe30179	66	*
mbed_official	522:aee49fe30179	67	******************************************************************************
mbed_official	522:aee49fe30179	68	*/
mbed_official	522:aee49fe30179	69
mbed_official	522:aee49fe30179	70	/** @addtogroup CMSIS
mbed_official	522:aee49fe30179	71	* @{
mbed_official	522:aee49fe30179	72	*/
mbed_official	522:aee49fe30179	73
mbed_official	522:aee49fe30179	74	/** @addtogroup stm32l1xx_system
mbed_official	522:aee49fe30179	75	* @{
mbed_official	522:aee49fe30179	76	*/
mbed_official	522:aee49fe30179	77
mbed_official	522:aee49fe30179	78	/** @addtogroup STM32L1xx_System_Private_Includes
mbed_official	522:aee49fe30179	79	* @{
mbed_official	522:aee49fe30179	80	*/
mbed_official	522:aee49fe30179	81
mbed_official	522:aee49fe30179	82	#include "stm32l1xx.h"
mbed_official	522:aee49fe30179	83	#include "hal_tick.h"
mbed_official	522:aee49fe30179	84
mbed_official	522:aee49fe30179	85	/**
mbed_official	522:aee49fe30179	86	* @}
mbed_official	522:aee49fe30179	87	*/
mbed_official	522:aee49fe30179	88
mbed_official	522:aee49fe30179	89	/** @addtogroup STM32L1xx_System_Private_TypesDefinitions
mbed_official	522:aee49fe30179	90	* @{
mbed_official	522:aee49fe30179	91	*/
mbed_official	522:aee49fe30179	92
mbed_official	522:aee49fe30179	93	/**
mbed_official	522:aee49fe30179	94	* @}
mbed_official	522:aee49fe30179	95	*/
mbed_official	522:aee49fe30179	96
mbed_official	522:aee49fe30179	97	/** @addtogroup STM32L1xx_System_Private_Defines
mbed_official	522:aee49fe30179	98	* @{
mbed_official	522:aee49fe30179	99	*/
mbed_official	522:aee49fe30179	100	#if !defined (HSE_VALUE)
mbed_official	522:aee49fe30179	101	#define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz.
mbed_official	522:aee49fe30179	102	This value can be provided and adapted by the user application. */
mbed_official	522:aee49fe30179	103	#endif /* HSE_VALUE */
mbed_official	522:aee49fe30179	104
mbed_official	522:aee49fe30179	105	#if !defined (HSI_VALUE)
mbed_official	522:aee49fe30179	106	#define HSI_VALUE ((uint32_t)16000000) /*!< Default value of the Internal oscillator in Hz.
mbed_official	522:aee49fe30179	107	This value can be provided and adapted by the user application. */
mbed_official	522:aee49fe30179	108	#endif /* HSI_VALUE */
mbed_official	522:aee49fe30179	109
mbed_official	522:aee49fe30179	110	/*!< Uncomment the following line if you need to use external SRAM mounted
mbed_official	522:aee49fe30179	111	on STM32L152D_EVAL board as data memory */
mbed_official	522:aee49fe30179	112	/* #define DATA_IN_ExtSRAM */
mbed_official	522:aee49fe30179	113
mbed_official	522:aee49fe30179	114	/*!< Uncomment the following line if you need to relocate your vector Table in
mbed_official	522:aee49fe30179	115	Internal SRAM. */
mbed_official	522:aee49fe30179	116	/* #define VECT_TAB_SRAM */
mbed_official	522:aee49fe30179	117	#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field.
mbed_official	522:aee49fe30179	118	This value must be a multiple of 0x200. */
mbed_official	522:aee49fe30179	119	/**
mbed_official	522:aee49fe30179	120	* @}
mbed_official	522:aee49fe30179	121	*/
mbed_official	522:aee49fe30179	122
mbed_official	522:aee49fe30179	123	/** @addtogroup STM32L1xx_System_Private_Macros
mbed_official	522:aee49fe30179	124	* @{
mbed_official	522:aee49fe30179	125	*/
mbed_official	522:aee49fe30179	126
mbed_official	522:aee49fe30179	127	/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
mbed_official	522:aee49fe30179	128	#define USE_PLL_HSE_EXTC (0) /* Use external clock */
mbed_official	522:aee49fe30179	129	#define USE_PLL_HSE_XTAL (1) /* Use external xtal */
mbed_official	522:aee49fe30179	130
mbed_official	522:aee49fe30179	131	/**
mbed_official	522:aee49fe30179	132	* @}
mbed_official	522:aee49fe30179	133	*/
mbed_official	522:aee49fe30179	134
mbed_official	522:aee49fe30179	135	/** @addtogroup STM32L1xx_System_Private_Variables
mbed_official	522:aee49fe30179	136	* @{
mbed_official	522:aee49fe30179	137	*/
mbed_official	522:aee49fe30179	138	/* This variable is updated in three ways:
mbed_official	522:aee49fe30179	139	1) by calling CMSIS function SystemCoreClockUpdate()
mbed_official	522:aee49fe30179	140	2) by calling HAL API function HAL_RCC_GetHCLKFreq()
mbed_official	522:aee49fe30179	141	3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
mbed_official	522:aee49fe30179	142	Note: If you use this function to configure the system clock; then there
mbed_official	522:aee49fe30179	143	is no need to call the 2 first functions listed above, since SystemCoreClock
mbed_official	522:aee49fe30179	144	variable is updated automatically.
mbed_official	522:aee49fe30179	145	*/
mbed_official	522:aee49fe30179	146	uint32_t SystemCoreClock = 32000000; /* Default with HSI. Will be updated if HSE is used */
mbed_official	522:aee49fe30179	147	const uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48};
mbed_official	522:aee49fe30179	148	const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
mbed_official	522:aee49fe30179	149
mbed_official	522:aee49fe30179	150	/**
mbed_official	522:aee49fe30179	151	* @}
mbed_official	522:aee49fe30179	152	*/
mbed_official	522:aee49fe30179	153
mbed_official	522:aee49fe30179	154	/** @addtogroup STM32L1xx_System_Private_FunctionPrototypes
mbed_official	522:aee49fe30179	155	* @{
mbed_official	522:aee49fe30179	156	*/
mbed_official	522:aee49fe30179	157
mbed_official	522:aee49fe30179	158	#if defined (STM32L151xD) \|\| defined (STM32L152xD) \|\| defined (STM32L162xD)
mbed_official	522:aee49fe30179	159	#ifdef DATA_IN_ExtSRAM
mbed_official	522:aee49fe30179	160	static void SystemInit_ExtMemCtl(void);
mbed_official	522:aee49fe30179	161	#endif /* DATA_IN_ExtSRAM */
mbed_official	522:aee49fe30179	162	#endif /* STM32L151xD \|\| STM32L152xD \|\| STM32L162xD */
mbed_official	522:aee49fe30179	163
mbed_official	522:aee49fe30179	164	#if (USE_PLL_HSE_XTAL != 0) \|\| (USE_PLL_HSE_EXTC != 0)
mbed_official	522:aee49fe30179	165	uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
mbed_official	522:aee49fe30179	166	#endif
mbed_official	522:aee49fe30179	167
mbed_official	522:aee49fe30179	168	uint8_t SetSysClock_PLL_HSI(void);
mbed_official	522:aee49fe30179	169
mbed_official	522:aee49fe30179	170	/**
mbed_official	522:aee49fe30179	171	* @}
mbed_official	522:aee49fe30179	172	*/
mbed_official	522:aee49fe30179	173
mbed_official	522:aee49fe30179	174	/** @addtogroup STM32L1xx_System_Private_Functions
mbed_official	522:aee49fe30179	175	* @{
mbed_official	522:aee49fe30179	176	*/
mbed_official	522:aee49fe30179	177
mbed_official	522:aee49fe30179	178	/**
mbed_official	522:aee49fe30179	179	* @brief Setup the microcontroller system.
mbed_official	522:aee49fe30179	180	* Initialize the Embedded Flash Interface, the PLL and update the
mbed_official	522:aee49fe30179	181	* SystemCoreClock variable.
mbed_official	522:aee49fe30179	182	* @param None
mbed_official	522:aee49fe30179	183	* @retval None
mbed_official	522:aee49fe30179	184	*/
mbed_official	522:aee49fe30179	185	void SystemInit (void)
mbed_official	522:aee49fe30179	186	{
mbed_official	522:aee49fe30179	187	/!< Set MSION bit /
mbed_official	522:aee49fe30179	188	RCC->CR \|= (uint32_t)0x00000100;
mbed_official	522:aee49fe30179	189
mbed_official	522:aee49fe30179	190	/!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits /
mbed_official	522:aee49fe30179	191	RCC->CFGR &= (uint32_t)0x88FFC00C;
mbed_official	522:aee49fe30179	192
mbed_official	522:aee49fe30179	193	/!< Reset HSION, HSEON, CSSON and PLLON bits /
mbed_official	522:aee49fe30179	194	RCC->CR &= (uint32_t)0xEEFEFFFE;
mbed_official	522:aee49fe30179	195
mbed_official	522:aee49fe30179	196	/!< Reset HSEBYP bit /
mbed_official	522:aee49fe30179	197	RCC->CR &= (uint32_t)0xFFFBFFFF;
mbed_official	522:aee49fe30179	198
mbed_official	522:aee49fe30179	199	/!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits /
mbed_official	522:aee49fe30179	200	RCC->CFGR &= (uint32_t)0xFF02FFFF;
mbed_official	522:aee49fe30179	201
mbed_official	522:aee49fe30179	202	/!< Disable all interrupts /
mbed_official	522:aee49fe30179	203	RCC->CIR = 0x00000000;
mbed_official	522:aee49fe30179	204
mbed_official	522:aee49fe30179	205	#ifdef DATA_IN_ExtSRAM
mbed_official	522:aee49fe30179	206	SystemInit_ExtMemCtl();
mbed_official	522:aee49fe30179	207	#endif /* DATA_IN_ExtSRAM */
mbed_official	522:aee49fe30179	208
mbed_official	522:aee49fe30179	209	#ifdef VECT_TAB_SRAM
mbed_official	522:aee49fe30179	210	SCB->VTOR = SRAM_BASE \| VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
mbed_official	522:aee49fe30179	211	#else
mbed_official	522:aee49fe30179	212	SCB->VTOR = FLASH_BASE \| VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
mbed_official	522:aee49fe30179	213	#endif
mbed_official	522:aee49fe30179	214
mbed_official	522:aee49fe30179	215	/* Configure the Cube driver */
mbed_official	522:aee49fe30179	216	SystemCoreClock = 16000000; // At this stage the HSI is used as system clock
mbed_official	522:aee49fe30179	217	HAL_Init();
mbed_official	522:aee49fe30179	218
mbed_official	522:aee49fe30179	219	/* Configure the System clock source, PLL Multiplier and Divider factors,
mbed_official	522:aee49fe30179	220	AHB/APBx prescalers and Flash settings */
mbed_official	522:aee49fe30179	221	SetSysClock();
mbed_official	522:aee49fe30179	222
mbed_official	522:aee49fe30179	223	/* Reset the timer to avoid issues after the RAM initialization */
mbed_official	522:aee49fe30179	224	TIM_MST_RESET_ON;
mbed_official	522:aee49fe30179	225	TIM_MST_RESET_OFF;
mbed_official	522:aee49fe30179	226	}
mbed_official	522:aee49fe30179	227
mbed_official	522:aee49fe30179	228	/**
mbed_official	522:aee49fe30179	229	* @brief Update SystemCoreClock according to Clock Register Values
mbed_official	522:aee49fe30179	230	* The SystemCoreClock variable contains the core clock (HCLK), it can
mbed_official	522:aee49fe30179	231	* be used by the user application to setup the SysTick timer or configure
mbed_official	522:aee49fe30179	232	* other parameters.
mbed_official	522:aee49fe30179	233	*
mbed_official	522:aee49fe30179	234	* @note Each time the core clock (HCLK) changes, this function must be called
mbed_official	522:aee49fe30179	235	* to update SystemCoreClock variable value. Otherwise, any configuration
mbed_official	522:aee49fe30179	236	* based on this variable will be incorrect.
mbed_official	522:aee49fe30179	237	*
mbed_official	522:aee49fe30179	238	* @note - The system frequency computed by this function is not the real
mbed_official	522:aee49fe30179	239	* frequency in the chip. It is calculated based on the predefined
mbed_official	522:aee49fe30179	240	* constant and the selected clock source:
mbed_official	522:aee49fe30179	241	*
mbed_official	522:aee49fe30179	242	* - If SYSCLK source is MSI, SystemCoreClock will contain the MSI
mbed_official	522:aee49fe30179	243	* value as defined by the MSI range.
mbed_official	522:aee49fe30179	244	*
mbed_official	522:aee49fe30179	245	* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
mbed_official	522:aee49fe30179	246	*
mbed_official	522:aee49fe30179	247	* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
mbed_official	522:aee49fe30179	248	*
mbed_official	522:aee49fe30179	249	* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
mbed_official	522:aee49fe30179	250	* or HSI_VALUE(*) multiplied/divided by the PLL factors.
mbed_official	522:aee49fe30179	251	*
mbed_official	522:aee49fe30179	252	* (*) HSI_VALUE is a constant defined in stm32l1xx.h file (default value
mbed_official	522:aee49fe30179	253	* 16 MHz) but the real value may vary depending on the variations
mbed_official	522:aee49fe30179	254	* in voltage and temperature.
mbed_official	522:aee49fe30179	255	*
mbed_official	522:aee49fe30179	256	* (**) HSE_VALUE is a constant defined in stm32l1xx.h file (default value
mbed_official	522:aee49fe30179	257	* 8 MHz), user has to ensure that HSE_VALUE is same as the real
mbed_official	522:aee49fe30179	258	* frequency of the crystal used. Otherwise, this function may
mbed_official	522:aee49fe30179	259	* have wrong result.
mbed_official	522:aee49fe30179	260	*
mbed_official	522:aee49fe30179	261	* - The result of this function could be not correct when using fractional
mbed_official	522:aee49fe30179	262	* value for HSE crystal.
mbed_official	522:aee49fe30179	263	* @param None
mbed_official	522:aee49fe30179	264	* @retval None
mbed_official	522:aee49fe30179	265	*/
mbed_official	522:aee49fe30179	266	void SystemCoreClockUpdate (void)
mbed_official	522:aee49fe30179	267	{
mbed_official	522:aee49fe30179	268	uint32_t tmp = 0, pllmul = 0, plldiv = 0, pllsource = 0, msirange = 0;
mbed_official	522:aee49fe30179	269
mbed_official	522:aee49fe30179	270	/* Get SYSCLK source -------------------------------------------------------*/
mbed_official	522:aee49fe30179	271	tmp = RCC->CFGR & RCC_CFGR_SWS;
mbed_official	522:aee49fe30179	272
mbed_official	522:aee49fe30179	273	switch (tmp)
mbed_official	522:aee49fe30179	274	{
mbed_official	522:aee49fe30179	275	case 0x00: /* MSI used as system clock */
mbed_official	522:aee49fe30179	276	msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;
mbed_official	522:aee49fe30179	277	SystemCoreClock = (32768 * (1 << (msirange + 1)));
mbed_official	522:aee49fe30179	278	break;
mbed_official	522:aee49fe30179	279	case 0x04: /* HSI used as system clock */
mbed_official	522:aee49fe30179	280	SystemCoreClock = HSI_VALUE;
mbed_official	522:aee49fe30179	281	break;
mbed_official	522:aee49fe30179	282	case 0x08: /* HSE used as system clock */
mbed_official	522:aee49fe30179	283	SystemCoreClock = HSE_VALUE;
mbed_official	522:aee49fe30179	284	break;
mbed_official	522:aee49fe30179	285	case 0x0C: /* PLL used as system clock */
mbed_official	522:aee49fe30179	286	/* Get PLL clock source and multiplication factor ----------------------*/
mbed_official	522:aee49fe30179	287	pllmul = RCC->CFGR & RCC_CFGR_PLLMUL;
mbed_official	522:aee49fe30179	288	plldiv = RCC->CFGR & RCC_CFGR_PLLDIV;
mbed_official	522:aee49fe30179	289	pllmul = PLLMulTable[(pllmul >> 18)];
mbed_official	522:aee49fe30179	290	plldiv = (plldiv >> 22) + 1;
mbed_official	522:aee49fe30179	291
mbed_official	522:aee49fe30179	292	pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
mbed_official	522:aee49fe30179	293
mbed_official	522:aee49fe30179	294	if (pllsource == 0x00)
mbed_official	522:aee49fe30179	295	{
mbed_official	522:aee49fe30179	296	/* HSI oscillator clock selected as PLL clock entry */
mbed_official	522:aee49fe30179	297	SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv);
mbed_official	522:aee49fe30179	298	}
mbed_official	522:aee49fe30179	299	else
mbed_official	522:aee49fe30179	300	{
mbed_official	522:aee49fe30179	301	/* HSE selected as PLL clock entry */
mbed_official	522:aee49fe30179	302	SystemCoreClock = (((HSE_VALUE) * pllmul) / plldiv);
mbed_official	522:aee49fe30179	303	}
mbed_official	522:aee49fe30179	304	break;
mbed_official	522:aee49fe30179	305	default: /* MSI used as system clock */
mbed_official	522:aee49fe30179	306	msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;
mbed_official	522:aee49fe30179	307	SystemCoreClock = (32768 * (1 << (msirange + 1)));
mbed_official	522:aee49fe30179	308	break;
mbed_official	522:aee49fe30179	309	}
mbed_official	522:aee49fe30179	310	/* Compute HCLK clock frequency --------------------------------------------*/
mbed_official	522:aee49fe30179	311	/* Get HCLK prescaler */
mbed_official	522:aee49fe30179	312	tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
mbed_official	522:aee49fe30179	313	/* HCLK clock frequency */
mbed_official	522:aee49fe30179	314	SystemCoreClock >>= tmp;
mbed_official	522:aee49fe30179	315	}
mbed_official	522:aee49fe30179	316
mbed_official	522:aee49fe30179	317	#if defined (STM32L151xD) \|\| defined (STM32L152xD) \|\| defined (STM32L162xD)
mbed_official	522:aee49fe30179	318	#ifdef DATA_IN_ExtSRAM
mbed_official	522:aee49fe30179	319	/**
mbed_official	522:aee49fe30179	320	* @brief Setup the external memory controller.
mbed_official	522:aee49fe30179	321	* Called in SystemInit() function before jump to main.
mbed_official	522:aee49fe30179	322	* This function configures the external SRAM mounted on STM32L152D_EVAL board
mbed_official	522:aee49fe30179	323	* This SRAM will be used as program data memory (including heap and stack).
mbed_official	522:aee49fe30179	324	* @param None
mbed_official	522:aee49fe30179	325	* @retval None
mbed_official	522:aee49fe30179	326	*/
mbed_official	522:aee49fe30179	327	void SystemInit_ExtMemCtl(void)
mbed_official	522:aee49fe30179	328	{
mbed_official	522:aee49fe30179	329	/-- GPIOs Configuration -----------------------------------------------------/
mbed_official	522:aee49fe30179	330	/*
mbed_official	522:aee49fe30179	331	+-------------------+--------------------+------------------+------------------+
mbed_official	522:aee49fe30179	332	+ SRAM pins assignment +
mbed_official	522:aee49fe30179	333	+-------------------+--------------------+------------------+------------------+
mbed_official	522:aee49fe30179	334	\| PD0 <-> FSMC_D2 \| PE0 <-> FSMC_NBL0 \| PF0 <-> FSMC_A0 \| PG0 <-> FSMC_A10 \|
mbed_official	522:aee49fe30179	335	\| PD1 <-> FSMC_D3 \| PE1 <-> FSMC_NBL1 \| PF1 <-> FSMC_A1 \| PG1 <-> FSMC_A11 \|
mbed_official	522:aee49fe30179	336	\| PD4 <-> FSMC_NOE \| PE7 <-> FSMC_D4 \| PF2 <-> FSMC_A2 \| PG2 <-> FSMC_A12 \|
mbed_official	522:aee49fe30179	337	\| PD5 <-> FSMC_NWE \| PE8 <-> FSMC_D5 \| PF3 <-> FSMC_A3 \| PG3 <-> FSMC_A13 \|
mbed_official	522:aee49fe30179	338	\| PD8 <-> FSMC_D13 \| PE9 <-> FSMC_D6 \| PF4 <-> FSMC_A4 \| PG4 <-> FSMC_A14 \|
mbed_official	522:aee49fe30179	339	\| PD9 <-> FSMC_D14 \| PE10 <-> FSMC_D7 \| PF5 <-> FSMC_A5 \| PG5 <-> FSMC_A15 \|
mbed_official	522:aee49fe30179	340	\| PD10 <-> FSMC_D15 \| PE11 <-> FSMC_D8 \| PF12 <-> FSMC_A6 \| PG10<-> FSMC_NE2 \|
mbed_official	522:aee49fe30179	341	\| PD11 <-> FSMC_A16 \| PE12 <-> FSMC_D9 \| PF13 <-> FSMC_A7 \|------------------+
mbed_official	522:aee49fe30179	342	\| PD12 <-> FSMC_A17 \| PE13 <-> FSMC_D10 \| PF14 <-> FSMC_A8 \|
mbed_official	522:aee49fe30179	343	\| PD13 <-> FSMC_A18 \| PE14 <-> FSMC_D11 \| PF15 <-> FSMC_A9 \|
mbed_official	522:aee49fe30179	344	\| PD14 <-> FSMC_D0 \| PE15 <-> FSMC_D12 \|------------------+
mbed_official	522:aee49fe30179	345	\| PD15 <-> FSMC_D1 \|--------------------+
mbed_official	522:aee49fe30179	346	+-------------------+
mbed_official	522:aee49fe30179	347	*/
mbed_official	522:aee49fe30179	348
mbed_official	522:aee49fe30179	349	/* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
mbed_official	522:aee49fe30179	350	RCC->AHBENR = 0x000080D8;
mbed_official	522:aee49fe30179	351
mbed_official	522:aee49fe30179	352	/* Connect PDx pins to FSMC Alternate function */
mbed_official	522:aee49fe30179	353	GPIOD->AFR[0] = 0x00CC00CC;
mbed_official	522:aee49fe30179	354	GPIOD->AFR[1] = 0xCCCCCCCC;
mbed_official	522:aee49fe30179	355	/* Configure PDx pins in Alternate function mode */
mbed_official	522:aee49fe30179	356	GPIOD->MODER = 0xAAAA0A0A;
mbed_official	522:aee49fe30179	357	/* Configure PDx pins speed to 40 MHz */
mbed_official	522:aee49fe30179	358	GPIOD->OSPEEDR = 0xFFFF0F0F;
mbed_official	522:aee49fe30179	359	/* Configure PDx pins Output type to push-pull */
mbed_official	522:aee49fe30179	360	GPIOD->OTYPER = 0x00000000;
mbed_official	522:aee49fe30179	361	/* No pull-up, pull-down for PDx pins */
mbed_official	522:aee49fe30179	362	GPIOD->PUPDR = 0x00000000;
mbed_official	522:aee49fe30179	363
mbed_official	522:aee49fe30179	364	/* Connect PEx pins to FSMC Alternate function */
mbed_official	522:aee49fe30179	365	GPIOE->AFR[0] = 0xC00000CC;
mbed_official	522:aee49fe30179	366	GPIOE->AFR[1] = 0xCCCCCCCC;
mbed_official	522:aee49fe30179	367	/* Configure PEx pins in Alternate function mode */
mbed_official	522:aee49fe30179	368	GPIOE->MODER = 0xAAAA800A;
mbed_official	522:aee49fe30179	369	/* Configure PEx pins speed to 40 MHz */
mbed_official	522:aee49fe30179	370	GPIOE->OSPEEDR = 0xFFFFC00F;
mbed_official	522:aee49fe30179	371	/* Configure PEx pins Output type to push-pull */
mbed_official	522:aee49fe30179	372	GPIOE->OTYPER = 0x00000000;
mbed_official	522:aee49fe30179	373	/* No pull-up, pull-down for PEx pins */
mbed_official	522:aee49fe30179	374	GPIOE->PUPDR = 0x00000000;
mbed_official	522:aee49fe30179	375
mbed_official	522:aee49fe30179	376	/* Connect PFx pins to FSMC Alternate function */
mbed_official	522:aee49fe30179	377	GPIOF->AFR[0] = 0x00CCCCCC;
mbed_official	522:aee49fe30179	378	GPIOF->AFR[1] = 0xCCCC0000;
mbed_official	522:aee49fe30179	379	/* Configure PFx pins in Alternate function mode */
mbed_official	522:aee49fe30179	380	GPIOF->MODER = 0xAA000AAA;
mbed_official	522:aee49fe30179	381	/* Configure PFx pins speed to 40 MHz */
mbed_official	522:aee49fe30179	382	GPIOF->OSPEEDR = 0xFF000FFF;
mbed_official	522:aee49fe30179	383	/* Configure PFx pins Output type to push-pull */
mbed_official	522:aee49fe30179	384	GPIOF->OTYPER = 0x00000000;
mbed_official	522:aee49fe30179	385	/* No pull-up, pull-down for PFx pins */
mbed_official	522:aee49fe30179	386	GPIOF->PUPDR = 0x00000000;
mbed_official	522:aee49fe30179	387
mbed_official	522:aee49fe30179	388	/* Connect PGx pins to FSMC Alternate function */
mbed_official	522:aee49fe30179	389	GPIOG->AFR[0] = 0x00CCCCCC;
mbed_official	522:aee49fe30179	390	GPIOG->AFR[1] = 0x00000C00;
mbed_official	522:aee49fe30179	391	/* Configure PGx pins in Alternate function mode */
mbed_official	522:aee49fe30179	392	GPIOG->MODER = 0x00200AAA;
mbed_official	522:aee49fe30179	393	/* Configure PGx pins speed to 40 MHz */
mbed_official	522:aee49fe30179	394	GPIOG->OSPEEDR = 0x00300FFF;
mbed_official	522:aee49fe30179	395	/* Configure PGx pins Output type to push-pull */
mbed_official	522:aee49fe30179	396	GPIOG->OTYPER = 0x00000000;
mbed_official	522:aee49fe30179	397	/* No pull-up, pull-down for PGx pins */
mbed_official	522:aee49fe30179	398	GPIOG->PUPDR = 0x00000000;
mbed_official	522:aee49fe30179	399
mbed_official	522:aee49fe30179	400	/-- FSMC Configuration ------------------------------------------------------/
mbed_official	522:aee49fe30179	401	/* Enable the FSMC interface clock */
mbed_official	522:aee49fe30179	402	RCC->AHBENR = 0x400080D8;
mbed_official	522:aee49fe30179	403
mbed_official	522:aee49fe30179	404	/* Configure and enable Bank1_SRAM3 */
mbed_official	522:aee49fe30179	405	FSMC_Bank1->BTCR[4] = 0x00001011;
mbed_official	522:aee49fe30179	406	FSMC_Bank1->BTCR[5] = 0x00000300;
mbed_official	522:aee49fe30179	407	FSMC_Bank1E->BWTR[4] = 0x0FFFFFFF;
mbed_official	522:aee49fe30179	408	/*
mbed_official	522:aee49fe30179	409	Bank1_SRAM3 is configured as follow:
mbed_official	522:aee49fe30179	410
mbed_official	522:aee49fe30179	411	p.FSMC_AddressSetupTime = 0;
mbed_official	522:aee49fe30179	412	p.FSMC_AddressHoldTime = 0;
mbed_official	522:aee49fe30179	413	p.FSMC_DataSetupTime = 3;
mbed_official	522:aee49fe30179	414	p.FSMC_BusTurnAroundDuration = 0;
mbed_official	522:aee49fe30179	415	p.FSMC_CLKDivision = 0;
mbed_official	522:aee49fe30179	416	p.FSMC_DataLatency = 0;
mbed_official	522:aee49fe30179	417	p.FSMC_AccessMode = FSMC_AccessMode_A;
mbed_official	522:aee49fe30179	418
mbed_official	522:aee49fe30179	419	FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM3;
mbed_official	522:aee49fe30179	420	FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
mbed_official	522:aee49fe30179	421	FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_SRAM;
mbed_official	522:aee49fe30179	422	FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
mbed_official	522:aee49fe30179	423	FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
mbed_official	522:aee49fe30179	424	FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
mbed_official	522:aee49fe30179	425	FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
mbed_official	522:aee49fe30179	426	FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
mbed_official	522:aee49fe30179	427	FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
mbed_official	522:aee49fe30179	428	FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
mbed_official	522:aee49fe30179	429	FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
mbed_official	522:aee49fe30179	430	FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
mbed_official	522:aee49fe30179	431	FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
mbed_official	522:aee49fe30179	432	FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
mbed_official	522:aee49fe30179	433	FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;
mbed_official	522:aee49fe30179	434
mbed_official	522:aee49fe30179	435	FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure);
mbed_official	522:aee49fe30179	436
mbed_official	522:aee49fe30179	437	FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM3, ENABLE);
mbed_official	522:aee49fe30179	438	*/
mbed_official	522:aee49fe30179	439
mbed_official	522:aee49fe30179	440	}
mbed_official	522:aee49fe30179	441	#endif /* DATA_IN_ExtSRAM */
mbed_official	522:aee49fe30179	442	#endif /* STM32L151xD \|\| STM32L152xD \|\| STM32L162xD */
mbed_official	522:aee49fe30179	443
mbed_official	522:aee49fe30179	444	/**
mbed_official	522:aee49fe30179	445	* @brief Configures the System clock source, PLL Multiplier and Divider factors,
mbed_official	522:aee49fe30179	446	* AHB/APBx prescalers and Flash settings
mbed_official	522:aee49fe30179	447	* @note This function should be called only once the RCC clock configuration
mbed_official	522:aee49fe30179	448	* is reset to the default reset state (done in SystemInit() function).
mbed_official	522:aee49fe30179	449	* @param None
mbed_official	522:aee49fe30179	450	* @retval None
mbed_official	522:aee49fe30179	451	*/
mbed_official	522:aee49fe30179	452	void SetSysClock(void)
mbed_official	522:aee49fe30179	453	{
mbed_official	522:aee49fe30179	454	/* 1- Try to start with HSE and external clock */
mbed_official	522:aee49fe30179	455	#if USE_PLL_HSE_EXTC != 0
mbed_official	522:aee49fe30179	456	if (SetSysClock_PLL_HSE(1) == 0)
mbed_official	522:aee49fe30179	457	#endif
mbed_official	522:aee49fe30179	458	{
mbed_official	522:aee49fe30179	459	/* 2- If fail try to start with HSE and external xtal */
mbed_official	522:aee49fe30179	460	#if USE_PLL_HSE_XTAL != 0
mbed_official	522:aee49fe30179	461	if (SetSysClock_PLL_HSE(0) == 0)
mbed_official	522:aee49fe30179	462	#endif
mbed_official	522:aee49fe30179	463	{
mbed_official	522:aee49fe30179	464	/* 3- If fail start with HSI clock */
mbed_official	522:aee49fe30179	465	if (SetSysClock_PLL_HSI() == 0)
mbed_official	522:aee49fe30179	466	{
mbed_official	522:aee49fe30179	467	while(1)
mbed_official	522:aee49fe30179	468	{
mbed_official	522:aee49fe30179	469	// [TODO] Put something here to tell the user that a problem occured...
mbed_official	522:aee49fe30179	470	}
mbed_official	522:aee49fe30179	471	}
mbed_official	522:aee49fe30179	472	}
mbed_official	522:aee49fe30179	473	}
mbed_official	522:aee49fe30179	474
mbed_official	522:aee49fe30179	475	/* Output clock on MCO1 pin(PA8) for debugging purpose */
mbed_official	522:aee49fe30179	476	//HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1);
mbed_official	522:aee49fe30179	477	}
mbed_official	522:aee49fe30179	478
mbed_official	522:aee49fe30179	479	#if (USE_PLL_HSE_XTAL != 0) \|\| (USE_PLL_HSE_EXTC != 0)
mbed_official	522:aee49fe30179	480	/******************************************************************************/
mbed_official	522:aee49fe30179	481	/* PLL (clocked by HSE) used as System clock source */
mbed_official	522:aee49fe30179	482	/******************************************************************************/
mbed_official	522:aee49fe30179	483	uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
mbed_official	522:aee49fe30179	484	{
mbed_official	522:aee49fe30179	485	RCC_ClkInitTypeDef RCC_ClkInitStruct;
mbed_official	522:aee49fe30179	486	RCC_OscInitTypeDef RCC_OscInitStruct;
mbed_official	522:aee49fe30179	487
mbed_official	522:aee49fe30179	488	if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL)
mbed_official	522:aee49fe30179	489	return 1; // already on HSE PLL, could occur from deepsleep waking
mbed_official	522:aee49fe30179	490
mbed_official	522:aee49fe30179	491	/* Used to gain time after DeepSleep in case HSI is used */
mbed_official	522:aee49fe30179	492	if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
mbed_official	522:aee49fe30179	493	{
mbed_official	522:aee49fe30179	494	return 0;
mbed_official	522:aee49fe30179	495	}
mbed_official	522:aee49fe30179	496
mbed_official	522:aee49fe30179	497	/* The voltage scaling allows optimizing the power consumption when the device is
mbed_official	522:aee49fe30179	498	clocked below the maximum system frequency, to update the voltage scaling value
mbed_official	522:aee49fe30179	499	regarding system frequency refer to product datasheet. */
mbed_official	522:aee49fe30179	500	__PWR_CLK_ENABLE();
mbed_official	522:aee49fe30179	501	__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
mbed_official	522:aee49fe30179	502
mbed_official	522:aee49fe30179	503	/* Enable HSE and HSI48 oscillators and activate PLL with HSE as source */
mbed_official	522:aee49fe30179	504	RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE \| RCC_OSCILLATORTYPE_HSI;
mbed_official	522:aee49fe30179	505	if (bypass == 0)
mbed_official	522:aee49fe30179	506	{
mbed_official	522:aee49fe30179	507	RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */
mbed_official	522:aee49fe30179	508	}
mbed_official	522:aee49fe30179	509	else
mbed_official	522:aee49fe30179	510	{
mbed_official	522:aee49fe30179	511	RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
mbed_official	522:aee49fe30179	512	}
mbed_official	522:aee49fe30179	513	RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
mbed_official	522:aee49fe30179	514	// SYSCLK = 24 MHz ((8 MHz * 6) / 2)
mbed_official	522:aee49fe30179	515	// USBCLK = 48 MHz (8 MHz * 6) --> USB OK
mbed_official	522:aee49fe30179	516	RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
mbed_official	522:aee49fe30179	517	RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
mbed_official	522:aee49fe30179	518	RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL6;
mbed_official	522:aee49fe30179	519	RCC_OscInitStruct.PLL.PLLDIV = RCC_PLL_DIV2;
mbed_official	522:aee49fe30179	520	if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
mbed_official	522:aee49fe30179	521	{
mbed_official	522:aee49fe30179	522	return 0; // FAIL
mbed_official	522:aee49fe30179	523	}
mbed_official	522:aee49fe30179	524
mbed_official	522:aee49fe30179	525	/* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
mbed_official	522:aee49fe30179	526	RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK \| RCC_CLOCKTYPE_HCLK \| RCC_CLOCKTYPE_PCLK1 \| RCC_CLOCKTYPE_PCLK2);
mbed_official	522:aee49fe30179	527	RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 24 MHz
mbed_official	522:aee49fe30179	528	RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 24 MHz
mbed_official	522:aee49fe30179	529	RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 24 MHz
mbed_official	522:aee49fe30179	530	RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 24 MHz
mbed_official	522:aee49fe30179	531	if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
mbed_official	522:aee49fe30179	532	{
mbed_official	522:aee49fe30179	533	return 0; // FAIL
mbed_official	522:aee49fe30179	534	}
mbed_official	522:aee49fe30179	535
mbed_official	522:aee49fe30179	536	/* Output clock on MCO1 pin(PA8) for debugging purpose */
mbed_official	522:aee49fe30179	537	//if (bypass == 0)
mbed_official	522:aee49fe30179	538	//HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
mbed_official	522:aee49fe30179	539	//else
mbed_official	522:aee49fe30179	540	//HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
mbed_official	522:aee49fe30179	541
mbed_official	522:aee49fe30179	542	return 1; // OK
mbed_official	522:aee49fe30179	543	}
mbed_official	522:aee49fe30179	544	#endif
mbed_official	522:aee49fe30179	545
mbed_official	522:aee49fe30179	546	/******************************************************************************/
mbed_official	522:aee49fe30179	547	/* PLL (clocked by HSI) used as System clock source */
mbed_official	522:aee49fe30179	548	/******************************************************************************/
mbed_official	522:aee49fe30179	549	uint8_t SetSysClock_PLL_HSI(void)
mbed_official	522:aee49fe30179	550	{
mbed_official	522:aee49fe30179	551	RCC_ClkInitTypeDef RCC_ClkInitStruct;
mbed_official	522:aee49fe30179	552	RCC_OscInitTypeDef RCC_OscInitStruct;
mbed_official	522:aee49fe30179	553
mbed_official	522:aee49fe30179	554	/* The voltage scaling allows optimizing the power consumption when the device is
mbed_official	522:aee49fe30179	555	clocked below the maximum system frequency, to update the voltage scaling value
mbed_official	522:aee49fe30179	556	regarding system frequency refer to product datasheet. */
mbed_official	522:aee49fe30179	557	__PWR_CLK_ENABLE();
mbed_official	522:aee49fe30179	558	__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
mbed_official	522:aee49fe30179	559
mbed_official	522:aee49fe30179	560	/* Enable HSI oscillator and activate PLL with HSI as source */
mbed_official	522:aee49fe30179	561	RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI \| RCC_OSCILLATORTYPE_HSE;
mbed_official	522:aee49fe30179	562	RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
mbed_official	522:aee49fe30179	563	RCC_OscInitStruct.HSIState = RCC_HSI_ON;
mbed_official	522:aee49fe30179	564	// SYSCLK = 32 MHz ((16 MHz * 4) / 2)
mbed_official	522:aee49fe30179	565	// USBCLK = 64 MHz (16 MHz * 4) --> USB not possible
mbed_official	522:aee49fe30179	566	RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
mbed_official	522:aee49fe30179	567	RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
mbed_official	522:aee49fe30179	568	RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL4;
mbed_official	522:aee49fe30179	569	RCC_OscInitStruct.PLL.PLLDIV = RCC_PLL_DIV2;
mbed_official	522:aee49fe30179	570	if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
mbed_official	522:aee49fe30179	571	{
mbed_official	522:aee49fe30179	572	return 0; // FAIL
mbed_official	522:aee49fe30179	573	}
mbed_official	522:aee49fe30179	574
mbed_official	522:aee49fe30179	575	/* Poll VOSF bit of in PWR_CSR. Wait until it is reset to 0 */
mbed_official	522:aee49fe30179	576	while (__HAL_PWR_GET_FLAG(PWR_FLAG_VOS) != RESET) {};
mbed_official	522:aee49fe30179	577
mbed_official	522:aee49fe30179	578	/* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
mbed_official	522:aee49fe30179	579	RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK \| RCC_CLOCKTYPE_HCLK \| RCC_CLOCKTYPE_PCLK1 \| RCC_CLOCKTYPE_PCLK2);
mbed_official	522:aee49fe30179	580	RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz
mbed_official	522:aee49fe30179	581	RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 32 MHz
mbed_official	522:aee49fe30179	582	RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 32 MHz
mbed_official	522:aee49fe30179	583	RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 32 MHz
mbed_official	522:aee49fe30179	584	if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
mbed_official	522:aee49fe30179	585	{
mbed_official	522:aee49fe30179	586	return 0; // FAIL
mbed_official	522:aee49fe30179	587	}
mbed_official	522:aee49fe30179	588
mbed_official	522:aee49fe30179	589	/* Output clock on MCO1 pin(PA8) for debugging purpose */
mbed_official	522:aee49fe30179	590	//HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
mbed_official	522:aee49fe30179	591
mbed_official	522:aee49fe30179	592	return 1; // OK
mbed_official	522:aee49fe30179	593	}
mbed_official	522:aee49fe30179	594
mbed_official	522:aee49fe30179	595	/**
mbed_official	522:aee49fe30179	596	* @}
mbed_official	522:aee49fe30179	597	*/
mbed_official	522:aee49fe30179	598
mbed_official	522:aee49fe30179	599	/**
mbed_official	522:aee49fe30179	600	* @}
mbed_official	522:aee49fe30179	601	*/
mbed_official	522:aee49fe30179	602
mbed_official	522:aee49fe30179	603	/**
mbed_official	522:aee49fe30179	604	* @}
mbed_official	522:aee49fe30179	605	*/
mbed_official	522:aee49fe30179	606
mbed_official	522:aee49fe30179	607	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/