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targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_tim.h@579:53297373a894, 2015-07-01 (annotated)

Committer:: mbed_official
Date:: Wed Jul 01 09:45:11 2015 +0100
Revision:: 579:53297373a894
Parent:: 489:119543c9f674

Synchronized with git revision d5b4d2ab9c47edb4dc5776e7177b0c2263459081

Full URL: https://github.com/mbedmicro/mbed/commit/d5b4d2ab9c47edb4dc5776e7177b0c2263459081/

Initial version of drivers for SAMR21

Who changed what in which revision?

User	Revision	Line number	New contents of line
mbed_official	376:cb4d9db17537	1	/**
mbed_official	376:cb4d9db17537	2	******************************************************************************
mbed_official	376:cb4d9db17537	3	* @file stm32l0xx_hal_tim.h
mbed_official	376:cb4d9db17537	4	* @author MCD Application Team
mbed_official	489:119543c9f674	5	* @version V1.2.0
mbed_official	489:119543c9f674	6	* @date 06-February-2015
mbed_official	376:cb4d9db17537	7	* @brief Header file of TIM HAL module.
mbed_official	376:cb4d9db17537	8	******************************************************************************
mbed_official	376:cb4d9db17537	9	* @attention
mbed_official	376:cb4d9db17537	10	*
mbed_official	489:119543c9f674	11	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
mbed_official	376:cb4d9db17537	12	*
mbed_official	376:cb4d9db17537	13	* Redistribution and use in source and binary forms, with or without modification,
mbed_official	376:cb4d9db17537	14	* are permitted provided that the following conditions are met:
mbed_official	376:cb4d9db17537	15	* 1. Redistributions of source code must retain the above copyright notice,
mbed_official	376:cb4d9db17537	16	* this list of conditions and the following disclaimer.
mbed_official	376:cb4d9db17537	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official	376:cb4d9db17537	18	* this list of conditions and the following disclaimer in the documentation
mbed_official	376:cb4d9db17537	19	* and/or other materials provided with the distribution.
mbed_official	376:cb4d9db17537	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official	376:cb4d9db17537	21	* may be used to endorse or promote products derived from this software
mbed_official	376:cb4d9db17537	22	* without specific prior written permission.
mbed_official	376:cb4d9db17537	23	*
mbed_official	376:cb4d9db17537	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official	376:cb4d9db17537	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official	376:cb4d9db17537	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official	376:cb4d9db17537	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official	376:cb4d9db17537	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official	376:cb4d9db17537	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official	376:cb4d9db17537	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official	376:cb4d9db17537	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official	376:cb4d9db17537	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official	376:cb4d9db17537	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official	376:cb4d9db17537	34	*
mbed_official	376:cb4d9db17537	35	******************************************************************************
mbed_official	376:cb4d9db17537	36	*/
mbed_official	376:cb4d9db17537	37
mbed_official	376:cb4d9db17537	38	/* Define to prevent recursive inclusion -------------------------------------*/
mbed_official	376:cb4d9db17537	39	#ifndef __STM32L0xx_HAL_TIM_H
mbed_official	376:cb4d9db17537	40	#define __STM32L0xx_HAL_TIM_H
mbed_official	376:cb4d9db17537	41
mbed_official	376:cb4d9db17537	42	#ifdef __cplusplus
mbed_official	376:cb4d9db17537	43	extern "C" {
mbed_official	376:cb4d9db17537	44	#endif
mbed_official	376:cb4d9db17537	45
mbed_official	376:cb4d9db17537	46	/* Includes ------------------------------------------------------------------*/
mbed_official	376:cb4d9db17537	47	#include "stm32l0xx_hal_def.h"
mbed_official	376:cb4d9db17537	48
mbed_official	376:cb4d9db17537	49	/** @addtogroup STM32L0xx_HAL_Driver
mbed_official	376:cb4d9db17537	50	* @{
mbed_official	376:cb4d9db17537	51	*/
mbed_official	376:cb4d9db17537	52
mbed_official	489:119543c9f674	53	/** @defgroup TIM TIM (Timer)
mbed_official	376:cb4d9db17537	54	* @{
mbed_official	376:cb4d9db17537	55	*/
mbed_official	376:cb4d9db17537	56
mbed_official	376:cb4d9db17537	57	/* Exported types ------------------------------------------------------------*/
mbed_official	376:cb4d9db17537	58
mbed_official	489:119543c9f674	59	/** @defgroup TIM_Exported_Types TIM Exported Types
mbed_official	489:119543c9f674	60	* @{
mbed_official	489:119543c9f674	61	*/
mbed_official	489:119543c9f674	62
mbed_official	489:119543c9f674	63	/** @defgroup TIM_Base_Configuration TIM base configuration structure
mbed_official	489:119543c9f674	64	* @{
mbed_official	489:119543c9f674	65	*/
mbed_official	376:cb4d9db17537	66	/**
mbed_official	376:cb4d9db17537	67	* @brief TIM Time base Configuration Structure definition
mbed_official	376:cb4d9db17537	68	*/
mbed_official	376:cb4d9db17537	69	typedef struct
mbed_official	376:cb4d9db17537	70	{
mbed_official	376:cb4d9db17537	71	uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
mbed_official	376:cb4d9db17537	72	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
mbed_official	376:cb4d9db17537	73
mbed_official	376:cb4d9db17537	74	uint32_t CounterMode; /*!< Specifies the counter mode.
mbed_official	376:cb4d9db17537	75	This parameter can be a value of @ref TIM_Counter_Mode */
mbed_official	376:cb4d9db17537	76
mbed_official	376:cb4d9db17537	77	uint32_t Period; /*!< Specifies the period value to be loaded into the active
mbed_official	376:cb4d9db17537	78	Auto-Reload Register at the next update event.
mbed_official	376:cb4d9db17537	79	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
mbed_official	376:cb4d9db17537	80
mbed_official	376:cb4d9db17537	81	uint32_t ClockDivision; /*!< Specifies the clock division.
mbed_official	376:cb4d9db17537	82	This parameter can be a value of @ref TIM_ClockDivision */
mbed_official	376:cb4d9db17537	83	} TIM_Base_InitTypeDef;
mbed_official	489:119543c9f674	84	/**
mbed_official	489:119543c9f674	85	* @}
mbed_official	489:119543c9f674	86	*/
mbed_official	376:cb4d9db17537	87
mbed_official	489:119543c9f674	88	/** @defgroup TIM_Output_Configuration TIM output compare configuration structure
mbed_official	489:119543c9f674	89	* @{
mbed_official	489:119543c9f674	90	*/
mbed_official	489:119543c9f674	91
mbed_official	489:119543c9f674	92	/**
mbed_official	376:cb4d9db17537	93	* @brief TIM Output Compare Configuration Structure definition
mbed_official	376:cb4d9db17537	94	*/
mbed_official	376:cb4d9db17537	95
mbed_official	376:cb4d9db17537	96	typedef struct
mbed_official	376:cb4d9db17537	97	{
mbed_official	376:cb4d9db17537	98	uint32_t OCMode; /*!< Specifies the TIM mode.
mbed_official	376:cb4d9db17537	99	This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
mbed_official	376:cb4d9db17537	100
mbed_official	376:cb4d9db17537	101	uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
mbed_official	376:cb4d9db17537	102	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
mbed_official	376:cb4d9db17537	103
mbed_official	376:cb4d9db17537	104	uint32_t OCPolarity; /*!< Specifies the output polarity.
mbed_official	376:cb4d9db17537	105	This parameter can be a value of @ref TIM_Output_Compare_Polarity */
mbed_official	376:cb4d9db17537	106
mbed_official	376:cb4d9db17537	107	uint32_t OCFastMode; /*!< Specifies the Fast mode state.
mbed_official	376:cb4d9db17537	108	This parameter can be a value of @ref TIM_Output_Fast_State
mbed_official	376:cb4d9db17537	109	@note This parameter is valid only in PWM1 and PWM2 mode. */
mbed_official	376:cb4d9db17537	110
mbed_official	376:cb4d9db17537	111	} TIM_OC_InitTypeDef;
mbed_official	489:119543c9f674	112	/**
mbed_official	489:119543c9f674	113	* @}
mbed_official	489:119543c9f674	114	*/
mbed_official	376:cb4d9db17537	115
mbed_official	489:119543c9f674	116	/** @defgroup TIM_OnePulse_Configuration TIM One Pulse configuration structure
mbed_official	489:119543c9f674	117	* @{
mbed_official	489:119543c9f674	118	*/
mbed_official	376:cb4d9db17537	119	/**
mbed_official	376:cb4d9db17537	120	* @brief TIM One Pulse Mode Configuration Structure definition
mbed_official	376:cb4d9db17537	121	*/
mbed_official	376:cb4d9db17537	122	typedef struct
mbed_official	376:cb4d9db17537	123	{
mbed_official	376:cb4d9db17537	124	uint32_t OCMode; /*!< Specifies the TIM mode.
mbed_official	376:cb4d9db17537	125	This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
mbed_official	376:cb4d9db17537	126
mbed_official	376:cb4d9db17537	127	uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
mbed_official	376:cb4d9db17537	128	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
mbed_official	376:cb4d9db17537	129
mbed_official	376:cb4d9db17537	130	uint32_t OCPolarity; /*!< Specifies the output polarity.
mbed_official	376:cb4d9db17537	131	This parameter can be a value of @ref TIM_Output_Compare_Polarity */
mbed_official	376:cb4d9db17537	132
mbed_official	376:cb4d9db17537	133
mbed_official	376:cb4d9db17537	134	uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
mbed_official	376:cb4d9db17537	135	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
mbed_official	376:cb4d9db17537	136
mbed_official	376:cb4d9db17537	137	uint32_t ICSelection; /*!< Specifies the input.
mbed_official	376:cb4d9db17537	138	This parameter can be a value of @ref TIM_Input_Capture_Selection */
mbed_official	376:cb4d9db17537	139
mbed_official	376:cb4d9db17537	140	uint32_t ICFilter; /*!< Specifies the input capture filter.
mbed_official	376:cb4d9db17537	141	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
mbed_official	376:cb4d9db17537	142	} TIM_OnePulse_InitTypeDef;
mbed_official	489:119543c9f674	143	/**
mbed_official	489:119543c9f674	144	* @}
mbed_official	489:119543c9f674	145	*/
mbed_official	376:cb4d9db17537	146
mbed_official	489:119543c9f674	147	/** @defgroup TIM_Input_Capture TIM input capture configuration structure
mbed_official	489:119543c9f674	148	* @{
mbed_official	489:119543c9f674	149	*/
mbed_official	376:cb4d9db17537	150	/**
mbed_official	376:cb4d9db17537	151	* @brief TIM Input Capture Configuration Structure definition
mbed_official	376:cb4d9db17537	152	*/
mbed_official	376:cb4d9db17537	153
mbed_official	376:cb4d9db17537	154	typedef struct
mbed_official	376:cb4d9db17537	155	{
mbed_official	376:cb4d9db17537	156	uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
mbed_official	376:cb4d9db17537	157	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
mbed_official	376:cb4d9db17537	158
mbed_official	376:cb4d9db17537	159	uint32_t ICSelection; /*!< Specifies the input.
mbed_official	376:cb4d9db17537	160	This parameter can be a value of @ref TIM_Input_Capture_Selection */
mbed_official	376:cb4d9db17537	161
mbed_official	376:cb4d9db17537	162	uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
mbed_official	376:cb4d9db17537	163	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
mbed_official	376:cb4d9db17537	164
mbed_official	376:cb4d9db17537	165	uint32_t ICFilter; /*!< Specifies the input capture filter.
mbed_official	376:cb4d9db17537	166	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
mbed_official	376:cb4d9db17537	167	} TIM_IC_InitTypeDef;
mbed_official	489:119543c9f674	168	/**
mbed_official	489:119543c9f674	169	* @}
mbed_official	489:119543c9f674	170	*/
mbed_official	376:cb4d9db17537	171
mbed_official	489:119543c9f674	172	/** @defgroup TIM_Encoder TIM encoder configuration structure
mbed_official	489:119543c9f674	173	* @{
mbed_official	489:119543c9f674	174	*/
mbed_official	376:cb4d9db17537	175	/**
mbed_official	376:cb4d9db17537	176	* @brief TIM Encoder Configuration Structure definition
mbed_official	376:cb4d9db17537	177	*/
mbed_official	376:cb4d9db17537	178
mbed_official	376:cb4d9db17537	179	typedef struct
mbed_official	376:cb4d9db17537	180	{
mbed_official	376:cb4d9db17537	181	uint32_t EncoderMode; /*!< Specifies the active edge of the input signal.
mbed_official	376:cb4d9db17537	182	This parameter can be a value of @ref TIM_Encoder_Mode */
mbed_official	376:cb4d9db17537	183
mbed_official	376:cb4d9db17537	184	uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
mbed_official	376:cb4d9db17537	185	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
mbed_official	376:cb4d9db17537	186
mbed_official	376:cb4d9db17537	187	uint32_t IC1Selection; /*!< Specifies the input.
mbed_official	376:cb4d9db17537	188	This parameter can be a value of @ref TIM_Input_Capture_Selection */
mbed_official	376:cb4d9db17537	189
mbed_official	376:cb4d9db17537	190	uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
mbed_official	376:cb4d9db17537	191	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
mbed_official	376:cb4d9db17537	192
mbed_official	376:cb4d9db17537	193	uint32_t IC1Filter; /*!< Specifies the input capture filter.
mbed_official	376:cb4d9db17537	194	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
mbed_official	376:cb4d9db17537	195
mbed_official	376:cb4d9db17537	196	uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.
mbed_official	376:cb4d9db17537	197	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
mbed_official	376:cb4d9db17537	198
mbed_official	376:cb4d9db17537	199	uint32_t IC2Selection; /*!< Specifies the input.
mbed_official	376:cb4d9db17537	200	This parameter can be a value of @ref TIM_Input_Capture_Selection */
mbed_official	376:cb4d9db17537	201
mbed_official	376:cb4d9db17537	202	uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler.
mbed_official	376:cb4d9db17537	203	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
mbed_official	376:cb4d9db17537	204
mbed_official	376:cb4d9db17537	205	uint32_t IC2Filter; /*!< Specifies the input capture filter.
mbed_official	376:cb4d9db17537	206	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
mbed_official	376:cb4d9db17537	207	} TIM_Encoder_InitTypeDef;
mbed_official	489:119543c9f674	208	/**
mbed_official	489:119543c9f674	209	* @}
mbed_official	489:119543c9f674	210	*/
mbed_official	376:cb4d9db17537	211
mbed_official	489:119543c9f674	212	/** @defgroup TIM_Clock_Configuration TIM clock configuration structure
mbed_official	489:119543c9f674	213	* @{
mbed_official	489:119543c9f674	214	*/
mbed_official	376:cb4d9db17537	215	/**
mbed_official	376:cb4d9db17537	216	* @brief Clock Configuration Handle Structure definition
mbed_official	376:cb4d9db17537	217	*/
mbed_official	376:cb4d9db17537	218	typedef struct
mbed_official	376:cb4d9db17537	219	{
mbed_official	376:cb4d9db17537	220	uint32_t ClockSource; /*!< TIM clock sources.
mbed_official	376:cb4d9db17537	221	This parameter can be a value of @ref TIM_Clock_Source */
mbed_official	376:cb4d9db17537	222	uint32_t ClockPolarity; /*!< TIM clock polarity.
mbed_official	376:cb4d9db17537	223	This parameter can be a value of @ref TIM_Clock_Polarity */
mbed_official	376:cb4d9db17537	224	uint32_t ClockPrescaler; /*!< TIM clock prescaler.
mbed_official	376:cb4d9db17537	225	This parameter can be a value of @ref TIM_Clock_Prescaler */
mbed_official	376:cb4d9db17537	226	uint32_t ClockFilter; /*!< TIM clock filter.
mbed_official	376:cb4d9db17537	227	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
mbed_official	376:cb4d9db17537	228	}TIM_ClockConfigTypeDef;
mbed_official	489:119543c9f674	229	/**
mbed_official	489:119543c9f674	230	* @}
mbed_official	489:119543c9f674	231	*/
mbed_official	376:cb4d9db17537	232
mbed_official	489:119543c9f674	233	/** @defgroup TIM_Clear_Input_Configuration TIM clear input configuration structure
mbed_official	489:119543c9f674	234	* @{
mbed_official	489:119543c9f674	235	*/
mbed_official	376:cb4d9db17537	236	/**
mbed_official	376:cb4d9db17537	237	* @brief Clear Input Configuration Handle Structure definition
mbed_official	376:cb4d9db17537	238	*/
mbed_official	376:cb4d9db17537	239	typedef struct
mbed_official	376:cb4d9db17537	240	{
mbed_official	376:cb4d9db17537	241	uint32_t ClearInputState; /*!< TIM clear Input state.
mbed_official	376:cb4d9db17537	242	This parameter can be ENABLE or DISABLE */
mbed_official	376:cb4d9db17537	243	uint32_t ClearInputSource; /*!< TIM clear Input sources.
mbed_official	376:cb4d9db17537	244	This parameter can be a value of @ref TIM_ClearInput_Source */
mbed_official	376:cb4d9db17537	245	uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity.
mbed_official	376:cb4d9db17537	246	This parameter can be a value of @ref TIM_ClearInput_Polarity */
mbed_official	376:cb4d9db17537	247	uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler.
mbed_official	376:cb4d9db17537	248	This parameter can be a value of @ref TIM_ClearInput_Prescaler */
mbed_official	376:cb4d9db17537	249	uint32_t ClearInputFilter; /*!< TIM Clear Input filter.
mbed_official	376:cb4d9db17537	250	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
mbed_official	376:cb4d9db17537	251	}TIM_ClearInputConfigTypeDef;
mbed_official	489:119543c9f674	252	/**
mbed_official	489:119543c9f674	253	* @}
mbed_official	489:119543c9f674	254	*/
mbed_official	376:cb4d9db17537	255
mbed_official	489:119543c9f674	256	/** @defgroup TIM_Slave_Configuratio TIM slave configuration structure
mbed_official	489:119543c9f674	257	* @{
mbed_official	489:119543c9f674	258	*/
mbed_official	376:cb4d9db17537	259	/**
mbed_official	376:cb4d9db17537	260	* @brief TIM Slave configuration Structure definition
mbed_official	376:cb4d9db17537	261	*/
mbed_official	376:cb4d9db17537	262	typedef struct {
mbed_official	376:cb4d9db17537	263	uint32_t SlaveMode; /*!< Slave mode selection.
mbed_official	376:cb4d9db17537	264	This parameter can be a value of @ref TIM_Slave_Mode */
mbed_official	376:cb4d9db17537	265	uint32_t InputTrigger; /*!< Input Trigger source.
mbed_official	376:cb4d9db17537	266	This parameter can be a value of @ref TIM_Trigger_Selection */
mbed_official	376:cb4d9db17537	267	uint32_t TriggerPolarity; /*!< Input Trigger polarity.
mbed_official	376:cb4d9db17537	268	This parameter can be a value of @ref TIM_Trigger_Polarity */
mbed_official	376:cb4d9db17537	269	uint32_t TriggerPrescaler; /*!< Input trigger prescaler.
mbed_official	376:cb4d9db17537	270	This parameter can be a value of @ref TIM_Trigger_Prescaler */
mbed_official	376:cb4d9db17537	271	uint32_t TriggerFilter; /*!< Input trigger filter.
mbed_official	376:cb4d9db17537	272	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
mbed_official	376:cb4d9db17537	273
mbed_official	376:cb4d9db17537	274	}TIM_SlaveConfigTypeDef;
mbed_official	489:119543c9f674	275	/**
mbed_official	489:119543c9f674	276	* @}
mbed_official	489:119543c9f674	277	*/
mbed_official	376:cb4d9db17537	278
mbed_official	489:119543c9f674	279	/** @defgroup TIM_State_Definition TIM state definition
mbed_official	489:119543c9f674	280	* @{
mbed_official	489:119543c9f674	281	*/
mbed_official	376:cb4d9db17537	282	/**
mbed_official	376:cb4d9db17537	283	* @brief HAL State structures definition
mbed_official	376:cb4d9db17537	284	*/
mbed_official	376:cb4d9db17537	285	typedef enum
mbed_official	376:cb4d9db17537	286	{
mbed_official	376:cb4d9db17537	287	HAL_TIM_STATE_RESET = 0x00, /!< Peripheral not yet initialized or disabled /
mbed_official	376:cb4d9db17537	288	HAL_TIM_STATE_READY = 0x01, /!< Peripheral Initialized and ready for use /
mbed_official	376:cb4d9db17537	289	HAL_TIM_STATE_BUSY = 0x02, /!< An internal process is ongoing /
mbed_official	376:cb4d9db17537	290	HAL_TIM_STATE_TIMEOUT = 0x03, /!< Timeout state /
mbed_official	376:cb4d9db17537	291	HAL_TIM_STATE_ERROR = 0x04 /!< Reception process is ongoing /
mbed_official	376:cb4d9db17537	292	}HAL_TIM_StateTypeDef;
mbed_official	489:119543c9f674	293	/**
mbed_official	489:119543c9f674	294	* @}
mbed_official	489:119543c9f674	295	*/
mbed_official	376:cb4d9db17537	296
mbed_official	489:119543c9f674	297	/** @defgroup TIM_Active_Channel TIM active channel definition
mbed_official	489:119543c9f674	298	* @{
mbed_official	489:119543c9f674	299	*/
mbed_official	376:cb4d9db17537	300	/**
mbed_official	376:cb4d9db17537	301	* @brief HAL Active channel structures definition
mbed_official	376:cb4d9db17537	302	*/
mbed_official	376:cb4d9db17537	303	typedef enum
mbed_official	376:cb4d9db17537	304	{
mbed_official	376:cb4d9db17537	305	HAL_TIM_ACTIVE_CHANNEL_1 = 0x01, /!< The active channel is 1 /
mbed_official	376:cb4d9db17537	306	HAL_TIM_ACTIVE_CHANNEL_2 = 0x02, /!< The active channel is 2 /
mbed_official	376:cb4d9db17537	307	HAL_TIM_ACTIVE_CHANNEL_3 = 0x04, /!< The active channel is 3 /
mbed_official	376:cb4d9db17537	308	HAL_TIM_ACTIVE_CHANNEL_4 = 0x08, /!< The active channel is 4 /
mbed_official	376:cb4d9db17537	309	HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00 /!< All active channels cleared /
mbed_official	376:cb4d9db17537	310	}HAL_TIM_ActiveChannel;
mbed_official	489:119543c9f674	311	/**
mbed_official	489:119543c9f674	312	* @}
mbed_official	489:119543c9f674	313	*/
mbed_official	376:cb4d9db17537	314
mbed_official	489:119543c9f674	315	/** @defgroup TIM_Handle TIM handler
mbed_official	489:119543c9f674	316	* @{
mbed_official	489:119543c9f674	317	*/
mbed_official	376:cb4d9db17537	318	/**
mbed_official	376:cb4d9db17537	319	* @brief TIM Time Base Handle Structure definition
mbed_official	376:cb4d9db17537	320	*/
mbed_official	376:cb4d9db17537	321	typedef struct
mbed_official	376:cb4d9db17537	322	{
mbed_official	376:cb4d9db17537	323	TIM_TypeDef Instance; /!< Register base address */
mbed_official	376:cb4d9db17537	324	TIM_Base_InitTypeDef Init; /!< TIM Time Base required parameters /
mbed_official	376:cb4d9db17537	325	HAL_TIM_ActiveChannel Channel; /!< Active channel /
mbed_official	376:cb4d9db17537	326	DMA_HandleTypeDef hdma[7]; /!< DMA Handlers array
mbed_official	376:cb4d9db17537	327	This array is accessed by a @ref DMA_Handle_index */
mbed_official	376:cb4d9db17537	328	HAL_LockTypeDef Lock; /!< Locking object /
mbed_official	376:cb4d9db17537	329	__IO HAL_TIM_StateTypeDef State; /!< TIM operation state /
mbed_official	376:cb4d9db17537	330	}TIM_HandleTypeDef;
mbed_official	489:119543c9f674	331	/**
mbed_official	489:119543c9f674	332	* @}
mbed_official	489:119543c9f674	333	*/
mbed_official	376:cb4d9db17537	334
mbed_official	489:119543c9f674	335	/**
mbed_official	489:119543c9f674	336	* @}
mbed_official	489:119543c9f674	337	*/
mbed_official	376:cb4d9db17537	338	/* Exported constants --------------------------------------------------------*/
mbed_official	489:119543c9f674	339	/** @defgroup TIM_Exported_Constants TIM Exported Constants
mbed_official	376:cb4d9db17537	340	* @{
mbed_official	376:cb4d9db17537	341	*/
mbed_official	376:cb4d9db17537	342
mbed_official	489:119543c9f674	343
mbed_official	489:119543c9f674	344	#define IS_TIM_PERIOD(__PERIOD__) ((__PERIOD__) <= 0xFFFF)
mbed_official	489:119543c9f674	345
mbed_official	489:119543c9f674	346	#define IS_TIM_PRESCALER(__PRESCALER__) ((__PRESCALER__) <= 0xFFFF)
mbed_official	489:119543c9f674	347
mbed_official	489:119543c9f674	348
mbed_official	489:119543c9f674	349	/** @defgroup TIM_Input_Channel_Polarity Input channel polarity
mbed_official	376:cb4d9db17537	350	* @{
mbed_official	376:cb4d9db17537	351	*/
mbed_official	376:cb4d9db17537	352	#define TIM_INPUTCHANNELPOLARITY_RISING ((uint32_t)0x00000000) /!< Polarity for TIx source /
mbed_official	376:cb4d9db17537	353	#define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P) /!< Polarity for TIx source /
mbed_official	376:cb4d9db17537	354	#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P \| TIM_CCER_CC1NP) /!< Polarity for TIx source /
mbed_official	376:cb4d9db17537	355	/**
mbed_official	376:cb4d9db17537	356	* @}
mbed_official	376:cb4d9db17537	357	*/
mbed_official	376:cb4d9db17537	358
mbed_official	489:119543c9f674	359	/** @defgroup TIM_ETR_Polarity ETR polarity
mbed_official	376:cb4d9db17537	360	* @{
mbed_official	376:cb4d9db17537	361	*/
mbed_official	376:cb4d9db17537	362	#define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /!< Polarity for ETR source /
mbed_official	376:cb4d9db17537	363	#define TIM_ETRPOLARITY_NONINVERTED ((uint32_t)0x0000) /!< Polarity for ETR source /
mbed_official	376:cb4d9db17537	364	/**
mbed_official	376:cb4d9db17537	365	* @}
mbed_official	376:cb4d9db17537	366	*/
mbed_official	376:cb4d9db17537	367
mbed_official	489:119543c9f674	368	/** @defgroup TIM_ETR_Prescaler ETR prescaler
mbed_official	376:cb4d9db17537	369	* @{
mbed_official	376:cb4d9db17537	370	*/
mbed_official	376:cb4d9db17537	371	#define TIM_ETRPRESCALER_DIV1 ((uint32_t)0x0000) /!< No prescaler is used /
mbed_official	376:cb4d9db17537	372	#define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /!< ETR input source is divided by 2 /
mbed_official	376:cb4d9db17537	373	#define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /!< ETR input source is divided by 4 /
mbed_official	376:cb4d9db17537	374	#define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS) /!< ETR input source is divided by 8 /
mbed_official	376:cb4d9db17537	375	/**
mbed_official	376:cb4d9db17537	376	* @}
mbed_official	376:cb4d9db17537	377	*/
mbed_official	376:cb4d9db17537	378
mbed_official	489:119543c9f674	379	/** @defgroup TIM_Counter_Mode Counter mode
mbed_official	376:cb4d9db17537	380	* @{
mbed_official	376:cb4d9db17537	381	*/
mbed_official	376:cb4d9db17537	382	#define TIM_COUNTERMODE_UP ((uint32_t)0x0000)
mbed_official	376:cb4d9db17537	383	#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR
mbed_official	376:cb4d9db17537	384	#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0
mbed_official	376:cb4d9db17537	385	#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1
mbed_official	376:cb4d9db17537	386	#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS
mbed_official	376:cb4d9db17537	387	/**
mbed_official	376:cb4d9db17537	388	* @}
mbed_official	489:119543c9f674	389	*/
mbed_official	489:119543c9f674	390	#define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) \|\| \
mbed_official	489:119543c9f674	391	((__MODE__) == TIM_COUNTERMODE_DOWN) \|\| \
mbed_official	489:119543c9f674	392	((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) \|\| \
mbed_official	489:119543c9f674	393	((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) \|\| \
mbed_official	489:119543c9f674	394	((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3))
mbed_official	489:119543c9f674	395
mbed_official	489:119543c9f674	396
mbed_official	489:119543c9f674	397
mbed_official	376:cb4d9db17537	398
mbed_official	489:119543c9f674	399	/** @defgroup TIM_ClockDivision Clock division
mbed_official	376:cb4d9db17537	400	* @{
mbed_official	376:cb4d9db17537	401	*/
mbed_official	376:cb4d9db17537	402	#define TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x0000)
mbed_official	376:cb4d9db17537	403	#define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0)
mbed_official	376:cb4d9db17537	404	#define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1)
mbed_official	376:cb4d9db17537	405	/**
mbed_official	376:cb4d9db17537	406	* @}
mbed_official	376:cb4d9db17537	407	*/
mbed_official	489:119543c9f674	408	#define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) \|\| \
mbed_official	489:119543c9f674	409	((__DIV__) == TIM_CLOCKDIVISION_DIV2) \|\| \
mbed_official	489:119543c9f674	410	((__DIV__) == TIM_CLOCKDIVISION_DIV4))
mbed_official	376:cb4d9db17537	411
mbed_official	489:119543c9f674	412
mbed_official	489:119543c9f674	413	/** @defgroup TIM_Output_Compare_and_PWM_modes Output compare and PWM modes
mbed_official	376:cb4d9db17537	414	* @{
mbed_official	376:cb4d9db17537	415	*/
mbed_official	376:cb4d9db17537	416	#define TIM_OCMODE_TIMING ((uint32_t)0x0000)
mbed_official	376:cb4d9db17537	417	#define TIM_OCMODE_ACTIVE (TIM_CCMR1_OC1M_0)
mbed_official	376:cb4d9db17537	418	#define TIM_OCMODE_INACTIVE (TIM_CCMR1_OC1M_1)
mbed_official	376:cb4d9db17537	419	#define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_0 \| TIM_CCMR1_OC1M_1)
mbed_official	376:cb4d9db17537	420	#define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_2)
mbed_official	376:cb4d9db17537	421	#define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M)
mbed_official	376:cb4d9db17537	422	#define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_0 \| TIM_CCMR1_OC1M_2)
mbed_official	376:cb4d9db17537	423	#define TIM_OCMODE_FORCED_INACTIVE (TIM_CCMR1_OC1M_2)
mbed_official	376:cb4d9db17537	424	/**
mbed_official	376:cb4d9db17537	425	* @}
mbed_official	376:cb4d9db17537	426	*/
mbed_official	376:cb4d9db17537	427
mbed_official	489:119543c9f674	428	#define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1) \|\| \
mbed_official	489:119543c9f674	429	((__MODE__) == TIM_OCMODE_PWM2))
mbed_official	489:119543c9f674	430
mbed_official	489:119543c9f674	431	#define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) \|\| \
mbed_official	489:119543c9f674	432	((__MODE__) == TIM_OCMODE_ACTIVE) \|\| \
mbed_official	489:119543c9f674	433	((__MODE__) == TIM_OCMODE_INACTIVE) \|\| \
mbed_official	489:119543c9f674	434	((__MODE__) == TIM_OCMODE_TOGGLE) \|\| \
mbed_official	489:119543c9f674	435	((__MODE__) == TIM_OCMODE_FORCED_ACTIVE) \|\| \
mbed_official	489:119543c9f674	436	((__MODE__) == TIM_OCMODE_FORCED_INACTIVE))
mbed_official	489:119543c9f674	437
mbed_official	489:119543c9f674	438
mbed_official	489:119543c9f674	439	/** @defgroup TIM_Output_Compare_State Output compare state
mbed_official	376:cb4d9db17537	440	* @{
mbed_official	376:cb4d9db17537	441	*/
mbed_official	376:cb4d9db17537	442	#define TIM_OUTPUTSTATE_DISABLE ((uint32_t)0x0000)
mbed_official	376:cb4d9db17537	443	#define TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E)
mbed_official	376:cb4d9db17537	444	/**
mbed_official	376:cb4d9db17537	445	* @}
mbed_official	489:119543c9f674	446	*/
mbed_official	489:119543c9f674	447
mbed_official	489:119543c9f674	448	/** @defgroup TIM_Output_Fast_State Output fast state
mbed_official	376:cb4d9db17537	449	* @{
mbed_official	376:cb4d9db17537	450	*/
mbed_official	376:cb4d9db17537	451	#define TIM_OCFAST_DISABLE ((uint32_t)0x0000)
mbed_official	376:cb4d9db17537	452	#define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE)
mbed_official	376:cb4d9db17537	453	/**
mbed_official	376:cb4d9db17537	454	* @}
mbed_official	376:cb4d9db17537	455	*/
mbed_official	489:119543c9f674	456	#define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) \|\| \
mbed_official	489:119543c9f674	457	((__STATE__) == TIM_OCFAST_ENABLE))
mbed_official	489:119543c9f674	458
mbed_official	489:119543c9f674	459	/** @defgroup TIM_Output_Compare_N_State Output compare N state
mbed_official	376:cb4d9db17537	460	* @{
mbed_official	376:cb4d9db17537	461	*/
mbed_official	376:cb4d9db17537	462	#define TIM_OUTPUTNSTATE_DISABLE ((uint32_t)0x0000)
mbed_official	376:cb4d9db17537	463	#define TIM_OUTPUTNSTATE_ENABLE (TIM_CCER_CC1NE)
mbed_official	376:cb4d9db17537	464	/**
mbed_official	376:cb4d9db17537	465	* @}
mbed_official	489:119543c9f674	466	*/
mbed_official	376:cb4d9db17537	467
mbed_official	489:119543c9f674	468	/** @defgroup TIM_Output_Compare_Polarity Output compare polarity
mbed_official	376:cb4d9db17537	469	* @{
mbed_official	376:cb4d9db17537	470	*/
mbed_official	376:cb4d9db17537	471	#define TIM_OCPOLARITY_HIGH ((uint32_t)0x0000)
mbed_official	376:cb4d9db17537	472	#define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P)
mbed_official	376:cb4d9db17537	473	/**
mbed_official	376:cb4d9db17537	474	* @}
mbed_official	376:cb4d9db17537	475	*/
mbed_official	489:119543c9f674	476	#define IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) \|\| \
mbed_official	489:119543c9f674	477	((__POLARITY__) == TIM_OCPOLARITY_LOW))
mbed_official	376:cb4d9db17537	478
mbed_official	489:119543c9f674	479	/** @defgroup TIM_Channel TIM channels
mbed_official	376:cb4d9db17537	480	* @{
mbed_official	376:cb4d9db17537	481	*/
mbed_official	376:cb4d9db17537	482	#define TIM_CHANNEL_1 ((uint32_t)0x0000)
mbed_official	376:cb4d9db17537	483	#define TIM_CHANNEL_2 ((uint32_t)0x0004)
mbed_official	376:cb4d9db17537	484	#define TIM_CHANNEL_3 ((uint32_t)0x0008)
mbed_official	376:cb4d9db17537	485	#define TIM_CHANNEL_4 ((uint32_t)0x000C)
mbed_official	376:cb4d9db17537	486	#define TIM_CHANNEL_ALL ((uint32_t)0x0018)
mbed_official	376:cb4d9db17537	487	/**
mbed_official	376:cb4d9db17537	488	* @}
mbed_official	489:119543c9f674	489	*/
mbed_official	376:cb4d9db17537	490
mbed_official	489:119543c9f674	491	#define IS_TIM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) \|\| \
mbed_official	489:119543c9f674	492	((__CHANNEL__) == TIM_CHANNEL_2) \|\| \
mbed_official	489:119543c9f674	493	((__CHANNEL__) == TIM_CHANNEL_3) \|\| \
mbed_official	489:119543c9f674	494	((__CHANNEL__) == TIM_CHANNEL_4) \|\| \
mbed_official	489:119543c9f674	495	((__CHANNEL__) == TIM_CHANNEL_ALL))
mbed_official	489:119543c9f674	496
mbed_official	489:119543c9f674	497	#define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) \|\| \
mbed_official	489:119543c9f674	498	((__CHANNEL__) == TIM_CHANNEL_2))
mbed_official	489:119543c9f674	499
mbed_official	489:119543c9f674	500
mbed_official	489:119543c9f674	501	/** @defgroup TIM_Input_Capture_Polarity Input capture polarity
mbed_official	376:cb4d9db17537	502	* @{
mbed_official	376:cb4d9db17537	503	*/
mbed_official	376:cb4d9db17537	504	#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
mbed_official	376:cb4d9db17537	505	#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
mbed_official	376:cb4d9db17537	506	#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
mbed_official	376:cb4d9db17537	507	/**
mbed_official	376:cb4d9db17537	508	* @}
mbed_official	489:119543c9f674	509	*/
mbed_official	489:119543c9f674	510	#define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) \|\| \
mbed_official	489:119543c9f674	511	((__POLARITY__) == TIM_ICPOLARITY_FALLING) \|\| \
mbed_official	489:119543c9f674	512	((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))
mbed_official	376:cb4d9db17537	513
mbed_official	489:119543c9f674	514
mbed_official	489:119543c9f674	515	/** @defgroup TIM_Input_Capture_Selection Input capture selection
mbed_official	376:cb4d9db17537	516	* @{
mbed_official	376:cb4d9db17537	517	*/
mbed_official	376:cb4d9db17537	518	#define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1, 2, 3 or 4 is selected to be
mbed_official	376:cb4d9db17537	519	connected to IC1, IC2, IC3 or IC4, respectively */
mbed_official	376:cb4d9db17537	520	#define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1) /*!< TIM Input 1, 2, 3 or 4 is selected to be
mbed_official	376:cb4d9db17537	521	connected to IC2, IC1, IC4 or IC3, respectively */
mbed_official	376:cb4d9db17537	522	#define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC /
mbed_official	376:cb4d9db17537	523
mbed_official	489:119543c9f674	524	#define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) \|\| \
mbed_official	489:119543c9f674	525	((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) \|\| \
mbed_official	489:119543c9f674	526	((__SELECTION__) == TIM_ICSELECTION_TRC))
mbed_official	376:cb4d9db17537	527	/**
mbed_official	376:cb4d9db17537	528	* @}
mbed_official	376:cb4d9db17537	529	*/
mbed_official	376:cb4d9db17537	530
mbed_official	489:119543c9f674	531	/** @defgroup TIM_Input_Capture_Prescaler Input capture prescaler
mbed_official	376:cb4d9db17537	532	* @{
mbed_official	376:cb4d9db17537	533	*/
mbed_official	376:cb4d9db17537	534	#define TIM_ICPSC_DIV1 ((uint32_t)0x0000) /!< Capture performed each time an edge is detected on the capture input /
mbed_official	376:cb4d9db17537	535	#define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /!< Capture performed once every 2 events /
mbed_official	376:cb4d9db17537	536	#define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /!< Capture performed once every 4 events /
mbed_official	376:cb4d9db17537	537	#define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /!< Capture performed once every 8 events /
mbed_official	376:cb4d9db17537	538	/**
mbed_official	376:cb4d9db17537	539	* @}
mbed_official	489:119543c9f674	540	*/
mbed_official	489:119543c9f674	541	#define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) \|\| \
mbed_official	489:119543c9f674	542	((__PRESCALER__) == TIM_ICPSC_DIV2) \|\| \
mbed_official	489:119543c9f674	543	((__PRESCALER__) == TIM_ICPSC_DIV4) \|\| \
mbed_official	489:119543c9f674	544	((__PRESCALER__) == TIM_ICPSC_DIV8))
mbed_official	376:cb4d9db17537	545
mbed_official	489:119543c9f674	546	/** @defgroup TIM_One_Pulse_Mode One pulse mode
mbed_official	376:cb4d9db17537	547	* @{
mbed_official	376:cb4d9db17537	548	*/
mbed_official	376:cb4d9db17537	549	#define TIM_OPMODE_SINGLE (TIM_CR1_OPM)
mbed_official	376:cb4d9db17537	550	#define TIM_OPMODE_REPETITIVE ((uint32_t)0x0000)
mbed_official	376:cb4d9db17537	551	/**
mbed_official	376:cb4d9db17537	552	* @}
mbed_official	376:cb4d9db17537	553	*/
mbed_official	489:119543c9f674	554	#define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) \|\| \
mbed_official	489:119543c9f674	555	((__MODE__) == TIM_OPMODE_REPETITIVE))
mbed_official	489:119543c9f674	556
mbed_official	489:119543c9f674	557	/** @defgroup TIM_Encoder_Mode Encoder_Mode
mbed_official	376:cb4d9db17537	558	* @{
mbed_official	376:cb4d9db17537	559	*/
mbed_official	376:cb4d9db17537	560	#define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0)
mbed_official	376:cb4d9db17537	561	#define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1)
mbed_official	376:cb4d9db17537	562	#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 \| TIM_SMCR_SMS_0)
mbed_official	376:cb4d9db17537	563	/**
mbed_official	376:cb4d9db17537	564	* @}
mbed_official	489:119543c9f674	565	*/
mbed_official	489:119543c9f674	566	#define IS_TIM_ENCODER_MODE(__MODE__) (((__MODE__) == TIM_ENCODERMODE_TI1) \|\| \
mbed_official	489:119543c9f674	567	((__MODE__) == TIM_ENCODERMODE_TI2) \|\| \
mbed_official	489:119543c9f674	568	((__MODE__) == TIM_ENCODERMODE_TI12))
mbed_official	489:119543c9f674	569
mbed_official	489:119543c9f674	570	/** @defgroup TIM_Interrupt_definition Interrupt definition
mbed_official	376:cb4d9db17537	571	* @{
mbed_official	376:cb4d9db17537	572	*/
mbed_official	376:cb4d9db17537	573	#define TIM_IT_UPDATE (TIM_DIER_UIE)
mbed_official	376:cb4d9db17537	574	#define TIM_IT_CC1 (TIM_DIER_CC1IE)
mbed_official	376:cb4d9db17537	575	#define TIM_IT_CC2 (TIM_DIER_CC2IE)
mbed_official	376:cb4d9db17537	576	#define TIM_IT_CC3 (TIM_DIER_CC3IE)
mbed_official	376:cb4d9db17537	577	#define TIM_IT_CC4 (TIM_DIER_CC4IE)
mbed_official	376:cb4d9db17537	578	#define TIM_IT_TRIGGER (TIM_DIER_TIE)
mbed_official	376:cb4d9db17537	579	/**
mbed_official	376:cb4d9db17537	580	* @}
mbed_official	376:cb4d9db17537	581	*/
mbed_official	489:119543c9f674	582	#define IS_TIM_IT(__IT__) ((((__IT__) & 0xFFFFFFA0) == 0x00000000) && ((__IT__) != 0x00000000))
mbed_official	376:cb4d9db17537	583
mbed_official	489:119543c9f674	584	#define IS_TIM_GET_IT(__IT__) (((__IT__) == TIM_IT_UPDATE) \|\| \
mbed_official	489:119543c9f674	585	((__IT__) == TIM_IT_CC1) \|\| \
mbed_official	489:119543c9f674	586	((__IT__) == TIM_IT_CC2) \|\| \
mbed_official	489:119543c9f674	587	((__IT__) == TIM_IT_CC3) \|\| \
mbed_official	489:119543c9f674	588	((__IT__) == TIM_IT_CC4) \|\| \
mbed_official	489:119543c9f674	589	((__IT__) == TIM_IT_TRIGGER))
mbed_official	489:119543c9f674	590
mbed_official	489:119543c9f674	591
mbed_official	489:119543c9f674	592	/** @defgroup TIM_DMA_sources DMA sources
mbed_official	376:cb4d9db17537	593	* @{
mbed_official	376:cb4d9db17537	594	*/
mbed_official	376:cb4d9db17537	595	#define TIM_DMA_UPDATE (TIM_DIER_UDE)
mbed_official	376:cb4d9db17537	596	#define TIM_DMA_CC1 (TIM_DIER_CC1DE)
mbed_official	376:cb4d9db17537	597	#define TIM_DMA_CC2 (TIM_DIER_CC2DE)
mbed_official	376:cb4d9db17537	598	#define TIM_DMA_CC3 (TIM_DIER_CC3DE)
mbed_official	376:cb4d9db17537	599	#define TIM_DMA_CC4 (TIM_DIER_CC4DE)
mbed_official	376:cb4d9db17537	600	#define TIM_DMA_TRIGGER (TIM_DIER_TDE)
mbed_official	376:cb4d9db17537	601	/**
mbed_official	376:cb4d9db17537	602	* @}
mbed_official	376:cb4d9db17537	603	*/
mbed_official	489:119543c9f674	604	#define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFA0FF) == 0x00000000) && ((__SOURCE__) != 0x00000000))
mbed_official	489:119543c9f674	605
mbed_official	489:119543c9f674	606
mbed_official	376:cb4d9db17537	607
mbed_official	489:119543c9f674	608	/** @defgroup TIM_Event_Source Event sources
mbed_official	376:cb4d9db17537	609	* @{
mbed_official	376:cb4d9db17537	610	*/
mbed_official	489:119543c9f674	611	#define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG
mbed_official	489:119543c9f674	612	#define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G
mbed_official	489:119543c9f674	613	#define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G
mbed_official	489:119543c9f674	614	#define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G
mbed_official	489:119543c9f674	615	#define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G
mbed_official	489:119543c9f674	616	#define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG
mbed_official	376:cb4d9db17537	617	/**
mbed_official	376:cb4d9db17537	618	* @}
mbed_official	489:119543c9f674	619	*/
mbed_official	489:119543c9f674	620	#define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFFA0) == 0x00000000) && ((__SOURCE__) != 0x00000000))
mbed_official	489:119543c9f674	621
mbed_official	376:cb4d9db17537	622
mbed_official	489:119543c9f674	623	/** @defgroup TIM_Flag_definition Flag definition
mbed_official	376:cb4d9db17537	624	* @{
mbed_official	376:cb4d9db17537	625	*/
mbed_official	376:cb4d9db17537	626	#define TIM_FLAG_UPDATE (TIM_SR_UIF)
mbed_official	376:cb4d9db17537	627	#define TIM_FLAG_CC1 (TIM_SR_CC1IF)
mbed_official	376:cb4d9db17537	628	#define TIM_FLAG_CC2 (TIM_SR_CC2IF)
mbed_official	376:cb4d9db17537	629	#define TIM_FLAG_CC3 (TIM_SR_CC3IF)
mbed_official	376:cb4d9db17537	630	#define TIM_FLAG_CC4 (TIM_SR_CC4IF)
mbed_official	376:cb4d9db17537	631	#define TIM_FLAG_TRIGGER (TIM_SR_TIF)
mbed_official	376:cb4d9db17537	632	#define TIM_FLAG_CC1OF (TIM_SR_CC1OF)
mbed_official	376:cb4d9db17537	633	#define TIM_FLAG_CC2OF (TIM_SR_CC2OF)
mbed_official	376:cb4d9db17537	634	#define TIM_FLAG_CC3OF (TIM_SR_CC3OF)
mbed_official	376:cb4d9db17537	635	#define TIM_FLAG_CC4OF (TIM_SR_CC4OF)
mbed_official	489:119543c9f674	636	/**
mbed_official	489:119543c9f674	637	* @}
mbed_official	489:119543c9f674	638	*/
mbed_official	489:119543c9f674	639	#define IS_TIM_FLAG(__FLAG__) (((__FLAG__) == TIM_FLAG_UPDATE) \|\| \
mbed_official	489:119543c9f674	640	((__FLAG__) == TIM_FLAG_CC1) \|\| \
mbed_official	489:119543c9f674	641	((__FLAG__) == TIM_FLAG_CC2) \|\| \
mbed_official	489:119543c9f674	642	((__FLAG__) == TIM_FLAG_CC3) \|\| \
mbed_official	489:119543c9f674	643	((__FLAG__) == TIM_FLAG_CC4) \|\| \
mbed_official	489:119543c9f674	644	((__FLAG__) == TIM_FLAG_TRIGGER) \|\| \
mbed_official	489:119543c9f674	645	((__FLAG__) == TIM_FLAG_CC1OF) \|\| \
mbed_official	489:119543c9f674	646	((__FLAG__) == TIM_FLAG_CC2OF) \|\| \
mbed_official	489:119543c9f674	647	((__FLAG__) == TIM_FLAG_CC3OF) \|\| \
mbed_official	489:119543c9f674	648	((__FLAG__) == TIM_FLAG_CC4OF))
mbed_official	376:cb4d9db17537	649
mbed_official	489:119543c9f674	650
mbed_official	489:119543c9f674	651	/** @defgroup TIM_Clock_Source Clock source
mbed_official	489:119543c9f674	652	* @{
mbed_official	489:119543c9f674	653	*/
mbed_official	489:119543c9f674	654	#define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1)
mbed_official	489:119543c9f674	655	#define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0)
mbed_official	489:119543c9f674	656	#define TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x0000)
mbed_official	489:119543c9f674	657	#define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0)
mbed_official	489:119543c9f674	658	#define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1)
mbed_official	489:119543c9f674	659	#define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 \| TIM_SMCR_TS_1)
mbed_official	489:119543c9f674	660	#define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2)
mbed_official	489:119543c9f674	661	#define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 \| TIM_SMCR_TS_2)
mbed_official	489:119543c9f674	662	#define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 \| TIM_SMCR_TS_2)
mbed_official	489:119543c9f674	663	#define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS)
mbed_official	376:cb4d9db17537	664	/**
mbed_official	376:cb4d9db17537	665	* @}
mbed_official	376:cb4d9db17537	666	*/
mbed_official	376:cb4d9db17537	667
mbed_official	489:119543c9f674	668	#define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) \|\| \
mbed_official	489:119543c9f674	669	((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) \|\| \
mbed_official	489:119543c9f674	670	((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) \|\| \
mbed_official	489:119543c9f674	671	((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) \|\| \
mbed_official	489:119543c9f674	672	((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) \|\| \
mbed_official	489:119543c9f674	673	((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) \|\| \
mbed_official	489:119543c9f674	674	((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) \|\| \
mbed_official	489:119543c9f674	675	((__CLOCK__) == TIM_CLOCKSOURCE_TI1) \|\| \
mbed_official	489:119543c9f674	676	((__CLOCK__) == TIM_CLOCKSOURCE_TI2) \|\| \
mbed_official	489:119543c9f674	677	((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1))
mbed_official	376:cb4d9db17537	678
mbed_official	376:cb4d9db17537	679
mbed_official	489:119543c9f674	680	/** @defgroup TIM_Clock_Polarity Clock polarity
mbed_official	376:cb4d9db17537	681	* @{
mbed_official	376:cb4d9db17537	682	*/
mbed_official	376:cb4d9db17537	683	#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx clock sources /
mbed_official	376:cb4d9db17537	684	#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx clock sources /
mbed_official	376:cb4d9db17537	685	#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /!< Polarity for TIx clock sources /
mbed_official	376:cb4d9db17537	686	#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /!< Polarity for TIx clock sources /
mbed_official	376:cb4d9db17537	687	#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /!< Polarity for TIx clock sources /
mbed_official	376:cb4d9db17537	688	/**
mbed_official	376:cb4d9db17537	689	* @}
mbed_official	376:cb4d9db17537	690	*/
mbed_official	489:119543c9f674	691	#define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) \|\| \
mbed_official	489:119543c9f674	692	((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) \|\| \
mbed_official	489:119543c9f674	693	((__POLARITY__) == TIM_CLOCKPOLARITY_RISING) \|\| \
mbed_official	489:119543c9f674	694	((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING) \|\| \
mbed_official	489:119543c9f674	695	((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE))
mbed_official	489:119543c9f674	696
mbed_official	489:119543c9f674	697	/** @defgroup TIM_Clock_Prescaler Clock prescaler
mbed_official	376:cb4d9db17537	698	* @{
mbed_official	376:cb4d9db17537	699	*/
mbed_official	376:cb4d9db17537	700	#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
mbed_official	376:cb4d9db17537	701	#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR Clock: Capture performed once every 2 events. /
mbed_official	376:cb4d9db17537	702	#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR Clock: Capture performed once every 4 events. /
mbed_official	376:cb4d9db17537	703	#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR Clock: Capture performed once every 8 events. /
mbed_official	376:cb4d9db17537	704	/**
mbed_official	376:cb4d9db17537	705	* @}
mbed_official	489:119543c9f674	706	*/
mbed_official	489:119543c9f674	707	#define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) \|\| \
mbed_official	489:119543c9f674	708	((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) \|\| \
mbed_official	489:119543c9f674	709	((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) \|\| \
mbed_official	489:119543c9f674	710	((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8))
mbed_official	489:119543c9f674	711
mbed_official	376:cb4d9db17537	712
mbed_official	489:119543c9f674	713	/* Check clock filter */
mbed_official	489:119543c9f674	714	#define IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xF)
mbed_official	489:119543c9f674	715
mbed_official	489:119543c9f674	716	/** @defgroup TIM_ClearInput_Source Clear input source
mbed_official	376:cb4d9db17537	717	* @{
mbed_official	376:cb4d9db17537	718	*/
mbed_official	489:119543c9f674	719	#define TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x0001)
mbed_official	489:119543c9f674	720	#define TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x0000)
mbed_official	376:cb4d9db17537	721	/**
mbed_official	376:cb4d9db17537	722	* @}
mbed_official	376:cb4d9db17537	723	*/
mbed_official	376:cb4d9db17537	724
mbed_official	489:119543c9f674	725	#define IS_TIM_CLEARINPUT_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_CLEARINPUTSOURCE_NONE) \|\| \
mbed_official	489:119543c9f674	726	((__SOURCE__) == TIM_CLEARINPUTSOURCE_ETR))
mbed_official	376:cb4d9db17537	727
mbed_official	376:cb4d9db17537	728
mbed_official	489:119543c9f674	729	/** @defgroup TIM_ClearInput_Polarity Clear input polarity
mbed_official	376:cb4d9db17537	730	* @{
mbed_official	376:cb4d9db17537	731	*/
mbed_official	376:cb4d9db17537	732	#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx pin /
mbed_official	376:cb4d9db17537	733	#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx pin /
mbed_official	376:cb4d9db17537	734	/**
mbed_official	376:cb4d9db17537	735	* @}
mbed_official	376:cb4d9db17537	736	*/
mbed_official	489:119543c9f674	737	#define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) \|\| \
mbed_official	489:119543c9f674	738	((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
mbed_official	376:cb4d9db17537	739
mbed_official	489:119543c9f674	740
mbed_official	489:119543c9f674	741	/** @defgroup TIM_ClearInput_Prescaler Clear input prescaler
mbed_official	376:cb4d9db17537	742	* @{
mbed_official	376:cb4d9db17537	743	*/
mbed_official	376:cb4d9db17537	744	#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
mbed_official	376:cb4d9db17537	745	#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR pin: Capture performed once every 2 events. /
mbed_official	376:cb4d9db17537	746	#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR pin: Capture performed once every 4 events. /
mbed_official	376:cb4d9db17537	747	#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR pin: Capture performed once every 8 events. /
mbed_official	376:cb4d9db17537	748	/**
mbed_official	376:cb4d9db17537	749	* @}
mbed_official	376:cb4d9db17537	750	*/
mbed_official	489:119543c9f674	751	#define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) \|\| \
mbed_official	489:119543c9f674	752	((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) \|\| \
mbed_official	489:119543c9f674	753	((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) \|\| \
mbed_official	489:119543c9f674	754	((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8))
mbed_official	376:cb4d9db17537	755
mbed_official	376:cb4d9db17537	756
mbed_official	489:119543c9f674	757	/* Check IC filter */
mbed_official	489:119543c9f674	758	#define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
mbed_official	489:119543c9f674	759
mbed_official	489:119543c9f674	760
mbed_official	489:119543c9f674	761	/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
mbed_official	376:cb4d9db17537	762	* @{
mbed_official	376:cb4d9db17537	763	*/
mbed_official	489:119543c9f674	764	#define TIM_TRGO_RESET ((uint32_t)0x0000)
mbed_official	489:119543c9f674	765	#define TIM_TRGO_ENABLE (TIM_CR2_MMS_0)
mbed_official	489:119543c9f674	766	#define TIM_TRGO_UPDATE (TIM_CR2_MMS_1)
mbed_official	489:119543c9f674	767	#define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 \| TIM_CR2_MMS_0))
mbed_official	489:119543c9f674	768	#define TIM_TRGO_OC1REF (TIM_CR2_MMS_2)
mbed_official	489:119543c9f674	769	#define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 \| TIM_CR2_MMS_0))
mbed_official	489:119543c9f674	770	#define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 \| TIM_CR2_MMS_1))
mbed_official	489:119543c9f674	771	#define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 \| TIM_CR2_MMS_1 \| TIM_CR2_MMS_0))
mbed_official	489:119543c9f674	772	/**
mbed_official	489:119543c9f674	773	* @}
mbed_official	489:119543c9f674	774	*/
mbed_official	489:119543c9f674	775	#define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) \|\| \
mbed_official	489:119543c9f674	776	((__SOURCE__) == TIM_TRGO_ENABLE) \|\| \
mbed_official	489:119543c9f674	777	((__SOURCE__) == TIM_TRGO_UPDATE) \|\| \
mbed_official	489:119543c9f674	778	((__SOURCE__) == TIM_TRGO_OC1) \|\| \
mbed_official	489:119543c9f674	779	((__SOURCE__) == TIM_TRGO_OC1REF) \|\| \
mbed_official	489:119543c9f674	780	((__SOURCE__) == TIM_TRGO_OC2REF) \|\| \
mbed_official	489:119543c9f674	781	((__SOURCE__) == TIM_TRGO_OC3REF) \|\| \
mbed_official	489:119543c9f674	782	((__SOURCE__) == TIM_TRGO_OC4REF))
mbed_official	376:cb4d9db17537	783
mbed_official	376:cb4d9db17537	784
mbed_official	489:119543c9f674	785
mbed_official	489:119543c9f674	786	/** @defgroup TIM_Slave_Mode Slave mode
mbed_official	376:cb4d9db17537	787	* @{
mbed_official	376:cb4d9db17537	788	*/
mbed_official	376:cb4d9db17537	789	#define TIM_SLAVEMODE_DISABLE ((uint32_t)0x0000)
mbed_official	376:cb4d9db17537	790	#define TIM_SLAVEMODE_RESET ((uint32_t)0x0004)
mbed_official	376:cb4d9db17537	791	#define TIM_SLAVEMODE_GATED ((uint32_t)0x0005)
mbed_official	376:cb4d9db17537	792	#define TIM_SLAVEMODE_TRIGGER ((uint32_t)0x0006)
mbed_official	376:cb4d9db17537	793	#define TIM_SLAVEMODE_EXTERNAL1 ((uint32_t)0x0007)
mbed_official	376:cb4d9db17537	794	/**
mbed_official	376:cb4d9db17537	795	* @}
mbed_official	489:119543c9f674	796	*/
mbed_official	489:119543c9f674	797	#define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE) \|\| \
mbed_official	489:119543c9f674	798	((__MODE__) == TIM_SLAVEMODE_GATED) \|\| \
mbed_official	489:119543c9f674	799	((__MODE__) == TIM_SLAVEMODE_RESET) \|\| \
mbed_official	489:119543c9f674	800	((__MODE__) == TIM_SLAVEMODE_TRIGGER) \|\| \
mbed_official	489:119543c9f674	801	((__MODE__) == TIM_SLAVEMODE_EXTERNAL1))
mbed_official	376:cb4d9db17537	802
mbed_official	489:119543c9f674	803	/** @defgroup TIM_Master_Slave_Mode Master slave mode
mbed_official	376:cb4d9db17537	804	* @{
mbed_official	376:cb4d9db17537	805	*/
mbed_official	376:cb4d9db17537	806
mbed_official	376:cb4d9db17537	807	#define TIM_MASTERSLAVEMODE_ENABLE ((uint32_t)0x0080)
mbed_official	376:cb4d9db17537	808	#define TIM_MASTERSLAVEMODE_DISABLE ((uint32_t)0x0000)
mbed_official	376:cb4d9db17537	809	/**
mbed_official	376:cb4d9db17537	810	* @}
mbed_official	489:119543c9f674	811	*/
mbed_official	489:119543c9f674	812	#define IS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) \|\| \
mbed_official	489:119543c9f674	813	((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE))
mbed_official	489:119543c9f674	814
mbed_official	489:119543c9f674	815	/** @defgroup TIM_Trigger_Selection Trigger selection
mbed_official	376:cb4d9db17537	816	* @{
mbed_official	376:cb4d9db17537	817	*/
mbed_official	376:cb4d9db17537	818	#define TIM_TS_ITR0 ((uint32_t)0x0000)
mbed_official	376:cb4d9db17537	819	#define TIM_TS_ITR1 ((uint32_t)0x0010)
mbed_official	376:cb4d9db17537	820	#define TIM_TS_ITR2 ((uint32_t)0x0020)
mbed_official	376:cb4d9db17537	821	#define TIM_TS_ITR3 ((uint32_t)0x0030)
mbed_official	376:cb4d9db17537	822	#define TIM_TS_TI1F_ED ((uint32_t)0x0040)
mbed_official	376:cb4d9db17537	823	#define TIM_TS_TI1FP1 ((uint32_t)0x0050)
mbed_official	376:cb4d9db17537	824	#define TIM_TS_TI2FP2 ((uint32_t)0x0060)
mbed_official	376:cb4d9db17537	825	#define TIM_TS_ETRF ((uint32_t)0x0070)
mbed_official	376:cb4d9db17537	826	#define TIM_TS_NONE ((uint32_t)0xFFFF)
mbed_official	376:cb4d9db17537	827	/**
mbed_official	376:cb4d9db17537	828	* @}
mbed_official	489:119543c9f674	829	*/
mbed_official	489:119543c9f674	830	#define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) \|\| \
mbed_official	489:119543c9f674	831	((__SELECTION__) == TIM_TS_ITR1) \|\| \
mbed_official	489:119543c9f674	832	((__SELECTION__) == TIM_TS_ITR2) \|\| \
mbed_official	489:119543c9f674	833	((__SELECTION__) == TIM_TS_ITR3) \|\| \
mbed_official	489:119543c9f674	834	((__SELECTION__) == TIM_TS_TI1F_ED) \|\| \
mbed_official	489:119543c9f674	835	((__SELECTION__) == TIM_TS_TI1FP1) \|\| \
mbed_official	489:119543c9f674	836	((__SELECTION__) == TIM_TS_TI2FP2) \|\| \
mbed_official	489:119543c9f674	837	((__SELECTION__) == TIM_TS_ETRF))
mbed_official	489:119543c9f674	838	#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) \|\| \
mbed_official	489:119543c9f674	839	((__SELECTION__) == TIM_TS_ITR1) \|\| \
mbed_official	489:119543c9f674	840	((__SELECTION__) == TIM_TS_ITR2) \|\| \
mbed_official	489:119543c9f674	841	((__SELECTION__) == TIM_TS_ITR3) \|\| \
mbed_official	489:119543c9f674	842	((__SELECTION__) == TIM_TS_NONE))
mbed_official	376:cb4d9db17537	843
mbed_official	489:119543c9f674	844
mbed_official	489:119543c9f674	845	/** @defgroup TIM_Trigger_Polarity Trigger polarity
mbed_official	376:cb4d9db17537	846	* @{
mbed_official	376:cb4d9db17537	847	*/
mbed_official	376:cb4d9db17537	848	#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx trigger sources /
mbed_official	376:cb4d9db17537	849	#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx trigger sources /
mbed_official	376:cb4d9db17537	850	#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /!< Polarity for TIxFPx or TI1_ED trigger sources /
mbed_official	376:cb4d9db17537	851	#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /!< Polarity for TIxFPx or TI1_ED trigger sources /
mbed_official	376:cb4d9db17537	852	#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /!< Polarity for TIxFPx or TI1_ED trigger sources /
mbed_official	376:cb4d9db17537	853	/**
mbed_official	376:cb4d9db17537	854	* @}
mbed_official	376:cb4d9db17537	855	*/
mbed_official	489:119543c9f674	856	#define IS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) \|\| \
mbed_official	489:119543c9f674	857	((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) \|\| \
mbed_official	489:119543c9f674	858	((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING ) \|\| \
mbed_official	489:119543c9f674	859	((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING ) \|\| \
mbed_official	489:119543c9f674	860	((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE ))
mbed_official	376:cb4d9db17537	861
mbed_official	489:119543c9f674	862
mbed_official	489:119543c9f674	863	/** @defgroup TIM_Trigger_Prescaler Trigger prescaler
mbed_official	376:cb4d9db17537	864	* @{
mbed_official	376:cb4d9db17537	865	*/
mbed_official	376:cb4d9db17537	866	#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
mbed_official	376:cb4d9db17537	867	#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR Trigger: Capture performed once every 2 events. /
mbed_official	376:cb4d9db17537	868	#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR Trigger: Capture performed once every 4 events. /
mbed_official	376:cb4d9db17537	869	#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR Trigger: Capture performed once every 8 events. /
mbed_official	376:cb4d9db17537	870	/**
mbed_official	376:cb4d9db17537	871	* @}
mbed_official	376:cb4d9db17537	872	*/
mbed_official	489:119543c9f674	873	#define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) \|\| \
mbed_official	489:119543c9f674	874	((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) \|\| \
mbed_official	489:119543c9f674	875	((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) \|\| \
mbed_official	489:119543c9f674	876	((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8))
mbed_official	376:cb4d9db17537	877
mbed_official	376:cb4d9db17537	878
mbed_official	489:119543c9f674	879	/* Check trigger filter */
mbed_official	489:119543c9f674	880	#define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xF)
mbed_official	489:119543c9f674	881
mbed_official	489:119543c9f674	882
mbed_official	489:119543c9f674	883	/** @defgroup TIM_TI1_Selection TI1 selection
mbed_official	376:cb4d9db17537	884	* @{
mbed_official	376:cb4d9db17537	885	*/
mbed_official	376:cb4d9db17537	886	#define TIM_TI1SELECTION_CH1 ((uint32_t)0x0000)
mbed_official	376:cb4d9db17537	887	#define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S)
mbed_official	376:cb4d9db17537	888	/**
mbed_official	376:cb4d9db17537	889	* @}
mbed_official	489:119543c9f674	890	*/
mbed_official	489:119543c9f674	891	#define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) \|\| \
mbed_official	489:119543c9f674	892	((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION))
mbed_official	489:119543c9f674	893
mbed_official	376:cb4d9db17537	894
mbed_official	489:119543c9f674	895	/** @defgroup TIM_DMA_Base_address DMA base address
mbed_official	376:cb4d9db17537	896	* @{
mbed_official	376:cb4d9db17537	897	*/
mbed_official	489:119543c9f674	898	#define TIM_DMABASE_CR1 (0x00000000)
mbed_official	489:119543c9f674	899	#define TIM_DMABASE_CR2 (0x00000001)
mbed_official	489:119543c9f674	900	#define TIM_DMABASE_SMCR (0x00000002)
mbed_official	489:119543c9f674	901	#define TIM_DMABASE_DIER (0x00000003)
mbed_official	489:119543c9f674	902	#define TIM_DMABASE_SR (0x00000004)
mbed_official	489:119543c9f674	903	#define TIM_DMABASE_EGR (0x00000005)
mbed_official	489:119543c9f674	904	#define TIM_DMABASE_CCMR1 (0x00000006)
mbed_official	489:119543c9f674	905	#define TIM_DMABASE_CCMR2 (0x00000007)
mbed_official	489:119543c9f674	906	#define TIM_DMABASE_CCER (0x00000008)
mbed_official	489:119543c9f674	907	#define TIM_DMABASE_CNT (0x00000009)
mbed_official	489:119543c9f674	908	#define TIM_DMABASE_PSC (0x0000000A)
mbed_official	489:119543c9f674	909	#define TIM_DMABASE_ARR (0x0000000B)
mbed_official	489:119543c9f674	910	#define TIM_DMABASE_CCR1 (0x0000000D)
mbed_official	489:119543c9f674	911	#define TIM_DMABASE_CCR2 (0x0000000E)
mbed_official	489:119543c9f674	912	#define TIM_DMABASE_CCR3 (0x0000000F)
mbed_official	489:119543c9f674	913	#define TIM_DMABASE_CCR4 (0x00000010)
mbed_official	489:119543c9f674	914	#define TIM_DMABASE_DCR (0x00000012)
mbed_official	489:119543c9f674	915	#define TIM_DMABASE_OR (0x00000013)
mbed_official	376:cb4d9db17537	916	/**
mbed_official	376:cb4d9db17537	917	* @}
mbed_official	489:119543c9f674	918	*/
mbed_official	489:119543c9f674	919	#define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) \|\| \
mbed_official	489:119543c9f674	920	((__BASE__) == TIM_DMABASE_CR2) \|\| \
mbed_official	489:119543c9f674	921	((__BASE__) == TIM_DMABASE_SMCR) \|\| \
mbed_official	489:119543c9f674	922	((__BASE__) == TIM_DMABASE_DIER) \|\| \
mbed_official	489:119543c9f674	923	((__BASE__) == TIM_DMABASE_SR) \|\| \
mbed_official	489:119543c9f674	924	((__BASE__) == TIM_DMABASE_EGR) \|\| \
mbed_official	489:119543c9f674	925	((__BASE__) == TIM_DMABASE_CCMR1) \|\| \
mbed_official	489:119543c9f674	926	((__BASE__) == TIM_DMABASE_CCMR2 ) \|\| \
mbed_official	489:119543c9f674	927	((__BASE__) == TIM_DMABASE_CCER) \|\| \
mbed_official	489:119543c9f674	928	((__BASE__) == TIM_DMABASE_CNT) \|\| \
mbed_official	489:119543c9f674	929	((__BASE__) == TIM_DMABASE_PSC) \|\| \
mbed_official	489:119543c9f674	930	((__BASE__) == TIM_DMABASE_ARR) \|\| \
mbed_official	489:119543c9f674	931	((__BASE__) == TIM_DMABASE_CCR1) \|\| \
mbed_official	489:119543c9f674	932	((__BASE__) == TIM_DMABASE_CCR2) \|\| \
mbed_official	489:119543c9f674	933	((__BASE__) == TIM_DMABASE_CCR3) \|\| \
mbed_official	489:119543c9f674	934	((__BASE__) == TIM_DMABASE_CCR4) \|\| \
mbed_official	489:119543c9f674	935	((__BASE__) == TIM_DMABASE_DCR) \|\| \
mbed_official	489:119543c9f674	936	((__BASE__) == TIM_DMABASE_OR))
mbed_official	376:cb4d9db17537	937
mbed_official	489:119543c9f674	938
mbed_official	489:119543c9f674	939	/** @defgroup TIM_DMA_Burst_Length DMA burst length
mbed_official	376:cb4d9db17537	940	* @{
mbed_official	376:cb4d9db17537	941	*/
mbed_official	489:119543c9f674	942	#define TIM_DMABURSTLENGTH_1TRANSFER (0x00000000)
mbed_official	489:119543c9f674	943	#define TIM_DMABURSTLENGTH_2TRANSFERS (0x00000100)
mbed_official	489:119543c9f674	944	#define TIM_DMABURSTLENGTH_3TRANSFERS (0x00000200)
mbed_official	489:119543c9f674	945	#define TIM_DMABURSTLENGTH_4TRANSFERS (0x00000300)
mbed_official	489:119543c9f674	946	#define TIM_DMABURSTLENGTH_5TRANSFERS (0x00000400)
mbed_official	489:119543c9f674	947	#define TIM_DMABURSTLENGTH_6TRANSFERS (0x00000500)
mbed_official	489:119543c9f674	948	#define TIM_DMABURSTLENGTH_7TRANSFERS (0x00000600)
mbed_official	489:119543c9f674	949	#define TIM_DMABURSTLENGTH_8TRANSFERS (0x00000700)
mbed_official	489:119543c9f674	950	#define TIM_DMABURSTLENGTH_9TRANSFERS (0x00000800)
mbed_official	489:119543c9f674	951	#define TIM_DMABURSTLENGTH_10TRANSFERS (0x00000900)
mbed_official	489:119543c9f674	952	#define TIM_DMABURSTLENGTH_11TRANSFERS (0x00000A00)
mbed_official	489:119543c9f674	953	#define TIM_DMABURSTLENGTH_12TRANSFERS (0x00000B00)
mbed_official	489:119543c9f674	954	#define TIM_DMABURSTLENGTH_13TRANSFERS (0x00000C00)
mbed_official	489:119543c9f674	955	#define TIM_DMABURSTLENGTH_14TRANSFERS (0x00000D00)
mbed_official	489:119543c9f674	956	#define TIM_DMABURSTLENGTH_15TRANSFERS (0x00000E00)
mbed_official	489:119543c9f674	957	#define TIM_DMABURSTLENGTH_16TRANSFERS (0x00000F00)
mbed_official	489:119543c9f674	958	#define TIM_DMABURSTLENGTH_17TRANSFERS (0x00001000)
mbed_official	489:119543c9f674	959	#define TIM_DMABURSTLENGTH_18TRANSFERS (0x00001100)
mbed_official	376:cb4d9db17537	960	/**
mbed_official	376:cb4d9db17537	961	* @}
mbed_official	489:119543c9f674	962	*/
mbed_official	489:119543c9f674	963	#define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER ) \|\| \
mbed_official	489:119543c9f674	964	((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) \|\| \
mbed_official	489:119543c9f674	965	((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) \|\| \
mbed_official	489:119543c9f674	966	((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) \|\| \
mbed_official	489:119543c9f674	967	((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) \|\| \
mbed_official	489:119543c9f674	968	((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) \|\| \
mbed_official	489:119543c9f674	969	((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) \|\| \
mbed_official	489:119543c9f674	970	((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) \|\| \
mbed_official	489:119543c9f674	971	((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS ) \|\| \
mbed_official	489:119543c9f674	972	((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) \|\| \
mbed_official	489:119543c9f674	973	((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS ) \|\| \
mbed_official	489:119543c9f674	974	((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) \|\| \
mbed_official	489:119543c9f674	975	((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) \|\| \
mbed_official	489:119543c9f674	976	((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) \|\| \
mbed_official	489:119543c9f674	977	((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) \|\| \
mbed_official	489:119543c9f674	978	((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) \|\| \
mbed_official	489:119543c9f674	979	((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) \|\| \
mbed_official	489:119543c9f674	980	((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS ))
mbed_official	376:cb4d9db17537	981
mbed_official	376:cb4d9db17537	982
mbed_official	489:119543c9f674	983	/* Check IC filter */
mbed_official	489:119543c9f674	984	#define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xF)
mbed_official	489:119543c9f674	985
mbed_official	489:119543c9f674	986	/** @defgroup DMA_Handle_index DMA handle index
mbed_official	376:cb4d9db17537	987	* @{
mbed_official	376:cb4d9db17537	988	*/
mbed_official	376:cb4d9db17537	989	#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0) /!< Index of the DMA handle used for Update DMA requests /
mbed_official	376:cb4d9db17537	990	#define TIM_DMA_ID_CC1 ((uint16_t) 0x1) /!< Index of the DMA handle used for Capture/Compare 1 DMA requests /
mbed_official	376:cb4d9db17537	991	#define TIM_DMA_ID_CC2 ((uint16_t) 0x2) /!< Index of the DMA handle used for Capture/Compare 2 DMA requests /
mbed_official	376:cb4d9db17537	992	#define TIM_DMA_ID_CC3 ((uint16_t) 0x3) /!< Index of the DMA handle used for Capture/Compare 3 DMA requests /
mbed_official	376:cb4d9db17537	993	#define TIM_DMA_ID_CC4 ((uint16_t) 0x4) /!< Index of the DMA handle used for Capture/Compare 4 DMA requests /
mbed_official	376:cb4d9db17537	994	#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x5) /!< Index of the DMA handle used for Trigger DMA requests /
mbed_official	376:cb4d9db17537	995	/**
mbed_official	376:cb4d9db17537	996	* @}
mbed_official	376:cb4d9db17537	997	*/
mbed_official	376:cb4d9db17537	998
mbed_official	489:119543c9f674	999	/** @defgroup Channel_CC_State Channel state
mbed_official	376:cb4d9db17537	1000	* @{
mbed_official	376:cb4d9db17537	1001	*/
mbed_official	376:cb4d9db17537	1002	#define TIM_CCx_ENABLE ((uint32_t)0x0001)
mbed_official	376:cb4d9db17537	1003	#define TIM_CCx_DISABLE ((uint32_t)0x0000)
mbed_official	376:cb4d9db17537	1004	/**
mbed_official	376:cb4d9db17537	1005	* @}
mbed_official	376:cb4d9db17537	1006	*/
mbed_official	376:cb4d9db17537	1007
mbed_official	376:cb4d9db17537	1008	/**
mbed_official	376:cb4d9db17537	1009	* @}
mbed_official	376:cb4d9db17537	1010	*/
mbed_official	376:cb4d9db17537	1011
mbed_official	376:cb4d9db17537	1012	/* Exported macro ------------------------------------------------------------*/
mbed_official	489:119543c9f674	1013	/** @defgroup TIM_Exported_Macro TIM Exported Macro
mbed_official	376:cb4d9db17537	1014	* @{
mbed_official	376:cb4d9db17537	1015	*/
mbed_official	376:cb4d9db17537	1016
mbed_official	376:cb4d9db17537	1017	/** @brief Reset UART handle state
mbed_official	489:119543c9f674	1018	* @param __HANDLE__ : TIM handle
mbed_official	376:cb4d9db17537	1019	* @retval None
mbed_official	376:cb4d9db17537	1020	*/
mbed_official	376:cb4d9db17537	1021	#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
mbed_official	376:cb4d9db17537	1022
mbed_official	376:cb4d9db17537	1023	/**
mbed_official	376:cb4d9db17537	1024	* @brief Enable the TIM peripheral.
mbed_official	489:119543c9f674	1025	* @param __HANDLE__ : TIM handle
mbed_official	376:cb4d9db17537	1026	* @retval None
mbed_official	376:cb4d9db17537	1027	*/
mbed_official	376:cb4d9db17537	1028	#define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1\|=(TIM_CR1_CEN))
mbed_official	376:cb4d9db17537	1029
mbed_official	376:cb4d9db17537	1030	/* The counter of a timer instance is disabled only if all the CCx channels have
mbed_official	376:cb4d9db17537	1031	been disabled */
mbed_official	489:119543c9f674	1032	#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E \| TIM_CCER_CC2E \| TIM_CCER_CC3E \| TIM_CCER_CC4E))
mbed_official	376:cb4d9db17537	1033
mbed_official	376:cb4d9db17537	1034	/**
mbed_official	376:cb4d9db17537	1035	* @brief Disable the TIM peripheral.
mbed_official	489:119543c9f674	1036	* @param __HANDLE__ : TIM handle
mbed_official	376:cb4d9db17537	1037	* @retval None
mbed_official	376:cb4d9db17537	1038	*/
mbed_official	376:cb4d9db17537	1039	#define __HAL_TIM_DISABLE(__HANDLE__) \
mbed_official	376:cb4d9db17537	1040	do { \
mbed_official	489:119543c9f674	1041	if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \
mbed_official	376:cb4d9db17537	1042	{ \
mbed_official	376:cb4d9db17537	1043	(__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
mbed_official	376:cb4d9db17537	1044	} \
mbed_official	376:cb4d9db17537	1045	} while(0)
mbed_official	376:cb4d9db17537	1046
mbed_official	376:cb4d9db17537	1047	#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER \|= (__INTERRUPT__))
mbed_official	376:cb4d9db17537	1048	#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER \|= (__DMA__))
mbed_official	376:cb4d9db17537	1049	#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
mbed_official	376:cb4d9db17537	1050	#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
mbed_official	376:cb4d9db17537	1051	#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
mbed_official	376:cb4d9db17537	1052	#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
mbed_official	376:cb4d9db17537	1053
mbed_official	489:119543c9f674	1054	#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
mbed_official	376:cb4d9db17537	1055	#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
mbed_official	376:cb4d9db17537	1056
mbed_official	489:119543c9f674	1057	#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
mbed_official	489:119543c9f674	1058	#define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
mbed_official	376:cb4d9db17537	1059
mbed_official	489:119543c9f674	1060	#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
mbed_official	376:cb4d9db17537	1061	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 \|= (__ICPSC__)) :\
mbed_official	376:cb4d9db17537	1062	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 \|= ((__ICPSC__) << 8)) :\
mbed_official	376:cb4d9db17537	1063	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 \|= (__ICPSC__)) :\
mbed_official	376:cb4d9db17537	1064	((__HANDLE__)->Instance->CCMR2 \|= ((__ICPSC__) << 8)))
mbed_official	376:cb4d9db17537	1065
mbed_official	489:119543c9f674	1066	#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
mbed_official	376:cb4d9db17537	1067	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\
mbed_official	376:cb4d9db17537	1068	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\
mbed_official	376:cb4d9db17537	1069	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\
mbed_official	376:cb4d9db17537	1070	((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC))
mbed_official	376:cb4d9db17537	1071
mbed_official	489:119543c9f674	1072	#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
mbed_official	489:119543c9f674	1073	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER \|= (__POLARITY__)) :\
mbed_official	489:119543c9f674	1074	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER \|= ((__POLARITY__) << 4)) :\
mbed_official	489:119543c9f674	1075	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER \|= ((__POLARITY__) << 8)) :\
mbed_official	489:119543c9f674	1076	((__HANDLE__)->Instance->CCER \|= (((__POLARITY__) << 12) & TIM_CCER_CC4P)))
mbed_official	489:119543c9f674	1077
mbed_official	489:119543c9f674	1078	#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
mbed_official	489:119543c9f674	1079	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P \| TIM_CCER_CC1NP)) :\
mbed_official	489:119543c9f674	1080	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P \| TIM_CCER_CC2NP)) :\
mbed_official	489:119543c9f674	1081	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P \| TIM_CCER_CC3NP)) :\
mbed_official	489:119543c9f674	1082	((__HANDLE__)->Instance->CCER &= (uint16_t)~TIM_CCER_CC4P))
mbed_official	489:119543c9f674	1083
mbed_official	376:cb4d9db17537	1084	/**
mbed_official	376:cb4d9db17537	1085	* @brief Sets the TIM Capture Compare Register value on runtime without
mbed_official	376:cb4d9db17537	1086	* calling another time ConfigChannel function.
mbed_official	489:119543c9f674	1087	* @param __HANDLE__ : TIM handle.
mbed_official	376:cb4d9db17537	1088	* @param __CHANNEL__ : TIM Channels to be configured.
mbed_official	376:cb4d9db17537	1089	* This parameter can be one of the following values:
mbed_official	376:cb4d9db17537	1090	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	376:cb4d9db17537	1091	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	376:cb4d9db17537	1092	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official	376:cb4d9db17537	1093	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official	376:cb4d9db17537	1094	* @param __COMPARE__: specifies the Capture Compare register new value.
mbed_official	376:cb4d9db17537	1095	* @retval None
mbed_official	376:cb4d9db17537	1096	*/
mbed_official	489:119543c9f674	1097	#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
mbed_official	376:cb4d9db17537	1098	((__IO uint32_t )(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)) = (__COMPARE__))
mbed_official	376:cb4d9db17537	1099
mbed_official	376:cb4d9db17537	1100	/**
mbed_official	376:cb4d9db17537	1101	* @brief Gets the TIM Capture Compare Register value on runtime
mbed_official	489:119543c9f674	1102	* @param __HANDLE__ : TIM handle.
mbed_official	376:cb4d9db17537	1103	* @param __CHANNEL__ : TIM Channel associated with the capture compare register
mbed_official	376:cb4d9db17537	1104	* This parameter can be one of the following values:
mbed_official	376:cb4d9db17537	1105	* @arg TIM_CHANNEL_1: get capture/compare 1 register value
mbed_official	376:cb4d9db17537	1106	* @arg TIM_CHANNEL_2: get capture/compare 2 register value
mbed_official	376:cb4d9db17537	1107	* @arg TIM_CHANNEL_3: get capture/compare 3 register value
mbed_official	376:cb4d9db17537	1108	* @arg TIM_CHANNEL_4: get capture/compare 4 register value
mbed_official	376:cb4d9db17537	1109	* @retval None
mbed_official	376:cb4d9db17537	1110	*/
mbed_official	489:119543c9f674	1111	#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
mbed_official	376:cb4d9db17537	1112	((__IO uint32_t )(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)))
mbed_official	376:cb4d9db17537	1113
mbed_official	376:cb4d9db17537	1114	/**
mbed_official	376:cb4d9db17537	1115	* @brief Sets the TIM Counter Register value on runtime.
mbed_official	489:119543c9f674	1116	* @param __HANDLE__ : TIM handle.
mbed_official	376:cb4d9db17537	1117	* @param __COUNTER__: specifies the Counter register new value.
mbed_official	376:cb4d9db17537	1118	* @retval None
mbed_official	376:cb4d9db17537	1119	*/
mbed_official	489:119543c9f674	1120	#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
mbed_official	376:cb4d9db17537	1121
mbed_official	376:cb4d9db17537	1122	/**
mbed_official	376:cb4d9db17537	1123	* @brief Gets the TIM Counter Register value on runtime.
mbed_official	489:119543c9f674	1124	* @param __HANDLE__ : TIM handle.
mbed_official	376:cb4d9db17537	1125	* @retval None
mbed_official	376:cb4d9db17537	1126	*/
mbed_official	489:119543c9f674	1127	#define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT)
mbed_official	376:cb4d9db17537	1128
mbed_official	376:cb4d9db17537	1129	/**
mbed_official	376:cb4d9db17537	1130	* @brief Sets the TIM Autoreload Register value on runtime without calling
mbed_official	376:cb4d9db17537	1131	* another time any Init function.
mbed_official	489:119543c9f674	1132	* @param __HANDLE__ : TIM handle.
mbed_official	376:cb4d9db17537	1133	* @param __AUTORELOAD__: specifies the Counter register new value.
mbed_official	376:cb4d9db17537	1134	* @retval None
mbed_official	376:cb4d9db17537	1135	*/
mbed_official	489:119543c9f674	1136	#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
mbed_official	376:cb4d9db17537	1137	do{ \
mbed_official	376:cb4d9db17537	1138	(__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
mbed_official	376:cb4d9db17537	1139	(__HANDLE__)->Init.Period = (__AUTORELOAD__); \
mbed_official	376:cb4d9db17537	1140	} while(0)
mbed_official	376:cb4d9db17537	1141	/**
mbed_official	376:cb4d9db17537	1142	* @brief Gets the TIM Autoreload Register value on runtime
mbed_official	489:119543c9f674	1143	* @param __HANDLE__ : TIM handle.
mbed_official	376:cb4d9db17537	1144	* @retval None
mbed_official	376:cb4d9db17537	1145	*/
mbed_official	489:119543c9f674	1146	#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR)
mbed_official	376:cb4d9db17537	1147
mbed_official	376:cb4d9db17537	1148	/**
mbed_official	376:cb4d9db17537	1149	* @brief Sets the TIM Clock Division value on runtime without calling
mbed_official	376:cb4d9db17537	1150	* another time any Init function.
mbed_official	489:119543c9f674	1151	* @param __HANDLE__ : TIM handle.
mbed_official	376:cb4d9db17537	1152	* @param __CKD__: specifies the clock division value.
mbed_official	376:cb4d9db17537	1153	* This parameter can be one of the following value:
mbed_official	376:cb4d9db17537	1154	* @arg TIM_CLOCKDIVISION_DIV1
mbed_official	376:cb4d9db17537	1155	* @arg TIM_CLOCKDIVISION_DIV2
mbed_official	376:cb4d9db17537	1156	* @arg TIM_CLOCKDIVISION_DIV4
mbed_official	376:cb4d9db17537	1157	* @retval None
mbed_official	376:cb4d9db17537	1158	*/
mbed_official	489:119543c9f674	1159	#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
mbed_official	376:cb4d9db17537	1160	do{ \
mbed_official	376:cb4d9db17537	1161	(__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD); \
mbed_official	376:cb4d9db17537	1162	(__HANDLE__)->Instance->CR1 \|= (__CKD__); \
mbed_official	376:cb4d9db17537	1163	(__HANDLE__)->Init.ClockDivision = (__CKD__); \
mbed_official	376:cb4d9db17537	1164	} while(0)
mbed_official	376:cb4d9db17537	1165	/**
mbed_official	376:cb4d9db17537	1166	* @brief Gets the TIM Clock Division value on runtime
mbed_official	489:119543c9f674	1167	* @param __HANDLE__ : TIM handle.
mbed_official	376:cb4d9db17537	1168	* @retval None
mbed_official	376:cb4d9db17537	1169	*/
mbed_official	489:119543c9f674	1170	#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
mbed_official	376:cb4d9db17537	1171
mbed_official	376:cb4d9db17537	1172	/**
mbed_official	376:cb4d9db17537	1173	* @brief Sets the TIM Input Capture prescaler on runtime without calling
mbed_official	376:cb4d9db17537	1174	* another time HAL_TIM_IC_ConfigChannel() function.
mbed_official	489:119543c9f674	1175	* @param __HANDLE__ : TIM handle.
mbed_official	376:cb4d9db17537	1176	* @param __CHANNEL__ : TIM Channels to be configured.
mbed_official	376:cb4d9db17537	1177	* This parameter can be one of the following values:
mbed_official	376:cb4d9db17537	1178	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	376:cb4d9db17537	1179	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	376:cb4d9db17537	1180	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official	376:cb4d9db17537	1181	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official	376:cb4d9db17537	1182	* @param __ICPSC__: specifies the Input Capture4 prescaler new value.
mbed_official	376:cb4d9db17537	1183	* This parameter can be one of the following values:
mbed_official	376:cb4d9db17537	1184	* @arg TIM_ICPSC_DIV1: no prescaler
mbed_official	376:cb4d9db17537	1185	* @arg TIM_ICPSC_DIV2: capture is done once every 2 events
mbed_official	376:cb4d9db17537	1186	* @arg TIM_ICPSC_DIV4: capture is done once every 4 events
mbed_official	376:cb4d9db17537	1187	* @arg TIM_ICPSC_DIV8: capture is done once every 8 events
mbed_official	376:cb4d9db17537	1188	* @retval None
mbed_official	376:cb4d9db17537	1189	*/
mbed_official	489:119543c9f674	1190	#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
mbed_official	376:cb4d9db17537	1191	do{ \
mbed_official	489:119543c9f674	1192	TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \
mbed_official	489:119543c9f674	1193	TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
mbed_official	376:cb4d9db17537	1194	} while(0)
mbed_official	376:cb4d9db17537	1195
mbed_official	376:cb4d9db17537	1196	/**
mbed_official	376:cb4d9db17537	1197	* @brief Gets the TIM Input Capture prescaler on runtime
mbed_official	489:119543c9f674	1198	* @param __HANDLE__ : TIM handle.
mbed_official	376:cb4d9db17537	1199	* @param __CHANNEL__ : TIM Channels to be configured.
mbed_official	376:cb4d9db17537	1200	* This parameter can be one of the following values:
mbed_official	376:cb4d9db17537	1201	* @arg TIM_CHANNEL_1: get input capture 1 prescaler value
mbed_official	376:cb4d9db17537	1202	* @arg TIM_CHANNEL_2: get input capture 2 prescaler value
mbed_official	376:cb4d9db17537	1203	* @arg TIM_CHANNEL_3: get input capture 3 prescaler value
mbed_official	376:cb4d9db17537	1204	* @arg TIM_CHANNEL_4: get input capture 4 prescaler value
mbed_official	376:cb4d9db17537	1205	* @retval None
mbed_official	376:cb4d9db17537	1206	*/
mbed_official	489:119543c9f674	1207	#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \
mbed_official	376:cb4d9db17537	1208	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
mbed_official	376:cb4d9db17537	1209	((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8) :\
mbed_official	376:cb4d9db17537	1210	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
mbed_official	376:cb4d9db17537	1211	(((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8)
mbed_official	376:cb4d9db17537	1212
mbed_official	376:cb4d9db17537	1213
mbed_official	376:cb4d9db17537	1214	/**
mbed_official	489:119543c9f674	1215	* @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register
mbed_official	489:119543c9f674	1216	* @param __HANDLE__: TIM handle.
mbed_official	489:119543c9f674	1217	* @note When the URS bit of the TIMx_CR1 register is set, only counter
mbed_official	489:119543c9f674	1218	* overflow/underflow generates an update interrupt or DMA request (if
mbed_official	489:119543c9f674	1219	* enabled)
mbed_official	489:119543c9f674	1220	* @retval None
mbed_official	489:119543c9f674	1221	*/
mbed_official	489:119543c9f674	1222	#define __HAL_TIM_URS_ENABLE(__HANDLE__) \
mbed_official	489:119543c9f674	1223	((__HANDLE__)->Instance->CR1\|= (TIM_CR1_URS))
mbed_official	489:119543c9f674	1224
mbed_official	489:119543c9f674	1225	/**
mbed_official	489:119543c9f674	1226	* @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register
mbed_official	489:119543c9f674	1227	* @param __HANDLE__: TIM handle.
mbed_official	489:119543c9f674	1228	* @note When the URS bit of the TIMx_CR1 register is reset, any of the
mbed_official	489:119543c9f674	1229	* following events generate an update interrupt or DMA request (if
mbed_official	489:119543c9f674	1230	* enabled):
mbed_official	489:119543c9f674	1231	* Counter overflow/underflow
mbed_official	489:119543c9f674	1232	* Setting the UG bit
mbed_official	489:119543c9f674	1233	* Update generation through the slave mode controller
mbed_official	489:119543c9f674	1234	* @retval None
mbed_official	489:119543c9f674	1235	*/
mbed_official	489:119543c9f674	1236	#define __HAL_TIM_URS_DISABLE(__HANDLE__) \
mbed_official	489:119543c9f674	1237	((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS))
mbed_official	489:119543c9f674	1238
mbed_official	489:119543c9f674	1239	/**
mbed_official	489:119543c9f674	1240	* @brief Sets the TIM Capture x input polarity on runtime.
mbed_official	489:119543c9f674	1241	* @param __HANDLE__: TIM handle.
mbed_official	489:119543c9f674	1242	* @param __CHANNEL__: TIM Channels to be configured.
mbed_official	489:119543c9f674	1243	* This parameter can be one of the following values:
mbed_official	489:119543c9f674	1244	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	489:119543c9f674	1245	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	489:119543c9f674	1246	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official	489:119543c9f674	1247	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official	489:119543c9f674	1248	* @param __POLARITY__: Polarity for TIx source
mbed_official	489:119543c9f674	1249	* @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
mbed_official	489:119543c9f674	1250	* @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
mbed_official	489:119543c9f674	1251	* @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
mbed_official	489:119543c9f674	1252	* @note The polarity TIM_INPUTCHANNELPOLARITY_BOTHEDGE is not authorized for TIM Channel 4.
mbed_official	489:119543c9f674	1253	* @retval None
mbed_official	489:119543c9f674	1254	*/
mbed_official	489:119543c9f674	1255	#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
mbed_official	489:119543c9f674	1256	do{ \
mbed_official	489:119543c9f674	1257	TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \
mbed_official	489:119543c9f674	1258	TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
mbed_official	489:119543c9f674	1259	}while(0)
mbed_official	489:119543c9f674	1260
mbed_official	489:119543c9f674	1261	/**
mbed_official	376:cb4d9db17537	1262	* @}
mbed_official	376:cb4d9db17537	1263	*/
mbed_official	376:cb4d9db17537	1264
mbed_official	376:cb4d9db17537	1265	/* Include TIM HAL Extension module */
mbed_official	376:cb4d9db17537	1266	#include "stm32l0xx_hal_tim_ex.h"
mbed_official	376:cb4d9db17537	1267
mbed_official	376:cb4d9db17537	1268	/* Exported functions --------------------------------------------------------*/
mbed_official	489:119543c9f674	1269	/** @defgroup TIM_Exported_Functions TIM Exported Functions
mbed_official	489:119543c9f674	1270	* @{
mbed_official	489:119543c9f674	1271	*/
mbed_official	489:119543c9f674	1272
mbed_official	489:119543c9f674	1273	/* Exported functions --------------------------------------------------------*/
mbed_official	376:cb4d9db17537	1274	/* Time Base functions ********************************************************/
mbed_official	489:119543c9f674	1275
mbed_official	489:119543c9f674	1276	/** @defgroup TIM_Exported_Functions_Group1 Timer Base functions
mbed_official	489:119543c9f674	1277	* @brief Time Base functions
mbed_official	489:119543c9f674	1278	* @{
mbed_official	489:119543c9f674	1279	*/
mbed_official	376:cb4d9db17537	1280	HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
mbed_official	376:cb4d9db17537	1281	HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
mbed_official	376:cb4d9db17537	1282	void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
mbed_official	376:cb4d9db17537	1283	void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
mbed_official	376:cb4d9db17537	1284	/* Blocking mode: Polling */
mbed_official	376:cb4d9db17537	1285	HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
mbed_official	376:cb4d9db17537	1286	HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
mbed_official	376:cb4d9db17537	1287	/* Non-Blocking mode: Interrupt */
mbed_official	376:cb4d9db17537	1288	HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
mbed_official	376:cb4d9db17537	1289	HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
mbed_official	376:cb4d9db17537	1290	/* Non-Blocking mode: DMA */
mbed_official	376:cb4d9db17537	1291	HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef htim, uint32_t pData, uint16_t Length);
mbed_official	376:cb4d9db17537	1292	HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
mbed_official	376:cb4d9db17537	1293
mbed_official	489:119543c9f674	1294	/**
mbed_official	489:119543c9f674	1295	* @}
mbed_official	489:119543c9f674	1296	*/
mbed_official	489:119543c9f674	1297
mbed_official	489:119543c9f674	1298
mbed_official	376:cb4d9db17537	1299	/* Timer Output Compare functions **********************************************/
mbed_official	489:119543c9f674	1300
mbed_official	489:119543c9f674	1301	/** @defgroup TIM_Exported_Functions_Group2 Timer Output Compare functions
mbed_official	489:119543c9f674	1302	* @brief Timer Output Compare functions
mbed_official	489:119543c9f674	1303	* @{
mbed_official	489:119543c9f674	1304	*/
mbed_official	489:119543c9f674	1305
mbed_official	376:cb4d9db17537	1306	HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
mbed_official	376:cb4d9db17537	1307	HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
mbed_official	376:cb4d9db17537	1308	void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
mbed_official	376:cb4d9db17537	1309	void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
mbed_official	376:cb4d9db17537	1310	/* Blocking mode: Polling */
mbed_official	376:cb4d9db17537	1311	HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	376:cb4d9db17537	1312	HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	376:cb4d9db17537	1313	/* Non-Blocking mode: Interrupt */
mbed_official	376:cb4d9db17537	1314	HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	376:cb4d9db17537	1315	HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	376:cb4d9db17537	1316	/* Non-Blocking mode: DMA */
mbed_official	376:cb4d9db17537	1317	HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
mbed_official	376:cb4d9db17537	1318	HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	489:119543c9f674	1319	/**
mbed_official	489:119543c9f674	1320	* @}
mbed_official	489:119543c9f674	1321	*/
mbed_official	489:119543c9f674	1322
mbed_official	376:cb4d9db17537	1323
mbed_official	376:cb4d9db17537	1324	/* Timer PWM functions *********************************************************/
mbed_official	489:119543c9f674	1325
mbed_official	489:119543c9f674	1326	/** @defgroup TIM_Exported_Functions_Group3 Timer PWM functions
mbed_official	489:119543c9f674	1327	* @brief Timer PWM functions
mbed_official	489:119543c9f674	1328	* @{
mbed_official	489:119543c9f674	1329	*/
mbed_official	376:cb4d9db17537	1330	HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
mbed_official	376:cb4d9db17537	1331	HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
mbed_official	376:cb4d9db17537	1332	void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
mbed_official	376:cb4d9db17537	1333	void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
mbed_official	376:cb4d9db17537	1334	/* Blocking mode: Polling */
mbed_official	376:cb4d9db17537	1335	HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	376:cb4d9db17537	1336	HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	376:cb4d9db17537	1337	/* Non-Blocking mode: Interrupt */
mbed_official	376:cb4d9db17537	1338	HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	376:cb4d9db17537	1339	HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	376:cb4d9db17537	1340	/* Non-Blocking mode: DMA */
mbed_official	376:cb4d9db17537	1341	HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
mbed_official	376:cb4d9db17537	1342	HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	489:119543c9f674	1343	/**
mbed_official	489:119543c9f674	1344	* @}
mbed_official	489:119543c9f674	1345	*/
mbed_official	376:cb4d9db17537	1346
mbed_official	376:cb4d9db17537	1347	/* Timer Input Capture functions ***********************************************/
mbed_official	489:119543c9f674	1348
mbed_official	489:119543c9f674	1349	/** @defgroup TIM_Exported_Functions_Group4 Timer Input Capture functions
mbed_official	489:119543c9f674	1350	* @brief Timer Input Capture functions
mbed_official	489:119543c9f674	1351	* @{
mbed_official	489:119543c9f674	1352	*/
mbed_official	376:cb4d9db17537	1353	HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
mbed_official	376:cb4d9db17537	1354	HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
mbed_official	376:cb4d9db17537	1355	void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
mbed_official	376:cb4d9db17537	1356	void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
mbed_official	376:cb4d9db17537	1357	/* Blocking mode: Polling */
mbed_official	376:cb4d9db17537	1358	HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	376:cb4d9db17537	1359	HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	376:cb4d9db17537	1360	/* Non-Blocking mode: Interrupt */
mbed_official	376:cb4d9db17537	1361	HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	376:cb4d9db17537	1362	HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	376:cb4d9db17537	1363	/* Non-Blocking mode: DMA */
mbed_official	376:cb4d9db17537	1364	HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
mbed_official	376:cb4d9db17537	1365	HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	489:119543c9f674	1366	/**
mbed_official	489:119543c9f674	1367	* @}
mbed_official	489:119543c9f674	1368	*/
mbed_official	376:cb4d9db17537	1369
mbed_official	376:cb4d9db17537	1370	/* Timer One Pulse functions ***************************************************/
mbed_official	489:119543c9f674	1371
mbed_official	489:119543c9f674	1372	/** @defgroup TIM_Exported_Functions_Group5 Timer One Pulse functions
mbed_official	489:119543c9f674	1373	* @brief Timer One Pulse functions
mbed_official	489:119543c9f674	1374	* @{
mbed_official	489:119543c9f674	1375	*/
mbed_official	376:cb4d9db17537	1376	HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
mbed_official	376:cb4d9db17537	1377	HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
mbed_official	376:cb4d9db17537	1378	void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
mbed_official	376:cb4d9db17537	1379	void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
mbed_official	376:cb4d9db17537	1380	/* Blocking mode: Polling */
mbed_official	376:cb4d9db17537	1381	HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
mbed_official	376:cb4d9db17537	1382	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
mbed_official	376:cb4d9db17537	1383
mbed_official	376:cb4d9db17537	1384	/* Non-Blocking mode: Interrupt */
mbed_official	376:cb4d9db17537	1385	HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
mbed_official	376:cb4d9db17537	1386	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
mbed_official	376:cb4d9db17537	1387
mbed_official	489:119543c9f674	1388	/**
mbed_official	489:119543c9f674	1389	* @}
mbed_official	489:119543c9f674	1390	*/
mbed_official	489:119543c9f674	1391
mbed_official	376:cb4d9db17537	1392	/* Timer Encoder functions *****************************************************/
mbed_official	489:119543c9f674	1393
mbed_official	489:119543c9f674	1394	/** @defgroup TIM_Exported_Functions_Group6 Timer Encoder functions
mbed_official	489:119543c9f674	1395	* @brief Timer Encoder functions
mbed_official	489:119543c9f674	1396	* @{
mbed_official	489:119543c9f674	1397	*/
mbed_official	376:cb4d9db17537	1398	HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef htim, TIM_Encoder_InitTypeDef sConfig);
mbed_official	376:cb4d9db17537	1399	HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
mbed_official	376:cb4d9db17537	1400	void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
mbed_official	376:cb4d9db17537	1401	void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
mbed_official	376:cb4d9db17537	1402	/* Blocking mode: Polling */
mbed_official	376:cb4d9db17537	1403	HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	376:cb4d9db17537	1404	HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	376:cb4d9db17537	1405	/* Non-Blocking mode: Interrupt */
mbed_official	376:cb4d9db17537	1406	HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	376:cb4d9db17537	1407	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	376:cb4d9db17537	1408	/* Non-Blocking mode: DMA */
mbed_official	376:cb4d9db17537	1409	HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData1, uint32_t *pData2, uint16_t Length);
mbed_official	376:cb4d9db17537	1410	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	376:cb4d9db17537	1411
mbed_official	489:119543c9f674	1412	/**
mbed_official	489:119543c9f674	1413	* @}
mbed_official	489:119543c9f674	1414	*/
mbed_official	489:119543c9f674	1415
mbed_official	376:cb4d9db17537	1416	/* Interrupt Handler functions **********************************************/
mbed_official	489:119543c9f674	1417
mbed_official	489:119543c9f674	1418	/** @defgroup TIM_Exported_Functions_Group7 Timer IRQ handler management
mbed_official	489:119543c9f674	1419	* @brief Interrupt Handler functions
mbed_official	489:119543c9f674	1420	* @{
mbed_official	489:119543c9f674	1421	*/
mbed_official	376:cb4d9db17537	1422	void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
mbed_official	489:119543c9f674	1423	/**
mbed_official	489:119543c9f674	1424	* @}
mbed_official	489:119543c9f674	1425	*/
mbed_official	376:cb4d9db17537	1426
mbed_official	376:cb4d9db17537	1427	/* Control functions *********************************************************/
mbed_official	489:119543c9f674	1428
mbed_official	489:119543c9f674	1429	/** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions
mbed_official	489:119543c9f674	1430	* @brief Control functions
mbed_official	489:119543c9f674	1431	* @{
mbed_official	489:119543c9f674	1432	*/
mbed_official	376:cb4d9db17537	1433	HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef htim, TIM_OC_InitTypeDef sConfig, uint32_t Channel);
mbed_official	376:cb4d9db17537	1434	HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef htim, TIM_OC_InitTypeDef sConfig, uint32_t Channel);
mbed_official	376:cb4d9db17537	1435	HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef htim, TIM_IC_InitTypeDef sConfig, uint32_t Channel);
mbed_official	376:cb4d9db17537	1436	HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef htim, TIM_OnePulse_InitTypeDef sConfig, uint32_t OutputChannel, uint32_t InputChannel);
mbed_official	376:cb4d9db17537	1437	HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef htim, TIM_ClearInputConfigTypeDef sClearInputConfig, uint32_t Channel);
mbed_official	376:cb4d9db17537	1438	HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef htim, TIM_ClockConfigTypeDef sClockSourceConfig);
mbed_official	376:cb4d9db17537	1439	HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
mbed_official	376:cb4d9db17537	1440	HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef htim, TIM_SlaveConfigTypeDef sSlaveConfig);
mbed_official	489:119543c9f674	1441	HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef htim, TIM_SlaveConfigTypeDef sSlaveConfig);
mbed_official	376:cb4d9db17537	1442	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
mbed_official	376:cb4d9db17537	1443	uint32_t *BurstBuffer, uint32_t BurstLength);
mbed_official	376:cb4d9db17537	1444	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
mbed_official	376:cb4d9db17537	1445	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
mbed_official	376:cb4d9db17537	1446	uint32_t *BurstBuffer, uint32_t BurstLength);
mbed_official	376:cb4d9db17537	1447	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
mbed_official	376:cb4d9db17537	1448	HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
mbed_official	376:cb4d9db17537	1449	uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	376:cb4d9db17537	1450
mbed_official	489:119543c9f674	1451	/**
mbed_official	489:119543c9f674	1452	* @}
mbed_official	489:119543c9f674	1453	*/
mbed_official	489:119543c9f674	1454
mbed_official	376:cb4d9db17537	1455	/* Callback in non blocking modes (Interrupt and DMA) *************************/
mbed_official	489:119543c9f674	1456
mbed_official	489:119543c9f674	1457	/** @defgroup TIM_Exported_Functions_Group9 Timer Callbacks functions
mbed_official	489:119543c9f674	1458	* @brief Callback functions
mbed_official	489:119543c9f674	1459	* @{
mbed_official	489:119543c9f674	1460	*/
mbed_official	376:cb4d9db17537	1461	void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
mbed_official	376:cb4d9db17537	1462	void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
mbed_official	376:cb4d9db17537	1463	void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
mbed_official	376:cb4d9db17537	1464	void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
mbed_official	376:cb4d9db17537	1465	void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
mbed_official	376:cb4d9db17537	1466	void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
mbed_official	489:119543c9f674	1467	/**
mbed_official	489:119543c9f674	1468	* @}
mbed_official	489:119543c9f674	1469	*/
mbed_official	489:119543c9f674	1470
mbed_official	376:cb4d9db17537	1471
mbed_official	376:cb4d9db17537	1472	/* Peripheral State functions **************************************************/
mbed_official	489:119543c9f674	1473
mbed_official	489:119543c9f674	1474	/** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions
mbed_official	489:119543c9f674	1475	* @brief Peripheral State functions
mbed_official	489:119543c9f674	1476	* @{
mbed_official	489:119543c9f674	1477	*/
mbed_official	376:cb4d9db17537	1478	HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
mbed_official	376:cb4d9db17537	1479	HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
mbed_official	376:cb4d9db17537	1480	HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
mbed_official	376:cb4d9db17537	1481	HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
mbed_official	376:cb4d9db17537	1482	HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
mbed_official	376:cb4d9db17537	1483	HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
mbed_official	489:119543c9f674	1484	void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
mbed_official	489:119543c9f674	1485	void TIM_DMAError(DMA_HandleTypeDef *hdma);
mbed_official	489:119543c9f674	1486	void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
mbed_official	376:cb4d9db17537	1487
mbed_official	376:cb4d9db17537	1488	/**
mbed_official	376:cb4d9db17537	1489	* @}
mbed_official	376:cb4d9db17537	1490	*/
mbed_official	376:cb4d9db17537	1491
mbed_official	376:cb4d9db17537	1492	/**
mbed_official	376:cb4d9db17537	1493	* @}
mbed_official	489:119543c9f674	1494	*/
mbed_official	489:119543c9f674	1495
mbed_official	489:119543c9f674	1496	/**
mbed_official	489:119543c9f674	1497	* @}
mbed_official	489:119543c9f674	1498	*/
mbed_official	489:119543c9f674	1499
mbed_official	489:119543c9f674	1500	/**
mbed_official	489:119543c9f674	1501	* @}
mbed_official	489:119543c9f674	1502	*/
mbed_official	489:119543c9f674	1503
mbed_official	376:cb4d9db17537	1504	#ifdef __cplusplus
mbed_official	376:cb4d9db17537	1505	}
mbed_official	376:cb4d9db17537	1506	#endif
mbed_official	376:cb4d9db17537	1507
mbed_official	376:cb4d9db17537	1508	#endif /* __STM32L0xx_HAL_TIM_H */
mbed_official	376:cb4d9db17537	1509
mbed_official	376:cb4d9db17537	1510	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/
mbed_official	489:119543c9f674	1511