mbed-src - mbed library sources

Users » mbed_official » Code » mbed-src

mbed library sources

Dependents: Encrypted my_mbed lklk CyaSSL_DTLS_Cellular ... more

Superseded

This library was superseded by mbed-dev - https://os.mbed.com/users/mbed_official/code/mbed-dev/.

Development branch of the mbed library sources. This library is kept in synch with the latest changes from the mbed SDK and it is not guaranteed to work.

If you are looking for a stable and tested release, please import one of the official mbed library releases:

Import library mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_spi.c@579:53297373a894, 2015-07-01 (annotated)

Committer:: mbed_official
Date:: Wed Jul 01 09:45:11 2015 +0100
Revision:: 579:53297373a894
Parent:: 489:119543c9f674

Synchronized with git revision d5b4d2ab9c47edb4dc5776e7177b0c2263459081

Full URL: https://github.com/mbedmicro/mbed/commit/d5b4d2ab9c47edb4dc5776e7177b0c2263459081/

Initial version of drivers for SAMR21

Who changed what in which revision?

User	Revision	Line number	New contents of line
mbed_official	376:cb4d9db17537	1	/**
mbed_official	376:cb4d9db17537	2	******************************************************************************
mbed_official	376:cb4d9db17537	3	* @file stm32l0xx_hal_spi.c
mbed_official	376:cb4d9db17537	4	* @author MCD Application Team
mbed_official	489:119543c9f674	5	* @version V1.2.0
mbed_official	489:119543c9f674	6	* @date 06-February-2015
mbed_official	376:cb4d9db17537	7	* @brief SPI HAL module driver.
mbed_official	489:119543c9f674	8	*
mbed_official	376:cb4d9db17537	9	* This file provides firmware functions to manage the following
mbed_official	376:cb4d9db17537	10	* functionalities of the Serial Peripheral Interface (SPI) peripheral:
mbed_official	376:cb4d9db17537	11	* + Initialization and de-initialization functions
mbed_official	376:cb4d9db17537	12	* + IO operation functions
mbed_official	376:cb4d9db17537	13	* + Peripheral Control functions
mbed_official	376:cb4d9db17537	14	* + Peripheral State functions
mbed_official	376:cb4d9db17537	15	@verbatim
mbed_official	376:cb4d9db17537	16	==============================================================================
mbed_official	376:cb4d9db17537	17	##### How to use this driver #####
mbed_official	376:cb4d9db17537	18	==============================================================================
mbed_official	376:cb4d9db17537	19	[..]
mbed_official	376:cb4d9db17537	20	The SPI HAL driver can be used as follows:
mbed_official	376:cb4d9db17537	21
mbed_official	376:cb4d9db17537	22	(#) Declare a SPI_HandleTypeDef handle structure, for example:
mbed_official	376:cb4d9db17537	23	SPI_HandleTypeDef hspi;
mbed_official	376:cb4d9db17537	24
mbed_official	489:119543c9f674	25	(#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit ()API:
mbed_official	376:cb4d9db17537	26	(##) Enable the SPIx interface clock
mbed_official	376:cb4d9db17537	27	(##) SPI pins configuration
mbed_official	376:cb4d9db17537	28	(+++) Enable the clock for the SPI GPIOs
mbed_official	376:cb4d9db17537	29	(+++) Configure these SPI pins as alternate function push-pull
mbed_official	376:cb4d9db17537	30	(##) NVIC configuration if you need to use interrupt process
mbed_official	376:cb4d9db17537	31	(+++) Configure the SPIx interrupt priority
mbed_official	376:cb4d9db17537	32	(+++) Enable the NVIC SPI IRQ handle
mbed_official	376:cb4d9db17537	33	(##) DMA Configuration if you need to use DMA process
mbed_official	489:119543c9f674	34	(+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive Channel
mbed_official	489:119543c9f674	35	(+++) Enable the DMAx clock
mbed_official	376:cb4d9db17537	36	(+++) Configure the DMA handle parameters
mbed_official	489:119543c9f674	37	(+++) Configure the DMA Tx or Rx Channel
mbed_official	489:119543c9f674	38	(+++) Associate the initilalized hdma_tx(or _rx) handle to the hspi DMA Tx (or Rx) handle
mbed_official	489:119543c9f674	39	(+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Channel
mbed_official	376:cb4d9db17537	40
mbed_official	376:cb4d9db17537	41	(#) Program the Mode, Direction , Data size, Baudrate Prescaler, NSS
mbed_official	376:cb4d9db17537	42	management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.
mbed_official	376:cb4d9db17537	43
mbed_official	376:cb4d9db17537	44	(#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
mbed_official	376:cb4d9db17537	45	(++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
mbed_official	489:119543c9f674	46	by calling the customed HAL_SPI_MspInit() API.
mbed_official	489:119543c9f674	47	[..]
mbed_official	376:cb4d9db17537	48	Circular mode restriction:
mbed_official	376:cb4d9db17537	49	(#) The DMA circular mode cannot be used when the SPI is configured in these modes:
mbed_official	376:cb4d9db17537	50	(##) Master 2Lines RxOnly
mbed_official	376:cb4d9db17537	51	(##) Master 1Line Rx
mbed_official	376:cb4d9db17537	52	(#) The CRC feature is not managed when the DMA circular mode is enabled
mbed_official	376:cb4d9db17537	53	(#) When the SPI DMA Pause/Stop features are used, we must use the following APIs
mbed_official	376:cb4d9db17537	54	the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks
mbed_official	376:cb4d9db17537	55
mbed_official	376:cb4d9db17537	56	[..]
mbed_official	376:cb4d9db17537	57	Using the HAL it is not possible to reach all supported SPI frequency with the differents SPI Modes,
mbed_official	489:119543c9f674	58	the following table resume the max SPI frequency reached with data size 8bits/16bits,
mbed_official	489:119543c9f674	59	according to frequency used on APBx Peripheral Clock (fPCLK) used by the SPI instance :
mbed_official	489:119543c9f674	60
mbed_official	489:119543c9f674	61	DataSize = SPI_DATASIZE_8BIT:
mbed_official	489:119543c9f674	62	+----------------------------------------------------------------------------------------------+
mbed_official	489:119543c9f674	63	\| \| \| 2Lines Fullduplex \| 2Lines RxOnly \| 1Line \|
mbed_official	489:119543c9f674	64	\| Process \| Tranfert mode \|---------------------\|----------------------\|----------------------\|
mbed_official	489:119543c9f674	65	\| \| \| Master \| Slave \| Master \| Slave \| Master \| Slave \|
mbed_official	489:119543c9f674	66	\|==============================================================================================\|
mbed_official	489:119543c9f674	67	\| T \| Polling \| Fpclk/4 \| Fpclk/8 \| NA \| NA \| NA \| NA \|
mbed_official	489:119543c9f674	68	\| X \|----------------\|----------\|----------\|-----------\|----------\|-----------\|----------\|
mbed_official	489:119543c9f674	69	\| / \| Interrupt \| Fpclk/64 \| Fpclk/64 \| NA \| NA \| NA \| NA \|
mbed_official	489:119543c9f674	70	\| R \|----------------\|----------\|----------\|-----------\|----------\|-----------\|----------\|
mbed_official	489:119543c9f674	71	\| X \| DMA \| Fpclk/2 \| Fpclk/4 \| NA \| NA \| NA \| NA \|
mbed_official	489:119543c9f674	72	\|=========\|================\|==========\|==========\|===========\|==========\|===========\|==========\|
mbed_official	489:119543c9f674	73	\| \| Polling \| Fpclk/2 \| Fpclk/8 \| Fpclk/8 \| Fpclk/8 \| Fpclk/8 \| Fpclk/8 \|
mbed_official	489:119543c9f674	74	\| \|----------------\|----------\|----------\|-----------\|----------\|-----------\|----------\|
mbed_official	489:119543c9f674	75	\| R \| Interrupt \| Fpclk/64 \| Fpclk/32 \| Fpclk/32 \| Fpclk/16 \| Fpclk/32 \| Fpclk/32 \|
mbed_official	489:119543c9f674	76	\| X \|----------------\|----------\|----------\|-----------\|----------\|-----------\|----------\|
mbed_official	489:119543c9f674	77	\| \| DMA \| Fpclk/2 \| Fpclk/2 \| Fpclk/16 \| Fpclk/2 \| Fpclk/16 \| Fpclk/2 \|
mbed_official	489:119543c9f674	78	\|=========\|================\|==========\|==========\|===========\|==========\|===========\|==========\|
mbed_official	489:119543c9f674	79	\| \| Polling \| Fpclk/8 \| Fpclk/8 \| NA \| NA \| Fpclk/4 \| Fpclk/16 \|
mbed_official	489:119543c9f674	80	\| \|----------------\|----------\|----------\|-----------\|----------\|-----------\|----------\|
mbed_official	489:119543c9f674	81	\| T \| Interrupt \| Fpclk/8 \| Fpclk/32 \| NA \| NA \| Fpclk/8 \| Fpclk/16 \|
mbed_official	489:119543c9f674	82	\| X \|----------------\|----------\|----------\|-----------\|----------\|-----------\|----------\|
mbed_official	489:119543c9f674	83	\| \| DMA \| Fpclk/2 \| Fpclk/4 \| NA \| NA \| Fpclk/2 \| Fpclk/2 \|
mbed_official	489:119543c9f674	84	+----------------------------------------------------------------------------------------------+
mbed_official	489:119543c9f674	85
mbed_official	489:119543c9f674	86	DataSize = SPI_DATASIZE_16BIT:
mbed_official	489:119543c9f674	87	+----------------------------------------------------------------------------------------------+
mbed_official	489:119543c9f674	88	\| \| \| 2Lines Fullduplex \| 2Lines RxOnly \| 1Line \|
mbed_official	489:119543c9f674	89	\| Process \| Tranfert mode \|---------------------\|----------------------\|----------------------\|
mbed_official	489:119543c9f674	90	\| \| \| Master \| Slave \| Master \| Slave \| Master \| Slave \|
mbed_official	489:119543c9f674	91	\|==============================================================================================\|
mbed_official	489:119543c9f674	92	\| T \| Polling \| Fpclk/4 \| Fpclk/8 \| NA \| NA \| NA \| NA \|
mbed_official	489:119543c9f674	93	\| X \|----------------\|----------\|----------\|-----------\|----------\|-----------\|----------\|
mbed_official	489:119543c9f674	94	\| / \| Interrupt \| Fpclk/32 \| Fpclk/16 \| NA \| NA \| NA \| NA \|
mbed_official	489:119543c9f674	95	\| R \|----------------\|----------\|----------\|-----------\|----------\|-----------\|----------\|
mbed_official	489:119543c9f674	96	\| X \| DMA \| Fpclk/2 \| Fpclk/4 \| NA \| NA \| NA \| NA \|
mbed_official	489:119543c9f674	97	\|=========\|================\|==========\|==========\|===========\|==========\|===========\|==========\|
mbed_official	489:119543c9f674	98	\| \| Polling \| Fpclk/2 \| Fpclk/4 \| Fpclk/8 \| Fpclk/4 \| Fpclk/2 \| Fpclk/8 \|
mbed_official	489:119543c9f674	99	\| \|----------------\|----------\|----------\|-----------\|----------\|-----------\|----------\|
mbed_official	489:119543c9f674	100	\| R \| Interrupt \| Fpclk/32 \| Fpclk/8 \| Fpclk/16 \| Fpclk/16 \| Fpclk/16 \| Fpclk/8 \|
mbed_official	489:119543c9f674	101	\| X \|----------------\|----------\|----------\|-----------\|----------\|-----------\|----------\|
mbed_official	489:119543c9f674	102	\| \| DMA \| Fpclk/2 \| Fpclk/2 \| Fpclk/8 \| Fpclk/2 \| Fpclk/8 \| Fpclk/2 \|
mbed_official	489:119543c9f674	103	\|=========\|================\|==========\|==========\|===========\|==========\|===========\|==========\|
mbed_official	489:119543c9f674	104	\| \| Polling \| Fpclk/4 \| Fpclk/4 \| NA \| NA \| Fpclk/4 \| Fpclk/8 \|
mbed_official	489:119543c9f674	105	\| \|----------------\|----------\|----------\|-----------\|----------\|-----------\|----------\|
mbed_official	489:119543c9f674	106	\| T \| Interrupt \| Fpclk/4 \| Fpclk/16 \| NA \| NA \| Fpclk/8 \| Fpclk/8 \|
mbed_official	489:119543c9f674	107	\| X \|----------------\|----------\|----------\|-----------\|----------\|-----------\|----------\|
mbed_official	489:119543c9f674	108	\| \| DMA \| Fpclk/2 \| Fpclk/4 \| NA \| NA \| Fpclk/2 \| Fpclk/2 \|
mbed_official	489:119543c9f674	109	+----------------------------------------------------------------------------------------------+
mbed_official	489:119543c9f674	110	@note The max SPI frequency depend on SPI data size (8bits, 16bits),
mbed_official	376:cb4d9db17537	111	SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA).
mbed_official	376:cb4d9db17537	112	@note
mbed_official	376:cb4d9db17537	113	(#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA()
mbed_official	376:cb4d9db17537	114	(#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA()
mbed_official	376:cb4d9db17537	115	(#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA()
mbed_official	376:cb4d9db17537	116
mbed_official	376:cb4d9db17537	117	@endverbatim
mbed_official	376:cb4d9db17537	118	******************************************************************************
mbed_official	376:cb4d9db17537	119	* @attention
mbed_official	376:cb4d9db17537	120	*
mbed_official	489:119543c9f674	121	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
mbed_official	376:cb4d9db17537	122	*
mbed_official	376:cb4d9db17537	123	* Redistribution and use in source and binary forms, with or without modification,
mbed_official	376:cb4d9db17537	124	* are permitted provided that the following conditions are met:
mbed_official	376:cb4d9db17537	125	* 1. Redistributions of source code must retain the above copyright notice,
mbed_official	376:cb4d9db17537	126	* this list of conditions and the following disclaimer.
mbed_official	376:cb4d9db17537	127	* 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official	376:cb4d9db17537	128	* this list of conditions and the following disclaimer in the documentation
mbed_official	376:cb4d9db17537	129	* and/or other materials provided with the distribution.
mbed_official	376:cb4d9db17537	130	* 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official	376:cb4d9db17537	131	* may be used to endorse or promote products derived from this software
mbed_official	376:cb4d9db17537	132	* without specific prior written permission.
mbed_official	376:cb4d9db17537	133	*
mbed_official	376:cb4d9db17537	134	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official	376:cb4d9db17537	135	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official	376:cb4d9db17537	136	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official	376:cb4d9db17537	137	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official	376:cb4d9db17537	138	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official	376:cb4d9db17537	139	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official	376:cb4d9db17537	140	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official	376:cb4d9db17537	141	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official	376:cb4d9db17537	142	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official	376:cb4d9db17537	143	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official	376:cb4d9db17537	144	*
mbed_official	376:cb4d9db17537	145	******************************************************************************
mbed_official	376:cb4d9db17537	146	*/
mbed_official	376:cb4d9db17537	147
mbed_official	376:cb4d9db17537	148	/* Includes ------------------------------------------------------------------*/
mbed_official	376:cb4d9db17537	149	#include "stm32l0xx_hal.h"
mbed_official	376:cb4d9db17537	150
mbed_official	376:cb4d9db17537	151	/** @addtogroup STM32L0xx_HAL_Driver
mbed_official	376:cb4d9db17537	152	* @{
mbed_official	376:cb4d9db17537	153	*/
mbed_official	376:cb4d9db17537	154
mbed_official	489:119543c9f674	155	/** @defgroup SPI SPI
mbed_official	376:cb4d9db17537	156	* @brief SPI HAL module driver
mbed_official	376:cb4d9db17537	157	* @{
mbed_official	376:cb4d9db17537	158	*/
mbed_official	376:cb4d9db17537	159
mbed_official	376:cb4d9db17537	160	#ifdef HAL_SPI_MODULE_ENABLED
mbed_official	376:cb4d9db17537	161
mbed_official	376:cb4d9db17537	162	/* Private typedef -----------------------------------------------------------*/
mbed_official	376:cb4d9db17537	163	/* Private define ------------------------------------------------------------*/
mbed_official	489:119543c9f674	164	/** @defgroup SPI_Private_Constants SPI Private Constants
mbed_official	489:119543c9f674	165	* @{
mbed_official	489:119543c9f674	166	*/
mbed_official	489:119543c9f674	167	#define SPI_TIMEOUT_VALUE 10
mbed_official	489:119543c9f674	168	/**
mbed_official	489:119543c9f674	169	* @}
mbed_official	489:119543c9f674	170	*/
mbed_official	489:119543c9f674	171
mbed_official	376:cb4d9db17537	172	/* Private macro -------------------------------------------------------------*/
mbed_official	376:cb4d9db17537	173	/* Private variables ---------------------------------------------------------*/
mbed_official	376:cb4d9db17537	174	/* Private function prototypes -----------------------------------------------*/
mbed_official	489:119543c9f674	175	/** @defgroup SPI_Private_Functions SPI Private Functions
mbed_official	489:119543c9f674	176	* @{
mbed_official	489:119543c9f674	177	*/
mbed_official	376:cb4d9db17537	178	static void SPI_TxCloseIRQHandler(SPI_HandleTypeDef *hspi);
mbed_official	376:cb4d9db17537	179	static void SPI_TxISR(SPI_HandleTypeDef *hspi);
mbed_official	376:cb4d9db17537	180	static void SPI_RxCloseIRQHandler(SPI_HandleTypeDef *hspi);
mbed_official	376:cb4d9db17537	181	static void SPI_2LinesRxISR(SPI_HandleTypeDef *hspi);
mbed_official	376:cb4d9db17537	182	static void SPI_RxISR(SPI_HandleTypeDef *hspi);
mbed_official	376:cb4d9db17537	183	static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
mbed_official	376:cb4d9db17537	184	static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
mbed_official	376:cb4d9db17537	185	static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);
mbed_official	376:cb4d9db17537	186	static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma);
mbed_official	376:cb4d9db17537	187	static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma);
mbed_official	376:cb4d9db17537	188	static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma);
mbed_official	376:cb4d9db17537	189	static void SPI_DMAError(DMA_HandleTypeDef *hdma);
mbed_official	376:cb4d9db17537	190	static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
mbed_official	489:119543c9f674	191	/**
mbed_official	489:119543c9f674	192	* @}
mbed_official	489:119543c9f674	193	*/
mbed_official	376:cb4d9db17537	194
mbed_official	489:119543c9f674	195	/* Exported functions ---------------------------------------------------------*/
mbed_official	376:cb4d9db17537	196
mbed_official	489:119543c9f674	197	/** @defgroup SPI_Exported_Functions SPI Exported Functions
mbed_official	376:cb4d9db17537	198	* @{
mbed_official	376:cb4d9db17537	199	*/
mbed_official	376:cb4d9db17537	200
mbed_official	489:119543c9f674	201	/** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
mbed_official	376:cb4d9db17537	202	* @brief Initialization and Configuration functions
mbed_official	376:cb4d9db17537	203	*
mbed_official	376:cb4d9db17537	204	@verbatim
mbed_official	376:cb4d9db17537	205	===============================================================================
mbed_official	376:cb4d9db17537	206	##### Initialization and de-initialization functions #####
mbed_official	376:cb4d9db17537	207	===============================================================================
mbed_official	376:cb4d9db17537	208	[..] This subsection provides a set of functions allowing to initialize and
mbed_official	376:cb4d9db17537	209	de-initialiaze the SPIx peripheral:
mbed_official	376:cb4d9db17537	210
mbed_official	489:119543c9f674	211	(+) User must implement HAL_SPI_MspInit() function in which he configures
mbed_official	376:cb4d9db17537	212	all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
mbed_official	376:cb4d9db17537	213
mbed_official	376:cb4d9db17537	214	(+) Call the function HAL_SPI_Init() to configure the selected device with
mbed_official	376:cb4d9db17537	215	the selected configuration:
mbed_official	376:cb4d9db17537	216	(++) Mode
mbed_official	376:cb4d9db17537	217	(++) Direction
mbed_official	376:cb4d9db17537	218	(++) Data Size
mbed_official	376:cb4d9db17537	219	(++) Clock Polarity and Phase
mbed_official	376:cb4d9db17537	220	(++) NSS Management
mbed_official	376:cb4d9db17537	221	(++) BaudRate Prescaler
mbed_official	376:cb4d9db17537	222	(++) FirstBit
mbed_official	376:cb4d9db17537	223	(++) TIMode
mbed_official	376:cb4d9db17537	224	(++) CRC Calculation
mbed_official	376:cb4d9db17537	225	(++) CRC Polynomial if CRC enabled
mbed_official	376:cb4d9db17537	226
mbed_official	376:cb4d9db17537	227	(+) Call the function HAL_SPI_DeInit() to restore the default configuration
mbed_official	376:cb4d9db17537	228	of the selected SPIx periperal.
mbed_official	376:cb4d9db17537	229
mbed_official	376:cb4d9db17537	230	@endverbatim
mbed_official	376:cb4d9db17537	231	* @{
mbed_official	376:cb4d9db17537	232	*/
mbed_official	376:cb4d9db17537	233
mbed_official	376:cb4d9db17537	234	/**
mbed_official	376:cb4d9db17537	235	* @brief Initializes the SPI according to the specified parameters
mbed_official	376:cb4d9db17537	236	* in the SPI_InitTypeDef and create the associated handle.
mbed_official	376:cb4d9db17537	237	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	376:cb4d9db17537	238	* the configuration information for SPI module.
mbed_official	376:cb4d9db17537	239	* @retval HAL status
mbed_official	376:cb4d9db17537	240	*/
mbed_official	376:cb4d9db17537	241	HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
mbed_official	376:cb4d9db17537	242	{
mbed_official	376:cb4d9db17537	243	/* Check the SPI handle allocation */
mbed_official	489:119543c9f674	244	if(hspi == NULL)
mbed_official	376:cb4d9db17537	245	{
mbed_official	376:cb4d9db17537	246	return HAL_ERROR;
mbed_official	376:cb4d9db17537	247	}
mbed_official	376:cb4d9db17537	248
mbed_official	376:cb4d9db17537	249	/* Check the parameters */
mbed_official	489:119543c9f674	250	assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
mbed_official	376:cb4d9db17537	251	assert_param(IS_SPI_MODE(hspi->Init.Mode));
mbed_official	376:cb4d9db17537	252	assert_param(IS_SPI_DIRECTION_MODE(hspi->Init.Direction));
mbed_official	376:cb4d9db17537	253	assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
mbed_official	376:cb4d9db17537	254	assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
mbed_official	376:cb4d9db17537	255	assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
mbed_official	376:cb4d9db17537	256	assert_param(IS_SPI_NSS(hspi->Init.NSS));
mbed_official	376:cb4d9db17537	257	assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
mbed_official	376:cb4d9db17537	258	assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
mbed_official	376:cb4d9db17537	259	assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
mbed_official	376:cb4d9db17537	260	assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
mbed_official	376:cb4d9db17537	261	assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
mbed_official	376:cb4d9db17537	262
mbed_official	376:cb4d9db17537	263	if(hspi->State == HAL_SPI_STATE_RESET)
mbed_official	376:cb4d9db17537	264	{
mbed_official	376:cb4d9db17537	265	/* Init the low level hardware : GPIO, CLOCK, NVIC... */
mbed_official	376:cb4d9db17537	266	HAL_SPI_MspInit(hspi);
mbed_official	376:cb4d9db17537	267	}
mbed_official	376:cb4d9db17537	268
mbed_official	376:cb4d9db17537	269	hspi->State = HAL_SPI_STATE_BUSY;
mbed_official	376:cb4d9db17537	270
mbed_official	376:cb4d9db17537	271	/* Disble the selected SPI peripheral */
mbed_official	376:cb4d9db17537	272	__HAL_SPI_DISABLE(hspi);
mbed_official	376:cb4d9db17537	273
mbed_official	376:cb4d9db17537	274	/----------------------- SPIx CR1 & CR2 Configuration ---------------------/
mbed_official	376:cb4d9db17537	275	/* Configure : SPI Mode, Communication Mode, Data size, Clock polarity and phase, NSS management,
mbed_official	376:cb4d9db17537	276	Communication speed, First bit and CRC calculation state */
mbed_official	489:119543c9f674	277	WRITE_REG(hspi->Instance->CR1, (hspi->Init.Mode \| hspi->Init.Direction \| hspi->Init.DataSize \|
mbed_official	489:119543c9f674	278	hspi->Init.CLKPolarity \| hspi->Init.CLKPhase \| (hspi->Init.NSS & SPI_CR1_SSM) \|
mbed_official	489:119543c9f674	279	hspi->Init.BaudRatePrescaler \| hspi->Init.FirstBit \| hspi->Init.CRCCalculation) );
mbed_official	376:cb4d9db17537	280
mbed_official	376:cb4d9db17537	281	/* Configure : NSS management */
mbed_official	489:119543c9f674	282	WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16) & SPI_CR2_SSOE) \| hspi->Init.TIMode));
mbed_official	376:cb4d9db17537	283
mbed_official	376:cb4d9db17537	284	/---------------------------- SPIx CRCPOLY Configuration ------------------/
mbed_official	376:cb4d9db17537	285	/* Configure : CRC Polynomial */
mbed_official	489:119543c9f674	286	WRITE_REG(hspi->Instance->CRCPR, hspi->Init.CRCPolynomial);
mbed_official	489:119543c9f674	287
mbed_official	376:cb4d9db17537	288	/* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
mbed_official	489:119543c9f674	289	CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
mbed_official	376:cb4d9db17537	290
mbed_official	376:cb4d9db17537	291	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official	376:cb4d9db17537	292	hspi->State = HAL_SPI_STATE_READY;
mbed_official	376:cb4d9db17537	293
mbed_official	376:cb4d9db17537	294	return HAL_OK;
mbed_official	376:cb4d9db17537	295	}
mbed_official	376:cb4d9db17537	296
mbed_official	376:cb4d9db17537	297	/**
mbed_official	376:cb4d9db17537	298	* @brief DeInitializes the SPI peripheral
mbed_official	376:cb4d9db17537	299	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	376:cb4d9db17537	300	* the configuration information for SPI module.
mbed_official	376:cb4d9db17537	301	* @retval HAL status
mbed_official	376:cb4d9db17537	302	*/
mbed_official	376:cb4d9db17537	303	HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
mbed_official	376:cb4d9db17537	304	{
mbed_official	376:cb4d9db17537	305	/* Check the SPI handle allocation */
mbed_official	489:119543c9f674	306	if(hspi == NULL)
mbed_official	376:cb4d9db17537	307	{
mbed_official	376:cb4d9db17537	308	return HAL_ERROR;
mbed_official	376:cb4d9db17537	309	}
mbed_official	376:cb4d9db17537	310
mbed_official	376:cb4d9db17537	311	hspi->State = HAL_SPI_STATE_BUSY;
mbed_official	376:cb4d9db17537	312
mbed_official	376:cb4d9db17537	313	/* Disable the SPI Peripheral Clock */
mbed_official	376:cb4d9db17537	314	__HAL_SPI_DISABLE(hspi);
mbed_official	376:cb4d9db17537	315
mbed_official	376:cb4d9db17537	316	/* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
mbed_official	376:cb4d9db17537	317	HAL_SPI_MspDeInit(hspi);
mbed_official	376:cb4d9db17537	318
mbed_official	376:cb4d9db17537	319	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official	376:cb4d9db17537	320	hspi->State = HAL_SPI_STATE_RESET;
mbed_official	376:cb4d9db17537	321
mbed_official	376:cb4d9db17537	322	/* Release Lock */
mbed_official	376:cb4d9db17537	323	__HAL_UNLOCK(hspi);
mbed_official	376:cb4d9db17537	324
mbed_official	376:cb4d9db17537	325	return HAL_OK;
mbed_official	376:cb4d9db17537	326	}
mbed_official	376:cb4d9db17537	327
mbed_official	376:cb4d9db17537	328	/**
mbed_official	376:cb4d9db17537	329	* @brief SPI MSP Init
mbed_official	376:cb4d9db17537	330	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	489:119543c9f674	331	* the configuration information for SPI module.
mbed_official	376:cb4d9db17537	332	* @retval None
mbed_official	376:cb4d9db17537	333	*/
mbed_official	376:cb4d9db17537	334	__weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
mbed_official	376:cb4d9db17537	335	{
mbed_official	376:cb4d9db17537	336	/* NOTE : This function Should not be modified, when the callback is needed,
mbed_official	489:119543c9f674	337	the HAL_SPI_MspInit could be implenetd in the user file
mbed_official	376:cb4d9db17537	338	*/
mbed_official	376:cb4d9db17537	339	}
mbed_official	376:cb4d9db17537	340
mbed_official	376:cb4d9db17537	341	/**
mbed_official	376:cb4d9db17537	342	* @brief SPI MSP DeInit
mbed_official	376:cb4d9db17537	343	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	489:119543c9f674	344	* the configuration information for SPI module.
mbed_official	376:cb4d9db17537	345	* @retval None
mbed_official	376:cb4d9db17537	346	*/
mbed_official	376:cb4d9db17537	347	__weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
mbed_official	376:cb4d9db17537	348	{
mbed_official	376:cb4d9db17537	349	/* NOTE : This function Should not be modified, when the callback is needed,
mbed_official	376:cb4d9db17537	350	the HAL_SPI_MspDeInit could be implenetd in the user file
mbed_official	376:cb4d9db17537	351	*/
mbed_official	376:cb4d9db17537	352	}
mbed_official	376:cb4d9db17537	353
mbed_official	376:cb4d9db17537	354	/**
mbed_official	376:cb4d9db17537	355	* @}
mbed_official	376:cb4d9db17537	356	*/
mbed_official	376:cb4d9db17537	357
mbed_official	489:119543c9f674	358	/** @defgroup SPI_Exported_Functions_Group2 IO operation functions
mbed_official	376:cb4d9db17537	359	* @brief Data transfers functions
mbed_official	376:cb4d9db17537	360	*
mbed_official	376:cb4d9db17537	361	@verbatim
mbed_official	376:cb4d9db17537	362	==============================================================================
mbed_official	376:cb4d9db17537	363	##### IO operation functions #####
mbed_official	376:cb4d9db17537	364	===============================================================================
mbed_official	376:cb4d9db17537	365	This subsection provides a set of functions allowing to manage the SPI
mbed_official	376:cb4d9db17537	366	data transfers.
mbed_official	376:cb4d9db17537	367
mbed_official	376:cb4d9db17537	368	[..] The SPI supports master and slave mode :
mbed_official	376:cb4d9db17537	369
mbed_official	489:119543c9f674	370	(#) There are two modes of transfer:
mbed_official	376:cb4d9db17537	371	(++) Blocking mode: The communication is performed in polling mode.
mbed_official	376:cb4d9db17537	372	The HAL status of all data processing is returned by the same function
mbed_official	376:cb4d9db17537	373	after finishing transfer.
mbed_official	376:cb4d9db17537	374	(++) No-Blocking mode: The communication is performed using Interrupts
mbed_official	489:119543c9f674	375	or DMA, These APIs return the HAL status.
mbed_official	376:cb4d9db17537	376	The end of the data processing will be indicated through the
mbed_official	376:cb4d9db17537	377	dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
mbed_official	376:cb4d9db17537	378	using DMA mode.
mbed_official	376:cb4d9db17537	379	The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
mbed_official	376:cb4d9db17537	380	will be executed respectivelly at the end of the transmit or Receive process
mbed_official	376:cb4d9db17537	381	The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected
mbed_official	376:cb4d9db17537	382
mbed_official	489:119543c9f674	383	(#) Blocking mode APIs are :
mbed_official	376:cb4d9db17537	384	(++) HAL_SPI_Transmit()in 1Line (simplex) and 2Lines (full duplex) mode
mbed_official	376:cb4d9db17537	385	(++) HAL_SPI_Receive() in 1Line (simplex) and 2Lines (full duplex) mode
mbed_official	376:cb4d9db17537	386	(++) HAL_SPI_TransmitReceive() in full duplex mode
mbed_official	376:cb4d9db17537	387
mbed_official	489:119543c9f674	388	(#) Non Blocking mode API's with Interrupt are :
mbed_official	376:cb4d9db17537	389	(++) HAL_SPI_Transmit_IT()in 1Line (simplex) and 2Lines (full duplex) mode
mbed_official	376:cb4d9db17537	390	(++) HAL_SPI_Receive_IT() in 1Line (simplex) and 2Lines (full duplex) mode
mbed_official	376:cb4d9db17537	391	(++) HAL_SPI_TransmitReceive_IT()in full duplex mode
mbed_official	376:cb4d9db17537	392	(++) HAL_SPI_IRQHandler()
mbed_official	376:cb4d9db17537	393
mbed_official	489:119543c9f674	394	(#) Non Blocking mode functions with DMA are :
mbed_official	376:cb4d9db17537	395	(++) HAL_SPI_Transmit_DMA()in 1Line (simplex) and 2Lines (full duplex) mode
mbed_official	376:cb4d9db17537	396	(++) HAL_SPI_Receive_DMA() in 1Line (simplex) and 2Lines (full duplex) mode
mbed_official	489:119543c9f674	397	(++) HAL_SPI_TransmitReceive_DMA() in full duplex mode
mbed_official	376:cb4d9db17537	398
mbed_official	489:119543c9f674	399	(#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
mbed_official	376:cb4d9db17537	400	(++) HAL_SPI_TxCpltCallback()
mbed_official	376:cb4d9db17537	401	(++) HAL_SPI_RxCpltCallback()
mbed_official	489:119543c9f674	402	(++) HAL_SPI_TxRxCpltCallback()
mbed_official	489:119543c9f674	403	(++) HAL_SPI_TxHalfCpltCallback()
mbed_official	489:119543c9f674	404	(++) HAL_SPI_RxHalfCpltCallback()
mbed_official	489:119543c9f674	405	(++) HAL_SPI_TxRxHalfCpltCallback()
mbed_official	376:cb4d9db17537	406	(++) HAL_SPI_ErrorCallback()
mbed_official	376:cb4d9db17537	407
mbed_official	376:cb4d9db17537	408	@endverbatim
mbed_official	376:cb4d9db17537	409	* @{
mbed_official	376:cb4d9db17537	410	*/
mbed_official	376:cb4d9db17537	411
mbed_official	376:cb4d9db17537	412	/**
mbed_official	376:cb4d9db17537	413	* @brief Transmit an amount of data in blocking mode
mbed_official	376:cb4d9db17537	414	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	376:cb4d9db17537	415	* the configuration information for SPI module.
mbed_official	376:cb4d9db17537	416	* @param pData: pointer to data buffer
mbed_official	376:cb4d9db17537	417	* @param Size: amount of data to be sent
mbed_official	376:cb4d9db17537	418	* @param Timeout: Timeout duration
mbed_official	376:cb4d9db17537	419	* @retval HAL status
mbed_official	376:cb4d9db17537	420	*/
mbed_official	376:cb4d9db17537	421	HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size, uint32_t Timeout)
mbed_official	376:cb4d9db17537	422	{
mbed_official	376:cb4d9db17537	423
mbed_official	376:cb4d9db17537	424	if(hspi->State == HAL_SPI_STATE_READY)
mbed_official	376:cb4d9db17537	425	{
mbed_official	489:119543c9f674	426	if((pData == NULL ) \|\| (Size == 0))
mbed_official	376:cb4d9db17537	427	{
mbed_official	376:cb4d9db17537	428	return HAL_ERROR;
mbed_official	376:cb4d9db17537	429	}
mbed_official	376:cb4d9db17537	430
mbed_official	376:cb4d9db17537	431	/* Check the parameters */
mbed_official	376:cb4d9db17537	432	assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
mbed_official	376:cb4d9db17537	433
mbed_official	376:cb4d9db17537	434	/* Process Locked */
mbed_official	376:cb4d9db17537	435	__HAL_LOCK(hspi);
mbed_official	376:cb4d9db17537	436
mbed_official	376:cb4d9db17537	437	/* Configure communication */
mbed_official	376:cb4d9db17537	438	hspi->State = HAL_SPI_STATE_BUSY_TX;
mbed_official	376:cb4d9db17537	439	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official	376:cb4d9db17537	440
mbed_official	489:119543c9f674	441	hspi->pTxBuffPtr = pData;
mbed_official	489:119543c9f674	442	hspi->TxXferSize = Size;
mbed_official	376:cb4d9db17537	443	hspi->TxXferCount = Size;
mbed_official	376:cb4d9db17537	444
mbed_official	376:cb4d9db17537	445	/Init field not used in handle to zero /
mbed_official	376:cb4d9db17537	446	hspi->TxISR = 0;
mbed_official	376:cb4d9db17537	447	hspi->RxISR = 0;
mbed_official	489:119543c9f674	448	hspi->pRxBuffPtr = NULL;
mbed_official	489:119543c9f674	449	hspi->RxXferSize = 0;
mbed_official	489:119543c9f674	450	hspi->RxXferCount = 0;
mbed_official	376:cb4d9db17537	451
mbed_official	376:cb4d9db17537	452	/* Reset CRC Calculation */
mbed_official	489:119543c9f674	453	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official	376:cb4d9db17537	454	{
mbed_official	489:119543c9f674	455	SPI_RESET_CRC(hspi);
mbed_official	376:cb4d9db17537	456	}
mbed_official	376:cb4d9db17537	457
mbed_official	376:cb4d9db17537	458	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
mbed_official	376:cb4d9db17537	459	{
mbed_official	376:cb4d9db17537	460	/* Configure communication direction : 1Line */
mbed_official	489:119543c9f674	461	SPI_1LINE_TX(hspi);
mbed_official	376:cb4d9db17537	462	}
mbed_official	376:cb4d9db17537	463
mbed_official	376:cb4d9db17537	464	/* Check if the SPI is already enabled */
mbed_official	376:cb4d9db17537	465	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official	376:cb4d9db17537	466	{
mbed_official	376:cb4d9db17537	467	/* Enable SPI peripheral */
mbed_official	376:cb4d9db17537	468	__HAL_SPI_ENABLE(hspi);
mbed_official	376:cb4d9db17537	469	}
mbed_official	376:cb4d9db17537	470
mbed_official	376:cb4d9db17537	471	/* Transmit data in 8 Bit mode */
mbed_official	376:cb4d9db17537	472	if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
mbed_official	376:cb4d9db17537	473	{
mbed_official	376:cb4d9db17537	474	if((hspi->Init.Mode == SPI_MODE_SLAVE)\|\| (hspi->TxXferCount == 0x01))
mbed_official	376:cb4d9db17537	475	{
mbed_official	376:cb4d9db17537	476	hspi->Instance->DR = (*hspi->pTxBuffPtr++);
mbed_official	376:cb4d9db17537	477	hspi->TxXferCount--;
mbed_official	376:cb4d9db17537	478	}
mbed_official	376:cb4d9db17537	479
mbed_official	376:cb4d9db17537	480	while(hspi->TxXferCount > 0)
mbed_official	376:cb4d9db17537	481	{
mbed_official	376:cb4d9db17537	482	/* Wait until TXE flag is set to send data */
mbed_official	376:cb4d9db17537	483	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
mbed_official	376:cb4d9db17537	484	{
mbed_official	376:cb4d9db17537	485	return HAL_TIMEOUT;
mbed_official	376:cb4d9db17537	486	}
mbed_official	376:cb4d9db17537	487	hspi->Instance->DR = (*hspi->pTxBuffPtr++);
mbed_official	376:cb4d9db17537	488	hspi->TxXferCount--;
mbed_official	376:cb4d9db17537	489	}
mbed_official	376:cb4d9db17537	490	/* Enable CRC Transmission */
mbed_official	489:119543c9f674	491	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official	376:cb4d9db17537	492	{
mbed_official	489:119543c9f674	493	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
mbed_official	376:cb4d9db17537	494	}
mbed_official	376:cb4d9db17537	495	}
mbed_official	376:cb4d9db17537	496	/* Transmit data in 16 Bit mode */
mbed_official	376:cb4d9db17537	497	else
mbed_official	376:cb4d9db17537	498	{
mbed_official	376:cb4d9db17537	499	if((hspi->Init.Mode == SPI_MODE_SLAVE) \|\| (hspi->TxXferCount == 0x01))
mbed_official	376:cb4d9db17537	500	{
mbed_official	376:cb4d9db17537	501	hspi->Instance->DR = ((uint16_t)hspi->pTxBuffPtr);
mbed_official	376:cb4d9db17537	502	hspi->pTxBuffPtr+=2;
mbed_official	376:cb4d9db17537	503	hspi->TxXferCount--;
mbed_official	376:cb4d9db17537	504	}
mbed_official	376:cb4d9db17537	505
mbed_official	376:cb4d9db17537	506	while(hspi->TxXferCount > 0)
mbed_official	376:cb4d9db17537	507	{
mbed_official	376:cb4d9db17537	508	/* Wait until TXE flag is set to send data */
mbed_official	376:cb4d9db17537	509	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
mbed_official	376:cb4d9db17537	510	{
mbed_official	376:cb4d9db17537	511	return HAL_TIMEOUT;
mbed_official	376:cb4d9db17537	512	}
mbed_official	376:cb4d9db17537	513	hspi->Instance->DR = ((uint16_t)hspi->pTxBuffPtr);
mbed_official	376:cb4d9db17537	514	hspi->pTxBuffPtr+=2;
mbed_official	376:cb4d9db17537	515	hspi->TxXferCount--;
mbed_official	376:cb4d9db17537	516	}
mbed_official	376:cb4d9db17537	517	/* Enable CRC Transmission */
mbed_official	489:119543c9f674	518	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official	376:cb4d9db17537	519	{
mbed_official	489:119543c9f674	520	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
mbed_official	376:cb4d9db17537	521	}
mbed_official	376:cb4d9db17537	522	}
mbed_official	376:cb4d9db17537	523
mbed_official	376:cb4d9db17537	524	/* Wait until TXE flag is set to send data */
mbed_official	376:cb4d9db17537	525	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
mbed_official	376:cb4d9db17537	526	{
mbed_official	489:119543c9f674	527	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
mbed_official	376:cb4d9db17537	528	return HAL_TIMEOUT;
mbed_official	376:cb4d9db17537	529	}
mbed_official	376:cb4d9db17537	530
mbed_official	376:cb4d9db17537	531	/* Wait until Busy flag is reset before disabling SPI */
mbed_official	376:cb4d9db17537	532	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, Timeout) != HAL_OK)
mbed_official	376:cb4d9db17537	533	{
mbed_official	489:119543c9f674	534	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
mbed_official	376:cb4d9db17537	535	return HAL_TIMEOUT;
mbed_official	376:cb4d9db17537	536	}
mbed_official	376:cb4d9db17537	537
mbed_official	376:cb4d9db17537	538	/* Clear OVERUN flag in 2 Lines communication mode because received is not read */
mbed_official	376:cb4d9db17537	539	if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
mbed_official	376:cb4d9db17537	540	{
mbed_official	376:cb4d9db17537	541	__HAL_SPI_CLEAR_OVRFLAG(hspi);
mbed_official	376:cb4d9db17537	542	}
mbed_official	376:cb4d9db17537	543
mbed_official	376:cb4d9db17537	544	hspi->State = HAL_SPI_STATE_READY;
mbed_official	376:cb4d9db17537	545
mbed_official	376:cb4d9db17537	546	/* Process Unlocked */
mbed_official	376:cb4d9db17537	547	__HAL_UNLOCK(hspi);
mbed_official	376:cb4d9db17537	548
mbed_official	376:cb4d9db17537	549	return HAL_OK;
mbed_official	376:cb4d9db17537	550	}
mbed_official	376:cb4d9db17537	551	else
mbed_official	376:cb4d9db17537	552	{
mbed_official	376:cb4d9db17537	553	return HAL_BUSY;
mbed_official	376:cb4d9db17537	554	}
mbed_official	376:cb4d9db17537	555	}
mbed_official	376:cb4d9db17537	556
mbed_official	376:cb4d9db17537	557	/**
mbed_official	376:cb4d9db17537	558	* @brief Receive an amount of data in blocking mode
mbed_official	376:cb4d9db17537	559	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	376:cb4d9db17537	560	* the configuration information for SPI module.
mbed_official	376:cb4d9db17537	561	* @param pData: pointer to data buffer
mbed_official	376:cb4d9db17537	562	* @param Size: amount of data to be sent
mbed_official	376:cb4d9db17537	563	* @param Timeout: Timeout duration
mbed_official	376:cb4d9db17537	564	* @retval HAL status
mbed_official	376:cb4d9db17537	565	*/
mbed_official	376:cb4d9db17537	566	HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size, uint32_t Timeout)
mbed_official	376:cb4d9db17537	567	{
mbed_official	489:119543c9f674	568	__IO uint16_t tmpreg = 0;
mbed_official	376:cb4d9db17537	569
mbed_official	376:cb4d9db17537	570	if(hspi->State == HAL_SPI_STATE_READY)
mbed_official	376:cb4d9db17537	571	{
mbed_official	489:119543c9f674	572	if((pData == NULL ) \|\| (Size == 0))
mbed_official	376:cb4d9db17537	573	{
mbed_official	376:cb4d9db17537	574	return HAL_ERROR;
mbed_official	376:cb4d9db17537	575	}
mbed_official	376:cb4d9db17537	576
mbed_official	376:cb4d9db17537	577	/* Process Locked */
mbed_official	376:cb4d9db17537	578	__HAL_LOCK(hspi);
mbed_official	376:cb4d9db17537	579
mbed_official	376:cb4d9db17537	580	/* Configure communication */
mbed_official	376:cb4d9db17537	581	hspi->State = HAL_SPI_STATE_BUSY_RX;
mbed_official	376:cb4d9db17537	582	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official	376:cb4d9db17537	583
mbed_official	376:cb4d9db17537	584	hspi->pRxBuffPtr = pData;
mbed_official	376:cb4d9db17537	585	hspi->RxXferSize = Size;
mbed_official	376:cb4d9db17537	586	hspi->RxXferCount = Size;
mbed_official	376:cb4d9db17537	587
mbed_official	376:cb4d9db17537	588	/Init field not used in handle to zero /
mbed_official	376:cb4d9db17537	589	hspi->RxISR = 0;
mbed_official	376:cb4d9db17537	590	hspi->TxISR = 0;
mbed_official	489:119543c9f674	591	hspi->pTxBuffPtr = NULL;
mbed_official	489:119543c9f674	592	hspi->TxXferSize = 0;
mbed_official	489:119543c9f674	593	hspi->TxXferCount = 0;
mbed_official	376:cb4d9db17537	594
mbed_official	376:cb4d9db17537	595	/* Configure communication direction : 1Line */
mbed_official	376:cb4d9db17537	596	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
mbed_official	376:cb4d9db17537	597	{
mbed_official	489:119543c9f674	598	SPI_1LINE_RX(hspi);
mbed_official	376:cb4d9db17537	599	}
mbed_official	376:cb4d9db17537	600
mbed_official	376:cb4d9db17537	601	/* Reset CRC Calculation */
mbed_official	489:119543c9f674	602	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official	376:cb4d9db17537	603	{
mbed_official	489:119543c9f674	604	SPI_RESET_CRC(hspi);
mbed_official	376:cb4d9db17537	605	}
mbed_official	376:cb4d9db17537	606
mbed_official	376:cb4d9db17537	607	if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
mbed_official	376:cb4d9db17537	608	{
mbed_official	376:cb4d9db17537	609	/* Process Unlocked */
mbed_official	376:cb4d9db17537	610	__HAL_UNLOCK(hspi);
mbed_official	376:cb4d9db17537	611
mbed_official	376:cb4d9db17537	612	/* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
mbed_official	376:cb4d9db17537	613	return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout);
mbed_official	376:cb4d9db17537	614	}
mbed_official	376:cb4d9db17537	615
mbed_official	376:cb4d9db17537	616	/* Check if the SPI is already enabled */
mbed_official	376:cb4d9db17537	617	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official	376:cb4d9db17537	618	{
mbed_official	376:cb4d9db17537	619	/* Enable SPI peripheral */
mbed_official	376:cb4d9db17537	620	__HAL_SPI_ENABLE(hspi);
mbed_official	376:cb4d9db17537	621	}
mbed_official	376:cb4d9db17537	622
mbed_official	376:cb4d9db17537	623	/* Receive data in 8 Bit mode */
mbed_official	376:cb4d9db17537	624	if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
mbed_official	376:cb4d9db17537	625	{
mbed_official	376:cb4d9db17537	626	while(hspi->RxXferCount > 1)
mbed_official	376:cb4d9db17537	627	{
mbed_official	376:cb4d9db17537	628	/* Wait until RXNE flag is set */
mbed_official	376:cb4d9db17537	629	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
mbed_official	376:cb4d9db17537	630	{
mbed_official	376:cb4d9db17537	631	return HAL_TIMEOUT;
mbed_official	376:cb4d9db17537	632	}
mbed_official	376:cb4d9db17537	633
mbed_official	376:cb4d9db17537	634	(*hspi->pRxBuffPtr++) = hspi->Instance->DR;
mbed_official	376:cb4d9db17537	635	hspi->RxXferCount--;
mbed_official	376:cb4d9db17537	636	}
mbed_official	489:119543c9f674	637	/* Enable CRC Reception */
mbed_official	489:119543c9f674	638	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official	376:cb4d9db17537	639	{
mbed_official	489:119543c9f674	640	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
mbed_official	376:cb4d9db17537	641	}
mbed_official	376:cb4d9db17537	642	}
mbed_official	376:cb4d9db17537	643	/* Receive data in 16 Bit mode */
mbed_official	376:cb4d9db17537	644	else
mbed_official	376:cb4d9db17537	645	{
mbed_official	376:cb4d9db17537	646	while(hspi->RxXferCount > 1)
mbed_official	376:cb4d9db17537	647	{
mbed_official	376:cb4d9db17537	648	/* Wait until RXNE flag is set to read data */
mbed_official	376:cb4d9db17537	649	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
mbed_official	376:cb4d9db17537	650	{
mbed_official	376:cb4d9db17537	651	return HAL_TIMEOUT;
mbed_official	376:cb4d9db17537	652	}
mbed_official	376:cb4d9db17537	653
mbed_official	376:cb4d9db17537	654	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
mbed_official	376:cb4d9db17537	655	hspi->pRxBuffPtr+=2;
mbed_official	376:cb4d9db17537	656	hspi->RxXferCount--;
mbed_official	376:cb4d9db17537	657	}
mbed_official	489:119543c9f674	658	/* Enable CRC Reception */
mbed_official	489:119543c9f674	659	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official	376:cb4d9db17537	660	{
mbed_official	489:119543c9f674	661	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
mbed_official	376:cb4d9db17537	662	}
mbed_official	376:cb4d9db17537	663	}
mbed_official	376:cb4d9db17537	664
mbed_official	376:cb4d9db17537	665	/* Wait until RXNE flag is set */
mbed_official	376:cb4d9db17537	666	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
mbed_official	376:cb4d9db17537	667	{
mbed_official	376:cb4d9db17537	668	return HAL_TIMEOUT;
mbed_official	376:cb4d9db17537	669	}
mbed_official	376:cb4d9db17537	670
mbed_official	376:cb4d9db17537	671	/* Receive last data in 8 Bit mode */
mbed_official	376:cb4d9db17537	672	if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
mbed_official	376:cb4d9db17537	673	{
mbed_official	376:cb4d9db17537	674	(*hspi->pRxBuffPtr++) = hspi->Instance->DR;
mbed_official	376:cb4d9db17537	675	}
mbed_official	376:cb4d9db17537	676	/* Receive last data in 16 Bit mode */
mbed_official	376:cb4d9db17537	677	else
mbed_official	376:cb4d9db17537	678	{
mbed_official	376:cb4d9db17537	679	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
mbed_official	376:cb4d9db17537	680	hspi->pRxBuffPtr+=2;
mbed_official	376:cb4d9db17537	681	}
mbed_official	376:cb4d9db17537	682	hspi->RxXferCount--;
mbed_official	376:cb4d9db17537	683
mbed_official	489:119543c9f674	684	/* If CRC computation is enabled */
mbed_official	489:119543c9f674	685	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official	376:cb4d9db17537	686	{
mbed_official	489:119543c9f674	687	/* Wait until RXNE flag is set: CRC Received */
mbed_official	376:cb4d9db17537	688	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
mbed_official	376:cb4d9db17537	689	{
mbed_official	489:119543c9f674	690	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
mbed_official	376:cb4d9db17537	691	return HAL_TIMEOUT;
mbed_official	376:cb4d9db17537	692	}
mbed_official	376:cb4d9db17537	693
mbed_official	489:119543c9f674	694	/* Read CRC to clear RXNE flag */
mbed_official	376:cb4d9db17537	695	tmpreg = hspi->Instance->DR;
mbed_official	489:119543c9f674	696	UNUSED(tmpreg); /* avoid warning on tmpreg affectation with stupid compiler */
mbed_official	376:cb4d9db17537	697	}
mbed_official	376:cb4d9db17537	698
mbed_official	376:cb4d9db17537	699	if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)\|\|(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
mbed_official	376:cb4d9db17537	700	{
mbed_official	376:cb4d9db17537	701	/* Disable SPI peripheral */
mbed_official	376:cb4d9db17537	702	__HAL_SPI_DISABLE(hspi);
mbed_official	376:cb4d9db17537	703	}
mbed_official	376:cb4d9db17537	704
mbed_official	376:cb4d9db17537	705	hspi->State = HAL_SPI_STATE_READY;
mbed_official	376:cb4d9db17537	706
mbed_official	376:cb4d9db17537	707	/* Check if CRC error occurred */
mbed_official	489:119543c9f674	708	if((hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET))
mbed_official	376:cb4d9db17537	709	{
mbed_official	489:119543c9f674	710	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
mbed_official	376:cb4d9db17537	711
mbed_official	376:cb4d9db17537	712	/* Reset CRC Calculation */
mbed_official	489:119543c9f674	713	SPI_RESET_CRC(hspi);
mbed_official	376:cb4d9db17537	714
mbed_official	376:cb4d9db17537	715	/* Process Unlocked */
mbed_official	376:cb4d9db17537	716	__HAL_UNLOCK(hspi);
mbed_official	376:cb4d9db17537	717
mbed_official	376:cb4d9db17537	718	return HAL_ERROR;
mbed_official	376:cb4d9db17537	719	}
mbed_official	376:cb4d9db17537	720
mbed_official	376:cb4d9db17537	721	/* Process Unlocked */
mbed_official	376:cb4d9db17537	722	__HAL_UNLOCK(hspi);
mbed_official	376:cb4d9db17537	723
mbed_official	376:cb4d9db17537	724	return HAL_OK;
mbed_official	376:cb4d9db17537	725	}
mbed_official	376:cb4d9db17537	726	else
mbed_official	376:cb4d9db17537	727	{
mbed_official	376:cb4d9db17537	728	return HAL_BUSY;
mbed_official	376:cb4d9db17537	729	}
mbed_official	376:cb4d9db17537	730	}
mbed_official	376:cb4d9db17537	731
mbed_official	376:cb4d9db17537	732	/**
mbed_official	376:cb4d9db17537	733	* @brief Transmit and Receive an amount of data in blocking mode
mbed_official	376:cb4d9db17537	734	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	376:cb4d9db17537	735	* the configuration information for SPI module.
mbed_official	376:cb4d9db17537	736	* @param pTxData: pointer to transmission data buffer
mbed_official	376:cb4d9db17537	737	* @param pRxData: pointer to reception data buffer to be
mbed_official	376:cb4d9db17537	738	* @param Size: amount of data to be sent
mbed_official	376:cb4d9db17537	739	* @param Timeout: Timeout duration
mbed_official	376:cb4d9db17537	740	* @retval HAL status
mbed_official	376:cb4d9db17537	741	*/
mbed_official	376:cb4d9db17537	742	HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef hspi, uint8_t pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
mbed_official	376:cb4d9db17537	743	{
mbed_official	489:119543c9f674	744	__IO uint16_t tmpreg = 0;
mbed_official	489:119543c9f674	745
mbed_official	489:119543c9f674	746	if((hspi->State == HAL_SPI_STATE_READY) \|\| (hspi->State == HAL_SPI_STATE_BUSY_RX))
mbed_official	376:cb4d9db17537	747	{
mbed_official	489:119543c9f674	748	if((pTxData == NULL ) \|\| (pRxData == NULL ) \|\| (Size == 0))
mbed_official	376:cb4d9db17537	749	{
mbed_official	376:cb4d9db17537	750	return HAL_ERROR;
mbed_official	376:cb4d9db17537	751	}
mbed_official	376:cb4d9db17537	752
mbed_official	376:cb4d9db17537	753	/* Check the parameters */
mbed_official	376:cb4d9db17537	754	assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
mbed_official	376:cb4d9db17537	755
mbed_official	376:cb4d9db17537	756	/* Process Locked */
mbed_official	376:cb4d9db17537	757	__HAL_LOCK(hspi);
mbed_official	376:cb4d9db17537	758
mbed_official	376:cb4d9db17537	759	/* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
mbed_official	376:cb4d9db17537	760	if(hspi->State == HAL_SPI_STATE_READY)
mbed_official	376:cb4d9db17537	761	{
mbed_official	376:cb4d9db17537	762	hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
mbed_official	376:cb4d9db17537	763	}
mbed_official	376:cb4d9db17537	764
mbed_official	376:cb4d9db17537	765	/* Configure communication */
mbed_official	376:cb4d9db17537	766	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official	376:cb4d9db17537	767
mbed_official	376:cb4d9db17537	768	hspi->pRxBuffPtr = pRxData;
mbed_official	376:cb4d9db17537	769	hspi->RxXferSize = Size;
mbed_official	376:cb4d9db17537	770	hspi->RxXferCount = Size;
mbed_official	376:cb4d9db17537	771
mbed_official	376:cb4d9db17537	772	hspi->pTxBuffPtr = pTxData;
mbed_official	376:cb4d9db17537	773	hspi->TxXferSize = Size;
mbed_official	376:cb4d9db17537	774	hspi->TxXferCount = Size;
mbed_official	376:cb4d9db17537	775
mbed_official	376:cb4d9db17537	776	/Init field not used in handle to zero /
mbed_official	376:cb4d9db17537	777	hspi->RxISR = 0;
mbed_official	376:cb4d9db17537	778	hspi->TxISR = 0;
mbed_official	376:cb4d9db17537	779
mbed_official	376:cb4d9db17537	780	/* Reset CRC Calculation */
mbed_official	489:119543c9f674	781	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official	376:cb4d9db17537	782	{
mbed_official	489:119543c9f674	783	SPI_RESET_CRC(hspi);
mbed_official	376:cb4d9db17537	784	}
mbed_official	376:cb4d9db17537	785
mbed_official	376:cb4d9db17537	786	/* Check if the SPI is already enabled */
mbed_official	376:cb4d9db17537	787	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official	376:cb4d9db17537	788	{
mbed_official	376:cb4d9db17537	789	/* Enable SPI peripheral */
mbed_official	376:cb4d9db17537	790	__HAL_SPI_ENABLE(hspi);
mbed_official	376:cb4d9db17537	791	}
mbed_official	376:cb4d9db17537	792
mbed_official	376:cb4d9db17537	793	/* Transmit and Receive data in 16 Bit mode */
mbed_official	376:cb4d9db17537	794	if(hspi->Init.DataSize == SPI_DATASIZE_16BIT)
mbed_official	376:cb4d9db17537	795	{
mbed_official	376:cb4d9db17537	796	if((hspi->Init.Mode == SPI_MODE_SLAVE) \|\| ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->TxXferCount == 0x01)))
mbed_official	376:cb4d9db17537	797	{
mbed_official	376:cb4d9db17537	798	hspi->Instance->DR = ((uint16_t)hspi->pTxBuffPtr);
mbed_official	376:cb4d9db17537	799	hspi->pTxBuffPtr+=2;
mbed_official	376:cb4d9db17537	800	hspi->TxXferCount--;
mbed_official	376:cb4d9db17537	801	}
mbed_official	376:cb4d9db17537	802	if(hspi->TxXferCount == 0)
mbed_official	376:cb4d9db17537	803	{
mbed_official	376:cb4d9db17537	804	/* Enable CRC Transmission */
mbed_official	489:119543c9f674	805	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official	376:cb4d9db17537	806	{
mbed_official	489:119543c9f674	807	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
mbed_official	376:cb4d9db17537	808	}
mbed_official	376:cb4d9db17537	809
mbed_official	376:cb4d9db17537	810	/* Wait until RXNE flag is set */
mbed_official	376:cb4d9db17537	811	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
mbed_official	376:cb4d9db17537	812	{
mbed_official	376:cb4d9db17537	813	return HAL_TIMEOUT;
mbed_official	376:cb4d9db17537	814	}
mbed_official	376:cb4d9db17537	815
mbed_official	376:cb4d9db17537	816	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
mbed_official	376:cb4d9db17537	817	hspi->pRxBuffPtr+=2;
mbed_official	376:cb4d9db17537	818	hspi->RxXferCount--;
mbed_official	376:cb4d9db17537	819	}
mbed_official	376:cb4d9db17537	820	else
mbed_official	376:cb4d9db17537	821	{
mbed_official	376:cb4d9db17537	822	while(hspi->TxXferCount > 0)
mbed_official	376:cb4d9db17537	823	{
mbed_official	376:cb4d9db17537	824	/* Wait until TXE flag is set to send data */
mbed_official	376:cb4d9db17537	825	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
mbed_official	376:cb4d9db17537	826	{
mbed_official	376:cb4d9db17537	827	return HAL_TIMEOUT;
mbed_official	376:cb4d9db17537	828	}
mbed_official	376:cb4d9db17537	829
mbed_official	376:cb4d9db17537	830	hspi->Instance->DR = ((uint16_t)hspi->pTxBuffPtr);
mbed_official	376:cb4d9db17537	831	hspi->pTxBuffPtr+=2;
mbed_official	376:cb4d9db17537	832	hspi->TxXferCount--;
mbed_official	376:cb4d9db17537	833
mbed_official	376:cb4d9db17537	834	/* Enable CRC Transmission */
mbed_official	489:119543c9f674	835	if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
mbed_official	376:cb4d9db17537	836	{
mbed_official	489:119543c9f674	837	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
mbed_official	376:cb4d9db17537	838	}
mbed_official	376:cb4d9db17537	839
mbed_official	376:cb4d9db17537	840	/* Wait until RXNE flag is set */
mbed_official	376:cb4d9db17537	841	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
mbed_official	376:cb4d9db17537	842	{
mbed_official	376:cb4d9db17537	843	return HAL_TIMEOUT;
mbed_official	376:cb4d9db17537	844	}
mbed_official	489:119543c9f674	845
mbed_official	376:cb4d9db17537	846	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
mbed_official	376:cb4d9db17537	847	hspi->pRxBuffPtr+=2;
mbed_official	376:cb4d9db17537	848	hspi->RxXferCount--;
mbed_official	376:cb4d9db17537	849	}
mbed_official	376:cb4d9db17537	850	/* Receive the last byte */
mbed_official	376:cb4d9db17537	851	if(hspi->Init.Mode == SPI_MODE_SLAVE)
mbed_official	376:cb4d9db17537	852	{
mbed_official	376:cb4d9db17537	853	/* Wait until RXNE flag is set */
mbed_official	376:cb4d9db17537	854	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
mbed_official	376:cb4d9db17537	855	{
mbed_official	376:cb4d9db17537	856	return HAL_TIMEOUT;
mbed_official	376:cb4d9db17537	857	}
mbed_official	376:cb4d9db17537	858
mbed_official	376:cb4d9db17537	859	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
mbed_official	376:cb4d9db17537	860	hspi->pRxBuffPtr+=2;
mbed_official	376:cb4d9db17537	861	hspi->RxXferCount--;
mbed_official	376:cb4d9db17537	862	}
mbed_official	376:cb4d9db17537	863	}
mbed_official	376:cb4d9db17537	864	}
mbed_official	376:cb4d9db17537	865	/* Transmit and Receive data in 8 Bit mode */
mbed_official	376:cb4d9db17537	866	else
mbed_official	376:cb4d9db17537	867	{
mbed_official	376:cb4d9db17537	868	if((hspi->Init.Mode == SPI_MODE_SLAVE) \|\| ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->TxXferCount == 0x01)))
mbed_official	376:cb4d9db17537	869	{
mbed_official	376:cb4d9db17537	870	hspi->Instance->DR = (*hspi->pTxBuffPtr++);
mbed_official	376:cb4d9db17537	871	hspi->TxXferCount--;
mbed_official	376:cb4d9db17537	872	}
mbed_official	376:cb4d9db17537	873	if(hspi->TxXferCount == 0)
mbed_official	376:cb4d9db17537	874	{
mbed_official	376:cb4d9db17537	875	/* Enable CRC Transmission */
mbed_official	489:119543c9f674	876	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official	376:cb4d9db17537	877	{
mbed_official	489:119543c9f674	878	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
mbed_official	376:cb4d9db17537	879	}
mbed_official	376:cb4d9db17537	880
mbed_official	376:cb4d9db17537	881	/* Wait until RXNE flag is set */
mbed_official	376:cb4d9db17537	882	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
mbed_official	376:cb4d9db17537	883	{
mbed_official	376:cb4d9db17537	884	return HAL_TIMEOUT;
mbed_official	376:cb4d9db17537	885	}
mbed_official	376:cb4d9db17537	886
mbed_official	376:cb4d9db17537	887	(*hspi->pRxBuffPtr) = hspi->Instance->DR;
mbed_official	376:cb4d9db17537	888	hspi->RxXferCount--;
mbed_official	376:cb4d9db17537	889	}
mbed_official	376:cb4d9db17537	890	else
mbed_official	376:cb4d9db17537	891	{
mbed_official	376:cb4d9db17537	892	while(hspi->TxXferCount > 0)
mbed_official	376:cb4d9db17537	893	{
mbed_official	376:cb4d9db17537	894	/* Wait until TXE flag is set to send data */
mbed_official	376:cb4d9db17537	895	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
mbed_official	376:cb4d9db17537	896	{
mbed_official	376:cb4d9db17537	897	return HAL_TIMEOUT;
mbed_official	376:cb4d9db17537	898	}
mbed_official	376:cb4d9db17537	899
mbed_official	376:cb4d9db17537	900	hspi->Instance->DR = (*hspi->pTxBuffPtr++);
mbed_official	376:cb4d9db17537	901	hspi->TxXferCount--;
mbed_official	376:cb4d9db17537	902
mbed_official	376:cb4d9db17537	903	/* Enable CRC Transmission */
mbed_official	489:119543c9f674	904	if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
mbed_official	376:cb4d9db17537	905	{
mbed_official	489:119543c9f674	906	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
mbed_official	376:cb4d9db17537	907	}
mbed_official	376:cb4d9db17537	908
mbed_official	489:119543c9f674	909	/* Wait until RXNE flag is set */
mbed_official	489:119543c9f674	910	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
mbed_official	489:119543c9f674	911	{
mbed_official	489:119543c9f674	912	return HAL_TIMEOUT;
mbed_official	489:119543c9f674	913	}
mbed_official	489:119543c9f674	914
mbed_official	489:119543c9f674	915	(*hspi->pRxBuffPtr++) = hspi->Instance->DR;
mbed_official	489:119543c9f674	916	hspi->RxXferCount--;
mbed_official	376:cb4d9db17537	917	}
mbed_official	376:cb4d9db17537	918	if(hspi->Init.Mode == SPI_MODE_SLAVE)
mbed_official	376:cb4d9db17537	919	{
mbed_official	376:cb4d9db17537	920	/* Wait until RXNE flag is set */
mbed_official	376:cb4d9db17537	921	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
mbed_official	376:cb4d9db17537	922	{
mbed_official	376:cb4d9db17537	923	return HAL_TIMEOUT;
mbed_official	376:cb4d9db17537	924	}
mbed_official	376:cb4d9db17537	925
mbed_official	376:cb4d9db17537	926	(*hspi->pRxBuffPtr++) = hspi->Instance->DR;
mbed_official	376:cb4d9db17537	927	hspi->RxXferCount--;
mbed_official	376:cb4d9db17537	928	}
mbed_official	376:cb4d9db17537	929	}
mbed_official	376:cb4d9db17537	930	}
mbed_official	376:cb4d9db17537	931
mbed_official	376:cb4d9db17537	932	/* Read CRC from DR to close CRC calculation process */
mbed_official	489:119543c9f674	933	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official	376:cb4d9db17537	934	{
mbed_official	376:cb4d9db17537	935	/* Wait until RXNE flag is set */
mbed_official	376:cb4d9db17537	936	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
mbed_official	376:cb4d9db17537	937	{
mbed_official	489:119543c9f674	938	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
mbed_official	376:cb4d9db17537	939	return HAL_TIMEOUT;
mbed_official	376:cb4d9db17537	940	}
mbed_official	376:cb4d9db17537	941	/* Read CRC */
mbed_official	376:cb4d9db17537	942	tmpreg = hspi->Instance->DR;
mbed_official	489:119543c9f674	943	UNUSED(tmpreg); /* avoid warning on tmpreg affectation with stupid compiler */
mbed_official	376:cb4d9db17537	944	}
mbed_official	376:cb4d9db17537	945
mbed_official	376:cb4d9db17537	946	/* Wait until Busy flag is reset before disabling SPI */
mbed_official	376:cb4d9db17537	947	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, Timeout) != HAL_OK)
mbed_official	376:cb4d9db17537	948	{
mbed_official	489:119543c9f674	949	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
mbed_official	376:cb4d9db17537	950	return HAL_TIMEOUT;
mbed_official	376:cb4d9db17537	951	}
mbed_official	376:cb4d9db17537	952
mbed_official	376:cb4d9db17537	953	hspi->State = HAL_SPI_STATE_READY;
mbed_official	376:cb4d9db17537	954
mbed_official	376:cb4d9db17537	955	/* Check if CRC error occurred */
mbed_official	489:119543c9f674	956	if((hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET))
mbed_official	376:cb4d9db17537	957	{
mbed_official	489:119543c9f674	958	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
mbed_official	376:cb4d9db17537	959
mbed_official	489:119543c9f674	960	SPI_RESET_CRC(hspi);
mbed_official	376:cb4d9db17537	961
mbed_official	376:cb4d9db17537	962	/* Process Unlocked */
mbed_official	376:cb4d9db17537	963	__HAL_UNLOCK(hspi);
mbed_official	376:cb4d9db17537	964
mbed_official	376:cb4d9db17537	965	return HAL_ERROR;
mbed_official	376:cb4d9db17537	966	}
mbed_official	376:cb4d9db17537	967
mbed_official	376:cb4d9db17537	968	/* Process Unlocked */
mbed_official	376:cb4d9db17537	969	__HAL_UNLOCK(hspi);
mbed_official	376:cb4d9db17537	970
mbed_official	376:cb4d9db17537	971	return HAL_OK;
mbed_official	376:cb4d9db17537	972	}
mbed_official	376:cb4d9db17537	973	else
mbed_official	376:cb4d9db17537	974	{
mbed_official	376:cb4d9db17537	975	return HAL_BUSY;
mbed_official	376:cb4d9db17537	976	}
mbed_official	376:cb4d9db17537	977	}
mbed_official	376:cb4d9db17537	978
mbed_official	376:cb4d9db17537	979	/**
mbed_official	376:cb4d9db17537	980	* @brief Transmit an amount of data in no-blocking mode with Interrupt
mbed_official	376:cb4d9db17537	981	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	376:cb4d9db17537	982	* the configuration information for SPI module.
mbed_official	376:cb4d9db17537	983	* @param pData: pointer to data buffer
mbed_official	376:cb4d9db17537	984	* @param Size: amount of data to be sent
mbed_official	376:cb4d9db17537	985	* @retval HAL status
mbed_official	376:cb4d9db17537	986	*/
mbed_official	376:cb4d9db17537	987	HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
mbed_official	376:cb4d9db17537	988	{
mbed_official	376:cb4d9db17537	989	if(hspi->State == HAL_SPI_STATE_READY)
mbed_official	376:cb4d9db17537	990	{
mbed_official	489:119543c9f674	991	if((pData == NULL) \|\| (Size == 0))
mbed_official	376:cb4d9db17537	992	{
mbed_official	376:cb4d9db17537	993	return HAL_ERROR;
mbed_official	376:cb4d9db17537	994	}
mbed_official	376:cb4d9db17537	995
mbed_official	376:cb4d9db17537	996	/* Check the parameters */
mbed_official	376:cb4d9db17537	997	assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
mbed_official	376:cb4d9db17537	998
mbed_official	376:cb4d9db17537	999	/* Process Locked */
mbed_official	376:cb4d9db17537	1000	__HAL_LOCK(hspi);
mbed_official	376:cb4d9db17537	1001
mbed_official	376:cb4d9db17537	1002	/* Configure communication */
mbed_official	376:cb4d9db17537	1003	hspi->State = HAL_SPI_STATE_BUSY_TX;
mbed_official	376:cb4d9db17537	1004	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official	376:cb4d9db17537	1005
mbed_official	489:119543c9f674	1006	hspi->TxISR = &SPI_TxISR;
mbed_official	376:cb4d9db17537	1007	hspi->pTxBuffPtr = pData;
mbed_official	376:cb4d9db17537	1008	hspi->TxXferSize = Size;
mbed_official	376:cb4d9db17537	1009	hspi->TxXferCount = Size;
mbed_official	376:cb4d9db17537	1010
mbed_official	376:cb4d9db17537	1011	/Init field not used in handle to zero /
mbed_official	489:119543c9f674	1012	hspi->RxISR = 0;
mbed_official	489:119543c9f674	1013	hspi->pRxBuffPtr = NULL;
mbed_official	376:cb4d9db17537	1014	hspi->RxXferSize = 0;
mbed_official	376:cb4d9db17537	1015	hspi->RxXferCount = 0;
mbed_official	376:cb4d9db17537	1016
mbed_official	376:cb4d9db17537	1017	/* Configure communication direction : 1Line */
mbed_official	376:cb4d9db17537	1018	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
mbed_official	376:cb4d9db17537	1019	{
mbed_official	489:119543c9f674	1020	SPI_1LINE_TX(hspi);
mbed_official	376:cb4d9db17537	1021	}
mbed_official	376:cb4d9db17537	1022
mbed_official	376:cb4d9db17537	1023	/* Reset CRC Calculation */
mbed_official	489:119543c9f674	1024	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official	376:cb4d9db17537	1025	{
mbed_official	489:119543c9f674	1026	SPI_RESET_CRC(hspi);
mbed_official	376:cb4d9db17537	1027	}
mbed_official	376:cb4d9db17537	1028
mbed_official	376:cb4d9db17537	1029	if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
mbed_official	376:cb4d9db17537	1030	{
mbed_official	376:cb4d9db17537	1031	__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE));
mbed_official	489:119543c9f674	1032	}
mbed_official	489:119543c9f674	1033	else
mbed_official	376:cb4d9db17537	1034	{
mbed_official	376:cb4d9db17537	1035	/* Enable TXE and ERR interrupt */
mbed_official	376:cb4d9db17537	1036	__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_ERR));
mbed_official	376:cb4d9db17537	1037	}
mbed_official	376:cb4d9db17537	1038	/* Process Unlocked */
mbed_official	376:cb4d9db17537	1039	__HAL_UNLOCK(hspi);
mbed_official	376:cb4d9db17537	1040
mbed_official	376:cb4d9db17537	1041	/* Check if the SPI is already enabled */
mbed_official	376:cb4d9db17537	1042	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official	376:cb4d9db17537	1043	{
mbed_official	376:cb4d9db17537	1044	/* Enable SPI peripheral */
mbed_official	376:cb4d9db17537	1045	__HAL_SPI_ENABLE(hspi);
mbed_official	376:cb4d9db17537	1046	}
mbed_official	376:cb4d9db17537	1047
mbed_official	376:cb4d9db17537	1048	return HAL_OK;
mbed_official	376:cb4d9db17537	1049	}
mbed_official	376:cb4d9db17537	1050	else
mbed_official	376:cb4d9db17537	1051	{
mbed_official	376:cb4d9db17537	1052	return HAL_BUSY;
mbed_official	376:cb4d9db17537	1053	}
mbed_official	376:cb4d9db17537	1054	}
mbed_official	376:cb4d9db17537	1055
mbed_official	376:cb4d9db17537	1056	/**
mbed_official	376:cb4d9db17537	1057	* @brief Receive an amount of data in no-blocking mode with Interrupt
mbed_official	376:cb4d9db17537	1058	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	376:cb4d9db17537	1059	* the configuration information for SPI module.
mbed_official	376:cb4d9db17537	1060	* @param pData: pointer to data buffer
mbed_official	376:cb4d9db17537	1061	* @param Size: amount of data to be sent
mbed_official	376:cb4d9db17537	1062	* @retval HAL status
mbed_official	376:cb4d9db17537	1063	*/
mbed_official	376:cb4d9db17537	1064	HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
mbed_official	376:cb4d9db17537	1065	{
mbed_official	376:cb4d9db17537	1066	if(hspi->State == HAL_SPI_STATE_READY)
mbed_official	376:cb4d9db17537	1067	{
mbed_official	489:119543c9f674	1068	if((pData == NULL) \|\| (Size == 0))
mbed_official	376:cb4d9db17537	1069	{
mbed_official	376:cb4d9db17537	1070	return HAL_ERROR;
mbed_official	376:cb4d9db17537	1071	}
mbed_official	376:cb4d9db17537	1072
mbed_official	376:cb4d9db17537	1073	/* Process Locked */
mbed_official	376:cb4d9db17537	1074	__HAL_LOCK(hspi);
mbed_official	376:cb4d9db17537	1075
mbed_official	376:cb4d9db17537	1076	/* Configure communication */
mbed_official	376:cb4d9db17537	1077	hspi->State = HAL_SPI_STATE_BUSY_RX;
mbed_official	376:cb4d9db17537	1078	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official	376:cb4d9db17537	1079
mbed_official	489:119543c9f674	1080	hspi->RxISR = &SPI_RxISR;
mbed_official	376:cb4d9db17537	1081	hspi->pRxBuffPtr = pData;
mbed_official	376:cb4d9db17537	1082	hspi->RxXferSize = Size;
mbed_official	376:cb4d9db17537	1083	hspi->RxXferCount = Size ;
mbed_official	376:cb4d9db17537	1084
mbed_official	376:cb4d9db17537	1085	/Init field not used in handle to zero /
mbed_official	489:119543c9f674	1086	hspi->TxISR = 0;
mbed_official	489:119543c9f674	1087	hspi->pTxBuffPtr = NULL;
mbed_official	376:cb4d9db17537	1088	hspi->TxXferSize = 0;
mbed_official	376:cb4d9db17537	1089	hspi->TxXferCount = 0;
mbed_official	376:cb4d9db17537	1090
mbed_official	376:cb4d9db17537	1091	/* Configure communication direction : 1Line */
mbed_official	376:cb4d9db17537	1092	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
mbed_official	376:cb4d9db17537	1093	{
mbed_official	489:119543c9f674	1094	SPI_1LINE_RX(hspi);
mbed_official	376:cb4d9db17537	1095	}
mbed_official	376:cb4d9db17537	1096	else if((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
mbed_official	376:cb4d9db17537	1097	{
mbed_official	489:119543c9f674	1098	/* Process Unlocked */
mbed_official	489:119543c9f674	1099	__HAL_UNLOCK(hspi);
mbed_official	376:cb4d9db17537	1100
mbed_official	489:119543c9f674	1101	/* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
mbed_official	489:119543c9f674	1102	return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size);
mbed_official	376:cb4d9db17537	1103	}
mbed_official	376:cb4d9db17537	1104
mbed_official	376:cb4d9db17537	1105	/* Reset CRC Calculation */
mbed_official	489:119543c9f674	1106	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official	376:cb4d9db17537	1107	{
mbed_official	489:119543c9f674	1108	SPI_RESET_CRC(hspi);
mbed_official	376:cb4d9db17537	1109	}
mbed_official	376:cb4d9db17537	1110
mbed_official	376:cb4d9db17537	1111	/* Enable TXE and ERR interrupt */
mbed_official	376:cb4d9db17537	1112	__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE \| SPI_IT_ERR));
mbed_official	376:cb4d9db17537	1113
mbed_official	376:cb4d9db17537	1114	/* Process Unlocked */
mbed_official	376:cb4d9db17537	1115	__HAL_UNLOCK(hspi);
mbed_official	376:cb4d9db17537	1116
mbed_official	376:cb4d9db17537	1117	/* Note : The SPI must be enabled after unlocking current process
mbed_official	376:cb4d9db17537	1118	to avoid the risk of SPI interrupt handle execution before current
mbed_official	376:cb4d9db17537	1119	process unlock */
mbed_official	376:cb4d9db17537	1120
mbed_official	489:119543c9f674	1121	/* Check if the SPI is already enabled */
mbed_official	376:cb4d9db17537	1122	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official	376:cb4d9db17537	1123	{
mbed_official	376:cb4d9db17537	1124	/* Enable SPI peripheral */
mbed_official	376:cb4d9db17537	1125	__HAL_SPI_ENABLE(hspi);
mbed_official	376:cb4d9db17537	1126	}
mbed_official	376:cb4d9db17537	1127
mbed_official	376:cb4d9db17537	1128	return HAL_OK;
mbed_official	376:cb4d9db17537	1129	}
mbed_official	376:cb4d9db17537	1130	else
mbed_official	376:cb4d9db17537	1131	{
mbed_official	376:cb4d9db17537	1132	return HAL_BUSY;
mbed_official	376:cb4d9db17537	1133	}
mbed_official	376:cb4d9db17537	1134	}
mbed_official	376:cb4d9db17537	1135
mbed_official	376:cb4d9db17537	1136	/**
mbed_official	376:cb4d9db17537	1137	* @brief Transmit and Receive an amount of data in no-blocking mode with Interrupt
mbed_official	376:cb4d9db17537	1138	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	376:cb4d9db17537	1139	* the configuration information for SPI module.
mbed_official	376:cb4d9db17537	1140	* @param pTxData: pointer to transmission data buffer
mbed_official	376:cb4d9db17537	1141	* @param pRxData: pointer to reception data buffer to be
mbed_official	376:cb4d9db17537	1142	* @param Size: amount of data to be sent
mbed_official	376:cb4d9db17537	1143	* @retval HAL status
mbed_official	376:cb4d9db17537	1144	*/
mbed_official	376:cb4d9db17537	1145	HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef hspi, uint8_t pTxData, uint8_t *pRxData, uint16_t Size)
mbed_official	376:cb4d9db17537	1146	{
mbed_official	376:cb4d9db17537	1147
mbed_official	489:119543c9f674	1148	if((hspi->State == HAL_SPI_STATE_READY) \|\| \
mbed_official	489:119543c9f674	1149	((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX)))
mbed_official	376:cb4d9db17537	1150	{
mbed_official	489:119543c9f674	1151	if((pTxData == NULL ) \|\| (pRxData == NULL ) \|\| (Size == 0))
mbed_official	376:cb4d9db17537	1152	{
mbed_official	376:cb4d9db17537	1153	return HAL_ERROR;
mbed_official	376:cb4d9db17537	1154	}
mbed_official	376:cb4d9db17537	1155
mbed_official	376:cb4d9db17537	1156	/* Check the parameters */
mbed_official	376:cb4d9db17537	1157	assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
mbed_official	376:cb4d9db17537	1158
mbed_official	376:cb4d9db17537	1159	/* Process locked */
mbed_official	376:cb4d9db17537	1160	__HAL_LOCK(hspi);
mbed_official	376:cb4d9db17537	1161
mbed_official	376:cb4d9db17537	1162	/* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
mbed_official	376:cb4d9db17537	1163	if(hspi->State != HAL_SPI_STATE_BUSY_RX)
mbed_official	376:cb4d9db17537	1164	{
mbed_official	376:cb4d9db17537	1165	hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
mbed_official	376:cb4d9db17537	1166	}
mbed_official	376:cb4d9db17537	1167
mbed_official	376:cb4d9db17537	1168	/* Configure communication */
mbed_official	376:cb4d9db17537	1169	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official	376:cb4d9db17537	1170
mbed_official	376:cb4d9db17537	1171	hspi->TxISR = &SPI_TxISR;
mbed_official	376:cb4d9db17537	1172	hspi->pTxBuffPtr = pTxData;
mbed_official	376:cb4d9db17537	1173	hspi->TxXferSize = Size;
mbed_official	376:cb4d9db17537	1174	hspi->TxXferCount = Size;
mbed_official	376:cb4d9db17537	1175
mbed_official	376:cb4d9db17537	1176	hspi->RxISR = &SPI_2LinesRxISR;
mbed_official	376:cb4d9db17537	1177	hspi->pRxBuffPtr = pRxData;
mbed_official	376:cb4d9db17537	1178	hspi->RxXferSize = Size;
mbed_official	376:cb4d9db17537	1179	hspi->RxXferCount = Size;
mbed_official	376:cb4d9db17537	1180
mbed_official	376:cb4d9db17537	1181	/* Reset CRC Calculation */
mbed_official	489:119543c9f674	1182	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official	376:cb4d9db17537	1183	{
mbed_official	489:119543c9f674	1184	SPI_RESET_CRC(hspi);
mbed_official	376:cb4d9db17537	1185	}
mbed_official	376:cb4d9db17537	1186
mbed_official	376:cb4d9db17537	1187	/* Enable TXE, RXNE and ERR interrupt */
mbed_official	376:cb4d9db17537	1188	__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_RXNE \| SPI_IT_ERR));
mbed_official	376:cb4d9db17537	1189
mbed_official	376:cb4d9db17537	1190	/* Process Unlocked */
mbed_official	376:cb4d9db17537	1191	__HAL_UNLOCK(hspi);
mbed_official	376:cb4d9db17537	1192
mbed_official	376:cb4d9db17537	1193	/* Check if the SPI is already enabled */
mbed_official	376:cb4d9db17537	1194	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official	376:cb4d9db17537	1195	{
mbed_official	376:cb4d9db17537	1196	/* Enable SPI peripheral */
mbed_official	376:cb4d9db17537	1197	__HAL_SPI_ENABLE(hspi);
mbed_official	376:cb4d9db17537	1198	}
mbed_official	376:cb4d9db17537	1199
mbed_official	376:cb4d9db17537	1200	return HAL_OK;
mbed_official	376:cb4d9db17537	1201	}
mbed_official	376:cb4d9db17537	1202	else
mbed_official	376:cb4d9db17537	1203	{
mbed_official	376:cb4d9db17537	1204	return HAL_BUSY;
mbed_official	376:cb4d9db17537	1205	}
mbed_official	376:cb4d9db17537	1206	}
mbed_official	376:cb4d9db17537	1207
mbed_official	376:cb4d9db17537	1208	/**
mbed_official	376:cb4d9db17537	1209	* @brief Transmit an amount of data in no-blocking mode with DMA
mbed_official	376:cb4d9db17537	1210	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	376:cb4d9db17537	1211	* the configuration information for SPI module.
mbed_official	376:cb4d9db17537	1212	* @param pData: pointer to data buffer
mbed_official	376:cb4d9db17537	1213	* @param Size: amount of data to be sent
mbed_official	376:cb4d9db17537	1214	* @retval HAL status
mbed_official	376:cb4d9db17537	1215	*/
mbed_official	376:cb4d9db17537	1216	HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
mbed_official	376:cb4d9db17537	1217	{
mbed_official	376:cb4d9db17537	1218	if(hspi->State == HAL_SPI_STATE_READY)
mbed_official	376:cb4d9db17537	1219	{
mbed_official	489:119543c9f674	1220	if((pData == NULL) \|\| (Size == 0))
mbed_official	376:cb4d9db17537	1221	{
mbed_official	489:119543c9f674	1222	/* Process Unlocked */
mbed_official	489:119543c9f674	1223	__HAL_UNLOCK(hspi);
mbed_official	376:cb4d9db17537	1224	return HAL_ERROR;
mbed_official	376:cb4d9db17537	1225	}
mbed_official	376:cb4d9db17537	1226
mbed_official	376:cb4d9db17537	1227	/* Check the parameters */
mbed_official	376:cb4d9db17537	1228	assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
mbed_official	376:cb4d9db17537	1229
mbed_official	376:cb4d9db17537	1230	/* Process Locked */
mbed_official	376:cb4d9db17537	1231	__HAL_LOCK(hspi);
mbed_official	376:cb4d9db17537	1232
mbed_official	376:cb4d9db17537	1233	/* Configure communication */
mbed_official	376:cb4d9db17537	1234	hspi->State = HAL_SPI_STATE_BUSY_TX;
mbed_official	376:cb4d9db17537	1235	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official	376:cb4d9db17537	1236
mbed_official	489:119543c9f674	1237	hspi->pTxBuffPtr = (uint8_t*)pData;
mbed_official	376:cb4d9db17537	1238	hspi->TxXferSize = Size;
mbed_official	376:cb4d9db17537	1239	hspi->TxXferCount = Size;
mbed_official	376:cb4d9db17537	1240
mbed_official	376:cb4d9db17537	1241	/Init field not used in handle to zero /
mbed_official	489:119543c9f674	1242	hspi->TxISR = 0;
mbed_official	489:119543c9f674	1243	hspi->RxISR = 0;
mbed_official	489:119543c9f674	1244
mbed_official	489:119543c9f674	1245	hspi->pRxBuffPtr = NULL;
mbed_official	489:119543c9f674	1246	hspi->RxXferSize = 0;
mbed_official	489:119543c9f674	1247	hspi->RxXferCount = 0;
mbed_official	376:cb4d9db17537	1248
mbed_official	376:cb4d9db17537	1249	/* Configure communication direction : 1Line */
mbed_official	376:cb4d9db17537	1250	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
mbed_official	376:cb4d9db17537	1251	{
mbed_official	489:119543c9f674	1252	SPI_1LINE_TX(hspi);
mbed_official	376:cb4d9db17537	1253	}
mbed_official	376:cb4d9db17537	1254
mbed_official	376:cb4d9db17537	1255	/* Reset CRC Calculation */
mbed_official	489:119543c9f674	1256	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official	376:cb4d9db17537	1257	{
mbed_official	489:119543c9f674	1258	SPI_RESET_CRC(hspi);
mbed_official	376:cb4d9db17537	1259	}
mbed_official	489:119543c9f674	1260
mbed_official	376:cb4d9db17537	1261	/* Set the SPI TxDMA Half transfer complete callback */
mbed_official	376:cb4d9db17537	1262	hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt;
mbed_official	489:119543c9f674	1263
mbed_official	376:cb4d9db17537	1264	/* Set the SPI TxDMA transfer complete callback */
mbed_official	376:cb4d9db17537	1265	hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt;
mbed_official	376:cb4d9db17537	1266
mbed_official	376:cb4d9db17537	1267	/* Set the DMA error callback */
mbed_official	376:cb4d9db17537	1268	hspi->hdmatx->XferErrorCallback = SPI_DMAError;
mbed_official	376:cb4d9db17537	1269
mbed_official	489:119543c9f674	1270	/* Reset content of SPI RxDMA descriptor */
mbed_official	489:119543c9f674	1271	hspi->hdmarx->XferHalfCpltCallback = (void ()(DMA_HandleTypeDef ))NULL;
mbed_official	489:119543c9f674	1272	hspi->hdmarx->XferCpltCallback = (void ()(DMA_HandleTypeDef ))NULL;
mbed_official	489:119543c9f674	1273	hspi->hdmarx->XferErrorCallback = (void ()(DMA_HandleTypeDef ))NULL;
mbed_official	489:119543c9f674	1274
mbed_official	489:119543c9f674	1275	/* Enable the Tx DMA Channel */
mbed_official	376:cb4d9db17537	1276	HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
mbed_official	376:cb4d9db17537	1277
mbed_official	376:cb4d9db17537	1278	/* Enable Tx DMA Request */
mbed_official	489:119543c9f674	1279	SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
mbed_official	376:cb4d9db17537	1280
mbed_official	376:cb4d9db17537	1281	/* Process Unlocked */
mbed_official	376:cb4d9db17537	1282	__HAL_UNLOCK(hspi);
mbed_official	376:cb4d9db17537	1283
mbed_official	376:cb4d9db17537	1284	/* Check if the SPI is already enabled */
mbed_official	376:cb4d9db17537	1285	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official	376:cb4d9db17537	1286	{
mbed_official	376:cb4d9db17537	1287	/* Enable SPI peripheral */
mbed_official	376:cb4d9db17537	1288	__HAL_SPI_ENABLE(hspi);
mbed_official	376:cb4d9db17537	1289	}
mbed_official	376:cb4d9db17537	1290
mbed_official	376:cb4d9db17537	1291	return HAL_OK;
mbed_official	376:cb4d9db17537	1292	}
mbed_official	376:cb4d9db17537	1293	else
mbed_official	376:cb4d9db17537	1294	{
mbed_official	489:119543c9f674	1295	/* Process Unlocked */
mbed_official	489:119543c9f674	1296	__HAL_UNLOCK(hspi);
mbed_official	376:cb4d9db17537	1297	return HAL_BUSY;
mbed_official	376:cb4d9db17537	1298	}
mbed_official	376:cb4d9db17537	1299	}
mbed_official	376:cb4d9db17537	1300
mbed_official	376:cb4d9db17537	1301	/**
mbed_official	376:cb4d9db17537	1302	* @brief Receive an amount of data in no-blocking mode with DMA
mbed_official	376:cb4d9db17537	1303	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	376:cb4d9db17537	1304	* the configuration information for SPI module.
mbed_official	376:cb4d9db17537	1305	* @param pData: pointer to data buffer
mbed_official	376:cb4d9db17537	1306	* @note When the CRC feature is enabled the pData Length must be Size + 1.
mbed_official	376:cb4d9db17537	1307	* @param Size: amount of data to be sent
mbed_official	376:cb4d9db17537	1308	* @retval HAL status
mbed_official	376:cb4d9db17537	1309	*/
mbed_official	376:cb4d9db17537	1310	HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
mbed_official	376:cb4d9db17537	1311	{
mbed_official	376:cb4d9db17537	1312	if(hspi->State == HAL_SPI_STATE_READY)
mbed_official	376:cb4d9db17537	1313	{
mbed_official	489:119543c9f674	1314	if((pData == NULL) \|\| (Size == 0))
mbed_official	376:cb4d9db17537	1315	{
mbed_official	489:119543c9f674	1316	/* Process Unlocked */
mbed_official	489:119543c9f674	1317	__HAL_UNLOCK(hspi);
mbed_official	376:cb4d9db17537	1318	return HAL_ERROR;
mbed_official	376:cb4d9db17537	1319	}
mbed_official	376:cb4d9db17537	1320
mbed_official	376:cb4d9db17537	1321	/* Process Locked */
mbed_official	376:cb4d9db17537	1322	__HAL_LOCK(hspi);
mbed_official	376:cb4d9db17537	1323
mbed_official	376:cb4d9db17537	1324	/* Configure communication */
mbed_official	376:cb4d9db17537	1325	hspi->State = HAL_SPI_STATE_BUSY_RX;
mbed_official	376:cb4d9db17537	1326	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official	376:cb4d9db17537	1327
mbed_official	489:119543c9f674	1328	hspi->pRxBuffPtr = (uint8_t*)pData;
mbed_official	376:cb4d9db17537	1329	hspi->RxXferSize = Size;
mbed_official	376:cb4d9db17537	1330	hspi->RxXferCount = Size;
mbed_official	376:cb4d9db17537	1331
mbed_official	376:cb4d9db17537	1332	/Init field not used in handle to zero /
mbed_official	489:119543c9f674	1333	hspi->RxISR = 0;
mbed_official	489:119543c9f674	1334	hspi->TxISR = 0;
mbed_official	489:119543c9f674	1335
mbed_official	489:119543c9f674	1336	hspi->pTxBuffPtr = NULL;
mbed_official	489:119543c9f674	1337	hspi->TxXferSize = 0;
mbed_official	489:119543c9f674	1338	hspi->TxXferCount = 0;
mbed_official	376:cb4d9db17537	1339
mbed_official	376:cb4d9db17537	1340	/* Configure communication direction : 1Line */
mbed_official	376:cb4d9db17537	1341	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
mbed_official	376:cb4d9db17537	1342	{
mbed_official	489:119543c9f674	1343	SPI_1LINE_RX(hspi);
mbed_official	376:cb4d9db17537	1344	}
mbed_official	376:cb4d9db17537	1345	else if((hspi->Init.Direction == SPI_DIRECTION_2LINES)&&(hspi->Init.Mode == SPI_MODE_MASTER))
mbed_official	376:cb4d9db17537	1346	{
mbed_official	489:119543c9f674	1347	/* Process Unlocked */
mbed_official	489:119543c9f674	1348	__HAL_UNLOCK(hspi);
mbed_official	376:cb4d9db17537	1349
mbed_official	489:119543c9f674	1350	/* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
mbed_official	489:119543c9f674	1351	return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size);
mbed_official	376:cb4d9db17537	1352	}
mbed_official	376:cb4d9db17537	1353
mbed_official	376:cb4d9db17537	1354	/* Reset CRC Calculation */
mbed_official	489:119543c9f674	1355	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official	376:cb4d9db17537	1356	{
mbed_official	489:119543c9f674	1357	SPI_RESET_CRC(hspi);
mbed_official	376:cb4d9db17537	1358	}
mbed_official	489:119543c9f674	1359
mbed_official	376:cb4d9db17537	1360	/* Set the SPI RxDMA Half transfer complete callback */
mbed_official	376:cb4d9db17537	1361	hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
mbed_official	489:119543c9f674	1362
mbed_official	376:cb4d9db17537	1363	/* Set the SPI Rx DMA transfer complete callback */
mbed_official	376:cb4d9db17537	1364	hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
mbed_official	376:cb4d9db17537	1365
mbed_official	376:cb4d9db17537	1366	/* Set the DMA error callback */
mbed_official	376:cb4d9db17537	1367	hspi->hdmarx->XferErrorCallback = SPI_DMAError;
mbed_official	376:cb4d9db17537	1368
mbed_official	489:119543c9f674	1369	/* Reset content of SPI TxDMA descriptor */
mbed_official	489:119543c9f674	1370	hspi->hdmatx->XferHalfCpltCallback = (void ()(DMA_HandleTypeDef ))NULL;
mbed_official	489:119543c9f674	1371	hspi->hdmatx->XferCpltCallback = (void ()(DMA_HandleTypeDef ))NULL;
mbed_official	489:119543c9f674	1372	hspi->hdmatx->XferErrorCallback = (void ()(DMA_HandleTypeDef ))NULL;
mbed_official	489:119543c9f674	1373
mbed_official	489:119543c9f674	1374	/* Enable the Rx DMA Channel */
mbed_official	376:cb4d9db17537	1375	HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
mbed_official	376:cb4d9db17537	1376
mbed_official	376:cb4d9db17537	1377	/* Enable Rx DMA Request */
mbed_official	489:119543c9f674	1378	SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
mbed_official	376:cb4d9db17537	1379
mbed_official	376:cb4d9db17537	1380	/* Process Unlocked */
mbed_official	376:cb4d9db17537	1381	__HAL_UNLOCK(hspi);
mbed_official	376:cb4d9db17537	1382
mbed_official	376:cb4d9db17537	1383	/* Check if the SPI is already enabled */
mbed_official	376:cb4d9db17537	1384	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official	376:cb4d9db17537	1385	{
mbed_official	376:cb4d9db17537	1386	/* Enable SPI peripheral */
mbed_official	376:cb4d9db17537	1387	__HAL_SPI_ENABLE(hspi);
mbed_official	376:cb4d9db17537	1388	}
mbed_official	376:cb4d9db17537	1389
mbed_official	376:cb4d9db17537	1390	return HAL_OK;
mbed_official	376:cb4d9db17537	1391	}
mbed_official	376:cb4d9db17537	1392	else
mbed_official	489:119543c9f674	1393	{
mbed_official	489:119543c9f674	1394	/* Process Unlocked */
mbed_official	489:119543c9f674	1395	__HAL_UNLOCK(hspi);
mbed_official	376:cb4d9db17537	1396	return HAL_BUSY;
mbed_official	376:cb4d9db17537	1397	}
mbed_official	376:cb4d9db17537	1398	}
mbed_official	376:cb4d9db17537	1399
mbed_official	376:cb4d9db17537	1400	/**
mbed_official	376:cb4d9db17537	1401	* @brief Transmit and Receive an amount of data in no-blocking mode with DMA
mbed_official	376:cb4d9db17537	1402	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	376:cb4d9db17537	1403	* the configuration information for SPI module.
mbed_official	376:cb4d9db17537	1404	* @param pTxData: pointer to transmission data buffer
mbed_official	376:cb4d9db17537	1405	* @param pRxData: pointer to reception data buffer
mbed_official	376:cb4d9db17537	1406	* @note When the CRC feature is enabled the pRxData Length must be Size + 1
mbed_official	376:cb4d9db17537	1407	* @param Size: amount of data to be sent
mbed_official	376:cb4d9db17537	1408	* @retval HAL status
mbed_official	376:cb4d9db17537	1409	*/
mbed_official	376:cb4d9db17537	1410	HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef hspi, uint8_t pTxData, uint8_t *pRxData, uint16_t Size)
mbed_official	376:cb4d9db17537	1411	{
mbed_official	489:119543c9f674	1412	if((hspi->State == HAL_SPI_STATE_READY) \|\| \
mbed_official	489:119543c9f674	1413	((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX)))
mbed_official	376:cb4d9db17537	1414	{
mbed_official	489:119543c9f674	1415	if((pTxData == NULL ) \|\| (pRxData == NULL ) \|\| (Size == 0))
mbed_official	376:cb4d9db17537	1416	{
mbed_official	376:cb4d9db17537	1417	return HAL_ERROR;
mbed_official	376:cb4d9db17537	1418	}
mbed_official	376:cb4d9db17537	1419
mbed_official	376:cb4d9db17537	1420	/* Check the parameters */
mbed_official	376:cb4d9db17537	1421	assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
mbed_official	376:cb4d9db17537	1422
mbed_official	376:cb4d9db17537	1423	/* Process locked */
mbed_official	376:cb4d9db17537	1424	__HAL_LOCK(hspi);
mbed_official	376:cb4d9db17537	1425
mbed_official	376:cb4d9db17537	1426	/* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
mbed_official	376:cb4d9db17537	1427	if(hspi->State != HAL_SPI_STATE_BUSY_RX)
mbed_official	376:cb4d9db17537	1428	{
mbed_official	376:cb4d9db17537	1429	hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
mbed_official	376:cb4d9db17537	1430	}
mbed_official	376:cb4d9db17537	1431
mbed_official	376:cb4d9db17537	1432	/* Configure communication */
mbed_official	376:cb4d9db17537	1433	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official	376:cb4d9db17537	1434
mbed_official	376:cb4d9db17537	1435	hspi->pTxBuffPtr = (uint8_t*)pTxData;
mbed_official	376:cb4d9db17537	1436	hspi->TxXferSize = Size;
mbed_official	376:cb4d9db17537	1437	hspi->TxXferCount = Size;
mbed_official	376:cb4d9db17537	1438
mbed_official	376:cb4d9db17537	1439	hspi->pRxBuffPtr = (uint8_t*)pRxData;
mbed_official	376:cb4d9db17537	1440	hspi->RxXferSize = Size;
mbed_official	376:cb4d9db17537	1441	hspi->RxXferCount = Size;
mbed_official	376:cb4d9db17537	1442
mbed_official	376:cb4d9db17537	1443	/Init field not used in handle to zero /
mbed_official	376:cb4d9db17537	1444	hspi->RxISR = 0;
mbed_official	376:cb4d9db17537	1445	hspi->TxISR = 0;
mbed_official	376:cb4d9db17537	1446
mbed_official	376:cb4d9db17537	1447	/* Reset CRC Calculation */
mbed_official	489:119543c9f674	1448	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official	376:cb4d9db17537	1449	{
mbed_official	489:119543c9f674	1450	SPI_RESET_CRC(hspi);
mbed_official	376:cb4d9db17537	1451	}
mbed_official	376:cb4d9db17537	1452
mbed_official	376:cb4d9db17537	1453	/* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */
mbed_official	376:cb4d9db17537	1454	if(hspi->State == HAL_SPI_STATE_BUSY_RX)
mbed_official	376:cb4d9db17537	1455	{
mbed_official	376:cb4d9db17537	1456	/* Set the SPI Rx DMA Half transfer complete callback */
mbed_official	376:cb4d9db17537	1457	hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
mbed_official	376:cb4d9db17537	1458
mbed_official	376:cb4d9db17537	1459	hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
mbed_official	376:cb4d9db17537	1460	}
mbed_official	376:cb4d9db17537	1461	else
mbed_official	376:cb4d9db17537	1462	{
mbed_official	376:cb4d9db17537	1463	/* Set the SPI Tx/Rx DMA Half transfer complete callback */
mbed_official	376:cb4d9db17537	1464	hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;
mbed_official	489:119543c9f674	1465
mbed_official	376:cb4d9db17537	1466	hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt;
mbed_official	376:cb4d9db17537	1467	}
mbed_official	376:cb4d9db17537	1468
mbed_official	376:cb4d9db17537	1469	/* Set the DMA error callback */
mbed_official	376:cb4d9db17537	1470	hspi->hdmarx->XferErrorCallback = SPI_DMAError;
mbed_official	376:cb4d9db17537	1471
mbed_official	489:119543c9f674	1472	/* Enable the Rx DMA Channel */
mbed_official	376:cb4d9db17537	1473	HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
mbed_official	376:cb4d9db17537	1474
mbed_official	376:cb4d9db17537	1475	/* Enable Rx DMA Request */
mbed_official	489:119543c9f674	1476	SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
mbed_official	376:cb4d9db17537	1477
mbed_official	489:119543c9f674	1478	/* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing
mbed_official	376:cb4d9db17537	1479	is performed in DMA reception complete callback */
mbed_official	489:119543c9f674	1480	hspi->hdmatx->XferHalfCpltCallback = (void ()(DMA_HandleTypeDef ))NULL;
mbed_official	489:119543c9f674	1481	hspi->hdmatx->XferCpltCallback = (void ()(DMA_HandleTypeDef ))NULL;
mbed_official	376:cb4d9db17537	1482
mbed_official	376:cb4d9db17537	1483	/* Set the DMA error callback */
mbed_official	489:119543c9f674	1484	hspi->hdmatx->XferErrorCallback = SPI_DMAError;
mbed_official	489:119543c9f674	1485
mbed_official	489:119543c9f674	1486	/* Enable the Tx DMA Channel */
mbed_official	376:cb4d9db17537	1487	HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
mbed_official	376:cb4d9db17537	1488
mbed_official	376:cb4d9db17537	1489	/* Check if the SPI is already enabled */
mbed_official	489:119543c9f674	1490	if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official	376:cb4d9db17537	1491	{
mbed_official	376:cb4d9db17537	1492	/* Enable SPI peripheral */
mbed_official	376:cb4d9db17537	1493	__HAL_SPI_ENABLE(hspi);
mbed_official	376:cb4d9db17537	1494	}
mbed_official	376:cb4d9db17537	1495
mbed_official	376:cb4d9db17537	1496	/* Enable Tx DMA Request */
mbed_official	489:119543c9f674	1497	SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
mbed_official	376:cb4d9db17537	1498
mbed_official	376:cb4d9db17537	1499	/* Process Unlocked */
mbed_official	376:cb4d9db17537	1500	__HAL_UNLOCK(hspi);
mbed_official	376:cb4d9db17537	1501
mbed_official	376:cb4d9db17537	1502	return HAL_OK;
mbed_official	376:cb4d9db17537	1503	}
mbed_official	376:cb4d9db17537	1504	else
mbed_official	376:cb4d9db17537	1505	{
mbed_official	376:cb4d9db17537	1506	return HAL_BUSY;
mbed_official	376:cb4d9db17537	1507	}
mbed_official	376:cb4d9db17537	1508	}
mbed_official	376:cb4d9db17537	1509
mbed_official	489:119543c9f674	1510
mbed_official	376:cb4d9db17537	1511	/**
mbed_official	376:cb4d9db17537	1512	* @brief Pauses the DMA Transfer.
mbed_official	376:cb4d9db17537	1513	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	376:cb4d9db17537	1514	* the configuration information for the specified SPI module.
mbed_official	376:cb4d9db17537	1515	* @retval HAL status
mbed_official	376:cb4d9db17537	1516	*/
mbed_official	376:cb4d9db17537	1517	HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi)
mbed_official	376:cb4d9db17537	1518	{
mbed_official	376:cb4d9db17537	1519	/* Process Locked */
mbed_official	376:cb4d9db17537	1520	__HAL_LOCK(hspi);
mbed_official	376:cb4d9db17537	1521
mbed_official	376:cb4d9db17537	1522	/* Disable the SPI DMA Tx & Rx requests */
mbed_official	489:119543c9f674	1523	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
mbed_official	489:119543c9f674	1524	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
mbed_official	376:cb4d9db17537	1525
mbed_official	376:cb4d9db17537	1526	/* Process Unlocked */
mbed_official	376:cb4d9db17537	1527	__HAL_UNLOCK(hspi);
mbed_official	376:cb4d9db17537	1528
mbed_official	376:cb4d9db17537	1529	return HAL_OK;
mbed_official	376:cb4d9db17537	1530	}
mbed_official	376:cb4d9db17537	1531
mbed_official	376:cb4d9db17537	1532	/**
mbed_official	376:cb4d9db17537	1533	* @brief Resumes the DMA Transfer.
mbed_official	376:cb4d9db17537	1534	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	376:cb4d9db17537	1535	* the configuration information for the specified SPI module.
mbed_official	376:cb4d9db17537	1536	* @retval HAL status
mbed_official	376:cb4d9db17537	1537	*/
mbed_official	376:cb4d9db17537	1538	HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi)
mbed_official	376:cb4d9db17537	1539	{
mbed_official	376:cb4d9db17537	1540	/* Process Locked */
mbed_official	376:cb4d9db17537	1541	__HAL_LOCK(hspi);
mbed_official	376:cb4d9db17537	1542
mbed_official	376:cb4d9db17537	1543	/* Enable the SPI DMA Tx & Rx requests */
mbed_official	489:119543c9f674	1544	SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
mbed_official	489:119543c9f674	1545	SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
mbed_official	376:cb4d9db17537	1546
mbed_official	376:cb4d9db17537	1547	/* Process Unlocked */
mbed_official	376:cb4d9db17537	1548	__HAL_UNLOCK(hspi);
mbed_official	376:cb4d9db17537	1549
mbed_official	376:cb4d9db17537	1550	return HAL_OK;
mbed_official	376:cb4d9db17537	1551	}
mbed_official	376:cb4d9db17537	1552
mbed_official	376:cb4d9db17537	1553	/**
mbed_official	376:cb4d9db17537	1554	* @brief Stops the DMA Transfer.
mbed_official	489:119543c9f674	1555	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	489:119543c9f674	1556	* the configuration information for the specified SPI module.
mbed_official	376:cb4d9db17537	1557	* @retval HAL status
mbed_official	376:cb4d9db17537	1558	*/
mbed_official	376:cb4d9db17537	1559	HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)
mbed_official	376:cb4d9db17537	1560	{
mbed_official	376:cb4d9db17537	1561	/* The Lock is not implemented on this API to allow the user application
mbed_official	376:cb4d9db17537	1562	to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback():
mbed_official	376:cb4d9db17537	1563	when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
mbed_official	376:cb4d9db17537	1564	and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback()
mbed_official	376:cb4d9db17537	1565	*/
mbed_official	376:cb4d9db17537	1566
mbed_official	489:119543c9f674	1567	/* Abort the SPI DMA tx Channel */
mbed_official	489:119543c9f674	1568	if(hspi->hdmatx != NULL)
mbed_official	376:cb4d9db17537	1569	{
mbed_official	376:cb4d9db17537	1570	HAL_DMA_Abort(hspi->hdmatx);
mbed_official	376:cb4d9db17537	1571	}
mbed_official	489:119543c9f674	1572	/* Abort the SPI DMA rx Channel */
mbed_official	489:119543c9f674	1573	if(hspi->hdmarx != NULL)
mbed_official	376:cb4d9db17537	1574	{
mbed_official	376:cb4d9db17537	1575	HAL_DMA_Abort(hspi->hdmarx);
mbed_official	376:cb4d9db17537	1576	}
mbed_official	376:cb4d9db17537	1577
mbed_official	376:cb4d9db17537	1578	/* Disable the SPI DMA Tx & Rx requests */
mbed_official	489:119543c9f674	1579	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
mbed_official	489:119543c9f674	1580	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
mbed_official	376:cb4d9db17537	1581
mbed_official	376:cb4d9db17537	1582	hspi->State = HAL_SPI_STATE_READY;
mbed_official	376:cb4d9db17537	1583
mbed_official	376:cb4d9db17537	1584	return HAL_OK;
mbed_official	376:cb4d9db17537	1585	}
mbed_official	376:cb4d9db17537	1586
mbed_official	376:cb4d9db17537	1587	/**
mbed_official	376:cb4d9db17537	1588	* @brief This function handles SPI interrupt request.
mbed_official	376:cb4d9db17537	1589	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	376:cb4d9db17537	1590	* the configuration information for SPI module.
mbed_official	376:cb4d9db17537	1591	* @retval HAL status
mbed_official	376:cb4d9db17537	1592	*/
mbed_official	376:cb4d9db17537	1593	void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
mbed_official	376:cb4d9db17537	1594	{
mbed_official	376:cb4d9db17537	1595	/* SPI in mode Receiver and Overrun not occurred ---------------------------*/
mbed_official	489:119543c9f674	1596	if((__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_RXNE) != RESET) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE) != RESET) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_OVR) == RESET))
mbed_official	376:cb4d9db17537	1597	{
mbed_official	376:cb4d9db17537	1598	hspi->RxISR(hspi);
mbed_official	376:cb4d9db17537	1599	return;
mbed_official	489:119543c9f674	1600	}
mbed_official	376:cb4d9db17537	1601
mbed_official	376:cb4d9db17537	1602	/* SPI in mode Tramitter ---------------------------------------------------*/
mbed_official	489:119543c9f674	1603	if((__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_TXE) != RESET) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE) != RESET))
mbed_official	376:cb4d9db17537	1604	{
mbed_official	376:cb4d9db17537	1605	hspi->TxISR(hspi);
mbed_official	376:cb4d9db17537	1606	return;
mbed_official	376:cb4d9db17537	1607	}
mbed_official	376:cb4d9db17537	1608
mbed_official	376:cb4d9db17537	1609	if(__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_ERR) != RESET)
mbed_official	376:cb4d9db17537	1610	{
mbed_official	489:119543c9f674	1611	/* SPI CRC error interrupt occurred ---------------------------------------*/
mbed_official	376:cb4d9db17537	1612	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
mbed_official	376:cb4d9db17537	1613	{
mbed_official	489:119543c9f674	1614	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
mbed_official	376:cb4d9db17537	1615	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
mbed_official	376:cb4d9db17537	1616	}
mbed_official	489:119543c9f674	1617	/* SPI Mode Fault error interrupt occurred --------------------------------*/
mbed_official	376:cb4d9db17537	1618	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_MODF) != RESET)
mbed_official	376:cb4d9db17537	1619	{
mbed_official	489:119543c9f674	1620	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF);
mbed_official	376:cb4d9db17537	1621	__HAL_SPI_CLEAR_MODFFLAG(hspi);
mbed_official	376:cb4d9db17537	1622	}
mbed_official	376:cb4d9db17537	1623
mbed_official	489:119543c9f674	1624	/* SPI Overrun error interrupt occurred -----------------------------------*/
mbed_official	376:cb4d9db17537	1625	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_OVR) != RESET)
mbed_official	376:cb4d9db17537	1626	{
mbed_official	376:cb4d9db17537	1627	if(hspi->State != HAL_SPI_STATE_BUSY_TX)
mbed_official	376:cb4d9db17537	1628	{
mbed_official	489:119543c9f674	1629	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR);
mbed_official	376:cb4d9db17537	1630	__HAL_SPI_CLEAR_OVRFLAG(hspi);
mbed_official	376:cb4d9db17537	1631	}
mbed_official	376:cb4d9db17537	1632	}
mbed_official	376:cb4d9db17537	1633
mbed_official	489:119543c9f674	1634	/* SPI Frame error interrupt occurred -------------------------------------*/
mbed_official	376:cb4d9db17537	1635	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_FRE) != RESET)
mbed_official	376:cb4d9db17537	1636	{
mbed_official	489:119543c9f674	1637	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FRE);
mbed_official	376:cb4d9db17537	1638	__HAL_SPI_CLEAR_FREFLAG(hspi);
mbed_official	376:cb4d9db17537	1639	}
mbed_official	376:cb4d9db17537	1640
mbed_official	376:cb4d9db17537	1641	/* Call the Error call Back in case of Errors */
mbed_official	376:cb4d9db17537	1642	if(hspi->ErrorCode!=HAL_SPI_ERROR_NONE)
mbed_official	376:cb4d9db17537	1643	{
mbed_official	489:119543c9f674	1644	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE \| SPI_IT_TXE \| SPI_IT_ERR);
mbed_official	376:cb4d9db17537	1645	hspi->State = HAL_SPI_STATE_READY;
mbed_official	376:cb4d9db17537	1646	HAL_SPI_ErrorCallback(hspi);
mbed_official	376:cb4d9db17537	1647	}
mbed_official	376:cb4d9db17537	1648	}
mbed_official	376:cb4d9db17537	1649	}
mbed_official	376:cb4d9db17537	1650
mbed_official	376:cb4d9db17537	1651	/**
mbed_official	376:cb4d9db17537	1652	* @brief Tx Transfer completed callbacks
mbed_official	376:cb4d9db17537	1653	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	376:cb4d9db17537	1654	* the configuration information for SPI module.
mbed_official	376:cb4d9db17537	1655	* @retval None
mbed_official	376:cb4d9db17537	1656	*/
mbed_official	376:cb4d9db17537	1657	__weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
mbed_official	376:cb4d9db17537	1658	{
mbed_official	376:cb4d9db17537	1659	/* NOTE : This function Should not be modified, when the callback is needed,
mbed_official	376:cb4d9db17537	1660	the HAL_SPI_TxCpltCallback could be implenetd in the user file
mbed_official	376:cb4d9db17537	1661	*/
mbed_official	376:cb4d9db17537	1662	}
mbed_official	376:cb4d9db17537	1663
mbed_official	376:cb4d9db17537	1664	/**
mbed_official	376:cb4d9db17537	1665	* @brief Rx Transfer completed callbacks
mbed_official	376:cb4d9db17537	1666	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	376:cb4d9db17537	1667	* the configuration information for SPI module.
mbed_official	376:cb4d9db17537	1668	* @retval None
mbed_official	376:cb4d9db17537	1669	*/
mbed_official	376:cb4d9db17537	1670	__weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
mbed_official	376:cb4d9db17537	1671	{
mbed_official	376:cb4d9db17537	1672	/* NOTE : This function Should not be modified, when the callback is needed,
mbed_official	376:cb4d9db17537	1673	the HAL_SPI_RxCpltCallback() could be implenetd in the user file
mbed_official	376:cb4d9db17537	1674	*/
mbed_official	376:cb4d9db17537	1675	}
mbed_official	376:cb4d9db17537	1676
mbed_official	376:cb4d9db17537	1677	/**
mbed_official	376:cb4d9db17537	1678	* @brief Tx and Rx Transfer completed callbacks
mbed_official	376:cb4d9db17537	1679	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	376:cb4d9db17537	1680	* the configuration information for SPI module.
mbed_official	376:cb4d9db17537	1681	* @retval None
mbed_official	376:cb4d9db17537	1682	*/
mbed_official	376:cb4d9db17537	1683	__weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
mbed_official	376:cb4d9db17537	1684	{
mbed_official	376:cb4d9db17537	1685	/* NOTE : This function Should not be modified, when the callback is needed,
mbed_official	376:cb4d9db17537	1686	the HAL_SPI_TxRxCpltCallback() could be implenetd in the user file
mbed_official	376:cb4d9db17537	1687	*/
mbed_official	376:cb4d9db17537	1688	}
mbed_official	376:cb4d9db17537	1689
mbed_official	376:cb4d9db17537	1690	/**
mbed_official	376:cb4d9db17537	1691	* @brief Tx Half Transfer completed callbacks
mbed_official	376:cb4d9db17537	1692	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	376:cb4d9db17537	1693	* the configuration information for SPI module.
mbed_official	376:cb4d9db17537	1694	* @retval None
mbed_official	376:cb4d9db17537	1695	*/
mbed_official	376:cb4d9db17537	1696	__weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)
mbed_official	376:cb4d9db17537	1697	{
mbed_official	376:cb4d9db17537	1698	/* NOTE : This function Should not be modified, when the callback is needed,
mbed_official	376:cb4d9db17537	1699	the HAL_SPI_TxHalfCpltCallback could be implenetd in the user file
mbed_official	376:cb4d9db17537	1700	*/
mbed_official	376:cb4d9db17537	1701	}
mbed_official	376:cb4d9db17537	1702
mbed_official	376:cb4d9db17537	1703	/**
mbed_official	376:cb4d9db17537	1704	* @brief Rx Half Transfer completed callbacks
mbed_official	376:cb4d9db17537	1705	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	376:cb4d9db17537	1706	* the configuration information for SPI module.
mbed_official	376:cb4d9db17537	1707	* @retval None
mbed_official	376:cb4d9db17537	1708	*/
mbed_official	376:cb4d9db17537	1709	__weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)
mbed_official	376:cb4d9db17537	1710	{
mbed_official	376:cb4d9db17537	1711	/* NOTE : This function Should not be modified, when the callback is needed,
mbed_official	376:cb4d9db17537	1712	the HAL_SPI_RxHalfCpltCallback() could be implenetd in the user file
mbed_official	376:cb4d9db17537	1713	*/
mbed_official	376:cb4d9db17537	1714	}
mbed_official	376:cb4d9db17537	1715
mbed_official	376:cb4d9db17537	1716	/**
mbed_official	376:cb4d9db17537	1717	* @brief Tx and Rx Transfer completed callbacks
mbed_official	376:cb4d9db17537	1718	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	376:cb4d9db17537	1719	* the configuration information for SPI module.
mbed_official	376:cb4d9db17537	1720	* @retval None
mbed_official	376:cb4d9db17537	1721	*/
mbed_official	376:cb4d9db17537	1722	__weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
mbed_official	376:cb4d9db17537	1723	{
mbed_official	376:cb4d9db17537	1724	/* NOTE : This function Should not be modified, when the callback is needed,
mbed_official	376:cb4d9db17537	1725	the HAL_SPI_TxRxHalfCpltCallback() could be implenetd in the user file
mbed_official	376:cb4d9db17537	1726	*/
mbed_official	376:cb4d9db17537	1727	}
mbed_official	376:cb4d9db17537	1728
mbed_official	376:cb4d9db17537	1729	/**
mbed_official	376:cb4d9db17537	1730	* @brief SPI error callbacks
mbed_official	376:cb4d9db17537	1731	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	376:cb4d9db17537	1732	* the configuration information for SPI module.
mbed_official	376:cb4d9db17537	1733	* @retval None
mbed_official	376:cb4d9db17537	1734	*/
mbed_official	376:cb4d9db17537	1735	__weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
mbed_official	376:cb4d9db17537	1736	{
mbed_official	376:cb4d9db17537	1737	/* NOTE : - This function Should not be modified, when the callback is needed,
mbed_official	376:cb4d9db17537	1738	the HAL_SPI_ErrorCallback() could be implenetd in the user file.
mbed_official	376:cb4d9db17537	1739	- The ErrorCode parameter in the hspi handle is updated by the SPI processes
mbed_official	489:119543c9f674	1740	and user can use HAL_SPI_GetError() API to check the latest error occurred.
mbed_official	376:cb4d9db17537	1741	*/
mbed_official	376:cb4d9db17537	1742	}
mbed_official	376:cb4d9db17537	1743
mbed_official	376:cb4d9db17537	1744	/**
mbed_official	376:cb4d9db17537	1745	* @}
mbed_official	376:cb4d9db17537	1746	*/
mbed_official	376:cb4d9db17537	1747
mbed_official	489:119543c9f674	1748	/** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions
mbed_official	376:cb4d9db17537	1749	* @brief SPI control functions
mbed_official	376:cb4d9db17537	1750	*
mbed_official	376:cb4d9db17537	1751	@verbatim
mbed_official	376:cb4d9db17537	1752	===============================================================================
mbed_official	376:cb4d9db17537	1753	##### Peripheral State and Errors functions #####
mbed_official	376:cb4d9db17537	1754	===============================================================================
mbed_official	376:cb4d9db17537	1755	[..]
mbed_official	376:cb4d9db17537	1756	This subsection provides a set of functions allowing to control the SPI.
mbed_official	376:cb4d9db17537	1757	(+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral
mbed_official	376:cb4d9db17537	1758	(+) HAL_SPI_GetError() check in run-time Errors occurring during communication
mbed_official	376:cb4d9db17537	1759	@endverbatim
mbed_official	376:cb4d9db17537	1760	* @{
mbed_official	376:cb4d9db17537	1761	*/
mbed_official	376:cb4d9db17537	1762
mbed_official	376:cb4d9db17537	1763	/**
mbed_official	376:cb4d9db17537	1764	* @brief Return the SPI state
mbed_official	489:119543c9f674	1765	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	489:119543c9f674	1766	* the configuration information for SPI module.
mbed_official	376:cb4d9db17537	1767	* @retval SPI state
mbed_official	376:cb4d9db17537	1768	*/
mbed_official	376:cb4d9db17537	1769	HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
mbed_official	376:cb4d9db17537	1770	{
mbed_official	376:cb4d9db17537	1771	return hspi->State;
mbed_official	376:cb4d9db17537	1772	}
mbed_official	376:cb4d9db17537	1773
mbed_official	376:cb4d9db17537	1774	/**
mbed_official	376:cb4d9db17537	1775	* @brief Return the SPI error code
mbed_official	489:119543c9f674	1776	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	489:119543c9f674	1777	* the configuration information for SPI module.
mbed_official	376:cb4d9db17537	1778	* @retval SPI Error Code
mbed_official	376:cb4d9db17537	1779	*/
mbed_official	489:119543c9f674	1780	uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
mbed_official	376:cb4d9db17537	1781	{
mbed_official	376:cb4d9db17537	1782	return hspi->ErrorCode;
mbed_official	376:cb4d9db17537	1783	}
mbed_official	376:cb4d9db17537	1784
mbed_official	376:cb4d9db17537	1785	/**
mbed_official	376:cb4d9db17537	1786	* @}
mbed_official	376:cb4d9db17537	1787	*/
mbed_official	489:119543c9f674	1788
mbed_official	489:119543c9f674	1789	/**
mbed_official	489:119543c9f674	1790	* @}
mbed_official	489:119543c9f674	1791	*/
mbed_official	489:119543c9f674	1792
mbed_official	489:119543c9f674	1793
mbed_official	489:119543c9f674	1794
mbed_official	489:119543c9f674	1795	/** @addtogroup SPI_Private_Functions
mbed_official	489:119543c9f674	1796	* @{
mbed_official	489:119543c9f674	1797	*/
mbed_official	489:119543c9f674	1798
mbed_official	376:cb4d9db17537	1799
mbed_official	376:cb4d9db17537	1800	/**
mbed_official	376:cb4d9db17537	1801	* @brief Interrupt Handler to close Tx transfer
mbed_official	376:cb4d9db17537	1802	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	376:cb4d9db17537	1803	* the configuration information for SPI module.
mbed_official	376:cb4d9db17537	1804	* @retval void
mbed_official	376:cb4d9db17537	1805	*/
mbed_official	376:cb4d9db17537	1806	static void SPI_TxCloseIRQHandler(SPI_HandleTypeDef *hspi)
mbed_official	376:cb4d9db17537	1807	{
mbed_official	376:cb4d9db17537	1808	/* Wait until TXE flag is set to send data */
mbed_official	376:cb4d9db17537	1809	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
mbed_official	376:cb4d9db17537	1810	{
mbed_official	489:119543c9f674	1811	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
mbed_official	376:cb4d9db17537	1812	}
mbed_official	376:cb4d9db17537	1813
mbed_official	376:cb4d9db17537	1814	/* Disable TXE interrupt */
mbed_official	489:119543c9f674	1815	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE));
mbed_official	376:cb4d9db17537	1816
mbed_official	376:cb4d9db17537	1817	/* Disable ERR interrupt if Receive process is finished */
mbed_official	376:cb4d9db17537	1818	if(__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_RXNE) == RESET)
mbed_official	376:cb4d9db17537	1819	{
mbed_official	489:119543c9f674	1820	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_ERR));
mbed_official	376:cb4d9db17537	1821
mbed_official	376:cb4d9db17537	1822	/* Wait until Busy flag is reset before disabling SPI */
mbed_official	376:cb4d9db17537	1823	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
mbed_official	376:cb4d9db17537	1824	{
mbed_official	489:119543c9f674	1825	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
mbed_official	376:cb4d9db17537	1826	}
mbed_official	376:cb4d9db17537	1827
mbed_official	376:cb4d9db17537	1828	/* Clear OVERUN flag in 2 Lines communication mode because received is not read */
mbed_official	376:cb4d9db17537	1829	if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
mbed_official	376:cb4d9db17537	1830	{
mbed_official	376:cb4d9db17537	1831	__HAL_SPI_CLEAR_OVRFLAG(hspi);
mbed_official	376:cb4d9db17537	1832	}
mbed_official	376:cb4d9db17537	1833
mbed_official	376:cb4d9db17537	1834	/* Check if Errors has been detected during transfer */
mbed_official	376:cb4d9db17537	1835	if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
mbed_official	376:cb4d9db17537	1836	{
mbed_official	376:cb4d9db17537	1837	/* Check if we are in Tx or in Rx/Tx Mode */
mbed_official	376:cb4d9db17537	1838	if(hspi->State == HAL_SPI_STATE_BUSY_TX_RX)
mbed_official	376:cb4d9db17537	1839	{
mbed_official	376:cb4d9db17537	1840	/* Set state to READY before run the Callback Complete */
mbed_official	376:cb4d9db17537	1841	hspi->State = HAL_SPI_STATE_READY;
mbed_official	376:cb4d9db17537	1842	HAL_SPI_TxRxCpltCallback(hspi);
mbed_official	376:cb4d9db17537	1843	}
mbed_official	376:cb4d9db17537	1844	else
mbed_official	376:cb4d9db17537	1845	{
mbed_official	376:cb4d9db17537	1846	/* Set state to READY before run the Callback Complete */
mbed_official	376:cb4d9db17537	1847	hspi->State = HAL_SPI_STATE_READY;
mbed_official	376:cb4d9db17537	1848	HAL_SPI_TxCpltCallback(hspi);
mbed_official	376:cb4d9db17537	1849	}
mbed_official	376:cb4d9db17537	1850	}
mbed_official	376:cb4d9db17537	1851	else
mbed_official	376:cb4d9db17537	1852	{
mbed_official	376:cb4d9db17537	1853	/* Set state to READY before run the Callback Complete */
mbed_official	376:cb4d9db17537	1854	hspi->State = HAL_SPI_STATE_READY;
mbed_official	376:cb4d9db17537	1855	/* Call Error call back in case of Error */
mbed_official	376:cb4d9db17537	1856	HAL_SPI_ErrorCallback(hspi);
mbed_official	376:cb4d9db17537	1857	}
mbed_official	376:cb4d9db17537	1858	}
mbed_official	376:cb4d9db17537	1859	}
mbed_official	376:cb4d9db17537	1860
mbed_official	376:cb4d9db17537	1861	/**
mbed_official	376:cb4d9db17537	1862	* @brief Interrupt Handler to transmit amount of data in no-blocking mode
mbed_official	376:cb4d9db17537	1863	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	376:cb4d9db17537	1864	* the configuration information for SPI module.
mbed_official	376:cb4d9db17537	1865	* @retval void
mbed_official	376:cb4d9db17537	1866	*/
mbed_official	376:cb4d9db17537	1867	static void SPI_TxISR(SPI_HandleTypeDef *hspi)
mbed_official	376:cb4d9db17537	1868	{
mbed_official	376:cb4d9db17537	1869	/* Transmit data in 8 Bit mode */
mbed_official	376:cb4d9db17537	1870	if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
mbed_official	376:cb4d9db17537	1871	{
mbed_official	376:cb4d9db17537	1872	hspi->Instance->DR = (*hspi->pTxBuffPtr++);
mbed_official	376:cb4d9db17537	1873	}
mbed_official	376:cb4d9db17537	1874	/* Transmit data in 16 Bit mode */
mbed_official	376:cb4d9db17537	1875	else
mbed_official	376:cb4d9db17537	1876	{
mbed_official	376:cb4d9db17537	1877	hspi->Instance->DR = ((uint16_t)hspi->pTxBuffPtr);
mbed_official	376:cb4d9db17537	1878	hspi->pTxBuffPtr+=2;
mbed_official	376:cb4d9db17537	1879	}
mbed_official	376:cb4d9db17537	1880	hspi->TxXferCount--;
mbed_official	376:cb4d9db17537	1881
mbed_official	376:cb4d9db17537	1882	if(hspi->TxXferCount == 0)
mbed_official	376:cb4d9db17537	1883	{
mbed_official	489:119543c9f674	1884	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official	376:cb4d9db17537	1885	{
mbed_official	376:cb4d9db17537	1886	/* calculate and transfer CRC on Tx line */
mbed_official	489:119543c9f674	1887	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
mbed_official	376:cb4d9db17537	1888	}
mbed_official	376:cb4d9db17537	1889	SPI_TxCloseIRQHandler(hspi);
mbed_official	376:cb4d9db17537	1890	}
mbed_official	376:cb4d9db17537	1891	}
mbed_official	376:cb4d9db17537	1892
mbed_official	376:cb4d9db17537	1893	/**
mbed_official	376:cb4d9db17537	1894	* @brief Interrupt Handler to close Rx transfer
mbed_official	376:cb4d9db17537	1895	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	376:cb4d9db17537	1896	* the configuration information for SPI module.
mbed_official	376:cb4d9db17537	1897	* @retval void
mbed_official	376:cb4d9db17537	1898	*/
mbed_official	376:cb4d9db17537	1899	static void SPI_RxCloseIRQHandler(SPI_HandleTypeDef *hspi)
mbed_official	376:cb4d9db17537	1900	{
mbed_official	489:119543c9f674	1901	__IO uint16_t tmpreg = 0;
mbed_official	376:cb4d9db17537	1902
mbed_official	489:119543c9f674	1903	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official	376:cb4d9db17537	1904	{
mbed_official	489:119543c9f674	1905	/* Wait until RXNE flag is set to read CRC data */
mbed_official	376:cb4d9db17537	1906	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
mbed_official	376:cb4d9db17537	1907	{
mbed_official	489:119543c9f674	1908	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
mbed_official	376:cb4d9db17537	1909	}
mbed_official	376:cb4d9db17537	1910
mbed_official	376:cb4d9db17537	1911	/* Read CRC to reset RXNE flag */
mbed_official	376:cb4d9db17537	1912	tmpreg = hspi->Instance->DR;
mbed_official	489:119543c9f674	1913	UNUSED(tmpreg); /* avoid warning on tmpreg affectation with some compiler */
mbed_official	376:cb4d9db17537	1914
mbed_official	489:119543c9f674	1915	/* Wait until RXNE flag is reset */
mbed_official	376:cb4d9db17537	1916	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
mbed_official	376:cb4d9db17537	1917	{
mbed_official	489:119543c9f674	1918	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
mbed_official	376:cb4d9db17537	1919	}
mbed_official	376:cb4d9db17537	1920
mbed_official	376:cb4d9db17537	1921	/* Check if CRC error occurred */
mbed_official	376:cb4d9db17537	1922	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
mbed_official	376:cb4d9db17537	1923	{
mbed_official	489:119543c9f674	1924	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
mbed_official	376:cb4d9db17537	1925
mbed_official	376:cb4d9db17537	1926	/* Reset CRC Calculation */
mbed_official	489:119543c9f674	1927	SPI_RESET_CRC(hspi);
mbed_official	376:cb4d9db17537	1928	}
mbed_official	376:cb4d9db17537	1929	}
mbed_official	376:cb4d9db17537	1930
mbed_official	489:119543c9f674	1931	/* Disable RXNE interrupt */
mbed_official	489:119543c9f674	1932	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE));
mbed_official	376:cb4d9db17537	1933
mbed_official	376:cb4d9db17537	1934	/* if Transmit process is finished */
mbed_official	376:cb4d9db17537	1935	if(__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_TXE) == RESET)
mbed_official	376:cb4d9db17537	1936	{
mbed_official	376:cb4d9db17537	1937	/* Disable ERR interrupt */
mbed_official	489:119543c9f674	1938	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_ERR));
mbed_official	376:cb4d9db17537	1939
mbed_official	376:cb4d9db17537	1940	if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)\|\|(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
mbed_official	376:cb4d9db17537	1941	{
mbed_official	376:cb4d9db17537	1942	/* Disable SPI peripheral */
mbed_official	376:cb4d9db17537	1943	__HAL_SPI_DISABLE(hspi);
mbed_official	376:cb4d9db17537	1944	}
mbed_official	376:cb4d9db17537	1945
mbed_official	376:cb4d9db17537	1946	/* Check if Errors has been detected during transfer */
mbed_official	376:cb4d9db17537	1947	if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
mbed_official	376:cb4d9db17537	1948	{
mbed_official	376:cb4d9db17537	1949	/* Check if we are in Rx or in Rx/Tx Mode */
mbed_official	376:cb4d9db17537	1950	if(hspi->State == HAL_SPI_STATE_BUSY_TX_RX)
mbed_official	376:cb4d9db17537	1951	{
mbed_official	376:cb4d9db17537	1952	/* Set state to READY before run the Callback Complete */
mbed_official	376:cb4d9db17537	1953	hspi->State = HAL_SPI_STATE_READY;
mbed_official	376:cb4d9db17537	1954	HAL_SPI_TxRxCpltCallback(hspi);
mbed_official	376:cb4d9db17537	1955	}
mbed_official	376:cb4d9db17537	1956	else
mbed_official	376:cb4d9db17537	1957	{
mbed_official	376:cb4d9db17537	1958	/* Set state to READY before run the Callback Complete */
mbed_official	376:cb4d9db17537	1959	hspi->State = HAL_SPI_STATE_READY;
mbed_official	376:cb4d9db17537	1960	HAL_SPI_RxCpltCallback(hspi);
mbed_official	376:cb4d9db17537	1961	}
mbed_official	376:cb4d9db17537	1962	}
mbed_official	376:cb4d9db17537	1963	else
mbed_official	376:cb4d9db17537	1964	{
mbed_official	376:cb4d9db17537	1965	/* Set state to READY before run the Callback Complete */
mbed_official	376:cb4d9db17537	1966	hspi->State = HAL_SPI_STATE_READY;
mbed_official	376:cb4d9db17537	1967	/* Call Error call back in case of Error */
mbed_official	376:cb4d9db17537	1968	HAL_SPI_ErrorCallback(hspi);
mbed_official	376:cb4d9db17537	1969	}
mbed_official	376:cb4d9db17537	1970	}
mbed_official	376:cb4d9db17537	1971	}
mbed_official	376:cb4d9db17537	1972
mbed_official	376:cb4d9db17537	1973	/**
mbed_official	376:cb4d9db17537	1974	* @brief Interrupt Handler to receive amount of data in 2Lines mode
mbed_official	376:cb4d9db17537	1975	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	376:cb4d9db17537	1976	* the configuration information for SPI module.
mbed_official	376:cb4d9db17537	1977	* @retval void
mbed_official	376:cb4d9db17537	1978	*/
mbed_official	376:cb4d9db17537	1979	static void SPI_2LinesRxISR(SPI_HandleTypeDef *hspi)
mbed_official	376:cb4d9db17537	1980	{
mbed_official	376:cb4d9db17537	1981	/* Receive data in 8 Bit mode */
mbed_official	376:cb4d9db17537	1982	if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
mbed_official	376:cb4d9db17537	1983	{
mbed_official	376:cb4d9db17537	1984	(*hspi->pRxBuffPtr++) = hspi->Instance->DR;
mbed_official	376:cb4d9db17537	1985	}
mbed_official	376:cb4d9db17537	1986	/* Receive data in 16 Bit mode */
mbed_official	376:cb4d9db17537	1987	else
mbed_official	376:cb4d9db17537	1988	{
mbed_official	376:cb4d9db17537	1989	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
mbed_official	376:cb4d9db17537	1990	hspi->pRxBuffPtr+=2;
mbed_official	376:cb4d9db17537	1991	}
mbed_official	376:cb4d9db17537	1992	hspi->RxXferCount--;
mbed_official	376:cb4d9db17537	1993
mbed_official	376:cb4d9db17537	1994	if(hspi->RxXferCount==0)
mbed_official	376:cb4d9db17537	1995	{
mbed_official	376:cb4d9db17537	1996	SPI_RxCloseIRQHandler(hspi);
mbed_official	376:cb4d9db17537	1997	}
mbed_official	376:cb4d9db17537	1998	}
mbed_official	376:cb4d9db17537	1999
mbed_official	376:cb4d9db17537	2000	/**
mbed_official	376:cb4d9db17537	2001	* @brief Interrupt Handler to receive amount of data in no-blocking mode
mbed_official	376:cb4d9db17537	2002	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	376:cb4d9db17537	2003	* the configuration information for SPI module.
mbed_official	376:cb4d9db17537	2004	* @retval void
mbed_official	376:cb4d9db17537	2005	*/
mbed_official	376:cb4d9db17537	2006	static void SPI_RxISR(SPI_HandleTypeDef *hspi)
mbed_official	376:cb4d9db17537	2007	{
mbed_official	376:cb4d9db17537	2008	/* Receive data in 8 Bit mode */
mbed_official	376:cb4d9db17537	2009	if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
mbed_official	376:cb4d9db17537	2010	{
mbed_official	376:cb4d9db17537	2011	(*hspi->pRxBuffPtr++) = hspi->Instance->DR;
mbed_official	376:cb4d9db17537	2012	}
mbed_official	376:cb4d9db17537	2013	/* Receive data in 16 Bit mode */
mbed_official	376:cb4d9db17537	2014	else
mbed_official	376:cb4d9db17537	2015	{
mbed_official	376:cb4d9db17537	2016	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
mbed_official	376:cb4d9db17537	2017	hspi->pRxBuffPtr+=2;
mbed_official	376:cb4d9db17537	2018	}
mbed_official	376:cb4d9db17537	2019	hspi->RxXferCount--;
mbed_official	376:cb4d9db17537	2020
mbed_official	376:cb4d9db17537	2021	/* Enable CRC Transmission */
mbed_official	489:119543c9f674	2022	if((hspi->RxXferCount == 1) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
mbed_official	376:cb4d9db17537	2023	{
mbed_official	376:cb4d9db17537	2024	/* Set CRC Next to calculate CRC on Rx side */
mbed_official	489:119543c9f674	2025	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
mbed_official	376:cb4d9db17537	2026	}
mbed_official	376:cb4d9db17537	2027
mbed_official	376:cb4d9db17537	2028	if(hspi->RxXferCount == 0)
mbed_official	376:cb4d9db17537	2029	{
mbed_official	376:cb4d9db17537	2030	SPI_RxCloseIRQHandler(hspi);
mbed_official	376:cb4d9db17537	2031	}
mbed_official	376:cb4d9db17537	2032	}
mbed_official	376:cb4d9db17537	2033
mbed_official	376:cb4d9db17537	2034	/**
mbed_official	376:cb4d9db17537	2035	* @brief DMA SPI transmit process complete callback
mbed_official	376:cb4d9db17537	2036	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
mbed_official	376:cb4d9db17537	2037	* the configuration information for the specified DMA module.
mbed_official	376:cb4d9db17537	2038	* @retval None
mbed_official	376:cb4d9db17537	2039	*/
mbed_official	376:cb4d9db17537	2040	static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
mbed_official	376:cb4d9db17537	2041	{
mbed_official	376:cb4d9db17537	2042	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official	376:cb4d9db17537	2043
mbed_official	376:cb4d9db17537	2044
mbed_official	376:cb4d9db17537	2045	/* DMA Normal Mode */
mbed_official	376:cb4d9db17537	2046	if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0)
mbed_official	376:cb4d9db17537	2047	{
mbed_official	376:cb4d9db17537	2048	/* Wait until TXE flag is set to send data */
mbed_official	376:cb4d9db17537	2049	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
mbed_official	376:cb4d9db17537	2050	{
mbed_official	489:119543c9f674	2051	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
mbed_official	376:cb4d9db17537	2052	}
mbed_official	489:119543c9f674	2053
mbed_official	376:cb4d9db17537	2054	/* Disable Tx DMA Request */
mbed_official	489:119543c9f674	2055	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
mbed_official	376:cb4d9db17537	2056
mbed_official	376:cb4d9db17537	2057	/* Wait until Busy flag is reset before disabling SPI */
mbed_official	376:cb4d9db17537	2058	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
mbed_official	376:cb4d9db17537	2059	{
mbed_official	489:119543c9f674	2060	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
mbed_official	376:cb4d9db17537	2061	}
mbed_official	376:cb4d9db17537	2062
mbed_official	376:cb4d9db17537	2063	hspi->TxXferCount = 0;
mbed_official	376:cb4d9db17537	2064	hspi->State = HAL_SPI_STATE_READY;
mbed_official	376:cb4d9db17537	2065	}
mbed_official	376:cb4d9db17537	2066
mbed_official	376:cb4d9db17537	2067	/* Clear OVERUN flag in 2 Lines communication mode because received is not read */
mbed_official	376:cb4d9db17537	2068	if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
mbed_official	376:cb4d9db17537	2069	{
mbed_official	489:119543c9f674	2070	__HAL_SPI_CLEAR_OVRFLAG(hspi);
mbed_official	376:cb4d9db17537	2071	}
mbed_official	376:cb4d9db17537	2072
mbed_official	376:cb4d9db17537	2073	/* Check if Errors has been detected during transfer */
mbed_official	376:cb4d9db17537	2074	if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
mbed_official	376:cb4d9db17537	2075	{
mbed_official	376:cb4d9db17537	2076	HAL_SPI_ErrorCallback(hspi);
mbed_official	376:cb4d9db17537	2077	}
mbed_official	376:cb4d9db17537	2078	else
mbed_official	376:cb4d9db17537	2079	{
mbed_official	376:cb4d9db17537	2080	HAL_SPI_TxCpltCallback(hspi);
mbed_official	376:cb4d9db17537	2081	}
mbed_official	376:cb4d9db17537	2082	}
mbed_official	376:cb4d9db17537	2083
mbed_official	376:cb4d9db17537	2084	/**
mbed_official	376:cb4d9db17537	2085	* @brief DMA SPI receive process complete callback
mbed_official	376:cb4d9db17537	2086	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
mbed_official	376:cb4d9db17537	2087	* the configuration information for the specified DMA module.
mbed_official	376:cb4d9db17537	2088	* @retval None
mbed_official	376:cb4d9db17537	2089	*/
mbed_official	376:cb4d9db17537	2090	static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
mbed_official	376:cb4d9db17537	2091	{
mbed_official	489:119543c9f674	2092	__IO uint16_t tmpreg = 0;
mbed_official	376:cb4d9db17537	2093
mbed_official	376:cb4d9db17537	2094	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official	489:119543c9f674	2095
mbed_official	376:cb4d9db17537	2096	/* DMA Normal mode */
mbed_official	376:cb4d9db17537	2097	if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0)
mbed_official	376:cb4d9db17537	2098	{
mbed_official	489:119543c9f674	2099	/* Disable Rx DMA Request */
mbed_official	489:119543c9f674	2100	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
mbed_official	489:119543c9f674	2101
mbed_official	489:119543c9f674	2102	/* Disable Tx DMA Request (done by default to handle the case Master RX direction 2 lines) */
mbed_official	489:119543c9f674	2103	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
mbed_official	489:119543c9f674	2104
mbed_official	489:119543c9f674	2105	/* CRC Calculation handling */
mbed_official	489:119543c9f674	2106	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official	489:119543c9f674	2107	{
mbed_official	489:119543c9f674	2108	/* Wait until RXNE flag is set (CRC ready) */
mbed_official	489:119543c9f674	2109	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
mbed_official	489:119543c9f674	2110	{
mbed_official	489:119543c9f674	2111	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
mbed_official	489:119543c9f674	2112	}
mbed_official	489:119543c9f674	2113
mbed_official	489:119543c9f674	2114	/* Read CRC */
mbed_official	489:119543c9f674	2115	tmpreg = hspi->Instance->DR;
mbed_official	489:119543c9f674	2116	UNUSED(tmpreg); /* avoid warning on tmpreg affectation with some compiler */
mbed_official	489:119543c9f674	2117
mbed_official	489:119543c9f674	2118	/* Wait until RXNE flag is reset */
mbed_official	489:119543c9f674	2119	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
mbed_official	489:119543c9f674	2120	{
mbed_official	489:119543c9f674	2121	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
mbed_official	489:119543c9f674	2122	}
mbed_official	489:119543c9f674	2123
mbed_official	489:119543c9f674	2124	/* Check if CRC error occurred */
mbed_official	489:119543c9f674	2125	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
mbed_official	489:119543c9f674	2126	{
mbed_official	489:119543c9f674	2127	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
mbed_official	489:119543c9f674	2128	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
mbed_official	489:119543c9f674	2129	}
mbed_official	489:119543c9f674	2130	}
mbed_official	489:119543c9f674	2131
mbed_official	376:cb4d9db17537	2132	if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)\|\|(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
mbed_official	376:cb4d9db17537	2133	{
mbed_official	376:cb4d9db17537	2134	/* Disable SPI peripheral */
mbed_official	376:cb4d9db17537	2135	__HAL_SPI_DISABLE(hspi);
mbed_official	376:cb4d9db17537	2136	}
mbed_official	376:cb4d9db17537	2137
mbed_official	376:cb4d9db17537	2138	hspi->RxXferCount = 0;
mbed_official	376:cb4d9db17537	2139	hspi->State = HAL_SPI_STATE_READY;
mbed_official	376:cb4d9db17537	2140
mbed_official	376:cb4d9db17537	2141	/* Check if Errors has been detected during transfer */
mbed_official	376:cb4d9db17537	2142	if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
mbed_official	376:cb4d9db17537	2143	{
mbed_official	376:cb4d9db17537	2144	HAL_SPI_ErrorCallback(hspi);
mbed_official	376:cb4d9db17537	2145	}
mbed_official	376:cb4d9db17537	2146	else
mbed_official	376:cb4d9db17537	2147	{
mbed_official	376:cb4d9db17537	2148	HAL_SPI_RxCpltCallback(hspi);
mbed_official	376:cb4d9db17537	2149	}
mbed_official	376:cb4d9db17537	2150	}
mbed_official	376:cb4d9db17537	2151	else
mbed_official	376:cb4d9db17537	2152	{
mbed_official	376:cb4d9db17537	2153	HAL_SPI_RxCpltCallback(hspi);
mbed_official	489:119543c9f674	2154	}
mbed_official	376:cb4d9db17537	2155	}
mbed_official	376:cb4d9db17537	2156
mbed_official	376:cb4d9db17537	2157	/**
mbed_official	376:cb4d9db17537	2158	* @brief DMA SPI transmit receive process complete callback
mbed_official	376:cb4d9db17537	2159	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
mbed_official	376:cb4d9db17537	2160	* the configuration information for the specified DMA module.
mbed_official	376:cb4d9db17537	2161	* @retval None
mbed_official	376:cb4d9db17537	2162	*/
mbed_official	376:cb4d9db17537	2163	static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
mbed_official	376:cb4d9db17537	2164	{
mbed_official	489:119543c9f674	2165	__IO uint16_t tmpreg = 0;
mbed_official	376:cb4d9db17537	2166
mbed_official	376:cb4d9db17537	2167	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official	376:cb4d9db17537	2168	if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0)
mbed_official	376:cb4d9db17537	2169	{
mbed_official	489:119543c9f674	2170	/* CRC Calculation handling */
mbed_official	489:119543c9f674	2171	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official	376:cb4d9db17537	2172	{
mbed_official	376:cb4d9db17537	2173	/* Check if CRC is done on going (RXNE flag set) */
mbed_official	376:cb4d9db17537	2174	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) == HAL_OK)
mbed_official	376:cb4d9db17537	2175	{
mbed_official	376:cb4d9db17537	2176	/* Wait until RXNE flag is set to send data */
mbed_official	376:cb4d9db17537	2177	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
mbed_official	376:cb4d9db17537	2178	{
mbed_official	489:119543c9f674	2179	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
mbed_official	376:cb4d9db17537	2180	}
mbed_official	376:cb4d9db17537	2181	}
mbed_official	376:cb4d9db17537	2182	/* Read CRC */
mbed_official	376:cb4d9db17537	2183	tmpreg = hspi->Instance->DR;
mbed_official	489:119543c9f674	2184	UNUSED(tmpreg); /* avoid warning on tmpreg affectation with some compiler */
mbed_official	376:cb4d9db17537	2185
mbed_official	376:cb4d9db17537	2186	/* Check if CRC error occurred */
mbed_official	376:cb4d9db17537	2187	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
mbed_official	376:cb4d9db17537	2188	{
mbed_official	489:119543c9f674	2189	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
mbed_official	376:cb4d9db17537	2190	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
mbed_official	376:cb4d9db17537	2191	}
mbed_official	376:cb4d9db17537	2192	}
mbed_official	489:119543c9f674	2193
mbed_official	376:cb4d9db17537	2194	/* Wait until TXE flag is set to send data */
mbed_official	376:cb4d9db17537	2195	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
mbed_official	376:cb4d9db17537	2196	{
mbed_official	489:119543c9f674	2197	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
mbed_official	376:cb4d9db17537	2198	}
mbed_official	376:cb4d9db17537	2199
mbed_official	376:cb4d9db17537	2200	/* Disable Tx DMA Request */
mbed_official	489:119543c9f674	2201	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
mbed_official	376:cb4d9db17537	2202
mbed_official	376:cb4d9db17537	2203	/* Wait until Busy flag is reset before disabling SPI */
mbed_official	376:cb4d9db17537	2204	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
mbed_official	376:cb4d9db17537	2205	{
mbed_official	489:119543c9f674	2206	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
mbed_official	376:cb4d9db17537	2207	}
mbed_official	376:cb4d9db17537	2208
mbed_official	376:cb4d9db17537	2209	/* Disable Rx DMA Request */
mbed_official	489:119543c9f674	2210	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
mbed_official	376:cb4d9db17537	2211
mbed_official	376:cb4d9db17537	2212	hspi->TxXferCount = 0;
mbed_official	376:cb4d9db17537	2213	hspi->RxXferCount = 0;
mbed_official	376:cb4d9db17537	2214
mbed_official	376:cb4d9db17537	2215	hspi->State = HAL_SPI_STATE_READY;
mbed_official	376:cb4d9db17537	2216
mbed_official	376:cb4d9db17537	2217	/* Check if Errors has been detected during transfer */
mbed_official	376:cb4d9db17537	2218	if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
mbed_official	376:cb4d9db17537	2219	{
mbed_official	376:cb4d9db17537	2220	HAL_SPI_ErrorCallback(hspi);
mbed_official	376:cb4d9db17537	2221	}
mbed_official	376:cb4d9db17537	2222	else
mbed_official	376:cb4d9db17537	2223	{
mbed_official	376:cb4d9db17537	2224	HAL_SPI_TxRxCpltCallback(hspi);
mbed_official	376:cb4d9db17537	2225	}
mbed_official	376:cb4d9db17537	2226	}
mbed_official	376:cb4d9db17537	2227	else
mbed_official	376:cb4d9db17537	2228	{
mbed_official	376:cb4d9db17537	2229	HAL_SPI_TxRxCpltCallback(hspi);
mbed_official	376:cb4d9db17537	2230	}
mbed_official	376:cb4d9db17537	2231	}
mbed_official	376:cb4d9db17537	2232
mbed_official	376:cb4d9db17537	2233	/**
mbed_official	376:cb4d9db17537	2234	* @brief DMA SPI half transmit process complete callback
mbed_official	376:cb4d9db17537	2235	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
mbed_official	376:cb4d9db17537	2236	* the configuration information for the specified DMA module.
mbed_official	376:cb4d9db17537	2237	* @retval None
mbed_official	376:cb4d9db17537	2238	*/
mbed_official	376:cb4d9db17537	2239	static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)
mbed_official	376:cb4d9db17537	2240	{
mbed_official	376:cb4d9db17537	2241	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official	376:cb4d9db17537	2242
mbed_official	376:cb4d9db17537	2243	HAL_SPI_TxHalfCpltCallback(hspi);
mbed_official	376:cb4d9db17537	2244	}
mbed_official	376:cb4d9db17537	2245
mbed_official	376:cb4d9db17537	2246	/**
mbed_official	376:cb4d9db17537	2247	* @brief DMA SPI half receive process complete callback
mbed_official	376:cb4d9db17537	2248	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
mbed_official	376:cb4d9db17537	2249	* the configuration information for the specified DMA module.
mbed_official	376:cb4d9db17537	2250	* @retval None
mbed_official	376:cb4d9db17537	2251	*/
mbed_official	376:cb4d9db17537	2252	static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)
mbed_official	376:cb4d9db17537	2253	{
mbed_official	376:cb4d9db17537	2254	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official	376:cb4d9db17537	2255
mbed_official	376:cb4d9db17537	2256	HAL_SPI_RxHalfCpltCallback(hspi);
mbed_official	376:cb4d9db17537	2257	}
mbed_official	376:cb4d9db17537	2258
mbed_official	376:cb4d9db17537	2259	/**
mbed_official	376:cb4d9db17537	2260	* @brief DMA SPI Half transmit receive process complete callback
mbed_official	376:cb4d9db17537	2261	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
mbed_official	376:cb4d9db17537	2262	* the configuration information for the specified DMA module.
mbed_official	376:cb4d9db17537	2263	* @retval None
mbed_official	376:cb4d9db17537	2264	*/
mbed_official	376:cb4d9db17537	2265	static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)
mbed_official	376:cb4d9db17537	2266	{
mbed_official	376:cb4d9db17537	2267	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official	376:cb4d9db17537	2268
mbed_official	376:cb4d9db17537	2269	HAL_SPI_TxRxHalfCpltCallback(hspi);
mbed_official	376:cb4d9db17537	2270	}
mbed_official	376:cb4d9db17537	2271
mbed_official	376:cb4d9db17537	2272	/**
mbed_official	376:cb4d9db17537	2273	* @brief DMA SPI communication error callback
mbed_official	376:cb4d9db17537	2274	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
mbed_official	376:cb4d9db17537	2275	* the configuration information for the specified DMA module.
mbed_official	376:cb4d9db17537	2276	* @retval None
mbed_official	376:cb4d9db17537	2277	*/
mbed_official	376:cb4d9db17537	2278	static void SPI_DMAError(DMA_HandleTypeDef *hdma)
mbed_official	376:cb4d9db17537	2279	{
mbed_official	376:cb4d9db17537	2280	SPI_HandleTypeDef* hspi = (SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official	376:cb4d9db17537	2281	hspi->TxXferCount = 0;
mbed_official	376:cb4d9db17537	2282	hspi->RxXferCount = 0;
mbed_official	376:cb4d9db17537	2283	hspi->State= HAL_SPI_STATE_READY;
mbed_official	489:119543c9f674	2284	SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
mbed_official	376:cb4d9db17537	2285	HAL_SPI_ErrorCallback(hspi);
mbed_official	376:cb4d9db17537	2286	}
mbed_official	376:cb4d9db17537	2287
mbed_official	376:cb4d9db17537	2288	/**
mbed_official	489:119543c9f674	2289	* @brief This function handles SPI Communication Timeout.
mbed_official	376:cb4d9db17537	2290	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	376:cb4d9db17537	2291	* the configuration information for SPI module.
mbed_official	489:119543c9f674	2292	* @param Flag: SPI flag to check
mbed_official	489:119543c9f674	2293	* @param Status: Flag status to check: RESET or set
mbed_official	489:119543c9f674	2294	* @param Timeout: Timeout duration
mbed_official	376:cb4d9db17537	2295	* @retval HAL status
mbed_official	376:cb4d9db17537	2296	*/
mbed_official	376:cb4d9db17537	2297	static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
mbed_official	376:cb4d9db17537	2298	{
mbed_official	489:119543c9f674	2299	uint32_t tickstart = 0;
mbed_official	489:119543c9f674	2300
mbed_official	489:119543c9f674	2301	/* Get tick */
mbed_official	376:cb4d9db17537	2302	tickstart = HAL_GetTick();
mbed_official	376:cb4d9db17537	2303
mbed_official	376:cb4d9db17537	2304	/* Wait until flag is set */
mbed_official	376:cb4d9db17537	2305	if(Status == RESET)
mbed_official	376:cb4d9db17537	2306	{
mbed_official	376:cb4d9db17537	2307	while(__HAL_SPI_GET_FLAG(hspi, Flag) == RESET)
mbed_official	376:cb4d9db17537	2308	{
mbed_official	376:cb4d9db17537	2309	if(Timeout != HAL_MAX_DELAY)
mbed_official	376:cb4d9db17537	2310	{
mbed_official	489:119543c9f674	2311	if((Timeout == 0) \|\| ((HAL_GetTick() - tickstart ) > Timeout))
mbed_official	376:cb4d9db17537	2312	{
mbed_official	376:cb4d9db17537	2313	/* Disable the SPI and reset the CRC: the CRC value should be cleared
mbed_official	376:cb4d9db17537	2314	on both master and slave sides in order to resynchronize the master
mbed_official	376:cb4d9db17537	2315	and slave for their respective CRC calculation */
mbed_official	376:cb4d9db17537	2316
mbed_official	376:cb4d9db17537	2317	/* Disable TXE, RXNE and ERR interrupts for the interrupt process */
mbed_official	376:cb4d9db17537	2318	__HAL_SPI_DISABLE_IT(hspi, (uint32_t)(SPI_IT_TXE \| SPI_IT_RXNE \| SPI_IT_ERR));
mbed_official	376:cb4d9db17537	2319
mbed_official	376:cb4d9db17537	2320	/* Disable SPI peripheral */
mbed_official	376:cb4d9db17537	2321	__HAL_SPI_DISABLE(hspi);
mbed_official	376:cb4d9db17537	2322
mbed_official	376:cb4d9db17537	2323	/* Reset CRC Calculation */
mbed_official	489:119543c9f674	2324	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official	376:cb4d9db17537	2325	{
mbed_official	489:119543c9f674	2326	SPI_RESET_CRC(hspi);
mbed_official	376:cb4d9db17537	2327	}
mbed_official	376:cb4d9db17537	2328
mbed_official	376:cb4d9db17537	2329	hspi->State= HAL_SPI_STATE_READY;
mbed_official	376:cb4d9db17537	2330
mbed_official	376:cb4d9db17537	2331	/* Process Unlocked */
mbed_official	376:cb4d9db17537	2332	__HAL_UNLOCK(hspi);
mbed_official	376:cb4d9db17537	2333
mbed_official	376:cb4d9db17537	2334	return HAL_TIMEOUT;
mbed_official	376:cb4d9db17537	2335	}
mbed_official	376:cb4d9db17537	2336	}
mbed_official	376:cb4d9db17537	2337	}
mbed_official	376:cb4d9db17537	2338	}
mbed_official	376:cb4d9db17537	2339	else
mbed_official	376:cb4d9db17537	2340	{
mbed_official	376:cb4d9db17537	2341	while(__HAL_SPI_GET_FLAG(hspi, Flag) != RESET)
mbed_official	376:cb4d9db17537	2342	{
mbed_official	376:cb4d9db17537	2343	if(Timeout != HAL_MAX_DELAY)
mbed_official	376:cb4d9db17537	2344	{
mbed_official	489:119543c9f674	2345	if((Timeout == 0) \|\| ((HAL_GetTick() - tickstart ) > Timeout))
mbed_official	376:cb4d9db17537	2346	{
mbed_official	376:cb4d9db17537	2347	/* Disable the SPI and reset the CRC: the CRC value should be cleared
mbed_official	376:cb4d9db17537	2348	on both master and slave sides in order to resynchronize the master
mbed_official	376:cb4d9db17537	2349	and slave for their respective CRC calculation */
mbed_official	376:cb4d9db17537	2350
mbed_official	376:cb4d9db17537	2351	/* Disable TXE, RXNE and ERR interrupts for the interrupt process */
mbed_official	376:cb4d9db17537	2352	__HAL_SPI_DISABLE_IT(hspi, (uint32_t)(SPI_IT_TXE \| SPI_IT_RXNE \| SPI_IT_ERR));
mbed_official	376:cb4d9db17537	2353
mbed_official	376:cb4d9db17537	2354	/* Disable SPI peripheral */
mbed_official	376:cb4d9db17537	2355	__HAL_SPI_DISABLE(hspi);
mbed_official	376:cb4d9db17537	2356
mbed_official	376:cb4d9db17537	2357	/* Reset CRC Calculation */
mbed_official	489:119543c9f674	2358	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official	376:cb4d9db17537	2359	{
mbed_official	489:119543c9f674	2360	SPI_RESET_CRC(hspi);
mbed_official	376:cb4d9db17537	2361	}
mbed_official	376:cb4d9db17537	2362
mbed_official	376:cb4d9db17537	2363	hspi->State= HAL_SPI_STATE_READY;
mbed_official	376:cb4d9db17537	2364
mbed_official	376:cb4d9db17537	2365	/* Process Unlocked */
mbed_official	376:cb4d9db17537	2366	__HAL_UNLOCK(hspi);
mbed_official	376:cb4d9db17537	2367
mbed_official	376:cb4d9db17537	2368	return HAL_TIMEOUT;
mbed_official	376:cb4d9db17537	2369	}
mbed_official	376:cb4d9db17537	2370	}
mbed_official	376:cb4d9db17537	2371	}
mbed_official	376:cb4d9db17537	2372	}
mbed_official	376:cb4d9db17537	2373	return HAL_OK;
mbed_official	376:cb4d9db17537	2374	}
mbed_official	376:cb4d9db17537	2375	/**
mbed_official	376:cb4d9db17537	2376	* @}
mbed_official	376:cb4d9db17537	2377	*/
mbed_official	376:cb4d9db17537	2378
mbed_official	376:cb4d9db17537	2379	#endif /* HAL_SPI_MODULE_ENABLED */
mbed_official	376:cb4d9db17537	2380	/**
mbed_official	376:cb4d9db17537	2381	* @}
mbed_official	376:cb4d9db17537	2382	*/
mbed_official	376:cb4d9db17537	2383
mbed_official	376:cb4d9db17537	2384	/**
mbed_official	376:cb4d9db17537	2385	* @}
mbed_official	376:cb4d9db17537	2386	*/
mbed_official	376:cb4d9db17537	2387
mbed_official	376:cb4d9db17537	2388	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/
mbed_official	489:119543c9f674	2389