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targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_rcc_ex.h@579:53297373a894, 2015-07-01 (annotated)

Committer:: mbed_official
Date:: Wed Jul 01 09:45:11 2015 +0100
Revision:: 579:53297373a894
Parent:: 489:119543c9f674

Synchronized with git revision d5b4d2ab9c47edb4dc5776e7177b0c2263459081

Full URL: https://github.com/mbedmicro/mbed/commit/d5b4d2ab9c47edb4dc5776e7177b0c2263459081/

Initial version of drivers for SAMR21

Who changed what in which revision?

User	Revision	Line number	New contents of line
mbed_official	376:cb4d9db17537	1	/**
mbed_official	376:cb4d9db17537	2	******************************************************************************
mbed_official	376:cb4d9db17537	3	* @file stm32l0xx_hal_rcc_ex.h
mbed_official	376:cb4d9db17537	4	* @author MCD Application Team
mbed_official	489:119543c9f674	5	* @version V1.2.0
mbed_official	489:119543c9f674	6	* @date 06-February-2015
mbed_official	376:cb4d9db17537	7	* @brief Header file of RCC HAL Extension module.
mbed_official	376:cb4d9db17537	8	******************************************************************************
mbed_official	376:cb4d9db17537	9	* @attention
mbed_official	376:cb4d9db17537	10	*
mbed_official	489:119543c9f674	11	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
mbed_official	376:cb4d9db17537	12	*
mbed_official	376:cb4d9db17537	13	* Redistribution and use in source and binary forms, with or without modification,
mbed_official	376:cb4d9db17537	14	* are permitted provided that the following conditions are met:
mbed_official	376:cb4d9db17537	15	* 1. Redistributions of source code must retain the above copyright notice,
mbed_official	376:cb4d9db17537	16	* this list of conditions and the following disclaimer.
mbed_official	376:cb4d9db17537	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official	376:cb4d9db17537	18	* this list of conditions and the following disclaimer in the documentation
mbed_official	376:cb4d9db17537	19	* and/or other materials provided with the distribution.
mbed_official	376:cb4d9db17537	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official	376:cb4d9db17537	21	* may be used to endorse or promote products derived from this software
mbed_official	376:cb4d9db17537	22	* without specific prior written permission.
mbed_official	376:cb4d9db17537	23	*
mbed_official	376:cb4d9db17537	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official	376:cb4d9db17537	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official	376:cb4d9db17537	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official	376:cb4d9db17537	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official	376:cb4d9db17537	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official	376:cb4d9db17537	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official	376:cb4d9db17537	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official	376:cb4d9db17537	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official	376:cb4d9db17537	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official	376:cb4d9db17537	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official	376:cb4d9db17537	34	*
mbed_official	376:cb4d9db17537	35	******************************************************************************
mbed_official	376:cb4d9db17537	36	*/
mbed_official	376:cb4d9db17537	37
mbed_official	376:cb4d9db17537	38	/* Define to prevent recursive inclusion -------------------------------------*/
mbed_official	376:cb4d9db17537	39	#ifndef __STM32L0xx_HAL_RCC_EX_H
mbed_official	376:cb4d9db17537	40	#define __STM32L0xx_HAL_RCC_EX_H
mbed_official	376:cb4d9db17537	41
mbed_official	376:cb4d9db17537	42	#ifdef __cplusplus
mbed_official	376:cb4d9db17537	43	extern "C" {
mbed_official	376:cb4d9db17537	44	#endif
mbed_official	376:cb4d9db17537	45
mbed_official	376:cb4d9db17537	46	/* Includes ------------------------------------------------------------------*/
mbed_official	376:cb4d9db17537	47	#include "stm32l0xx_hal_def.h"
mbed_official	376:cb4d9db17537	48
mbed_official	376:cb4d9db17537	49	/** @addtogroup STM32L0xx_HAL_Driver
mbed_official	376:cb4d9db17537	50	* @{
mbed_official	376:cb4d9db17537	51	*/
mbed_official	376:cb4d9db17537	52
mbed_official	489:119543c9f674	53	/** @defgroup RCCEx
mbed_official	376:cb4d9db17537	54	* @{
mbed_official	376:cb4d9db17537	55	*/
mbed_official	376:cb4d9db17537	56
mbed_official	376:cb4d9db17537	57	/* Exported types ------------------------------------------------------------*/
mbed_official	376:cb4d9db17537	58	/**
mbed_official	376:cb4d9db17537	59	* @brief RCC extended clocks structure definition
mbed_official	376:cb4d9db17537	60	*/
mbed_official	489:119543c9f674	61	#if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
mbed_official	376:cb4d9db17537	62	typedef struct
mbed_official	376:cb4d9db17537	63	{
mbed_official	376:cb4d9db17537	64	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
mbed_official	376:cb4d9db17537	65	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
mbed_official	376:cb4d9db17537	66	uint32_t Usart1ClockSelection; /*!< USART1 clock source
mbed_official	376:cb4d9db17537	67	This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
mbed_official	376:cb4d9db17537	68
mbed_official	376:cb4d9db17537	69	uint32_t Usart2ClockSelection; /*!< USART2 clock source
mbed_official	376:cb4d9db17537	70	This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
mbed_official	376:cb4d9db17537	71
mbed_official	376:cb4d9db17537	72	uint32_t Lpuart1ClockSelection; /*!< LPUART1 clock source
mbed_official	376:cb4d9db17537	73	This parameter can be a value of @ref RCCEx_LPUART_Clock_Source */
mbed_official	376:cb4d9db17537	74
mbed_official	376:cb4d9db17537	75	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
mbed_official	376:cb4d9db17537	76	This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */
mbed_official	489:119543c9f674	77	#if defined (STM32L072xx) \|\| defined(STM32L073xx) \|\| defined(STM32L082xx) \|\| defined(STM32L083xx)
mbed_official	489:119543c9f674	78	uint32_t I2c3ClockSelection; /*!< I2C3 clock source
mbed_official	489:119543c9f674	79	This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
mbed_official	489:119543c9f674	80	#endif
mbed_official	376:cb4d9db17537	81
mbed_official	376:cb4d9db17537	82	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
mbed_official	489:119543c9f674	83	This parameter can be a value of @ref RCC_RTC_Clock_Source */
mbed_official	489:119543c9f674	84	#if defined (STM32L053xx) \|\| defined(STM32L063xx) \|\| defined(STM32L073xx) \|\| defined(STM32L083xx)
mbed_official	489:119543c9f674	85	uint32_t LCDClockSelection; /*!< specifies the LCD clock source.
mbed_official	489:119543c9f674	86	This parameter can be a value of @ref RCC_RTC_Clock_Source */
mbed_official	489:119543c9f674	87	#endif
mbed_official	376:cb4d9db17537	88
mbed_official	376:cb4d9db17537	89	uint32_t UsbClockSelection; /*!< Specifies USB and RNG Clock Selection
mbed_official	376:cb4d9db17537	90	This parameter can be a value of @ref RCCEx_USB_Clock_Source */
mbed_official	376:cb4d9db17537	91
mbed_official	376:cb4d9db17537	92	uint32_t LptimClockSelection; /*!< LPTIM1 clock source
mbed_official	376:cb4d9db17537	93	This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */
mbed_official	376:cb4d9db17537	94
mbed_official	376:cb4d9db17537	95	}RCC_PeriphCLKInitTypeDef;
mbed_official	489:119543c9f674	96
mbed_official	376:cb4d9db17537	97
mbed_official	489:119543c9f674	98	#else /* !(STM32L031xx) && !(STM32L041xx) && !(STM32L051xx) && !(STM32L061xx) && !(STM32L071xx) && !(STM32L081xx) */
mbed_official	489:119543c9f674	99
mbed_official	376:cb4d9db17537	100	typedef struct
mbed_official	376:cb4d9db17537	101	{
mbed_official	376:cb4d9db17537	102	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
mbed_official	376:cb4d9db17537	103	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
mbed_official	489:119543c9f674	104	#if !defined (STM32L031xx) && !defined (STM32L041xx)
mbed_official	376:cb4d9db17537	105	uint32_t Usart1ClockSelection; /*!< USART1 clock source
mbed_official	376:cb4d9db17537	106	This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
mbed_official	489:119543c9f674	107	#endif
mbed_official	376:cb4d9db17537	108	uint32_t Usart2ClockSelection; /*!< USART2 clock source
mbed_official	376:cb4d9db17537	109	This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
mbed_official	376:cb4d9db17537	110
mbed_official	376:cb4d9db17537	111	uint32_t Lpuart1ClockSelection; /*!< LPUART1 clock source
mbed_official	376:cb4d9db17537	112	This parameter can be a value of @ref RCCEx_LPUART1_Clock_Source */
mbed_official	376:cb4d9db17537	113
mbed_official	376:cb4d9db17537	114	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
mbed_official	376:cb4d9db17537	115	This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */
mbed_official	376:cb4d9db17537	116
mbed_official	489:119543c9f674	117	#if defined (STM32L071xx) \|\| defined(STM32L081xx)
mbed_official	489:119543c9f674	118	uint32_t I2c3ClockSelection; /*!< I2C3 clock source
mbed_official	489:119543c9f674	119	This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
mbed_official	489:119543c9f674	120	#endif
mbed_official	489:119543c9f674	121
mbed_official	376:cb4d9db17537	122	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
mbed_official	489:119543c9f674	123	This parameter can be a value of @ref RCC_RTC_Clock_Source */
mbed_official	376:cb4d9db17537	124
mbed_official	376:cb4d9db17537	125	uint32_t LptimClockSelection; /*!< LPTIM1 clock source
mbed_official	376:cb4d9db17537	126	This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */
mbed_official	376:cb4d9db17537	127
mbed_official	376:cb4d9db17537	128	}RCC_PeriphCLKInitTypeDef;
mbed_official	489:119543c9f674	129
mbed_official	489:119543c9f674	130	#endif /* STM32L0x1xx */
mbed_official	489:119543c9f674	131
mbed_official	376:cb4d9db17537	132
mbed_official	489:119543c9f674	133	#if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
mbed_official	489:119543c9f674	134	/** @defgroup RCCEx_Exported_Constants
mbed_official	489:119543c9f674	135	* @{
mbed_official	489:119543c9f674	136	*/
mbed_official	376:cb4d9db17537	137	/**
mbed_official	489:119543c9f674	138	* @brief RCC CRS Status definition
mbed_official	376:cb4d9db17537	139	*/
mbed_official	376:cb4d9db17537	140
mbed_official	489:119543c9f674	141	#define RCC_CRS_NONE ((uint32_t) 0x00000000)
mbed_official	489:119543c9f674	142	#define RCC_CRS_TIMEOUT ((uint32_t) 0x00000001)
mbed_official	489:119543c9f674	143	#define RCC_CRS_SYNCOK ((uint32_t) 0x00000002)
mbed_official	489:119543c9f674	144	#define RCC_CRS_SYNCWARM ((uint32_t) 0x00000004)
mbed_official	489:119543c9f674	145	#define RCC_CRS_SYNCERR ((uint32_t) 0x00000008)
mbed_official	489:119543c9f674	146	#define RCC_CRS_SYNCMISS ((uint32_t) 0x00000010)
mbed_official	489:119543c9f674	147	#define RCC_CRS_TRIMOV ((uint32_t) 0x00000020)
mbed_official	489:119543c9f674	148
mbed_official	489:119543c9f674	149	/**
mbed_official	489:119543c9f674	150	* @}
mbed_official	489:119543c9f674	151	*/
mbed_official	376:cb4d9db17537	152	/**
mbed_official	376:cb4d9db17537	153	* @brief RCC_CRS Init structure definition
mbed_official	376:cb4d9db17537	154	*/
mbed_official	376:cb4d9db17537	155	typedef struct
mbed_official	376:cb4d9db17537	156	{
mbed_official	376:cb4d9db17537	157	uint32_t Prescaler; /*!< Specifies the division factor of the SYNC signal.
mbed_official	376:cb4d9db17537	158	This parameter can be a value of @ref RCCEx_CRS_SynchroDivider */
mbed_official	376:cb4d9db17537	159
mbed_official	376:cb4d9db17537	160	uint32_t Source; /*!< Specifies the SYNC signal source.
mbed_official	376:cb4d9db17537	161	This parameter can be a value of @ref RCCEx_CRS_SynchroSource */
mbed_official	376:cb4d9db17537	162
mbed_official	376:cb4d9db17537	163	uint32_t Polarity; /*!< Specifies the input polarity for the SYNC signal source.
mbed_official	376:cb4d9db17537	164	This parameter can be a value of @ref RCCEx_CRS_SynchroPolarity */
mbed_official	376:cb4d9db17537	165
mbed_official	376:cb4d9db17537	166	uint32_t ReloadValue; /*!< Specifies the value to be loaded in the frequency error counter with each SYNC event.
mbed_official	376:cb4d9db17537	167	It can be calculated in using macro __HAL_RCC_CRS_CALCULATE_RELOADVALUE(_FTARGET_, _FSYNC_)
mbed_official	376:cb4d9db17537	168	This parameter must be a number between 0 and 0xFFFF or a value of @ref RCCEx_CRS_ReloadValueDefault .*/
mbed_official	376:cb4d9db17537	169
mbed_official	376:cb4d9db17537	170	uint32_t ErrorLimitValue; /*!< Specifies the value to be used to evaluate the captured frequency error value.
mbed_official	376:cb4d9db17537	171	This parameter must be a number between 0 and 0xFF or a value of @ref RCCEx_CRS_ErrorLimitDefault */
mbed_official	376:cb4d9db17537	172
mbed_official	376:cb4d9db17537	173	uint32_t HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value to the HSI48 oscillator.
mbed_official	376:cb4d9db17537	174	This parameter must be a number between 0 and 0x3F or a value of @ref RCCEx_CRS_HSI48CalibrationDefault */
mbed_official	376:cb4d9db17537	175
mbed_official	376:cb4d9db17537	176	}RCC_CRSInitTypeDef;
mbed_official	376:cb4d9db17537	177
mbed_official	376:cb4d9db17537	178	/**
mbed_official	376:cb4d9db17537	179	* @brief RCC_CRS Synchronization structure definition
mbed_official	376:cb4d9db17537	180	*/
mbed_official	376:cb4d9db17537	181	typedef struct
mbed_official	376:cb4d9db17537	182	{
mbed_official	376:cb4d9db17537	183	uint32_t ReloadValue; /*!< Specifies the value loaded in the Counter reload value.
mbed_official	376:cb4d9db17537	184	This parameter must be a number between 0 and 0xFFFF*/
mbed_official	376:cb4d9db17537	185
mbed_official	376:cb4d9db17537	186	uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48 oscillator smooth trimming.
mbed_official	376:cb4d9db17537	187	This parameter must be a number between 0 and 0x3F */
mbed_official	376:cb4d9db17537	188
mbed_official	376:cb4d9db17537	189	uint32_t FreqErrorCapture; /*!< Specifies the value loaded in the .FECAP, the frequency error counter
mbed_official	376:cb4d9db17537	190	value latched in the time of the last SYNC event.
mbed_official	376:cb4d9db17537	191	This parameter must be a number between 0 and 0xFFFF */
mbed_official	376:cb4d9db17537	192
mbed_official	376:cb4d9db17537	193	uint32_t FreqErrorDirection; /*!< Specifies the value loaded in the .FEDIR, the counting direction of the
mbed_official	376:cb4d9db17537	194	frequency error counter latched in the time of the last SYNC event.
mbed_official	376:cb4d9db17537	195	It shows whether the actual frequency is below or above the target.
mbed_official	376:cb4d9db17537	196	This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/
mbed_official	376:cb4d9db17537	197
mbed_official	376:cb4d9db17537	198	}RCC_CRSSynchroInfoTypeDef;
mbed_official	489:119543c9f674	199	#endif /* !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
mbed_official	376:cb4d9db17537	200
mbed_official	376:cb4d9db17537	201	/* Exported constants --------------------------------------------------------*/
mbed_official	489:119543c9f674	202	/** @addtogroup RCCEx_Exported_Constants
mbed_official	376:cb4d9db17537	203	* @{
mbed_official	376:cb4d9db17537	204	*/
mbed_official	376:cb4d9db17537	205
mbed_official	376:cb4d9db17537	206	/** @defgroup RCCEx_Periph_Clock_Selection
mbed_official	376:cb4d9db17537	207	* @{
mbed_official	376:cb4d9db17537	208	*/
mbed_official	489:119543c9f674	209	#if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
mbed_official	489:119543c9f674	210
mbed_official	376:cb4d9db17537	211	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
mbed_official	376:cb4d9db17537	212	#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
mbed_official	376:cb4d9db17537	213	#define RCC_PERIPHCLK_LPUART1 ((uint32_t)0x00000004)
mbed_official	376:cb4d9db17537	214	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000008)
mbed_official	376:cb4d9db17537	215	#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000010)
mbed_official	376:cb4d9db17537	216	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00000020)
mbed_official	376:cb4d9db17537	217	#define RCC_PERIPHCLK_USB ((uint32_t)0x00000040)
mbed_official	376:cb4d9db17537	218	#define RCC_PERIPHCLK_LPTIM1 ((uint32_t)0x00000080)
mbed_official	489:119543c9f674	219	#if defined (STM32L053xx) \|\| defined(STM32L063xx) \|\| defined(STM32L073xx) \|\| defined(STM32L083xx)
mbed_official	489:119543c9f674	220	#define RCC_PERIPHCLK_LCD ((uint32_t)0x00000800)
mbed_official	489:119543c9f674	221	#endif
mbed_official	489:119543c9f674	222	#if defined (STM32L072xx) \|\| defined(STM32L073xx) \|\| defined(STM32L082xx) \|\| defined(STM32L083xx)
mbed_official	489:119543c9f674	223	#define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00000100)
mbed_official	489:119543c9f674	224	#endif
mbed_official	376:cb4d9db17537	225
mbed_official	489:119543c9f674	226	#if defined (STM32L052xx) \|\| defined(STM32L062xx)
mbed_official	489:119543c9f674	227	#define IS_RCC_PERIPHCLK(__CLK__) ((__CLK__) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_LPUART1 \| \
mbed_official	489:119543c9f674	228	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_I2C2 \| RCC_PERIPHCLK_RTC \| \
mbed_official	489:119543c9f674	229	RCC_PERIPHCLK_USB \| RCC_PERIPHCLK_LPTIM1))
mbed_official	489:119543c9f674	230	#elif defined (STM32L053xx) \|\| defined(STM32L063xx)
mbed_official	489:119543c9f674	231	#define IS_RCC_PERIPHCLK(__CLK__) ((__CLK__) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_LPUART1 \| \
mbed_official	489:119543c9f674	232	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_I2C2 \| RCC_PERIPHCLK_RTC \| \
mbed_official	489:119543c9f674	233	RCC_PERIPHCLK_USB \| RCC_PERIPHCLK_LPTIM1 \| RCC_PERIPHCLK_LCD))
mbed_official	489:119543c9f674	234	#elif defined (STM32L072xx) \|\| defined(STM32L082xx)
mbed_official	489:119543c9f674	235	#define IS_RCC_PERIPHCLK(__CLK__) ((__CLK__) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_LPUART1 \| \
mbed_official	489:119543c9f674	236	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_I2C2 \| RCC_PERIPHCLK_RTC \| \
mbed_official	489:119543c9f674	237	RCC_PERIPHCLK_USB \| RCC_PERIPHCLK_LPTIM1 \| RCC_PERIPHCLK_I2C3 ))
mbed_official	489:119543c9f674	238	#elif defined (STM32L073xx) \|\| defined(STM32L083xx)
mbed_official	489:119543c9f674	239	#define IS_RCC_PERIPHCLK(__CLK__) ((__CLK__) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_LPUART1 \| \
mbed_official	489:119543c9f674	240	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_I2C2 \| RCC_PERIPHCLK_RTC \| \
mbed_official	489:119543c9f674	241	RCC_PERIPHCLK_USB \| RCC_PERIPHCLK_LPTIM1 \| RCC_PERIPHCLK_I2C3 \| \
mbed_official	489:119543c9f674	242	RCC_PERIPHCLK_LCD))
mbed_official	489:119543c9f674	243	#endif
mbed_official	376:cb4d9db17537	244
mbed_official	489:119543c9f674	245	#else /* !(STM32L031xx) && !(STM32L041xx) && !(STM32L051xx) && !(STM32L061xx) && !(STM32L071xx) && !(STM32L081xx) */
mbed_official	489:119543c9f674	246
mbed_official	489:119543c9f674	247	#if !defined(STM32L031xx) && !defined(STM32L041xx)
mbed_official	376:cb4d9db17537	248	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
mbed_official	489:119543c9f674	249	#endif
mbed_official	376:cb4d9db17537	250	#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
mbed_official	376:cb4d9db17537	251	#define RCC_PERIPHCLK_LPUART1 ((uint32_t)0x00000004)
mbed_official	376:cb4d9db17537	252	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000008)
mbed_official	489:119543c9f674	253	#if !defined(STM32L031xx) && !defined(STM32L041xx)
mbed_official	376:cb4d9db17537	254	#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000010)
mbed_official	489:119543c9f674	255	#endif
mbed_official	376:cb4d9db17537	256	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00000020)
mbed_official	376:cb4d9db17537	257	#define RCC_PERIPHCLK_LPTIM1 ((uint32_t)0x00000080)
mbed_official	489:119543c9f674	258	#if defined(STM32L071xx) \|\| defined(STM32L081xx)
mbed_official	489:119543c9f674	259	#define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00000100)
mbed_official	489:119543c9f674	260	#endif
mbed_official	376:cb4d9db17537	261
mbed_official	489:119543c9f674	262	#if defined(STM32L031xx) \|\| defined(STM32L041xx)
mbed_official	489:119543c9f674	263	#define IS_RCC_PERIPHCLK(__CLK__) ((__CLK__) <= ( RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_LPUART1 \| \
mbed_official	489:119543c9f674	264	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_RTC ))
mbed_official	489:119543c9f674	265	#elif defined(STM32L051xx) \|\| defined(STM32L061xx)
mbed_official	489:119543c9f674	266	#define IS_RCC_PERIPHCLK(__CLK__) ((__CLK__) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_LPUART1 \| \
mbed_official	489:119543c9f674	267	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_I2C2 \| RCC_PERIPHCLK_RTC \| \
mbed_official	489:119543c9f674	268	RCC_PERIPHCLK_LPTIM1))
mbed_official	489:119543c9f674	269	#elif defined(STM32L071xx) \|\| defined(STM32L081xx)
mbed_official	489:119543c9f674	270	#define IS_RCC_PERIPHCLK(__CLK__) ((__CLK__) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_LPUART1 \| \
mbed_official	489:119543c9f674	271	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_I2C2 \| RCC_PERIPHCLK_RTC \| \
mbed_official	489:119543c9f674	272	RCC_PERIPHCLK_LPTIM1 \| RCC_PERIPHCLK_I2C3))
mbed_official	489:119543c9f674	273	#endif
mbed_official	489:119543c9f674	274
mbed_official	489:119543c9f674	275	#endif /* !(STM32L031xx) && !(STM32L041xx) && !(STM32L061xx) && !(STM32L071xx) && !(STM32L081xx) */
mbed_official	376:cb4d9db17537	276	/**
mbed_official	376:cb4d9db17537	277	* @}
mbed_official	376:cb4d9db17537	278	*/
mbed_official	489:119543c9f674	279
mbed_official	376:cb4d9db17537	280	/** @defgroup RCCEx_USART1_Clock_Source
mbed_official	376:cb4d9db17537	281	* @{
mbed_official	376:cb4d9db17537	282	*/
mbed_official	376:cb4d9db17537	283	#define RCC_USART1CLKSOURCE_PCLK2 ((uint32_t)0x00000000)
mbed_official	376:cb4d9db17537	284	#define RCC_USART1CLKSOURCE_SYSCLK RCC_CCIPR_USART1SEL_0
mbed_official	376:cb4d9db17537	285	#define RCC_USART1CLKSOURCE_HSI RCC_CCIPR_USART1SEL_1
mbed_official	376:cb4d9db17537	286	#define RCC_USART1CLKSOURCE_LSE (RCC_CCIPR_USART1SEL_0 \| RCC_CCIPR_USART1SEL_1)
mbed_official	489:119543c9f674	287	#define IS_RCC_USART1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK2) \|\| \
mbed_official	489:119543c9f674	288	((__SOURCE__) == RCC_USART1CLKSOURCE_SYSCLK) \|\| \
mbed_official	489:119543c9f674	289	((__SOURCE__) == RCC_USART1CLKSOURCE_LSE) \|\| \
mbed_official	489:119543c9f674	290	((__SOURCE__) == RCC_USART1CLKSOURCE_HSI))
mbed_official	376:cb4d9db17537	291	/**
mbed_official	376:cb4d9db17537	292	* @}
mbed_official	376:cb4d9db17537	293	*/
mbed_official	376:cb4d9db17537	294
mbed_official	376:cb4d9db17537	295	/** @defgroup RCCEx_USART2_Clock_Source
mbed_official	376:cb4d9db17537	296	* @{
mbed_official	376:cb4d9db17537	297	*/
mbed_official	376:cb4d9db17537	298	#define RCC_USART2CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
mbed_official	376:cb4d9db17537	299	#define RCC_USART2CLKSOURCE_SYSCLK RCC_CCIPR_USART2SEL_0
mbed_official	376:cb4d9db17537	300	#define RCC_USART2CLKSOURCE_HSI RCC_CCIPR_USART2SEL_1
mbed_official	376:cb4d9db17537	301	#define RCC_USART2CLKSOURCE_LSE (RCC_CCIPR_USART2SEL_0 \| RCC_CCIPR_USART2SEL_1)
mbed_official	489:119543c9f674	302	#define IS_RCC_USART2CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_USART2CLKSOURCE_PCLK1) \|\| \
mbed_official	489:119543c9f674	303	((__SOURCE__) == RCC_USART2CLKSOURCE_SYSCLK) \|\| \
mbed_official	489:119543c9f674	304	((__SOURCE__) == RCC_USART2CLKSOURCE_LSE) \|\| \
mbed_official	489:119543c9f674	305	((__SOURCE__) == RCC_USART2CLKSOURCE_HSI))
mbed_official	376:cb4d9db17537	306	/**
mbed_official	376:cb4d9db17537	307	* @}
mbed_official	376:cb4d9db17537	308	*/
mbed_official	376:cb4d9db17537	309
mbed_official	376:cb4d9db17537	310	/** @defgroup RCCEx_LPUART_Clock_Source
mbed_official	376:cb4d9db17537	311	* @{
mbed_official	376:cb4d9db17537	312	*/
mbed_official	376:cb4d9db17537	313	#define RCC_LPUART1CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
mbed_official	376:cb4d9db17537	314	#define RCC_LPUART1CLKSOURCE_SYSCLK RCC_CCIPR_LPUART1SEL_0
mbed_official	376:cb4d9db17537	315	#define RCC_LPUART1CLKSOURCE_HSI RCC_CCIPR_LPUART1SEL_1
mbed_official	376:cb4d9db17537	316	#define RCC_LPUART1CLKSOURCE_LSE (RCC_CCIPR_LPUART1SEL_0 \| RCC_CCIPR_LPUART1SEL_1)
mbed_official	489:119543c9f674	317	#define IS_RCC_LPUART1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_LPUART1CLKSOURCE_PCLK1) \|\| \
mbed_official	489:119543c9f674	318	((__SOURCE__) == RCC_LPUART1CLKSOURCE_SYSCLK) \|\| \
mbed_official	489:119543c9f674	319	((__SOURCE__) == RCC_LPUART1CLKSOURCE_LSE) \|\| \
mbed_official	489:119543c9f674	320	((__SOURCE__) == RCC_LPUART1CLKSOURCE_HSI))
mbed_official	376:cb4d9db17537	321	/**
mbed_official	376:cb4d9db17537	322	* @}
mbed_official	376:cb4d9db17537	323	*/
mbed_official	376:cb4d9db17537	324
mbed_official	376:cb4d9db17537	325	/** @defgroup RCCEx_I2C1_Clock_Source
mbed_official	376:cb4d9db17537	326	* @{
mbed_official	376:cb4d9db17537	327	*/
mbed_official	376:cb4d9db17537	328	#define RCC_I2C1CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
mbed_official	376:cb4d9db17537	329	#define RCC_I2C1CLKSOURCE_SYSCLK RCC_CCIPR_I2C1SEL_0
mbed_official	376:cb4d9db17537	330	#define RCC_I2C1CLKSOURCE_HSI RCC_CCIPR_I2C1SEL_1
mbed_official	489:119543c9f674	331	#define IS_RCC_I2C1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2C1CLKSOURCE_PCLK1) \|\| \
mbed_official	489:119543c9f674	332	((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK)\|\| \
mbed_official	489:119543c9f674	333	((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI))
mbed_official	489:119543c9f674	334	/**
mbed_official	489:119543c9f674	335	* @}
mbed_official	489:119543c9f674	336	*/
mbed_official	489:119543c9f674	337
mbed_official	489:119543c9f674	338	#if defined(STM32L071xx) \|\| defined(STM32L072xx) \|\| defined(STM32L073xx)\|\| defined(STM32L081xx) \|\| defined(STM32L082xx) \|\| defined(STM32L083xx)
mbed_official	489:119543c9f674	339
mbed_official	489:119543c9f674	340	/** @defgroup RCCEx_I2C3_Clock_Source
mbed_official	489:119543c9f674	341	* @{
mbed_official	489:119543c9f674	342	*/
mbed_official	489:119543c9f674	343	#define RCC_I2C3CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
mbed_official	489:119543c9f674	344	#define RCC_I2C3CLKSOURCE_SYSCLK RCC_CCIPR_I2C3SEL_0
mbed_official	489:119543c9f674	345	#define RCC_I2C3CLKSOURCE_HSI RCC_CCIPR_I2C3SEL_1
mbed_official	489:119543c9f674	346	#define IS_RCC_I2C3CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2C3CLKSOURCE_PCLK1) \|\| \
mbed_official	489:119543c9f674	347	((__SOURCE__) == RCC_I2C3CLKSOURCE_SYSCLK)\|\| \
mbed_official	489:119543c9f674	348	((__SOURCE__) == RCC_I2C3CLKSOURCE_HSI))
mbed_official	489:119543c9f674	349	#endif /* defined(STM32L071xx) \|\| defined(STM32L072xx) \|\| defined(STM32L073xx) \|\| defined(STM32L081xx)\|\| defined(STM32L082xx) \|\| defined(STM32L083xx) */
mbed_official	489:119543c9f674	350
mbed_official	376:cb4d9db17537	351	/**
mbed_official	376:cb4d9db17537	352	* @}
mbed_official	376:cb4d9db17537	353	*/
mbed_official	376:cb4d9db17537	354
mbed_official	376:cb4d9db17537	355	/** @defgroup RCCEx_TIM_PRescaler_Selection
mbed_official	376:cb4d9db17537	356	* @{
mbed_official	376:cb4d9db17537	357	*/
mbed_official	376:cb4d9db17537	358	#define RCC_TIMPRES_DESACTIVATED ((uint8_t)0x00)
mbed_official	376:cb4d9db17537	359	#define RCC_TIMPRES_ACTIVATED ((uint8_t)0x01)
mbed_official	376:cb4d9db17537	360	/**
mbed_official	376:cb4d9db17537	361	* @}
mbed_official	376:cb4d9db17537	362	*/
mbed_official	376:cb4d9db17537	363
mbed_official	489:119543c9f674	364	#if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
mbed_official	376:cb4d9db17537	365	/** @defgroup RCCEx_USB_Clock_Source
mbed_official	376:cb4d9db17537	366	* @{
mbed_official	376:cb4d9db17537	367	*/
mbed_official	376:cb4d9db17537	368	#define RCC_USBCLKSOURCE_HSI48 RCC_CCIPR_HSI48SEL
mbed_official	376:cb4d9db17537	369	#define RCC_USBCLKSOURCE_PLLCLK ((uint32_t)0x00000000)
mbed_official	376:cb4d9db17537	370
mbed_official	489:119543c9f674	371	#define IS_RCC_USBCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_USBCLKSOURCE_HSI48) \|\| \
mbed_official	489:119543c9f674	372	((__SOURCE__) == RCC_USBCLKSOURCE_PLLCLK))
mbed_official	376:cb4d9db17537	373	/**
mbed_official	376:cb4d9db17537	374	* @}
mbed_official	376:cb4d9db17537	375	*/
mbed_official	376:cb4d9db17537	376
mbed_official	376:cb4d9db17537	377	/** @defgroup RCCEx_RNG_Clock_Source
mbed_official	376:cb4d9db17537	378	* @{
mbed_official	376:cb4d9db17537	379	*/
mbed_official	376:cb4d9db17537	380	#define RCC_RNGCLKSOURCE_HSI48 RCC_CCIPR_HSI48SEL
mbed_official	376:cb4d9db17537	381	#define RCC_RNGCLKSOURCE_PLLCLK ((uint32_t)0x00000000)
mbed_official	376:cb4d9db17537	382
mbed_official	489:119543c9f674	383	#define IS_RCC_RNGCLKSOURCE(_SOURCE_) (((_SOURCE_) == RCC_RNGCLKSOURCE_HSI48) \|\| \
mbed_official	489:119543c9f674	384	((_SOURCE_) == RCC_RNGCLKSOURCE_PLLCLK))
mbed_official	376:cb4d9db17537	385	/**
mbed_official	376:cb4d9db17537	386	* @}
mbed_official	376:cb4d9db17537	387	*/
mbed_official	376:cb4d9db17537	388
mbed_official	376:cb4d9db17537	389	/** @defgroup RCCEx_HSI48M_Clock_Source
mbed_official	376:cb4d9db17537	390	* @{
mbed_official	376:cb4d9db17537	391	*/
mbed_official	489:119543c9f674	392	#define RCC_FLAG_HSI48 SYSCFG_CFGR3_REF_HSI48_RDYF
mbed_official	376:cb4d9db17537	393
mbed_official	376:cb4d9db17537	394	#define RCC_HSI48M_PLL ((uint32_t)0x00000000)
mbed_official	489:119543c9f674	395	#define RCC_HSI48M_HSI48 RCC_CCIPR_HSI48SEL
mbed_official	376:cb4d9db17537	396
mbed_official	489:119543c9f674	397	#define IS_RCC_HSI48MCLKSOURCE(__HSI48MCLK__) (((__HSI48MCLK__) == RCC_HSI48M_PLL) \|\| ((__HSI48MCLK__) == RCC_HSI48M_HSI48))
mbed_official	376:cb4d9db17537	398
mbed_official	376:cb4d9db17537	399	/**
mbed_official	376:cb4d9db17537	400	* @}
mbed_official	376:cb4d9db17537	401	*/
mbed_official	489:119543c9f674	402	#endif /* !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
mbed_official	489:119543c9f674	403
mbed_official	489:119543c9f674	404	/** @defgroup RCC_HSI_Config
mbed_official	489:119543c9f674	405	* @{
mbed_official	489:119543c9f674	406	*/
mbed_official	489:119543c9f674	407	#define RCC_HSI_OFF ((uint8_t)0x00)
mbed_official	489:119543c9f674	408	#define RCC_HSI_ON RCC_CR_HSION
mbed_official	489:119543c9f674	409	#define RCC_HSI_DIV4 (RCC_CR_HSIDIVEN \| RCC_CR_HSION)
mbed_official	489:119543c9f674	410	#if defined(STM32L073xx) \|\| defined(STM32L083xx) \|\| \
mbed_official	489:119543c9f674	411	defined(STM32L072xx) \|\| defined(STM32L082xx) \|\| \
mbed_official	489:119543c9f674	412	defined(STM32L071xx) \|\| defined(STM32L081xx)
mbed_official	489:119543c9f674	413	#define RCC_HSI_OUTEN RCC_CR_HSIOUTEN
mbed_official	489:119543c9f674	414
mbed_official	489:119543c9f674	415	#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) \|\| ((__HSI__) == RCC_HSI_ON) \|\| \
mbed_official	489:119543c9f674	416	((__HSI__) == RCC_HSI_DIV4) \|\| ((__HSI__) == RCC_HSI_OUTEN ))
mbed_official	489:119543c9f674	417	#else
mbed_official	489:119543c9f674	418	#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) \|\| ((__HSI__) == RCC_HSI_ON) \|\| \
mbed_official	489:119543c9f674	419	((__HSI__) == RCC_HSI_DIV4))
mbed_official	489:119543c9f674	420	#endif
mbed_official	489:119543c9f674	421
mbed_official	489:119543c9f674	422	/**
mbed_official	489:119543c9f674	423	* @}
mbed_official	489:119543c9f674	424	*/
mbed_official	376:cb4d9db17537	425
mbed_official	376:cb4d9db17537	426	/** @defgroup RCCEx_LPTIM1_Clock_Source
mbed_official	376:cb4d9db17537	427	* @{
mbed_official	376:cb4d9db17537	428	*/
mbed_official	376:cb4d9db17537	429	#define RCC_LPTIM1CLKSOURCE_PCLK ((uint32_t)0x00000000)
mbed_official	376:cb4d9db17537	430	#define RCC_LPTIM1CLKSOURCE_LSI RCC_CCIPR_LPTIM1SEL_0
mbed_official	376:cb4d9db17537	431	#define RCC_LPTIM1CLKSOURCE_HSI RCC_CCIPR_LPTIM1SEL_1
mbed_official	376:cb4d9db17537	432	#define RCC_LPTIM1CLKSOURCE_LSE RCC_CCIPR_LPTIM1SEL
mbed_official	376:cb4d9db17537	433
mbed_official	489:119543c9f674	434	#define IS_RCC_LPTIMCLK(__LPTIMCLK_) (((__LPTIMCLK_) == RCC_LPTIM1CLKSOURCE_PCLK) \|\| \
mbed_official	489:119543c9f674	435	((__LPTIMCLK_) == RCC_LPTIM1CLKSOURCE_LSI) \|\| \
mbed_official	489:119543c9f674	436	((__LPTIMCLK_) == RCC_LPTIM1CLKSOURCE_HSI) \|\| \
mbed_official	489:119543c9f674	437	((__LPTIMCLK_) == RCC_LPTIM1CLKSOURCE_LSE))
mbed_official	376:cb4d9db17537	438	/**
mbed_official	376:cb4d9db17537	439	* @}
mbed_official	376:cb4d9db17537	440	*/
mbed_official	376:cb4d9db17537	441
mbed_official	376:cb4d9db17537	442	/** @defgroup RCCEx_StopWakeUp_Clock
mbed_official	376:cb4d9db17537	443	* @{
mbed_official	376:cb4d9db17537	444	*/
mbed_official	376:cb4d9db17537	445
mbed_official	489:119543c9f674	446	#define RCC_STOP_WAKEUPCLOCK_MSI ((uint32_t)0x00)
mbed_official	489:119543c9f674	447	#define RCC_STOP_WAKEUPCLOCK_HSI RCC_CFGR_STOPWUCK
mbed_official	376:cb4d9db17537	448
mbed_official	489:119543c9f674	449	#define IS_RCC_STOPWAKEUP_CLOCK(__SOURCE__) (((__SOURCE__) == RCC_StopWakeUpClock_MSI) \|\| \
mbed_official	489:119543c9f674	450	((__SOURCE__) == RCC_StopWakeUpClock_HSI))
mbed_official	376:cb4d9db17537	451	/**
mbed_official	376:cb4d9db17537	452	* @}
mbed_official	376:cb4d9db17537	453	*/
mbed_official	376:cb4d9db17537	454
mbed_official	376:cb4d9db17537	455	/** @defgroup RCCEx_LSEDrive_Configuration
mbed_official	376:cb4d9db17537	456	* @{
mbed_official	376:cb4d9db17537	457	*/
mbed_official	376:cb4d9db17537	458
mbed_official	376:cb4d9db17537	459	#define RCC_LSEDRIVE_LOW ((uint32_t)0x00000000)
mbed_official	376:cb4d9db17537	460	#define RCC_LSEDRIVE_MEDIUMLOW RCC_CSR_LSEDRV_0
mbed_official	376:cb4d9db17537	461	#define RCC_LSEDRIVE_MEDIUMHIGH RCC_CSR_LSEDRV_1
mbed_official	376:cb4d9db17537	462	#define RCC_LSEDRIVE_HIGH RCC_CSR_LSEDRV
mbed_official	489:119543c9f674	463	#define IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_LOW) \|\| ((__SOURCE__) == RCC_LSEDRIVE_MEDIUMLOW) \|\| \
mbed_official	489:119543c9f674	464	((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) \|\| ((__SOURCE__) == RCC_LSEDRIVE_HIGH))
mbed_official	376:cb4d9db17537	465	/**
mbed_official	376:cb4d9db17537	466	* @}
mbed_official	376:cb4d9db17537	467	*/
mbed_official	376:cb4d9db17537	468
mbed_official	489:119543c9f674	469	#if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
mbed_official	376:cb4d9db17537	470	/** @defgroup RCCEx_CRS_SynchroSource
mbed_official	376:cb4d9db17537	471	* @{
mbed_official	376:cb4d9db17537	472	*/
mbed_official	376:cb4d9db17537	473	#define RCC_CRS_SYNC_SOURCE_GPIO ((uint32_t)0x00) /!< Synchro Signal source GPIO /
mbed_official	376:cb4d9db17537	474	#define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /!< Synchro Signal source LSE /
mbed_official	376:cb4d9db17537	475	#define RCC_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /!< Synchro Signal source USB SOF (default)/
mbed_official	376:cb4d9db17537	476
mbed_official	489:119543c9f674	477	#define IS_RCC_CRS_SYNC_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_CRS_SYNC_SOURCE_GPIO) \|\| \
mbed_official	489:119543c9f674	478	((__SOURCE__) == RCC_CRS_SYNC_SOURCE_LSE) \|\|\
mbed_official	489:119543c9f674	479	((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB))
mbed_official	376:cb4d9db17537	480	/**
mbed_official	376:cb4d9db17537	481	* @}
mbed_official	376:cb4d9db17537	482	*/
mbed_official	376:cb4d9db17537	483
mbed_official	376:cb4d9db17537	484	/** @defgroup RCCEx_CRS_SynchroDivider
mbed_official	376:cb4d9db17537	485	* @{
mbed_official	376:cb4d9db17537	486	*/
mbed_official	376:cb4d9db17537	487	#define RCC_CRS_SYNC_DIV1 ((uint32_t)0x00) /!< Synchro Signal not divided (default) /
mbed_official	376:cb4d9db17537	488	#define RCC_CRS_SYNC_DIV2 CRS_CFGR_SYNCDIV_0 /!< Synchro Signal divided by 2 /
mbed_official	376:cb4d9db17537	489	#define RCC_CRS_SYNC_DIV4 CRS_CFGR_SYNCDIV_1 /!< Synchro Signal divided by 4 /
mbed_official	376:cb4d9db17537	490	#define RCC_CRS_SYNC_DIV8 (CRS_CFGR_SYNCDIV_1 \| CRS_CFGR_SYNCDIV_0) /!< Synchro Signal divided by 8 /
mbed_official	376:cb4d9db17537	491	#define RCC_CRS_SYNC_DIV16 CRS_CFGR_SYNCDIV_2 /!< Synchro Signal divided by 16 /
mbed_official	376:cb4d9db17537	492	#define RCC_CRS_SYNC_DIV32 (CRS_CFGR_SYNCDIV_2 \| CRS_CFGR_SYNCDIV_0) /!< Synchro Signal divided by 32 /
mbed_official	376:cb4d9db17537	493	#define RCC_CRS_SYNC_DIV64 (CRS_CFGR_SYNCDIV_2 \| CRS_CFGR_SYNCDIV_1) /!< Synchro Signal divided by 64 /
mbed_official	376:cb4d9db17537	494	#define RCC_CRS_SYNC_DIV128 CRS_CFGR_SYNCDIV /!< Synchro Signal divided by 128 /
mbed_official	376:cb4d9db17537	495
mbed_official	489:119543c9f674	496	#define IS_RCC_CRS_SYNC_DIV(__DIV__) (((__DIV__) == RCC_CRS_SYNC_DIV1) \|\| ((__DIV__) == RCC_CRS_SYNC_DIV2) \|\|\
mbed_official	489:119543c9f674	497	((__DIV__) == RCC_CRS_SYNC_DIV4) \|\| ((__DIV__) == RCC_CRS_SYNC_DIV8) \|\| \
mbed_official	489:119543c9f674	498	((__DIV__) == RCC_CRS_SYNC_DIV16) \|\| ((__DIV__) == RCC_CRS_SYNC_DIV32) \|\| \
mbed_official	489:119543c9f674	499	((__DIV__) == RCC_CRS_SYNC_DIV64) \|\| ((__DIV__) == RCC_CRS_SYNC_DIV128))
mbed_official	376:cb4d9db17537	500	/**
mbed_official	376:cb4d9db17537	501	* @}
mbed_official	376:cb4d9db17537	502	*/
mbed_official	376:cb4d9db17537	503
mbed_official	376:cb4d9db17537	504	/** @defgroup RCCEx_CRS_SynchroPolarity
mbed_official	376:cb4d9db17537	505	* @{
mbed_official	376:cb4d9db17537	506	*/
mbed_official	376:cb4d9db17537	507	#define RCC_CRS_SYNC_POLARITY_RISING ((uint32_t)0x00) /!< Synchro Active on rising edge (default) /
mbed_official	376:cb4d9db17537	508	#define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /!< Synchro Active on falling edge /
mbed_official	376:cb4d9db17537	509
mbed_official	489:119543c9f674	510	#define IS_RCC_CRS_SYNC_POLARITY(__POLARITY__) (((__POLARITY__) == RCC_CRS_SYNC_POLARITY_RISING) \|\| \
mbed_official	489:119543c9f674	511	((__POLARITY__) == RCC_CRS_SYNC_POLARITY_FALLING))
mbed_official	376:cb4d9db17537	512	/**
mbed_official	376:cb4d9db17537	513	* @}
mbed_official	376:cb4d9db17537	514	*/
mbed_official	376:cb4d9db17537	515
mbed_official	376:cb4d9db17537	516	/** @defgroup RCCEx_CRS_ReloadValueDefault
mbed_official	376:cb4d9db17537	517	* @{
mbed_official	376:cb4d9db17537	518	*/
mbed_official	376:cb4d9db17537	519	#define RCC_CRS_RELOADVALUE_DEFAULT ((uint32_t)0xBB7F) /*!< The reset value of the RELOAD field corresponds
mbed_official	376:cb4d9db17537	520	to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */
mbed_official	376:cb4d9db17537	521
mbed_official	489:119543c9f674	522	#define IS_RCC_CRS_RELOADVALUE(__VALUE__) (((__VALUE__) <= 0xFFFF))
mbed_official	376:cb4d9db17537	523	/**
mbed_official	376:cb4d9db17537	524	* @}
mbed_official	376:cb4d9db17537	525	*/
mbed_official	376:cb4d9db17537	526
mbed_official	376:cb4d9db17537	527	/** @defgroup RCCEx_CRS_ErrorLimitDefault
mbed_official	376:cb4d9db17537	528	* @{
mbed_official	376:cb4d9db17537	529	*/
mbed_official	376:cb4d9db17537	530	#define RCC_CRS_ERRORLIMIT_DEFAULT ((uint32_t)0x22) /!< Default Frequency error limit /
mbed_official	376:cb4d9db17537	531
mbed_official	489:119543c9f674	532	#define IS_RCC_CRS_ERRORLIMIT(__VALUE__) (((__VALUE__) <= 0xFF))
mbed_official	376:cb4d9db17537	533	/**
mbed_official	376:cb4d9db17537	534	* @}
mbed_official	376:cb4d9db17537	535	*/
mbed_official	376:cb4d9db17537	536
mbed_official	376:cb4d9db17537	537	/** @defgroup RCCEx_CRS_HSI48CalibrationDefault
mbed_official	376:cb4d9db17537	538	* @{
mbed_official	376:cb4d9db17537	539	*/
mbed_official	376:cb4d9db17537	540	#define RCC_CRS_HSI48CALIBRATION_DEFAULT ((uint32_t)0x20) /*!< The default value is 32, which corresponds to the middle of the trimming interval.
mbed_official	376:cb4d9db17537	541	The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value
mbed_official	376:cb4d9db17537	542	corresponds to a higher output frequency */
mbed_official	376:cb4d9db17537	543
mbed_official	489:119543c9f674	544	#define IS_RCC_CRS_HSI48CALIBRATION(__VALUE__) (((__VALUE__) <= 0x3F))
mbed_official	376:cb4d9db17537	545	/**
mbed_official	376:cb4d9db17537	546	* @}
mbed_official	376:cb4d9db17537	547	*/
mbed_official	376:cb4d9db17537	548
mbed_official	376:cb4d9db17537	549	/** @defgroup RCCEx_CRS_FreqErrorDirection
mbed_official	376:cb4d9db17537	550	* @{
mbed_official	376:cb4d9db17537	551	*/
mbed_official	376:cb4d9db17537	552	#define RCC_CRS_FREQERRORDIR_UP ((uint32_t)0x00) /!< Upcounting direction, the actual frequency is above the target /
mbed_official	376:cb4d9db17537	553	#define RCC_CRS_FREQERRORDIR_DOWN ((uint32_t)CRS_ISR_FEDIR) /!< Downcounting direction, the actual frequency is below the target /
mbed_official	376:cb4d9db17537	554
mbed_official	489:119543c9f674	555	#define IS_RCC_CRS_FREQERRORDIR(__DIR__) (((__DIR__) == RCC_CRS_FREQERRORDIR_UP) \|\| \
mbed_official	489:119543c9f674	556	((__DIR__) == RCC_CRS_FREQERRORDIR_DOWN))
mbed_official	376:cb4d9db17537	557	/**
mbed_official	376:cb4d9db17537	558	* @}
mbed_official	376:cb4d9db17537	559	*/
mbed_official	376:cb4d9db17537	560
mbed_official	376:cb4d9db17537	561	/** @defgroup RCCEx_CRS_Interrupt_Sources
mbed_official	376:cb4d9db17537	562	* @{
mbed_official	376:cb4d9db17537	563	*/
mbed_official	376:cb4d9db17537	564	#define RCC_CRS_IT_SYNCOK CRS_ISR_SYNCOKF /!< SYNC event OK /
mbed_official	376:cb4d9db17537	565	#define RCC_CRS_IT_SYNCWARN CRS_ISR_SYNCWARNF /!< SYNC warning /
mbed_official	376:cb4d9db17537	566	#define RCC_CRS_IT_ERR CRS_ISR_ERRF /!< error /
mbed_official	376:cb4d9db17537	567	#define RCC_CRS_IT_ESYNC CRS_ISR_ESYNCF /!< Expected SYNC /
mbed_official	376:cb4d9db17537	568	#define RCC_CRS_IT_TRIMOVF CRS_ISR_TRIMOVF /!< Trimming overflow or underflow /
mbed_official	376:cb4d9db17537	569	#define RCC_CRS_IT_SYNCERR CRS_ISR_SYNCERR /!< SYNC error /
mbed_official	376:cb4d9db17537	570	#define RCC_CRS_IT_SYNCMISS CRS_ISR_SYNCMISS /!< SYNC missed/
mbed_official	376:cb4d9db17537	571
mbed_official	376:cb4d9db17537	572	/**
mbed_official	376:cb4d9db17537	573	* @}
mbed_official	376:cb4d9db17537	574	*/
mbed_official	376:cb4d9db17537	575
mbed_official	376:cb4d9db17537	576	/** @defgroup RCCEx_CRS_Flags
mbed_official	376:cb4d9db17537	577	* @{
mbed_official	376:cb4d9db17537	578	*/
mbed_official	376:cb4d9db17537	579	#define RCC_CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF /* SYNC event OK flag */
mbed_official	376:cb4d9db17537	580	#define RCC_CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF /* SYNC warning flag */
mbed_official	376:cb4d9db17537	581	#define RCC_CRS_FLAG_ERR CRS_ISR_ERRF /* Error flag */
mbed_official	376:cb4d9db17537	582	#define RCC_CRS_FLAG_ESYNC CRS_ISR_ESYNCF /* Expected SYNC flag */
mbed_official	376:cb4d9db17537	583	#define RCC_CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF /!< Trimming overflow or underflow /
mbed_official	376:cb4d9db17537	584	#define RCC_CRS_FLAG_SYNCERR CRS_ISR_SYNCERR /!< SYNC error /
mbed_official	376:cb4d9db17537	585	#define RCC_CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS /!< SYNC missed/
mbed_official	376:cb4d9db17537	586
mbed_official	376:cb4d9db17537	587	/**
mbed_official	376:cb4d9db17537	588	* @}
mbed_official	376:cb4d9db17537	589	*/
mbed_official	376:cb4d9db17537	590
mbed_official	489:119543c9f674	591	#endif /* !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
mbed_official	376:cb4d9db17537	592	/**
mbed_official	376:cb4d9db17537	593	* @}
mbed_official	376:cb4d9db17537	594	*/
mbed_official	376:cb4d9db17537	595
mbed_official	376:cb4d9db17537	596	/* Exported macro ------------------------------------------------------------*/
mbed_official	489:119543c9f674	597	/** @defgroup RCCEx_Exported_Macros RCC Ex Exported Macros
mbed_official	376:cb4d9db17537	598	* @{
mbed_official	376:cb4d9db17537	599	*/
mbed_official	376:cb4d9db17537	600
mbed_official	376:cb4d9db17537	601	/** @brief Enable or disable the AHB peripheral clock.
mbed_official	376:cb4d9db17537	602	* @note After reset, the peripheral clock (used for registers read/write access)
mbed_official	376:cb4d9db17537	603	* is disabled and the application software has to enable this clock before
mbed_official	376:cb4d9db17537	604	* using it.
mbed_official	376:cb4d9db17537	605	*/
mbed_official	376:cb4d9db17537	606
mbed_official	489:119543c9f674	607	#if defined(STM32L062xx) \|\| defined(STM32L063xx)\|\| defined(STM32L082xx) \|\| defined(STM32L083xx)
mbed_official	489:119543c9f674	608	#define __HAL_RCC_AES_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_CRYPEN))
mbed_official	489:119543c9f674	609	#define __HAL_RCC_AES_CLK_DISABLE() (RCC->AHBENR &= ~ (RCC_AHBENR_CRYPEN))
mbed_official	489:119543c9f674	610	#endif /* STM32L062xx \|\| STM32L063xx \|\| STM32L072xx \|\| STM32L073xx \|\| STM32L082xx \|\| STM32L083xx */
mbed_official	489:119543c9f674	611
mbed_official	489:119543c9f674	612	#if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
mbed_official	489:119543c9f674	613	#define __HAL_RCC_TSC_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_TSCEN))
mbed_official	489:119543c9f674	614	#define __HAL_RCC_TSC_CLK_DISABLE() (RCC->AHBENR &= ~ (RCC_AHBENR_TSCEN))
mbed_official	489:119543c9f674	615
mbed_official	489:119543c9f674	616	#define __HAL_RCC_RNG_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_RNGEN))
mbed_official	489:119543c9f674	617	#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHBENR &= ~ (RCC_AHBENR_RNGEN))
mbed_official	489:119543c9f674	618	#endif /* !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
mbed_official	489:119543c9f674	619
mbed_official	376:cb4d9db17537	620
mbed_official	489:119543c9f674	621	#if defined(STM32L073xx) \|\| defined(STM32L083xx) \|\| \
mbed_official	489:119543c9f674	622	defined(STM32L072xx) \|\| defined(STM32L082xx) \|\| \
mbed_official	489:119543c9f674	623	defined(STM32L071xx) \|\| defined(STM32L081xx)
mbed_official	489:119543c9f674	624	/** @brief Enable or disable the IOPORT peripheral clock.
mbed_official	489:119543c9f674	625	* @note After reset, the peripheral clock (used for registers read/write access)
mbed_official	489:119543c9f674	626	* is disabled and the application software has to enable this clock before
mbed_official	489:119543c9f674	627	* using it.
mbed_official	489:119543c9f674	628	*/
mbed_official	489:119543c9f674	629	#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
mbed_official	489:119543c9f674	630	__IO uint32_t tmpreg; \
mbed_official	489:119543c9f674	631	SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOEEN);\
mbed_official	489:119543c9f674	632	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	489:119543c9f674	633	tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOEEN);\
mbed_official	489:119543c9f674	634	UNUSED(tmpreg); \
mbed_official	489:119543c9f674	635	} while(0)
mbed_official	376:cb4d9db17537	636
mbed_official	489:119543c9f674	637	#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->IOPENR &= ~(RCC_IOPENR_GPIOEEN))
mbed_official	489:119543c9f674	638
mbed_official	489:119543c9f674	639	#endif /* STM32L071xx \|\| STM32L081xx \|\| */
mbed_official	489:119543c9f674	640	/* STM32L072xx \|\| STM32L082xx \|\| */
mbed_official	489:119543c9f674	641	/* STM32L073xx \|\| STM32L083xx */
mbed_official	376:cb4d9db17537	642
mbed_official	376:cb4d9db17537	643	/** @brief Enable or disable the APB1 peripheral clock.
mbed_official	376:cb4d9db17537	644	* @note After reset, the peripheral clock (used for registers read/write access)
mbed_official	376:cb4d9db17537	645	* is disabled and the application software has to enable this clock before
mbed_official	376:cb4d9db17537	646	* using it.
mbed_official	376:cb4d9db17537	647	*/
mbed_official	376:cb4d9db17537	648
mbed_official	489:119543c9f674	649	#if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
mbed_official	489:119543c9f674	650	#define __HAL_RCC_USB_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_USBEN))
mbed_official	489:119543c9f674	651	#define __HAL_RCC_USB_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_USBEN))
mbed_official	376:cb4d9db17537	652
mbed_official	489:119543c9f674	653	#define __HAL_RCC_CRS_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_CRSEN))
mbed_official	489:119543c9f674	654	#define __HAL_RCC_CRS_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CRSEN))
mbed_official	489:119543c9f674	655	#endif /* !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
mbed_official	376:cb4d9db17537	656
mbed_official	376:cb4d9db17537	657
mbed_official	489:119543c9f674	658	#if defined(STM32L053xx) \|\| defined(STM32L063xx) \|\| defined(STM32L073xx) \|\| defined(STM32L083xx)
mbed_official	489:119543c9f674	659	#define __HAL_RCC_LCD_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_LCDEN))
mbed_official	489:119543c9f674	660	#define __HAL_RCC_LCD_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_LCDEN))
mbed_official	489:119543c9f674	661	#endif /* STM32L053xx \|\| STM32L063xx \|\| STM32L073xx \|\| STM32L083xx */
mbed_official	376:cb4d9db17537	662
mbed_official	376:cb4d9db17537	663	#if defined(STM32L053xx) \|\| defined(STM32L063xx) \|\| \
mbed_official	376:cb4d9db17537	664	defined(STM32L052xx) \|\| defined(STM32L062xx) \|\| \
mbed_official	376:cb4d9db17537	665	defined(STM32L051xx) \|\| defined(STM32L061xx)
mbed_official	489:119543c9f674	666	#define __HAL_RCC_TIM2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM2EN))
mbed_official	489:119543c9f674	667	#define __HAL_RCC_TIM6_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM6EN))
mbed_official	489:119543c9f674	668	#define __HAL_RCC_SPI2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_SPI2EN))
mbed_official	489:119543c9f674	669	#define __HAL_RCC_USART2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_USART2EN))
mbed_official	489:119543c9f674	670	#define __HAL_RCC_LPUART1_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_LPUART1EN))
mbed_official	489:119543c9f674	671	#define __HAL_RCC_I2C1_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_I2C1EN))
mbed_official	489:119543c9f674	672	#define __HAL_RCC_I2C2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_I2C2EN))
mbed_official	489:119543c9f674	673	#define __HAL_RCC_DAC_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_DACEN))
mbed_official	489:119543c9f674	674	#define __HAL_RCC_LPTIM1_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_LPTIM1EN))
mbed_official	489:119543c9f674	675
mbed_official	489:119543c9f674	676	#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_TIM2EN))
mbed_official	489:119543c9f674	677	#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_TIM6EN))
mbed_official	489:119543c9f674	678	#define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_SPI2EN))
mbed_official	489:119543c9f674	679	#define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_USART2EN))
mbed_official	489:119543c9f674	680	#define __HAL_RCC_LPUART1_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_LPUART1EN))
mbed_official	489:119543c9f674	681	#define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_I2C1EN))
mbed_official	489:119543c9f674	682	#define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_I2C2EN))
mbed_official	489:119543c9f674	683	#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_DACEN))
mbed_official	489:119543c9f674	684	#define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_LPTIM1EN))
mbed_official	489:119543c9f674	685	#endif /* STM32L051xx \|\| STM32L061xx \|\| */
mbed_official	489:119543c9f674	686	/* STM32L052xx \|\| STM32L062xx \|\| */
mbed_official	489:119543c9f674	687	/* STM32L053xx \|\| STM32L063xx \|\| */
mbed_official	489:119543c9f674	688
mbed_official	489:119543c9f674	689	#if defined(STM32L031xx) \|\| defined(STM32L041xx)
mbed_official	489:119543c9f674	690	#define __HAL_RCC_TIM2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM2EN))
mbed_official	489:119543c9f674	691	#define __HAL_RCC_USART2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_USART2EN))
mbed_official	489:119543c9f674	692	#define __HAL_RCC_LPUART1_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_LPUART1EN))
mbed_official	489:119543c9f674	693	#define __HAL_RCC_I2C1_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_I2C1EN))
mbed_official	489:119543c9f674	694	#define __HAL_RCC_LPTIM1_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_LPTIM1EN))
mbed_official	489:119543c9f674	695
mbed_official	489:119543c9f674	696	#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_TIM2EN))
mbed_official	489:119543c9f674	697	#define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_USART2EN))
mbed_official	489:119543c9f674	698	#define __HAL_RCC_LPUART1_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_LPUART1EN))
mbed_official	489:119543c9f674	699	#define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_I2C1EN))
mbed_official	489:119543c9f674	700	#define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_LPTIM1EN))
mbed_official	489:119543c9f674	701	#endif /* STM32L031xx \|\| STM32L041xx \|\| */
mbed_official	489:119543c9f674	702
mbed_official	376:cb4d9db17537	703
mbed_official	489:119543c9f674	704	#if defined(STM32L073xx) \|\| defined(STM32L083xx) \|\| \
mbed_official	489:119543c9f674	705	defined(STM32L072xx) \|\| defined(STM32L082xx) \|\| \
mbed_official	489:119543c9f674	706	defined(STM32L071xx) \|\| defined(STM32L081xx)
mbed_official	489:119543c9f674	707	#define __HAL_RCC_TIM2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM2EN))
mbed_official	489:119543c9f674	708	#define __HAL_RCC_TIM3_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM3EN))
mbed_official	489:119543c9f674	709	#define __HAL_RCC_TIM6_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM6EN))
mbed_official	489:119543c9f674	710	#define __HAL_RCC_TIM7_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM7EN))
mbed_official	489:119543c9f674	711	#define __HAL_RCC_SPI2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_SPI2EN))
mbed_official	489:119543c9f674	712	#define __HAL_RCC_USART2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_USART2EN))
mbed_official	489:119543c9f674	713	#define __HAL_RCC_USART4_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_USART4EN))
mbed_official	489:119543c9f674	714	#define __HAL_RCC_USART5_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_USART5EN))
mbed_official	489:119543c9f674	715	#define __HAL_RCC_LPUART1_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_LPUART1EN))
mbed_official	489:119543c9f674	716	#define __HAL_RCC_I2C1_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_I2C1EN))
mbed_official	489:119543c9f674	717	#define __HAL_RCC_I2C2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_I2C2EN))
mbed_official	489:119543c9f674	718	#define __HAL_RCC_I2C3_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_I2C3EN))
mbed_official	489:119543c9f674	719	#define __HAL_RCC_DAC_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_DACEN))
mbed_official	489:119543c9f674	720	#define __HAL_RCC_LPTIM1_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_LPTIM1EN))
mbed_official	489:119543c9f674	721
mbed_official	489:119543c9f674	722	#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_TIM2EN))
mbed_official	489:119543c9f674	723	#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_TIM3EN))
mbed_official	489:119543c9f674	724	#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_TIM6EN))
mbed_official	489:119543c9f674	725	#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_TIM7EN))
mbed_official	489:119543c9f674	726	#define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_SPI2EN))
mbed_official	489:119543c9f674	727	#define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_USART2EN))
mbed_official	489:119543c9f674	728	#define __HAL_RCC_USART4_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_USART4EN))
mbed_official	489:119543c9f674	729	#define __HAL_RCC_USART5_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_USART5EN))
mbed_official	489:119543c9f674	730	#define __HAL_RCC_LPUART1_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_LPUART1EN))
mbed_official	489:119543c9f674	731	#define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_I2C1EN))
mbed_official	489:119543c9f674	732	#define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_I2C2EN))
mbed_official	489:119543c9f674	733	#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_I2C3EN))
mbed_official	489:119543c9f674	734	#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_DACEN))
mbed_official	489:119543c9f674	735	#define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_LPTIM1EN))
mbed_official	489:119543c9f674	736	#endif /* STM32L071xx \|\| STM32L081xx \|\| */
mbed_official	489:119543c9f674	737	/* STM32L072xx \|\| STM32L082xx \|\| */
mbed_official	489:119543c9f674	738	/* STM32L073xx \|\| STM32L083xx */
mbed_official	489:119543c9f674	739
mbed_official	489:119543c9f674	740	#if defined(STM32L053xx) \|\| defined(STM32L063xx) \|\| defined(STM32L073xx) \|\| defined(STM32L083xx) \|\| \
mbed_official	489:119543c9f674	741	defined(STM32L052xx) \|\| defined(STM32L062xx) \|\| defined(STM32L072xx) \|\| defined(STM32L082xx) \|\| \
mbed_official	489:119543c9f674	742	defined(STM32L051xx) \|\| defined(STM32L061xx) \|\| defined(STM32L071xx) \|\| defined(STM32L081xx) \|\| \
mbed_official	489:119543c9f674	743	defined(STM32L031xx) \|\| defined(STM32L041xx)
mbed_official	489:119543c9f674	744
mbed_official	376:cb4d9db17537	745	/** @brief Enable or disable the APB2 peripheral clock.
mbed_official	376:cb4d9db17537	746	* @note After reset, the peripheral clock (used for registers read/write access)
mbed_official	376:cb4d9db17537	747	* is disabled and the application software has to enable this clock before
mbed_official	376:cb4d9db17537	748	* using it.
mbed_official	376:cb4d9db17537	749	*/
mbed_official	489:119543c9f674	750	#define __HAL_RCC_TIM21_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_TIM21EN))
mbed_official	489:119543c9f674	751	#define __HAL_RCC_TIM22_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_TIM22EN))
mbed_official	489:119543c9f674	752	#define __HAL_RCC_FIREWALL_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_MIFIEN))
mbed_official	489:119543c9f674	753	#define __HAL_RCC_ADC1_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_ADC1EN))
mbed_official	489:119543c9f674	754	#define __HAL_RCC_SPI1_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_SPI1EN))
mbed_official	489:119543c9f674	755	#define __HAL_RCC_USART1_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_USART1EN))
mbed_official	376:cb4d9db17537	756
mbed_official	489:119543c9f674	757	#define __HAL_RCC_TIM21_CLK_DISABLE() (RCC->APB2ENR &= ~ (RCC_APB2ENR_TIM21EN))
mbed_official	489:119543c9f674	758	#define __HAL_RCC_TIM22_CLK_DISABLE() (RCC->APB2ENR &= ~ (RCC_APB2ENR_TIM22EN))
mbed_official	489:119543c9f674	759	#define __HAL_RCC_FIREWALL_CLK_DISABLE() (RCC->APB2ENR &= ~ (RCC_APB2ENR_MIFIEN))
mbed_official	489:119543c9f674	760	#define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~ (RCC_APB2ENR_ADC1EN))
mbed_official	489:119543c9f674	761	#define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~ (RCC_APB2ENR_SPI1EN))
mbed_official	489:119543c9f674	762	#define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~ (RCC_APB2ENR_USART1EN))
mbed_official	489:119543c9f674	763	#endif /* STM32L051xx \|\| STM32L061xx \|\| STM32L071xx \|\| STM32L081xx \|\| */
mbed_official	489:119543c9f674	764	/* STM32L052xx \|\| STM32L062xx \|\| STM32L072xx \|\| STM32L082xx \|\| */
mbed_official	489:119543c9f674	765	/* STM32L053xx \|\| STM32L063xx \|\| STM32L073xx \|\| STM32L083xx */
mbed_official	376:cb4d9db17537	766
mbed_official	376:cb4d9db17537	767	/** @brief Force or release AHB peripheral reset.
mbed_official	376:cb4d9db17537	768	*/
mbed_official	489:119543c9f674	769	#if defined(STM32L062xx) \|\| defined(STM32L063xx)\|\| defined(STM32L082xx) \|\| defined(STM32L083xx)
mbed_official	489:119543c9f674	770	#define __HAL_RCC_AES_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_CRYPRST))
mbed_official	489:119543c9f674	771	#define __HAL_RCC_AES_RELEASE_RESET() (RCC->AHBRSTR &= ~ (RCC_AHBRSTR_CRYPRST))
mbed_official	489:119543c9f674	772	#endif /* STM32L062xx \|\| STM32L063xx \|\| STM32L072xx \|\| STM32L073xx \|\| STM32L082xx \|\| STM32L083xx */
mbed_official	489:119543c9f674	773
mbed_official	489:119543c9f674	774	#if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
mbed_official	489:119543c9f674	775	#define __HAL_RCC_TSC_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_TSCRST))
mbed_official	489:119543c9f674	776	#define __HAL_RCC_TSC_RELEASE_RESET() (RCC->AHBRSTR &= ~ (RCC_AHBRSTR_TSCRST))
mbed_official	489:119543c9f674	777	#define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_RNGRST))
mbed_official	489:119543c9f674	778	#define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHBRSTR &= ~ (RCC_AHBRSTR_RNGRST))
mbed_official	489:119543c9f674	779	#endif /* !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
mbed_official	376:cb4d9db17537	780
mbed_official	489:119543c9f674	781	/** @brief Force or release IOPORT peripheral reset.
mbed_official	489:119543c9f674	782	*/
mbed_official	489:119543c9f674	783	#if defined(STM32L073xx) \|\| defined(STM32L083xx) \|\| \
mbed_official	489:119543c9f674	784	defined(STM32L072xx) \|\| defined(STM32L082xx) \|\| \
mbed_official	489:119543c9f674	785	defined(STM32L071xx) \|\| defined(STM32L081xx)
mbed_official	489:119543c9f674	786	#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->IOPRSTR \|= (RCC_IOPRSTR_GPIOERST))
mbed_official	376:cb4d9db17537	787
mbed_official	489:119543c9f674	788	#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->IOPRSTR &= ~(RCC_IOPRSTR_GPIOERST))
mbed_official	489:119543c9f674	789
mbed_official	489:119543c9f674	790	#endif /* STM32L071xx \|\| STM32L081xx \|\| */
mbed_official	489:119543c9f674	791	/* STM32L072xx \|\| STM32L082xx \|\| */
mbed_official	489:119543c9f674	792	/* STM32L073xx \|\| STM32L083xx */
mbed_official	489:119543c9f674	793
mbed_official	376:cb4d9db17537	794	/** @brief Force or release APB1 peripheral reset.
mbed_official	376:cb4d9db17537	795	*/
mbed_official	489:119543c9f674	796
mbed_official	376:cb4d9db17537	797	#if defined(STM32L053xx) \|\| defined(STM32L063xx) \|\| \
mbed_official	376:cb4d9db17537	798	defined(STM32L052xx) \|\| defined(STM32L062xx) \|\| \
mbed_official	489:119543c9f674	799	defined(STM32L051xx) \|\| defined(STM32L061xx)
mbed_official	489:119543c9f674	800	#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM2RST))
mbed_official	489:119543c9f674	801	#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM6RST))
mbed_official	489:119543c9f674	802	#define __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_LPTIM1RST))
mbed_official	489:119543c9f674	803	#define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C1RST))
mbed_official	489:119543c9f674	804	#define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C2RST))
mbed_official	489:119543c9f674	805	#define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART2RST))
mbed_official	489:119543c9f674	806	#define __HAL_RCC_LPUART1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_LPUART1RST))
mbed_official	489:119543c9f674	807	#define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI2RST))
mbed_official	489:119543c9f674	808	#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_DACRST))
mbed_official	376:cb4d9db17537	809
mbed_official	489:119543c9f674	810	#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_TIM2RST))
mbed_official	489:119543c9f674	811	#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_TIM6RST))
mbed_official	489:119543c9f674	812	#define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_LPTIM1RST))
mbed_official	489:119543c9f674	813	#define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_I2C1RST))
mbed_official	489:119543c9f674	814	#define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_I2C2RST))
mbed_official	489:119543c9f674	815	#define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_USART2RST))
mbed_official	489:119543c9f674	816	#define __HAL_RCC_LPUART1_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_LPUART1RST))
mbed_official	489:119543c9f674	817	#define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_SPI2RST))
mbed_official	489:119543c9f674	818	#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_DACRST))
mbed_official	376:cb4d9db17537	819	#endif /* STM32L051xx \|\| STM32L061xx \|\| */
mbed_official	376:cb4d9db17537	820	/* STM32L052xx \|\| STM32L062xx \|\| */
mbed_official	489:119543c9f674	821	/* STM32L053xx \|\| STM32L063xx */
mbed_official	489:119543c9f674	822	#if defined(STM32L031xx) \|\| defined(STM32L041xx)
mbed_official	489:119543c9f674	823	#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM2RST))
mbed_official	489:119543c9f674	824	#define __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_LPTIM1RST))
mbed_official	489:119543c9f674	825	#define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C1RST))
mbed_official	489:119543c9f674	826	#define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART2RST))
mbed_official	489:119543c9f674	827	#define __HAL_RCC_LPUART1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_LPUART1RST))
mbed_official	489:119543c9f674	828
mbed_official	489:119543c9f674	829	#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_TIM2RST))
mbed_official	489:119543c9f674	830	#define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_LPTIM1RST))
mbed_official	489:119543c9f674	831	#define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_I2C1RST))
mbed_official	489:119543c9f674	832	#define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_USART2RST))
mbed_official	489:119543c9f674	833	#define __HAL_RCC_LPUART1_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_LPUART1RST))
mbed_official	489:119543c9f674	834	#endif /* STM32L031xx \|\| STM32L041xx \|\| */
mbed_official	376:cb4d9db17537	835
mbed_official	489:119543c9f674	836	#if defined(STM32L073xx) \|\| defined(STM32L083xx) \|\| \
mbed_official	489:119543c9f674	837	defined(STM32L072xx) \|\| defined(STM32L082xx) \|\| \
mbed_official	489:119543c9f674	838	defined(STM32L071xx) \|\| defined(STM32L081xx)
mbed_official	489:119543c9f674	839	#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM2RST))
mbed_official	489:119543c9f674	840	#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM3RST))
mbed_official	489:119543c9f674	841	#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM6RST))
mbed_official	489:119543c9f674	842	#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM7RST))
mbed_official	489:119543c9f674	843	#define __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_LPTIM1RST))
mbed_official	489:119543c9f674	844	#define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C1RST))
mbed_official	489:119543c9f674	845	#define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C2RST))
mbed_official	489:119543c9f674	846	#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C3RST))
mbed_official	489:119543c9f674	847	#define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART2RST))
mbed_official	489:119543c9f674	848	#define __HAL_RCC_USART4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART4RST))
mbed_official	489:119543c9f674	849	#define __HAL_RCC_USART5_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART5RST))
mbed_official	489:119543c9f674	850	#define __HAL_RCC_LPUART1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_LPUART1RST))
mbed_official	489:119543c9f674	851	#define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI2RST))
mbed_official	489:119543c9f674	852	#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_DACRST))
mbed_official	376:cb4d9db17537	853
mbed_official	489:119543c9f674	854	#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_TIM2RST))
mbed_official	489:119543c9f674	855	#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_TIM3RST))
mbed_official	489:119543c9f674	856	#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_TIM6RST))
mbed_official	489:119543c9f674	857	#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_TIM7RST))
mbed_official	489:119543c9f674	858	#define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_LPTIM1RST))
mbed_official	489:119543c9f674	859	#define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_I2C1RST))
mbed_official	489:119543c9f674	860	#define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_I2C2RST))
mbed_official	489:119543c9f674	861	#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_I2C3RST))
mbed_official	489:119543c9f674	862	#define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_USART2RST))
mbed_official	489:119543c9f674	863	#define __HAL_RCC_USART4_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_USART4RST))
mbed_official	489:119543c9f674	864	#define __HAL_RCC_USART5_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_USART5RST))
mbed_official	489:119543c9f674	865	#define __HAL_RCC_LPUART1_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_LPUART1RST))
mbed_official	489:119543c9f674	866	#define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_SPI2RST))
mbed_official	489:119543c9f674	867	#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_DACRST))
mbed_official	489:119543c9f674	868	#endif /* STM32L071xx \|\| STM32L081xx \|\| */
mbed_official	489:119543c9f674	869	/* STM32L072xx \|\| STM32L082xx \|\| */
mbed_official	489:119543c9f674	870	/* STM32L073xx \|\| STM32L083xx \|\| */
mbed_official	489:119543c9f674	871
mbed_official	489:119543c9f674	872	#if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
mbed_official	489:119543c9f674	873	#define __HAL_RCC_USB_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USBRST))
mbed_official	489:119543c9f674	874	#define __HAL_RCC_USB_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_USBRST))
mbed_official	489:119543c9f674	875	#define __HAL_RCC_CRS_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CRSRST))
mbed_official	489:119543c9f674	876	#define __HAL_RCC_CRS_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CRSRST))
mbed_official	489:119543c9f674	877	#endif /* !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
mbed_official	489:119543c9f674	878
mbed_official	489:119543c9f674	879	#if defined(STM32L053xx) \|\| defined(STM32L063xx) \|\| defined(STM32L073xx) \|\| defined(STM32L083xx)
mbed_official	489:119543c9f674	880	#define __HAL_RCC_LCD_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_LCDRST))
mbed_official	489:119543c9f674	881	#define __HAL_RCC_LCD_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_LCDRST))
mbed_official	489:119543c9f674	882	#endif /* STM32L053xx \|\| STM32L063xx \|\| STM32L073xx \|\| STM32L083xx */
mbed_official	489:119543c9f674	883
mbed_official	489:119543c9f674	884	#if defined(STM32L053xx) \|\| defined(STM32L063xx) \|\| defined(STM32L073xx) \|\| defined(STM32L083xx) \|\| \
mbed_official	489:119543c9f674	885	defined(STM32L052xx) \|\| defined(STM32L062xx) \|\| defined(STM32L072xx) \|\| defined(STM32L082xx) \|\| \
mbed_official	489:119543c9f674	886	defined(STM32L051xx) \|\| defined(STM32L061xx) \|\| defined(STM32L071xx) \|\| defined(STM32L081xx)
mbed_official	489:119543c9f674	887	/** @brief Force or release APB2 peripheral reset.
mbed_official	376:cb4d9db17537	888	*/
mbed_official	489:119543c9f674	889	#define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_USART1RST))
mbed_official	489:119543c9f674	890	#define __HAL_RCC_ADC1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_ADC1RST))
mbed_official	489:119543c9f674	891	#define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI1RST))
mbed_official	489:119543c9f674	892	#define __HAL_RCC_TIM21_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM21RST))
mbed_official	489:119543c9f674	893	#define __HAL_RCC_TIM22_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM22RST))
mbed_official	376:cb4d9db17537	894
mbed_official	489:119543c9f674	895	#define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~ (RCC_APB2RSTR_USART1RST))
mbed_official	489:119543c9f674	896	#define __HAL_RCC_ADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~ (RCC_APB2RSTR_ADC1RST))
mbed_official	489:119543c9f674	897	#define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~ (RCC_APB2RSTR_SPI1RST))
mbed_official	489:119543c9f674	898	#define __HAL_RCC_TIM21_RELEASE_RESET() (RCC->APB2RSTR &= ~ (RCC_APB2RSTR_TIM21RST))
mbed_official	489:119543c9f674	899	#define __HAL_RCC_TIM22_RELEASE_RESET() (RCC->APB2RSTR &= ~ (RCC_APB2RSTR_TIM22RST))
mbed_official	489:119543c9f674	900	#endif /* STM32L051xx \|\| STM32L061xx \|\| STM32L071xx \|\| STM32L081xx \|\| */
mbed_official	489:119543c9f674	901	/* STM32L052xx \|\| STM32L062xx \|\| STM32L072xx \|\| STM32L082xx \|\| */
mbed_official	489:119543c9f674	902	/* STM32L053xx \|\| STM32L063xx \|\| STM32L073xx \|\| STM32L083xx \|\| */
mbed_official	376:cb4d9db17537	903
mbed_official	376:cb4d9db17537	904	/** @brief Enable or disable the AHB peripheral clock during Low Power (Sleep) mode.
mbed_official	376:cb4d9db17537	905	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
mbed_official	376:cb4d9db17537	906	* power consumption.
mbed_official	376:cb4d9db17537	907	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
mbed_official	376:cb4d9db17537	908	* @note By default, all peripheral clocks are enabled during SLEEP mode.
mbed_official	376:cb4d9db17537	909	*/
mbed_official	376:cb4d9db17537	910
mbed_official	489:119543c9f674	911	#if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
mbed_official	489:119543c9f674	912	#define __HAL_RCC_TSC_CLK_SLEEP_ENABLE() (RCC->AHBSMENR \|= (RCC_AHBSMENR_TSCSMEN))
mbed_official	489:119543c9f674	913	#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHBSMENR \|= (RCC_AHBSMENR_RNGSMEN))
mbed_official	489:119543c9f674	914	#define __HAL_RCC_TSC_CLK_SLEEP_DISABLE() (RCC->AHBSMENR &= ~ (RCC_AHBSMENR_TSCSMEN))
mbed_official	489:119543c9f674	915	#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHBSMENR &= ~ (RCC_AHBSMENR_RNGSMEN))
mbed_official	489:119543c9f674	916	#endif /* !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
mbed_official	376:cb4d9db17537	917
mbed_official	489:119543c9f674	918	#if defined(STM32L062xx) \|\| defined(STM32L063xx)\|\| defined(STM32L082xx) \|\| defined(STM32L083xx)
mbed_official	489:119543c9f674	919	#define __HAL_RCC_AES_CLK_SLEEP_ENABLE() (RCC->AHBLPENR \|= (RCC_AHBSMENR_CRYPSMEN))
mbed_official	489:119543c9f674	920	#define __HAL_RCC_AES_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~ (RCC_AHBSMENR_CRYPSMEN))
mbed_official	489:119543c9f674	921	#endif /* STM32L062xx \|\| STM32L063xx \|\| STM32L072xx \|\| STM32L073xx \|\| STM32L082xx \|\| STM32L083xx */
mbed_official	376:cb4d9db17537	922
mbed_official	489:119543c9f674	923	#if defined(STM32L073xx) \|\| defined(STM32L083xx) \|\| \
mbed_official	489:119543c9f674	924	defined(STM32L072xx) \|\| defined(STM32L082xx) \|\| \
mbed_official	489:119543c9f674	925	defined(STM32L071xx) \|\| defined(STM32L081xx)
mbed_official	489:119543c9f674	926	/** @brief Enable or disable the IOPORT peripheral clock during Low Power (Sleep) mode.
mbed_official	489:119543c9f674	927	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
mbed_official	489:119543c9f674	928	* power consumption.
mbed_official	489:119543c9f674	929	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
mbed_official	489:119543c9f674	930	* @note By default, all peripheral clocks are enabled during SLEEP mode.
mbed_official	489:119543c9f674	931	*/
mbed_official	489:119543c9f674	932
mbed_official	489:119543c9f674	933	#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->IOPSMENR \|= (RCC_IOPSMENR_GPIOESMEN))
mbed_official	489:119543c9f674	934	#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->IOPSMENR &= ~(RCC_IOPSMENR_GPIOESMEN))
mbed_official	489:119543c9f674	935
mbed_official	489:119543c9f674	936	#endif /* STM32L071xx \|\| STM32L081xx \|\| */
mbed_official	489:119543c9f674	937	/* STM32L072xx \|\| STM32L082xx \|\| */
mbed_official	489:119543c9f674	938	/* STM32L073xx \|\| STM32L083xx \|\| */
mbed_official	376:cb4d9db17537	939
mbed_official	376:cb4d9db17537	940	/** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
mbed_official	376:cb4d9db17537	941	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
mbed_official	376:cb4d9db17537	942	* power consumption.
mbed_official	376:cb4d9db17537	943	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
mbed_official	376:cb4d9db17537	944	* @note By default, all peripheral clocks are enabled during SLEEP mode.
mbed_official	376:cb4d9db17537	945	*/
mbed_official	376:cb4d9db17537	946
mbed_official	376:cb4d9db17537	947	#if defined(STM32L053xx) \|\| defined(STM32L063xx) \|\| \
mbed_official	376:cb4d9db17537	948	defined(STM32L052xx) \|\| defined(STM32L062xx) \|\| \
mbed_official	489:119543c9f674	949	defined(STM32L051xx) \|\| defined(STM32L061xx)
mbed_official	489:119543c9f674	950	#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1SMENR \|= (RCC_APB1SMENR_TIM2SMEN))
mbed_official	489:119543c9f674	951	#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1SMENR \|= (RCC_APB1SMENR_TIM6SMEN))
mbed_official	489:119543c9f674	952	#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->APB1SMENR \|= (RCC_APB1SMENR_SPI2SMEN))
mbed_official	489:119543c9f674	953	#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->APB1SMENR \|= (RCC_APB1SMENR_USART2SMEN))
mbed_official	489:119543c9f674	954	#define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() (RCC->APB1SMENR \|= (RCC_APB1SMENR_LPUART1SMEN))
mbed_official	489:119543c9f674	955	#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->APB1SMENR \|= (RCC_APB1SMENR_I2C1SMEN))
mbed_official	489:119543c9f674	956	#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->APB1SMENR \|= (RCC_APB1SMENR_I2C2SMEN))
mbed_official	489:119543c9f674	957	#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1SMENR \|= (RCC_APB1SMENR_DACSMEN))
mbed_official	489:119543c9f674	958	#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->APB1SMENR \|= (RCC_APB1SMENR_LPTIM1SMEN))
mbed_official	376:cb4d9db17537	959
mbed_official	489:119543c9f674	960	#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_TIM2SMEN))
mbed_official	489:119543c9f674	961	#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_TIM6SMEN))
mbed_official	489:119543c9f674	962	#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_SPI2SMEN))
mbed_official	489:119543c9f674	963	#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_USART2SMEN))
mbed_official	489:119543c9f674	964	#define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_LPUART1SMEN))
mbed_official	489:119543c9f674	965	#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_I2C1SMEN))
mbed_official	489:119543c9f674	966	#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_I2C2SMEN))
mbed_official	489:119543c9f674	967	#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_DACSMEN))
mbed_official	489:119543c9f674	968	#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_LPTIM1SMEN))
mbed_official	376:cb4d9db17537	969	#endif /* STM32L051xx \|\| STM32L061xx \|\| */
mbed_official	376:cb4d9db17537	970	/* STM32L052xx \|\| STM32L062xx \|\| */
mbed_official	489:119543c9f674	971	/* STM32L053xx \|\| STM32L063xx */
mbed_official	376:cb4d9db17537	972
mbed_official	489:119543c9f674	973	#if defined(STM32L073xx) \|\| defined(STM32L083xx) \|\| \
mbed_official	489:119543c9f674	974	defined(STM32L072xx) \|\| defined(STM32L082xx) \|\| \
mbed_official	489:119543c9f674	975	defined(STM32L071xx) \|\| defined(STM32L081xx)
mbed_official	489:119543c9f674	976	#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1SMENR \|= (RCC_APB1SMENR_TIM2SMEN))
mbed_official	489:119543c9f674	977	#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1SMENR \|= (RCC_APB1SMENR_TIM3SMEN))
mbed_official	489:119543c9f674	978	#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1SMENR \|= (RCC_APB1SMENR_TIM6SMEN))
mbed_official	489:119543c9f674	979	#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1SMENR \|= (RCC_APB1SMENR_TIM7SMEN))
mbed_official	489:119543c9f674	980	#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->APB1SMENR \|= (RCC_APB1SMENR_SPI2SMEN))
mbed_official	489:119543c9f674	981	#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->APB1SMENR \|= (RCC_APB1SMENR_USART2SMEN))
mbed_official	489:119543c9f674	982	#define __HAL_RCC_USART4_CLK_SLEEP_ENABLE() (RCC->APB1SMENR \|= (RCC_APB1SMENR_USART4SMEN))
mbed_official	489:119543c9f674	983	#define __HAL_RCC_USART5_CLK_SLEEP_ENABLE() (RCC->APB1SMENR \|= (RCC_APB1SMENR_USART5SMEN))
mbed_official	489:119543c9f674	984	#define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() (RCC->APB1SMENR \|= (RCC_APB1SMENR_LPUART1SMEN))
mbed_official	489:119543c9f674	985	#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->APB1SMENR \|= (RCC_APB1SMENR_I2C1SMEN))
mbed_official	489:119543c9f674	986	#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->APB1SMENR \|= (RCC_APB1SMENR_I2C2SMEN))
mbed_official	489:119543c9f674	987	#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1SMENR \|= (RCC_APB1SMENR_I2C3SMEN))
mbed_official	489:119543c9f674	988	#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1SMENR \|= (RCC_APB1SMENR_DACSMEN))
mbed_official	489:119543c9f674	989	#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->APB1SMENR \|= (RCC_APB1SMENR_LPTIM1SMEN))
mbed_official	376:cb4d9db17537	990
mbed_official	489:119543c9f674	991	#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_TIM2SMEN))
mbed_official	489:119543c9f674	992	#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_TIM3SMEN))
mbed_official	489:119543c9f674	993	#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_TIM6SMEN))
mbed_official	489:119543c9f674	994	#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_TIM7SMEN))
mbed_official	489:119543c9f674	995	#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_SPI2SMEN))
mbed_official	489:119543c9f674	996	#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_USART2SMEN))
mbed_official	489:119543c9f674	997	#define __HAL_RCC_USART4_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_USART4SMEN))
mbed_official	489:119543c9f674	998	#define __HAL_RCC_USART5_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_USART5SMEN))
mbed_official	489:119543c9f674	999	#define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_LPUART1SMEN))
mbed_official	489:119543c9f674	1000	#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_I2C1SMEN))
mbed_official	489:119543c9f674	1001	#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_I2C2SMEN))
mbed_official	489:119543c9f674	1002	#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_I2C3SMEN))
mbed_official	489:119543c9f674	1003	#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_DACSMEN))
mbed_official	489:119543c9f674	1004	#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_LPTIM1SMEN))
mbed_official	489:119543c9f674	1005	#endif /* STM32L071xx \|\| STM32L081xx \|\| */
mbed_official	489:119543c9f674	1006	/* STM32L072xx \|\| STM32L082xx \|\| */
mbed_official	489:119543c9f674	1007	/* STM32L073xx \|\| STM32L083xx \|\| */
mbed_official	489:119543c9f674	1008
mbed_official	489:119543c9f674	1009	#if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
mbed_official	489:119543c9f674	1010	#define __HAL_RCC_USB_CLK_SLEEP_ENABLE() (RCC->APB1SMENR \|= (RCC_APB1SMENR_USBSMEN))
mbed_official	489:119543c9f674	1011	#define __HAL_RCC_USB_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_USBSMEN))
mbed_official	489:119543c9f674	1012	#define __HAL_RCC_CRS_CLK_SLEEP_ENABLE() (RCC->APB1SMENR \|= (RCC_APB1SMENR_CRSSMEN))
mbed_official	489:119543c9f674	1013	#define __HAL_RCC_CRS_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_CRSSMEN))
mbed_official	489:119543c9f674	1014	#endif /* !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
mbed_official	376:cb4d9db17537	1015
mbed_official	489:119543c9f674	1016	#if defined(STM32L053xx) \|\| defined(STM32L063xx) \|\| defined(STM32L073xx) \|\| defined(STM32L083xx)
mbed_official	489:119543c9f674	1017	#define __HAL_RCC_LCD_CLK_SLEEP_ENABLE() (RCC->APB1SMENR \|= (RCC_APB1SMENR_LCDSMEN))
mbed_official	489:119543c9f674	1018	#define __HAL_RCC_LCD_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_LCDSMEN))
mbed_official	489:119543c9f674	1019	#endif /* STM32L053xx \|\| STM32L063xx \|\| STM32L073xx \|\| STM32L083xx */
mbed_official	376:cb4d9db17537	1020
mbed_official	489:119543c9f674	1021	#if defined(STM32L053xx) \|\| defined(STM32L063xx) \|\| defined(STM32L073xx) \|\| defined(STM32L083xx) \|\| \
mbed_official	489:119543c9f674	1022	defined(STM32L052xx) \|\| defined(STM32L062xx) \|\| defined(STM32L072xx) \|\| defined(STM32L082xx) \|\| \
mbed_official	489:119543c9f674	1023	defined(STM32L051xx) \|\| defined(STM32L061xx) \|\| defined(STM32L071xx) \|\| defined(STM32L081xx)
mbed_official	376:cb4d9db17537	1024	/** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
mbed_official	376:cb4d9db17537	1025	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
mbed_official	376:cb4d9db17537	1026	* power consumption.
mbed_official	376:cb4d9db17537	1027	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
mbed_official	376:cb4d9db17537	1028	* @note By default, all peripheral clocks are enabled during SLEEP mode.
mbed_official	376:cb4d9db17537	1029	*/
mbed_official	489:119543c9f674	1030	#define __HAL_RCC_TIM21_CLK_SLEEP_ENABLE() (RCC->APB2SMENR \|= (RCC_APB2SMENR_TIM21SMEN))
mbed_official	489:119543c9f674	1031	#define __HAL_RCC_TIM22_CLK_SLEEP_ENABLE() (RCC->APB2SMENR \|= (RCC_APB2SMENR_TIM22SMEN))
mbed_official	489:119543c9f674	1032	#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE() (RCC->APB2SMENR \|= (RCC_APB2SMENR_ADC1SMEN))
mbed_official	489:119543c9f674	1033	#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() (RCC->APB2SMENR \|= (RCC_APB2SMENR_SPI1SMEN))
mbed_official	489:119543c9f674	1034	#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->APB2SMENR \|= (RCC_APB2SMENR_USART1SMEN))
mbed_official	376:cb4d9db17537	1035
mbed_official	489:119543c9f674	1036	#define __HAL_RCC_TIM21_CLK_SLEEP_DISABLE() (RCC->APB2SMENR &= ~ (RCC_APB2SMENR_TIM21SMEN))
mbed_official	489:119543c9f674	1037	#define __HAL_RCC_TIM22_CLK_SLEEP_DISABLE() (RCC->APB2SMENR &= ~ (RCC_APB2SMENR_TIM22SMEN))
mbed_official	489:119543c9f674	1038	#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE() (RCC->APB2SMENR &= ~ (RCC_APB2SMENR_ADC1SMEN))
mbed_official	489:119543c9f674	1039	#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() (RCC->APB2SMENR &= ~ (RCC_APB2SMENR_SPI1SMEN))
mbed_official	489:119543c9f674	1040	#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->APB2SMENR &= ~ (RCC_APB2SMENR_USART1SMEN))
mbed_official	489:119543c9f674	1041	#endif /* STM32L051xx \|\| STM32L061xx \|\| STM32L071xx \|\| STM32L081xx \|\| */
mbed_official	489:119543c9f674	1042	/* STM32L052xx \|\| STM32L062xx \|\| STM32L072xx \|\| STM32L082xx \|\| */
mbed_official	489:119543c9f674	1043	/* STM32L053xx \|\| STM32L063xx \|\| STM32L073xx \|\| STM32L083xx \|\| */
mbed_official	376:cb4d9db17537	1044
mbed_official	376:cb4d9db17537	1045	/** @brief macro to configure the I2C1 clock (I2C1CLK).
mbed_official	376:cb4d9db17537	1046	*
mbed_official	376:cb4d9db17537	1047	* @param __I2C1CLKSource__: specifies the I2C1 clock source.
mbed_official	376:cb4d9db17537	1048	* This parameter can be one of the following values:
mbed_official	376:cb4d9db17537	1049	* @arg RCC_I2C1CLKSOURCE_PCLK1: PCLK1 selected as I2C1 clock
mbed_official	376:cb4d9db17537	1050	* @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
mbed_official	376:cb4d9db17537	1051	* @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock
mbed_official	376:cb4d9db17537	1052	*/
mbed_official	376:cb4d9db17537	1053	#define __HAL_RCC_I2C1_CONFIG(__I2C1CLKSource__) \
mbed_official	376:cb4d9db17537	1054	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C1SEL, (uint32_t)(__I2C1CLKSource__))
mbed_official	376:cb4d9db17537	1055
mbed_official	376:cb4d9db17537	1056	/** @brief macro to get the I2C1 clock source.
mbed_official	376:cb4d9db17537	1057	* @retval The clock source can be one of the following values:
mbed_official	376:cb4d9db17537	1058	* @arg RCC_I2C1CLKSOURCE_PCLK1: PCLK1 selected as I2C1 clock
mbed_official	376:cb4d9db17537	1059	* @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
mbed_official	376:cb4d9db17537	1060	* @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock
mbed_official	376:cb4d9db17537	1061	*/
mbed_official	376:cb4d9db17537	1062	#define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C1SEL)))
mbed_official	376:cb4d9db17537	1063
mbed_official	489:119543c9f674	1064	#if defined (STM32L073xx) \|\| defined(STM32L083xx) \|\| \
mbed_official	489:119543c9f674	1065	defined(STM32L072xx) \|\| defined(STM32L082xx) \|\| \
mbed_official	489:119543c9f674	1066	defined(STM32L071xx) \|\| defined(STM32L081xx)
mbed_official	489:119543c9f674	1067	/** @brief macro to configure the I2C3 clock (I2C3CLK).
mbed_official	489:119543c9f674	1068	*
mbed_official	489:119543c9f674	1069	* @param __I2C3CLKSource__: specifies the I2C3 clock source.
mbed_official	489:119543c9f674	1070	* This parameter can be one of the following values:
mbed_official	489:119543c9f674	1071	* @arg RCC_I2C3CLKSOURCE_PCLK1: PCLK1 selected as I2C3 clock
mbed_official	489:119543c9f674	1072	* @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock
mbed_official	489:119543c9f674	1073	* @arg RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock
mbed_official	489:119543c9f674	1074	*/
mbed_official	489:119543c9f674	1075	#define __HAL_RCC_I2C3_CONFIG(__I2C3CLKSource__) \
mbed_official	489:119543c9f674	1076	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C3SEL, (uint32_t)(__I2C3CLKSource__))
mbed_official	489:119543c9f674	1077
mbed_official	489:119543c9f674	1078	/** @brief macro to get the I2C3 clock source.
mbed_official	489:119543c9f674	1079	* @retval The clock source can be one of the following values:
mbed_official	489:119543c9f674	1080	* @arg RCC_I2C3CLKSOURCE_PCLK1: PCLK1 selected as I2C3 clock
mbed_official	489:119543c9f674	1081	* @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock
mbed_official	489:119543c9f674	1082	* @arg RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock
mbed_official	489:119543c9f674	1083	*/
mbed_official	489:119543c9f674	1084	#define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C3SEL)))
mbed_official	489:119543c9f674	1085
mbed_official	489:119543c9f674	1086	#endif /* STM32L071xx \|\| STM32L081xx \|\| */
mbed_official	489:119543c9f674	1087	/* STM32L072xx \|\| STM32L082xx \|\| */
mbed_official	489:119543c9f674	1088	/* STM32L073xx \|\| STM32L083xx \|\| */
mbed_official	489:119543c9f674	1089
mbed_official	376:cb4d9db17537	1090	/** @brief macro to configure the USART1 clock (USART1CLK).
mbed_official	376:cb4d9db17537	1091	*
mbed_official	376:cb4d9db17537	1092	* @param __USART1CLKSource__: specifies the USART1 clock source.
mbed_official	376:cb4d9db17537	1093	* This parameter can be one of the following values:
mbed_official	376:cb4d9db17537	1094	* @arg RCC_USART1CLKSOURCE_PCLK2: PCLK2 selected as USART1 clock
mbed_official	376:cb4d9db17537	1095	* @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
mbed_official	376:cb4d9db17537	1096	* @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock
mbed_official	376:cb4d9db17537	1097	* @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock
mbed_official	376:cb4d9db17537	1098	*/
mbed_official	376:cb4d9db17537	1099	#define __HAL_RCC_USART1_CONFIG(__USART1CLKSource__) \
mbed_official	376:cb4d9db17537	1100	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART1SEL, (uint32_t)(__USART1CLKSource__))
mbed_official	376:cb4d9db17537	1101
mbed_official	376:cb4d9db17537	1102	/** @brief macro to get the USART1 clock source.
mbed_official	376:cb4d9db17537	1103	* @retval The clock source can be one of the following values:
mbed_official	376:cb4d9db17537	1104	* @arg RCC_USART1CLKSOURCE_PCLK2: PCLK2 selected as USART1 clock
mbed_official	376:cb4d9db17537	1105	* @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
mbed_official	376:cb4d9db17537	1106	* @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock
mbed_official	376:cb4d9db17537	1107	* @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock
mbed_official	376:cb4d9db17537	1108	*/
mbed_official	376:cb4d9db17537	1109	#define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART1SEL)))
mbed_official	376:cb4d9db17537	1110
mbed_official	376:cb4d9db17537	1111	/** @brief macro to configure the USART2 clock (USART2CLK).
mbed_official	376:cb4d9db17537	1112	*
mbed_official	376:cb4d9db17537	1113	* @param __USART2CLKSource__: specifies the USART2 clock source.
mbed_official	376:cb4d9db17537	1114	* This parameter can be one of the following values:
mbed_official	376:cb4d9db17537	1115	* @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock
mbed_official	376:cb4d9db17537	1116	* @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
mbed_official	376:cb4d9db17537	1117	* @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock
mbed_official	376:cb4d9db17537	1118	* @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock
mbed_official	376:cb4d9db17537	1119	*/
mbed_official	376:cb4d9db17537	1120	#define __HAL_RCC_USART2_CONFIG(__USART2CLKSource__) \
mbed_official	376:cb4d9db17537	1121	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART2SEL, (uint32_t)(__USART2CLKSource__))
mbed_official	376:cb4d9db17537	1122
mbed_official	376:cb4d9db17537	1123	/** @brief macro to get the USART2 clock source.
mbed_official	376:cb4d9db17537	1124	* @retval The clock source can be one of the following values:
mbed_official	376:cb4d9db17537	1125	* @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock
mbed_official	376:cb4d9db17537	1126	* @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
mbed_official	376:cb4d9db17537	1127	* @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock
mbed_official	376:cb4d9db17537	1128	* @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock
mbed_official	376:cb4d9db17537	1129	*/
mbed_official	376:cb4d9db17537	1130	#define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART2SEL)))
mbed_official	376:cb4d9db17537	1131
mbed_official	376:cb4d9db17537	1132	/** @brief macro to configure the LPUART1 clock (LPUART1CLK).
mbed_official	376:cb4d9db17537	1133	*
mbed_official	376:cb4d9db17537	1134	* @param __LPUART1CLKSource__: specifies the LPUART1 clock source.
mbed_official	376:cb4d9db17537	1135	* This parameter can be one of the following values:
mbed_official	376:cb4d9db17537	1136	* @arg RCC_LPUART1CLKSOURCE_PCLK1: PCLK1 selected as LPUART1 clock
mbed_official	376:cb4d9db17537	1137	* @arg RCC_LPUART1CLKSOURCE_HSI: HSI selected as LPUART1 clock
mbed_official	376:cb4d9db17537	1138	* @arg RCC_LPUART1CLKSOURCE_SYSCLK: System Clock selected as LPUART1 clock
mbed_official	376:cb4d9db17537	1139	* @arg RCC_LPUART1CLKSOURCE_LSE: LSE selected as LPUART1 clock
mbed_official	376:cb4d9db17537	1140	*/
mbed_official	376:cb4d9db17537	1141	#define __HAL_RCC_LPUART1_CONFIG(__LPUART1CLKSource__) \
mbed_official	376:cb4d9db17537	1142	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, (uint32_t)(__LPUART1CLKSource__))
mbed_official	376:cb4d9db17537	1143
mbed_official	376:cb4d9db17537	1144	/** @brief macro to get the LPUART1 clock source.
mbed_official	376:cb4d9db17537	1145	* @retval The clock source can be one of the following values:
mbed_official	376:cb4d9db17537	1146	* @arg RCC_LPUART1CLKSOURCE_PCLK1: PCLK1 selected as LPUART1 clock
mbed_official	376:cb4d9db17537	1147	* @arg RCC_LPUART1CLKSOURCE_HSI: HSI selected as LPUART1 clock
mbed_official	376:cb4d9db17537	1148	* @arg RCC_LPUART1CLKSOURCE_SYSCLK: System Clock selected as LPUART1 clock
mbed_official	376:cb4d9db17537	1149	* @arg RCC_LPUART1CLKSOURCE_LSE: LSE selected as LPUART1 clock
mbed_official	376:cb4d9db17537	1150	*/
mbed_official	376:cb4d9db17537	1151	#define __HAL_RCC_GET_LPUART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPUART1SEL)))
mbed_official	376:cb4d9db17537	1152
mbed_official	376:cb4d9db17537	1153	/** @brief macro to configure the LPTIM1 clock (LPTIM1CLK).
mbed_official	376:cb4d9db17537	1154	*
mbed_official	376:cb4d9db17537	1155	* @param __LPTIM1CLKSource__: specifies the LPTIM1 clock source.
mbed_official	376:cb4d9db17537	1156	* This parameter can be one of the following values:
mbed_official	376:cb4d9db17537	1157	* @arg RCC_LPTIM1CLKSOURCE_PCLK: PCLK selected as LPTIM1 clock
mbed_official	376:cb4d9db17537	1158	* @arg RCC_LPTIM1CLKSOURCE_LSI : HSI selected as LPTIM1 clock
mbed_official	376:cb4d9db17537	1159	* @arg RCC_LPTIM1CLKSOURCE_HSI : LSI selected as LPTIM1 clock
mbed_official	376:cb4d9db17537	1160	* @arg RCC_LPTIM1CLKSOURCE_LSE : LSE selected as LPTIM1 clock
mbed_official	376:cb4d9db17537	1161	*/
mbed_official	376:cb4d9db17537	1162	#define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1CLKSource__) \
mbed_official	376:cb4d9db17537	1163	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL, (uint32_t)(__LPTIM1CLKSource__))
mbed_official	376:cb4d9db17537	1164
mbed_official	376:cb4d9db17537	1165	/** @brief macro to get the LPTIM1 clock source.
mbed_official	376:cb4d9db17537	1166	* @retval The clock source can be one of the following values:
mbed_official	376:cb4d9db17537	1167	* @arg RCC_LPTIM1CLKSOURCE_PCLK: PCLK selected as LPUART1 clock
mbed_official	376:cb4d9db17537	1168	* @arg RCC_LPTIM1CLKSOURCE_LSI : HSI selected as LPUART1 clock
mbed_official	376:cb4d9db17537	1169	* @arg RCC_LPTIM1CLKSOURCE_HSI : System Clock selected as LPUART1 clock
mbed_official	376:cb4d9db17537	1170	* @arg RCC_LPTIM1CLKSOURCE_LSE : LSE selected as LPUART1 clock
mbed_official	376:cb4d9db17537	1171	*/
mbed_official	376:cb4d9db17537	1172	#define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL)))
mbed_official	376:cb4d9db17537	1173
mbed_official	489:119543c9f674	1174	#if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
mbed_official	376:cb4d9db17537	1175	/** @brief Macro to configure the USB clock (USBCLK).
mbed_official	376:cb4d9db17537	1176	* @param __USBCLKSource__: specifies the USB clock source.
mbed_official	376:cb4d9db17537	1177	* This parameter can be one of the following values:
mbed_official	376:cb4d9db17537	1178	* @arg RCC_USBCLKSOURCE_HSI48: HSI48 selected as USB clock
mbed_official	376:cb4d9db17537	1179	* @arg RCC_USBCLKSOURCE_PLLCLK: PLL Clock selected as USB clock
mbed_official	376:cb4d9db17537	1180	*/
mbed_official	376:cb4d9db17537	1181	#define __HAL_RCC_USB_CONFIG(__USBCLKSource__) \
mbed_official	376:cb4d9db17537	1182	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_HSI48SEL, (uint32_t)(__USBCLKSource__))
mbed_official	376:cb4d9db17537	1183
mbed_official	376:cb4d9db17537	1184	/** @brief Macro to get the USB clock source.
mbed_official	376:cb4d9db17537	1185	* @retval The clock source can be one of the following values:
mbed_official	376:cb4d9db17537	1186	* @arg RCC_USBCLKSOURCE_HSI48: HSI48 selected as USB clock
mbed_official	376:cb4d9db17537	1187	* @arg RCC_USBCLKSOURCE_PLLCLK: PLL Clock selected as USB clock
mbed_official	376:cb4d9db17537	1188	*/
mbed_official	376:cb4d9db17537	1189	#define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_HSI48SEL)))
mbed_official	376:cb4d9db17537	1190
mbed_official	376:cb4d9db17537	1191	/** @brief Macro to configure the RNG clock (RNGCLK).
mbed_official	376:cb4d9db17537	1192	* @param __RNGCLKSource__: specifies the USB clock source.
mbed_official	376:cb4d9db17537	1193	* This parameter can be one of the following values:
mbed_official	376:cb4d9db17537	1194	* @arg RCC_RNGCLKSOURCE_HSI48: HSI48 selected as RNG clock
mbed_official	376:cb4d9db17537	1195	* @arg RCC_RNGCLKSOURCE_PLLCLK: PLL Clock selected as RNG clock
mbed_official	376:cb4d9db17537	1196	*/
mbed_official	376:cb4d9db17537	1197	#define __HAL_RCC_RNG_CONFIG(__RNGCLKSource__) \
mbed_official	376:cb4d9db17537	1198	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_HSI48SEL, (uint32_t)(__RNGCLKSource__))
mbed_official	376:cb4d9db17537	1199
mbed_official	376:cb4d9db17537	1200	/** @brief Macro to get the RNG clock source.
mbed_official	376:cb4d9db17537	1201	* @retval The clock source can be one of the following values:
mbed_official	376:cb4d9db17537	1202	* @arg RCC_RNGCLKSOURCE_HSI48: HSI48 selected as RNG clock
mbed_official	376:cb4d9db17537	1203	* @arg RCC_RNGCLKSOURCE_PLLCLK: PLL Clock selected as RNG clock
mbed_official	376:cb4d9db17537	1204	*/
mbed_official	376:cb4d9db17537	1205	#define __HAL_RCC_GET_RNG_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_HSI48SEL)))
mbed_official	376:cb4d9db17537	1206
mbed_official	376:cb4d9db17537	1207	/** @brief macro to select the HSI48M clock source
mbed_official	376:cb4d9db17537	1208	* @note This macro can be replaced by either __HAL_RCC_RNG_CONFIG or
mbed_official	376:cb4d9db17537	1209	* __HAL_RCC_USB_CONFIG to configure respectively RNG or UBS clock sources.
mbed_official	376:cb4d9db17537	1210	*
mbed_official	376:cb4d9db17537	1211	* @param __HSI48MCLKSource__: specifies the HSI48M clock source dedicated for
mbed_official	376:cb4d9db17537	1212	* USB an RNG peripherals.
mbed_official	376:cb4d9db17537	1213	* This parameter can be one of the following values:
mbed_official	376:cb4d9db17537	1214	* @arg RCC_HSI48M_PLL: A dedicated 48MHZ PLL output.
mbed_official	489:119543c9f674	1215	* @arg RCC_HSI48M_HSI48: 48MHZ issued from internal HSI48 oscillator.
mbed_official	376:cb4d9db17537	1216	*/
mbed_official	376:cb4d9db17537	1217	#define __HAL_RCC_HSI48M_CONFIG(__HSI48MCLKSource__) \
mbed_official	376:cb4d9db17537	1218	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_HSI48SEL, (uint32_t)(__HSI48MCLKSource__))
mbed_official	376:cb4d9db17537	1219
mbed_official	376:cb4d9db17537	1220	/** @brief macro to get the HSI48M clock source.
mbed_official	376:cb4d9db17537	1221	* @note This macro can be replaced by either __HAL_RCC_GET_RNG_SOURCE or
mbed_official	376:cb4d9db17537	1222	* __HAL_RCC_GET_USB_SOURCE to get respectively RNG or UBS clock sources.
mbed_official	376:cb4d9db17537	1223	* @retval The clock source can be one of the following values:
mbed_official	376:cb4d9db17537	1224	* @arg RCC_HSI48M_PLL: A dedicated 48MHZ PLL output.
mbed_official	489:119543c9f674	1225	* @arg RCC_HSI48M_HSI48: 48MHZ issued from internal HSI48 oscillator.
mbed_official	376:cb4d9db17537	1226	*/
mbed_official	376:cb4d9db17537	1227	#define __HAL_RCC_GET_HSI48M_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_HSI48SEL)))
mbed_official	489:119543c9f674	1228	#endif /* !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
mbed_official	376:cb4d9db17537	1229
mbed_official	376:cb4d9db17537	1230	/**
mbed_official	376:cb4d9db17537	1231	* @brief Macros to enable or disable the force of the Internal High Speed oscillator (HSI)
mbed_official	376:cb4d9db17537	1232	* in STOP mode to be quickly available as kernel clock for USART and I2C.
mbed_official	376:cb4d9db17537	1233	* @note The Enable of this function has not effect on the HSION bit.
mbed_official	376:cb4d9db17537	1234	* This parameter can be: ENABLE or DISABLE.
mbed_official	376:cb4d9db17537	1235	* @retval None
mbed_official	376:cb4d9db17537	1236	*/
mbed_official	376:cb4d9db17537	1237	#define __HAL_RCC_HSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIKERON)
mbed_official	376:cb4d9db17537	1238	#define __HAL_RCC_HSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON)
mbed_official	376:cb4d9db17537	1239
mbed_official	376:cb4d9db17537	1240	/**
mbed_official	376:cb4d9db17537	1241	* @brief Macro to configures the External Low Speed oscillator (LSE) drive capability.
mbed_official	376:cb4d9db17537	1242	* @param RCC_LSEDrive: specifies the new state of the LSE drive capability.
mbed_official	376:cb4d9db17537	1243	* This parameter can be one of the following values:
mbed_official	376:cb4d9db17537	1244	* @arg RCC_LSEDRIVE_LOW: LSE oscillator low drive capability.
mbed_official	376:cb4d9db17537	1245	* @arg RCC_LSEDRIVE_MEDIUMLOW: LSE oscillator medium low drive capability.
mbed_official	376:cb4d9db17537	1246	* @arg RCC_LSEDRIVE_MEDIUMHIGH: LSE oscillator medium high drive capability.
mbed_official	376:cb4d9db17537	1247	* @arg RCC_LSEDRIVE_HIGH: LSE oscillator high drive capability.
mbed_official	376:cb4d9db17537	1248	* @retval None
mbed_official	376:cb4d9db17537	1249	*/
mbed_official	376:cb4d9db17537	1250	#define __HAL_RCC_LSEDRIVE_CONFIG(__RCC_LSEDrive__) (MODIFY_REG(RCC->CSR,\
mbed_official	376:cb4d9db17537	1251	RCC_CSR_LSEDRV, (uint32_t)(__RCC_LSEDrive__) ))
mbed_official	376:cb4d9db17537	1252
mbed_official	376:cb4d9db17537	1253	/**
mbed_official	376:cb4d9db17537	1254	* @brief Macro to configures the wake up from stop clock.
mbed_official	376:cb4d9db17537	1255	* @param RCC_STOPWUCLK: specifies the clock source used after wake up from stop
mbed_official	376:cb4d9db17537	1256	* This parameter can be one of the following values:
mbed_official	489:119543c9f674	1257	* @arg RCC_STOP_WAKEUPCLOCK_MSI: MSI selected as system clock source
mbed_official	489:119543c9f674	1258	* @arg RCC_STOP_WAKEUPCLOCK_HSI: HSI selected as system clock source
mbed_official	376:cb4d9db17537	1259	* @retval None
mbed_official	376:cb4d9db17537	1260	*/
mbed_official	376:cb4d9db17537	1261	#define __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(__RCC_STOPWUCLK__) (MODIFY_REG(RCC->CFGR,\
mbed_official	376:cb4d9db17537	1262	RCC_CFGR_STOPWUCK, (uint32_t)(__RCC_STOPWUCLK__) ))
mbed_official	376:cb4d9db17537	1263
mbed_official	489:119543c9f674	1264	#if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
mbed_official	376:cb4d9db17537	1265	/**
mbed_official	376:cb4d9db17537	1266	* @brief Enables the specified CRS interrupts.
mbed_official	376:cb4d9db17537	1267	* @param __INTERRUPT__: specifies the CRS interrupt sources to be enabled.
mbed_official	376:cb4d9db17537	1268	* This parameter can be any combination of the following values:
mbed_official	376:cb4d9db17537	1269	* @arg RCC_CRS_IT_SYNCOK
mbed_official	376:cb4d9db17537	1270	* @arg RCC_CRS_IT_SYNCWARN
mbed_official	376:cb4d9db17537	1271	* @arg RCC_CRS_IT_ERR
mbed_official	376:cb4d9db17537	1272	* @arg RCC_CRS_IT_ESYNC
mbed_official	376:cb4d9db17537	1273	* @retval None
mbed_official	376:cb4d9db17537	1274	*/
mbed_official	376:cb4d9db17537	1275	#define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) (CRS->CR \|= (__INTERRUPT__))
mbed_official	376:cb4d9db17537	1276
mbed_official	376:cb4d9db17537	1277	/**
mbed_official	376:cb4d9db17537	1278	* @brief Disables the specified CRS interrupts.
mbed_official	376:cb4d9db17537	1279	* @param __INTERRUPT__: specifies the CRS interrupt sources to be disabled.
mbed_official	376:cb4d9db17537	1280	* This parameter can be any combination of the following values:
mbed_official	376:cb4d9db17537	1281	* @arg RCC_CRS_IT_SYNCOK
mbed_official	376:cb4d9db17537	1282	* @arg RCC_CRS_IT_SYNCWARN
mbed_official	376:cb4d9db17537	1283	* @arg RCC_CRS_IT_ERR
mbed_official	376:cb4d9db17537	1284	* @arg RCC_CRS_IT_ESYNC
mbed_official	376:cb4d9db17537	1285	* @retval None
mbed_official	376:cb4d9db17537	1286	*/
mbed_official	376:cb4d9db17537	1287	#define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) (CRS->CR &= ~(__INTERRUPT__))
mbed_official	376:cb4d9db17537	1288
mbed_official	489:119543c9f674	1289	/** @brief Check the CRS interrupt has occurred or not.
mbed_official	376:cb4d9db17537	1290	* @param __INTERRUPT__: specifies the CRS interrupt source to check.
mbed_official	376:cb4d9db17537	1291	* This parameter can be one of the following values:
mbed_official	376:cb4d9db17537	1292	* @arg RCC_CRS_IT_SYNCOK
mbed_official	376:cb4d9db17537	1293	* @arg RCC_CRS_IT_SYNCWARN
mbed_official	376:cb4d9db17537	1294	* @arg RCC_CRS_IT_ERR
mbed_official	376:cb4d9db17537	1295	* @arg RCC_CRS_IT_ESYNC
mbed_official	376:cb4d9db17537	1296	* @retval The new state of __INTERRUPT__ (SET or RESET).
mbed_official	376:cb4d9db17537	1297	*/
mbed_official	376:cb4d9db17537	1298	#define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((CRS->CR & (__INTERRUPT__))? SET : RESET)
mbed_official	376:cb4d9db17537	1299
mbed_official	489:119543c9f674	1300	/** @brief Clear the CRS interrupt pending bits
mbed_official	376:cb4d9db17537	1301	* bits to clear the selected interrupt pending bits.
mbed_official	376:cb4d9db17537	1302	* @param __INTERRUPT__: specifies the interrupt pending bit to clear.
mbed_official	376:cb4d9db17537	1303	* This parameter can be any combination of the following values:
mbed_official	376:cb4d9db17537	1304	* @arg RCC_CRS_IT_SYNCOK
mbed_official	376:cb4d9db17537	1305	* @arg RCC_CRS_IT_SYNCWARN
mbed_official	376:cb4d9db17537	1306	* @arg RCC_CRS_IT_ERR
mbed_official	376:cb4d9db17537	1307	* @arg RCC_CRS_IT_ESYNC
mbed_official	376:cb4d9db17537	1308	* @arg RCC_CRS_IT_TRIMOVF
mbed_official	376:cb4d9db17537	1309	* @arg RCC_CRS_IT_SYNCERR
mbed_official	376:cb4d9db17537	1310	* @arg RCC_CRS_IT_SYNCMISS
mbed_official	376:cb4d9db17537	1311	*/
mbed_official	376:cb4d9db17537	1312	/* CRS IT Error Mask */
mbed_official	489:119543c9f674	1313	#define RCC_CRS_IT_ERROR_MASK ((uint32_t)(RCC_CRS_IT_TRIMOVF \| RCC_CRS_IT_SYNCERR \| RCC_CRS_IT_SYNCMISS))
mbed_official	376:cb4d9db17537	1314
mbed_official	376:cb4d9db17537	1315	#define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) ((((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK)!= 0) ? (CRS->ICR \|= CRS_ICR_ERRC) : \
mbed_official	376:cb4d9db17537	1316	(CRS->ICR = (__INTERRUPT__)))
mbed_official	376:cb4d9db17537	1317
mbed_official	376:cb4d9db17537	1318	/**
mbed_official	376:cb4d9db17537	1319	* @brief Checks whether the specified CRS flag is set or not.
mbed_official	376:cb4d9db17537	1320	* @param _FLAG_: specifies the flag to check.
mbed_official	376:cb4d9db17537	1321	* This parameter can be one of the following values:
mbed_official	376:cb4d9db17537	1322	* @arg RCC_CRS_FLAG_SYNCOK
mbed_official	376:cb4d9db17537	1323	* @arg RCC_CRS_FLAG_SYNCWARN
mbed_official	376:cb4d9db17537	1324	* @arg RCC_CRS_FLAG_ERR
mbed_official	376:cb4d9db17537	1325	* @arg RCC_CRS_FLAG_ESYNC
mbed_official	376:cb4d9db17537	1326	* @arg RCC_CRS_FLAG_TRIMOVF
mbed_official	376:cb4d9db17537	1327	* @arg RCC_CRS_FLAG_SYNCERR
mbed_official	376:cb4d9db17537	1328	* @arg RCC_CRS_FLAG_SYNCMISS
mbed_official	376:cb4d9db17537	1329	* @retval The new state of _FLAG_ (TRUE or FALSE).
mbed_official	376:cb4d9db17537	1330	*/
mbed_official	489:119543c9f674	1331	#define __HAL_RCC_CRS_GET_FLAG(__FLAG__) ((CRS->ISR & (__FLAG__)) == (__FLAG__))
mbed_official	376:cb4d9db17537	1332
mbed_official	376:cb4d9db17537	1333	/**
mbed_official	376:cb4d9db17537	1334	* @brief Clears the CRS specified FLAG.
mbed_official	376:cb4d9db17537	1335	* @param _FLAG_: specifies the flag to clear.
mbed_official	376:cb4d9db17537	1336	* This parameter can be one of the following values:
mbed_official	376:cb4d9db17537	1337	* @arg RCC_CRS_FLAG_SYNCOK
mbed_official	376:cb4d9db17537	1338	* @arg RCC_CRS_FLAG_SYNCWARN
mbed_official	376:cb4d9db17537	1339	* @arg RCC_CRS_FLAG_ERR
mbed_official	376:cb4d9db17537	1340	* @arg RCC_CRS_FLAG_ESYNC
mbed_official	376:cb4d9db17537	1341	* @arg RCC_CRS_FLAG_TRIMOVF
mbed_official	376:cb4d9db17537	1342	* @arg RCC_CRS_FLAG_SYNCERR
mbed_official	376:cb4d9db17537	1343	* @arg RCC_CRS_FLAG_SYNCMISS
mbed_official	376:cb4d9db17537	1344	* @retval None
mbed_official	376:cb4d9db17537	1345	*/
mbed_official	376:cb4d9db17537	1346
mbed_official	376:cb4d9db17537	1347	/* CRS Flag Error Mask */
mbed_official	489:119543c9f674	1348	#define RCC_CRS_FLAG_ERROR_MASK ((uint32_t)(RCC_CRS_FLAG_TRIMOVF \| RCC_CRS_FLAG_SYNCERR \| RCC_CRS_FLAG_SYNCMISS))
mbed_official	376:cb4d9db17537	1349
mbed_official	376:cb4d9db17537	1350	#define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) ((((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK)!= 0) ? (CRS->ICR \|= CRS_ICR_ERRC) : \
mbed_official	376:cb4d9db17537	1351	(CRS->ICR = (__FLAG__)))
mbed_official	376:cb4d9db17537	1352
mbed_official	376:cb4d9db17537	1353
mbed_official	376:cb4d9db17537	1354	/**
mbed_official	376:cb4d9db17537	1355	* @brief Enables the oscillator clock for frequency error counter.
mbed_official	376:cb4d9db17537	1356	* @note when the CEN bit is set the CRS_CFGR register becomes write-protected.
mbed_official	376:cb4d9db17537	1357	* @param None
mbed_official	376:cb4d9db17537	1358	* @retval None
mbed_official	376:cb4d9db17537	1359	*/
mbed_official	376:cb4d9db17537	1360	#define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER() (CRS->CR \|= CRS_CR_CEN)
mbed_official	376:cb4d9db17537	1361
mbed_official	376:cb4d9db17537	1362	/**
mbed_official	376:cb4d9db17537	1363	* @brief Disables the oscillator clock for frequency error counter.
mbed_official	376:cb4d9db17537	1364	* @param None
mbed_official	376:cb4d9db17537	1365	* @retval None
mbed_official	376:cb4d9db17537	1366	*/
mbed_official	376:cb4d9db17537	1367	#define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER() (CRS->CR &= ~CRS_CR_CEN)
mbed_official	376:cb4d9db17537	1368
mbed_official	376:cb4d9db17537	1369	/**
mbed_official	376:cb4d9db17537	1370	* @brief Enables the automatic hardware adjustment of TRIM bits.
mbed_official	376:cb4d9db17537	1371	* @note When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected.
mbed_official	376:cb4d9db17537	1372	* @param None
mbed_official	376:cb4d9db17537	1373	* @retval None
mbed_official	376:cb4d9db17537	1374	*/
mbed_official	376:cb4d9db17537	1375	#define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB() (CRS->CR \|= CRS_CR_AUTOTRIMEN)
mbed_official	376:cb4d9db17537	1376
mbed_official	376:cb4d9db17537	1377	/**
mbed_official	376:cb4d9db17537	1378	* @brief Enables or disables the automatic hardware adjustment of TRIM bits.
mbed_official	376:cb4d9db17537	1379	* @param None
mbed_official	376:cb4d9db17537	1380	* @retval None
mbed_official	376:cb4d9db17537	1381	*/
mbed_official	376:cb4d9db17537	1382	#define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB() (CRS->CR &= ~CRS_CR_AUTOTRIMEN)
mbed_official	376:cb4d9db17537	1383
mbed_official	376:cb4d9db17537	1384	/**
mbed_official	376:cb4d9db17537	1385	* @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies
mbed_official	376:cb4d9db17537	1386	* @note The RELOAD value should be selected according to the ratio between the target frequency and the frequency
mbed_official	376:cb4d9db17537	1387	* of the synchronization source after prescaling. It is then decreased by one in order to
mbed_official	376:cb4d9db17537	1388	* reach the expected synchronization on the zero value. The formula is the following:
mbed_official	376:cb4d9db17537	1389	* RELOAD = (fTARGET / fSYNC) -1
mbed_official	376:cb4d9db17537	1390	* @param _FTARGET_ Target frequency (value in Hz)
mbed_official	376:cb4d9db17537	1391	* @param _FSYNC_ Synchronization signal frequency (value in Hz)
mbed_official	376:cb4d9db17537	1392	* @retval None
mbed_official	376:cb4d9db17537	1393	*/
mbed_official	489:119543c9f674	1394	#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1)
mbed_official	489:119543c9f674	1395
mbed_official	489:119543c9f674	1396	#endif /* !(STM32L031xx) && !(STM32L041xx) && !(STM32L051xx) && !(STM32L061xx) && !(STM32L071xx) && !(STM32L081xx) */
mbed_official	489:119543c9f674	1397
mbed_official	489:119543c9f674	1398	#if defined(STM32L073xx) \|\| defined(STM32L083xx) \|\| \
mbed_official	489:119543c9f674	1399	defined(STM32L072xx) \|\| defined(STM32L082xx) \|\| \
mbed_official	489:119543c9f674	1400	defined(STM32L071xx) \|\| defined(STM32L081xx)
mbed_official	489:119543c9f674	1401	/** @brief Enable or disable the HSI OUT .
mbed_official	489:119543c9f674	1402	* @note After reset, the HSI output is not available
mbed_official	489:119543c9f674	1403	*/
mbed_official	489:119543c9f674	1404
mbed_official	489:119543c9f674	1405	#define __HAL_RCC_HSI_OUT_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIOUTEN)
mbed_official	489:119543c9f674	1406	#define __HAL_RCC_HSI_OUT_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIOUTEN)
mbed_official	489:119543c9f674	1407
mbed_official	489:119543c9f674	1408	#endif /* STM32L071xx \|\| STM32L081xx \|\| */
mbed_official	489:119543c9f674	1409	/* STM32L072xx \|\| STM32L082xx \|\| */
mbed_official	489:119543c9f674	1410	/* STM32L073xx \|\| STM32L083xx */
mbed_official	489:119543c9f674	1411
mbed_official	489:119543c9f674	1412	#if defined(STM32L053xx) \|\| defined(STM32L063xx) \|\| defined(STM32L073xx) \|\| defined(STM32L083xx) \|\|\
mbed_official	489:119543c9f674	1413	defined(STM32L052xx) \|\| defined(STM32L062xx) \|\| defined(STM32L072xx) \|\| defined(STM32L082xx)
mbed_official	376:cb4d9db17537	1414
mbed_official	489:119543c9f674	1415	/**
mbed_official	489:119543c9f674	1416	* @brief Macro to enable or disable the Internal High Speed oscillator for USB (HSI48).
mbed_official	489:119543c9f674	1417	* @note After enabling the HSI48, the application software should wait on
mbed_official	489:119543c9f674	1418	* HSI48RDY flag to be set indicating that HSI48 clock is stable and can
mbed_official	489:119543c9f674	1419	* be used to clock the USB.
mbed_official	489:119543c9f674	1420	* @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes.
mbed_official	489:119543c9f674	1421	*/
mbed_official	489:119543c9f674	1422	#define __HAL_RCC_HSI48_ENABLE() do { SET_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON); \
mbed_official	489:119543c9f674	1423	RCC->APB2ENR \|= RCC_APB2ENR_SYSCFGEN; \
mbed_official	489:119543c9f674	1424	SYSCFG->CFGR3 \|= (SYSCFG_CFGR3_ENREF_HSI48 \| SYSCFG_CFGR3_EN_VREFINT); \
mbed_official	489:119543c9f674	1425	} while (0)
mbed_official	489:119543c9f674	1426	#define __HAL_RCC_HSI48_DISABLE() do { CLEAR_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON); \
mbed_official	489:119543c9f674	1427	SYSCFG->CFGR3 &= (uint32_t)~((uint32_t)(SYSCFG_CFGR3_ENREF_HSI48 \| SYSCFG_CFGR3_EN_VREFINT)); \
mbed_official	489:119543c9f674	1428	} while (0)
mbed_official	489:119543c9f674	1429	/** @brief Enable or disable the HSI48M DIV6 OUT .
mbed_official	489:119543c9f674	1430	* @note After reset, the HSI48Mhz (divided by 6) output is not available
mbed_official	489:119543c9f674	1431	*/
mbed_official	376:cb4d9db17537	1432
mbed_official	489:119543c9f674	1433	#define __HAL_RCC_HSI48M_DIV6_OUT_ENABLE() SET_BIT(RCC->CR, RCC_CRRCR_HSI48DIV6OUTEN)
mbed_official	489:119543c9f674	1434	#define __HAL_RCC_HSI48M_DIV6_OUT_DISABLE() CLEAR_BIT(RCC->CR, RCC_CRRCR_HSI48DIV6OUTEN)
mbed_official	489:119543c9f674	1435
mbed_official	489:119543c9f674	1436	#endif /* STM32L071xx \|\| STM32L081xx \|\| */
mbed_official	489:119543c9f674	1437	/* STM32L072xx \|\| STM32L082xx \|\| */
mbed_official	489:119543c9f674	1438	/* STM32L073xx \|\| STM32L083xx */
mbed_official	489:119543c9f674	1439
mbed_official	376:cb4d9db17537	1440	/**
mbed_official	376:cb4d9db17537	1441	* @}
mbed_official	376:cb4d9db17537	1442	*/
mbed_official	376:cb4d9db17537	1443
mbed_official	489:119543c9f674	1444	/** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions
mbed_official	489:119543c9f674	1445	* @{
mbed_official	489:119543c9f674	1446	*/
mbed_official	489:119543c9f674	1447
mbed_official	489:119543c9f674	1448	/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions
mbed_official	489:119543c9f674	1449
mbed_official	489:119543c9f674	1450	* @{
mbed_official	489:119543c9f674	1451	*/
mbed_official	376:cb4d9db17537	1452	HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
mbed_official	489:119543c9f674	1453	void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
mbed_official	489:119543c9f674	1454	void HAL_RCCEx_EnableLSECSS(void);
mbed_official	489:119543c9f674	1455	void HAL_RCCEx_DisableLSECSS(void);
mbed_official	489:119543c9f674	1456	#if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
mbed_official	376:cb4d9db17537	1457	void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit);
mbed_official	376:cb4d9db17537	1458	void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void);
mbed_official	376:cb4d9db17537	1459	void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo);
mbed_official	489:119543c9f674	1460	uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout);
mbed_official	489:119543c9f674	1461	void HAL_RCCEx_EnableHSI48_VREFINT(void);
mbed_official	489:119543c9f674	1462	void HAL_RCCEx_DisableHSI48_VREFINT(void);
mbed_official	489:119543c9f674	1463	#endif /* !(STM32L051xx) && !(STM32L061xx) && !(STM32L071xx) && !(STM32L081xx) */
mbed_official	489:119543c9f674	1464
mbed_official	489:119543c9f674	1465	/**
mbed_official	489:119543c9f674	1466	* @}
mbed_official	489:119543c9f674	1467	*/
mbed_official	489:119543c9f674	1468	/**
mbed_official	489:119543c9f674	1469	* @}
mbed_official	489:119543c9f674	1470	*/
mbed_official	489:119543c9f674	1471
mbed_official	376:cb4d9db17537	1472	/**
mbed_official	376:cb4d9db17537	1473	* @}
mbed_official	376:cb4d9db17537	1474	*/
mbed_official	376:cb4d9db17537	1475
mbed_official	376:cb4d9db17537	1476	/**
mbed_official	376:cb4d9db17537	1477	* @}
mbed_official	376:cb4d9db17537	1478	*/
mbed_official	376:cb4d9db17537	1479
mbed_official	376:cb4d9db17537	1480	#ifdef __cplusplus
mbed_official	376:cb4d9db17537	1481	}
mbed_official	376:cb4d9db17537	1482	#endif
mbed_official	376:cb4d9db17537	1483
mbed_official	376:cb4d9db17537	1484	#endif /* __STM32L0xx_HAL_RCC_EX_H */
mbed_official	376:cb4d9db17537	1485
mbed_official	376:cb4d9db17537	1486	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/
mbed_official	489:119543c9f674	1487