mbed-src - mbed library sources

Users » mbed_official » Code » mbed-src

mbed library sources

Dependents: Encrypted my_mbed lklk CyaSSL_DTLS_Cellular ... more

Superseded

This library was superseded by mbed-dev - https://os.mbed.com/users/mbed_official/code/mbed-dev/.

Development branch of the mbed library sources. This library is kept in synch with the latest changes from the mbed SDK and it is not guaranteed to work.

If you are looking for a stable and tested release, please import one of the official mbed library releases:

Import library mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_rcc.h@579:53297373a894, 2015-07-01 (annotated)

Committer:: mbed_official
Date:: Wed Jul 01 09:45:11 2015 +0100
Revision:: 579:53297373a894
Parent:: 489:119543c9f674

Synchronized with git revision d5b4d2ab9c47edb4dc5776e7177b0c2263459081

Full URL: https://github.com/mbedmicro/mbed/commit/d5b4d2ab9c47edb4dc5776e7177b0c2263459081/

Initial version of drivers for SAMR21

Who changed what in which revision?

User	Revision	Line number	New contents of line
mbed_official	376:cb4d9db17537	1	/**
mbed_official	376:cb4d9db17537	2	******************************************************************************
mbed_official	376:cb4d9db17537	3	* @file stm32l0xx_hal_rcc.h
mbed_official	376:cb4d9db17537	4	* @author MCD Application Team
mbed_official	489:119543c9f674	5	* @version V1.2.0
mbed_official	489:119543c9f674	6	* @date 06-February-2015
mbed_official	376:cb4d9db17537	7	* @brief Header file of RCC HAL module.
mbed_official	376:cb4d9db17537	8	******************************************************************************
mbed_official	376:cb4d9db17537	9	* @attention
mbed_official	376:cb4d9db17537	10	*
mbed_official	489:119543c9f674	11	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
mbed_official	376:cb4d9db17537	12	*
mbed_official	376:cb4d9db17537	13	* Redistribution and use in source and binary forms, with or without modification,
mbed_official	376:cb4d9db17537	14	* are permitted provided that the following conditions are met:
mbed_official	376:cb4d9db17537	15	* 1. Redistributions of source code must retain the above copyright notice,
mbed_official	376:cb4d9db17537	16	* this list of conditions and the following disclaimer.
mbed_official	376:cb4d9db17537	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official	376:cb4d9db17537	18	* this list of conditions and the following disclaimer in the documentation
mbed_official	376:cb4d9db17537	19	* and/or other materials provided with the distribution.
mbed_official	376:cb4d9db17537	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official	376:cb4d9db17537	21	* may be used to endorse or promote products derived from this software
mbed_official	376:cb4d9db17537	22	* without specific prior written permission.
mbed_official	376:cb4d9db17537	23	*
mbed_official	376:cb4d9db17537	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official	376:cb4d9db17537	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official	376:cb4d9db17537	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official	376:cb4d9db17537	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official	376:cb4d9db17537	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official	376:cb4d9db17537	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official	376:cb4d9db17537	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official	376:cb4d9db17537	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official	376:cb4d9db17537	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official	376:cb4d9db17537	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official	376:cb4d9db17537	34	*
mbed_official	376:cb4d9db17537	35	******************************************************************************
mbed_official	376:cb4d9db17537	36	*/
mbed_official	376:cb4d9db17537	37
mbed_official	376:cb4d9db17537	38	/* Define to prevent recursive inclusion -------------------------------------*/
mbed_official	376:cb4d9db17537	39	#ifndef __STM32L0xx_HAL_RCC_H
mbed_official	376:cb4d9db17537	40	#define __STM32L0xx_HAL_RCC_H
mbed_official	376:cb4d9db17537	41
mbed_official	376:cb4d9db17537	42	#ifdef __cplusplus
mbed_official	376:cb4d9db17537	43	extern "C" {
mbed_official	376:cb4d9db17537	44	#endif
mbed_official	376:cb4d9db17537	45
mbed_official	376:cb4d9db17537	46	/* Includes ------------------------------------------------------------------*/
mbed_official	376:cb4d9db17537	47	#include "stm32l0xx_hal_def.h"
mbed_official	376:cb4d9db17537	48
mbed_official	376:cb4d9db17537	49	/** @addtogroup STM32L0xx_HAL_Driver
mbed_official	376:cb4d9db17537	50	* @{
mbed_official	376:cb4d9db17537	51	*/
mbed_official	376:cb4d9db17537	52
mbed_official	489:119543c9f674	53	/** @defgroup RCC RCC
mbed_official	376:cb4d9db17537	54	* @{
mbed_official	376:cb4d9db17537	55	*/
mbed_official	376:cb4d9db17537	56
mbed_official	376:cb4d9db17537	57	/* Exported types ------------------------------------------------------------*/
mbed_official	376:cb4d9db17537	58
mbed_official	376:cb4d9db17537	59	/**
mbed_official	376:cb4d9db17537	60	* @brief RCC PLL configuration structure definition
mbed_official	376:cb4d9db17537	61	*/
mbed_official	376:cb4d9db17537	62	typedef struct
mbed_official	376:cb4d9db17537	63	{
mbed_official	376:cb4d9db17537	64	uint32_t PLLState; /*!< The new state of the PLL.
mbed_official	376:cb4d9db17537	65	This parameter can be a value of @ref RCC_PLL_Config */
mbed_official	376:cb4d9db17537	66
mbed_official	376:cb4d9db17537	67	uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source.
mbed_official	376:cb4d9db17537	68	This parameter must be a value of @ref RCC_PLL_Clock_Source */
mbed_official	376:cb4d9db17537	69
mbed_official	376:cb4d9db17537	70	uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO output clock
mbed_official	376:cb4d9db17537	71	This parameter must of @ref RCC_PLLMultiplication_Factor */
mbed_official	376:cb4d9db17537	72
mbed_official	376:cb4d9db17537	73	uint32_t PLLDIV; /*!< PLLDIV: Division factor for main system clock (SYSCLK)
mbed_official	376:cb4d9db17537	74	This parameter must be a value of @ref RCC_PLLDivider_Factor */
mbed_official	376:cb4d9db17537	75
mbed_official	376:cb4d9db17537	76	}RCC_PLLInitTypeDef;
mbed_official	376:cb4d9db17537	77
mbed_official	376:cb4d9db17537	78	/**
mbed_official	376:cb4d9db17537	79	* @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
mbed_official	376:cb4d9db17537	80	*/
mbed_official	376:cb4d9db17537	81	typedef struct
mbed_official	376:cb4d9db17537	82	{
mbed_official	376:cb4d9db17537	83	uint32_t OscillatorType; /*!< The oscillators to be configured.
mbed_official	376:cb4d9db17537	84	This parameter can be a value of @ref RCC_Oscillator_Type */
mbed_official	376:cb4d9db17537	85
mbed_official	376:cb4d9db17537	86	uint32_t HSEState; /*!< The new state of the HSE.
mbed_official	376:cb4d9db17537	87	This parameter can be a value of @ref RCC_HSE_Config */
mbed_official	376:cb4d9db17537	88
mbed_official	376:cb4d9db17537	89	uint32_t LSEState; /*!< The new state of the LSE.
mbed_official	376:cb4d9db17537	90	This parameter can be a value of @ref RCC_LSE_Config */
mbed_official	376:cb4d9db17537	91
mbed_official	376:cb4d9db17537	92	uint32_t HSIState; /*!< The new state of the HSI.
mbed_official	376:cb4d9db17537	93	This parameter can be a value of @ref RCC_HSI_Config */
mbed_official	376:cb4d9db17537	94
mbed_official	376:cb4d9db17537	95	uint32_t HSICalibrationValue; /*!< The calibration trimming value.
mbed_official	376:cb4d9db17537	96	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
mbed_official	376:cb4d9db17537	97
mbed_official	376:cb4d9db17537	98	uint32_t LSIState; /*!< The new state of the LSI.
mbed_official	376:cb4d9db17537	99	This parameter can be a value of @ref RCC_LSI_Config */
mbed_official	376:cb4d9db17537	100
mbed_official	489:119543c9f674	101	#if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
mbed_official	376:cb4d9db17537	102	uint32_t HSI48State; /*!< The new state of the HSI48.
mbed_official	376:cb4d9db17537	103	This parameter can be a value of @ref RCC_HSI48_Config */
mbed_official	489:119543c9f674	104	#endif
mbed_official	376:cb4d9db17537	105
mbed_official	376:cb4d9db17537	106	uint32_t MSIState; /*!< The new state of the MSI.
mbed_official	376:cb4d9db17537	107	This parameter can be a value of @ref RCC_MSI_Config */
mbed_official	376:cb4d9db17537	108
mbed_official	376:cb4d9db17537	109	uint32_t MSICalibrationValue; /*!< The calibration trimming value.
mbed_official	376:cb4d9db17537	110	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
mbed_official	376:cb4d9db17537	111
mbed_official	376:cb4d9db17537	112	uint32_t MSIClockRange; /*!< The MSI frequency range.
mbed_official	376:cb4d9db17537	113	This parameter can be a value of @ref RCC_MSI_Clock_Range */
mbed_official	376:cb4d9db17537	114
mbed_official	376:cb4d9db17537	115	RCC_PLLInitTypeDef PLL; /!< PLL structure parameters /
mbed_official	376:cb4d9db17537	116
mbed_official	376:cb4d9db17537	117	}RCC_OscInitTypeDef;
mbed_official	376:cb4d9db17537	118
mbed_official	376:cb4d9db17537	119	/**
mbed_official	376:cb4d9db17537	120	* @brief RCC System, AHB and APB busses clock configuration structure definition
mbed_official	376:cb4d9db17537	121	*/
mbed_official	376:cb4d9db17537	122	typedef struct
mbed_official	376:cb4d9db17537	123	{
mbed_official	376:cb4d9db17537	124	uint32_t ClockType; /*!< The clock to be configured.
mbed_official	376:cb4d9db17537	125	This parameter can be a value of @ref RCC_System_Clock_Type */
mbed_official	376:cb4d9db17537	126
mbed_official	376:cb4d9db17537	127	uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.
mbed_official	376:cb4d9db17537	128	This parameter can be a value of @ref RCC_System_Clock_Source */
mbed_official	376:cb4d9db17537	129
mbed_official	376:cb4d9db17537	130	uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
mbed_official	376:cb4d9db17537	131	This parameter can be a value of @ref RCC_AHB_Clock_Source */
mbed_official	376:cb4d9db17537	132
mbed_official	376:cb4d9db17537	133	uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
mbed_official	376:cb4d9db17537	134	This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
mbed_official	376:cb4d9db17537	135
mbed_official	376:cb4d9db17537	136	uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
mbed_official	376:cb4d9db17537	137	This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
mbed_official	376:cb4d9db17537	138
mbed_official	376:cb4d9db17537	139	}RCC_ClkInitTypeDef;
mbed_official	376:cb4d9db17537	140
mbed_official	376:cb4d9db17537	141
mbed_official	489:119543c9f674	142	/** @defgroup RCC_Private_Constants RCC Private constatnts
mbed_official	376:cb4d9db17537	143	* @brief RCC registers bit address in the alias region
mbed_official	376:cb4d9db17537	144	* @{
mbed_official	376:cb4d9db17537	145	*/
mbed_official	376:cb4d9db17537	146	#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
mbed_official	376:cb4d9db17537	147	/* --- CR Register ---*/
mbed_official	376:cb4d9db17537	148	/* Alias word address of HSION bit */
mbed_official	376:cb4d9db17537	149	#define RCC_CR_OFFSET (RCC_OFFSET + 0x00)
mbed_official	376:cb4d9db17537	150	/* --- CFGR Register ---*/
mbed_official	376:cb4d9db17537	151	/* Alias word address of I2SSRC bit */
mbed_official	376:cb4d9db17537	152	#define RCC_CFGR_OFFSET (RCC_OFFSET + 0x08)
mbed_official	376:cb4d9db17537	153	/* --- CSR Register ---*/
mbed_official	376:cb4d9db17537	154	#define RCC_CSR_OFFSET (RCC_OFFSET + 0x74)
mbed_official	376:cb4d9db17537	155
mbed_official	376:cb4d9db17537	156	/* CR register byte 3 (Bits[23:16]) base address */
mbed_official	489:119543c9f674	157	#define RCC_CR_BYTE2_ADDRESS ((uint32_t)0x40023802)
mbed_official	376:cb4d9db17537	158
mbed_official	376:cb4d9db17537	159	/* CIER register byte 0 (Bits[0:8]) base address */
mbed_official	376:cb4d9db17537	160	#define CIER_BYTE0_ADDRESS ((uint32_t)(RCC_BASE + 0x10 + 0x00))
mbed_official	376:cb4d9db17537	161
mbed_official	489:119543c9f674	162	#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
mbed_official	489:119543c9f674	163	#define RCC_DBP_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
mbed_official	376:cb4d9db17537	164
mbed_official	376:cb4d9db17537	165	/**
mbed_official	376:cb4d9db17537	166	* @}
mbed_official	376:cb4d9db17537	167	*/
mbed_official	376:cb4d9db17537	168
mbed_official	489:119543c9f674	169	/** @defgroup RCC_Exported_Constants RCC Exported Constants
mbed_official	489:119543c9f674	170	* @{
mbed_official	489:119543c9f674	171	*/
mbed_official	489:119543c9f674	172
mbed_official	489:119543c9f674	173	/** @defgroup RCC_Oscillator_Type RCC Oscillator Type
mbed_official	376:cb4d9db17537	174	* @{
mbed_official	376:cb4d9db17537	175	*/
mbed_official	376:cb4d9db17537	176	#define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000)
mbed_official	376:cb4d9db17537	177	#define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001)
mbed_official	376:cb4d9db17537	178	#define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002)
mbed_official	376:cb4d9db17537	179	#define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004)
mbed_official	376:cb4d9db17537	180	#define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008)
mbed_official	376:cb4d9db17537	181	#define RCC_OSCILLATORTYPE_MSI ((uint32_t)0x00000010)
mbed_official	489:119543c9f674	182	#if !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
mbed_official	376:cb4d9db17537	183	#define RCC_OSCILLATORTYPE_HSI48 ((uint32_t)0x00000020)
mbed_official	489:119543c9f674	184	#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) ((__OSCILLATOR__) <= 0x3F)
mbed_official	489:119543c9f674	185	#else
mbed_official	489:119543c9f674	186	#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) ((__OSCILLATOR__) <= 0x1F)
mbed_official	489:119543c9f674	187	#endif /* !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) */
mbed_official	376:cb4d9db17537	188
mbed_official	376:cb4d9db17537	189	/**
mbed_official	376:cb4d9db17537	190	* @}
mbed_official	376:cb4d9db17537	191	*/
mbed_official	376:cb4d9db17537	192
mbed_official	489:119543c9f674	193	/** @defgroup RCC_HSE_Config RCC HSE Config
mbed_official	376:cb4d9db17537	194	* @{
mbed_official	376:cb4d9db17537	195	*/
mbed_official	376:cb4d9db17537	196	#define RCC_HSE_OFF ((uint32_t)0x00000000)
mbed_official	376:cb4d9db17537	197	#define RCC_HSE_ON RCC_CR_HSEON
mbed_official	376:cb4d9db17537	198	#define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP \| RCC_CR_HSEON))
mbed_official	376:cb4d9db17537	199
mbed_official	489:119543c9f674	200	#define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) \|\| ((__HSE__) == RCC_HSE_ON) \|\| \
mbed_official	489:119543c9f674	201	((__HSE__) == RCC_HSE_BYPASS))
mbed_official	376:cb4d9db17537	202	/**
mbed_official	376:cb4d9db17537	203	* @}
mbed_official	376:cb4d9db17537	204	*/
mbed_official	376:cb4d9db17537	205
mbed_official	489:119543c9f674	206	/** @defgroup RCC_LSE_Config RCC LSE Config
mbed_official	376:cb4d9db17537	207	* @{
mbed_official	376:cb4d9db17537	208	*/
mbed_official	376:cb4d9db17537	209	#define RCC_LSE_OFF ((uint32_t)0x00000000)
mbed_official	376:cb4d9db17537	210	#define RCC_LSE_ON RCC_CSR_LSEON
mbed_official	376:cb4d9db17537	211	#define RCC_LSE_BYPASS ((uint32_t)(RCC_CSR_LSEBYP \| RCC_CSR_LSEON))
mbed_official	376:cb4d9db17537	212
mbed_official	489:119543c9f674	213	#define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) \|\| ((__LSE__) == RCC_LSE_ON) \|\| \
mbed_official	489:119543c9f674	214	((__LSE__) == RCC_LSE_BYPASS))
mbed_official	376:cb4d9db17537	215	/**
mbed_official	376:cb4d9db17537	216	* @}
mbed_official	376:cb4d9db17537	217	*/
mbed_official	376:cb4d9db17537	218
mbed_official	489:119543c9f674	219
mbed_official	376:cb4d9db17537	220
mbed_official	489:119543c9f674	221	/** @defgroup RCC_MSI_Clock_Range RCC MSI Clock Range
mbed_official	376:cb4d9db17537	222	* @{
mbed_official	376:cb4d9db17537	223	*/
mbed_official	376:cb4d9db17537	224
mbed_official	376:cb4d9db17537	225	#define RCC_MSIRANGE_0 RCC_ICSCR_MSIRANGE_0 /!< MSI = 65.536 KHz /
mbed_official	376:cb4d9db17537	226	#define RCC_MSIRANGE_1 RCC_ICSCR_MSIRANGE_1 /!< MSI = 131.072 KHz /
mbed_official	376:cb4d9db17537	227	#define RCC_MSIRANGE_2 RCC_ICSCR_MSIRANGE_2 /!< MSI = 262.144 KHz /
mbed_official	376:cb4d9db17537	228	#define RCC_MSIRANGE_3 RCC_ICSCR_MSIRANGE_3 /!< MSI = 524.288 KHz /
mbed_official	376:cb4d9db17537	229	#define RCC_MSIRANGE_4 RCC_ICSCR_MSIRANGE_4 /!< MSI = 1.048 MHz /
mbed_official	376:cb4d9db17537	230	#define RCC_MSIRANGE_5 RCC_ICSCR_MSIRANGE_5 /!< MSI = 2.097 MHz /
mbed_official	376:cb4d9db17537	231	#define RCC_MSIRANGE_6 RCC_ICSCR_MSIRANGE_6 /!< MSI = 4.194 MHz /
mbed_official	376:cb4d9db17537	232
mbed_official	489:119543c9f674	233	#define IS_RCC_MSI_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_0) \|\| \
mbed_official	489:119543c9f674	234	((__RANGE__) == RCC_MSIRANGE_1) \|\| \
mbed_official	489:119543c9f674	235	((__RANGE__) == RCC_MSIRANGE_2) \|\| \
mbed_official	489:119543c9f674	236	((__RANGE__) == RCC_MSIRANGE_3) \|\| \
mbed_official	489:119543c9f674	237	((__RANGE__) == RCC_MSIRANGE_4) \|\| \
mbed_official	489:119543c9f674	238	((__RANGE__) == RCC_MSIRANGE_5) \|\| \
mbed_official	489:119543c9f674	239	((__RANGE__) == RCC_MSIRANGE_6))
mbed_official	376:cb4d9db17537	240
mbed_official	376:cb4d9db17537	241	/**
mbed_official	376:cb4d9db17537	242	* @}
mbed_official	376:cb4d9db17537	243	*/
mbed_official	376:cb4d9db17537	244
mbed_official	489:119543c9f674	245	/** @defgroup RCC_LSI_Config RCC LSI Config
mbed_official	376:cb4d9db17537	246	* @{
mbed_official	376:cb4d9db17537	247	*/
mbed_official	376:cb4d9db17537	248	#define RCC_LSI_OFF ((uint8_t)0x00)
mbed_official	376:cb4d9db17537	249	#define RCC_LSI_ON ((uint8_t)0x01)
mbed_official	376:cb4d9db17537	250
mbed_official	489:119543c9f674	251	#define RCC_MSICALIBRATION_DEFAULT ((uint32_t)0) /* Default MSI calibration trimming value */
mbed_official	489:119543c9f674	252
mbed_official	489:119543c9f674	253	#define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) \|\| ((__LSI__) == RCC_LSI_ON))
mbed_official	376:cb4d9db17537	254	/**
mbed_official	376:cb4d9db17537	255	* @}
mbed_official	376:cb4d9db17537	256	*/
mbed_official	376:cb4d9db17537	257
mbed_official	376:cb4d9db17537	258
mbed_official	489:119543c9f674	259	/** @defgroup RCC_MSI_Config RCC MSI Config
mbed_official	376:cb4d9db17537	260	* @{
mbed_official	376:cb4d9db17537	261	*/
mbed_official	376:cb4d9db17537	262	#define RCC_MSI_OFF ((uint8_t)0x00)
mbed_official	376:cb4d9db17537	263	#define RCC_MSI_ON ((uint8_t)0x01)
mbed_official	376:cb4d9db17537	264
mbed_official	489:119543c9f674	265	#define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x10) /* Default HSI calibration trimming value */
mbed_official	489:119543c9f674	266
mbed_official	489:119543c9f674	267	#define IS_RCC_MSI(__MSI__) (((__MSI__) == RCC_MSI_OFF) \|\| ((__MSI__) == RCC_MSI_ON))
mbed_official	376:cb4d9db17537	268	/**
mbed_official	376:cb4d9db17537	269	* @}
mbed_official	376:cb4d9db17537	270	*/
mbed_official	376:cb4d9db17537	271
mbed_official	489:119543c9f674	272	#if !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
mbed_official	376:cb4d9db17537	273	/** @defgroup RCC_HSI48_Config
mbed_official	376:cb4d9db17537	274	* @{
mbed_official	376:cb4d9db17537	275	*/
mbed_official	376:cb4d9db17537	276	#define RCC_HSI48_OFF ((uint8_t)0x00)
mbed_official	376:cb4d9db17537	277	#define RCC_HSI48_ON ((uint8_t)0x01)
mbed_official	376:cb4d9db17537	278
mbed_official	489:119543c9f674	279	#define IS_RCC_HSI48(__HSI48__) (((__HSI48__) == RCC_HSI48_OFF) \|\| ((__HSI48__) == RCC_HSI48_ON))
mbed_official	376:cb4d9db17537	280	/**
mbed_official	376:cb4d9db17537	281	* @}
mbed_official	376:cb4d9db17537	282	*/
mbed_official	489:119543c9f674	283	#endif /* !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) */
mbed_official	376:cb4d9db17537	284
mbed_official	489:119543c9f674	285	/** @defgroup RCC_PLL_Config RCC PLL Config
mbed_official	376:cb4d9db17537	286	* @{
mbed_official	376:cb4d9db17537	287	*/
mbed_official	376:cb4d9db17537	288	#define RCC_PLL_NONE ((uint8_t)0x00)
mbed_official	376:cb4d9db17537	289	#define RCC_PLL_OFF ((uint8_t)0x01)
mbed_official	376:cb4d9db17537	290	#define RCC_PLL_ON ((uint8_t)0x02)
mbed_official	376:cb4d9db17537	291
mbed_official	489:119543c9f674	292	#define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) \|\|((__PLL__) == RCC_PLL_OFF) \|\| ((__PLL__) == RCC_PLL_ON))
mbed_official	376:cb4d9db17537	293	/**
mbed_official	376:cb4d9db17537	294	* @}
mbed_official	376:cb4d9db17537	295	*/
mbed_official	376:cb4d9db17537	296
mbed_official	489:119543c9f674	297	/** @defgroup RCC_PLL_Clock_Source PCC PLL Clock Source
mbed_official	376:cb4d9db17537	298	* @{
mbed_official	376:cb4d9db17537	299	*/
mbed_official	376:cb4d9db17537	300	#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI
mbed_official	376:cb4d9db17537	301	#define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE
mbed_official	376:cb4d9db17537	302
mbed_official	489:119543c9f674	303	#define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_HSI) \|\| \
mbed_official	489:119543c9f674	304	((__SOURCE__) == RCC_PLLSOURCE_HSE))
mbed_official	376:cb4d9db17537	305
mbed_official	376:cb4d9db17537	306	/**
mbed_official	376:cb4d9db17537	307	* @}
mbed_official	376:cb4d9db17537	308	*/
mbed_official	376:cb4d9db17537	309
mbed_official	489:119543c9f674	310	/** @defgroup RCC_PLLMultiplication_Factor RCC PLL Multipliers
mbed_official	376:cb4d9db17537	311	* @{
mbed_official	376:cb4d9db17537	312	*/
mbed_official	376:cb4d9db17537	313
mbed_official	376:cb4d9db17537	314	#define RCC_PLLMUL_3 RCC_CFGR_PLLMUL3
mbed_official	376:cb4d9db17537	315	#define RCC_PLLMUL_4 RCC_CFGR_PLLMUL4
mbed_official	376:cb4d9db17537	316	#define RCC_PLLMUL_6 RCC_CFGR_PLLMUL6
mbed_official	376:cb4d9db17537	317	#define RCC_PLLMUL_8 RCC_CFGR_PLLMUL8
mbed_official	376:cb4d9db17537	318	#define RCC_PLLMUL_12 RCC_CFGR_PLLMUL12
mbed_official	376:cb4d9db17537	319	#define RCC_PLLMUL_16 RCC_CFGR_PLLMUL16
mbed_official	376:cb4d9db17537	320	#define RCC_PLLMUL_24 RCC_CFGR_PLLMUL24
mbed_official	376:cb4d9db17537	321	#define RCC_PLLMUL_32 RCC_CFGR_PLLMUL32
mbed_official	376:cb4d9db17537	322	#define RCC_PLLMUL_48 RCC_CFGR_PLLMUL48
mbed_official	489:119543c9f674	323	#define IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLLMUL_3) \|\| ((__MUL__) == RCC_PLLMUL_4) \|\| \
mbed_official	489:119543c9f674	324	((__MUL__) == RCC_PLLMUL_6) \|\| ((__MUL__) == RCC_PLLMUL_8) \|\| \
mbed_official	489:119543c9f674	325	((__MUL__) == RCC_PLLMUL_12) \|\| ((__MUL__) == RCC_PLLMUL_16) \|\| \
mbed_official	489:119543c9f674	326	((__MUL__) == RCC_PLLMUL_24) \|\| ((__MUL__) == RCC_PLLMUL_32) \|\| \
mbed_official	489:119543c9f674	327	((__MUL__) == RCC_PLLMUL_48))
mbed_official	376:cb4d9db17537	328	/**
mbed_official	376:cb4d9db17537	329	* @}
mbed_official	376:cb4d9db17537	330	*/
mbed_official	376:cb4d9db17537	331
mbed_official	489:119543c9f674	332	/** @defgroup RCC_PLLDivider_Factor RCC PLL Dividers
mbed_official	376:cb4d9db17537	333	* @{
mbed_official	376:cb4d9db17537	334	*/
mbed_official	376:cb4d9db17537	335
mbed_official	376:cb4d9db17537	336	#define RCC_PLLDIV_2 RCC_CFGR_PLLDIV2
mbed_official	376:cb4d9db17537	337	#define RCC_PLLDIV_3 RCC_CFGR_PLLDIV3
mbed_official	376:cb4d9db17537	338	#define RCC_PLLDIV_4 RCC_CFGR_PLLDIV4
mbed_official	489:119543c9f674	339	#define IS_RCC_PLL_DIV(__DIV__) (((__DIV__) == RCC_PLLDIV_2) \|\| ((__DIV__) == RCC_PLLDIV_3) \|\| \
mbed_official	489:119543c9f674	340	((__DIV__) == RCC_PLLDIV_4))
mbed_official	376:cb4d9db17537	341	/**
mbed_official	376:cb4d9db17537	342	* @}
mbed_official	376:cb4d9db17537	343	*/
mbed_official	376:cb4d9db17537	344
mbed_official	489:119543c9f674	345	/** @defgroup RCC_System_Clock_Type RCC System Clock Type
mbed_official	376:cb4d9db17537	346	* @{
mbed_official	376:cb4d9db17537	347	*/
mbed_official	376:cb4d9db17537	348	#define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001)
mbed_official	376:cb4d9db17537	349	#define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002)
mbed_official	376:cb4d9db17537	350	#define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004)
mbed_official	376:cb4d9db17537	351	#define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008)
mbed_official	376:cb4d9db17537	352
mbed_official	489:119543c9f674	353	#define IS_RCC_CLOCKTYPE(__CLK__) ((1 <= (__CLK__)) && ((__CLK__) <= 15))
mbed_official	376:cb4d9db17537	354	/**
mbed_official	376:cb4d9db17537	355	* @}
mbed_official	376:cb4d9db17537	356	*/
mbed_official	376:cb4d9db17537	357
mbed_official	489:119543c9f674	358	/** @defgroup RCC_System_Clock_Source RCC System Clock Source
mbed_official	376:cb4d9db17537	359	* @{
mbed_official	376:cb4d9db17537	360	*/
mbed_official	376:cb4d9db17537	361	#define RCC_SYSCLKSOURCE_MSI RCC_CFGR_SW_MSI
mbed_official	376:cb4d9db17537	362	#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI
mbed_official	376:cb4d9db17537	363	#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE
mbed_official	376:cb4d9db17537	364	#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL
mbed_official	376:cb4d9db17537	365
mbed_official	489:119543c9f674	366	#define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) \|\| \
mbed_official	489:119543c9f674	367	((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) \|\| \
mbed_official	489:119543c9f674	368	((__SOURCE__) == RCC_SYSCLKSOURCE_MSI) \|\| \
mbed_official	489:119543c9f674	369	((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK))
mbed_official	376:cb4d9db17537	370	/**
mbed_official	376:cb4d9db17537	371	* @}
mbed_official	376:cb4d9db17537	372	*/
mbed_official	376:cb4d9db17537	373
mbed_official	489:119543c9f674	374	/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
mbed_official	489:119543c9f674	375	* @{
mbed_official	489:119543c9f674	376	*/
mbed_official	489:119543c9f674	377	#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI
mbed_official	489:119543c9f674	378	#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE
mbed_official	489:119543c9f674	379	#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL
mbed_official	489:119543c9f674	380
mbed_official	489:119543c9f674	381	/**
mbed_official	489:119543c9f674	382	* @}
mbed_official	489:119543c9f674	383	*/
mbed_official	489:119543c9f674	384
mbed_official	489:119543c9f674	385	/** @defgroup RCC_AHB_Clock_Source RCC AHB Clock SOurce
mbed_official	376:cb4d9db17537	386	* @{
mbed_official	376:cb4d9db17537	387	*/
mbed_official	376:cb4d9db17537	388	#define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1
mbed_official	376:cb4d9db17537	389	#define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2
mbed_official	376:cb4d9db17537	390	#define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4
mbed_official	376:cb4d9db17537	391	#define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8
mbed_official	376:cb4d9db17537	392	#define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16
mbed_official	376:cb4d9db17537	393	#define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64
mbed_official	376:cb4d9db17537	394	#define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128
mbed_official	376:cb4d9db17537	395	#define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256
mbed_official	376:cb4d9db17537	396	#define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512
mbed_official	376:cb4d9db17537	397
mbed_official	489:119543c9f674	398	#define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) \|\| ((__HCLK__) == RCC_SYSCLK_DIV2) \|\| \
mbed_official	489:119543c9f674	399	((__HCLK__) == RCC_SYSCLK_DIV4) \|\| ((__HCLK__) == RCC_SYSCLK_DIV8) \|\| \
mbed_official	489:119543c9f674	400	((__HCLK__) == RCC_SYSCLK_DIV16) \|\| ((__HCLK__) == RCC_SYSCLK_DIV64) \|\| \
mbed_official	489:119543c9f674	401	((__HCLK__) == RCC_SYSCLK_DIV128) \|\| ((__HCLK__) == RCC_SYSCLK_DIV256) \|\| \
mbed_official	489:119543c9f674	402	((__HCLK__) == RCC_SYSCLK_DIV512))
mbed_official	376:cb4d9db17537	403	/**
mbed_official	376:cb4d9db17537	404	* @}
mbed_official	376:cb4d9db17537	405	*/
mbed_official	376:cb4d9db17537	406
mbed_official	489:119543c9f674	407	/** @defgroup RCC_APB1_APB2_Clock_Source RCC APB1 Clock Source
mbed_official	376:cb4d9db17537	408	* @{
mbed_official	376:cb4d9db17537	409	*/
mbed_official	376:cb4d9db17537	410	#define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1
mbed_official	376:cb4d9db17537	411	#define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2
mbed_official	376:cb4d9db17537	412	#define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4
mbed_official	376:cb4d9db17537	413	#define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8
mbed_official	376:cb4d9db17537	414	#define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16
mbed_official	376:cb4d9db17537	415
mbed_official	489:119543c9f674	416	#define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) \|\| ((__PCLK__) == RCC_HCLK_DIV2) \|\| \
mbed_official	489:119543c9f674	417	((__PCLK__) == RCC_HCLK_DIV4) \|\| ((__PCLK__) == RCC_HCLK_DIV8) \|\| \
mbed_official	489:119543c9f674	418	((__PCLK__) == RCC_HCLK_DIV16))
mbed_official	376:cb4d9db17537	419	/**
mbed_official	376:cb4d9db17537	420	* @}
mbed_official	376:cb4d9db17537	421	*/
mbed_official	376:cb4d9db17537	422
mbed_official	489:119543c9f674	423	/** @defgroup RCC_RTC_Clock_Source RCC RTC Clock Source
mbed_official	376:cb4d9db17537	424	* @{
mbed_official	376:cb4d9db17537	425	*/
mbed_official	489:119543c9f674	426	#define RCC_RTCCLKSOURCE_NO_CLK ((uint32_t)0x00000000)
mbed_official	376:cb4d9db17537	427	#define RCC_RTCCLKSOURCE_LSE RCC_CSR_RTCSEL_LSE
mbed_official	376:cb4d9db17537	428	#define RCC_RTCCLKSOURCE_LSI RCC_CSR_RTCSEL_LSI
mbed_official	376:cb4d9db17537	429	#define RCC_RTCCLKSOURCE_HSE_DIV2 RCC_CSR_RTCSEL_HSE
mbed_official	376:cb4d9db17537	430	#define RCC_RTCCLKSOURCE_HSE_DIV4 ((uint32_t)RCC_CSR_RTCSEL_HSE \| RCC_CR_RTCPRE_0)
mbed_official	376:cb4d9db17537	431	#define RCC_RTCCLKSOURCE_HSE_DIV8 ((uint32_t)RCC_CSR_RTCSEL_HSE \| RCC_CR_RTCPRE_1)
mbed_official	376:cb4d9db17537	432	#define RCC_RTCCLKSOURCE_HSE_DIV16 ((uint32_t)RCC_CSR_RTCSEL_HSE \| RCC_CR_RTCPRE)
mbed_official	489:119543c9f674	433	#define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) \|\| \
mbed_official	489:119543c9f674	434	((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) \|\| \
mbed_official	489:119543c9f674	435	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV2) \|\| \
mbed_official	489:119543c9f674	436	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV4) \|\| \
mbed_official	489:119543c9f674	437	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV8) \|\| \
mbed_official	489:119543c9f674	438	((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV16))
mbed_official	376:cb4d9db17537	439	/**
mbed_official	376:cb4d9db17537	440	* @}
mbed_official	376:cb4d9db17537	441	*/
mbed_official	376:cb4d9db17537	442
mbed_official	489:119543c9f674	443	/** @defgroup RCC_MCO_Clock_Source RCC MCo Clock Source
mbed_official	376:cb4d9db17537	444	* @{
mbed_official	376:cb4d9db17537	445	*/
mbed_official	489:119543c9f674	446
mbed_official	489:119543c9f674	447	#define RCC_MCO1SOURCE_NOCLOCK RCC_CFGR_MCO_NOCLOCK
mbed_official	489:119543c9f674	448	#define RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCO_SYSCLK
mbed_official	489:119543c9f674	449	#define RCC_MCO1SOURCE_HSI RCC_CFGR_MCO_HSI
mbed_official	489:119543c9f674	450	#define RCC_MCO1SOURCE_MSI RCC_CFGR_MCO_MSI
mbed_official	489:119543c9f674	451	#define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO_HSE
mbed_official	489:119543c9f674	452	#define RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCO_PLL
mbed_official	489:119543c9f674	453	#define RCC_MCO1SOURCE_LSI RCC_CFGR_MCO_LSI
mbed_official	489:119543c9f674	454	#define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO_LSE
mbed_official	489:119543c9f674	455	#if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
mbed_official	489:119543c9f674	456	#define RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCO_HSI48
mbed_official	489:119543c9f674	457	#endif
mbed_official	376:cb4d9db17537	458
mbed_official	489:119543c9f674	459	#if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
mbed_official	489:119543c9f674	460	#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) \|\| ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) \|\| \
mbed_official	489:119543c9f674	461	((__SOURCE__) == RCC_MCO1SOURCE_HSI) \|\| ((__SOURCE__) == RCC_MCO1SOURCE_MSI) \|\| \
mbed_official	489:119543c9f674	462	((__SOURCE__) == RCC_MCO1SOURCE_HSE) \|\| ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) \|\| \
mbed_official	489:119543c9f674	463	((__SOURCE__) == RCC_MCO1SOURCE_LSI) \|\| ((__SOURCE__) == RCC_MCO1SOURCE_LSE) \|\| \
mbed_official	489:119543c9f674	464	((__SOURCE__) == RCC_MCO1SOURCE_HSI48))
mbed_official	489:119543c9f674	465	#else
mbed_official	489:119543c9f674	466	#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) \|\| ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) \|\| \
mbed_official	489:119543c9f674	467	((__SOURCE__) == RCC_MCO1SOURCE_HSI) \|\| ((__SOURCE__) == RCC_MCO1SOURCE_MSI) \|\| \
mbed_official	489:119543c9f674	468	((__SOURCE__) == RCC_MCO1SOURCE_HSE) \|\| ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) \|\| \
mbed_official	489:119543c9f674	469	((__SOURCE__) == RCC_MCO1SOURCE_LSI) \|\| ((__SOURCE__) == RCC_MCO1SOURCE_LSE))
mbed_official	489:119543c9f674	470	#endif
mbed_official	489:119543c9f674	471
mbed_official	376:cb4d9db17537	472	/**
mbed_official	376:cb4d9db17537	473	* @}
mbed_official	376:cb4d9db17537	474	*/
mbed_official	376:cb4d9db17537	475
mbed_official	489:119543c9f674	476	/** @defgroup RCC_MCOPrescaler RCC MCO Prescaler
mbed_official	376:cb4d9db17537	477	* @{
mbed_official	376:cb4d9db17537	478	*/
mbed_official	376:cb4d9db17537	479
mbed_official	376:cb4d9db17537	480	#define RCC_MCODIV_1 RCC_CFGR_MCO_PRE_1
mbed_official	376:cb4d9db17537	481	#define RCC_MCODIV_2 RCC_CFGR_MCO_PRE_2
mbed_official	376:cb4d9db17537	482	#define RCC_MCODIV_4 RCC_CFGR_MCO_PRE_4
mbed_official	376:cb4d9db17537	483	#define RCC_MCODIV_8 RCC_CFGR_MCO_PRE_8
mbed_official	376:cb4d9db17537	484	#define RCC_MCODIV_16 RCC_CFGR_MCO_PRE_16
mbed_official	376:cb4d9db17537	485
mbed_official	489:119543c9f674	486	#define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1) \|\| \
mbed_official	489:119543c9f674	487	((__DIV__) == RCC_MCODIV_2) \|\| \
mbed_official	489:119543c9f674	488	((__DIV__) == RCC_MCODIV_4) \|\| \
mbed_official	489:119543c9f674	489	((__DIV__) == RCC_MCODIV_8) \|\| \
mbed_official	489:119543c9f674	490	((__DIV__) == RCC_MCODIV_16))
mbed_official	376:cb4d9db17537	491	/**
mbed_official	376:cb4d9db17537	492	* @}
mbed_official	376:cb4d9db17537	493	*/
mbed_official	376:cb4d9db17537	494
mbed_official	489:119543c9f674	495	/** @defgroup RCC_MCO_Index RCC MCO Index
mbed_official	376:cb4d9db17537	496	* @{
mbed_official	376:cb4d9db17537	497	*/
mbed_official	376:cb4d9db17537	498	#define RCC_MCO1 ((uint32_t)0x00000000)
mbed_official	376:cb4d9db17537	499	#define RCC_MCO2 ((uint32_t)0x00000001)
mbed_official	376:cb4d9db17537	500
mbed_official	489:119543c9f674	501	#define IS_RCC_MCO(__MCOx__) (((__MCOx__) == RCC_MCO1) \|\| ((__MCOx__) == RCC_MCO2))
mbed_official	376:cb4d9db17537	502	/**
mbed_official	376:cb4d9db17537	503	* @}
mbed_official	376:cb4d9db17537	504	*/
mbed_official	376:cb4d9db17537	505
mbed_official	489:119543c9f674	506	/** @defgroup RCC_Interrupt RCC Interruptions
mbed_official	376:cb4d9db17537	507	* @{
mbed_official	376:cb4d9db17537	508	*/
mbed_official	376:cb4d9db17537	509	#define RCC_IT_LSIRDY RCC_CIFR_LSIRDYF
mbed_official	376:cb4d9db17537	510	#define RCC_IT_LSERDY RCC_CIFR_LSERDYF
mbed_official	376:cb4d9db17537	511	#define RCC_IT_HSIRDY RCC_CIFR_HSIRDYF
mbed_official	376:cb4d9db17537	512	#define RCC_IT_HSERDY RCC_CIFR_HSERDYF
mbed_official	376:cb4d9db17537	513	#define RCC_IT_PLLRDY RCC_CIFR_PLLRDYF
mbed_official	376:cb4d9db17537	514	#define RCC_IT_MSIRDY RCC_CIFR_MSIRDYF
mbed_official	489:119543c9f674	515
mbed_official	376:cb4d9db17537	516	#define RCC_IT_LSECSS RCC_CIFR_LSECSSF
mbed_official	376:cb4d9db17537	517	#define RCC_IT_CSS RCC_CIFR_CSSF
mbed_official	489:119543c9f674	518	#if !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
mbed_official	489:119543c9f674	519	#define RCC_IT_HSI48RDY RCC_CIFR_HSI48RDYF
mbed_official	376:cb4d9db17537	520
mbed_official	489:119543c9f674	521	#define IS_RCC_IT(__IT__) (((__IT__) == RCC_IT_LSIRDY) \|\| ((__IT__) == RCC_IT_LSERDY) \|\| \
mbed_official	489:119543c9f674	522	((__IT__) == RCC_IT_HSIRDY) \|\| ((__IT__) == RCC_IT_HSERDY) \|\| \
mbed_official	489:119543c9f674	523	((__IT__) == RCC_IT_PLLRDY) \|\| ((__IT__) == RCC_IT_MSIRDY) \|\| \
mbed_official	489:119543c9f674	524	((__IT__) == RCC_IT_HSI48RDY) \|\| ((__IT__) == RCC_IT_LSECSS))
mbed_official	489:119543c9f674	525
mbed_official	489:119543c9f674	526	#define IS_RCC_GET_IT(__IT__) (((__IT__) == RCC_IT_LSIRDY) \|\| ((__IT__) == RCC_IT_LSERDY) \|\| \
mbed_official	489:119543c9f674	527	((__IT__) == RCC_IT_HSIRDY) \|\| ((__IT__) == RCC_IT_HSERDY) \|\| \
mbed_official	489:119543c9f674	528	((__IT__) == RCC_IT_PLLRDY) \|\| ((__IT__) == RCC_IT_MSIRDY) \|\| \
mbed_official	489:119543c9f674	529	((__IT__) == RCC_IT_CSS) \|\| ((__IT__) == RCC_IT_HSI48RDY) \|\| \
mbed_official	489:119543c9f674	530	((__IT__) == RCC_IT_LSECSS))
mbed_official	376:cb4d9db17537	531
mbed_official	489:119543c9f674	532	#define IS_RCC_CLEAR_IT(__IT__) (((__IT__) == RCC_IT_LSIRDY) \|\| ((__IT__) == RCC_IT_LSERDY) \|\| \
mbed_official	489:119543c9f674	533	((__IT__) == RCC_IT_HSIRDY) \|\| ((__IT__) == RCC_IT_HSERDY) \|\| \
mbed_official	489:119543c9f674	534	((__IT__) == RCC_IT_PLLRDY) \|\| ((__IT__) == RCC_IT_MSIRDY) \|\| \
mbed_official	489:119543c9f674	535	((__IT__) == RCC_IT_CSS) \|\| ((__IT__) == RCC_IT_HSI48RDY) \|\| \
mbed_official	489:119543c9f674	536	((__IT__) == RCC_IT_LSECSS))
mbed_official	489:119543c9f674	537	#else
mbed_official	489:119543c9f674	538	#define IS_RCC_IT(__IT__) (((__IT__) == RCC_IT_LSIRDY) \|\| ((__IT__) == RCC_IT_LSERDY) \|\| \
mbed_official	489:119543c9f674	539	((__IT__) == RCC_IT_HSIRDY) \|\| ((__IT__) == RCC_IT_HSERDY) \|\| \
mbed_official	489:119543c9f674	540	((__IT__) == RCC_IT_PLLRDY) \|\| ((__IT__) == RCC_IT_MSIRDY) \|\| \
mbed_official	489:119543c9f674	541	((__IT__) == RCC_IT_LSECSS))
mbed_official	376:cb4d9db17537	542
mbed_official	489:119543c9f674	543	#define IS_RCC_GET_IT(__IT__) (((__IT__) == RCC_IT_LSIRDY) \|\| ((__IT__) == RCC_IT_LSERDY) \|\| \
mbed_official	489:119543c9f674	544	((__IT__) == RCC_IT_HSIRDY) \|\| ((__IT__) == RCC_IT_HSERDY) \|\| \
mbed_official	489:119543c9f674	545	((__IT__) == RCC_IT_PLLRDY) \|\| ((__IT__) == RCC_IT_MSIRDY) \|\| \
mbed_official	489:119543c9f674	546	((__IT__) == RCC_IT_CSS) \|\| ((__IT__) == RCC_IT_LSECSS))
mbed_official	489:119543c9f674	547
mbed_official	376:cb4d9db17537	548
mbed_official	489:119543c9f674	549	#define IS_RCC_CLEAR_IT(__IT__) (((__IT__) == RCC_IT_LSIRDY) \|\| ((__IT__) == RCC_IT_LSERDY) \|\| \
mbed_official	489:119543c9f674	550	((__IT__) == RCC_IT_HSIRDY) \|\| ((__IT__) == RCC_IT_HSERDY) \|\| \
mbed_official	489:119543c9f674	551	((__IT__) == RCC_IT_PLLRDY) \|\| ((__IT__) == RCC_IT_MSIRDY) \|\| \
mbed_official	489:119543c9f674	552	((__IT__) == RCC_IT_CSS) \|\| ((__IT__) == RCC_IT_LSECSS))
mbed_official	489:119543c9f674	553
mbed_official	489:119543c9f674	554	#endif /* !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) */
mbed_official	376:cb4d9db17537	555	/**
mbed_official	376:cb4d9db17537	556	* @}
mbed_official	376:cb4d9db17537	557	*/
mbed_official	489:119543c9f674	558
mbed_official	376:cb4d9db17537	559	/** @defgroup RCC_Flag
mbed_official	376:cb4d9db17537	560	* Elements values convention: 0XXYYYYYb
mbed_official	376:cb4d9db17537	561	* - YYYYY : Flag position in the register
mbed_official	376:cb4d9db17537	562	* - 0XX : Register index
mbed_official	376:cb4d9db17537	563	* - 01: CR register
mbed_official	376:cb4d9db17537	564	* - 10: CSR register
mbed_official	376:cb4d9db17537	565	* - 11: CRRCR register
mbed_official	376:cb4d9db17537	566	* @{
mbed_official	376:cb4d9db17537	567	*/
mbed_official	376:cb4d9db17537	568	/* Flags in the CR register */
mbed_official	376:cb4d9db17537	569	#define RCC_FLAG_HSIRDY ((uint8_t)0x22)
mbed_official	376:cb4d9db17537	570	#define RCC_FLAG_HSIDIV ((uint8_t)0x24)
mbed_official	376:cb4d9db17537	571	#define RCC_FLAG_MSIRDY ((uint8_t)0x29)
mbed_official	376:cb4d9db17537	572	#define RCC_FLAG_HSERDY ((uint8_t)0x31)
mbed_official	376:cb4d9db17537	573	#define RCC_FLAG_PLLRDY ((uint8_t)0x39)
mbed_official	376:cb4d9db17537	574
mbed_official	376:cb4d9db17537	575	/* Flags in the CSR register */
mbed_official	376:cb4d9db17537	576	#define RCC_FLAG_LSERDY ((uint8_t)0x49)
mbed_official	376:cb4d9db17537	577	#define RCC_FLAG_LSECSS ((uint8_t)0x4E)
mbed_official	376:cb4d9db17537	578	#define RCC_FLAG_LSIRDY ((uint8_t)0x41)
mbed_official	489:119543c9f674	579	#define RCC_FLAG_FWRST ((uint8_t)0x58)
mbed_official	376:cb4d9db17537	580	#define RCC_FLAG_OBLRST ((uint8_t)0x59)
mbed_official	376:cb4d9db17537	581	#define RCC_FLAG_PINRST ((uint8_t)0x5A)
mbed_official	376:cb4d9db17537	582	#define RCC_FLAG_PORRST ((uint8_t)0x5B)
mbed_official	376:cb4d9db17537	583	#define RCC_FLAG_SFTRST ((uint8_t)0x5C)
mbed_official	376:cb4d9db17537	584	#define RCC_FLAG_IWDGRST ((uint8_t)0x5D)
mbed_official	376:cb4d9db17537	585	#define RCC_FLAG_WWDGRST ((uint8_t)0x5E)
mbed_official	376:cb4d9db17537	586	#define RCC_FLAG_LPWRRST ((uint8_t)0x5F)
mbed_official	376:cb4d9db17537	587
mbed_official	489:119543c9f674	588	#if !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
mbed_official	376:cb4d9db17537	589	/* Flags in the CRRCR register */
mbed_official	376:cb4d9db17537	590	#define RCC_FLAG_HSI48RDY ((uint8_t)0x61)
mbed_official	489:119543c9f674	591	#endif /* !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) */
mbed_official	376:cb4d9db17537	592
mbed_official	489:119543c9f674	593	#define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1F)
mbed_official	489:119543c9f674	594	#define IS_RCC_MSICALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0xFF)
mbed_official	489:119543c9f674	595
mbed_official	376:cb4d9db17537	596	/**
mbed_official	376:cb4d9db17537	597	* @}
mbed_official	376:cb4d9db17537	598	*/
mbed_official	376:cb4d9db17537	599
mbed_official	376:cb4d9db17537	600	/**
mbed_official	376:cb4d9db17537	601	* @}
mbed_official	376:cb4d9db17537	602	*/
mbed_official	376:cb4d9db17537	603	/* Exported macro ------------------------------------------------------------*/
mbed_official	489:119543c9f674	604	/** @defgroup RCC_Exported_Macros RCC Exported Macros
mbed_official	376:cb4d9db17537	605	* @{
mbed_official	376:cb4d9db17537	606	*/
mbed_official	376:cb4d9db17537	607
mbed_official	376:cb4d9db17537	608	/** @brief Enable or disable the AHB peripheral clock.
mbed_official	376:cb4d9db17537	609	* @note After reset, the peripheral clock (used for registers read/write access)
mbed_official	376:cb4d9db17537	610	* is disabled and the application software has to enable this clock before
mbed_official	376:cb4d9db17537	611	* using it.
mbed_official	376:cb4d9db17537	612	*/
mbed_official	489:119543c9f674	613	#define __HAL_RCC_DMA1_CLK_ENABLE() do { \
mbed_official	489:119543c9f674	614	__IO uint32_t tmpreg; \
mbed_official	489:119543c9f674	615	SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
mbed_official	489:119543c9f674	616	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	489:119543c9f674	617	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
mbed_official	489:119543c9f674	618	UNUSED(tmpreg); \
mbed_official	489:119543c9f674	619	} while(0)
mbed_official	489:119543c9f674	620
mbed_official	489:119543c9f674	621	#define __HAL_RCC_MIF_CLK_ENABLE() do { \
mbed_official	489:119543c9f674	622	__IO uint32_t tmpreg; \
mbed_official	489:119543c9f674	623	SET_BIT(RCC->AHBENR, RCC_AHBENR_MIFEN);\
mbed_official	489:119543c9f674	624	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	489:119543c9f674	625	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_MIFEN);\
mbed_official	489:119543c9f674	626	UNUSED(tmpreg); \
mbed_official	489:119543c9f674	627	} while(0)
mbed_official	489:119543c9f674	628
mbed_official	489:119543c9f674	629	#define __HAL_RCC_CRC_CLK_ENABLE() do { \
mbed_official	489:119543c9f674	630	__IO uint32_t tmpreg; \
mbed_official	489:119543c9f674	631	SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
mbed_official	489:119543c9f674	632	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	489:119543c9f674	633	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
mbed_official	489:119543c9f674	634	UNUSED(tmpreg); \
mbed_official	489:119543c9f674	635	} while(0)
mbed_official	376:cb4d9db17537	636
mbed_official	376:cb4d9db17537	637
mbed_official	489:119543c9f674	638	#define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHBENR &= ~ (RCC_AHBENR_DMA1EN))
mbed_official	489:119543c9f674	639	#define __HAL_RCC_MIF_CLK_DISABLE() (RCC->AHBENR &= ~ (RCC_AHBENR_MIFEN))
mbed_official	489:119543c9f674	640	#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHBENR &= ~ (RCC_AHBENR_CRCEN))
mbed_official	376:cb4d9db17537	641
mbed_official	376:cb4d9db17537	642
mbed_official	376:cb4d9db17537	643	/** @brief Enable or disable the IOPORT peripheral clock.
mbed_official	376:cb4d9db17537	644	* @note After reset, the peripheral clock (used for registers read/write access)
mbed_official	376:cb4d9db17537	645	* is disabled and the application software has to enable this clock before
mbed_official	376:cb4d9db17537	646	* using it.
mbed_official	376:cb4d9db17537	647	*/
mbed_official	489:119543c9f674	648	#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
mbed_official	489:119543c9f674	649	__IO uint32_t tmpreg; \
mbed_official	489:119543c9f674	650	SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN);\
mbed_official	489:119543c9f674	651	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	489:119543c9f674	652	tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN);\
mbed_official	489:119543c9f674	653	UNUSED(tmpreg); \
mbed_official	489:119543c9f674	654	} while(0)
mbed_official	489:119543c9f674	655
mbed_official	489:119543c9f674	656	#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
mbed_official	489:119543c9f674	657	__IO uint32_t tmpreg; \
mbed_official	489:119543c9f674	658	SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN);\
mbed_official	489:119543c9f674	659	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	489:119543c9f674	660	tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN);\
mbed_official	489:119543c9f674	661	UNUSED(tmpreg); \
mbed_official	489:119543c9f674	662	} while(0)
mbed_official	489:119543c9f674	663
mbed_official	489:119543c9f674	664	#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
mbed_official	489:119543c9f674	665	__IO uint32_t tmpreg; \
mbed_official	489:119543c9f674	666	SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN);\
mbed_official	489:119543c9f674	667	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	489:119543c9f674	668	tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN);\
mbed_official	489:119543c9f674	669	UNUSED(tmpreg); \
mbed_official	489:119543c9f674	670	} while(0)
mbed_official	376:cb4d9db17537	671
mbed_official	489:119543c9f674	672	#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
mbed_official	489:119543c9f674	673	__IO uint32_t tmpreg; \
mbed_official	489:119543c9f674	674	SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIODEN);\
mbed_official	489:119543c9f674	675	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	489:119543c9f674	676	tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIODEN);\
mbed_official	489:119543c9f674	677	UNUSED(tmpreg); \
mbed_official	489:119543c9f674	678	} while(0)
mbed_official	489:119543c9f674	679
mbed_official	489:119543c9f674	680	#define __HAL_RCC_GPIOH_CLK_ENABLE() do { \
mbed_official	489:119543c9f674	681	__IO uint32_t tmpreg; \
mbed_official	489:119543c9f674	682	SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOHEN);\
mbed_official	489:119543c9f674	683	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	489:119543c9f674	684	tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOHEN);\
mbed_official	489:119543c9f674	685	UNUSED(tmpreg); \
mbed_official	489:119543c9f674	686	} while(0)
mbed_official	489:119543c9f674	687
mbed_official	489:119543c9f674	688
mbed_official	489:119543c9f674	689	#define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->IOPENR &= ~(RCC_IOPENR_GPIOAEN))
mbed_official	489:119543c9f674	690	#define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->IOPENR &= ~(RCC_IOPENR_GPIOBEN))
mbed_official	489:119543c9f674	691	#define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->IOPENR &= ~(RCC_IOPENR_GPIOCEN))
mbed_official	489:119543c9f674	692	#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->IOPENR &= ~(RCC_IOPENR_GPIODEN))
mbed_official	489:119543c9f674	693	#define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->IOPENR &= ~(RCC_IOPENR_GPIOHEN))
mbed_official	376:cb4d9db17537	694
mbed_official	376:cb4d9db17537	695
mbed_official	376:cb4d9db17537	696	/** @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
mbed_official	376:cb4d9db17537	697	* @note After reset, the peripheral clock (used for registers read/write access)
mbed_official	376:cb4d9db17537	698	* is disabled and the application software has to enable this clock before
mbed_official	376:cb4d9db17537	699	* using it.
mbed_official	376:cb4d9db17537	700	*/
mbed_official	489:119543c9f674	701	#define __HAL_RCC_WWDG_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_WWDGEN))
mbed_official	489:119543c9f674	702	#define __HAL_RCC_PWR_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_PWREN))
mbed_official	376:cb4d9db17537	703
mbed_official	489:119543c9f674	704	#define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_WWDGEN))
mbed_official	489:119543c9f674	705	#define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_PWREN))
mbed_official	376:cb4d9db17537	706
mbed_official	376:cb4d9db17537	707	/** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
mbed_official	376:cb4d9db17537	708	* @note After reset, the peripheral clock (used for registers read/write access)
mbed_official	376:cb4d9db17537	709	* is disabled and the application software has to enable this clock before
mbed_official	376:cb4d9db17537	710	* using it.
mbed_official	376:cb4d9db17537	711	*/
mbed_official	489:119543c9f674	712	#define __HAL_RCC_SYSCFG_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_SYSCFGEN))
mbed_official	489:119543c9f674	713	#define __HAL_RCC_DBGMCU_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_DBGMCUEN))
mbed_official	376:cb4d9db17537	714
mbed_official	489:119543c9f674	715	#define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~ (RCC_APB2ENR_SYSCFGEN))
mbed_official	489:119543c9f674	716	#define __HAL_RCC_DBGMCU_CLK_DISABLE() (RCC->APB2ENR &= ~ (RCC_APB2ENR_DBGMCUEN))
mbed_official	376:cb4d9db17537	717
mbed_official	376:cb4d9db17537	718	/** @brief Force or release AHB peripheral reset.
mbed_official	376:cb4d9db17537	719	*/
mbed_official	489:119543c9f674	720	#define __HAL_RCC_AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFF)
mbed_official	489:119543c9f674	721	#define __HAL_RCC_DMA1_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_DMA1RST))
mbed_official	489:119543c9f674	722	#define __HAL_RCC_MIF_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_MIFRST))
mbed_official	489:119543c9f674	723	#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_CRCRST))
mbed_official	376:cb4d9db17537	724
mbed_official	489:119543c9f674	725	#define __HAL_RCC_AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00)
mbed_official	489:119543c9f674	726	#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHBRSTR &= ~ (RCC_AHBRSTR_CRCRST))
mbed_official	489:119543c9f674	727	#define __HAL_RCC_DMA1_RELEASE_RESET() (RCC->AHBRSTR &= ~ (RCC_AHBRSTR_DMA1RST))
mbed_official	489:119543c9f674	728	#define __HAL_RCC_MIF_RELEASE_RESET() (RCC->AHBRSTR &= ~ (RCC_AHBRSTR_MIFRST))
mbed_official	376:cb4d9db17537	729
mbed_official	376:cb4d9db17537	730
mbed_official	376:cb4d9db17537	731	/** @brief Force or release IOPORT peripheral reset.
mbed_official	376:cb4d9db17537	732	*/
mbed_official	489:119543c9f674	733	#define __HAL_RCC_IOP_FORCE_RESET() (RCC->IOPRSTR = 0xFFFFFFFF)
mbed_official	489:119543c9f674	734	#define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->IOPRSTR \|= (RCC_IOPRSTR_GPIOARST))
mbed_official	489:119543c9f674	735	#define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->IOPRSTR \|= (RCC_IOPRSTR_GPIOBRST))
mbed_official	489:119543c9f674	736	#define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->IOPRSTR \|= (RCC_IOPRSTR_GPIOCRST))
mbed_official	489:119543c9f674	737	#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->IOPRSTR \|= (RCC_IOPRSTR_GPIODRST))
mbed_official	489:119543c9f674	738	#define __HAL_RCC_GPIOH_FORCE_RESET() (RCC->IOPRSTR \|= (RCC_IOPRSTR_GPIOHRST))
mbed_official	376:cb4d9db17537	739
mbed_official	489:119543c9f674	740	#define __HAL_RCC_IOP_RELEASE_RESET() (RCC->IOPRSTR = 0x00)
mbed_official	489:119543c9f674	741	#define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->IOPRSTR &= ~(RCC_IOPRSTR_GPIOARST))
mbed_official	489:119543c9f674	742	#define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->IOPRSTR &= ~(RCC_IOPRSTR_GPIOBRST))
mbed_official	489:119543c9f674	743	#define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->IOPRSTR &= ~(RCC_IOPRSTR_GPIOCRST))
mbed_official	489:119543c9f674	744	#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->IOPRSTR &= ~(RCC_IOPRSTR_GPIODRST))
mbed_official	489:119543c9f674	745	#define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->IOPRSTR &= ~(RCC_IOPRSTR_GPIOHRST))
mbed_official	376:cb4d9db17537	746
mbed_official	376:cb4d9db17537	747	/** @brief Force or release APB1 peripheral reset.
mbed_official	376:cb4d9db17537	748	*/
mbed_official	489:119543c9f674	749	#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFF)
mbed_official	489:119543c9f674	750	#define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_WWDGRST))
mbed_official	489:119543c9f674	751	#define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_PWRRST))
mbed_official	376:cb4d9db17537	752
mbed_official	489:119543c9f674	753	#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00)
mbed_official	489:119543c9f674	754	#define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_WWDGRST))
mbed_official	489:119543c9f674	755	#define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_PWRRST))
mbed_official	376:cb4d9db17537	756
mbed_official	376:cb4d9db17537	757	/** @brief Force or release APB2 peripheral reset.
mbed_official	376:cb4d9db17537	758	*/
mbed_official	489:119543c9f674	759	#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFF)
mbed_official	489:119543c9f674	760	#define __HAL_RCC_DBGMCU_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_DBGMCURST))
mbed_official	489:119543c9f674	761	#define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SYSCFGRST))
mbed_official	376:cb4d9db17537	762
mbed_official	489:119543c9f674	763	#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00)
mbed_official	489:119543c9f674	764	#define __HAL_RCC_DBGMCU_RELEASE_RESET() (RCC->APB2RSTR &= ~ (RCC_APB2RSTR_DBGMCURST))
mbed_official	489:119543c9f674	765	#define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~ (RCC_APB2RSTR_SYSCFGRST))
mbed_official	376:cb4d9db17537	766
mbed_official	376:cb4d9db17537	767	/** @brief Enable or disable the AHB peripheral clock during Low Power (Sleep) mode.
mbed_official	376:cb4d9db17537	768	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
mbed_official	376:cb4d9db17537	769	* power consumption.
mbed_official	376:cb4d9db17537	770	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
mbed_official	489:119543c9f674	771	* @note By default, all peripheral activated clocks remain enabled during SLEEP mode.
mbed_official	376:cb4d9db17537	772	*/
mbed_official	489:119543c9f674	773	#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHBSMENR \|= (RCC_AHBSMENR_CRCSMEN))
mbed_official	489:119543c9f674	774	#define __HAL_RCC_MIF_CLK_SLEEP_ENABLE() (RCC->AHBSMENR \|= (RCC_AHBSMENR_MIFSMEN))
mbed_official	489:119543c9f674	775	#define __HAL_RCC_SRAM_CLK_SLEEP_ENABLE() (RCC->AHBSMENR \|= (RCC_AHBSMENR_SRAMSMEN))
mbed_official	489:119543c9f674	776	#define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() (RCC->AHBSMENR \|= (RCC_AHBSMENR_DMA1SMEN))
mbed_official	376:cb4d9db17537	777
mbed_official	489:119543c9f674	778	#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHBSMENR &= ~ (RCC_AHBSMENR_CRCSMEN))
mbed_official	489:119543c9f674	779	#define __HAL_RCC_MIF_CLK_SLEEP_DISABLE() (RCC->AHBSMENR &= ~ (RCC_AHBSMENR_MIFSMEN))
mbed_official	489:119543c9f674	780	#define __HAL_RCC_SRAM_CLK_SLEEP_DISABLE() (RCC->AHBSMENR &= ~ (RCC_AHBSMENR_SRAMSMEN))
mbed_official	489:119543c9f674	781	#define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() (RCC->AHBSMENR &= ~ (RCC_AHBSMENR_DMA1SMEN))
mbed_official	376:cb4d9db17537	782
mbed_official	376:cb4d9db17537	783	/** @brief Enable or disable the IOPORT peripheral clock during Low Power (Sleep) mode.
mbed_official	376:cb4d9db17537	784	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
mbed_official	376:cb4d9db17537	785	* power consumption.
mbed_official	376:cb4d9db17537	786	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
mbed_official	489:119543c9f674	787	* @note By default, all peripheral activated clocks remain enabled during SLEEP mode.
mbed_official	376:cb4d9db17537	788	*/
mbed_official	376:cb4d9db17537	789
mbed_official	489:119543c9f674	790	#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() (RCC->IOPSMENR \|= (RCC_IOPSMENR_GPIOASMEN))
mbed_official	489:119543c9f674	791	#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() (RCC->IOPSMENR \|= (RCC_IOPSMENR_GPIOBSMEN))
mbed_official	489:119543c9f674	792	#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() (RCC->IOPSMENR \|= (RCC_IOPSMENR_GPIOCSMEN))
mbed_official	489:119543c9f674	793	#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->IOPSMENR \|= (RCC_IOPSMENR_GPIODSMEN))
mbed_official	489:119543c9f674	794	#define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() (RCC->IOPSMENR \|= (RCC_IOPSMENR_GPIOHSMEN))
mbed_official	376:cb4d9db17537	795
mbed_official	489:119543c9f674	796	#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() (RCC->IOPSMENR &= ~(RCC_IOPSMENR_GPIOASMEN))
mbed_official	489:119543c9f674	797	#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() (RCC->IOPSMENR &= ~(RCC_IOPSMENR_GPIOBSMEN))
mbed_official	489:119543c9f674	798	#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() (RCC->IOPSMENR &= ~(RCC_IOPSMENR_GPIOCSMEN))
mbed_official	489:119543c9f674	799	#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->IOPSMENR &= ~(RCC_IOPSMENR_GPIODSMEN))
mbed_official	489:119543c9f674	800	#define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() (RCC->IOPSMENR &= ~(RCC_IOPSMENR_GPIOHSMEN))
mbed_official	376:cb4d9db17537	801
mbed_official	376:cb4d9db17537	802	/** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
mbed_official	376:cb4d9db17537	803	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
mbed_official	376:cb4d9db17537	804	* power consumption.
mbed_official	376:cb4d9db17537	805	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
mbed_official	489:119543c9f674	806	* @note By default, all peripheral activated clocks remain enabled during SLEEP mode.
mbed_official	376:cb4d9db17537	807	*/
mbed_official	489:119543c9f674	808	#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() (RCC->APB1SMENR \|= (RCC_APB1SMENR_WWDGSMEN))
mbed_official	489:119543c9f674	809	#define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() (RCC->APB1SMENR \|= (RCC_APB1SMENR_PWRSMEN))
mbed_official	376:cb4d9db17537	810
mbed_official	489:119543c9f674	811	#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_WWDGSMEN))
mbed_official	489:119543c9f674	812	#define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_PWRSMEN))
mbed_official	376:cb4d9db17537	813
mbed_official	376:cb4d9db17537	814	/** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
mbed_official	376:cb4d9db17537	815	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
mbed_official	376:cb4d9db17537	816	* power consumption.
mbed_official	376:cb4d9db17537	817	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
mbed_official	489:119543c9f674	818	* @note By default, all peripheral actiated clocks remain enabled during SLEEP mode.
mbed_official	376:cb4d9db17537	819	*/
mbed_official	489:119543c9f674	820	#define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB2SMENR \|= (RCC_APB2SMENR_SYSCFGSMEN))
mbed_official	489:119543c9f674	821	#define __HAL_RCC_DBGMCU_CLK_SLEEP_ENABLE() (RCC->APB2SMENR \|= (RCC_APB2SMENR_DBGMCUSMEN))
mbed_official	376:cb4d9db17537	822
mbed_official	489:119543c9f674	823	#define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB2SMENR &= ~ (RCC_APB2SMENR_SYSCFGSMEN))
mbed_official	489:119543c9f674	824	#define __HAL_RCC_DBGMCU_CLK_SLEEP_DISABLE() (RCC->APB2SMENR &= ~ (RCC_APB2SMENR_DBGMCUSMEN))
mbed_official	376:cb4d9db17537	825
mbed_official	376:cb4d9db17537	826	/** @brief Macro to enable or disable the Internal High Speed oscillator (HSI).
mbed_official	376:cb4d9db17537	827	* @note After enabling the HSI, the application software should wait on
mbed_official	376:cb4d9db17537	828	* HSIRDY flag to be set indicating that HSI clock is stable and can
mbed_official	376:cb4d9db17537	829	* be used to clock the PLL and/or system clock.
mbed_official	376:cb4d9db17537	830	* @note HSI can not be stopped if it is used directly or through the PLL
mbed_official	376:cb4d9db17537	831	* as system clock. In this case, you have to select another source
mbed_official	376:cb4d9db17537	832	* of the system clock then stop the HSI.
mbed_official	376:cb4d9db17537	833	* @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
mbed_official	376:cb4d9db17537	834	* @param __STATE__: specifies the new state of the HSI.
mbed_official	376:cb4d9db17537	835	* This parameter can be one of the following values:
mbed_official	376:cb4d9db17537	836	* @arg RCC_HSI_OFF: turn OFF the HSI oscillator
mbed_official	376:cb4d9db17537	837	* @arg RCC_HSI_ON: turn ON the HSI oscillator
mbed_official	376:cb4d9db17537	838	* @arg RCC_HSI_DIV4: turn ON the HSI oscillator and divide it by 4
mbed_official	376:cb4d9db17537	839	* @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
mbed_official	376:cb4d9db17537	840	* clock cycles.
mbed_official	376:cb4d9db17537	841	*/
mbed_official	376:cb4d9db17537	842	#define __HAL_RCC_HSI_CONFIG(__STATE__) \
mbed_official	489:119543c9f674	843	MODIFY_REG(RCC->CR, RCC_CR_HSION \| RCC_CR_HSIDIVEN , (uint32_t)(__STATE__))
mbed_official	376:cb4d9db17537	844
mbed_official	376:cb4d9db17537	845	/** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
mbed_official	376:cb4d9db17537	846	* @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
mbed_official	376:cb4d9db17537	847	* It is used (enabled by hardware) as system clock source after startup
mbed_official	376:cb4d9db17537	848	* from Reset, wakeup from STOP and STANDBY mode, or in case of failure
mbed_official	376:cb4d9db17537	849	* of the HSE used directly or indirectly as system clock (if the Clock
mbed_official	376:cb4d9db17537	850	* Security System CSS is enabled).
mbed_official	376:cb4d9db17537	851	* @note HSI can not be stopped if it is used as system clock source. In this case,
mbed_official	376:cb4d9db17537	852	* you have to select another source of the system clock then stop the HSI.
mbed_official	376:cb4d9db17537	853	* @note After enabling the HSI, the application software should wait on HSIRDY
mbed_official	376:cb4d9db17537	854	* flag to be set indicating that HSI clock is stable and can be used as
mbed_official	376:cb4d9db17537	855	* system clock source.
mbed_official	376:cb4d9db17537	856	* @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
mbed_official	376:cb4d9db17537	857	* clock cycles.
mbed_official	376:cb4d9db17537	858	*/
mbed_official	376:cb4d9db17537	859	#define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION)
mbed_official	376:cb4d9db17537	860	#define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION)
mbed_official	376:cb4d9db17537	861
mbed_official	376:cb4d9db17537	862	/**
mbed_official	376:cb4d9db17537	863	* @brief Macros to enable or disable the Internal Multi Speed oscillator (MSI).
mbed_official	376:cb4d9db17537	864	* @note The MSI is stopped by hardware when entering STOP and STANDBY modes.
mbed_official	376:cb4d9db17537	865	* It is used (enabled by hardware) as system clock source after
mbed_official	376:cb4d9db17537	866	* startup from Reset, wakeup from STOP and STANDBY mode, or in case
mbed_official	376:cb4d9db17537	867	* of failure of the HSE used directly or indirectly as system clock
mbed_official	376:cb4d9db17537	868	* (if the Clock Security System CSS is enabled).
mbed_official	376:cb4d9db17537	869	* @note MSI can not be stopped if it is used as system clock source.
mbed_official	376:cb4d9db17537	870	* In this case, you have to select another source of the system
mbed_official	376:cb4d9db17537	871	* clock then stop the MSI.
mbed_official	376:cb4d9db17537	872	* @note After enabling the MSI, the application software should wait on
mbed_official	376:cb4d9db17537	873	* MSIRDY flag to be set indicating that MSI clock is stable and can
mbed_official	376:cb4d9db17537	874	* be used as system clock source.
mbed_official	376:cb4d9db17537	875	* @note When the MSI is stopped, MSIRDY flag goes low after 6 MSI oscillator
mbed_official	376:cb4d9db17537	876	* clock cycles.
mbed_official	376:cb4d9db17537	877	*/
mbed_official	376:cb4d9db17537	878	#define __HAL_RCC_MSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_MSION)
mbed_official	376:cb4d9db17537	879	#define __HAL_RCC_MSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_MSION)
mbed_official	376:cb4d9db17537	880
mbed_official	376:cb4d9db17537	881	/** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
mbed_official	376:cb4d9db17537	882	* @note The calibration is used to compensate for the variations in voltage
mbed_official	376:cb4d9db17537	883	* and temperature that influence the frequency of the internal HSI RC.
mbed_official	376:cb4d9db17537	884	* @param __HSICalibrationValue__: specifies the calibration trimming value.
mbed_official	376:cb4d9db17537	885	* This parameter must be a number between 0 and 0x1F.
mbed_official	376:cb4d9db17537	886	*/
mbed_official	376:cb4d9db17537	887	#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) (MODIFY_REG(RCC->ICSCR,\
mbed_official	376:cb4d9db17537	888	RCC_ICSCR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << 8))
mbed_official	376:cb4d9db17537	889
mbed_official	376:cb4d9db17537	890	/** @brief Macro Adjusts the Internal Multi Speed oscillator (MSI) calibration value.
mbed_official	376:cb4d9db17537	891	* @note The calibration is used to compensate for the variations in voltage
mbed_official	376:cb4d9db17537	892	* and temperature that influence the frequency of the internal MSI RC.
mbed_official	376:cb4d9db17537	893	* Refer to the Application Note AN3300 for more details on how to
mbed_official	376:cb4d9db17537	894	* calibrate the MSI.
mbed_official	376:cb4d9db17537	895	* @param __MSICalibrationValue__: specifies the calibration trimming value.
mbed_official	376:cb4d9db17537	896	* This parameter must be a number between 0 and 0xFF.
mbed_official	376:cb4d9db17537	897	*/
mbed_official	376:cb4d9db17537	898	#define __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(__MSICalibrationValue__) (MODIFY_REG(RCC->ICSCR,\
mbed_official	376:cb4d9db17537	899	RCC_ICSCR_MSITRIM, (uint32_t)(__MSICalibrationValue__) << 24))
mbed_official	376:cb4d9db17537	900
mbed_official	376:cb4d9db17537	901	/**
mbed_official	376:cb4d9db17537	902	* @brief Macro to configures the Internal Multi Speed oscillator (MSI) clock range.
mbed_official	376:cb4d9db17537	903	* @note After restart from Reset or wakeup from STANDBY, the MSI clock is
mbed_official	376:cb4d9db17537	904	* around 2.097 MHz. The MSI clock does not change after wake-up from
mbed_official	376:cb4d9db17537	905	* STOP mode.
mbed_official	376:cb4d9db17537	906	* @note The MSI clock range can be modified on the fly.
mbed_official	376:cb4d9db17537	907	* @param RCC_MSIRange: specifies the MSI Clock range.
mbed_official	376:cb4d9db17537	908	* This parameter must be one of the following values:
mbed_official	376:cb4d9db17537	909	* @arg RCC_MSIRANGE_0: MSI clock is around 65.536 KHz
mbed_official	376:cb4d9db17537	910	* @arg RCC_MSIRANGE_1: MSI clock is around 131.072 KHz
mbed_official	376:cb4d9db17537	911	* @arg RCC_MSIRANGE_2: MSI clock is around 262.144 KHz
mbed_official	376:cb4d9db17537	912	* @arg RCC_MSIRANGE_3: MSI clock is around 524.288 KHz
mbed_official	376:cb4d9db17537	913	* @arg RCC_MSIRANGE_4: MSI clock is around 1.048 MHz
mbed_official	376:cb4d9db17537	914	* @arg RCC_MSIRANGE_5: MSI clock is around 2.097 MHz (default after Reset or wake-up from STANDBY)
mbed_official	376:cb4d9db17537	915	* @arg RCC_MSIRANGE_6: MSI clock is around 4.194 MHz
mbed_official	376:cb4d9db17537	916	*/
mbed_official	376:cb4d9db17537	917	#define __HAL_RCC_MSI_RANGE_CONFIG(__RCC_MSIRange__) (MODIFY_REG(RCC->ICSCR,\
mbed_official	376:cb4d9db17537	918	RCC_ICSCR_MSIRANGE, (uint32_t)(__RCC_MSIRange__) ))
mbed_official	376:cb4d9db17537	919
mbed_official	376:cb4d9db17537	920	/** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI).
mbed_official	376:cb4d9db17537	921	* @note After enabling the LSI, the application software should wait on
mbed_official	376:cb4d9db17537	922	* LSIRDY flag to be set indicating that LSI clock is stable and can
mbed_official	376:cb4d9db17537	923	* be used to clock the IWDG and/or the RTC.
mbed_official	376:cb4d9db17537	924	* @note LSI can not be disabled if the IWDG is running.
mbed_official	376:cb4d9db17537	925	* @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
mbed_official	376:cb4d9db17537	926	* clock cycles.
mbed_official	376:cb4d9db17537	927	*/
mbed_official	376:cb4d9db17537	928	#define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION)
mbed_official	376:cb4d9db17537	929	#define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_LSION)
mbed_official	376:cb4d9db17537	930
mbed_official	376:cb4d9db17537	931	/**
mbed_official	376:cb4d9db17537	932	* @brief Macro to configure the External High Speed oscillator (HSE).
mbed_official	376:cb4d9db17537	933	* @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
mbed_official	376:cb4d9db17537	934	* software should wait on HSERDY flag to be set indicating that HSE clock
mbed_official	376:cb4d9db17537	935	* is stable and can be used to clock the PLL and/or system clock.
mbed_official	376:cb4d9db17537	936	* @note HSE state can not be changed if it is used directly or through the
mbed_official	376:cb4d9db17537	937	* PLL as system clock. In this case, you have to select another source
mbed_official	376:cb4d9db17537	938	* of the system clock then change the HSE state (ex. disable it).
mbed_official	376:cb4d9db17537	939	* @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
mbed_official	376:cb4d9db17537	940	* @note This function reset the CSSON bit, so if the clock security system(CSS)
mbed_official	376:cb4d9db17537	941	* was previously enabled you have to enable it again after calling this
mbed_official	376:cb4d9db17537	942	* function.
mbed_official	376:cb4d9db17537	943	* @param __STATE__: specifies the new state of the HSE.
mbed_official	376:cb4d9db17537	944	* This parameter can be one of the following values:
mbed_official	376:cb4d9db17537	945	* @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
mbed_official	376:cb4d9db17537	946	* 6 HSE oscillator clock cycles.
mbed_official	376:cb4d9db17537	947	* @arg RCC_HSE_ON: turn ON the HSE oscillator.
mbed_official	376:cb4d9db17537	948	* @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock.
mbed_official	376:cb4d9db17537	949	*/
mbed_official	376:cb4d9db17537	950	#define __HAL_RCC_HSE_CONFIG(__STATE__) \
mbed_official	489:119543c9f674	951	do { \
mbed_official	489:119543c9f674	952	CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
mbed_official	489:119543c9f674	953	if((__STATE__) == RCC_HSE_ON) \
mbed_official	489:119543c9f674	954	{ \
mbed_official	489:119543c9f674	955	CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
mbed_official	489:119543c9f674	956	SET_BIT(RCC->CR, RCC_CR_HSEON); \
mbed_official	489:119543c9f674	957	} \
mbed_official	489:119543c9f674	958	else if((__STATE__) == RCC_HSE_BYPASS) \
mbed_official	489:119543c9f674	959	{ \
mbed_official	489:119543c9f674	960	SET_BIT(RCC->CR, RCC_CR_HSEBYP); \
mbed_official	489:119543c9f674	961	SET_BIT(RCC->CR, RCC_CR_HSEON); \
mbed_official	489:119543c9f674	962	} \
mbed_official	489:119543c9f674	963	else \
mbed_official	489:119543c9f674	964	{ \
mbed_official	489:119543c9f674	965	CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
mbed_official	489:119543c9f674	966	} \
mbed_official	489:119543c9f674	967	} while(0)
mbed_official	489:119543c9f674	968
mbed_official	376:cb4d9db17537	969	/**
mbed_official	376:cb4d9db17537	970	* @brief Macro to configure the External Low Speed oscillator (LSE).
mbed_official	376:cb4d9db17537	971	* @note As the LSE is in the Backup domain and write access is denied to
mbed_official	376:cb4d9db17537	972	* this domain after reset, you have to enable write access using
mbed_official	376:cb4d9db17537	973	* HAL_PWR_EnableBkUpAccess() function before to configure the LSE
mbed_official	376:cb4d9db17537	974	* (to be done once after reset).
mbed_official	376:cb4d9db17537	975	* @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
mbed_official	376:cb4d9db17537	976	* software should wait on LSERDY flag to be set indicating that LSE clock
mbed_official	376:cb4d9db17537	977	* is stable and can be used to clock the RTC.
mbed_official	376:cb4d9db17537	978	* @param __STATE__: specifies the new state of the LSE.
mbed_official	376:cb4d9db17537	979	* This parameter can be one of the following values:
mbed_official	376:cb4d9db17537	980	* @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
mbed_official	376:cb4d9db17537	981	* 6 LSE oscillator clock cycles.
mbed_official	376:cb4d9db17537	982	* @arg RCC_LSE_ON: turn ON the LSE oscillator.
mbed_official	376:cb4d9db17537	983	* @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock.
mbed_official	376:cb4d9db17537	984	*/
mbed_official	376:cb4d9db17537	985	#define __HAL_RCC_LSE_CONFIG(__STATE__) \
mbed_official	489:119543c9f674	986	do { \
mbed_official	489:119543c9f674	987	if((__STATE__) == RCC_LSE_ON) \
mbed_official	489:119543c9f674	988	{ \
mbed_official	489:119543c9f674	989	SET_BIT(RCC->CSR, RCC_CSR_LSEON); \
mbed_official	489:119543c9f674	990	} \
mbed_official	489:119543c9f674	991	else if((__STATE__) == RCC_LSE_OFF) \
mbed_official	489:119543c9f674	992	{ \
mbed_official	489:119543c9f674	993	CLEAR_BIT(RCC->CSR, RCC_CSR_LSEON); \
mbed_official	489:119543c9f674	994	} \
mbed_official	489:119543c9f674	995	else if((__STATE__) == RCC_LSE_BYPASS) \
mbed_official	489:119543c9f674	996	{ \
mbed_official	489:119543c9f674	997	CLEAR_BIT(RCC->CSR, RCC_CSR_LSEON); \
mbed_official	489:119543c9f674	998	SET_BIT(RCC->CSR, RCC_CSR_LSEBYP); \
mbed_official	489:119543c9f674	999	SET_BIT(RCC->CSR, RCC_CSR_LSEON); \
mbed_official	489:119543c9f674	1000	} \
mbed_official	489:119543c9f674	1001	else \
mbed_official	489:119543c9f674	1002	{ \
mbed_official	489:119543c9f674	1003	CLEAR_BIT(RCC->CSR, RCC_CSR_LSEON); \
mbed_official	489:119543c9f674	1004	CLEAR_BIT(RCC->CSR, RCC_CSR_LSEBYP); \
mbed_official	489:119543c9f674	1005	} \
mbed_official	489:119543c9f674	1006	} while(0)
mbed_official	376:cb4d9db17537	1007
mbed_official	376:cb4d9db17537	1008	/** @brief Macros to enable or disable the the RTC clock.
mbed_official	376:cb4d9db17537	1009	* @note These macros must be used only after the RTC clock source was selected.
mbed_official	376:cb4d9db17537	1010	*/
mbed_official	376:cb4d9db17537	1011	#define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_RTCEN)
mbed_official	376:cb4d9db17537	1012	#define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_RTCEN)
mbed_official	376:cb4d9db17537	1013
mbed_official	376:cb4d9db17537	1014	/**
mbed_official	376:cb4d9db17537	1015	* @brief Configures or Get the RTC and LCD clock (RTCCLK / LCDCLK).
mbed_official	376:cb4d9db17537	1016	* @note As the RTC clock configuration bits are in the RTC domain and write
mbed_official	376:cb4d9db17537	1017	* access is denied to this domain after reset, you have to enable write
mbed_official	376:cb4d9db17537	1018	* access using PWR_RTCAccessCmd(ENABLE) function before to configure
mbed_official	376:cb4d9db17537	1019	* the RTC clock source (to be done once after reset).
mbed_official	489:119543c9f674	1020	* @note Once the RTC clock is configured it cannot be changed unless the RTC
mbed_official	376:cb4d9db17537	1021	* is reset using RCC_RTCResetCmd function, or by a Power On Reset (POR)
mbed_official	376:cb4d9db17537	1022	* @note The RTC clock (RTCCLK) is used also to clock the LCD (LCDCLK).
mbed_official	376:cb4d9db17537	1023	*
mbed_official	376:cb4d9db17537	1024	* @param RCC_RTCCLKSource: specifies the RTC clock source.
mbed_official	376:cb4d9db17537	1025	* This parameter can be one of the following values:
mbed_official	376:cb4d9db17537	1026	* @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock
mbed_official	376:cb4d9db17537	1027	* @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock
mbed_official	376:cb4d9db17537	1028	* @arg RCC_RTCCLKSOURCE_HSE_DIV2: HSE divided by 2 selected as RTC clock
mbed_official	376:cb4d9db17537	1029	* @arg RCC_RTCCLKSOURCE_HSE_DIV4: HSE divided by 4 selected as RTC clock
mbed_official	376:cb4d9db17537	1030	* @arg RCC_RTCCLKSOURCE_HSE_DIV8: HSE divided by 8 selected as RTC clock
mbed_official	376:cb4d9db17537	1031	* @arg RCC_RTCCLKSOURCE_HSE_DIV16: HSE divided by 16 selected as RTC clock
mbed_official	376:cb4d9db17537	1032	*
mbed_official	376:cb4d9db17537	1033	* @note If the LSE or LSI is used as RTC clock source, the RTC continues to
mbed_official	376:cb4d9db17537	1034	* work in STOP and STANDBY modes, and can be used as wakeup source.
mbed_official	376:cb4d9db17537	1035	* However, when the HSE clock is used as RTC clock source, the RTC
mbed_official	376:cb4d9db17537	1036	* cannot be used in STOP and STANDBY modes.
mbed_official	376:cb4d9db17537	1037	* @note The maximum input clock frequency for RTC is 1MHz (when using HSE as
mbed_official	376:cb4d9db17537	1038	* RTC clock source).
mbed_official	376:cb4d9db17537	1039	*/
mbed_official	376:cb4d9db17537	1040	#define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_CSR_RTCSEL) == RCC_CSR_RTCSEL) ? \
mbed_official	376:cb4d9db17537	1041	MODIFY_REG(RCC->CR, RCC_CR_RTCPRE, ((__RTCCLKSource__) & 0xFFFCFFFF)) : CLEAR_BIT(RCC->CR, RCC_CR_RTCPRE)
mbed_official	376:cb4d9db17537	1042
mbed_official	376:cb4d9db17537	1043	#define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__); \
mbed_official	376:cb4d9db17537	1044	MODIFY_REG( RCC->CSR, RCC_CSR_RTCSEL, (uint32_t)(__RTCCLKSource__)); \
mbed_official	376:cb4d9db17537	1045	} while (0)
mbed_official	376:cb4d9db17537	1046
mbed_official	376:cb4d9db17537	1047	#define __HAL_RCC_GET_RTC_SOURCE() ((uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_RTCSEL)))
mbed_official	376:cb4d9db17537	1048
mbed_official	376:cb4d9db17537	1049	/** @brief Macros to force or release the Backup domain reset.
mbed_official	376:cb4d9db17537	1050	* @note This function resets the RTC peripheral (including the backup registers)
mbed_official	376:cb4d9db17537	1051	* and the RTC clock source selection in RCC_CSR register.
mbed_official	376:cb4d9db17537	1052	* @note The BKPSRAM is not affected by this reset.
mbed_official	376:cb4d9db17537	1053	*/
mbed_official	376:cb4d9db17537	1054	#define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->CSR, RCC_CSR_RTCRST)
mbed_official	376:cb4d9db17537	1055	#define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->CSR, RCC_CSR_RTCRST)
mbed_official	376:cb4d9db17537	1056
mbed_official	376:cb4d9db17537	1057	/** @brief Macros to enable or disable the main PLL.
mbed_official	376:cb4d9db17537	1058	* @note After enabling the main PLL, the application software should wait on
mbed_official	376:cb4d9db17537	1059	* PLLRDY flag to be set indicating that PLL clock is stable and can
mbed_official	376:cb4d9db17537	1060	* be used as system clock source.
mbed_official	376:cb4d9db17537	1061	* @note The main PLL can not be disabled if it is used as system clock source
mbed_official	376:cb4d9db17537	1062	* @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
mbed_official	376:cb4d9db17537	1063	*/
mbed_official	376:cb4d9db17537	1064	#define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON)
mbed_official	376:cb4d9db17537	1065	#define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON)
mbed_official	376:cb4d9db17537	1066
mbed_official	376:cb4d9db17537	1067	/** @brief Macro to configure the main PLL clock source, multiplication and division factors.
mbed_official	376:cb4d9db17537	1068	* @note This function must be used only when the main PLL is disabled.
mbed_official	376:cb4d9db17537	1069	* @param __RCC_PLLSource__: specifies the PLL entry clock source.
mbed_official	376:cb4d9db17537	1070	* This parameter can be one of the following values:
mbed_official	376:cb4d9db17537	1071	* @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
mbed_official	376:cb4d9db17537	1072	* @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
mbed_official	376:cb4d9db17537	1073	* @param __PLLMUL__: specifies the multiplication factor to generate the PLL VCO clock
mbed_official	376:cb4d9db17537	1074	* This parameter must be one of the following values:
mbed_official	376:cb4d9db17537	1075	* @arg RCC_CFGR_PLLMUL3: PLLVCO = PLL clock entry x 3
mbed_official	376:cb4d9db17537	1076	* @arg RCC_CFGR_PLLMUL4: PLLVCO = PLL clock entry x 4
mbed_official	376:cb4d9db17537	1077	* @arg RCC_CFGR_PLLMUL6: PLLVCO = PLL clock entry x 6
mbed_official	376:cb4d9db17537	1078	* @arg RCC_CFGR_PLLMUL8: PLLVCO = PLL clock entry x 8
mbed_official	376:cb4d9db17537	1079	* @arg RCC_CFGR_PLLMUL12: PLLVCO = PLL clock entry x 12
mbed_official	376:cb4d9db17537	1080	* @arg RCC_CFGR_PLLMUL16: PLLVCO = PLL clock entry x 16
mbed_official	376:cb4d9db17537	1081	* @arg RCC_CFGR_PLLMUL24: PLLVCO = PLL clock entry x 24
mbed_official	376:cb4d9db17537	1082	* @arg RCC_CFGR_PLLMUL32: PLLVCO = PLL clock entry x 32
mbed_official	376:cb4d9db17537	1083	* @arg RCC_CFGR_PLLMUL48: PLLVCO = PLL clock entry x 48
mbed_official	376:cb4d9db17537	1084	* @note The PLL VCO clock frequency must not exceed 96 MHz when the product is in
mbed_official	376:cb4d9db17537	1085	* Range 1, 48 MHz when the product is in Range 2 and 24 MHz when the product is
mbed_official	376:cb4d9db17537	1086	* in Range 3.
mbed_official	376:cb4d9db17537	1087	* @param __PLLDIV__: specifies the PLL output clock division from PLL VCO clock
mbed_official	376:cb4d9db17537	1088	* This parameter must be one of the following values:
mbed_official	376:cb4d9db17537	1089	* @arg RCC_PLLDIV_2: PLL clock output = PLLVCO / 2
mbed_official	376:cb4d9db17537	1090	* @arg RCC_PLLDIV_3: PLL clock output = PLLVCO / 3
mbed_official	376:cb4d9db17537	1091	* @arg RCC_PLLDIV_4: PLL clock output = PLLVCO / 4
mbed_official	376:cb4d9db17537	1092	*/
mbed_official	376:cb4d9db17537	1093
mbed_official	376:cb4d9db17537	1094	#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__ , __PLLMUL__ ,__PLLDIV__ ) \
mbed_official	376:cb4d9db17537	1095	MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLMUL \| RCC_CFGR_PLLDIV \| RCC_CFGR_PLLSRC, (uint32_t)((__PLLMUL__)\| (__PLLDIV__)\| (__RCC_PLLSource__)))
mbed_official	376:cb4d9db17537	1096
mbed_official	376:cb4d9db17537	1097	/** @brief Macro to get the clock source used as system clock.
mbed_official	376:cb4d9db17537	1098	* @retval The clock source used as system clock. The returned value can be one
mbed_official	376:cb4d9db17537	1099	* of the following:
mbed_official	376:cb4d9db17537	1100	* - RCC_CFGR_SWS_HSI: HSI used as system clock.
mbed_official	376:cb4d9db17537	1101	* - RCC_CFGR_SWS_HSE: HSE used as system clock.
mbed_official	376:cb4d9db17537	1102	* - RCC_CFGR_SWS_PLL: PLL used as system clock.
mbed_official	376:cb4d9db17537	1103	*/
mbed_official	376:cb4d9db17537	1104	#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS))
mbed_official	376:cb4d9db17537	1105
mbed_official	376:cb4d9db17537	1106	/** @brief Macro to get the oscillator used as PLL clock source.
mbed_official	376:cb4d9db17537	1107	* @retval The oscillator used as PLL clock source. The returned value can be one
mbed_official	376:cb4d9db17537	1108	* of the following:
mbed_official	376:cb4d9db17537	1109	* - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
mbed_official	376:cb4d9db17537	1110	* - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.
mbed_official	376:cb4d9db17537	1111	*/
mbed_official	376:cb4d9db17537	1112	#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_PLLSRC))
mbed_official	376:cb4d9db17537	1113
mbed_official	376:cb4d9db17537	1114	/** @defgroup RCC_Flags_Interrupts_Management
mbed_official	376:cb4d9db17537	1115	* @brief macros to manage the specified RCC Flags and interrupts.
mbed_official	376:cb4d9db17537	1116	* @{
mbed_official	376:cb4d9db17537	1117	*/
mbed_official	376:cb4d9db17537	1118
mbed_official	376:cb4d9db17537	1119	/** @brief Enable RCC interrupt (Perform Byte access to RCC_CIER[0:7] bits to enable
mbed_official	376:cb4d9db17537	1120	* the selected interrupts).
mbed_official	376:cb4d9db17537	1121	* @note The CSS interrupt doesn't have an enable bit; once the CSS is enabled
mbed_official	376:cb4d9db17537	1122	* and if the HSE clock fails, the CSS interrupt occurs and an NMI is
mbed_official	376:cb4d9db17537	1123	* automatically generated. The NMI will be executed indefinitely, and
mbed_official	376:cb4d9db17537	1124	* since NMI has higher priority than any other IRQ (and main program)
mbed_official	376:cb4d9db17537	1125	* the application will be stacked in the NMI ISR unless the CSS interrupt
mbed_official	376:cb4d9db17537	1126	* pending bit is cleared.
mbed_official	376:cb4d9db17537	1127	* @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled.
mbed_official	376:cb4d9db17537	1128	* This parameter can be any combination of the following values:
mbed_official	376:cb4d9db17537	1129	* @arg RCC_IT_LSIRDY: LSI ready interrupt
mbed_official	376:cb4d9db17537	1130	* @arg RCC_IT_LSERDY: LSE ready interrupt
mbed_official	376:cb4d9db17537	1131	* @arg RCC_IT_HSIRDY: HSI ready interrupt
mbed_official	376:cb4d9db17537	1132	* @arg RCC_IT_HSERDY: HSE ready interrupt
mbed_official	376:cb4d9db17537	1133	* @arg RCC_IT_PLLRDY: PLL ready interrupt
mbed_official	376:cb4d9db17537	1134	* @arg RCC_IT_MSIRDY: MSI ready interrupt
mbed_official	376:cb4d9db17537	1135	* @arg RCC_IT_LSECSS: LSE CSS interrupt
mbed_official	489:119543c9f674	1136	* @arg RCC_IT_HSI48RDY: HSI48 ready interrupt
mbed_official	376:cb4d9db17537	1137	*/
mbed_official	489:119543c9f674	1138	#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (RCC->CIER \|= (__INTERRUPT__))
mbed_official	376:cb4d9db17537	1139
mbed_official	376:cb4d9db17537	1140	/** @brief Disable RCC interrupt (Perform Byte access to RCC_CIER[0:7] bits to disable
mbed_official	376:cb4d9db17537	1141	* the selected interrupts).
mbed_official	376:cb4d9db17537	1142	* @note The CSS interrupt doesn't have an enable bit; once the CSS is enabled
mbed_official	376:cb4d9db17537	1143	* and if the HSE clock fails, the CSS interrupt occurs and an NMI is
mbed_official	376:cb4d9db17537	1144	* automatically generated. The NMI will be executed indefinitely, and
mbed_official	376:cb4d9db17537	1145	* since NMI has higher priority than any other IRQ (and main program)
mbed_official	376:cb4d9db17537	1146	* the application will be stacked in the NMI ISR unless the CSS interrupt
mbed_official	376:cb4d9db17537	1147	* pending bit is cleared.
mbed_official	376:cb4d9db17537	1148	* @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled.
mbed_official	376:cb4d9db17537	1149	* This parameter can be any combination of the following values:
mbed_official	376:cb4d9db17537	1150	* @arg RCC_IT_LSIRDY: LSI ready interrupt
mbed_official	376:cb4d9db17537	1151	* @arg RCC_IT_LSERDY: LSE ready interrupt
mbed_official	376:cb4d9db17537	1152	* @arg RCC_IT_HSIRDY: HSI ready interrupt
mbed_official	376:cb4d9db17537	1153	* @arg RCC_IT_HSERDY: HSE ready interrupt
mbed_official	376:cb4d9db17537	1154	* @arg RCC_IT_PLLRDY: PLL ready interrupt
mbed_official	376:cb4d9db17537	1155	* @arg RCC_IT_MSIRDY: MSI ready interrupt
mbed_official	489:119543c9f674	1156	* @arg RCC_IT_HSI48RDY: HSI48 ready interrupt
mbed_official	376:cb4d9db17537	1157	* @arg RCC_IT_LSECSS: LSE CSS interrupt
mbed_official	489:119543c9f674	1158
mbed_official	376:cb4d9db17537	1159	*/
mbed_official	489:119543c9f674	1160	#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (RCC->CIER &= ~(__INTERRUPT__))
mbed_official	376:cb4d9db17537	1161
mbed_official	376:cb4d9db17537	1162	/** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16]
mbed_official	376:cb4d9db17537	1163	* bits to clear the selected interrupt pending bits.
mbed_official	376:cb4d9db17537	1164	* @param __INTERRUPT__: specifies the interrupt pending bit to clear.
mbed_official	376:cb4d9db17537	1165	* This parameter can be any combination of the following values:
mbed_official	376:cb4d9db17537	1166	* @arg RCC_IT_LSIRDY: LSI ready interrupt
mbed_official	376:cb4d9db17537	1167	* @arg RCC_IT_LSERDY: LSE ready interrupt
mbed_official	376:cb4d9db17537	1168	* @arg RCC_IT_HSIRDY: HSI ready interrupt
mbed_official	376:cb4d9db17537	1169	* @arg RCC_IT_HSERDY: HSE ready interrupt
mbed_official	376:cb4d9db17537	1170	* @arg RCC_IT_PLLRDY: PLL ready interrupt
mbed_official	489:119543c9f674	1171	* @arg RCC_IT_MSIRDY: MSI ready interrupt
mbed_official	489:119543c9f674	1172	* @arg RCC_IT_HSI48RDY: HSI48 ready interrupt
mbed_official	376:cb4d9db17537	1173	* @arg RCC_IT_LSECSS: LSE CSS interrupt
mbed_official	376:cb4d9db17537	1174	* @arg RCC_IT_CSS: Clock Security System interrupt
mbed_official	376:cb4d9db17537	1175	*/
mbed_official	376:cb4d9db17537	1176	#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (RCC->CICR = (__INTERRUPT__))
mbed_official	376:cb4d9db17537	1177
mbed_official	376:cb4d9db17537	1178	/** @brief Check the RCC's interrupt has occurred or not.
mbed_official	376:cb4d9db17537	1179	* @param __INTERRUPT__: specifies the RCC interrupt source to check.
mbed_official	376:cb4d9db17537	1180	* This parameter can be one of the following values:
mbed_official	376:cb4d9db17537	1181	* @arg RCC_IT_LSIRDY: LSI ready interrupt
mbed_official	376:cb4d9db17537	1182	* @arg RCC_IT_LSERDY: LSE ready interrupt
mbed_official	376:cb4d9db17537	1183	* @arg RCC_IT_HSIRDY: HSI ready interrupt
mbed_official	376:cb4d9db17537	1184	* @arg RCC_IT_HSERDY: HSE ready interrupt
mbed_official	376:cb4d9db17537	1185	* @arg RCC_IT_PLLRDY: PLL ready interrupt
mbed_official	376:cb4d9db17537	1186	* @arg RCC_IT_MSIRDY: MSI ready interrupt
mbed_official	376:cb4d9db17537	1187	* @arg RCC_IT_LSECSS: LSE CSS interrupt
mbed_official	376:cb4d9db17537	1188	* @arg RCC_IT_CSS: Clock Security System interrupt
mbed_official	376:cb4d9db17537	1189	* @retval The new state of __INTERRUPT__ (TRUE or FALSE).
mbed_official	376:cb4d9db17537	1190	*/
mbed_official	489:119543c9f674	1191	#define __HAL_RCC_GET_IT_SOURCE(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__))
mbed_official	376:cb4d9db17537	1192
mbed_official	376:cb4d9db17537	1193	/** @brief Set RMVF bit to clear the reset flags.
mbed_official	376:cb4d9db17537	1194	* The reset flags are: RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_PORRST,
mbed_official	376:cb4d9db17537	1195	* RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST.
mbed_official	376:cb4d9db17537	1196	*/
mbed_official	376:cb4d9db17537	1197	#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR \|= RCC_CSR_RMVF)
mbed_official	376:cb4d9db17537	1198
mbed_official	376:cb4d9db17537	1199	/** @brief Check RCC flag is set or not.
mbed_official	376:cb4d9db17537	1200	* @param __FLAG__: specifies the flag to check.
mbed_official	376:cb4d9db17537	1201	* This parameter can be one of the following values:
mbed_official	376:cb4d9db17537	1202	* @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready
mbed_official	376:cb4d9db17537	1203	* @arg RCC_FLAG_MSIRDY: MSI oscillator clock ready
mbed_official	376:cb4d9db17537	1204	* @arg RCC_FLAG_HSERDY: HSE oscillator clock ready
mbed_official	376:cb4d9db17537	1205	* @arg RCC_FLAG_PLLRDY: PLL clock ready
mbed_official	376:cb4d9db17537	1206	* @arg RCC_FLAG_LSECSS: LSE oscillator clock CSS detected
mbed_official	376:cb4d9db17537	1207	* @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
mbed_official	376:cb4d9db17537	1208	* @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
mbed_official	489:119543c9f674	1209	* @arg RCC_FLAG_FWRST: Firewall reset
mbed_official	376:cb4d9db17537	1210	* @arg RCC_FLAG_OBLRST: Option Byte Loader (OBL) reset
mbed_official	376:cb4d9db17537	1211	* @arg RCC_FLAG_PINRST: Pin reset
mbed_official	376:cb4d9db17537	1212	* @arg RCC_FLAG_PORRST: POR/PDR reset
mbed_official	376:cb4d9db17537	1213	* @arg RCC_FLAG_SFTRST: Software reset
mbed_official	376:cb4d9db17537	1214	* @arg RCC_FLAG_IWDGRST: Independent Watchdog reset
mbed_official	376:cb4d9db17537	1215	* @arg RCC_FLAG_WWDGRST: Window Watchdog reset
mbed_official	376:cb4d9db17537	1216	* @arg RCC_FLAG_LPWRRST: Low Power reset
mbed_official	376:cb4d9db17537	1217	* @retval The new state of __FLAG__ (TRUE or FALSE).
mbed_official	376:cb4d9db17537	1218	*/
mbed_official	376:cb4d9db17537	1219	#define RCC_FLAG_MASK ((uint8_t)0x1F)
mbed_official	376:cb4d9db17537	1220	#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5) == 1)? RCC->CR :((((__FLAG__) >> 5) == 2) ? RCC->CSR :((((__FLAG__) >> 5) == 3)? \
mbed_official	376:cb4d9db17537	1221	RCC->CRRCR :RCC->CIFR))) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK))) != 0 ) ? 1 : 0 )
mbed_official	376:cb4d9db17537	1222
mbed_official	376:cb4d9db17537	1223	/**
mbed_official	376:cb4d9db17537	1224	* @}
mbed_official	376:cb4d9db17537	1225	*/
mbed_official	376:cb4d9db17537	1226
mbed_official	376:cb4d9db17537	1227	/**
mbed_official	489:119543c9f674	1228	* @}
mbed_official	489:119543c9f674	1229	*/
mbed_official	376:cb4d9db17537	1230
mbed_official	376:cb4d9db17537	1231	/* Include RCC HAL Extension module */
mbed_official	384:ef87175507f1	1232	#include "stm32l0xx_hal_rcc_ex.h"
mbed_official	376:cb4d9db17537	1233
mbed_official	489:119543c9f674	1234	/** @defgroup RCC_Exported_Functions RCC Exported Functions
mbed_official	489:119543c9f674	1235	* @{
mbed_official	489:119543c9f674	1236	*/
mbed_official	489:119543c9f674	1237
mbed_official	489:119543c9f674	1238	/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions
mbed_official	489:119543c9f674	1239	* @{
mbed_official	489:119543c9f674	1240	*/
mbed_official	376:cb4d9db17537	1241	void HAL_RCC_DeInit(void);
mbed_official	376:cb4d9db17537	1242	HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
mbed_official	376:cb4d9db17537	1243	HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
mbed_official	489:119543c9f674	1244	/**
mbed_official	489:119543c9f674	1245	* @}
mbed_official	489:119543c9f674	1246	*/
mbed_official	376:cb4d9db17537	1247
mbed_official	489:119543c9f674	1248	/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions
mbed_official	489:119543c9f674	1249	* @{
mbed_official	489:119543c9f674	1250	*/
mbed_official	376:cb4d9db17537	1251	void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
mbed_official	376:cb4d9db17537	1252	void HAL_RCC_EnableCSS(void);
mbed_official	376:cb4d9db17537	1253	uint32_t HAL_RCC_GetSysClockFreq(void);
mbed_official	376:cb4d9db17537	1254	uint32_t HAL_RCC_GetHCLKFreq(void);
mbed_official	376:cb4d9db17537	1255	uint32_t HAL_RCC_GetPCLK1Freq(void);
mbed_official	376:cb4d9db17537	1256	uint32_t HAL_RCC_GetPCLK2Freq(void);
mbed_official	376:cb4d9db17537	1257	void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
mbed_official	376:cb4d9db17537	1258	void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef RCC_ClkInitStruct, uint32_t pFLatency);
mbed_official	376:cb4d9db17537	1259	/* CSS NMI IRQ handler */
mbed_official	376:cb4d9db17537	1260	void HAL_RCC_NMI_IRQHandler(void);
mbed_official	376:cb4d9db17537	1261
mbed_official	376:cb4d9db17537	1262	/* User Callbacks in non blocking mode (IT mode) */
mbed_official	489:119543c9f674	1263	void HAL_RCC_CSSCallback(void);
mbed_official	489:119543c9f674	1264	/**
mbed_official	489:119543c9f674	1265	* @}
mbed_official	489:119543c9f674	1266	*/
mbed_official	489:119543c9f674	1267
mbed_official	489:119543c9f674	1268	/**
mbed_official	489:119543c9f674	1269	* @}
mbed_official	489:119543c9f674	1270	*/
mbed_official	489:119543c9f674	1271
mbed_official	376:cb4d9db17537	1272	/**
mbed_official	376:cb4d9db17537	1273	* @}
mbed_official	376:cb4d9db17537	1274	*/
mbed_official	376:cb4d9db17537	1275
mbed_official	376:cb4d9db17537	1276	/**
mbed_official	376:cb4d9db17537	1277	* @}
mbed_official	376:cb4d9db17537	1278	*/
mbed_official	376:cb4d9db17537	1279
mbed_official	376:cb4d9db17537	1280	#ifdef __cplusplus
mbed_official	376:cb4d9db17537	1281	}
mbed_official	376:cb4d9db17537	1282	#endif
mbed_official	376:cb4d9db17537	1283
mbed_official	489:119543c9f674	1284	#endif /* __STM32l0xx_HAL_RCC_H */
mbed_official	376:cb4d9db17537	1285
mbed_official	376:cb4d9db17537	1286	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/
mbed_official	489:119543c9f674	1287