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targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_ll_fmc.h@579:53297373a894, 2015-07-01 (annotated)

Committer:: mbed_official
Date:: Wed Jul 01 09:45:11 2015 +0100
Revision:: 579:53297373a894
Parent:: 573:ad23fe03a082
Child:: 610:813dcc80987e

Synchronized with git revision d5b4d2ab9c47edb4dc5776e7177b0c2263459081

Full URL: https://github.com/mbedmicro/mbed/commit/d5b4d2ab9c47edb4dc5776e7177b0c2263459081/

Initial version of drivers for SAMR21

Who changed what in which revision?

User	Revision	Line number	New contents of line
mbed_official	573:ad23fe03a082	1	/**
mbed_official	573:ad23fe03a082	2	******************************************************************************
mbed_official	573:ad23fe03a082	3	* @file stm32f7xx_ll_fmc.h
mbed_official	573:ad23fe03a082	4	* @author MCD Application Team
mbed_official	573:ad23fe03a082	5	* @version V1.0.0
mbed_official	573:ad23fe03a082	6	* @date 12-May-2015
mbed_official	573:ad23fe03a082	7	* @brief Header file of FMC HAL module.
mbed_official	573:ad23fe03a082	8	******************************************************************************
mbed_official	573:ad23fe03a082	9	* @attention
mbed_official	573:ad23fe03a082	10	*
mbed_official	573:ad23fe03a082	11	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
mbed_official	573:ad23fe03a082	12	*
mbed_official	573:ad23fe03a082	13	* Redistribution and use in source and binary forms, with or without modification,
mbed_official	573:ad23fe03a082	14	* are permitted provided that the following conditions are met:
mbed_official	573:ad23fe03a082	15	* 1. Redistributions of source code must retain the above copyright notice,
mbed_official	573:ad23fe03a082	16	* this list of conditions and the following disclaimer.
mbed_official	573:ad23fe03a082	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official	573:ad23fe03a082	18	* this list of conditions and the following disclaimer in the documentation
mbed_official	573:ad23fe03a082	19	* and/or other materials provided with the distribution.
mbed_official	573:ad23fe03a082	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official	573:ad23fe03a082	21	* may be used to endorse or promote products derived from this software
mbed_official	573:ad23fe03a082	22	* without specific prior written permission.
mbed_official	573:ad23fe03a082	23	*
mbed_official	573:ad23fe03a082	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official	573:ad23fe03a082	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official	573:ad23fe03a082	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official	573:ad23fe03a082	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official	573:ad23fe03a082	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official	573:ad23fe03a082	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official	573:ad23fe03a082	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official	573:ad23fe03a082	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official	573:ad23fe03a082	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official	573:ad23fe03a082	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official	573:ad23fe03a082	34	*
mbed_official	573:ad23fe03a082	35	******************************************************************************
mbed_official	573:ad23fe03a082	36	*/
mbed_official	573:ad23fe03a082	37
mbed_official	573:ad23fe03a082	38	/* Define to prevent recursive inclusion -------------------------------------*/
mbed_official	573:ad23fe03a082	39	#ifndef __STM32F7xx_LL_FMC_H
mbed_official	573:ad23fe03a082	40	#define __STM32F7xx_LL_FMC_H
mbed_official	573:ad23fe03a082	41
mbed_official	573:ad23fe03a082	42	#ifdef __cplusplus
mbed_official	573:ad23fe03a082	43	extern "C" {
mbed_official	573:ad23fe03a082	44	#endif
mbed_official	573:ad23fe03a082	45
mbed_official	573:ad23fe03a082	46	/* Includes ------------------------------------------------------------------*/
mbed_official	573:ad23fe03a082	47	#include "stm32f7xx_hal_def.h"
mbed_official	573:ad23fe03a082	48
mbed_official	573:ad23fe03a082	49	/** @addtogroup STM32F7xx_HAL_Driver
mbed_official	573:ad23fe03a082	50	* @{
mbed_official	573:ad23fe03a082	51	*/
mbed_official	573:ad23fe03a082	52
mbed_official	573:ad23fe03a082	53	/** @addtogroup FMC_LL
mbed_official	573:ad23fe03a082	54	* @{
mbed_official	573:ad23fe03a082	55	*/
mbed_official	573:ad23fe03a082	56
mbed_official	573:ad23fe03a082	57	/** @addtogroup FMC_LL_Private_Macros
mbed_official	573:ad23fe03a082	58	* @{
mbed_official	573:ad23fe03a082	59	*/
mbed_official	573:ad23fe03a082	60	#define IS_FMC_NORSRAM_BANK(BANK) (((BANK) == FMC_NORSRAM_BANK1) \|\| \
mbed_official	573:ad23fe03a082	61	((BANK) == FMC_NORSRAM_BANK2) \|\| \
mbed_official	573:ad23fe03a082	62	((BANK) == FMC_NORSRAM_BANK3) \|\| \
mbed_official	573:ad23fe03a082	63	((BANK) == FMC_NORSRAM_BANK4))
mbed_official	573:ad23fe03a082	64
mbed_official	573:ad23fe03a082	65	#define IS_FMC_MUX(__MUX__) (((__MUX__) == FMC_DATA_ADDRESS_MUX_DISABLE) \|\| \
mbed_official	573:ad23fe03a082	66	((__MUX__) == FMC_DATA_ADDRESS_MUX_ENABLE))
mbed_official	573:ad23fe03a082	67
mbed_official	573:ad23fe03a082	68	#define IS_FMC_MEMORY(__MEMORY__) (((__MEMORY__) == FMC_MEMORY_TYPE_SRAM) \|\| \
mbed_official	573:ad23fe03a082	69	((__MEMORY__) == FMC_MEMORY_TYPE_PSRAM)\|\| \
mbed_official	573:ad23fe03a082	70	((__MEMORY__) == FMC_MEMORY_TYPE_NOR))
mbed_official	573:ad23fe03a082	71
mbed_official	573:ad23fe03a082	72	#define IS_FMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_8) \|\| \
mbed_official	573:ad23fe03a082	73	((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_16) \|\| \
mbed_official	573:ad23fe03a082	74	((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_32))
mbed_official	573:ad23fe03a082	75
mbed_official	573:ad23fe03a082	76	#define IS_FMC_ACCESS_MODE(__MODE__) (((__MODE__) == FMC_ACCESS_MODE_A) \|\| \
mbed_official	573:ad23fe03a082	77	((__MODE__) == FMC_ACCESS_MODE_B) \|\| \
mbed_official	573:ad23fe03a082	78	((__MODE__) == FMC_ACCESS_MODE_C) \|\| \
mbed_official	573:ad23fe03a082	79	((__MODE__) == FMC_ACCESS_MODE_D))
mbed_official	573:ad23fe03a082	80
mbed_official	573:ad23fe03a082	81	#define IS_FMC_NAND_BANK(BANK) ((BANK) == FMC_NAND_BANK3)
mbed_official	573:ad23fe03a082	82
mbed_official	573:ad23fe03a082	83	#define IS_FMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FMC_NAND_WAIT_FEATURE_DISABLE) \|\| \
mbed_official	573:ad23fe03a082	84	((FEATURE) == FMC_NAND_WAIT_FEATURE_ENABLE))
mbed_official	573:ad23fe03a082	85
mbed_official	573:ad23fe03a082	86	#define IS_FMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_NAND_MEM_BUS_WIDTH_8) \|\| \
mbed_official	573:ad23fe03a082	87	((WIDTH) == FMC_NAND_MEM_BUS_WIDTH_16))
mbed_official	573:ad23fe03a082	88
mbed_official	573:ad23fe03a082	89	#define IS_FMC_ECC_STATE(STATE) (((STATE) == FMC_NAND_ECC_DISABLE) \|\| \
mbed_official	573:ad23fe03a082	90	((STATE) == FMC_NAND_ECC_ENABLE))
mbed_official	573:ad23fe03a082	91
mbed_official	573:ad23fe03a082	92	#define IS_FMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FMC_NAND_ECC_PAGE_SIZE_256BYTE) \|\| \
mbed_official	573:ad23fe03a082	93	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_512BYTE) \|\| \
mbed_official	573:ad23fe03a082	94	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) \|\| \
mbed_official	573:ad23fe03a082	95	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) \|\| \
mbed_official	573:ad23fe03a082	96	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) \|\| \
mbed_official	573:ad23fe03a082	97	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE))
mbed_official	573:ad23fe03a082	98
mbed_official	573:ad23fe03a082	99	#define IS_FMC_SDMEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_8) \|\| \
mbed_official	573:ad23fe03a082	100	((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_16) \|\| \
mbed_official	573:ad23fe03a082	101	((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_32))
mbed_official	573:ad23fe03a082	102
mbed_official	573:ad23fe03a082	103	#define IS_FMC_WRITE_PROTECTION(__WRITE__) (((__WRITE__) == FMC_SDRAM_WRITE_PROTECTION_DISABLE) \|\| \
mbed_official	573:ad23fe03a082	104	((__WRITE__) == FMC_SDRAM_WRITE_PROTECTION_ENABLE))
mbed_official	573:ad23fe03a082	105
mbed_official	573:ad23fe03a082	106	#define IS_FMC_SDCLOCK_PERIOD(__PERIOD__) (((__PERIOD__) == FMC_SDRAM_CLOCK_DISABLE) \|\| \
mbed_official	573:ad23fe03a082	107	((__PERIOD__) == FMC_SDRAM_CLOCK_PERIOD_2) \|\| \
mbed_official	573:ad23fe03a082	108	((__PERIOD__) == FMC_SDRAM_CLOCK_PERIOD_3))
mbed_official	573:ad23fe03a082	109
mbed_official	573:ad23fe03a082	110	#define IS_FMC_READ_BURST(__RBURST__) (((__RBURST__) == FMC_SDRAM_RBURST_DISABLE) \|\| \
mbed_official	573:ad23fe03a082	111	((__RBURST__) == FMC_SDRAM_RBURST_ENABLE))
mbed_official	573:ad23fe03a082	112
mbed_official	573:ad23fe03a082	113	#define IS_FMC_READPIPE_DELAY(__DELAY__) (((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_0) \|\| \
mbed_official	573:ad23fe03a082	114	((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_1) \|\| \
mbed_official	573:ad23fe03a082	115	((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_2))
mbed_official	573:ad23fe03a082	116
mbed_official	573:ad23fe03a082	117	#define IS_FMC_COMMAND_MODE(__COMMAND__) (((__COMMAND__) == FMC_SDRAM_CMD_NORMAL_MODE) \|\| \
mbed_official	573:ad23fe03a082	118	((__COMMAND__) == FMC_SDRAM_CMD_CLK_ENABLE) \|\| \
mbed_official	573:ad23fe03a082	119	((__COMMAND__) == FMC_SDRAM_CMD_PALL) \|\| \
mbed_official	573:ad23fe03a082	120	((__COMMAND__) == FMC_SDRAM_CMD_AUTOREFRESH_MODE) \|\| \
mbed_official	573:ad23fe03a082	121	((__COMMAND__) == FMC_SDRAM_CMD_LOAD_MODE) \|\| \
mbed_official	573:ad23fe03a082	122	((__COMMAND__) == FMC_SDRAM_CMD_SELFREFRESH_MODE) \|\| \
mbed_official	573:ad23fe03a082	123	((__COMMAND__) == FMC_SDRAM_CMD_POWERDOWN_MODE))
mbed_official	573:ad23fe03a082	124
mbed_official	573:ad23fe03a082	125	#define IS_FMC_COMMAND_TARGET(__TARGET__) (((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK1) \|\| \
mbed_official	573:ad23fe03a082	126	((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK2) \|\| \
mbed_official	573:ad23fe03a082	127	((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK1_2))
mbed_official	573:ad23fe03a082	128
mbed_official	573:ad23fe03a082	129	/** @defgroup FMC_TCLR_Setup_Time FMC TCLR Setup Time
mbed_official	573:ad23fe03a082	130	* @{
mbed_official	573:ad23fe03a082	131	*/
mbed_official	573:ad23fe03a082	132	#define IS_FMC_TCLR_TIME(__TIME__) ((__TIME__) <= 255)
mbed_official	573:ad23fe03a082	133	/**
mbed_official	573:ad23fe03a082	134	* @}
mbed_official	573:ad23fe03a082	135	*/
mbed_official	573:ad23fe03a082	136
mbed_official	573:ad23fe03a082	137	/** @defgroup FMC_TAR_Setup_Time FMC TAR Setup Time
mbed_official	573:ad23fe03a082	138	* @{
mbed_official	573:ad23fe03a082	139	*/
mbed_official	573:ad23fe03a082	140	#define IS_FMC_TAR_TIME(TIME) ((TIME) <= 255)
mbed_official	573:ad23fe03a082	141	/**
mbed_official	573:ad23fe03a082	142	* @}
mbed_official	573:ad23fe03a082	143	*/
mbed_official	573:ad23fe03a082	144
mbed_official	573:ad23fe03a082	145	/** @defgroup FMC_Setup_Time FMC Setup Time
mbed_official	573:ad23fe03a082	146	* @{
mbed_official	573:ad23fe03a082	147	*/
mbed_official	573:ad23fe03a082	148	#define IS_FMC_SETUP_TIME(TIME) ((TIME) <= 255)
mbed_official	573:ad23fe03a082	149	/**
mbed_official	573:ad23fe03a082	150	* @}
mbed_official	573:ad23fe03a082	151	*/
mbed_official	573:ad23fe03a082	152
mbed_official	573:ad23fe03a082	153	/** @defgroup FMC_Wait_Setup_Time FMC Wait Setup Time
mbed_official	573:ad23fe03a082	154	* @{
mbed_official	573:ad23fe03a082	155	*/
mbed_official	573:ad23fe03a082	156	#define IS_FMC_WAIT_TIME(TIME) ((TIME) <= 255)
mbed_official	573:ad23fe03a082	157	/**
mbed_official	573:ad23fe03a082	158	* @}
mbed_official	573:ad23fe03a082	159	*/
mbed_official	573:ad23fe03a082	160
mbed_official	573:ad23fe03a082	161	/** @defgroup FMC_Hold_Setup_Time FMC Hold Setup Time
mbed_official	573:ad23fe03a082	162	* @{
mbed_official	573:ad23fe03a082	163	*/
mbed_official	573:ad23fe03a082	164	#define IS_FMC_HOLD_TIME(TIME) ((TIME) <= 255)
mbed_official	573:ad23fe03a082	165	/**
mbed_official	573:ad23fe03a082	166	* @}
mbed_official	573:ad23fe03a082	167	*/
mbed_official	573:ad23fe03a082	168
mbed_official	573:ad23fe03a082	169	/** @defgroup FMC_HiZ_Setup_Time FMC HiZ Setup Time
mbed_official	573:ad23fe03a082	170	* @{
mbed_official	573:ad23fe03a082	171	*/
mbed_official	573:ad23fe03a082	172	#define IS_FMC_HIZ_TIME(TIME) ((TIME) <= 255)
mbed_official	573:ad23fe03a082	173	/**
mbed_official	573:ad23fe03a082	174	* @}
mbed_official	573:ad23fe03a082	175	*/
mbed_official	573:ad23fe03a082	176
mbed_official	573:ad23fe03a082	177	#define IS_FMC_BURSTMODE(__STATE__) (((__STATE__) == FMC_BURST_ACCESS_MODE_DISABLE) \|\| \
mbed_official	573:ad23fe03a082	178	((__STATE__) == FMC_BURST_ACCESS_MODE_ENABLE))
mbed_official	573:ad23fe03a082	179
mbed_official	573:ad23fe03a082	180	#define IS_FMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_LOW) \|\| \
mbed_official	573:ad23fe03a082	181	((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_HIGH))
mbed_official	573:ad23fe03a082	182
mbed_official	573:ad23fe03a082	183	#define IS_FMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FMC_WAIT_TIMING_BEFORE_WS) \|\| \
mbed_official	573:ad23fe03a082	184	((__ACTIVE__) == FMC_WAIT_TIMING_DURING_WS))
mbed_official	573:ad23fe03a082	185
mbed_official	573:ad23fe03a082	186	#define IS_FMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FMC_WRITE_OPERATION_DISABLE) \|\| \
mbed_official	573:ad23fe03a082	187	((__OPERATION__) == FMC_WRITE_OPERATION_ENABLE))
mbed_official	573:ad23fe03a082	188
mbed_official	573:ad23fe03a082	189	#define IS_FMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FMC_WAIT_SIGNAL_DISABLE) \|\| \
mbed_official	573:ad23fe03a082	190	((__SIGNAL__) == FMC_WAIT_SIGNAL_ENABLE))
mbed_official	573:ad23fe03a082	191
mbed_official	573:ad23fe03a082	192	#define IS_FMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FMC_EXTENDED_MODE_DISABLE) \|\| \
mbed_official	573:ad23fe03a082	193	((__MODE__) == FMC_EXTENDED_MODE_ENABLE))
mbed_official	573:ad23fe03a082	194
mbed_official	573:ad23fe03a082	195	#define IS_FMC_ASYNWAIT(__STATE__) (((__STATE__) == FMC_ASYNCHRONOUS_WAIT_DISABLE) \|\| \
mbed_official	573:ad23fe03a082	196	((__STATE__) == FMC_ASYNCHRONOUS_WAIT_ENABLE))
mbed_official	573:ad23fe03a082	197
mbed_official	573:ad23fe03a082	198	/** @defgroup FMC_Data_Latency FMC Data Latency
mbed_official	573:ad23fe03a082	199	* @{
mbed_official	573:ad23fe03a082	200	*/
mbed_official	573:ad23fe03a082	201	#define IS_FMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1) && ((__LATENCY__) <= 17))
mbed_official	573:ad23fe03a082	202	/**
mbed_official	573:ad23fe03a082	203	* @}
mbed_official	573:ad23fe03a082	204	*/
mbed_official	573:ad23fe03a082	205
mbed_official	573:ad23fe03a082	206	#define IS_FMC_WRITE_BURST(__BURST__) (((__BURST__) == FMC_WRITE_BURST_DISABLE) \|\| \
mbed_official	573:ad23fe03a082	207	((__BURST__) == FMC_WRITE_BURST_ENABLE))
mbed_official	573:ad23fe03a082	208
mbed_official	573:ad23fe03a082	209	#define IS_FMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) \|\| \
mbed_official	573:ad23fe03a082	210	((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
mbed_official	573:ad23fe03a082	211
mbed_official	573:ad23fe03a082	212
mbed_official	573:ad23fe03a082	213	/** @defgroup FMC_Address_Setup_Time FMC Address Setup Time
mbed_official	573:ad23fe03a082	214	* @{
mbed_official	573:ad23fe03a082	215	*/
mbed_official	573:ad23fe03a082	216	#define IS_FMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15)
mbed_official	573:ad23fe03a082	217	/**
mbed_official	573:ad23fe03a082	218	* @}
mbed_official	573:ad23fe03a082	219	*/
mbed_official	573:ad23fe03a082	220
mbed_official	573:ad23fe03a082	221	/** @defgroup FMC_Address_Hold_Time FMC Address Hold Time
mbed_official	573:ad23fe03a082	222	* @{
mbed_official	573:ad23fe03a082	223	*/
mbed_official	573:ad23fe03a082	224	#define IS_FMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 15))
mbed_official	573:ad23fe03a082	225	/**
mbed_official	573:ad23fe03a082	226	* @}
mbed_official	573:ad23fe03a082	227	*/
mbed_official	573:ad23fe03a082	228
mbed_official	573:ad23fe03a082	229	/** @defgroup FMC_Data_Setup_Time FMC Data Setup Time
mbed_official	573:ad23fe03a082	230	* @{
mbed_official	573:ad23fe03a082	231	*/
mbed_official	573:ad23fe03a082	232	#define IS_FMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 255))
mbed_official	573:ad23fe03a082	233	/**
mbed_official	573:ad23fe03a082	234	* @}
mbed_official	573:ad23fe03a082	235	*/
mbed_official	573:ad23fe03a082	236
mbed_official	573:ad23fe03a082	237	/** @defgroup FMC_Bus_Turn_around_Duration FMC Bus Turn around Duration
mbed_official	573:ad23fe03a082	238	* @{
mbed_official	573:ad23fe03a082	239	*/
mbed_official	573:ad23fe03a082	240	#define IS_FMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15)
mbed_official	573:ad23fe03a082	241	/**
mbed_official	573:ad23fe03a082	242	* @}
mbed_official	573:ad23fe03a082	243	*/
mbed_official	573:ad23fe03a082	244
mbed_official	573:ad23fe03a082	245	/** @defgroup FMC_CLK_Division FMC CLK Division
mbed_official	573:ad23fe03a082	246	* @{
mbed_official	573:ad23fe03a082	247	*/
mbed_official	573:ad23fe03a082	248	#define IS_FMC_CLK_DIV(DIV) (((DIV) > 1) && ((DIV) <= 16))
mbed_official	573:ad23fe03a082	249	/**
mbed_official	573:ad23fe03a082	250	* @}
mbed_official	573:ad23fe03a082	251	*/
mbed_official	573:ad23fe03a082	252
mbed_official	573:ad23fe03a082	253	/** @defgroup FMC_SDRAM_LoadToActive_Delay FMC SDRAM LoadToActive Delay
mbed_official	573:ad23fe03a082	254	* @{
mbed_official	573:ad23fe03a082	255	*/
mbed_official	573:ad23fe03a082	256	#define IS_FMC_LOADTOACTIVE_DELAY(__DELAY__) (((__DELAY__) > 0) && ((__DELAY__) <= 16))
mbed_official	573:ad23fe03a082	257	/**
mbed_official	573:ad23fe03a082	258	* @}
mbed_official	573:ad23fe03a082	259	*/
mbed_official	573:ad23fe03a082	260
mbed_official	573:ad23fe03a082	261	/** @defgroup FMC_SDRAM_ExitSelfRefresh_Delay FMC SDRAM ExitSelfRefresh Delay
mbed_official	573:ad23fe03a082	262	* @{
mbed_official	573:ad23fe03a082	263	*/
mbed_official	573:ad23fe03a082	264	#define IS_FMC_EXITSELFREFRESH_DELAY(__DELAY__) (((__DELAY__) > 0) && ((__DELAY__) <= 16))
mbed_official	573:ad23fe03a082	265	/**
mbed_official	573:ad23fe03a082	266	* @}
mbed_official	573:ad23fe03a082	267	*/
mbed_official	573:ad23fe03a082	268
mbed_official	573:ad23fe03a082	269	/** @defgroup FMC_SDRAM_SelfRefresh_Time FMC SDRAM SelfRefresh Time
mbed_official	573:ad23fe03a082	270	* @{
mbed_official	573:ad23fe03a082	271	*/
mbed_official	573:ad23fe03a082	272	#define IS_FMC_SELFREFRESH_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 16))
mbed_official	573:ad23fe03a082	273	/**
mbed_official	573:ad23fe03a082	274	* @}
mbed_official	573:ad23fe03a082	275	*/
mbed_official	573:ad23fe03a082	276
mbed_official	573:ad23fe03a082	277	/** @defgroup FMC_SDRAM_RowCycle_Delay FMC SDRAM RowCycle Delay
mbed_official	573:ad23fe03a082	278	* @{
mbed_official	573:ad23fe03a082	279	*/
mbed_official	573:ad23fe03a082	280	#define IS_FMC_ROWCYCLE_DELAY(__DELAY__) (((__DELAY__) > 0) && ((__DELAY__) <= 16))
mbed_official	573:ad23fe03a082	281	/**
mbed_official	573:ad23fe03a082	282	* @}
mbed_official	573:ad23fe03a082	283	*/
mbed_official	573:ad23fe03a082	284
mbed_official	573:ad23fe03a082	285	/** @defgroup FMC_SDRAM_Write_Recovery_Time FMC SDRAM Write Recovery Time
mbed_official	573:ad23fe03a082	286	* @{
mbed_official	573:ad23fe03a082	287	*/
mbed_official	573:ad23fe03a082	288	#define IS_FMC_WRITE_RECOVERY_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 16))
mbed_official	573:ad23fe03a082	289	/**
mbed_official	573:ad23fe03a082	290	* @}
mbed_official	573:ad23fe03a082	291	*/
mbed_official	573:ad23fe03a082	292
mbed_official	573:ad23fe03a082	293	/** @defgroup FMC_SDRAM_RP_Delay FMC SDRAM RP Delay
mbed_official	573:ad23fe03a082	294	* @{
mbed_official	573:ad23fe03a082	295	*/
mbed_official	573:ad23fe03a082	296	#define IS_FMC_RP_DELAY(__DELAY__) (((__DELAY__) > 0) && ((__DELAY__) <= 16))
mbed_official	573:ad23fe03a082	297	/**
mbed_official	573:ad23fe03a082	298	* @}
mbed_official	573:ad23fe03a082	299	*/
mbed_official	573:ad23fe03a082	300
mbed_official	573:ad23fe03a082	301	/** @defgroup FMC_SDRAM_RCD_Delay FMC SDRAM RCD Delay
mbed_official	573:ad23fe03a082	302	* @{
mbed_official	573:ad23fe03a082	303	*/
mbed_official	573:ad23fe03a082	304	#define IS_FMC_RCD_DELAY(__DELAY__) (((__DELAY__) > 0) && ((__DELAY__) <= 16))
mbed_official	573:ad23fe03a082	305	/**
mbed_official	573:ad23fe03a082	306	* @}
mbed_official	573:ad23fe03a082	307	*/
mbed_official	573:ad23fe03a082	308
mbed_official	573:ad23fe03a082	309	/** @defgroup FMC_SDRAM_AutoRefresh_Number FMC SDRAM AutoRefresh Number
mbed_official	573:ad23fe03a082	310	* @{
mbed_official	573:ad23fe03a082	311	*/
mbed_official	573:ad23fe03a082	312	#define IS_FMC_AUTOREFRESH_NUMBER(__NUMBER__) (((__NUMBER__) > 0) && ((__NUMBER__) <= 16))
mbed_official	573:ad23fe03a082	313	/**
mbed_official	573:ad23fe03a082	314	* @}
mbed_official	573:ad23fe03a082	315	*/
mbed_official	573:ad23fe03a082	316
mbed_official	573:ad23fe03a082	317	/** @defgroup FMC_SDRAM_ModeRegister_Definition FMC SDRAM ModeRegister Definition
mbed_official	573:ad23fe03a082	318	* @{
mbed_official	573:ad23fe03a082	319	*/
mbed_official	573:ad23fe03a082	320	#define IS_FMC_MODE_REGISTER(__CONTENT__) ((__CONTENT__) <= 8191)
mbed_official	573:ad23fe03a082	321	/**
mbed_official	573:ad23fe03a082	322	* @}
mbed_official	573:ad23fe03a082	323	*/
mbed_official	573:ad23fe03a082	324
mbed_official	573:ad23fe03a082	325	/** @defgroup FMC_SDRAM_Refresh_rate FMC SDRAM Refresh rate
mbed_official	573:ad23fe03a082	326	* @{
mbed_official	573:ad23fe03a082	327	*/
mbed_official	573:ad23fe03a082	328	#define IS_FMC_REFRESH_RATE(__RATE__) ((__RATE__) <= 8191)
mbed_official	573:ad23fe03a082	329	/**
mbed_official	573:ad23fe03a082	330	* @}
mbed_official	573:ad23fe03a082	331	*/
mbed_official	573:ad23fe03a082	332
mbed_official	573:ad23fe03a082	333	/** @defgroup FMC_NORSRAM_Device_Instance FMC NORSRAM Device Instance
mbed_official	573:ad23fe03a082	334	* @{
mbed_official	573:ad23fe03a082	335	*/
mbed_official	573:ad23fe03a082	336	#define IS_FMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_DEVICE)
mbed_official	573:ad23fe03a082	337	/**
mbed_official	573:ad23fe03a082	338	* @}
mbed_official	573:ad23fe03a082	339	*/
mbed_official	573:ad23fe03a082	340
mbed_official	573:ad23fe03a082	341	/** @defgroup FMC_NORSRAM_EXTENDED_Device_Instance FMC NORSRAM EXTENDED Device Instance
mbed_official	573:ad23fe03a082	342	* @{
mbed_official	573:ad23fe03a082	343	*/
mbed_official	573:ad23fe03a082	344	#define IS_FMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_EXTENDED_DEVICE)
mbed_official	573:ad23fe03a082	345	/**
mbed_official	573:ad23fe03a082	346	* @}
mbed_official	573:ad23fe03a082	347	*/
mbed_official	573:ad23fe03a082	348
mbed_official	573:ad23fe03a082	349	/** @defgroup FMC_NAND_Device_Instance FMC NAND Device Instance
mbed_official	573:ad23fe03a082	350	* @{
mbed_official	573:ad23fe03a082	351	*/
mbed_official	573:ad23fe03a082	352	#define IS_FMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NAND_DEVICE)
mbed_official	573:ad23fe03a082	353	/**
mbed_official	573:ad23fe03a082	354	* @}
mbed_official	573:ad23fe03a082	355	*/
mbed_official	573:ad23fe03a082	356
mbed_official	573:ad23fe03a082	357	/** @defgroup FMC_SDRAM_Device_Instance FMC SDRAM Device Instance
mbed_official	573:ad23fe03a082	358	* @{
mbed_official	573:ad23fe03a082	359	*/
mbed_official	573:ad23fe03a082	360	#define IS_FMC_SDRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_SDRAM_DEVICE)
mbed_official	573:ad23fe03a082	361	/**
mbed_official	573:ad23fe03a082	362	* @}
mbed_official	573:ad23fe03a082	363	*/
mbed_official	573:ad23fe03a082	364
mbed_official	573:ad23fe03a082	365	#define IS_FMC_SDRAM_BANK(BANK) (((BANK) == FMC_SDRAM_BANK1) \|\| \
mbed_official	573:ad23fe03a082	366	((BANK) == FMC_SDRAM_BANK2))
mbed_official	573:ad23fe03a082	367
mbed_official	573:ad23fe03a082	368	#define IS_FMC_COLUMNBITS_NUMBER(COLUMN) (((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_8) \|\| \
mbed_official	573:ad23fe03a082	369	((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_9) \|\| \
mbed_official	573:ad23fe03a082	370	((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_10) \|\| \
mbed_official	573:ad23fe03a082	371	((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_11))
mbed_official	573:ad23fe03a082	372
mbed_official	573:ad23fe03a082	373	#define IS_FMC_ROWBITS_NUMBER(ROW) (((ROW) == FMC_SDRAM_ROW_BITS_NUM_11) \|\| \
mbed_official	573:ad23fe03a082	374	((ROW) == FMC_SDRAM_ROW_BITS_NUM_12) \|\| \
mbed_official	573:ad23fe03a082	375	((ROW) == FMC_SDRAM_ROW_BITS_NUM_13))
mbed_official	573:ad23fe03a082	376
mbed_official	573:ad23fe03a082	377	#define IS_FMC_INTERNALBANK_NUMBER(NUMBER) (((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_2) \|\| \
mbed_official	573:ad23fe03a082	378	((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_4))
mbed_official	573:ad23fe03a082	379
mbed_official	573:ad23fe03a082	380
mbed_official	573:ad23fe03a082	381	#define IS_FMC_CAS_LATENCY(LATENCY) (((LATENCY) == FMC_SDRAM_CAS_LATENCY_1) \|\| \
mbed_official	573:ad23fe03a082	382	((LATENCY) == FMC_SDRAM_CAS_LATENCY_2) \|\| \
mbed_official	573:ad23fe03a082	383	((LATENCY) == FMC_SDRAM_CAS_LATENCY_3))
mbed_official	573:ad23fe03a082	384
mbed_official	573:ad23fe03a082	385	#define IS_FMC_PAGESIZE(__SIZE__) (((__SIZE__) == FMC_PAGE_SIZE_NONE) \|\| \
mbed_official	573:ad23fe03a082	386	((__SIZE__) == FMC_PAGE_SIZE_128) \|\| \
mbed_official	573:ad23fe03a082	387	((__SIZE__) == FMC_PAGE_SIZE_256) \|\| \
mbed_official	573:ad23fe03a082	388	((__SIZE__) == FMC_PAGE_SIZE_1024))
mbed_official	573:ad23fe03a082	389
mbed_official	573:ad23fe03a082	390	#define IS_FMC_WRITE_FIFO(__FIFO__) (((__FIFO__) == FMC_WRITE_FIFO_DISABLE) \|\| \
mbed_official	573:ad23fe03a082	391	((__FIFO__) == FMC_WRITE_FIFO_ENABLE))
mbed_official	573:ad23fe03a082	392	/**
mbed_official	573:ad23fe03a082	393	* @}
mbed_official	573:ad23fe03a082	394	*/
mbed_official	573:ad23fe03a082	395
mbed_official	573:ad23fe03a082	396	/* Exported typedef ----------------------------------------------------------*/
mbed_official	573:ad23fe03a082	397	/** @defgroup FMC_Exported_typedef FMC Low Layer Exported Types
mbed_official	573:ad23fe03a082	398	* @{
mbed_official	573:ad23fe03a082	399	*/
mbed_official	573:ad23fe03a082	400	#define FMC_NORSRAM_TypeDef FMC_Bank1_TypeDef
mbed_official	573:ad23fe03a082	401	#define FMC_NORSRAM_EXTENDED_TypeDef FMC_Bank1E_TypeDef
mbed_official	573:ad23fe03a082	402	#define FMC_NAND_TypeDef FMC_Bank3_TypeDef
mbed_official	573:ad23fe03a082	403	#define FMC_SDRAM_TypeDef FMC_Bank5_6_TypeDef
mbed_official	573:ad23fe03a082	404
mbed_official	573:ad23fe03a082	405	#define FMC_NORSRAM_DEVICE FMC_Bank1
mbed_official	573:ad23fe03a082	406	#define FMC_NORSRAM_EXTENDED_DEVICE FMC_Bank1E
mbed_official	573:ad23fe03a082	407	#define FMC_NAND_DEVICE FMC_Bank3
mbed_official	573:ad23fe03a082	408	#define FMC_SDRAM_DEVICE FMC_Bank5_6
mbed_official	573:ad23fe03a082	409
mbed_official	573:ad23fe03a082	410	/**
mbed_official	573:ad23fe03a082	411	* @brief FMC NORSRAM Configuration Structure definition
mbed_official	573:ad23fe03a082	412	*/
mbed_official	573:ad23fe03a082	413	typedef struct
mbed_official	573:ad23fe03a082	414	{
mbed_official	573:ad23fe03a082	415	uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used.
mbed_official	573:ad23fe03a082	416	This parameter can be a value of @ref FMC_NORSRAM_Bank */
mbed_official	573:ad23fe03a082	417
mbed_official	573:ad23fe03a082	418	uint32_t DataAddressMux; /*!< Specifies whether the address and data values are
mbed_official	573:ad23fe03a082	419	multiplexed on the data bus or not.
mbed_official	573:ad23fe03a082	420	This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */
mbed_official	573:ad23fe03a082	421
mbed_official	573:ad23fe03a082	422	uint32_t MemoryType; /*!< Specifies the type of external memory attached to
mbed_official	573:ad23fe03a082	423	the corresponding memory device.
mbed_official	573:ad23fe03a082	424	This parameter can be a value of @ref FMC_Memory_Type */
mbed_official	573:ad23fe03a082	425
mbed_official	573:ad23fe03a082	426	uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
mbed_official	573:ad23fe03a082	427	This parameter can be a value of @ref FMC_NORSRAM_Data_Width */
mbed_official	573:ad23fe03a082	428
mbed_official	573:ad23fe03a082	429	uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
mbed_official	573:ad23fe03a082	430	valid only with synchronous burst Flash memories.
mbed_official	573:ad23fe03a082	431	This parameter can be a value of @ref FMC_Burst_Access_Mode */
mbed_official	573:ad23fe03a082	432
mbed_official	573:ad23fe03a082	433	uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
mbed_official	573:ad23fe03a082	434	the Flash memory in burst mode.
mbed_official	573:ad23fe03a082	435	This parameter can be a value of @ref FMC_Wait_Signal_Polarity */
mbed_official	573:ad23fe03a082	436
mbed_official	573:ad23fe03a082	437	uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
mbed_official	573:ad23fe03a082	438	clock cycle before the wait state or during the wait state,
mbed_official	573:ad23fe03a082	439	valid only when accessing memories in burst mode.
mbed_official	573:ad23fe03a082	440	This parameter can be a value of @ref FMC_Wait_Timing */
mbed_official	573:ad23fe03a082	441
mbed_official	573:ad23fe03a082	442	uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FMC.
mbed_official	573:ad23fe03a082	443	This parameter can be a value of @ref FMC_Write_Operation */
mbed_official	573:ad23fe03a082	444
mbed_official	573:ad23fe03a082	445	uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait
mbed_official	573:ad23fe03a082	446	signal, valid for Flash memory access in burst mode.
mbed_official	573:ad23fe03a082	447	This parameter can be a value of @ref FMC_Wait_Signal */
mbed_official	573:ad23fe03a082	448
mbed_official	573:ad23fe03a082	449	uint32_t ExtendedMode; /*!< Enables or disables the extended mode.
mbed_official	573:ad23fe03a082	450	This parameter can be a value of @ref FMC_Extended_Mode */
mbed_official	573:ad23fe03a082	451
mbed_official	573:ad23fe03a082	452	uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
mbed_official	573:ad23fe03a082	453	valid only with asynchronous Flash memories.
mbed_official	573:ad23fe03a082	454	This parameter can be a value of @ref FMC_AsynchronousWait */
mbed_official	573:ad23fe03a082	455
mbed_official	573:ad23fe03a082	456	uint32_t WriteBurst; /*!< Enables or disables the write burst operation.
mbed_official	573:ad23fe03a082	457	This parameter can be a value of @ref FMC_Write_Burst */
mbed_official	573:ad23fe03a082	458
mbed_official	573:ad23fe03a082	459	uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices.
mbed_official	573:ad23fe03a082	460	This parameter is only enabled through the FMC_BCR1 register, and don't care
mbed_official	573:ad23fe03a082	461	through FMC_BCR2..4 registers.
mbed_official	573:ad23fe03a082	462	This parameter can be a value of @ref FMC_Continous_Clock */
mbed_official	573:ad23fe03a082	463
mbed_official	573:ad23fe03a082	464	uint32_t WriteFifo; /*!< Enables or disables the write FIFO used by the FMC controller.
mbed_official	573:ad23fe03a082	465	This parameter is only enabled through the FMC_BCR1 register, and don't care
mbed_official	573:ad23fe03a082	466	through FMC_BCR2..4 registers.
mbed_official	573:ad23fe03a082	467	This parameter can be a value of @ref FMC_Write_FIFO */
mbed_official	573:ad23fe03a082	468
mbed_official	573:ad23fe03a082	469	uint32_t PageSize; /*!< Specifies the memory page size.
mbed_official	573:ad23fe03a082	470	This parameter can be a value of @ref FMC_Page_Size */
mbed_official	573:ad23fe03a082	471
mbed_official	573:ad23fe03a082	472	}FMC_NORSRAM_InitTypeDef;
mbed_official	573:ad23fe03a082	473
mbed_official	573:ad23fe03a082	474	/**
mbed_official	573:ad23fe03a082	475	* @brief FMC NORSRAM Timing parameters structure definition
mbed_official	573:ad23fe03a082	476	*/
mbed_official	573:ad23fe03a082	477	typedef struct
mbed_official	573:ad23fe03a082	478	{
mbed_official	573:ad23fe03a082	479	uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
mbed_official	573:ad23fe03a082	480	the duration of the address setup time.
mbed_official	573:ad23fe03a082	481	This parameter can be a value between Min_Data = 0 and Max_Data = 15.
mbed_official	573:ad23fe03a082	482	@note This parameter is not used with synchronous NOR Flash memories. */
mbed_official	573:ad23fe03a082	483
mbed_official	573:ad23fe03a082	484	uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
mbed_official	573:ad23fe03a082	485	the duration of the address hold time.
mbed_official	573:ad23fe03a082	486	This parameter can be a value between Min_Data = 1 and Max_Data = 15.
mbed_official	573:ad23fe03a082	487	@note This parameter is not used with synchronous NOR Flash memories. */
mbed_official	573:ad23fe03a082	488
mbed_official	573:ad23fe03a082	489	uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure
mbed_official	573:ad23fe03a082	490	the duration of the data setup time.
mbed_official	573:ad23fe03a082	491	This parameter can be a value between Min_Data = 1 and Max_Data = 255.
mbed_official	573:ad23fe03a082	492	@note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
mbed_official	573:ad23fe03a082	493	NOR Flash memories. */
mbed_official	573:ad23fe03a082	494
mbed_official	573:ad23fe03a082	495	uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
mbed_official	573:ad23fe03a082	496	the duration of the bus turnaround.
mbed_official	573:ad23fe03a082	497	This parameter can be a value between Min_Data = 0 and Max_Data = 15.
mbed_official	573:ad23fe03a082	498	@note This parameter is only used for multiplexed NOR Flash memories. */
mbed_official	573:ad23fe03a082	499
mbed_official	573:ad23fe03a082	500	uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of
mbed_official	573:ad23fe03a082	501	HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16.
mbed_official	573:ad23fe03a082	502	@note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
mbed_official	573:ad23fe03a082	503	accesses. */
mbed_official	573:ad23fe03a082	504
mbed_official	573:ad23fe03a082	505	uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue
mbed_official	573:ad23fe03a082	506	to the memory before getting the first data.
mbed_official	573:ad23fe03a082	507	The parameter value depends on the memory type as shown below:
mbed_official	573:ad23fe03a082	508	- It must be set to 0 in case of a CRAM
mbed_official	573:ad23fe03a082	509	- It is don't care in asynchronous NOR, SRAM or ROM accesses
mbed_official	573:ad23fe03a082	510	- It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories
mbed_official	573:ad23fe03a082	511	with synchronous burst mode enable */
mbed_official	573:ad23fe03a082	512
mbed_official	573:ad23fe03a082	513	uint32_t AccessMode; /*!< Specifies the asynchronous access mode.
mbed_official	573:ad23fe03a082	514	This parameter can be a value of @ref FMC_Access_Mode */
mbed_official	573:ad23fe03a082	515	}FMC_NORSRAM_TimingTypeDef;
mbed_official	573:ad23fe03a082	516
mbed_official	573:ad23fe03a082	517	/**
mbed_official	573:ad23fe03a082	518	* @brief FMC NAND Configuration Structure definition
mbed_official	573:ad23fe03a082	519	*/
mbed_official	573:ad23fe03a082	520	typedef struct
mbed_official	573:ad23fe03a082	521	{
mbed_official	573:ad23fe03a082	522	uint32_t NandBank; /*!< Specifies the NAND memory device that will be used.
mbed_official	573:ad23fe03a082	523	This parameter can be a value of @ref FMC_NAND_Bank */
mbed_official	573:ad23fe03a082	524
mbed_official	573:ad23fe03a082	525	uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device.
mbed_official	573:ad23fe03a082	526	This parameter can be any value of @ref FMC_Wait_feature */
mbed_official	573:ad23fe03a082	527
mbed_official	573:ad23fe03a082	528	uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
mbed_official	573:ad23fe03a082	529	This parameter can be any value of @ref FMC_NAND_Data_Width */
mbed_official	573:ad23fe03a082	530
mbed_official	573:ad23fe03a082	531	uint32_t EccComputation; /*!< Enables or disables the ECC computation.
mbed_official	573:ad23fe03a082	532	This parameter can be any value of @ref FMC_ECC */
mbed_official	573:ad23fe03a082	533
mbed_official	573:ad23fe03a082	534	uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC.
mbed_official	573:ad23fe03a082	535	This parameter can be any value of @ref FMC_ECC_Page_Size */
mbed_official	573:ad23fe03a082	536
mbed_official	573:ad23fe03a082	537	uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
mbed_official	573:ad23fe03a082	538	delay between CLE low and RE low.
mbed_official	573:ad23fe03a082	539	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
mbed_official	573:ad23fe03a082	540
mbed_official	573:ad23fe03a082	541	uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
mbed_official	573:ad23fe03a082	542	delay between ALE low and RE low.
mbed_official	573:ad23fe03a082	543	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
mbed_official	573:ad23fe03a082	544	}FMC_NAND_InitTypeDef;
mbed_official	573:ad23fe03a082	545
mbed_official	573:ad23fe03a082	546	/**
mbed_official	573:ad23fe03a082	547	* @brief FMC NAND Timing parameters structure definition
mbed_official	573:ad23fe03a082	548	*/
mbed_official	573:ad23fe03a082	549	typedef struct
mbed_official	573:ad23fe03a082	550	{
mbed_official	573:ad23fe03a082	551	uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before
mbed_official	573:ad23fe03a082	552	the command assertion for NAND-Flash read or write access
mbed_official	573:ad23fe03a082	553	to common/Attribute or I/O memory space (depending on
mbed_official	573:ad23fe03a082	554	the memory space timing to be configured).
mbed_official	573:ad23fe03a082	555	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
mbed_official	573:ad23fe03a082	556
mbed_official	573:ad23fe03a082	557	uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
mbed_official	573:ad23fe03a082	558	command for NAND-Flash read or write access to
mbed_official	573:ad23fe03a082	559	common/Attribute or I/O memory space (depending on the
mbed_official	573:ad23fe03a082	560	memory space timing to be configured).
mbed_official	573:ad23fe03a082	561	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
mbed_official	573:ad23fe03a082	562
mbed_official	573:ad23fe03a082	563	uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
mbed_official	573:ad23fe03a082	564	(and data for write access) after the command de-assertion
mbed_official	573:ad23fe03a082	565	for NAND-Flash read or write access to common/Attribute
mbed_official	573:ad23fe03a082	566	or I/O memory space (depending on the memory space timing
mbed_official	573:ad23fe03a082	567	to be configured).
mbed_official	573:ad23fe03a082	568	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
mbed_official	573:ad23fe03a082	569
mbed_official	573:ad23fe03a082	570	uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
mbed_official	573:ad23fe03a082	571	data bus is kept in HiZ after the start of a NAND-Flash
mbed_official	573:ad23fe03a082	572	write access to common/Attribute or I/O memory space (depending
mbed_official	573:ad23fe03a082	573	on the memory space timing to be configured).
mbed_official	573:ad23fe03a082	574	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
mbed_official	573:ad23fe03a082	575	}FMC_NAND_PCC_TimingTypeDef;
mbed_official	573:ad23fe03a082	576
mbed_official	573:ad23fe03a082	577	/**
mbed_official	573:ad23fe03a082	578	* @brief FMC SDRAM Configuration Structure definition
mbed_official	573:ad23fe03a082	579	*/
mbed_official	573:ad23fe03a082	580	typedef struct
mbed_official	573:ad23fe03a082	581	{
mbed_official	573:ad23fe03a082	582	uint32_t SDBank; /*!< Specifies the SDRAM memory device that will be used.
mbed_official	573:ad23fe03a082	583	This parameter can be a value of @ref FMC_SDRAM_Bank */
mbed_official	573:ad23fe03a082	584
mbed_official	573:ad23fe03a082	585	uint32_t ColumnBitsNumber; /*!< Defines the number of bits of column address.
mbed_official	573:ad23fe03a082	586	This parameter can be a value of @ref FMC_SDRAM_Column_Bits_number. */
mbed_official	573:ad23fe03a082	587
mbed_official	573:ad23fe03a082	588	uint32_t RowBitsNumber; /*!< Defines the number of bits of column address.
mbed_official	573:ad23fe03a082	589	This parameter can be a value of @ref FMC_SDRAM_Row_Bits_number. */
mbed_official	573:ad23fe03a082	590
mbed_official	573:ad23fe03a082	591	uint32_t MemoryDataWidth; /*!< Defines the memory device width.
mbed_official	573:ad23fe03a082	592	This parameter can be a value of @ref FMC_SDRAM_Memory_Bus_Width. */
mbed_official	573:ad23fe03a082	593
mbed_official	573:ad23fe03a082	594	uint32_t InternalBankNumber; /*!< Defines the number of the device's internal banks.
mbed_official	573:ad23fe03a082	595	This parameter can be of @ref FMC_SDRAM_Internal_Banks_Number. */
mbed_official	573:ad23fe03a082	596
mbed_official	573:ad23fe03a082	597	uint32_t CASLatency; /*!< Defines the SDRAM CAS latency in number of memory clock cycles.
mbed_official	573:ad23fe03a082	598	This parameter can be a value of @ref FMC_SDRAM_CAS_Latency. */
mbed_official	573:ad23fe03a082	599
mbed_official	573:ad23fe03a082	600	uint32_t WriteProtection; /*!< Enables the SDRAM device to be accessed in write mode.
mbed_official	573:ad23fe03a082	601	This parameter can be a value of @ref FMC_SDRAM_Write_Protection. */
mbed_official	573:ad23fe03a082	602
mbed_official	573:ad23fe03a082	603	uint32_t SDClockPeriod; /*!< Define the SDRAM Clock Period for both SDRAM devices and they allow
mbed_official	573:ad23fe03a082	604	to disable the clock before changing frequency.
mbed_official	573:ad23fe03a082	605	This parameter can be a value of @ref FMC_SDRAM_Clock_Period. */
mbed_official	573:ad23fe03a082	606
mbed_official	573:ad23fe03a082	607	uint32_t ReadBurst; /*!< This bit enable the SDRAM controller to anticipate the next read
mbed_official	573:ad23fe03a082	608	commands during the CAS latency and stores data in the Read FIFO.
mbed_official	573:ad23fe03a082	609	This parameter can be a value of @ref FMC_SDRAM_Read_Burst. */
mbed_official	573:ad23fe03a082	610
mbed_official	573:ad23fe03a082	611	uint32_t ReadPipeDelay; /*!< Define the delay in system clock cycles on read data path.
mbed_official	573:ad23fe03a082	612	This parameter can be a value of @ref FMC_SDRAM_Read_Pipe_Delay. */
mbed_official	573:ad23fe03a082	613	}FMC_SDRAM_InitTypeDef;
mbed_official	573:ad23fe03a082	614
mbed_official	573:ad23fe03a082	615	/**
mbed_official	573:ad23fe03a082	616	* @brief FMC SDRAM Timing parameters structure definition
mbed_official	573:ad23fe03a082	617	*/
mbed_official	573:ad23fe03a082	618	typedef struct
mbed_official	573:ad23fe03a082	619	{
mbed_official	573:ad23fe03a082	620	uint32_t LoadToActiveDelay; /*!< Defines the delay between a Load Mode Register command and
mbed_official	573:ad23fe03a082	621	an active or Refresh command in number of memory clock cycles.
mbed_official	573:ad23fe03a082	622	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
mbed_official	573:ad23fe03a082	623
mbed_official	573:ad23fe03a082	624	uint32_t ExitSelfRefreshDelay; /*!< Defines the delay from releasing the self refresh command to
mbed_official	573:ad23fe03a082	625	issuing the Activate command in number of memory clock cycles.
mbed_official	573:ad23fe03a082	626	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
mbed_official	573:ad23fe03a082	627
mbed_official	573:ad23fe03a082	628	uint32_t SelfRefreshTime; /*!< Defines the minimum Self Refresh period in number of memory clock
mbed_official	573:ad23fe03a082	629	cycles.
mbed_official	573:ad23fe03a082	630	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
mbed_official	573:ad23fe03a082	631
mbed_official	573:ad23fe03a082	632	uint32_t RowCycleDelay; /*!< Defines the delay between the Refresh command and the Activate command
mbed_official	573:ad23fe03a082	633	and the delay between two consecutive Refresh commands in number of
mbed_official	573:ad23fe03a082	634	memory clock cycles.
mbed_official	573:ad23fe03a082	635	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
mbed_official	573:ad23fe03a082	636
mbed_official	573:ad23fe03a082	637	uint32_t WriteRecoveryTime; /*!< Defines the Write recovery Time in number of memory clock cycles.
mbed_official	573:ad23fe03a082	638	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
mbed_official	573:ad23fe03a082	639
mbed_official	573:ad23fe03a082	640	uint32_t RPDelay; /*!< Defines the delay between a Precharge Command and an other command
mbed_official	573:ad23fe03a082	641	in number of memory clock cycles.
mbed_official	573:ad23fe03a082	642	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
mbed_official	573:ad23fe03a082	643
mbed_official	573:ad23fe03a082	644	uint32_t RCDDelay; /*!< Defines the delay between the Activate Command and a Read/Write
mbed_official	573:ad23fe03a082	645	command in number of memory clock cycles.
mbed_official	573:ad23fe03a082	646	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
mbed_official	573:ad23fe03a082	647	}FMC_SDRAM_TimingTypeDef;
mbed_official	573:ad23fe03a082	648
mbed_official	573:ad23fe03a082	649	/**
mbed_official	573:ad23fe03a082	650	* @brief SDRAM command parameters structure definition
mbed_official	573:ad23fe03a082	651	*/
mbed_official	573:ad23fe03a082	652	typedef struct
mbed_official	573:ad23fe03a082	653	{
mbed_official	573:ad23fe03a082	654	uint32_t CommandMode; /*!< Defines the command issued to the SDRAM device.
mbed_official	573:ad23fe03a082	655	This parameter can be a value of @ref FMC_SDRAM_Command_Mode. */
mbed_official	573:ad23fe03a082	656
mbed_official	573:ad23fe03a082	657	uint32_t CommandTarget; /*!< Defines which device (1 or 2) the command will be issued to.
mbed_official	573:ad23fe03a082	658	This parameter can be a value of @ref FMC_SDRAM_Command_Target. */
mbed_official	573:ad23fe03a082	659
mbed_official	573:ad23fe03a082	660	uint32_t AutoRefreshNumber; /*!< Defines the number of consecutive auto refresh command issued
mbed_official	573:ad23fe03a082	661	in auto refresh mode.
mbed_official	573:ad23fe03a082	662	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
mbed_official	573:ad23fe03a082	663	uint32_t ModeRegisterDefinition; /!< Defines the SDRAM Mode register content /
mbed_official	573:ad23fe03a082	664	}FMC_SDRAM_CommandTypeDef;
mbed_official	573:ad23fe03a082	665	/**
mbed_official	573:ad23fe03a082	666	* @}
mbed_official	573:ad23fe03a082	667	*/
mbed_official	573:ad23fe03a082	668
mbed_official	573:ad23fe03a082	669	/* Exported constants --------------------------------------------------------*/
mbed_official	573:ad23fe03a082	670	/** @addtogroup FMC_LL_Exported_Constants FMC Low Layer Exported Constants
mbed_official	573:ad23fe03a082	671	* @{
mbed_official	573:ad23fe03a082	672	*/
mbed_official	573:ad23fe03a082	673
mbed_official	573:ad23fe03a082	674	/** @defgroup FMC_LL_NOR_SRAM_Controller FMC NOR/SRAM Controller
mbed_official	573:ad23fe03a082	675	* @{
mbed_official	573:ad23fe03a082	676	*/
mbed_official	573:ad23fe03a082	677
mbed_official	573:ad23fe03a082	678	/** @defgroup FMC_NORSRAM_Bank FMC NOR/SRAM Bank
mbed_official	573:ad23fe03a082	679	* @{
mbed_official	573:ad23fe03a082	680	*/
mbed_official	573:ad23fe03a082	681	#define FMC_NORSRAM_BANK1 ((uint32_t)0x00000000)
mbed_official	573:ad23fe03a082	682	#define FMC_NORSRAM_BANK2 ((uint32_t)0x00000002)
mbed_official	573:ad23fe03a082	683	#define FMC_NORSRAM_BANK3 ((uint32_t)0x00000004)
mbed_official	573:ad23fe03a082	684	#define FMC_NORSRAM_BANK4 ((uint32_t)0x00000006)
mbed_official	573:ad23fe03a082	685	/**
mbed_official	573:ad23fe03a082	686	* @}
mbed_official	573:ad23fe03a082	687	*/
mbed_official	573:ad23fe03a082	688
mbed_official	573:ad23fe03a082	689	/** @defgroup FMC_Data_Address_Bus_Multiplexing FMC Data Address Bus Multiplexing
mbed_official	573:ad23fe03a082	690	* @{
mbed_official	573:ad23fe03a082	691	*/
mbed_official	573:ad23fe03a082	692	#define FMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000)
mbed_official	573:ad23fe03a082	693	#define FMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)0x00000002)
mbed_official	573:ad23fe03a082	694	/**
mbed_official	573:ad23fe03a082	695	* @}
mbed_official	573:ad23fe03a082	696	*/
mbed_official	573:ad23fe03a082	697
mbed_official	573:ad23fe03a082	698	/** @defgroup FMC_Memory_Type FMC Memory Type
mbed_official	573:ad23fe03a082	699	* @{
mbed_official	573:ad23fe03a082	700	*/
mbed_official	573:ad23fe03a082	701	#define FMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000)
mbed_official	573:ad23fe03a082	702	#define FMC_MEMORY_TYPE_PSRAM ((uint32_t)0x00000004)
mbed_official	573:ad23fe03a082	703	#define FMC_MEMORY_TYPE_NOR ((uint32_t)0x00000008)
mbed_official	573:ad23fe03a082	704	/**
mbed_official	573:ad23fe03a082	705	* @}
mbed_official	573:ad23fe03a082	706	*/
mbed_official	573:ad23fe03a082	707
mbed_official	573:ad23fe03a082	708	/** @defgroup FMC_NORSRAM_Data_Width FMC NORSRAM Data Width
mbed_official	573:ad23fe03a082	709	* @{
mbed_official	573:ad23fe03a082	710	*/
mbed_official	573:ad23fe03a082	711	#define FMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
mbed_official	573:ad23fe03a082	712	#define FMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
mbed_official	573:ad23fe03a082	713	#define FMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020)
mbed_official	573:ad23fe03a082	714	/**
mbed_official	573:ad23fe03a082	715	* @}
mbed_official	573:ad23fe03a082	716	*/
mbed_official	573:ad23fe03a082	717
mbed_official	573:ad23fe03a082	718	/** @defgroup FMC_NORSRAM_Flash_Access FMC NOR/SRAM Flash Access
mbed_official	573:ad23fe03a082	719	* @{
mbed_official	573:ad23fe03a082	720	*/
mbed_official	573:ad23fe03a082	721	#define FMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)0x00000040)
mbed_official	573:ad23fe03a082	722	#define FMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000)
mbed_official	573:ad23fe03a082	723	/**
mbed_official	573:ad23fe03a082	724	* @}
mbed_official	573:ad23fe03a082	725	*/
mbed_official	573:ad23fe03a082	726
mbed_official	573:ad23fe03a082	727	/** @defgroup FMC_Burst_Access_Mode FMC Burst Access Mode
mbed_official	573:ad23fe03a082	728	* @{
mbed_official	573:ad23fe03a082	729	*/
mbed_official	573:ad23fe03a082	730	#define FMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000)
mbed_official	573:ad23fe03a082	731	#define FMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)0x00000100)
mbed_official	573:ad23fe03a082	732	/**
mbed_official	573:ad23fe03a082	733	* @}
mbed_official	573:ad23fe03a082	734	*/
mbed_official	573:ad23fe03a082	735
mbed_official	573:ad23fe03a082	736	/** @defgroup FMC_Wait_Signal_Polarity FMC Wait Signal Polarity
mbed_official	573:ad23fe03a082	737	* @{
mbed_official	573:ad23fe03a082	738	*/
mbed_official	573:ad23fe03a082	739	#define FMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000)
mbed_official	573:ad23fe03a082	740	#define FMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)0x00000200)
mbed_official	573:ad23fe03a082	741	/**
mbed_official	573:ad23fe03a082	742	* @}
mbed_official	573:ad23fe03a082	743	*/
mbed_official	573:ad23fe03a082	744
mbed_official	573:ad23fe03a082	745	/** @defgroup FMC_Wait_Timing FMC Wait Timing
mbed_official	573:ad23fe03a082	746	* @{
mbed_official	573:ad23fe03a082	747	*/
mbed_official	573:ad23fe03a082	748	#define FMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000)
mbed_official	573:ad23fe03a082	749	#define FMC_WAIT_TIMING_DURING_WS ((uint32_t)0x00000800)
mbed_official	573:ad23fe03a082	750	/**
mbed_official	573:ad23fe03a082	751	* @}
mbed_official	573:ad23fe03a082	752	*/
mbed_official	573:ad23fe03a082	753
mbed_official	573:ad23fe03a082	754	/** @defgroup FMC_Write_Operation FMC Write Operation
mbed_official	573:ad23fe03a082	755	* @{
mbed_official	573:ad23fe03a082	756	*/
mbed_official	573:ad23fe03a082	757	#define FMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000)
mbed_official	573:ad23fe03a082	758	#define FMC_WRITE_OPERATION_ENABLE ((uint32_t)0x00001000)
mbed_official	573:ad23fe03a082	759	/**
mbed_official	573:ad23fe03a082	760	* @}
mbed_official	573:ad23fe03a082	761	*/
mbed_official	573:ad23fe03a082	762
mbed_official	573:ad23fe03a082	763	/** @defgroup FMC_Wait_Signal FMC Wait Signal
mbed_official	573:ad23fe03a082	764	* @{
mbed_official	573:ad23fe03a082	765	*/
mbed_official	573:ad23fe03a082	766	#define FMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000)
mbed_official	573:ad23fe03a082	767	#define FMC_WAIT_SIGNAL_ENABLE ((uint32_t)0x00002000)
mbed_official	573:ad23fe03a082	768	/**
mbed_official	573:ad23fe03a082	769	* @}
mbed_official	573:ad23fe03a082	770	*/
mbed_official	573:ad23fe03a082	771
mbed_official	573:ad23fe03a082	772	/** @defgroup FMC_Extended_Mode FMC Extended Mode
mbed_official	573:ad23fe03a082	773	* @{
mbed_official	573:ad23fe03a082	774	*/
mbed_official	573:ad23fe03a082	775	#define FMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000)
mbed_official	573:ad23fe03a082	776	#define FMC_EXTENDED_MODE_ENABLE ((uint32_t)0x00004000)
mbed_official	573:ad23fe03a082	777	/**
mbed_official	573:ad23fe03a082	778	* @}
mbed_official	573:ad23fe03a082	779	*/
mbed_official	573:ad23fe03a082	780
mbed_official	573:ad23fe03a082	781	/** @defgroup FMC_AsynchronousWait FMC Asynchronous Wait
mbed_official	573:ad23fe03a082	782	* @{
mbed_official	573:ad23fe03a082	783	*/
mbed_official	573:ad23fe03a082	784	#define FMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000)
mbed_official	573:ad23fe03a082	785	#define FMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)0x00008000)
mbed_official	573:ad23fe03a082	786	/**
mbed_official	573:ad23fe03a082	787	* @}
mbed_official	573:ad23fe03a082	788	*/
mbed_official	573:ad23fe03a082	789
mbed_official	573:ad23fe03a082	790	/** @defgroup FMC_Page_Size FMC Page Size
mbed_official	573:ad23fe03a082	791	* @{
mbed_official	573:ad23fe03a082	792	*/
mbed_official	573:ad23fe03a082	793	#define FMC_PAGE_SIZE_NONE ((uint32_t)0x00000000)
mbed_official	573:ad23fe03a082	794	#define FMC_PAGE_SIZE_128 ((uint32_t)FMC_BCR1_CPSIZE_0)
mbed_official	573:ad23fe03a082	795	#define FMC_PAGE_SIZE_256 ((uint32_t)FMC_BCR1_CPSIZE_1)
mbed_official	573:ad23fe03a082	796	#define FMC_PAGE_SIZE_1024 ((uint32_t)FMC_BCR1_CPSIZE_2)
mbed_official	573:ad23fe03a082	797	/**
mbed_official	573:ad23fe03a082	798	* @}
mbed_official	573:ad23fe03a082	799	*/
mbed_official	573:ad23fe03a082	800
mbed_official	573:ad23fe03a082	801	/** @defgroup FMC_Write_Burst FMC Write Burst
mbed_official	573:ad23fe03a082	802	* @{
mbed_official	573:ad23fe03a082	803	*/
mbed_official	573:ad23fe03a082	804	#define FMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000)
mbed_official	573:ad23fe03a082	805	#define FMC_WRITE_BURST_ENABLE ((uint32_t)0x00080000)
mbed_official	573:ad23fe03a082	806	/**
mbed_official	573:ad23fe03a082	807	* @}
mbed_official	573:ad23fe03a082	808	*/
mbed_official	573:ad23fe03a082	809
mbed_official	573:ad23fe03a082	810	/** @defgroup FMC_Continous_Clock FMC Continuous Clock
mbed_official	573:ad23fe03a082	811	* @{
mbed_official	573:ad23fe03a082	812	*/
mbed_official	573:ad23fe03a082	813	#define FMC_CONTINUOUS_CLOCK_SYNC_ONLY ((uint32_t)0x00000000)
mbed_official	573:ad23fe03a082	814	#define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC ((uint32_t)0x00100000)
mbed_official	573:ad23fe03a082	815	/**
mbed_official	573:ad23fe03a082	816	* @}
mbed_official	573:ad23fe03a082	817	*/
mbed_official	573:ad23fe03a082	818
mbed_official	573:ad23fe03a082	819	/** @defgroup FMC_Write_FIFO FMC Write FIFO
mbed_official	573:ad23fe03a082	820	* @{
mbed_official	573:ad23fe03a082	821	*/
mbed_official	573:ad23fe03a082	822	#define FMC_WRITE_FIFO_DISABLE ((uint32_t)0x00000000)
mbed_official	573:ad23fe03a082	823	#define FMC_WRITE_FIFO_ENABLE ((uint32_t)FMC_BCR1_WFDIS)
mbed_official	573:ad23fe03a082	824	/**
mbed_official	573:ad23fe03a082	825	* @}
mbed_official	573:ad23fe03a082	826	*/
mbed_official	573:ad23fe03a082	827
mbed_official	573:ad23fe03a082	828	/** @defgroup FMC_Access_Mode FMC Access Mode
mbed_official	573:ad23fe03a082	829	* @{
mbed_official	573:ad23fe03a082	830	*/
mbed_official	573:ad23fe03a082	831	#define FMC_ACCESS_MODE_A ((uint32_t)0x00000000)
mbed_official	573:ad23fe03a082	832	#define FMC_ACCESS_MODE_B ((uint32_t)0x10000000)
mbed_official	573:ad23fe03a082	833	#define FMC_ACCESS_MODE_C ((uint32_t)0x20000000)
mbed_official	573:ad23fe03a082	834	#define FMC_ACCESS_MODE_D ((uint32_t)0x30000000)
mbed_official	573:ad23fe03a082	835	/**
mbed_official	573:ad23fe03a082	836	* @}
mbed_official	573:ad23fe03a082	837	*/
mbed_official	573:ad23fe03a082	838
mbed_official	573:ad23fe03a082	839	/**
mbed_official	573:ad23fe03a082	840	* @}
mbed_official	573:ad23fe03a082	841	*/
mbed_official	573:ad23fe03a082	842
mbed_official	573:ad23fe03a082	843	/** @defgroup FMC_LL_NAND_Controller FMC NAND Controller
mbed_official	573:ad23fe03a082	844	* @{
mbed_official	573:ad23fe03a082	845	*/
mbed_official	573:ad23fe03a082	846	/** @defgroup FMC_NAND_Bank FMC NAND Bank
mbed_official	573:ad23fe03a082	847	* @{
mbed_official	573:ad23fe03a082	848	*/
mbed_official	573:ad23fe03a082	849	#define FMC_NAND_BANK3 ((uint32_t)0x00000100)
mbed_official	573:ad23fe03a082	850	/**
mbed_official	573:ad23fe03a082	851	* @}
mbed_official	573:ad23fe03a082	852	*/
mbed_official	573:ad23fe03a082	853
mbed_official	573:ad23fe03a082	854	/** @defgroup FMC_Wait_feature FMC Wait feature
mbed_official	573:ad23fe03a082	855	* @{
mbed_official	573:ad23fe03a082	856	*/
mbed_official	573:ad23fe03a082	857	#define FMC_NAND_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000)
mbed_official	573:ad23fe03a082	858	#define FMC_NAND_WAIT_FEATURE_ENABLE ((uint32_t)0x00000002)
mbed_official	573:ad23fe03a082	859	/**
mbed_official	573:ad23fe03a082	860	* @}
mbed_official	573:ad23fe03a082	861	*/
mbed_official	573:ad23fe03a082	862
mbed_official	573:ad23fe03a082	863	/** @defgroup FMC_PCR_Memory_Type FMC PCR Memory Type
mbed_official	573:ad23fe03a082	864	* @{
mbed_official	573:ad23fe03a082	865	*/
mbed_official	573:ad23fe03a082	866	#define FMC_PCR_MEMORY_TYPE_NAND ((uint32_t)0x00000008)
mbed_official	573:ad23fe03a082	867	/**
mbed_official	573:ad23fe03a082	868	* @}
mbed_official	573:ad23fe03a082	869	*/
mbed_official	573:ad23fe03a082	870
mbed_official	573:ad23fe03a082	871	/** @defgroup FMC_NAND_Data_Width FMC NAND Data Width
mbed_official	573:ad23fe03a082	872	* @{
mbed_official	573:ad23fe03a082	873	*/
mbed_official	573:ad23fe03a082	874	#define FMC_NAND_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
mbed_official	573:ad23fe03a082	875	#define FMC_NAND_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
mbed_official	573:ad23fe03a082	876	/**
mbed_official	573:ad23fe03a082	877	* @}
mbed_official	573:ad23fe03a082	878	*/
mbed_official	573:ad23fe03a082	879
mbed_official	573:ad23fe03a082	880	/** @defgroup FMC_ECC FMC ECC
mbed_official	573:ad23fe03a082	881	* @{
mbed_official	573:ad23fe03a082	882	*/
mbed_official	573:ad23fe03a082	883	#define FMC_NAND_ECC_DISABLE ((uint32_t)0x00000000)
mbed_official	573:ad23fe03a082	884	#define FMC_NAND_ECC_ENABLE ((uint32_t)0x00000040)
mbed_official	573:ad23fe03a082	885	/**
mbed_official	573:ad23fe03a082	886	* @}
mbed_official	573:ad23fe03a082	887	*/
mbed_official	573:ad23fe03a082	888
mbed_official	573:ad23fe03a082	889	/** @defgroup FMC_ECC_Page_Size FMC ECC Page Size
mbed_official	573:ad23fe03a082	890	* @{
mbed_official	573:ad23fe03a082	891	*/
mbed_official	573:ad23fe03a082	892	#define FMC_NAND_ECC_PAGE_SIZE_256BYTE ((uint32_t)0x00000000)
mbed_official	573:ad23fe03a082	893	#define FMC_NAND_ECC_PAGE_SIZE_512BYTE ((uint32_t)0x00020000)
mbed_official	573:ad23fe03a082	894	#define FMC_NAND_ECC_PAGE_SIZE_1024BYTE ((uint32_t)0x00040000)
mbed_official	573:ad23fe03a082	895	#define FMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)0x00060000)
mbed_official	573:ad23fe03a082	896	#define FMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)0x00080000)
mbed_official	573:ad23fe03a082	897	#define FMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)0x000A0000)
mbed_official	573:ad23fe03a082	898	/**
mbed_official	573:ad23fe03a082	899	* @}
mbed_official	573:ad23fe03a082	900	*/
mbed_official	573:ad23fe03a082	901
mbed_official	573:ad23fe03a082	902	/**
mbed_official	573:ad23fe03a082	903	* @}
mbed_official	573:ad23fe03a082	904	*/
mbed_official	573:ad23fe03a082	905
mbed_official	573:ad23fe03a082	906	/** @defgroup FMC_LL_SDRAM_Controller FMC SDRAM Controller
mbed_official	573:ad23fe03a082	907	* @{
mbed_official	573:ad23fe03a082	908	*/
mbed_official	573:ad23fe03a082	909	/** @defgroup FMC_SDRAM_Bank FMC SDRAM Bank
mbed_official	573:ad23fe03a082	910	* @{
mbed_official	573:ad23fe03a082	911	*/
mbed_official	573:ad23fe03a082	912	#define FMC_SDRAM_BANK1 ((uint32_t)0x00000000)
mbed_official	573:ad23fe03a082	913	#define FMC_SDRAM_BANK2 ((uint32_t)0x00000001)
mbed_official	573:ad23fe03a082	914	/**
mbed_official	573:ad23fe03a082	915	* @}
mbed_official	573:ad23fe03a082	916	*/
mbed_official	573:ad23fe03a082	917
mbed_official	573:ad23fe03a082	918	/** @defgroup FMC_SDRAM_Column_Bits_number FMC SDRAM Column Bits number
mbed_official	573:ad23fe03a082	919	* @{
mbed_official	573:ad23fe03a082	920	*/
mbed_official	573:ad23fe03a082	921	#define FMC_SDRAM_COLUMN_BITS_NUM_8 ((uint32_t)0x00000000)
mbed_official	573:ad23fe03a082	922	#define FMC_SDRAM_COLUMN_BITS_NUM_9 ((uint32_t)0x00000001)
mbed_official	573:ad23fe03a082	923	#define FMC_SDRAM_COLUMN_BITS_NUM_10 ((uint32_t)0x00000002)
mbed_official	573:ad23fe03a082	924	#define FMC_SDRAM_COLUMN_BITS_NUM_11 ((uint32_t)0x00000003)
mbed_official	573:ad23fe03a082	925	/**
mbed_official	573:ad23fe03a082	926	* @}
mbed_official	573:ad23fe03a082	927	*/
mbed_official	573:ad23fe03a082	928
mbed_official	573:ad23fe03a082	929	/** @defgroup FMC_SDRAM_Row_Bits_number FMC SDRAM Row Bits number
mbed_official	573:ad23fe03a082	930	* @{
mbed_official	573:ad23fe03a082	931	*/
mbed_official	573:ad23fe03a082	932	#define FMC_SDRAM_ROW_BITS_NUM_11 ((uint32_t)0x00000000)
mbed_official	573:ad23fe03a082	933	#define FMC_SDRAM_ROW_BITS_NUM_12 ((uint32_t)0x00000004)
mbed_official	573:ad23fe03a082	934	#define FMC_SDRAM_ROW_BITS_NUM_13 ((uint32_t)0x00000008)
mbed_official	573:ad23fe03a082	935	/**
mbed_official	573:ad23fe03a082	936	* @}
mbed_official	573:ad23fe03a082	937	*/
mbed_official	573:ad23fe03a082	938
mbed_official	573:ad23fe03a082	939	/** @defgroup FMC_SDRAM_Memory_Bus_Width FMC SDRAM Memory Bus Width
mbed_official	573:ad23fe03a082	940	* @{
mbed_official	573:ad23fe03a082	941	*/
mbed_official	573:ad23fe03a082	942	#define FMC_SDRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
mbed_official	573:ad23fe03a082	943	#define FMC_SDRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
mbed_official	573:ad23fe03a082	944	#define FMC_SDRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020)
mbed_official	573:ad23fe03a082	945	/**
mbed_official	573:ad23fe03a082	946	* @}
mbed_official	573:ad23fe03a082	947	*/
mbed_official	573:ad23fe03a082	948
mbed_official	573:ad23fe03a082	949	/** @defgroup FMC_SDRAM_Internal_Banks_Number FMC SDRAM Internal Banks Number
mbed_official	573:ad23fe03a082	950	* @{
mbed_official	573:ad23fe03a082	951	*/
mbed_official	573:ad23fe03a082	952	#define FMC_SDRAM_INTERN_BANKS_NUM_2 ((uint32_t)0x00000000)
mbed_official	573:ad23fe03a082	953	#define FMC_SDRAM_INTERN_BANKS_NUM_4 ((uint32_t)0x00000040)
mbed_official	573:ad23fe03a082	954	/**
mbed_official	573:ad23fe03a082	955	* @}
mbed_official	573:ad23fe03a082	956	*/
mbed_official	573:ad23fe03a082	957
mbed_official	573:ad23fe03a082	958	/** @defgroup FMC_SDRAM_CAS_Latency FMC SDRAM CAS Latency
mbed_official	573:ad23fe03a082	959	* @{
mbed_official	573:ad23fe03a082	960	*/
mbed_official	573:ad23fe03a082	961	#define FMC_SDRAM_CAS_LATENCY_1 ((uint32_t)0x00000080)
mbed_official	573:ad23fe03a082	962	#define FMC_SDRAM_CAS_LATENCY_2 ((uint32_t)0x00000100)
mbed_official	573:ad23fe03a082	963	#define FMC_SDRAM_CAS_LATENCY_3 ((uint32_t)0x00000180)
mbed_official	573:ad23fe03a082	964	/**
mbed_official	573:ad23fe03a082	965	* @}
mbed_official	573:ad23fe03a082	966	*/
mbed_official	573:ad23fe03a082	967
mbed_official	573:ad23fe03a082	968	/** @defgroup FMC_SDRAM_Write_Protection FMC SDRAM Write Protection
mbed_official	573:ad23fe03a082	969	* @{
mbed_official	573:ad23fe03a082	970	*/
mbed_official	573:ad23fe03a082	971	#define FMC_SDRAM_WRITE_PROTECTION_DISABLE ((uint32_t)0x00000000)
mbed_official	573:ad23fe03a082	972	#define FMC_SDRAM_WRITE_PROTECTION_ENABLE ((uint32_t)0x00000200)
mbed_official	573:ad23fe03a082	973	/**
mbed_official	573:ad23fe03a082	974	* @}
mbed_official	573:ad23fe03a082	975	*/
mbed_official	573:ad23fe03a082	976
mbed_official	573:ad23fe03a082	977	/** @defgroup FMC_SDRAM_Clock_Period FMC SDRAM Clock Period
mbed_official	573:ad23fe03a082	978	* @{
mbed_official	573:ad23fe03a082	979	*/
mbed_official	573:ad23fe03a082	980	#define FMC_SDRAM_CLOCK_DISABLE ((uint32_t)0x00000000)
mbed_official	573:ad23fe03a082	981	#define FMC_SDRAM_CLOCK_PERIOD_2 ((uint32_t)0x00000800)
mbed_official	573:ad23fe03a082	982	#define FMC_SDRAM_CLOCK_PERIOD_3 ((uint32_t)0x00000C00)
mbed_official	573:ad23fe03a082	983	/**
mbed_official	573:ad23fe03a082	984	* @}
mbed_official	573:ad23fe03a082	985	*/
mbed_official	573:ad23fe03a082	986
mbed_official	573:ad23fe03a082	987	/** @defgroup FMC_SDRAM_Read_Burst FMC SDRAM Read Burst
mbed_official	573:ad23fe03a082	988	* @{
mbed_official	573:ad23fe03a082	989	*/
mbed_official	573:ad23fe03a082	990	#define FMC_SDRAM_RBURST_DISABLE ((uint32_t)0x00000000)
mbed_official	573:ad23fe03a082	991	#define FMC_SDRAM_RBURST_ENABLE ((uint32_t)0x00001000)
mbed_official	573:ad23fe03a082	992	/**
mbed_official	573:ad23fe03a082	993	* @}
mbed_official	573:ad23fe03a082	994	*/
mbed_official	573:ad23fe03a082	995
mbed_official	573:ad23fe03a082	996	/** @defgroup FMC_SDRAM_Read_Pipe_Delay FMC SDRAM Read Pipe Delay
mbed_official	573:ad23fe03a082	997	* @{
mbed_official	573:ad23fe03a082	998	*/
mbed_official	573:ad23fe03a082	999	#define FMC_SDRAM_RPIPE_DELAY_0 ((uint32_t)0x00000000)
mbed_official	573:ad23fe03a082	1000	#define FMC_SDRAM_RPIPE_DELAY_1 ((uint32_t)0x00002000)
mbed_official	573:ad23fe03a082	1001	#define FMC_SDRAM_RPIPE_DELAY_2 ((uint32_t)0x00004000)
mbed_official	573:ad23fe03a082	1002	/**
mbed_official	573:ad23fe03a082	1003	* @}
mbed_official	573:ad23fe03a082	1004	*/
mbed_official	573:ad23fe03a082	1005
mbed_official	573:ad23fe03a082	1006	/** @defgroup FMC_SDRAM_Command_Mode FMC SDRAM Command Mode
mbed_official	573:ad23fe03a082	1007	* @{
mbed_official	573:ad23fe03a082	1008	*/
mbed_official	573:ad23fe03a082	1009	#define FMC_SDRAM_CMD_NORMAL_MODE ((uint32_t)0x00000000)
mbed_official	573:ad23fe03a082	1010	#define FMC_SDRAM_CMD_CLK_ENABLE ((uint32_t)0x00000001)
mbed_official	573:ad23fe03a082	1011	#define FMC_SDRAM_CMD_PALL ((uint32_t)0x00000002)
mbed_official	573:ad23fe03a082	1012	#define FMC_SDRAM_CMD_AUTOREFRESH_MODE ((uint32_t)0x00000003)
mbed_official	573:ad23fe03a082	1013	#define FMC_SDRAM_CMD_LOAD_MODE ((uint32_t)0x00000004)
mbed_official	573:ad23fe03a082	1014	#define FMC_SDRAM_CMD_SELFREFRESH_MODE ((uint32_t)0x00000005)
mbed_official	573:ad23fe03a082	1015	#define FMC_SDRAM_CMD_POWERDOWN_MODE ((uint32_t)0x00000006)
mbed_official	573:ad23fe03a082	1016	/**
mbed_official	573:ad23fe03a082	1017	* @}
mbed_official	573:ad23fe03a082	1018	*/
mbed_official	573:ad23fe03a082	1019
mbed_official	573:ad23fe03a082	1020	/** @defgroup FMC_SDRAM_Command_Target FMC SDRAM Command Target
mbed_official	573:ad23fe03a082	1021	* @{
mbed_official	573:ad23fe03a082	1022	*/
mbed_official	573:ad23fe03a082	1023	#define FMC_SDRAM_CMD_TARGET_BANK2 FMC_SDCMR_CTB2
mbed_official	573:ad23fe03a082	1024	#define FMC_SDRAM_CMD_TARGET_BANK1 FMC_SDCMR_CTB1
mbed_official	573:ad23fe03a082	1025	#define FMC_SDRAM_CMD_TARGET_BANK1_2 ((uint32_t)0x00000018)
mbed_official	573:ad23fe03a082	1026	/**
mbed_official	573:ad23fe03a082	1027	* @}
mbed_official	573:ad23fe03a082	1028	*/
mbed_official	573:ad23fe03a082	1029
mbed_official	573:ad23fe03a082	1030	/** @defgroup FMC_SDRAM_Mode_Status FMC SDRAM Mode Status
mbed_official	573:ad23fe03a082	1031	* @{
mbed_official	573:ad23fe03a082	1032	*/
mbed_official	573:ad23fe03a082	1033	#define FMC_SDRAM_NORMAL_MODE ((uint32_t)0x00000000)
mbed_official	573:ad23fe03a082	1034	#define FMC_SDRAM_SELF_REFRESH_MODE FMC_SDSR_MODES1_0
mbed_official	573:ad23fe03a082	1035	#define FMC_SDRAM_POWER_DOWN_MODE FMC_SDSR_MODES1_1
mbed_official	573:ad23fe03a082	1036	/**
mbed_official	573:ad23fe03a082	1037	* @}
mbed_official	573:ad23fe03a082	1038	*/
mbed_official	573:ad23fe03a082	1039
mbed_official	573:ad23fe03a082	1040	/**
mbed_official	573:ad23fe03a082	1041	* @}
mbed_official	573:ad23fe03a082	1042	*/
mbed_official	573:ad23fe03a082	1043
mbed_official	573:ad23fe03a082	1044	/** @defgroup FMC_LL_Interrupt_definition FMC Low Layer Interrupt definition
mbed_official	573:ad23fe03a082	1045	* @{
mbed_official	573:ad23fe03a082	1046	*/
mbed_official	573:ad23fe03a082	1047	#define FMC_IT_RISING_EDGE ((uint32_t)0x00000008)
mbed_official	573:ad23fe03a082	1048	#define FMC_IT_LEVEL ((uint32_t)0x00000010)
mbed_official	573:ad23fe03a082	1049	#define FMC_IT_FALLING_EDGE ((uint32_t)0x00000020)
mbed_official	573:ad23fe03a082	1050	#define FMC_IT_REFRESH_ERROR ((uint32_t)0x00004000)
mbed_official	573:ad23fe03a082	1051	/**
mbed_official	573:ad23fe03a082	1052	* @}
mbed_official	573:ad23fe03a082	1053	*/
mbed_official	573:ad23fe03a082	1054
mbed_official	573:ad23fe03a082	1055	/** @defgroup FMC_LL_Flag_definition FMC Low Layer Flag definition
mbed_official	573:ad23fe03a082	1056	* @{
mbed_official	573:ad23fe03a082	1057	*/
mbed_official	573:ad23fe03a082	1058	#define FMC_FLAG_RISING_EDGE ((uint32_t)0x00000001)
mbed_official	573:ad23fe03a082	1059	#define FMC_FLAG_LEVEL ((uint32_t)0x00000002)
mbed_official	573:ad23fe03a082	1060	#define FMC_FLAG_FALLING_EDGE ((uint32_t)0x00000004)
mbed_official	573:ad23fe03a082	1061	#define FMC_FLAG_FEMPT ((uint32_t)0x00000040)
mbed_official	573:ad23fe03a082	1062	#define FMC_SDRAM_FLAG_REFRESH_IT FMC_SDSR_RE
mbed_official	573:ad23fe03a082	1063	#define FMC_SDRAM_FLAG_BUSY FMC_SDSR_BUSY
mbed_official	573:ad23fe03a082	1064	#define FMC_SDRAM_FLAG_REFRESH_ERROR FMC_SDRTR_CRE
mbed_official	573:ad23fe03a082	1065	/**
mbed_official	573:ad23fe03a082	1066	* @}
mbed_official	573:ad23fe03a082	1067	*/
mbed_official	573:ad23fe03a082	1068	/**
mbed_official	573:ad23fe03a082	1069	* @}
mbed_official	573:ad23fe03a082	1070	*/
mbed_official	573:ad23fe03a082	1071
mbed_official	573:ad23fe03a082	1072	/**
mbed_official	573:ad23fe03a082	1073	* @}
mbed_official	573:ad23fe03a082	1074	*/
mbed_official	573:ad23fe03a082	1075
mbed_official	573:ad23fe03a082	1076	/* Private macro -------------------------------------------------------------*/
mbed_official	573:ad23fe03a082	1077	/** @defgroup FMC_LL_Private_Macros FMC_LL Private Macros
mbed_official	573:ad23fe03a082	1078	* @{
mbed_official	573:ad23fe03a082	1079	*/
mbed_official	573:ad23fe03a082	1080
mbed_official	573:ad23fe03a082	1081	/** @defgroup FMC_LL_NOR_Macros FMC NOR/SRAM Macros
mbed_official	573:ad23fe03a082	1082	* @brief macros to handle NOR device enable/disable and read/write operations
mbed_official	573:ad23fe03a082	1083	* @{
mbed_official	573:ad23fe03a082	1084	*/
mbed_official	573:ad23fe03a082	1085
mbed_official	573:ad23fe03a082	1086	/**
mbed_official	573:ad23fe03a082	1087	* @brief Enable the NORSRAM device access.
mbed_official	573:ad23fe03a082	1088	* @param __INSTANCE__: FMC_NORSRAM Instance
mbed_official	573:ad23fe03a082	1089	* @param __BANK__: FMC_NORSRAM Bank
mbed_official	573:ad23fe03a082	1090	* @retval None
mbed_official	573:ad23fe03a082	1091	*/
mbed_official	573:ad23fe03a082	1092	#define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] \|= FMC_BCR1_MBKEN)
mbed_official	573:ad23fe03a082	1093
mbed_official	573:ad23fe03a082	1094	/**
mbed_official	573:ad23fe03a082	1095	* @brief Disable the NORSRAM device access.
mbed_official	573:ad23fe03a082	1096	* @param __INSTANCE__: FMC_NORSRAM Instance
mbed_official	573:ad23fe03a082	1097	* @param __BANK__: FMC_NORSRAM Bank
mbed_official	573:ad23fe03a082	1098	* @retval None
mbed_official	573:ad23fe03a082	1099	*/
mbed_official	573:ad23fe03a082	1100	#define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FMC_BCR1_MBKEN)
mbed_official	573:ad23fe03a082	1101
mbed_official	573:ad23fe03a082	1102	/**
mbed_official	573:ad23fe03a082	1103	* @}
mbed_official	573:ad23fe03a082	1104	*/
mbed_official	573:ad23fe03a082	1105
mbed_official	573:ad23fe03a082	1106	/** @defgroup FMC_LL_NAND_Macros FMC NAND Macros
mbed_official	573:ad23fe03a082	1107	* @brief macros to handle NAND device enable/disable
mbed_official	573:ad23fe03a082	1108	* @{
mbed_official	573:ad23fe03a082	1109	*/
mbed_official	573:ad23fe03a082	1110
mbed_official	573:ad23fe03a082	1111	/**
mbed_official	573:ad23fe03a082	1112	* @brief Enable the NAND device access.
mbed_official	573:ad23fe03a082	1113	* @param __INSTANCE__: FMC_NAND Instance
mbed_official	573:ad23fe03a082	1114	* @retval None
mbed_official	573:ad23fe03a082	1115	*/
mbed_official	573:ad23fe03a082	1116	#define __FMC_NAND_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR \|= FMC_PCR_PBKEN)
mbed_official	573:ad23fe03a082	1117
mbed_official	573:ad23fe03a082	1118	/**
mbed_official	573:ad23fe03a082	1119	* @brief Disable the NAND device access.
mbed_official	573:ad23fe03a082	1120	* @param __INSTANCE__: FMC_NAND Instance
mbed_official	573:ad23fe03a082	1121	* @retval None
mbed_official	573:ad23fe03a082	1122	*/
mbed_official	573:ad23fe03a082	1123	#define __FMC_NAND_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR &= ~FMC_PCR_PBKEN)
mbed_official	573:ad23fe03a082	1124
mbed_official	573:ad23fe03a082	1125	/**
mbed_official	573:ad23fe03a082	1126	* @}
mbed_official	573:ad23fe03a082	1127	*/
mbed_official	573:ad23fe03a082	1128
mbed_official	573:ad23fe03a082	1129	/** @defgroup FMC_Interrupt FMC Interrupt
mbed_official	573:ad23fe03a082	1130	* @brief macros to handle FMC interrupts
mbed_official	573:ad23fe03a082	1131	* @{
mbed_official	573:ad23fe03a082	1132	*/
mbed_official	573:ad23fe03a082	1133
mbed_official	573:ad23fe03a082	1134	/**
mbed_official	573:ad23fe03a082	1135	* @brief Enable the NAND device interrupt.
mbed_official	573:ad23fe03a082	1136	* @param __INSTANCE__: FMC_NAND instance
mbed_official	573:ad23fe03a082	1137	* @param __INTERRUPT__: FMC_NAND interrupt
mbed_official	573:ad23fe03a082	1138	* This parameter can be any combination of the following values:
mbed_official	573:ad23fe03a082	1139	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
mbed_official	573:ad23fe03a082	1140	* @arg FMC_IT_LEVEL: Interrupt level.
mbed_official	573:ad23fe03a082	1141	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
mbed_official	573:ad23fe03a082	1142	* @retval None
mbed_official	573:ad23fe03a082	1143	*/
mbed_official	573:ad23fe03a082	1144	#define __FMC_NAND_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR \|= (__INTERRUPT__))
mbed_official	573:ad23fe03a082	1145
mbed_official	573:ad23fe03a082	1146	/**
mbed_official	573:ad23fe03a082	1147	* @brief Disable the NAND device interrupt.
mbed_official	573:ad23fe03a082	1148	* @param __INSTANCE__: FMC_NAND Instance
mbed_official	573:ad23fe03a082	1149	* @param __INTERRUPT__: FMC_NAND interrupt
mbed_official	573:ad23fe03a082	1150	* This parameter can be any combination of the following values:
mbed_official	573:ad23fe03a082	1151	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
mbed_official	573:ad23fe03a082	1152	* @arg FMC_IT_LEVEL: Interrupt level.
mbed_official	573:ad23fe03a082	1153	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
mbed_official	573:ad23fe03a082	1154	* @retval None
mbed_official	573:ad23fe03a082	1155	*/
mbed_official	573:ad23fe03a082	1156	#define __FMC_NAND_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR &= ~(__INTERRUPT__))
mbed_official	573:ad23fe03a082	1157
mbed_official	573:ad23fe03a082	1158	/**
mbed_official	573:ad23fe03a082	1159	* @brief Get flag status of the NAND device.
mbed_official	573:ad23fe03a082	1160	* @param __INSTANCE__: FMC_NAND Instance
mbed_official	573:ad23fe03a082	1161	* @param __BANK__: FMC_NAND Bank
mbed_official	573:ad23fe03a082	1162	* @param __FLAG__: FMC_NAND flag
mbed_official	573:ad23fe03a082	1163	* This parameter can be any combination of the following values:
mbed_official	573:ad23fe03a082	1164	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
mbed_official	573:ad23fe03a082	1165	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
mbed_official	573:ad23fe03a082	1166	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
mbed_official	573:ad23fe03a082	1167	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
mbed_official	573:ad23fe03a082	1168	* @retval The state of FLAG (SET or RESET).
mbed_official	573:ad23fe03a082	1169	*/
mbed_official	573:ad23fe03a082	1170	#define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__INSTANCE__)->SR &(__FLAG__)) == (__FLAG__))
mbed_official	573:ad23fe03a082	1171
mbed_official	573:ad23fe03a082	1172	/**
mbed_official	573:ad23fe03a082	1173	* @brief Clear flag status of the NAND device.
mbed_official	573:ad23fe03a082	1174	* @param __INSTANCE__: FMC_NAND Instance
mbed_official	573:ad23fe03a082	1175	* @param __FLAG__: FMC_NAND flag
mbed_official	573:ad23fe03a082	1176	* This parameter can be any combination of the following values:
mbed_official	573:ad23fe03a082	1177	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
mbed_official	573:ad23fe03a082	1178	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
mbed_official	573:ad23fe03a082	1179	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
mbed_official	573:ad23fe03a082	1180	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
mbed_official	573:ad23fe03a082	1181	* @retval None
mbed_official	573:ad23fe03a082	1182	*/
mbed_official	573:ad23fe03a082	1183	#define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR &= ~(__FLAG__))
mbed_official	573:ad23fe03a082	1184
mbed_official	573:ad23fe03a082	1185	/**
mbed_official	573:ad23fe03a082	1186	* @brief Enable the SDRAM device interrupt.
mbed_official	573:ad23fe03a082	1187	* @param __INSTANCE__: FMC_SDRAM instance
mbed_official	573:ad23fe03a082	1188	* @param __INTERRUPT__: FMC_SDRAM interrupt
mbed_official	573:ad23fe03a082	1189	* This parameter can be any combination of the following values:
mbed_official	573:ad23fe03a082	1190	* @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error
mbed_official	573:ad23fe03a082	1191	* @retval None
mbed_official	573:ad23fe03a082	1192	*/
mbed_official	573:ad23fe03a082	1193	#define __FMC_SDRAM_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR \|= (__INTERRUPT__))
mbed_official	573:ad23fe03a082	1194
mbed_official	573:ad23fe03a082	1195	/**
mbed_official	573:ad23fe03a082	1196	* @brief Disable the SDRAM device interrupt.
mbed_official	573:ad23fe03a082	1197	* @param __INSTANCE__: FMC_SDRAM instance
mbed_official	573:ad23fe03a082	1198	* @param __INTERRUPT__: FMC_SDRAM interrupt
mbed_official	573:ad23fe03a082	1199	* This parameter can be any combination of the following values:
mbed_official	573:ad23fe03a082	1200	* @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error
mbed_official	573:ad23fe03a082	1201	* @retval None
mbed_official	573:ad23fe03a082	1202	*/
mbed_official	573:ad23fe03a082	1203	#define __FMC_SDRAM_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR &= ~(__INTERRUPT__))
mbed_official	573:ad23fe03a082	1204
mbed_official	573:ad23fe03a082	1205	/**
mbed_official	573:ad23fe03a082	1206	* @brief Get flag status of the SDRAM device.
mbed_official	573:ad23fe03a082	1207	* @param __INSTANCE__: FMC_SDRAM instance
mbed_official	573:ad23fe03a082	1208	* @param __FLAG__: FMC_SDRAM flag
mbed_official	573:ad23fe03a082	1209	* This parameter can be any combination of the following values:
mbed_official	573:ad23fe03a082	1210	* @arg FMC_SDRAM_FLAG_REFRESH_IT: Interrupt refresh error.
mbed_official	573:ad23fe03a082	1211	* @arg FMC_SDRAM_FLAG_BUSY: SDRAM busy flag.
mbed_official	573:ad23fe03a082	1212	* @arg FMC_SDRAM_FLAG_REFRESH_ERROR: Refresh error flag.
mbed_official	573:ad23fe03a082	1213	* @retval The state of FLAG (SET or RESET).
mbed_official	573:ad23fe03a082	1214	*/
mbed_official	573:ad23fe03a082	1215	#define __FMC_SDRAM_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SDSR &(__FLAG__)) == (__FLAG__))
mbed_official	573:ad23fe03a082	1216
mbed_official	573:ad23fe03a082	1217	/**
mbed_official	573:ad23fe03a082	1218	* @brief Clear flag status of the SDRAM device.
mbed_official	573:ad23fe03a082	1219	* @param __INSTANCE__: FMC_SDRAM instance
mbed_official	573:ad23fe03a082	1220	* @param __FLAG__: FMC_SDRAM flag
mbed_official	573:ad23fe03a082	1221	* This parameter can be any combination of the following values:
mbed_official	573:ad23fe03a082	1222	* @arg FMC_SDRAM_FLAG_REFRESH_ERROR
mbed_official	573:ad23fe03a082	1223	* @retval None
mbed_official	573:ad23fe03a082	1224	*/
mbed_official	573:ad23fe03a082	1225	#define __FMC_SDRAM_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SDRTR \|= (__FLAG__))
mbed_official	573:ad23fe03a082	1226	/**
mbed_official	573:ad23fe03a082	1227	* @}
mbed_official	573:ad23fe03a082	1228	*/
mbed_official	573:ad23fe03a082	1229
mbed_official	573:ad23fe03a082	1230	/**
mbed_official	573:ad23fe03a082	1231	* @}
mbed_official	573:ad23fe03a082	1232	*/
mbed_official	573:ad23fe03a082	1233
mbed_official	573:ad23fe03a082	1234	/* Private functions ---------------------------------------------------------*/
mbed_official	573:ad23fe03a082	1235	/** @defgroup FMC_LL_Private_Functions FMC LL Private Functions
mbed_official	573:ad23fe03a082	1236	* @{
mbed_official	573:ad23fe03a082	1237	*/
mbed_official	573:ad23fe03a082	1238
mbed_official	573:ad23fe03a082	1239	/** @defgroup FMC_LL_NORSRAM NOR SRAM
mbed_official	573:ad23fe03a082	1240	* @{
mbed_official	573:ad23fe03a082	1241	*/
mbed_official	573:ad23fe03a082	1242	/** @defgroup FMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions
mbed_official	573:ad23fe03a082	1243	* @{
mbed_official	573:ad23fe03a082	1244	*/
mbed_official	573:ad23fe03a082	1245	HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef Device, FMC_NORSRAM_InitTypeDef Init);
mbed_official	573:ad23fe03a082	1246	HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef Device, FMC_NORSRAM_TimingTypeDef Timing, uint32_t Bank);
mbed_official	573:ad23fe03a082	1247	HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef Device, FMC_NORSRAM_TimingTypeDef Timing, uint32_t Bank, uint32_t ExtendedMode);
mbed_official	573:ad23fe03a082	1248	HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef Device, FMC_NORSRAM_EXTENDED_TypeDef ExDevice, uint32_t Bank);
mbed_official	573:ad23fe03a082	1249	/**
mbed_official	573:ad23fe03a082	1250	* @}
mbed_official	573:ad23fe03a082	1251	*/
mbed_official	573:ad23fe03a082	1252
mbed_official	573:ad23fe03a082	1253	/** @defgroup FMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions
mbed_official	573:ad23fe03a082	1254	* @{
mbed_official	573:ad23fe03a082	1255	*/
mbed_official	573:ad23fe03a082	1256	HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
mbed_official	573:ad23fe03a082	1257	HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
mbed_official	573:ad23fe03a082	1258	/**
mbed_official	573:ad23fe03a082	1259	* @}
mbed_official	573:ad23fe03a082	1260	*/
mbed_official	573:ad23fe03a082	1261	/**
mbed_official	573:ad23fe03a082	1262	* @}
mbed_official	573:ad23fe03a082	1263	*/
mbed_official	573:ad23fe03a082	1264
mbed_official	573:ad23fe03a082	1265	/** @defgroup FMC_LL_NAND NAND
mbed_official	573:ad23fe03a082	1266	* @{
mbed_official	573:ad23fe03a082	1267	*/
mbed_official	573:ad23fe03a082	1268	/** @defgroup FMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions
mbed_official	573:ad23fe03a082	1269	* @{
mbed_official	573:ad23fe03a082	1270	*/
mbed_official	573:ad23fe03a082	1271	HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef Device, FMC_NAND_InitTypeDef Init);
mbed_official	573:ad23fe03a082	1272	HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing, uint32_t Bank);
mbed_official	573:ad23fe03a082	1273	HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing, uint32_t Bank);
mbed_official	573:ad23fe03a082	1274	HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank);
mbed_official	573:ad23fe03a082	1275	/**
mbed_official	573:ad23fe03a082	1276	* @}
mbed_official	573:ad23fe03a082	1277	*/
mbed_official	573:ad23fe03a082	1278
mbed_official	573:ad23fe03a082	1279	/** @defgroup FMC_LL_NAND_Private_Functions_Group2 NAND Control functions
mbed_official	573:ad23fe03a082	1280	* @{
mbed_official	573:ad23fe03a082	1281	*/
mbed_official	573:ad23fe03a082	1282	HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank);
mbed_official	573:ad23fe03a082	1283	HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank);
mbed_official	573:ad23fe03a082	1284	HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef Device, uint32_t ECCval, uint32_t Bank, uint32_t Timeout);
mbed_official	573:ad23fe03a082	1285	/**
mbed_official	573:ad23fe03a082	1286	* @}
mbed_official	573:ad23fe03a082	1287	*/
mbed_official	573:ad23fe03a082	1288
mbed_official	573:ad23fe03a082	1289	/** @defgroup FMC_LL_SDRAM SDRAM
mbed_official	573:ad23fe03a082	1290	* @{
mbed_official	573:ad23fe03a082	1291	*/
mbed_official	573:ad23fe03a082	1292	/** @defgroup FMC_LL_SDRAM_Private_Functions_Group1 SDRAM Initialization/de-initialization functions
mbed_official	573:ad23fe03a082	1293	* @{
mbed_official	573:ad23fe03a082	1294	*/
mbed_official	573:ad23fe03a082	1295	HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef Device, FMC_SDRAM_InitTypeDef Init);
mbed_official	573:ad23fe03a082	1296	HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef Device, FMC_SDRAM_TimingTypeDef Timing, uint32_t Bank);
mbed_official	573:ad23fe03a082	1297	HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
mbed_official	573:ad23fe03a082	1298
mbed_official	573:ad23fe03a082	1299	/**
mbed_official	573:ad23fe03a082	1300	* @}
mbed_official	573:ad23fe03a082	1301	*/
mbed_official	573:ad23fe03a082	1302
mbed_official	573:ad23fe03a082	1303	/** @defgroup FMC_LL_SDRAM_Private_Functions_Group2 SDRAM Control functions
mbed_official	573:ad23fe03a082	1304	* @{
mbed_official	573:ad23fe03a082	1305	*/
mbed_official	573:ad23fe03a082	1306	HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
mbed_official	573:ad23fe03a082	1307	HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
mbed_official	573:ad23fe03a082	1308	HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef Device, FMC_SDRAM_CommandTypeDef Command, uint32_t Timeout);
mbed_official	573:ad23fe03a082	1309	HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate);
mbed_official	573:ad23fe03a082	1310	HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint32_t AutoRefreshNumber);
mbed_official	573:ad23fe03a082	1311	uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
mbed_official	573:ad23fe03a082	1312	/**
mbed_official	573:ad23fe03a082	1313	* @}
mbed_official	573:ad23fe03a082	1314	*/
mbed_official	573:ad23fe03a082	1315
mbed_official	573:ad23fe03a082	1316	/**
mbed_official	573:ad23fe03a082	1317	* @}
mbed_official	573:ad23fe03a082	1318	*/
mbed_official	573:ad23fe03a082	1319
mbed_official	573:ad23fe03a082	1320	/**
mbed_official	573:ad23fe03a082	1321	* @}
mbed_official	573:ad23fe03a082	1322	*/
mbed_official	573:ad23fe03a082	1323
mbed_official	573:ad23fe03a082	1324	/**
mbed_official	573:ad23fe03a082	1325	* @}
mbed_official	573:ad23fe03a082	1326	*/
mbed_official	573:ad23fe03a082	1327
mbed_official	573:ad23fe03a082	1328	/**
mbed_official	573:ad23fe03a082	1329	* @}
mbed_official	573:ad23fe03a082	1330	*/
mbed_official	573:ad23fe03a082	1331	#ifdef __cplusplus
mbed_official	573:ad23fe03a082	1332	}
mbed_official	573:ad23fe03a082	1333	#endif
mbed_official	573:ad23fe03a082	1334
mbed_official	573:ad23fe03a082	1335	#endif /* __STM32F7xx_LL_FMC_H */
mbed_official	573:ad23fe03a082	1336
mbed_official	573:ad23fe03a082	1337	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/