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Last commit 20 Feb 2019 by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_spi.c@579:53297373a894, 2015-07-01 (annotated)

Committer:
mbed_official
Date:
Wed Jul 01 09:45:11 2015 +0100
Revision:
579:53297373a894
Parent:
573:ad23fe03a082
Child:
610:813dcc80987e
Synchronized with git revision d5b4d2ab9c47edb4dc5776e7177b0c2263459081



Full URL: https://github.com/mbedmicro/mbed/commit/d5b4d2ab9c47edb4dc5776e7177b0c2263459081/



Initial version of drivers for SAMR21

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 573:ad23fe03a082 1 /**
mbed_official 573:ad23fe03a082 2 ******************************************************************************
mbed_official 573:ad23fe03a082 3 * @file stm32f7xx_hal_spi.c
mbed_official 573:ad23fe03a082 4 * @author MCD Application Team
mbed_official 573:ad23fe03a082 5 * @version V1.0.0
mbed_official 573:ad23fe03a082 6 * @date 12-May-2015
mbed_official 573:ad23fe03a082 7 * @brief SPI HAL module driver.
mbed_official 573:ad23fe03a082 8 *
mbed_official 573:ad23fe03a082 9 * This file provides firmware functions to manage the following
mbed_official 573:ad23fe03a082 10 * functionalities of the Serial Peripheral Interface (SPI) peripheral:
mbed_official 573:ad23fe03a082 11 * + Initialization and de-initialization functions
mbed_official 573:ad23fe03a082 12 * + IO operation functions
mbed_official 573:ad23fe03a082 13 * + Peripheral Control functions
mbed_official 573:ad23fe03a082 14 * + Peripheral State functions
mbed_official 573:ad23fe03a082 15 @verbatim
mbed_official 573:ad23fe03a082 16 ==============================================================================
mbed_official 573:ad23fe03a082 17 ##### How to use this driver #####
mbed_official 573:ad23fe03a082 18 ==============================================================================
mbed_official 573:ad23fe03a082 19 [..]
mbed_official 573:ad23fe03a082 20 The SPI HAL driver can be used as follows:
mbed_official 573:ad23fe03a082 21
mbed_official 573:ad23fe03a082 22 (#) Declare a SPI_HandleTypeDef handle structure, for example:
mbed_official 573:ad23fe03a082 23 SPI_HandleTypeDef hspi;
mbed_official 573:ad23fe03a082 24
mbed_official 573:ad23fe03a082 25 (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit ()API:
mbed_official 573:ad23fe03a082 26 (##) Enable the SPIx interface clock
mbed_official 573:ad23fe03a082 27 (##) SPI pins configuration
mbed_official 573:ad23fe03a082 28 (+++) Enable the clock for the SPI GPIOs
mbed_official 573:ad23fe03a082 29 (+++) Configure these SPI pins as alternate function push-pull
mbed_official 573:ad23fe03a082 30 (##) NVIC configuration if you need to use interrupt process
mbed_official 573:ad23fe03a082 31 (+++) Configure the SPIx interrupt priority
mbed_official 573:ad23fe03a082 32 (+++) Enable the NVIC SPI IRQ handle
mbed_official 573:ad23fe03a082 33 (##) DMA Configuration if you need to use DMA process
mbed_official 573:ad23fe03a082 34 (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive channel
mbed_official 573:ad23fe03a082 35 (+++) Enable the DMAx clock
mbed_official 573:ad23fe03a082 36 (+++) Configure the DMA handle parameters
mbed_official 573:ad23fe03a082 37 (+++) Configure the DMA Tx or Rx channel
mbed_official 573:ad23fe03a082 38 (+++) Associate the initialized hdma_tx handle to the hspi DMA Tx or Rx handle
mbed_official 573:ad23fe03a082 39 (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx channel
mbed_official 573:ad23fe03a082 40
mbed_official 573:ad23fe03a082 41 (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS
mbed_official 573:ad23fe03a082 42 management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.
mbed_official 573:ad23fe03a082 43
mbed_official 573:ad23fe03a082 44 (#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
mbed_official 573:ad23fe03a082 45 (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
mbed_official 573:ad23fe03a082 46 by calling the customised HAL_SPI_MspInit() API.
mbed_official 573:ad23fe03a082 47 [..]
mbed_official 573:ad23fe03a082 48 Circular mode restriction:
mbed_official 573:ad23fe03a082 49 (#) The DMA circular mode cannot be used when the SPI is configured in these modes:
mbed_official 573:ad23fe03a082 50 (##) Master 2Lines RxOnly
mbed_official 573:ad23fe03a082 51 (##) Master 1Line Rx
mbed_official 573:ad23fe03a082 52 (#) The CRC feature is not managed when the DMA circular mode is enabled
mbed_official 573:ad23fe03a082 53 (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs
mbed_official 573:ad23fe03a082 54 the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks
mbed_official 573:ad23fe03a082 55
mbed_official 573:ad23fe03a082 56 @endverbatim
mbed_official 573:ad23fe03a082 57 ******************************************************************************
mbed_official 573:ad23fe03a082 58 * @attention
mbed_official 573:ad23fe03a082 59 *
mbed_official 573:ad23fe03a082 60 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
mbed_official 573:ad23fe03a082 61 *
mbed_official 573:ad23fe03a082 62 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 573:ad23fe03a082 63 * are permitted provided that the following conditions are met:
mbed_official 573:ad23fe03a082 64 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 573:ad23fe03a082 65 * this list of conditions and the following disclaimer.
mbed_official 573:ad23fe03a082 66 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 573:ad23fe03a082 67 * this list of conditions and the following disclaimer in the documentation
mbed_official 573:ad23fe03a082 68 * and/or other materials provided with the distribution.
mbed_official 573:ad23fe03a082 69 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 573:ad23fe03a082 70 * may be used to endorse or promote products derived from this software
mbed_official 573:ad23fe03a082 71 * without specific prior written permission.
mbed_official 573:ad23fe03a082 72 *
mbed_official 573:ad23fe03a082 73 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 573:ad23fe03a082 74 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 573:ad23fe03a082 75 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 573:ad23fe03a082 76 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 573:ad23fe03a082 77 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 573:ad23fe03a082 78 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 573:ad23fe03a082 79 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 573:ad23fe03a082 80 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 573:ad23fe03a082 81 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 573:ad23fe03a082 82 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 573:ad23fe03a082 83 *
mbed_official 573:ad23fe03a082 84 ******************************************************************************
mbed_official 573:ad23fe03a082 85 */
mbed_official 573:ad23fe03a082 86
mbed_official 573:ad23fe03a082 87 /* Includes ------------------------------------------------------------------*/
mbed_official 573:ad23fe03a082 88 #include "stm32f7xx_hal.h"
mbed_official 573:ad23fe03a082 89
mbed_official 573:ad23fe03a082 90 /** @addtogroup STM32F7xx_HAL_Driver
mbed_official 573:ad23fe03a082 91 * @{
mbed_official 573:ad23fe03a082 92 */
mbed_official 573:ad23fe03a082 93
mbed_official 573:ad23fe03a082 94 /** @defgroup SPI SPI
mbed_official 573:ad23fe03a082 95 * @brief SPI HAL module driver
mbed_official 573:ad23fe03a082 96 * @{
mbed_official 573:ad23fe03a082 97 */
mbed_official 573:ad23fe03a082 98 #ifdef HAL_SPI_MODULE_ENABLED
mbed_official 573:ad23fe03a082 99
mbed_official 573:ad23fe03a082 100 /* Private typedef -----------------------------------------------------------*/
mbed_official 573:ad23fe03a082 101 /* Private defines -----------------------------------------------------------*/
mbed_official 573:ad23fe03a082 102 /** @defgroup SPI_Private_Constants SPI Private Constants
mbed_official 573:ad23fe03a082 103 * @{
mbed_official 573:ad23fe03a082 104 */
mbed_official 573:ad23fe03a082 105 #define SPI_DEFAULT_TIMEOUT 50
mbed_official 573:ad23fe03a082 106 /**
mbed_official 573:ad23fe03a082 107 * @}
mbed_official 573:ad23fe03a082 108 */
mbed_official 573:ad23fe03a082 109
mbed_official 573:ad23fe03a082 110 /* Private macro -------------------------------------------------------------*/
mbed_official 573:ad23fe03a082 111 /* Private variables ---------------------------------------------------------*/
mbed_official 573:ad23fe03a082 112 /* Private function prototypes -----------------------------------------------*/
mbed_official 573:ad23fe03a082 113 /** @addtogroup SPI_Private_Functions
mbed_official 573:ad23fe03a082 114 * @{
mbed_official 573:ad23fe03a082 115 */
mbed_official 573:ad23fe03a082 116 static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
mbed_official 573:ad23fe03a082 117 static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
mbed_official 573:ad23fe03a082 118 static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);
mbed_official 573:ad23fe03a082 119 static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma);
mbed_official 573:ad23fe03a082 120 static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma);
mbed_official 573:ad23fe03a082 121 static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma);
mbed_official 573:ad23fe03a082 122 static void SPI_DMAError(DMA_HandleTypeDef *hdma);
mbed_official 573:ad23fe03a082 123 static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout);
mbed_official 573:ad23fe03a082 124 static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, uint32_t Timeout);
mbed_official 573:ad23fe03a082 125 static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
mbed_official 573:ad23fe03a082 126 static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
mbed_official 573:ad23fe03a082 127 static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
mbed_official 573:ad23fe03a082 128 static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
mbed_official 573:ad23fe03a082 129 static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
mbed_official 573:ad23fe03a082 130 static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
mbed_official 573:ad23fe03a082 131 static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
mbed_official 573:ad23fe03a082 132 static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
mbed_official 573:ad23fe03a082 133 static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
mbed_official 573:ad23fe03a082 134 static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
mbed_official 573:ad23fe03a082 135 static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
mbed_official 573:ad23fe03a082 136 static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
mbed_official 573:ad23fe03a082 137 static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi);
mbed_official 573:ad23fe03a082 138 static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi);
mbed_official 573:ad23fe03a082 139 static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi);
mbed_official 573:ad23fe03a082 140 static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout);
mbed_official 573:ad23fe03a082 141 static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout);
mbed_official 573:ad23fe03a082 142 /**
mbed_official 573:ad23fe03a082 143 * @}
mbed_official 573:ad23fe03a082 144 */
mbed_official 573:ad23fe03a082 145
mbed_official 573:ad23fe03a082 146 /* Exported functions ---------------------------------------------------------*/
mbed_official 573:ad23fe03a082 147
mbed_official 573:ad23fe03a082 148 /** @defgroup SPI_Exported_Functions SPI Exported Functions
mbed_official 573:ad23fe03a082 149 * @{
mbed_official 573:ad23fe03a082 150 */
mbed_official 573:ad23fe03a082 151
mbed_official 573:ad23fe03a082 152 /** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
mbed_official 573:ad23fe03a082 153 * @brief Initialization and Configuration functions
mbed_official 573:ad23fe03a082 154 *
mbed_official 573:ad23fe03a082 155 @verbatim
mbed_official 573:ad23fe03a082 156 ===============================================================================
mbed_official 573:ad23fe03a082 157 ##### Initialization and de-initialization functions #####
mbed_official 573:ad23fe03a082 158 ===============================================================================
mbed_official 573:ad23fe03a082 159 [..] This subsection provides a set of functions allowing to initialize and
mbed_official 573:ad23fe03a082 160 de-initialize the SPIx peripheral:
mbed_official 573:ad23fe03a082 161
mbed_official 573:ad23fe03a082 162 (+) User must implement HAL_SPI_MspInit() function in which he configures
mbed_official 573:ad23fe03a082 163 all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
mbed_official 573:ad23fe03a082 164
mbed_official 573:ad23fe03a082 165 (+) Call the function HAL_SPI_Init() to configure the selected device with
mbed_official 573:ad23fe03a082 166 the selected configuration:
mbed_official 573:ad23fe03a082 167 (++) Mode
mbed_official 573:ad23fe03a082 168 (++) Direction
mbed_official 573:ad23fe03a082 169 (++) Data Size
mbed_official 573:ad23fe03a082 170 (++) Clock Polarity and Phase
mbed_official 573:ad23fe03a082 171 (++) NSS Management
mbed_official 573:ad23fe03a082 172 (++) BaudRate Prescaler
mbed_official 573:ad23fe03a082 173 (++) FirstBit
mbed_official 573:ad23fe03a082 174 (++) TIMode
mbed_official 573:ad23fe03a082 175 (++) CRC Calculation
mbed_official 573:ad23fe03a082 176 (++) CRC Polynomial if CRC enabled
mbed_official 573:ad23fe03a082 177 (++) CRC Length, used only with Data8 and Data16
mbed_official 573:ad23fe03a082 178 (++) FIFO reception threshold
mbed_official 573:ad23fe03a082 179
mbed_official 573:ad23fe03a082 180 (+) Call the function HAL_SPI_DeInit() to restore the default configuration
mbed_official 573:ad23fe03a082 181 of the selected SPIx peripheral.
mbed_official 573:ad23fe03a082 182
mbed_official 573:ad23fe03a082 183 @endverbatim
mbed_official 573:ad23fe03a082 184 * @{
mbed_official 573:ad23fe03a082 185 */
mbed_official 573:ad23fe03a082 186
mbed_official 573:ad23fe03a082 187 /**
mbed_official 573:ad23fe03a082 188 * @brief Initializes the SPI according to the specified parameters
mbed_official 573:ad23fe03a082 189 * in the SPI_InitTypeDef and create the associated handle.
mbed_official 573:ad23fe03a082 190 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 573:ad23fe03a082 191 * the configuration information for SPI module.
mbed_official 573:ad23fe03a082 192 * @retval HAL status
mbed_official 573:ad23fe03a082 193 */
mbed_official 573:ad23fe03a082 194 HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
mbed_official 573:ad23fe03a082 195 {
mbed_official 573:ad23fe03a082 196 uint32_t frxth;
mbed_official 573:ad23fe03a082 197
mbed_official 573:ad23fe03a082 198 /* Check the SPI handle allocation */
mbed_official 573:ad23fe03a082 199 if(hspi == NULL)
mbed_official 573:ad23fe03a082 200 {
mbed_official 573:ad23fe03a082 201 return HAL_ERROR;
mbed_official 573:ad23fe03a082 202 }
mbed_official 573:ad23fe03a082 203
mbed_official 573:ad23fe03a082 204 /* Check the parameters */
mbed_official 573:ad23fe03a082 205 assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
mbed_official 573:ad23fe03a082 206 assert_param(IS_SPI_MODE(hspi->Init.Mode));
mbed_official 573:ad23fe03a082 207 assert_param(IS_SPI_DIRECTION(hspi->Init.Direction));
mbed_official 573:ad23fe03a082 208 assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
mbed_official 573:ad23fe03a082 209 assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
mbed_official 573:ad23fe03a082 210 assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
mbed_official 573:ad23fe03a082 211 assert_param(IS_SPI_NSS(hspi->Init.NSS));
mbed_official 573:ad23fe03a082 212 assert_param(IS_SPI_NSSP(hspi->Init.NSSPMode));
mbed_official 573:ad23fe03a082 213 assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
mbed_official 573:ad23fe03a082 214 assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
mbed_official 573:ad23fe03a082 215 assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
mbed_official 573:ad23fe03a082 216 assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
mbed_official 573:ad23fe03a082 217 assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
mbed_official 573:ad23fe03a082 218 assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength));
mbed_official 573:ad23fe03a082 219
mbed_official 573:ad23fe03a082 220 if(hspi->State == HAL_SPI_STATE_RESET)
mbed_official 573:ad23fe03a082 221 {
mbed_official 573:ad23fe03a082 222 /* Allocate lock resource and initialize it */
mbed_official 573:ad23fe03a082 223 hspi->Lock = HAL_UNLOCKED;
mbed_official 573:ad23fe03a082 224
mbed_official 573:ad23fe03a082 225 /* Init the low level hardware : GPIO, CLOCK, NVIC... */
mbed_official 573:ad23fe03a082 226 HAL_SPI_MspInit(hspi);
mbed_official 573:ad23fe03a082 227 }
mbed_official 573:ad23fe03a082 228
mbed_official 573:ad23fe03a082 229 hspi->State = HAL_SPI_STATE_BUSY;
mbed_official 573:ad23fe03a082 230
mbed_official 573:ad23fe03a082 231 /* Disable the selected SPI peripheral */
mbed_official 573:ad23fe03a082 232 __HAL_SPI_DISABLE(hspi);
mbed_official 573:ad23fe03a082 233
mbed_official 573:ad23fe03a082 234 /* Align by default the rs fifo threshold on the data size */
mbed_official 573:ad23fe03a082 235 if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
mbed_official 573:ad23fe03a082 236 {
mbed_official 573:ad23fe03a082 237 frxth = SPI_RXFIFO_THRESHOLD_HF;
mbed_official 573:ad23fe03a082 238 }
mbed_official 573:ad23fe03a082 239 else
mbed_official 573:ad23fe03a082 240 {
mbed_official 573:ad23fe03a082 241 frxth = SPI_RXFIFO_THRESHOLD_QF;
mbed_official 573:ad23fe03a082 242 }
mbed_official 573:ad23fe03a082 243
mbed_official 573:ad23fe03a082 244 /* CRC calculation is valid only for 16Bit and 8 Bit */
mbed_official 573:ad23fe03a082 245 if(( hspi->Init.DataSize != SPI_DATASIZE_16BIT ) && ( hspi->Init.DataSize != SPI_DATASIZE_8BIT ))
mbed_official 573:ad23fe03a082 246 {
mbed_official 573:ad23fe03a082 247 /* CRC must be disabled */
mbed_official 573:ad23fe03a082 248 hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
mbed_official 573:ad23fe03a082 249 }
mbed_official 573:ad23fe03a082 250
mbed_official 573:ad23fe03a082 251 /* Align the CRC Length on the data size */
mbed_official 573:ad23fe03a082 252 if( hspi->Init.CRCLength == SPI_CRC_LENGTH_DATASIZE)
mbed_official 573:ad23fe03a082 253 {
mbed_official 573:ad23fe03a082 254 /* CRC Length aligned on the data size : value set by default */
mbed_official 573:ad23fe03a082 255 if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
mbed_official 573:ad23fe03a082 256 {
mbed_official 573:ad23fe03a082 257 hspi->Init.CRCLength = SPI_CRC_LENGTH_16BIT;
mbed_official 573:ad23fe03a082 258 }
mbed_official 573:ad23fe03a082 259 else
mbed_official 573:ad23fe03a082 260 {
mbed_official 573:ad23fe03a082 261 hspi->Init.CRCLength = SPI_CRC_LENGTH_8BIT;
mbed_official 573:ad23fe03a082 262 }
mbed_official 573:ad23fe03a082 263 }
mbed_official 573:ad23fe03a082 264
mbed_official 573:ad23fe03a082 265 /*---------------------------- SPIx CR1 & CR2 Configuration ------------------------*/
mbed_official 573:ad23fe03a082 266 /* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management,
mbed_official 573:ad23fe03a082 267 Communication speed, First bit, CRC calculation state, CRC Length */
mbed_official 573:ad23fe03a082 268 hspi->Instance->CR1 = (hspi->Init.Mode | hspi->Init.Direction |
mbed_official 573:ad23fe03a082 269 hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) |
mbed_official 573:ad23fe03a082 270 hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit | hspi->Init.CRCCalculation);
mbed_official 573:ad23fe03a082 271
mbed_official 573:ad23fe03a082 272 if( hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
mbed_official 573:ad23fe03a082 273 {
mbed_official 573:ad23fe03a082 274 hspi->Instance->CR1|= SPI_CR1_CRCL;
mbed_official 573:ad23fe03a082 275 }
mbed_official 573:ad23fe03a082 276
mbed_official 573:ad23fe03a082 277 /* Configure : NSS management */
mbed_official 573:ad23fe03a082 278 /* Configure : Rx Fifo Threshold */
mbed_official 573:ad23fe03a082 279 hspi->Instance->CR2 = (((hspi->Init.NSS >> 16) & SPI_CR2_SSOE) | hspi->Init.TIMode | hspi->Init.NSSPMode |
mbed_official 573:ad23fe03a082 280 hspi->Init.DataSize ) | frxth;
mbed_official 573:ad23fe03a082 281
mbed_official 573:ad23fe03a082 282 /*---------------------------- SPIx CRCPOLY Configuration --------------------*/
mbed_official 573:ad23fe03a082 283 /* Configure : CRC Polynomial */
mbed_official 573:ad23fe03a082 284 hspi->Instance->CRCPR = hspi->Init.CRCPolynomial;
mbed_official 573:ad23fe03a082 285
mbed_official 573:ad23fe03a082 286 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official 573:ad23fe03a082 287 hspi->State= HAL_SPI_STATE_READY;
mbed_official 573:ad23fe03a082 288
mbed_official 573:ad23fe03a082 289 return HAL_OK;
mbed_official 573:ad23fe03a082 290 }
mbed_official 573:ad23fe03a082 291
mbed_official 573:ad23fe03a082 292 /**
mbed_official 573:ad23fe03a082 293 * @brief DeInitializes the SPI peripheral
mbed_official 573:ad23fe03a082 294 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 573:ad23fe03a082 295 * the configuration information for SPI module.
mbed_official 573:ad23fe03a082 296 * @retval HAL status
mbed_official 573:ad23fe03a082 297 */
mbed_official 573:ad23fe03a082 298 HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
mbed_official 573:ad23fe03a082 299 {
mbed_official 573:ad23fe03a082 300 /* Check the SPI handle allocation */
mbed_official 573:ad23fe03a082 301 if(hspi == NULL)
mbed_official 573:ad23fe03a082 302 {
mbed_official 573:ad23fe03a082 303 return HAL_ERROR;
mbed_official 573:ad23fe03a082 304 }
mbed_official 573:ad23fe03a082 305
mbed_official 573:ad23fe03a082 306 /* Check the parameters */
mbed_official 573:ad23fe03a082 307 assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
mbed_official 573:ad23fe03a082 308
mbed_official 573:ad23fe03a082 309 hspi->State = HAL_SPI_STATE_BUSY;
mbed_official 573:ad23fe03a082 310
mbed_official 573:ad23fe03a082 311 /* check flag before the SPI disable */
mbed_official 573:ad23fe03a082 312 SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FTLVL, SPI_FTLVL_EMPTY, SPI_DEFAULT_TIMEOUT);
mbed_official 573:ad23fe03a082 313 SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT);
mbed_official 573:ad23fe03a082 314 SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT);
mbed_official 573:ad23fe03a082 315
mbed_official 573:ad23fe03a082 316 /* Disable the SPI Peripheral Clock */
mbed_official 573:ad23fe03a082 317 __HAL_SPI_DISABLE(hspi);
mbed_official 573:ad23fe03a082 318
mbed_official 573:ad23fe03a082 319 /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
mbed_official 573:ad23fe03a082 320 HAL_SPI_MspDeInit(hspi);
mbed_official 573:ad23fe03a082 321
mbed_official 573:ad23fe03a082 322 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official 573:ad23fe03a082 323 hspi->State = HAL_SPI_STATE_RESET;
mbed_official 573:ad23fe03a082 324
mbed_official 573:ad23fe03a082 325 __HAL_UNLOCK(hspi);
mbed_official 573:ad23fe03a082 326
mbed_official 573:ad23fe03a082 327 return HAL_OK;
mbed_official 573:ad23fe03a082 328 }
mbed_official 573:ad23fe03a082 329
mbed_official 573:ad23fe03a082 330 /**
mbed_official 573:ad23fe03a082 331 * @brief SPI MSP Init
mbed_official 573:ad23fe03a082 332 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 573:ad23fe03a082 333 * the configuration information for SPI module.
mbed_official 573:ad23fe03a082 334 * @retval None
mbed_official 573:ad23fe03a082 335 */
mbed_official 573:ad23fe03a082 336 __weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
mbed_official 573:ad23fe03a082 337 {
mbed_official 573:ad23fe03a082 338 /* NOTE : This function should not be modified, when the callback is needed,
mbed_official 573:ad23fe03a082 339 the HAL_SPI_MspInit should be implemented in the user file
mbed_official 573:ad23fe03a082 340 */
mbed_official 573:ad23fe03a082 341 }
mbed_official 573:ad23fe03a082 342
mbed_official 573:ad23fe03a082 343 /**
mbed_official 573:ad23fe03a082 344 * @brief SPI MSP DeInit
mbed_official 573:ad23fe03a082 345 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 573:ad23fe03a082 346 * the configuration information for SPI module.
mbed_official 573:ad23fe03a082 347 * @retval None
mbed_official 573:ad23fe03a082 348 */
mbed_official 573:ad23fe03a082 349 __weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
mbed_official 573:ad23fe03a082 350 {
mbed_official 573:ad23fe03a082 351 /* NOTE : This function should not be modified, when the callback is needed,
mbed_official 573:ad23fe03a082 352 the HAL_SPI_MspDeInit should be implemented in the user file
mbed_official 573:ad23fe03a082 353 */
mbed_official 573:ad23fe03a082 354 }
mbed_official 573:ad23fe03a082 355
mbed_official 573:ad23fe03a082 356 /**
mbed_official 573:ad23fe03a082 357 * @}
mbed_official 573:ad23fe03a082 358 */
mbed_official 573:ad23fe03a082 359
mbed_official 573:ad23fe03a082 360 /** @defgroup SPI_Exported_Functions_Group2 IO operation functions
mbed_official 573:ad23fe03a082 361 * @brief Data transfers functions
mbed_official 573:ad23fe03a082 362 *
mbed_official 573:ad23fe03a082 363 @verbatim
mbed_official 573:ad23fe03a082 364 ==============================================================================
mbed_official 573:ad23fe03a082 365 ##### IO operation functions #####
mbed_official 573:ad23fe03a082 366 ===============================================================================
mbed_official 573:ad23fe03a082 367 This subsection provides a set of functions allowing to manage the SPI
mbed_official 573:ad23fe03a082 368 data transfers.
mbed_official 573:ad23fe03a082 369
mbed_official 573:ad23fe03a082 370 [..] The SPI supports master and slave mode :
mbed_official 573:ad23fe03a082 371
mbed_official 573:ad23fe03a082 372 (#) There are two modes of transfer:
mbed_official 573:ad23fe03a082 373 (++) Blocking mode: The communication is performed in polling mode.
mbed_official 573:ad23fe03a082 374 The HAL status of all data processing is returned by the same function
mbed_official 573:ad23fe03a082 375 after finishing transfer.
mbed_official 573:ad23fe03a082 376 (++) No-Blocking mode: The communication is performed using Interrupts
mbed_official 573:ad23fe03a082 377 or DMA, These APIs return the HAL status.
mbed_official 573:ad23fe03a082 378 The end of the data processing will be indicated through the
mbed_official 573:ad23fe03a082 379 dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
mbed_official 573:ad23fe03a082 380 using DMA mode.
mbed_official 573:ad23fe03a082 381 The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
mbed_official 573:ad23fe03a082 382 will be executed respectively at the end of the transmit or Receive process
mbed_official 573:ad23fe03a082 383 The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected
mbed_official 573:ad23fe03a082 384
mbed_official 573:ad23fe03a082 385 (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA)
mbed_official 573:ad23fe03a082 386 exist for 1Line (simplex) and 2Lines (full duplex) modes.
mbed_official 573:ad23fe03a082 387
mbed_official 573:ad23fe03a082 388 @endverbatim
mbed_official 573:ad23fe03a082 389 * @{
mbed_official 573:ad23fe03a082 390 */
mbed_official 573:ad23fe03a082 391
mbed_official 573:ad23fe03a082 392 /**
mbed_official 573:ad23fe03a082 393 * @brief Transmit an amount of data in blocking mode
mbed_official 573:ad23fe03a082 394 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 573:ad23fe03a082 395 * the configuration information for SPI module.
mbed_official 573:ad23fe03a082 396 * @param pData: pointer to data buffer
mbed_official 573:ad23fe03a082 397 * @param Size: amount of data to be sent
mbed_official 573:ad23fe03a082 398 * @param Timeout: Timeout duration
mbed_official 573:ad23fe03a082 399 * @retval HAL status
mbed_official 573:ad23fe03a082 400 */
mbed_official 573:ad23fe03a082 401 HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
mbed_official 573:ad23fe03a082 402 {
mbed_official 573:ad23fe03a082 403 assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
mbed_official 573:ad23fe03a082 404
mbed_official 573:ad23fe03a082 405 /* Process Locked */
mbed_official 573:ad23fe03a082 406 __HAL_LOCK(hspi);
mbed_official 573:ad23fe03a082 407
mbed_official 573:ad23fe03a082 408 if(hspi->State != HAL_SPI_STATE_READY)
mbed_official 573:ad23fe03a082 409 {
mbed_official 573:ad23fe03a082 410 hspi->State = HAL_SPI_STATE_READY;
mbed_official 573:ad23fe03a082 411 /* Process Unlocked */
mbed_official 573:ad23fe03a082 412 __HAL_UNLOCK(hspi);
mbed_official 573:ad23fe03a082 413 return HAL_BUSY;
mbed_official 573:ad23fe03a082 414 }
mbed_official 573:ad23fe03a082 415
mbed_official 573:ad23fe03a082 416 if((pData == NULL ) || (Size == 0))
mbed_official 573:ad23fe03a082 417 {
mbed_official 573:ad23fe03a082 418 hspi->State = HAL_SPI_STATE_READY;
mbed_official 573:ad23fe03a082 419 /* Process Unlocked */
mbed_official 573:ad23fe03a082 420 __HAL_UNLOCK(hspi);
mbed_official 573:ad23fe03a082 421 return HAL_ERROR;
mbed_official 573:ad23fe03a082 422 }
mbed_official 573:ad23fe03a082 423
mbed_official 573:ad23fe03a082 424 /* Set the transaction information */
mbed_official 573:ad23fe03a082 425 hspi->State = HAL_SPI_STATE_BUSY_TX;
mbed_official 573:ad23fe03a082 426 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official 573:ad23fe03a082 427 hspi->pTxBuffPtr = pData;
mbed_official 573:ad23fe03a082 428 hspi->TxXferSize = Size;
mbed_official 573:ad23fe03a082 429 hspi->TxXferCount = Size;
mbed_official 573:ad23fe03a082 430 hspi->pRxBuffPtr = (uint8_t *)NULL;
mbed_official 573:ad23fe03a082 431 hspi->RxXferSize = 0;
mbed_official 573:ad23fe03a082 432 hspi->RxXferCount = 0;
mbed_official 573:ad23fe03a082 433
mbed_official 573:ad23fe03a082 434 /* Configure communication direction : 1Line */
mbed_official 573:ad23fe03a082 435 if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
mbed_official 573:ad23fe03a082 436 {
mbed_official 573:ad23fe03a082 437 SPI_1LINE_TX(hspi);
mbed_official 573:ad23fe03a082 438 }
mbed_official 573:ad23fe03a082 439
mbed_official 573:ad23fe03a082 440 /* Reset CRC Calculation */
mbed_official 573:ad23fe03a082 441 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official 573:ad23fe03a082 442 {
mbed_official 573:ad23fe03a082 443 SPI_RESET_CRC(hspi);
mbed_official 573:ad23fe03a082 444 }
mbed_official 573:ad23fe03a082 445
mbed_official 573:ad23fe03a082 446 /* Check if the SPI is already enabled */
mbed_official 573:ad23fe03a082 447 if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official 573:ad23fe03a082 448 {
mbed_official 573:ad23fe03a082 449 /* Enable SPI peripheral */
mbed_official 573:ad23fe03a082 450 __HAL_SPI_ENABLE(hspi);
mbed_official 573:ad23fe03a082 451 }
mbed_official 573:ad23fe03a082 452
mbed_official 573:ad23fe03a082 453 /* Transmit data in 16 Bit mode */
mbed_official 573:ad23fe03a082 454 if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
mbed_official 573:ad23fe03a082 455 {
mbed_official 573:ad23fe03a082 456 /* Transmit data in 16 Bit mode */
mbed_official 573:ad23fe03a082 457 while (hspi->TxXferCount > 0)
mbed_official 573:ad23fe03a082 458 {
mbed_official 573:ad23fe03a082 459 /* Wait until TXE flag is set to send data */
mbed_official 573:ad23fe03a082 460 if(SPI_WaitFlagStateUntilTimeout(hspi,SPI_FLAG_TXE,SPI_FLAG_TXE,Timeout) != HAL_OK)
mbed_official 573:ad23fe03a082 461 {
mbed_official 573:ad23fe03a082 462 hspi->State = HAL_SPI_STATE_READY;
mbed_official 573:ad23fe03a082 463 /* Process Unlocked */
mbed_official 573:ad23fe03a082 464 __HAL_UNLOCK(hspi);
mbed_official 573:ad23fe03a082 465 return HAL_TIMEOUT;
mbed_official 573:ad23fe03a082 466 }
mbed_official 573:ad23fe03a082 467 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
mbed_official 573:ad23fe03a082 468 hspi->pTxBuffPtr += sizeof(uint16_t);
mbed_official 573:ad23fe03a082 469 hspi->TxXferCount--;
mbed_official 573:ad23fe03a082 470 }
mbed_official 573:ad23fe03a082 471 }
mbed_official 573:ad23fe03a082 472 /* Transmit data in 8 Bit mode */
mbed_official 573:ad23fe03a082 473 else
mbed_official 573:ad23fe03a082 474 {
mbed_official 573:ad23fe03a082 475 while (hspi->TxXferCount > 0)
mbed_official 573:ad23fe03a082 476 {
mbed_official 573:ad23fe03a082 477 if(hspi->TxXferCount != 0x1)
mbed_official 573:ad23fe03a082 478 {
mbed_official 573:ad23fe03a082 479 /* Wait until TXE flag is set to send data */
mbed_official 573:ad23fe03a082 480 if(SPI_WaitFlagStateUntilTimeout(hspi,SPI_FLAG_TXE,SPI_FLAG_TXE,Timeout) != HAL_OK)
mbed_official 573:ad23fe03a082 481 {
mbed_official 573:ad23fe03a082 482 hspi->State = HAL_SPI_STATE_READY;
mbed_official 573:ad23fe03a082 483 /* Process Unlocked */
mbed_official 573:ad23fe03a082 484 __HAL_UNLOCK(hspi);
mbed_official 573:ad23fe03a082 485 return HAL_TIMEOUT;
mbed_official 573:ad23fe03a082 486 }
mbed_official 573:ad23fe03a082 487 hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr);
mbed_official 573:ad23fe03a082 488 hspi->pTxBuffPtr += sizeof(uint16_t);
mbed_official 573:ad23fe03a082 489 hspi->TxXferCount -= 2;
mbed_official 573:ad23fe03a082 490 }
mbed_official 573:ad23fe03a082 491 else
mbed_official 573:ad23fe03a082 492 {
mbed_official 573:ad23fe03a082 493 /* Wait until TXE flag is set to send data */
mbed_official 573:ad23fe03a082 494 if(SPI_WaitFlagStateUntilTimeout(hspi,SPI_FLAG_TXE,SPI_FLAG_TXE,Timeout) != HAL_OK)
mbed_official 573:ad23fe03a082 495 {
mbed_official 573:ad23fe03a082 496 return HAL_TIMEOUT;
mbed_official 573:ad23fe03a082 497 }
mbed_official 573:ad23fe03a082 498 *((__IO uint8_t*)&hspi->Instance->DR) = (*hspi->pTxBuffPtr++);
mbed_official 573:ad23fe03a082 499 hspi->TxXferCount--;
mbed_official 573:ad23fe03a082 500 }
mbed_official 573:ad23fe03a082 501 }
mbed_official 573:ad23fe03a082 502 }
mbed_official 573:ad23fe03a082 503
mbed_official 573:ad23fe03a082 504 /* Enable CRC Transmission */
mbed_official 573:ad23fe03a082 505 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official 573:ad23fe03a082 506 {
mbed_official 573:ad23fe03a082 507 hspi->Instance->CR1|= SPI_CR1_CRCNEXT;
mbed_official 573:ad23fe03a082 508 }
mbed_official 573:ad23fe03a082 509
mbed_official 573:ad23fe03a082 510 /* Check the end of the transaction */
mbed_official 573:ad23fe03a082 511 if(SPI_EndRxTxTransaction(hspi,Timeout) != HAL_OK)
mbed_official 573:ad23fe03a082 512 {
mbed_official 573:ad23fe03a082 513 return HAL_TIMEOUT;
mbed_official 573:ad23fe03a082 514 }
mbed_official 573:ad23fe03a082 515
mbed_official 573:ad23fe03a082 516 /* Clear OVERUN flag in 2 Lines communication mode because received is not read */
mbed_official 573:ad23fe03a082 517 if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
mbed_official 573:ad23fe03a082 518 {
mbed_official 573:ad23fe03a082 519 __HAL_SPI_CLEAR_OVRFLAG(hspi);
mbed_official 573:ad23fe03a082 520 }
mbed_official 573:ad23fe03a082 521
mbed_official 573:ad23fe03a082 522 hspi->State = HAL_SPI_STATE_READY;
mbed_official 573:ad23fe03a082 523
mbed_official 573:ad23fe03a082 524 /* Process Unlocked */
mbed_official 573:ad23fe03a082 525 __HAL_UNLOCK(hspi);
mbed_official 573:ad23fe03a082 526
mbed_official 573:ad23fe03a082 527 if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
mbed_official 573:ad23fe03a082 528 {
mbed_official 573:ad23fe03a082 529 return HAL_ERROR;
mbed_official 573:ad23fe03a082 530 }
mbed_official 573:ad23fe03a082 531 else
mbed_official 573:ad23fe03a082 532 {
mbed_official 573:ad23fe03a082 533 return HAL_OK;
mbed_official 573:ad23fe03a082 534 }
mbed_official 573:ad23fe03a082 535 }
mbed_official 573:ad23fe03a082 536
mbed_official 573:ad23fe03a082 537 /**
mbed_official 573:ad23fe03a082 538 * @brief Receive an amount of data in blocking mode
mbed_official 573:ad23fe03a082 539 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 573:ad23fe03a082 540 * the configuration information for SPI module.
mbed_official 573:ad23fe03a082 541 * @param pData: pointer to data buffer
mbed_official 573:ad23fe03a082 542 * @param Size: amount of data to be received
mbed_official 573:ad23fe03a082 543 * @param Timeout: Timeout duration
mbed_official 573:ad23fe03a082 544 * @retval HAL status
mbed_official 573:ad23fe03a082 545 */
mbed_official 573:ad23fe03a082 546 HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
mbed_official 573:ad23fe03a082 547 {
mbed_official 573:ad23fe03a082 548 __IO uint16_t tmpreg;
mbed_official 573:ad23fe03a082 549
mbed_official 573:ad23fe03a082 550 if(hspi->State != HAL_SPI_STATE_READY)
mbed_official 573:ad23fe03a082 551 {
mbed_official 573:ad23fe03a082 552 return HAL_BUSY;
mbed_official 573:ad23fe03a082 553 }
mbed_official 573:ad23fe03a082 554
mbed_official 573:ad23fe03a082 555 if((pData == NULL ) || (Size == 0))
mbed_official 573:ad23fe03a082 556 {
mbed_official 573:ad23fe03a082 557 return HAL_ERROR;
mbed_official 573:ad23fe03a082 558 }
mbed_official 573:ad23fe03a082 559
mbed_official 573:ad23fe03a082 560 if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
mbed_official 573:ad23fe03a082 561 {
mbed_official 573:ad23fe03a082 562 /* the receive process is not supported in 2Lines direction master mode */
mbed_official 573:ad23fe03a082 563 /* in this case we call the transmitReceive process */
mbed_official 573:ad23fe03a082 564 return HAL_SPI_TransmitReceive(hspi,pData,pData,Size,Timeout);
mbed_official 573:ad23fe03a082 565 }
mbed_official 573:ad23fe03a082 566
mbed_official 573:ad23fe03a082 567 /* Process Locked */
mbed_official 573:ad23fe03a082 568 __HAL_LOCK(hspi);
mbed_official 573:ad23fe03a082 569
mbed_official 573:ad23fe03a082 570 hspi->State = HAL_SPI_STATE_BUSY_RX;
mbed_official 573:ad23fe03a082 571 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official 573:ad23fe03a082 572 hspi->pRxBuffPtr = pData;
mbed_official 573:ad23fe03a082 573 hspi->RxXferSize = Size;
mbed_official 573:ad23fe03a082 574 hspi->RxXferCount = Size;
mbed_official 573:ad23fe03a082 575 hspi->pTxBuffPtr = (uint8_t *)NULL;
mbed_official 573:ad23fe03a082 576 hspi->TxXferSize = 0;
mbed_official 573:ad23fe03a082 577 hspi->TxXferCount = 0;
mbed_official 573:ad23fe03a082 578
mbed_official 573:ad23fe03a082 579 /* Reset CRC Calculation */
mbed_official 573:ad23fe03a082 580 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official 573:ad23fe03a082 581 {
mbed_official 573:ad23fe03a082 582 SPI_RESET_CRC(hspi);
mbed_official 573:ad23fe03a082 583 /* this is done to handle the CRCNEXT before the latest data */
mbed_official 573:ad23fe03a082 584 hspi->RxXferCount--;
mbed_official 573:ad23fe03a082 585 }
mbed_official 573:ad23fe03a082 586
mbed_official 573:ad23fe03a082 587 /* Set the Rx Fido threshold */
mbed_official 573:ad23fe03a082 588 if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
mbed_official 573:ad23fe03a082 589 {
mbed_official 573:ad23fe03a082 590 /* set fiforxthreshold according the reception data length: 16bit */
mbed_official 573:ad23fe03a082 591 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
mbed_official 573:ad23fe03a082 592 }
mbed_official 573:ad23fe03a082 593 else
mbed_official 573:ad23fe03a082 594 {
mbed_official 573:ad23fe03a082 595 /* set fiforxthreshold according the reception data length: 8bit */
mbed_official 573:ad23fe03a082 596 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
mbed_official 573:ad23fe03a082 597 }
mbed_official 573:ad23fe03a082 598
mbed_official 573:ad23fe03a082 599 /* Configure communication direction 1Line and enabled SPI if needed */
mbed_official 573:ad23fe03a082 600 if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
mbed_official 573:ad23fe03a082 601 {
mbed_official 573:ad23fe03a082 602 SPI_1LINE_RX(hspi);
mbed_official 573:ad23fe03a082 603 }
mbed_official 573:ad23fe03a082 604
mbed_official 573:ad23fe03a082 605 /* Check if the SPI is already enabled */
mbed_official 573:ad23fe03a082 606 if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official 573:ad23fe03a082 607 {
mbed_official 573:ad23fe03a082 608 /* Enable SPI peripheral */
mbed_official 573:ad23fe03a082 609 __HAL_SPI_ENABLE(hspi);
mbed_official 573:ad23fe03a082 610 }
mbed_official 573:ad23fe03a082 611
mbed_official 573:ad23fe03a082 612 /* Receive data in 8 Bit mode */
mbed_official 573:ad23fe03a082 613 if(hspi->Init.DataSize <= SPI_DATASIZE_8BIT)
mbed_official 573:ad23fe03a082 614 {
mbed_official 573:ad23fe03a082 615 while(hspi->RxXferCount > 1)
mbed_official 573:ad23fe03a082 616 {
mbed_official 573:ad23fe03a082 617 /* Wait until the RXNE flag */
mbed_official 573:ad23fe03a082 618 if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
mbed_official 573:ad23fe03a082 619 {
mbed_official 573:ad23fe03a082 620 return HAL_TIMEOUT;
mbed_official 573:ad23fe03a082 621 }
mbed_official 573:ad23fe03a082 622 (*hspi->pRxBuffPtr++)= *(__IO uint8_t *)&hspi->Instance->DR;
mbed_official 573:ad23fe03a082 623 hspi->RxXferCount--;
mbed_official 573:ad23fe03a082 624 }
mbed_official 573:ad23fe03a082 625 }
mbed_official 573:ad23fe03a082 626 else /* Receive data in 16 Bit mode */
mbed_official 573:ad23fe03a082 627 {
mbed_official 573:ad23fe03a082 628 while(hspi->RxXferCount > 1 )
mbed_official 573:ad23fe03a082 629 {
mbed_official 573:ad23fe03a082 630 /* Wait until RXNE flag is reset to read data */
mbed_official 573:ad23fe03a082 631 if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
mbed_official 573:ad23fe03a082 632 {
mbed_official 573:ad23fe03a082 633 return HAL_TIMEOUT;
mbed_official 573:ad23fe03a082 634 }
mbed_official 573:ad23fe03a082 635 *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
mbed_official 573:ad23fe03a082 636 hspi->pRxBuffPtr += sizeof(uint16_t);
mbed_official 573:ad23fe03a082 637 hspi->RxXferCount--;
mbed_official 573:ad23fe03a082 638 }
mbed_official 573:ad23fe03a082 639 }
mbed_official 573:ad23fe03a082 640
mbed_official 573:ad23fe03a082 641 /* Enable CRC Transmission */
mbed_official 573:ad23fe03a082 642 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official 573:ad23fe03a082 643 {
mbed_official 573:ad23fe03a082 644 hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
mbed_official 573:ad23fe03a082 645 }
mbed_official 573:ad23fe03a082 646
mbed_official 573:ad23fe03a082 647 /* Wait until RXNE flag is set */
mbed_official 573:ad23fe03a082 648 if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
mbed_official 573:ad23fe03a082 649 {
mbed_official 573:ad23fe03a082 650 return HAL_TIMEOUT;
mbed_official 573:ad23fe03a082 651 }
mbed_official 573:ad23fe03a082 652
mbed_official 573:ad23fe03a082 653 /* Receive last data in 16 Bit mode */
mbed_official 573:ad23fe03a082 654 if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
mbed_official 573:ad23fe03a082 655 {
mbed_official 573:ad23fe03a082 656 *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
mbed_official 573:ad23fe03a082 657 hspi->pRxBuffPtr += sizeof(uint16_t);
mbed_official 573:ad23fe03a082 658 }
mbed_official 573:ad23fe03a082 659 /* Receive last data in 8 Bit mode */
mbed_official 573:ad23fe03a082 660 else
mbed_official 573:ad23fe03a082 661 {
mbed_official 573:ad23fe03a082 662 (*hspi->pRxBuffPtr++) = *(__IO uint8_t *)&hspi->Instance->DR;
mbed_official 573:ad23fe03a082 663 }
mbed_official 573:ad23fe03a082 664 hspi->RxXferCount--;
mbed_official 573:ad23fe03a082 665
mbed_official 573:ad23fe03a082 666 /* Read CRC from DR to close CRC calculation process */
mbed_official 573:ad23fe03a082 667 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official 573:ad23fe03a082 668 {
mbed_official 573:ad23fe03a082 669 /* Wait until TXE flag */
mbed_official 573:ad23fe03a082 670 if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
mbed_official 573:ad23fe03a082 671 {
mbed_official 573:ad23fe03a082 672 /* Error on the CRC reception */
mbed_official 573:ad23fe03a082 673 hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
mbed_official 573:ad23fe03a082 674 }
mbed_official 573:ad23fe03a082 675 if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
mbed_official 573:ad23fe03a082 676 {
mbed_official 573:ad23fe03a082 677 tmpreg = hspi->Instance->DR;
mbed_official 573:ad23fe03a082 678 UNUSED(tmpreg); /* To avoid GCC warning */
mbed_official 573:ad23fe03a082 679 }
mbed_official 573:ad23fe03a082 680 else
mbed_official 573:ad23fe03a082 681 {
mbed_official 573:ad23fe03a082 682 tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
mbed_official 573:ad23fe03a082 683 UNUSED(tmpreg); /* To avoid GCC warning */
mbed_official 573:ad23fe03a082 684
mbed_official 573:ad23fe03a082 685 if((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
mbed_official 573:ad23fe03a082 686 {
mbed_official 573:ad23fe03a082 687 if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
mbed_official 573:ad23fe03a082 688 {
mbed_official 573:ad23fe03a082 689 /* Error on the CRC reception */
mbed_official 573:ad23fe03a082 690 hspi->ErrorCode|= HAL_SPI_ERROR_FLAG;
mbed_official 573:ad23fe03a082 691 }
mbed_official 573:ad23fe03a082 692 tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
mbed_official 573:ad23fe03a082 693 UNUSED(tmpreg); /* To avoid GCC warning */
mbed_official 573:ad23fe03a082 694 }
mbed_official 573:ad23fe03a082 695 }
mbed_official 573:ad23fe03a082 696 }
mbed_official 573:ad23fe03a082 697
mbed_official 573:ad23fe03a082 698 /* Check the end of the transaction */
mbed_official 573:ad23fe03a082 699 if(SPI_EndRxTransaction(hspi,Timeout) != HAL_OK)
mbed_official 573:ad23fe03a082 700 {
mbed_official 573:ad23fe03a082 701 return HAL_TIMEOUT;
mbed_official 573:ad23fe03a082 702 }
mbed_official 573:ad23fe03a082 703
mbed_official 573:ad23fe03a082 704 hspi->State = HAL_SPI_STATE_READY;
mbed_official 573:ad23fe03a082 705
mbed_official 573:ad23fe03a082 706 /* Check if CRC error occurred */
mbed_official 573:ad23fe03a082 707 if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
mbed_official 573:ad23fe03a082 708 {
mbed_official 573:ad23fe03a082 709 hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
mbed_official 573:ad23fe03a082 710 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
mbed_official 573:ad23fe03a082 711
mbed_official 573:ad23fe03a082 712 /* Process Unlocked */
mbed_official 573:ad23fe03a082 713 __HAL_UNLOCK(hspi);
mbed_official 573:ad23fe03a082 714 return HAL_ERROR;
mbed_official 573:ad23fe03a082 715 }
mbed_official 573:ad23fe03a082 716
mbed_official 573:ad23fe03a082 717 /* Process Unlocked */
mbed_official 573:ad23fe03a082 718 __HAL_UNLOCK(hspi);
mbed_official 573:ad23fe03a082 719
mbed_official 573:ad23fe03a082 720 if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
mbed_official 573:ad23fe03a082 721 {
mbed_official 573:ad23fe03a082 722 return HAL_ERROR;
mbed_official 573:ad23fe03a082 723 }
mbed_official 573:ad23fe03a082 724 else
mbed_official 573:ad23fe03a082 725 {
mbed_official 573:ad23fe03a082 726 return HAL_OK;
mbed_official 573:ad23fe03a082 727 }
mbed_official 573:ad23fe03a082 728 }
mbed_official 573:ad23fe03a082 729
mbed_official 573:ad23fe03a082 730 /**
mbed_official 573:ad23fe03a082 731 * @brief Transmit and Receive an amount of data in blocking mode
mbed_official 573:ad23fe03a082 732 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 573:ad23fe03a082 733 * the configuration information for SPI module.
mbed_official 573:ad23fe03a082 734 * @param pTxData: pointer to transmission data buffer
mbed_official 573:ad23fe03a082 735 * @param pRxData: pointer to reception data buffer
mbed_official 573:ad23fe03a082 736 * @param Size: amount of data to be sent and received
mbed_official 573:ad23fe03a082 737 * @param Timeout: Timeout duration
mbed_official 573:ad23fe03a082 738 * @retval HAL status
mbed_official 573:ad23fe03a082 739 */
mbed_official 573:ad23fe03a082 740 HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
mbed_official 573:ad23fe03a082 741 {
mbed_official 573:ad23fe03a082 742 __IO uint16_t tmpreg = 0;
mbed_official 573:ad23fe03a082 743 uint32_t tickstart = HAL_GetTick();
mbed_official 573:ad23fe03a082 744
mbed_official 573:ad23fe03a082 745 assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
mbed_official 573:ad23fe03a082 746
mbed_official 573:ad23fe03a082 747 if(hspi->State != HAL_SPI_STATE_READY)
mbed_official 573:ad23fe03a082 748 {
mbed_official 573:ad23fe03a082 749 return HAL_BUSY;
mbed_official 573:ad23fe03a082 750 }
mbed_official 573:ad23fe03a082 751
mbed_official 573:ad23fe03a082 752 if((pTxData == NULL) || (pRxData == NULL) || (Size == 0))
mbed_official 573:ad23fe03a082 753 {
mbed_official 573:ad23fe03a082 754 return HAL_ERROR;
mbed_official 573:ad23fe03a082 755 }
mbed_official 573:ad23fe03a082 756
mbed_official 573:ad23fe03a082 757
mbed_official 573:ad23fe03a082 758 /* Process Locked */
mbed_official 573:ad23fe03a082 759 __HAL_LOCK(hspi);
mbed_official 573:ad23fe03a082 760
mbed_official 573:ad23fe03a082 761 hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
mbed_official 573:ad23fe03a082 762 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official 573:ad23fe03a082 763 hspi->pRxBuffPtr = pRxData;
mbed_official 573:ad23fe03a082 764 hspi->RxXferCount = Size;
mbed_official 573:ad23fe03a082 765 hspi->RxXferSize = Size;
mbed_official 573:ad23fe03a082 766 hspi->pTxBuffPtr = pTxData;
mbed_official 573:ad23fe03a082 767 hspi->TxXferCount = Size;
mbed_official 573:ad23fe03a082 768 hspi->TxXferSize = Size;
mbed_official 573:ad23fe03a082 769
mbed_official 573:ad23fe03a082 770 /* Reset CRC Calculation */
mbed_official 573:ad23fe03a082 771 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official 573:ad23fe03a082 772 {
mbed_official 573:ad23fe03a082 773 SPI_RESET_CRC(hspi);
mbed_official 573:ad23fe03a082 774 }
mbed_official 573:ad23fe03a082 775
mbed_official 573:ad23fe03a082 776 /* Set the Rx Fido threshold */
mbed_official 573:ad23fe03a082 777 if((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (hspi->RxXferCount > 1))
mbed_official 573:ad23fe03a082 778 {
mbed_official 573:ad23fe03a082 779 /* set fiforxthreshold according the reception data length: 16bit */
mbed_official 573:ad23fe03a082 780 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
mbed_official 573:ad23fe03a082 781 }
mbed_official 573:ad23fe03a082 782 else
mbed_official 573:ad23fe03a082 783 {
mbed_official 573:ad23fe03a082 784 /* set fiforxthreshold according the reception data length: 8bit */
mbed_official 573:ad23fe03a082 785 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
mbed_official 573:ad23fe03a082 786 }
mbed_official 573:ad23fe03a082 787
mbed_official 573:ad23fe03a082 788 /* Check if the SPI is already enabled */
mbed_official 573:ad23fe03a082 789 if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official 573:ad23fe03a082 790 {
mbed_official 573:ad23fe03a082 791 /* Enable SPI peripheral */
mbed_official 573:ad23fe03a082 792 __HAL_SPI_ENABLE(hspi);
mbed_official 573:ad23fe03a082 793 }
mbed_official 573:ad23fe03a082 794
mbed_official 573:ad23fe03a082 795 /* Transmit and Receive data in 16 Bit mode */
mbed_official 573:ad23fe03a082 796 if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
mbed_official 573:ad23fe03a082 797 {
mbed_official 573:ad23fe03a082 798 while ((hspi->TxXferCount > 0 ) || (hspi->RxXferCount > 0))
mbed_official 573:ad23fe03a082 799 {
mbed_official 573:ad23fe03a082 800 /* Check TXE flag */
mbed_official 573:ad23fe03a082 801 if((hspi->TxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_TXE) == SPI_FLAG_TXE))
mbed_official 573:ad23fe03a082 802 {
mbed_official 573:ad23fe03a082 803 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
mbed_official 573:ad23fe03a082 804 hspi->pTxBuffPtr += sizeof(uint16_t);
mbed_official 573:ad23fe03a082 805 hspi->TxXferCount--;
mbed_official 573:ad23fe03a082 806
mbed_official 573:ad23fe03a082 807 /* Enable CRC Transmission */
mbed_official 573:ad23fe03a082 808 if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
mbed_official 573:ad23fe03a082 809 {
mbed_official 573:ad23fe03a082 810 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
mbed_official 573:ad23fe03a082 811 }
mbed_official 573:ad23fe03a082 812 }
mbed_official 573:ad23fe03a082 813
mbed_official 573:ad23fe03a082 814 /* Check RXNE flag */
mbed_official 573:ad23fe03a082 815 if((hspi->RxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_RXNE) == SPI_FLAG_RXNE))
mbed_official 573:ad23fe03a082 816 {
mbed_official 573:ad23fe03a082 817 *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR;
mbed_official 573:ad23fe03a082 818 hspi->pRxBuffPtr += sizeof(uint16_t);
mbed_official 573:ad23fe03a082 819 hspi->RxXferCount--;
mbed_official 573:ad23fe03a082 820 }
mbed_official 573:ad23fe03a082 821 if(Timeout != HAL_MAX_DELAY)
mbed_official 573:ad23fe03a082 822 {
mbed_official 573:ad23fe03a082 823 if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
mbed_official 573:ad23fe03a082 824 {
mbed_official 573:ad23fe03a082 825 hspi->State = HAL_SPI_STATE_READY;
mbed_official 573:ad23fe03a082 826 __HAL_UNLOCK(hspi);
mbed_official 573:ad23fe03a082 827 return HAL_TIMEOUT;
mbed_official 573:ad23fe03a082 828 }
mbed_official 573:ad23fe03a082 829 }
mbed_official 573:ad23fe03a082 830 }
mbed_official 573:ad23fe03a082 831 }
mbed_official 573:ad23fe03a082 832 /* Transmit and Receive data in 8 Bit mode */
mbed_official 573:ad23fe03a082 833 else
mbed_official 573:ad23fe03a082 834 {
mbed_official 573:ad23fe03a082 835 while((hspi->TxXferCount > 0) || (hspi->RxXferCount > 0))
mbed_official 573:ad23fe03a082 836 {
mbed_official 573:ad23fe03a082 837 /* check TXE flag */
mbed_official 573:ad23fe03a082 838 if((hspi->TxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_TXE) == SPI_FLAG_TXE))
mbed_official 573:ad23fe03a082 839 {
mbed_official 573:ad23fe03a082 840 if(hspi->TxXferCount > 1)
mbed_official 573:ad23fe03a082 841 {
mbed_official 573:ad23fe03a082 842 hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr);
mbed_official 573:ad23fe03a082 843 hspi->pTxBuffPtr += sizeof(uint16_t);
mbed_official 573:ad23fe03a082 844 hspi->TxXferCount -= 2;
mbed_official 573:ad23fe03a082 845 }
mbed_official 573:ad23fe03a082 846 else
mbed_official 573:ad23fe03a082 847 {
mbed_official 573:ad23fe03a082 848 *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
mbed_official 573:ad23fe03a082 849 hspi->TxXferCount--;
mbed_official 573:ad23fe03a082 850 }
mbed_official 573:ad23fe03a082 851
mbed_official 573:ad23fe03a082 852 /* Enable CRC Transmission */
mbed_official 573:ad23fe03a082 853 if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
mbed_official 573:ad23fe03a082 854 {
mbed_official 573:ad23fe03a082 855 SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
mbed_official 573:ad23fe03a082 856 }
mbed_official 573:ad23fe03a082 857 }
mbed_official 573:ad23fe03a082 858
mbed_official 573:ad23fe03a082 859 /* Wait until RXNE flag is reset */
mbed_official 573:ad23fe03a082 860 if((hspi->RxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_RXNE) == SPI_FLAG_RXNE))
mbed_official 573:ad23fe03a082 861 {
mbed_official 573:ad23fe03a082 862 if(hspi->RxXferCount > 1)
mbed_official 573:ad23fe03a082 863 {
mbed_official 573:ad23fe03a082 864 *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
mbed_official 573:ad23fe03a082 865 hspi->pRxBuffPtr += sizeof(uint16_t);
mbed_official 573:ad23fe03a082 866 hspi->RxXferCount -= 2;
mbed_official 573:ad23fe03a082 867 if(hspi->RxXferCount <= 1)
mbed_official 573:ad23fe03a082 868 {
mbed_official 573:ad23fe03a082 869 /* set fiforxthreshold before to switch on 8 bit data size */
mbed_official 573:ad23fe03a082 870 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
mbed_official 573:ad23fe03a082 871 }
mbed_official 573:ad23fe03a082 872 }
mbed_official 573:ad23fe03a082 873 else
mbed_official 573:ad23fe03a082 874 {
mbed_official 573:ad23fe03a082 875 (*hspi->pRxBuffPtr++) = *(__IO uint8_t *)&hspi->Instance->DR;
mbed_official 573:ad23fe03a082 876 hspi->RxXferCount--;
mbed_official 573:ad23fe03a082 877 }
mbed_official 573:ad23fe03a082 878 }
mbed_official 573:ad23fe03a082 879 if(Timeout != HAL_MAX_DELAY)
mbed_official 573:ad23fe03a082 880 {
mbed_official 573:ad23fe03a082 881 if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout))
mbed_official 573:ad23fe03a082 882 {
mbed_official 573:ad23fe03a082 883 hspi->State = HAL_SPI_STATE_READY;
mbed_official 573:ad23fe03a082 884 __HAL_UNLOCK(hspi);
mbed_official 573:ad23fe03a082 885 return HAL_TIMEOUT;
mbed_official 573:ad23fe03a082 886 }
mbed_official 573:ad23fe03a082 887 }
mbed_official 573:ad23fe03a082 888 }
mbed_official 573:ad23fe03a082 889 }
mbed_official 573:ad23fe03a082 890
mbed_official 573:ad23fe03a082 891 /* Read CRC from DR to close CRC calculation process */
mbed_official 573:ad23fe03a082 892 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official 573:ad23fe03a082 893 {
mbed_official 573:ad23fe03a082 894 /* Wait until TXE flag */
mbed_official 573:ad23fe03a082 895 if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
mbed_official 573:ad23fe03a082 896 {
mbed_official 573:ad23fe03a082 897 /* Error on the CRC reception */
mbed_official 573:ad23fe03a082 898 hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
mbed_official 573:ad23fe03a082 899 }
mbed_official 573:ad23fe03a082 900
mbed_official 573:ad23fe03a082 901 if(hspi->Init.DataSize == SPI_DATASIZE_16BIT)
mbed_official 573:ad23fe03a082 902 {
mbed_official 573:ad23fe03a082 903 tmpreg = hspi->Instance->DR;
mbed_official 573:ad23fe03a082 904 UNUSED(tmpreg); /* To avoid GCC warning */
mbed_official 573:ad23fe03a082 905 }
mbed_official 573:ad23fe03a082 906 else
mbed_official 573:ad23fe03a082 907 {
mbed_official 573:ad23fe03a082 908 tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
mbed_official 573:ad23fe03a082 909 UNUSED(tmpreg); /* To avoid GCC warning */
mbed_official 573:ad23fe03a082 910
mbed_official 573:ad23fe03a082 911 if(hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
mbed_official 573:ad23fe03a082 912 {
mbed_official 573:ad23fe03a082 913 if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
mbed_official 573:ad23fe03a082 914 {
mbed_official 573:ad23fe03a082 915 /* Error on the CRC reception */
mbed_official 573:ad23fe03a082 916 hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
mbed_official 573:ad23fe03a082 917 }
mbed_official 573:ad23fe03a082 918 tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
mbed_official 573:ad23fe03a082 919 UNUSED(tmpreg); /* To avoid GCC warning */
mbed_official 573:ad23fe03a082 920 }
mbed_official 573:ad23fe03a082 921 }
mbed_official 573:ad23fe03a082 922 }
mbed_official 573:ad23fe03a082 923
mbed_official 573:ad23fe03a082 924 /* Check the end of the transaction */
mbed_official 573:ad23fe03a082 925 if(SPI_EndRxTxTransaction(hspi,Timeout) != HAL_OK)
mbed_official 573:ad23fe03a082 926 {
mbed_official 573:ad23fe03a082 927 return HAL_TIMEOUT;
mbed_official 573:ad23fe03a082 928 }
mbed_official 573:ad23fe03a082 929
mbed_official 573:ad23fe03a082 930 hspi->State = HAL_SPI_STATE_READY;
mbed_official 573:ad23fe03a082 931
mbed_official 573:ad23fe03a082 932 /* Check if CRC error occurred */
mbed_official 573:ad23fe03a082 933 if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
mbed_official 573:ad23fe03a082 934 {
mbed_official 573:ad23fe03a082 935 hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
mbed_official 573:ad23fe03a082 936 /* Clear CRC Flag */
mbed_official 573:ad23fe03a082 937 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
mbed_official 573:ad23fe03a082 938
mbed_official 573:ad23fe03a082 939 /* Process Unlocked */
mbed_official 573:ad23fe03a082 940 __HAL_UNLOCK(hspi);
mbed_official 573:ad23fe03a082 941
mbed_official 573:ad23fe03a082 942 return HAL_ERROR;
mbed_official 573:ad23fe03a082 943 }
mbed_official 573:ad23fe03a082 944
mbed_official 573:ad23fe03a082 945 /* Process Unlocked */
mbed_official 573:ad23fe03a082 946 __HAL_UNLOCK(hspi);
mbed_official 573:ad23fe03a082 947
mbed_official 573:ad23fe03a082 948 if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
mbed_official 573:ad23fe03a082 949 {
mbed_official 573:ad23fe03a082 950 return HAL_ERROR;
mbed_official 573:ad23fe03a082 951 }
mbed_official 573:ad23fe03a082 952 else
mbed_official 573:ad23fe03a082 953 {
mbed_official 573:ad23fe03a082 954 return HAL_OK;
mbed_official 573:ad23fe03a082 955 }
mbed_official 573:ad23fe03a082 956 }
mbed_official 573:ad23fe03a082 957
mbed_official 573:ad23fe03a082 958 /**
mbed_official 573:ad23fe03a082 959 * @brief Transmit an amount of data in no-blocking mode with Interrupt
mbed_official 573:ad23fe03a082 960 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 573:ad23fe03a082 961 * the configuration information for SPI module.
mbed_official 573:ad23fe03a082 962 * @param pData: pointer to data buffer
mbed_official 573:ad23fe03a082 963 * @param Size: amount of data to be sent
mbed_official 573:ad23fe03a082 964 * @retval HAL status
mbed_official 573:ad23fe03a082 965 */
mbed_official 573:ad23fe03a082 966 HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
mbed_official 573:ad23fe03a082 967 {
mbed_official 573:ad23fe03a082 968 assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
mbed_official 573:ad23fe03a082 969
mbed_official 573:ad23fe03a082 970 if(hspi->State == HAL_SPI_STATE_READY)
mbed_official 573:ad23fe03a082 971 {
mbed_official 573:ad23fe03a082 972 if((pData == NULL) || (Size == 0))
mbed_official 573:ad23fe03a082 973 {
mbed_official 573:ad23fe03a082 974 return HAL_ERROR;
mbed_official 573:ad23fe03a082 975 }
mbed_official 573:ad23fe03a082 976
mbed_official 573:ad23fe03a082 977 /* Process Locked */
mbed_official 573:ad23fe03a082 978 __HAL_LOCK(hspi);
mbed_official 573:ad23fe03a082 979
mbed_official 573:ad23fe03a082 980 hspi->State = HAL_SPI_STATE_BUSY_TX;
mbed_official 573:ad23fe03a082 981 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official 573:ad23fe03a082 982 hspi->pTxBuffPtr = pData;
mbed_official 573:ad23fe03a082 983 hspi->TxXferSize = Size;
mbed_official 573:ad23fe03a082 984 hspi->TxXferCount = Size;
mbed_official 573:ad23fe03a082 985 hspi->pRxBuffPtr = NULL;
mbed_official 573:ad23fe03a082 986 hspi->RxXferSize = 0;
mbed_official 573:ad23fe03a082 987 hspi->RxXferCount = 0;
mbed_official 573:ad23fe03a082 988
mbed_official 573:ad23fe03a082 989 /* Set the function for IT treatement */
mbed_official 573:ad23fe03a082 990 if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
mbed_official 573:ad23fe03a082 991 {
mbed_official 573:ad23fe03a082 992 hspi->RxISR = NULL;
mbed_official 573:ad23fe03a082 993 hspi->TxISR = SPI_TxISR_16BIT;
mbed_official 573:ad23fe03a082 994 }
mbed_official 573:ad23fe03a082 995 else
mbed_official 573:ad23fe03a082 996 {
mbed_official 573:ad23fe03a082 997 hspi->RxISR = NULL;
mbed_official 573:ad23fe03a082 998 hspi->TxISR = SPI_TxISR_8BIT;
mbed_official 573:ad23fe03a082 999 }
mbed_official 573:ad23fe03a082 1000
mbed_official 573:ad23fe03a082 1001 /* Configure communication direction : 1Line */
mbed_official 573:ad23fe03a082 1002 if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
mbed_official 573:ad23fe03a082 1003 {
mbed_official 573:ad23fe03a082 1004 SPI_1LINE_TX(hspi);
mbed_official 573:ad23fe03a082 1005 }
mbed_official 573:ad23fe03a082 1006
mbed_official 573:ad23fe03a082 1007 /* Reset CRC Calculation */
mbed_official 573:ad23fe03a082 1008 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official 573:ad23fe03a082 1009 {
mbed_official 573:ad23fe03a082 1010 SPI_RESET_CRC(hspi);
mbed_official 573:ad23fe03a082 1011 }
mbed_official 573:ad23fe03a082 1012
mbed_official 573:ad23fe03a082 1013 /* Enable TXE and ERR interrupt */
mbed_official 573:ad23fe03a082 1014 __HAL_SPI_ENABLE_IT(hspi,(SPI_IT_TXE));
mbed_official 573:ad23fe03a082 1015
mbed_official 573:ad23fe03a082 1016 /* Process Unlocked */
mbed_official 573:ad23fe03a082 1017 __HAL_UNLOCK(hspi);
mbed_official 573:ad23fe03a082 1018
mbed_official 573:ad23fe03a082 1019 /* Note : The SPI must be enabled after unlocking current process
mbed_official 573:ad23fe03a082 1020 to avoid the risk of SPI interrupt handle execution before current
mbed_official 573:ad23fe03a082 1021 process unlock */
mbed_official 573:ad23fe03a082 1022
mbed_official 573:ad23fe03a082 1023 /* Check if the SPI is already enabled */
mbed_official 573:ad23fe03a082 1024 if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official 573:ad23fe03a082 1025 {
mbed_official 573:ad23fe03a082 1026 /* Enable SPI peripheral */
mbed_official 573:ad23fe03a082 1027 __HAL_SPI_ENABLE(hspi);
mbed_official 573:ad23fe03a082 1028 }
mbed_official 573:ad23fe03a082 1029
mbed_official 573:ad23fe03a082 1030 return HAL_OK;
mbed_official 573:ad23fe03a082 1031 }
mbed_official 573:ad23fe03a082 1032 else
mbed_official 573:ad23fe03a082 1033 {
mbed_official 573:ad23fe03a082 1034 return HAL_BUSY;
mbed_official 573:ad23fe03a082 1035 }
mbed_official 573:ad23fe03a082 1036 }
mbed_official 573:ad23fe03a082 1037
mbed_official 573:ad23fe03a082 1038 /**
mbed_official 573:ad23fe03a082 1039 * @brief Receive an amount of data in no-blocking mode with Interrupt
mbed_official 573:ad23fe03a082 1040 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 573:ad23fe03a082 1041 * the configuration information for SPI module.
mbed_official 573:ad23fe03a082 1042 * @param pData: pointer to data buffer
mbed_official 573:ad23fe03a082 1043 * @param Size: amount of data to be sent
mbed_official 573:ad23fe03a082 1044 * @retval HAL status
mbed_official 573:ad23fe03a082 1045 */
mbed_official 573:ad23fe03a082 1046 HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
mbed_official 573:ad23fe03a082 1047 {
mbed_official 573:ad23fe03a082 1048 if(hspi->State == HAL_SPI_STATE_READY)
mbed_official 573:ad23fe03a082 1049 {
mbed_official 573:ad23fe03a082 1050 if((pData == NULL) || (Size == 0))
mbed_official 573:ad23fe03a082 1051 {
mbed_official 573:ad23fe03a082 1052 return HAL_ERROR;
mbed_official 573:ad23fe03a082 1053 }
mbed_official 573:ad23fe03a082 1054
mbed_official 573:ad23fe03a082 1055 /* Process Locked */
mbed_official 573:ad23fe03a082 1056 __HAL_LOCK(hspi);
mbed_official 573:ad23fe03a082 1057
mbed_official 573:ad23fe03a082 1058 /* Configure communication */
mbed_official 573:ad23fe03a082 1059 hspi->State = HAL_SPI_STATE_BUSY_RX;
mbed_official 573:ad23fe03a082 1060 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official 573:ad23fe03a082 1061 hspi->pRxBuffPtr = pData;
mbed_official 573:ad23fe03a082 1062 hspi->RxXferSize = Size;
mbed_official 573:ad23fe03a082 1063 hspi->RxXferCount = Size;
mbed_official 573:ad23fe03a082 1064 hspi->pTxBuffPtr = NULL;
mbed_official 573:ad23fe03a082 1065 hspi->TxXferSize = 0;
mbed_official 573:ad23fe03a082 1066 hspi->TxXferCount = 0;
mbed_official 573:ad23fe03a082 1067
mbed_official 573:ad23fe03a082 1068 if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
mbed_official 573:ad23fe03a082 1069 {
mbed_official 573:ad23fe03a082 1070 /* Process Unlocked */
mbed_official 573:ad23fe03a082 1071 __HAL_UNLOCK(hspi);
mbed_official 573:ad23fe03a082 1072 /* the receive process is not supported in 2Lines direction master mode */
mbed_official 573:ad23fe03a082 1073 /* in this we call the transmitReceive process */
mbed_official 573:ad23fe03a082 1074 return HAL_SPI_TransmitReceive_IT(hspi,pData,pData,Size);
mbed_official 573:ad23fe03a082 1075 }
mbed_official 573:ad23fe03a082 1076
mbed_official 573:ad23fe03a082 1077 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official 573:ad23fe03a082 1078 {
mbed_official 573:ad23fe03a082 1079 hspi->CRCSize = 1;
mbed_official 573:ad23fe03a082 1080 if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
mbed_official 573:ad23fe03a082 1081 {
mbed_official 573:ad23fe03a082 1082 hspi->CRCSize = 2;
mbed_official 573:ad23fe03a082 1083 }
mbed_official 573:ad23fe03a082 1084 }
mbed_official 573:ad23fe03a082 1085 else
mbed_official 573:ad23fe03a082 1086 {
mbed_official 573:ad23fe03a082 1087 hspi->CRCSize = 0;
mbed_official 573:ad23fe03a082 1088 }
mbed_official 573:ad23fe03a082 1089
mbed_official 573:ad23fe03a082 1090 /* check the data size to adapt Rx threshold and the set the function for IT treatment */
mbed_official 573:ad23fe03a082 1091 if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
mbed_official 573:ad23fe03a082 1092 {
mbed_official 573:ad23fe03a082 1093 /* set fiforxthreshold according the reception data length: 16 bit */
mbed_official 573:ad23fe03a082 1094 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
mbed_official 573:ad23fe03a082 1095 hspi->RxISR = SPI_RxISR_16BIT;
mbed_official 573:ad23fe03a082 1096 hspi->TxISR = NULL;
mbed_official 573:ad23fe03a082 1097 }
mbed_official 573:ad23fe03a082 1098 else
mbed_official 573:ad23fe03a082 1099 {
mbed_official 573:ad23fe03a082 1100 /* set fiforxthreshold according the reception data length: 8 bit */
mbed_official 573:ad23fe03a082 1101 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
mbed_official 573:ad23fe03a082 1102 hspi->RxISR = SPI_RxISR_8BIT;
mbed_official 573:ad23fe03a082 1103 hspi->TxISR = NULL;
mbed_official 573:ad23fe03a082 1104 }
mbed_official 573:ad23fe03a082 1105
mbed_official 573:ad23fe03a082 1106 /* Configure communication direction : 1Line */
mbed_official 573:ad23fe03a082 1107 if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
mbed_official 573:ad23fe03a082 1108 {
mbed_official 573:ad23fe03a082 1109 SPI_1LINE_RX(hspi);
mbed_official 573:ad23fe03a082 1110 }
mbed_official 573:ad23fe03a082 1111
mbed_official 573:ad23fe03a082 1112 /* Reset CRC Calculation */
mbed_official 573:ad23fe03a082 1113 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official 573:ad23fe03a082 1114 {
mbed_official 573:ad23fe03a082 1115 SPI_RESET_CRC(hspi);
mbed_official 573:ad23fe03a082 1116 }
mbed_official 573:ad23fe03a082 1117
mbed_official 573:ad23fe03a082 1118 /* Enable TXE and ERR interrupt */
mbed_official 573:ad23fe03a082 1119 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
mbed_official 573:ad23fe03a082 1120
mbed_official 573:ad23fe03a082 1121 /* Process Unlocked */
mbed_official 573:ad23fe03a082 1122 __HAL_UNLOCK(hspi);
mbed_official 573:ad23fe03a082 1123
mbed_official 573:ad23fe03a082 1124 /* Note : The SPI must be enabled after unlocking current process
mbed_official 573:ad23fe03a082 1125 to avoid the risk of SPI interrupt handle execution before current
mbed_official 573:ad23fe03a082 1126 process unlock */
mbed_official 573:ad23fe03a082 1127
mbed_official 573:ad23fe03a082 1128 /* Check if the SPI is already enabled */
mbed_official 573:ad23fe03a082 1129 if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official 573:ad23fe03a082 1130 {
mbed_official 573:ad23fe03a082 1131 /* Enable SPI peripheral */
mbed_official 573:ad23fe03a082 1132 __HAL_SPI_ENABLE(hspi);
mbed_official 573:ad23fe03a082 1133 }
mbed_official 573:ad23fe03a082 1134
mbed_official 573:ad23fe03a082 1135 return HAL_OK;
mbed_official 573:ad23fe03a082 1136 }
mbed_official 573:ad23fe03a082 1137 else
mbed_official 573:ad23fe03a082 1138 {
mbed_official 573:ad23fe03a082 1139 return HAL_BUSY;
mbed_official 573:ad23fe03a082 1140 }
mbed_official 573:ad23fe03a082 1141 }
mbed_official 573:ad23fe03a082 1142
mbed_official 573:ad23fe03a082 1143 /**
mbed_official 573:ad23fe03a082 1144 * @brief Transmit and Receive an amount of data in no-blocking mode with Interrupt
mbed_official 573:ad23fe03a082 1145 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 573:ad23fe03a082 1146 * the configuration information for SPI module.
mbed_official 573:ad23fe03a082 1147 * @param pTxData: pointer to transmission data buffer
mbed_official 573:ad23fe03a082 1148 * @param pRxData: pointer to reception data buffer
mbed_official 573:ad23fe03a082 1149 * @param Size: amount of data to be sent and received
mbed_official 573:ad23fe03a082 1150 * @retval HAL status
mbed_official 573:ad23fe03a082 1151 */
mbed_official 573:ad23fe03a082 1152 HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
mbed_official 573:ad23fe03a082 1153 {
mbed_official 573:ad23fe03a082 1154 assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
mbed_official 573:ad23fe03a082 1155
mbed_official 573:ad23fe03a082 1156 if((hspi->State == HAL_SPI_STATE_READY) || \
mbed_official 573:ad23fe03a082 1157 ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX)))
mbed_official 573:ad23fe03a082 1158 {
mbed_official 573:ad23fe03a082 1159 if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0))
mbed_official 573:ad23fe03a082 1160 {
mbed_official 573:ad23fe03a082 1161 return HAL_ERROR;
mbed_official 573:ad23fe03a082 1162 }
mbed_official 573:ad23fe03a082 1163
mbed_official 573:ad23fe03a082 1164 /* Process locked */
mbed_official 573:ad23fe03a082 1165 __HAL_LOCK(hspi);
mbed_official 573:ad23fe03a082 1166
mbed_official 573:ad23fe03a082 1167 hspi->CRCSize = 0;
mbed_official 573:ad23fe03a082 1168 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official 573:ad23fe03a082 1169 {
mbed_official 573:ad23fe03a082 1170 hspi->CRCSize = 1;
mbed_official 573:ad23fe03a082 1171 if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
mbed_official 573:ad23fe03a082 1172 {
mbed_official 573:ad23fe03a082 1173 hspi->CRCSize = 2;
mbed_official 573:ad23fe03a082 1174 }
mbed_official 573:ad23fe03a082 1175 }
mbed_official 573:ad23fe03a082 1176
mbed_official 573:ad23fe03a082 1177 if(hspi->State != HAL_SPI_STATE_BUSY_RX)
mbed_official 573:ad23fe03a082 1178 {
mbed_official 573:ad23fe03a082 1179 hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
mbed_official 573:ad23fe03a082 1180 }
mbed_official 573:ad23fe03a082 1181
mbed_official 573:ad23fe03a082 1182 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official 573:ad23fe03a082 1183 hspi->pTxBuffPtr = pTxData;
mbed_official 573:ad23fe03a082 1184 hspi->TxXferSize = Size;
mbed_official 573:ad23fe03a082 1185 hspi->TxXferCount = Size;
mbed_official 573:ad23fe03a082 1186 hspi->pRxBuffPtr = pRxData;
mbed_official 573:ad23fe03a082 1187 hspi->RxXferSize = Size;
mbed_official 573:ad23fe03a082 1188 hspi->RxXferCount = Size;
mbed_official 573:ad23fe03a082 1189
mbed_official 573:ad23fe03a082 1190 /* Set the function for IT treatement */
mbed_official 573:ad23fe03a082 1191 if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
mbed_official 573:ad23fe03a082 1192 {
mbed_official 573:ad23fe03a082 1193 hspi->RxISR = SPI_2linesRxISR_16BIT;
mbed_official 573:ad23fe03a082 1194 hspi->TxISR = SPI_2linesTxISR_16BIT;
mbed_official 573:ad23fe03a082 1195 }
mbed_official 573:ad23fe03a082 1196 else
mbed_official 573:ad23fe03a082 1197 {
mbed_official 573:ad23fe03a082 1198 hspi->RxISR = SPI_2linesRxISR_8BIT;
mbed_official 573:ad23fe03a082 1199 hspi->TxISR = SPI_2linesTxISR_8BIT;
mbed_official 573:ad23fe03a082 1200 }
mbed_official 573:ad23fe03a082 1201
mbed_official 573:ad23fe03a082 1202 /* Reset CRC Calculation */
mbed_official 573:ad23fe03a082 1203 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official 573:ad23fe03a082 1204 {
mbed_official 573:ad23fe03a082 1205 SPI_RESET_CRC(hspi);
mbed_official 573:ad23fe03a082 1206 }
mbed_official 573:ad23fe03a082 1207
mbed_official 573:ad23fe03a082 1208 /* check if packing mode is enabled and if there is more than 2 data to receive */
mbed_official 573:ad23fe03a082 1209 if((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (hspi->RxXferCount >= 2))
mbed_official 573:ad23fe03a082 1210 {
mbed_official 573:ad23fe03a082 1211 /* set fiforxthreshold according the reception data length: 16 bit */
mbed_official 573:ad23fe03a082 1212 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
mbed_official 573:ad23fe03a082 1213 }
mbed_official 573:ad23fe03a082 1214 else
mbed_official 573:ad23fe03a082 1215 {
mbed_official 573:ad23fe03a082 1216 /* set fiforxthreshold according the reception data length: 8 bit */
mbed_official 573:ad23fe03a082 1217 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
mbed_official 573:ad23fe03a082 1218 }
mbed_official 573:ad23fe03a082 1219
mbed_official 573:ad23fe03a082 1220 /* Enable TXE, RXNE and ERR interrupt */
mbed_official 573:ad23fe03a082 1221 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
mbed_official 573:ad23fe03a082 1222
mbed_official 573:ad23fe03a082 1223 /* Process Unlocked */
mbed_official 573:ad23fe03a082 1224 __HAL_UNLOCK(hspi);
mbed_official 573:ad23fe03a082 1225
mbed_official 573:ad23fe03a082 1226 /* Check if the SPI is already enabled */
mbed_official 573:ad23fe03a082 1227 if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official 573:ad23fe03a082 1228 {
mbed_official 573:ad23fe03a082 1229 /* Enable SPI peripheral */
mbed_official 573:ad23fe03a082 1230 __HAL_SPI_ENABLE(hspi);
mbed_official 573:ad23fe03a082 1231 }
mbed_official 573:ad23fe03a082 1232
mbed_official 573:ad23fe03a082 1233 return HAL_OK;
mbed_official 573:ad23fe03a082 1234 }
mbed_official 573:ad23fe03a082 1235 else
mbed_official 573:ad23fe03a082 1236 {
mbed_official 573:ad23fe03a082 1237 return HAL_BUSY;
mbed_official 573:ad23fe03a082 1238 }
mbed_official 573:ad23fe03a082 1239 }
mbed_official 573:ad23fe03a082 1240
mbed_official 573:ad23fe03a082 1241 /**
mbed_official 573:ad23fe03a082 1242 * @brief Transmit an amount of data in no-blocking mode with DMA
mbed_official 573:ad23fe03a082 1243 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 573:ad23fe03a082 1244 * the configuration information for SPI module.
mbed_official 573:ad23fe03a082 1245 * @param pData: pointer to data buffer
mbed_official 573:ad23fe03a082 1246 * @param Size: amount of data to be sent
mbed_official 573:ad23fe03a082 1247 * @retval HAL status
mbed_official 573:ad23fe03a082 1248 */
mbed_official 573:ad23fe03a082 1249 HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
mbed_official 573:ad23fe03a082 1250 {
mbed_official 573:ad23fe03a082 1251 assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
mbed_official 573:ad23fe03a082 1252
mbed_official 573:ad23fe03a082 1253 if(hspi->State != HAL_SPI_STATE_READY)
mbed_official 573:ad23fe03a082 1254 {
mbed_official 573:ad23fe03a082 1255 return HAL_BUSY;
mbed_official 573:ad23fe03a082 1256 }
mbed_official 573:ad23fe03a082 1257
mbed_official 573:ad23fe03a082 1258 if((pData == NULL) || (Size == 0))
mbed_official 573:ad23fe03a082 1259 {
mbed_official 573:ad23fe03a082 1260 return HAL_ERROR;
mbed_official 573:ad23fe03a082 1261 }
mbed_official 573:ad23fe03a082 1262
mbed_official 573:ad23fe03a082 1263 /* Process Locked */
mbed_official 573:ad23fe03a082 1264 __HAL_LOCK(hspi);
mbed_official 573:ad23fe03a082 1265
mbed_official 573:ad23fe03a082 1266 hspi->State = HAL_SPI_STATE_BUSY_TX;
mbed_official 573:ad23fe03a082 1267 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official 573:ad23fe03a082 1268 hspi->pTxBuffPtr = pData;
mbed_official 573:ad23fe03a082 1269 hspi->TxXferSize = Size;
mbed_official 573:ad23fe03a082 1270 hspi->TxXferCount = Size;
mbed_official 573:ad23fe03a082 1271 hspi->pRxBuffPtr = (uint8_t *)NULL;
mbed_official 573:ad23fe03a082 1272 hspi->RxXferSize = 0;
mbed_official 573:ad23fe03a082 1273 hspi->RxXferCount = 0;
mbed_official 573:ad23fe03a082 1274
mbed_official 573:ad23fe03a082 1275 /* Configure communication direction : 1Line */
mbed_official 573:ad23fe03a082 1276 if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
mbed_official 573:ad23fe03a082 1277 {
mbed_official 573:ad23fe03a082 1278 SPI_1LINE_TX(hspi);
mbed_official 573:ad23fe03a082 1279 }
mbed_official 573:ad23fe03a082 1280
mbed_official 573:ad23fe03a082 1281 /* Reset CRC Calculation */
mbed_official 573:ad23fe03a082 1282 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official 573:ad23fe03a082 1283 {
mbed_official 573:ad23fe03a082 1284 SPI_RESET_CRC(hspi);
mbed_official 573:ad23fe03a082 1285 }
mbed_official 573:ad23fe03a082 1286
mbed_official 573:ad23fe03a082 1287 /* Set the SPI TxDMA Half transfer complete callback */
mbed_official 573:ad23fe03a082 1288 hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt;
mbed_official 573:ad23fe03a082 1289
mbed_official 573:ad23fe03a082 1290 /* Set the SPI TxDMA transfer complete callback */
mbed_official 573:ad23fe03a082 1291 hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt;
mbed_official 573:ad23fe03a082 1292
mbed_official 573:ad23fe03a082 1293 /* Set the DMA error callback */
mbed_official 573:ad23fe03a082 1294 hspi->hdmatx->XferErrorCallback = SPI_DMAError;
mbed_official 573:ad23fe03a082 1295
mbed_official 573:ad23fe03a082 1296 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
mbed_official 573:ad23fe03a082 1297 /* packing mode is enabled only if the DMA setting is HALWORD */
mbed_official 573:ad23fe03a082 1298 if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))
mbed_official 573:ad23fe03a082 1299 {
mbed_official 573:ad23fe03a082 1300 /* Check the even/odd of the data size + crc if enabled */
mbed_official 573:ad23fe03a082 1301 if((hspi->TxXferCount & 0x1) == 0)
mbed_official 573:ad23fe03a082 1302 {
mbed_official 573:ad23fe03a082 1303 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
mbed_official 573:ad23fe03a082 1304 hspi->TxXferCount = (hspi->TxXferCount >> 1);
mbed_official 573:ad23fe03a082 1305 }
mbed_official 573:ad23fe03a082 1306 else
mbed_official 573:ad23fe03a082 1307 {
mbed_official 573:ad23fe03a082 1308 SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
mbed_official 573:ad23fe03a082 1309 hspi->TxXferCount = (hspi->TxXferCount >> 1) + 1;
mbed_official 573:ad23fe03a082 1310 }
mbed_official 573:ad23fe03a082 1311 }
mbed_official 573:ad23fe03a082 1312
mbed_official 573:ad23fe03a082 1313 /* Enable the Tx DMA channel */
mbed_official 573:ad23fe03a082 1314 HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
mbed_official 573:ad23fe03a082 1315
mbed_official 573:ad23fe03a082 1316 /* Check if the SPI is already enabled */
mbed_official 573:ad23fe03a082 1317 if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official 573:ad23fe03a082 1318 {
mbed_official 573:ad23fe03a082 1319 /* Enable SPI peripheral */
mbed_official 573:ad23fe03a082 1320 __HAL_SPI_ENABLE(hspi);
mbed_official 573:ad23fe03a082 1321 }
mbed_official 573:ad23fe03a082 1322
mbed_official 573:ad23fe03a082 1323 /* Enable Tx DMA Request */
mbed_official 573:ad23fe03a082 1324 hspi->Instance->CR2 |= SPI_CR2_TXDMAEN;
mbed_official 573:ad23fe03a082 1325
mbed_official 573:ad23fe03a082 1326 /* Process Unlocked */
mbed_official 573:ad23fe03a082 1327 __HAL_UNLOCK(hspi);
mbed_official 573:ad23fe03a082 1328
mbed_official 573:ad23fe03a082 1329 return HAL_OK;
mbed_official 573:ad23fe03a082 1330 }
mbed_official 573:ad23fe03a082 1331
mbed_official 573:ad23fe03a082 1332 /**
mbed_official 573:ad23fe03a082 1333 * @brief Receive an amount of data in no-blocking mode with DMA
mbed_official 573:ad23fe03a082 1334 * @param hspi: SPI handle
mbed_official 573:ad23fe03a082 1335 * @param pData: pointer to data buffer
mbed_official 573:ad23fe03a082 1336 * @param Size: amount of data to be sent
mbed_official 573:ad23fe03a082 1337 * @retval HAL status
mbed_official 573:ad23fe03a082 1338 */
mbed_official 573:ad23fe03a082 1339 HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
mbed_official 573:ad23fe03a082 1340 {
mbed_official 573:ad23fe03a082 1341 if(hspi->State != HAL_SPI_STATE_READY)
mbed_official 573:ad23fe03a082 1342 {
mbed_official 573:ad23fe03a082 1343 return HAL_BUSY;
mbed_official 573:ad23fe03a082 1344 }
mbed_official 573:ad23fe03a082 1345
mbed_official 573:ad23fe03a082 1346 if((pData == NULL) || (Size == 0))
mbed_official 573:ad23fe03a082 1347 {
mbed_official 573:ad23fe03a082 1348 return HAL_ERROR;
mbed_official 573:ad23fe03a082 1349 }
mbed_official 573:ad23fe03a082 1350
mbed_official 573:ad23fe03a082 1351 /* Process Locked */
mbed_official 573:ad23fe03a082 1352 __HAL_LOCK(hspi);
mbed_official 573:ad23fe03a082 1353
mbed_official 573:ad23fe03a082 1354 hspi->State = HAL_SPI_STATE_BUSY_RX;
mbed_official 573:ad23fe03a082 1355 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official 573:ad23fe03a082 1356 hspi->pRxBuffPtr = pData;
mbed_official 573:ad23fe03a082 1357 hspi->RxXferSize = Size;
mbed_official 573:ad23fe03a082 1358 hspi->RxXferCount = Size;
mbed_official 573:ad23fe03a082 1359 hspi->pTxBuffPtr = (uint8_t *)NULL;
mbed_official 573:ad23fe03a082 1360 hspi->TxXferSize = 0;
mbed_official 573:ad23fe03a082 1361 hspi->TxXferCount = 0;
mbed_official 573:ad23fe03a082 1362
mbed_official 573:ad23fe03a082 1363 if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
mbed_official 573:ad23fe03a082 1364 {
mbed_official 573:ad23fe03a082 1365 /* Process Unlocked */
mbed_official 573:ad23fe03a082 1366 __HAL_UNLOCK(hspi);
mbed_official 573:ad23fe03a082 1367 /* the receive process is not supported in 2Lines direction master mode */
mbed_official 573:ad23fe03a082 1368 /* in this case we call the transmitReceive process */
mbed_official 573:ad23fe03a082 1369 return HAL_SPI_TransmitReceive_DMA(hspi,pData,pData,Size);
mbed_official 573:ad23fe03a082 1370 }
mbed_official 573:ad23fe03a082 1371
mbed_official 573:ad23fe03a082 1372 /* Configure communication direction : 1Line */
mbed_official 573:ad23fe03a082 1373 if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
mbed_official 573:ad23fe03a082 1374 {
mbed_official 573:ad23fe03a082 1375 SPI_1LINE_RX(hspi);
mbed_official 573:ad23fe03a082 1376 }
mbed_official 573:ad23fe03a082 1377
mbed_official 573:ad23fe03a082 1378 /* Reset CRC Calculation */
mbed_official 573:ad23fe03a082 1379 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official 573:ad23fe03a082 1380 {
mbed_official 573:ad23fe03a082 1381 SPI_RESET_CRC(hspi);
mbed_official 573:ad23fe03a082 1382 }
mbed_official 573:ad23fe03a082 1383
mbed_official 573:ad23fe03a082 1384 /* packing mode management is enabled by the DMA settings */
mbed_official 573:ad23fe03a082 1385 if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))
mbed_official 573:ad23fe03a082 1386 {
mbed_official 573:ad23fe03a082 1387 /* Process Locked */
mbed_official 573:ad23fe03a082 1388 __HAL_UNLOCK(hspi);
mbed_official 573:ad23fe03a082 1389 /* Restriction the DMA data received is not allowed in this mode */
mbed_official 573:ad23fe03a082 1390 return HAL_ERROR;
mbed_official 573:ad23fe03a082 1391 }
mbed_official 573:ad23fe03a082 1392
mbed_official 573:ad23fe03a082 1393 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
mbed_official 573:ad23fe03a082 1394 if( hspi->Init.DataSize > SPI_DATASIZE_8BIT)
mbed_official 573:ad23fe03a082 1395 {
mbed_official 573:ad23fe03a082 1396 /* set fiforxthreshold according the reception data length: 16bit */
mbed_official 573:ad23fe03a082 1397 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
mbed_official 573:ad23fe03a082 1398 }
mbed_official 573:ad23fe03a082 1399 else
mbed_official 573:ad23fe03a082 1400 {
mbed_official 573:ad23fe03a082 1401 /* set fiforxthreshold according the reception data length: 8bit */
mbed_official 573:ad23fe03a082 1402 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
mbed_official 573:ad23fe03a082 1403 }
mbed_official 573:ad23fe03a082 1404
mbed_official 573:ad23fe03a082 1405 /* Set the SPI RxDMA Half transfer complete callback */
mbed_official 573:ad23fe03a082 1406 hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
mbed_official 573:ad23fe03a082 1407
mbed_official 573:ad23fe03a082 1408 /* Set the SPI Rx DMA transfer complete callback */
mbed_official 573:ad23fe03a082 1409 hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
mbed_official 573:ad23fe03a082 1410
mbed_official 573:ad23fe03a082 1411 /* Set the DMA error callback */
mbed_official 573:ad23fe03a082 1412 hspi->hdmarx->XferErrorCallback = SPI_DMAError;
mbed_official 573:ad23fe03a082 1413
mbed_official 573:ad23fe03a082 1414 /* Enable Rx DMA Request */
mbed_official 573:ad23fe03a082 1415 hspi->Instance->CR2 |= SPI_CR2_RXDMAEN;
mbed_official 573:ad23fe03a082 1416
mbed_official 573:ad23fe03a082 1417 /* Enable the Rx DMA channel */
mbed_official 573:ad23fe03a082 1418 HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
mbed_official 573:ad23fe03a082 1419
mbed_official 573:ad23fe03a082 1420 /* Process Unlocked */
mbed_official 573:ad23fe03a082 1421 __HAL_UNLOCK(hspi);
mbed_official 573:ad23fe03a082 1422
mbed_official 573:ad23fe03a082 1423 /* Check if the SPI is already enabled */
mbed_official 573:ad23fe03a082 1424 if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official 573:ad23fe03a082 1425 {
mbed_official 573:ad23fe03a082 1426 /* Enable SPI peripheral */
mbed_official 573:ad23fe03a082 1427 __HAL_SPI_ENABLE(hspi);
mbed_official 573:ad23fe03a082 1428 }
mbed_official 573:ad23fe03a082 1429
mbed_official 573:ad23fe03a082 1430 return HAL_OK;
mbed_official 573:ad23fe03a082 1431 }
mbed_official 573:ad23fe03a082 1432
mbed_official 573:ad23fe03a082 1433 /**
mbed_official 573:ad23fe03a082 1434 * @brief Transmit and Receive an amount of data in no-blocking mode with DMA
mbed_official 573:ad23fe03a082 1435 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 573:ad23fe03a082 1436 * the configuration information for SPI module.
mbed_official 573:ad23fe03a082 1437 * @param pTxData: pointer to transmission data buffer
mbed_official 573:ad23fe03a082 1438 * @param pRxData: pointer to reception data buffer
mbed_official 573:ad23fe03a082 1439 * @note When the CRC feature is enabled the pRxData Length must be Size + 1
mbed_official 573:ad23fe03a082 1440 * @param Size: amount of data to be sent
mbed_official 573:ad23fe03a082 1441 * @retval HAL status
mbed_official 573:ad23fe03a082 1442 */
mbed_official 573:ad23fe03a082 1443 HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
mbed_official 573:ad23fe03a082 1444 {
mbed_official 573:ad23fe03a082 1445 assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
mbed_official 573:ad23fe03a082 1446
mbed_official 573:ad23fe03a082 1447 if((hspi->State == HAL_SPI_STATE_READY) ||
mbed_official 573:ad23fe03a082 1448 ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX)))
mbed_official 573:ad23fe03a082 1449 {
mbed_official 573:ad23fe03a082 1450 if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0))
mbed_official 573:ad23fe03a082 1451 {
mbed_official 573:ad23fe03a082 1452 return HAL_ERROR;
mbed_official 573:ad23fe03a082 1453 }
mbed_official 573:ad23fe03a082 1454
mbed_official 573:ad23fe03a082 1455 /* Process locked */
mbed_official 573:ad23fe03a082 1456 __HAL_LOCK(hspi);
mbed_official 573:ad23fe03a082 1457
mbed_official 573:ad23fe03a082 1458 /* check if the transmit Receive function is not called by a receive master */
mbed_official 573:ad23fe03a082 1459 if(hspi->State != HAL_SPI_STATE_BUSY_RX)
mbed_official 573:ad23fe03a082 1460 {
mbed_official 573:ad23fe03a082 1461 hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
mbed_official 573:ad23fe03a082 1462 }
mbed_official 573:ad23fe03a082 1463
mbed_official 573:ad23fe03a082 1464 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official 573:ad23fe03a082 1465 hspi->pTxBuffPtr = (uint8_t *)pTxData;
mbed_official 573:ad23fe03a082 1466 hspi->TxXferSize = Size;
mbed_official 573:ad23fe03a082 1467 hspi->TxXferCount = Size;
mbed_official 573:ad23fe03a082 1468 hspi->pRxBuffPtr = (uint8_t *)pRxData;
mbed_official 573:ad23fe03a082 1469 hspi->RxXferSize = Size;
mbed_official 573:ad23fe03a082 1470 hspi->RxXferCount = Size;
mbed_official 573:ad23fe03a082 1471
mbed_official 573:ad23fe03a082 1472 /* Reset CRC Calculation + increase the rxsize */
mbed_official 573:ad23fe03a082 1473 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official 573:ad23fe03a082 1474 {
mbed_official 573:ad23fe03a082 1475 SPI_RESET_CRC(hspi);
mbed_official 573:ad23fe03a082 1476 }
mbed_official 573:ad23fe03a082 1477
mbed_official 573:ad23fe03a082 1478 /* Reset the threshold bit */
mbed_official 573:ad23fe03a082 1479 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
mbed_official 573:ad23fe03a082 1480 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
mbed_official 573:ad23fe03a082 1481
mbed_official 573:ad23fe03a082 1482 /* the packing mode management is enabled by the DMA settings according the spi data size */
mbed_official 573:ad23fe03a082 1483 if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
mbed_official 573:ad23fe03a082 1484 {
mbed_official 573:ad23fe03a082 1485 /* set fiforxthreshold according the reception data length: 16bit */
mbed_official 573:ad23fe03a082 1486 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
mbed_official 573:ad23fe03a082 1487 }
mbed_official 573:ad23fe03a082 1488 else
mbed_official 573:ad23fe03a082 1489 {
mbed_official 573:ad23fe03a082 1490 /* set fiforxthreshold according the reception data length: 8bit */
mbed_official 573:ad23fe03a082 1491 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
mbed_official 573:ad23fe03a082 1492
mbed_official 573:ad23fe03a082 1493 if(hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
mbed_official 573:ad23fe03a082 1494 {
mbed_official 573:ad23fe03a082 1495 if((hspi->TxXferSize & 0x1) == 0x0 )
mbed_official 573:ad23fe03a082 1496 {
mbed_official 573:ad23fe03a082 1497 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
mbed_official 573:ad23fe03a082 1498 hspi->TxXferCount = hspi->TxXferCount >> 1;
mbed_official 573:ad23fe03a082 1499 }
mbed_official 573:ad23fe03a082 1500 else
mbed_official 573:ad23fe03a082 1501 {
mbed_official 573:ad23fe03a082 1502 SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
mbed_official 573:ad23fe03a082 1503 hspi->TxXferCount = (hspi->TxXferCount >> 1) + 1;
mbed_official 573:ad23fe03a082 1504 }
mbed_official 573:ad23fe03a082 1505 }
mbed_official 573:ad23fe03a082 1506
mbed_official 573:ad23fe03a082 1507 if(hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
mbed_official 573:ad23fe03a082 1508 {
mbed_official 573:ad23fe03a082 1509 /* set fiforxthreshold according the reception data length: 16bit */
mbed_official 573:ad23fe03a082 1510 CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
mbed_official 573:ad23fe03a082 1511
mbed_official 573:ad23fe03a082 1512 /* Size must include the CRC length */
mbed_official 573:ad23fe03a082 1513 if((hspi->RxXferCount & 0x1) == 0x0 )
mbed_official 573:ad23fe03a082 1514 {
mbed_official 573:ad23fe03a082 1515 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
mbed_official 573:ad23fe03a082 1516 hspi->RxXferCount = hspi->RxXferCount >> 1;
mbed_official 573:ad23fe03a082 1517 }
mbed_official 573:ad23fe03a082 1518 else
mbed_official 573:ad23fe03a082 1519 {
mbed_official 573:ad23fe03a082 1520 SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
mbed_official 573:ad23fe03a082 1521 hspi->RxXferCount = (hspi->RxXferCount >> 1) + 1;
mbed_official 573:ad23fe03a082 1522 }
mbed_official 573:ad23fe03a082 1523 }
mbed_official 573:ad23fe03a082 1524 }
mbed_official 573:ad23fe03a082 1525
mbed_official 573:ad23fe03a082 1526 /* Set the SPI Rx DMA transfer complete callback because the last generated transfer request is
mbed_official 573:ad23fe03a082 1527 the reception request (RXNE) */
mbed_official 573:ad23fe03a082 1528 if(hspi->State == HAL_SPI_STATE_BUSY_RX)
mbed_official 573:ad23fe03a082 1529 {
mbed_official 573:ad23fe03a082 1530 hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
mbed_official 573:ad23fe03a082 1531 hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
mbed_official 573:ad23fe03a082 1532 }
mbed_official 573:ad23fe03a082 1533 else
mbed_official 573:ad23fe03a082 1534 {
mbed_official 573:ad23fe03a082 1535 hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;
mbed_official 573:ad23fe03a082 1536 hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt;
mbed_official 573:ad23fe03a082 1537 }
mbed_official 573:ad23fe03a082 1538 /* Set the DMA error callback */
mbed_official 573:ad23fe03a082 1539 hspi->hdmarx->XferErrorCallback = SPI_DMAError;
mbed_official 573:ad23fe03a082 1540
mbed_official 573:ad23fe03a082 1541 /* Enable Rx DMA Request */
mbed_official 573:ad23fe03a082 1542 hspi->Instance->CR2 |= SPI_CR2_RXDMAEN;
mbed_official 573:ad23fe03a082 1543
mbed_official 573:ad23fe03a082 1544 /* Enable the Rx DMA channel */
mbed_official 573:ad23fe03a082 1545 HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t) hspi->pRxBuffPtr, hspi->RxXferCount);
mbed_official 573:ad23fe03a082 1546
mbed_official 573:ad23fe03a082 1547 /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing
mbed_official 573:ad23fe03a082 1548 is performed in DMA reception complete callback */
mbed_official 573:ad23fe03a082 1549 hspi->hdmatx->XferHalfCpltCallback = NULL;
mbed_official 573:ad23fe03a082 1550 hspi->hdmatx->XferCpltCallback = NULL;
mbed_official 573:ad23fe03a082 1551
mbed_official 573:ad23fe03a082 1552 if(hspi->State == HAL_SPI_STATE_BUSY_TX_RX)
mbed_official 573:ad23fe03a082 1553 {
mbed_official 573:ad23fe03a082 1554 /* Set the DMA error callback */
mbed_official 573:ad23fe03a082 1555 hspi->hdmatx->XferErrorCallback = SPI_DMAError;
mbed_official 573:ad23fe03a082 1556 }
mbed_official 573:ad23fe03a082 1557 else
mbed_official 573:ad23fe03a082 1558 {
mbed_official 573:ad23fe03a082 1559 hspi->hdmatx->XferErrorCallback = NULL;
mbed_official 573:ad23fe03a082 1560 }
mbed_official 573:ad23fe03a082 1561
mbed_official 573:ad23fe03a082 1562 /* Enable the Tx DMA channel */
mbed_official 573:ad23fe03a082 1563 HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
mbed_official 573:ad23fe03a082 1564
mbed_official 573:ad23fe03a082 1565 /* Process Unlocked */
mbed_official 573:ad23fe03a082 1566 __HAL_UNLOCK(hspi);
mbed_official 573:ad23fe03a082 1567
mbed_official 573:ad23fe03a082 1568 /* Check if the SPI is already enabled */
mbed_official 573:ad23fe03a082 1569 if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official 573:ad23fe03a082 1570 {
mbed_official 573:ad23fe03a082 1571 /* Enable SPI peripheral */
mbed_official 573:ad23fe03a082 1572 __HAL_SPI_ENABLE(hspi);
mbed_official 573:ad23fe03a082 1573 }
mbed_official 573:ad23fe03a082 1574
mbed_official 573:ad23fe03a082 1575 /* Enable Tx DMA Request */
mbed_official 573:ad23fe03a082 1576 hspi->Instance->CR2 |= SPI_CR2_TXDMAEN;
mbed_official 573:ad23fe03a082 1577
mbed_official 573:ad23fe03a082 1578 return HAL_OK;
mbed_official 573:ad23fe03a082 1579 }
mbed_official 573:ad23fe03a082 1580 else
mbed_official 573:ad23fe03a082 1581 {
mbed_official 573:ad23fe03a082 1582 return HAL_BUSY;
mbed_official 573:ad23fe03a082 1583 }
mbed_official 573:ad23fe03a082 1584 }
mbed_official 573:ad23fe03a082 1585
mbed_official 573:ad23fe03a082 1586 /**
mbed_official 573:ad23fe03a082 1587 * @brief Pauses the DMA Transfer.
mbed_official 573:ad23fe03a082 1588 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 573:ad23fe03a082 1589 * the configuration information for the specified SPI module.
mbed_official 573:ad23fe03a082 1590 * @retval HAL status
mbed_official 573:ad23fe03a082 1591 */
mbed_official 573:ad23fe03a082 1592 HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi)
mbed_official 573:ad23fe03a082 1593 {
mbed_official 573:ad23fe03a082 1594 /* Process Locked */
mbed_official 573:ad23fe03a082 1595 __HAL_LOCK(hspi);
mbed_official 573:ad23fe03a082 1596
mbed_official 573:ad23fe03a082 1597 /* Disable the SPI DMA Tx & Rx requests */
mbed_official 573:ad23fe03a082 1598 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
mbed_official 573:ad23fe03a082 1599
mbed_official 573:ad23fe03a082 1600 /* Process Unlocked */
mbed_official 573:ad23fe03a082 1601 __HAL_UNLOCK(hspi);
mbed_official 573:ad23fe03a082 1602
mbed_official 573:ad23fe03a082 1603 return HAL_OK;
mbed_official 573:ad23fe03a082 1604 }
mbed_official 573:ad23fe03a082 1605
mbed_official 573:ad23fe03a082 1606 /**
mbed_official 573:ad23fe03a082 1607 * @brief Resumes the DMA Transfer.
mbed_official 573:ad23fe03a082 1608 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 573:ad23fe03a082 1609 * the configuration information for the specified SPI module.
mbed_official 573:ad23fe03a082 1610 * @retval HAL status
mbed_official 573:ad23fe03a082 1611 */
mbed_official 573:ad23fe03a082 1612 HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi)
mbed_official 573:ad23fe03a082 1613 {
mbed_official 573:ad23fe03a082 1614 /* Process Locked */
mbed_official 573:ad23fe03a082 1615 __HAL_LOCK(hspi);
mbed_official 573:ad23fe03a082 1616
mbed_official 573:ad23fe03a082 1617 /* Enable the SPI DMA Tx & Rx requests */
mbed_official 573:ad23fe03a082 1618 SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
mbed_official 573:ad23fe03a082 1619
mbed_official 573:ad23fe03a082 1620 /* Process Unlocked */
mbed_official 573:ad23fe03a082 1621 __HAL_UNLOCK(hspi);
mbed_official 573:ad23fe03a082 1622
mbed_official 573:ad23fe03a082 1623 return HAL_OK;
mbed_official 573:ad23fe03a082 1624 }
mbed_official 573:ad23fe03a082 1625
mbed_official 573:ad23fe03a082 1626 /**
mbed_official 573:ad23fe03a082 1627 * @brief Stops the DMA Transfer.
mbed_official 573:ad23fe03a082 1628 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 573:ad23fe03a082 1629 * the configuration information for the specified SPI module.
mbed_official 573:ad23fe03a082 1630 * @retval HAL status
mbed_official 573:ad23fe03a082 1631 */
mbed_official 573:ad23fe03a082 1632 HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)
mbed_official 573:ad23fe03a082 1633 {
mbed_official 573:ad23fe03a082 1634 /* The Lock is not implemented on this API to allow the user application
mbed_official 573:ad23fe03a082 1635 to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback():
mbed_official 573:ad23fe03a082 1636 when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
mbed_official 573:ad23fe03a082 1637 and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback()
mbed_official 573:ad23fe03a082 1638 */
mbed_official 573:ad23fe03a082 1639
mbed_official 573:ad23fe03a082 1640 /* Abort the SPI DMA tx Stream */
mbed_official 573:ad23fe03a082 1641 if(hspi->hdmatx != NULL)
mbed_official 573:ad23fe03a082 1642 {
mbed_official 573:ad23fe03a082 1643 HAL_DMA_Abort(hspi->hdmatx);
mbed_official 573:ad23fe03a082 1644 }
mbed_official 573:ad23fe03a082 1645 /* Abort the SPI DMA rx Stream */
mbed_official 573:ad23fe03a082 1646 if(hspi->hdmarx != NULL)
mbed_official 573:ad23fe03a082 1647 {
mbed_official 573:ad23fe03a082 1648 HAL_DMA_Abort(hspi->hdmarx);
mbed_official 573:ad23fe03a082 1649 }
mbed_official 573:ad23fe03a082 1650
mbed_official 573:ad23fe03a082 1651 /* Disable the SPI DMA Tx & Rx requests */
mbed_official 573:ad23fe03a082 1652 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
mbed_official 573:ad23fe03a082 1653 hspi->State = HAL_SPI_STATE_READY;
mbed_official 573:ad23fe03a082 1654 return HAL_OK;
mbed_official 573:ad23fe03a082 1655 }
mbed_official 573:ad23fe03a082 1656
mbed_official 573:ad23fe03a082 1657 /**
mbed_official 573:ad23fe03a082 1658 * @brief This function handles SPI interrupt request.
mbed_official 573:ad23fe03a082 1659 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 573:ad23fe03a082 1660 * the configuration information for the specified SPI module.
mbed_official 573:ad23fe03a082 1661 * @retval None
mbed_official 573:ad23fe03a082 1662 */
mbed_official 573:ad23fe03a082 1663 void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
mbed_official 573:ad23fe03a082 1664 {
mbed_official 573:ad23fe03a082 1665 /* SPI in mode Receiver ----------------------------------------------------*/
mbed_official 573:ad23fe03a082 1666 if((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_OVR) == RESET) &&
mbed_official 573:ad23fe03a082 1667 (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE) != RESET) && (__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_RXNE) != RESET))
mbed_official 573:ad23fe03a082 1668 {
mbed_official 573:ad23fe03a082 1669 hspi->RxISR(hspi);
mbed_official 573:ad23fe03a082 1670 return;
mbed_official 573:ad23fe03a082 1671 }
mbed_official 573:ad23fe03a082 1672
mbed_official 573:ad23fe03a082 1673 /* SPI in mode Transmitter ---------------------------------------------------*/
mbed_official 573:ad23fe03a082 1674 if((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE) != RESET) && (__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_TXE) != RESET))
mbed_official 573:ad23fe03a082 1675 {
mbed_official 573:ad23fe03a082 1676 hspi->TxISR(hspi);
mbed_official 573:ad23fe03a082 1677 return;
mbed_official 573:ad23fe03a082 1678 }
mbed_official 573:ad23fe03a082 1679
mbed_official 573:ad23fe03a082 1680 /* SPI in ERROR Treatment ---------------------------------------------------*/
mbed_official 573:ad23fe03a082 1681 if((hspi->Instance->SR & (SPI_FLAG_MODF | SPI_FLAG_OVR | SPI_FLAG_FRE)) != RESET)
mbed_official 573:ad23fe03a082 1682 {
mbed_official 573:ad23fe03a082 1683 /* SPI Overrun error interrupt occurred -------------------------------------*/
mbed_official 573:ad23fe03a082 1684 if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_OVR) != RESET)
mbed_official 573:ad23fe03a082 1685 {
mbed_official 573:ad23fe03a082 1686 if(hspi->State != HAL_SPI_STATE_BUSY_TX)
mbed_official 573:ad23fe03a082 1687 {
mbed_official 573:ad23fe03a082 1688 hspi->ErrorCode |= HAL_SPI_ERROR_OVR;
mbed_official 573:ad23fe03a082 1689 __HAL_SPI_CLEAR_OVRFLAG(hspi);
mbed_official 573:ad23fe03a082 1690 }
mbed_official 573:ad23fe03a082 1691 else
mbed_official 573:ad23fe03a082 1692 {
mbed_official 573:ad23fe03a082 1693 return;
mbed_official 573:ad23fe03a082 1694 }
mbed_official 573:ad23fe03a082 1695 }
mbed_official 573:ad23fe03a082 1696
mbed_official 573:ad23fe03a082 1697 /* SPI Mode Fault error interrupt occurred -------------------------------------*/
mbed_official 573:ad23fe03a082 1698 if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_MODF) != RESET)
mbed_official 573:ad23fe03a082 1699 {
mbed_official 573:ad23fe03a082 1700 hspi->ErrorCode |= HAL_SPI_ERROR_MODF;
mbed_official 573:ad23fe03a082 1701 __HAL_SPI_CLEAR_MODFFLAG(hspi);
mbed_official 573:ad23fe03a082 1702 }
mbed_official 573:ad23fe03a082 1703
mbed_official 573:ad23fe03a082 1704 /* SPI Frame error interrupt occurred ----------------------------------------*/
mbed_official 573:ad23fe03a082 1705 if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_FRE) != RESET)
mbed_official 573:ad23fe03a082 1706 {
mbed_official 573:ad23fe03a082 1707 hspi->ErrorCode |= HAL_SPI_ERROR_FRE;
mbed_official 573:ad23fe03a082 1708 __HAL_SPI_CLEAR_FREFLAG(hspi);
mbed_official 573:ad23fe03a082 1709 }
mbed_official 573:ad23fe03a082 1710
mbed_official 573:ad23fe03a082 1711 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR);
mbed_official 573:ad23fe03a082 1712 hspi->State = HAL_SPI_STATE_READY;
mbed_official 573:ad23fe03a082 1713 HAL_SPI_ErrorCallback(hspi);
mbed_official 573:ad23fe03a082 1714
mbed_official 573:ad23fe03a082 1715 return;
mbed_official 573:ad23fe03a082 1716 }
mbed_official 573:ad23fe03a082 1717 }
mbed_official 573:ad23fe03a082 1718
mbed_official 573:ad23fe03a082 1719 /**
mbed_official 573:ad23fe03a082 1720 * @brief Tx Transfer completed callback
mbed_official 573:ad23fe03a082 1721 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 573:ad23fe03a082 1722 * the configuration information for SPI module.
mbed_official 573:ad23fe03a082 1723 * @retval None
mbed_official 573:ad23fe03a082 1724 */
mbed_official 573:ad23fe03a082 1725 __weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
mbed_official 573:ad23fe03a082 1726 {
mbed_official 573:ad23fe03a082 1727 /* NOTE : This function should not be modified, when the callback is needed,
mbed_official 573:ad23fe03a082 1728 the HAL_SPI_TxCpltCallback should be implemented in the user file
mbed_official 573:ad23fe03a082 1729 */
mbed_official 573:ad23fe03a082 1730 }
mbed_official 573:ad23fe03a082 1731
mbed_official 573:ad23fe03a082 1732 /**
mbed_official 573:ad23fe03a082 1733 * @brief Rx Transfer completed callbacks
mbed_official 573:ad23fe03a082 1734 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 573:ad23fe03a082 1735 * the configuration information for SPI module.
mbed_official 573:ad23fe03a082 1736 * @retval None
mbed_official 573:ad23fe03a082 1737 */
mbed_official 573:ad23fe03a082 1738 __weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
mbed_official 573:ad23fe03a082 1739 {
mbed_official 573:ad23fe03a082 1740 /* NOTE : This function should not be modified, when the callback is needed,
mbed_official 573:ad23fe03a082 1741 the HAL_SPI_RxCpltCallback should be implemented in the user file
mbed_official 573:ad23fe03a082 1742 */
mbed_official 573:ad23fe03a082 1743 }
mbed_official 573:ad23fe03a082 1744
mbed_official 573:ad23fe03a082 1745 /**
mbed_official 573:ad23fe03a082 1746 * @brief Tx and Rx Transfer completed callback
mbed_official 573:ad23fe03a082 1747 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 573:ad23fe03a082 1748 * the configuration information for SPI module.
mbed_official 573:ad23fe03a082 1749 * @retval None
mbed_official 573:ad23fe03a082 1750 */
mbed_official 573:ad23fe03a082 1751 __weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
mbed_official 573:ad23fe03a082 1752 {
mbed_official 573:ad23fe03a082 1753 /* NOTE : This function should not be modified, when the callback is needed,
mbed_official 573:ad23fe03a082 1754 the HAL_SPI_TxRxCpltCallback should be implemented in the user file
mbed_official 573:ad23fe03a082 1755 */
mbed_official 573:ad23fe03a082 1756 }
mbed_official 573:ad23fe03a082 1757
mbed_official 573:ad23fe03a082 1758 /**
mbed_official 573:ad23fe03a082 1759 * @brief Tx Half Transfer completed callback
mbed_official 573:ad23fe03a082 1760 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 573:ad23fe03a082 1761 * the configuration information for SPI module.
mbed_official 573:ad23fe03a082 1762 * @retval None
mbed_official 573:ad23fe03a082 1763 */
mbed_official 573:ad23fe03a082 1764 __weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)
mbed_official 573:ad23fe03a082 1765 {
mbed_official 573:ad23fe03a082 1766 /* NOTE : This function should not be modified, when the callback is needed,
mbed_official 573:ad23fe03a082 1767 the HAL_SPI_TxHalfCpltCallback should be implemented in the user file
mbed_official 573:ad23fe03a082 1768 */
mbed_official 573:ad23fe03a082 1769 }
mbed_official 573:ad23fe03a082 1770
mbed_official 573:ad23fe03a082 1771 /**
mbed_official 573:ad23fe03a082 1772 * @brief Rx Half Transfer completed callback
mbed_official 573:ad23fe03a082 1773 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 573:ad23fe03a082 1774 * the configuration information for SPI module.
mbed_official 573:ad23fe03a082 1775 * @retval None
mbed_official 573:ad23fe03a082 1776 */
mbed_official 573:ad23fe03a082 1777 __weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)
mbed_official 573:ad23fe03a082 1778 {
mbed_official 573:ad23fe03a082 1779 /* NOTE : This function should not be modified, when the callback is needed,
mbed_official 573:ad23fe03a082 1780 the HAL_SPI_RxHalfCpltCallback() should be implemented in the user file
mbed_official 573:ad23fe03a082 1781 */
mbed_official 573:ad23fe03a082 1782 }
mbed_official 573:ad23fe03a082 1783
mbed_official 573:ad23fe03a082 1784 /**
mbed_official 573:ad23fe03a082 1785 * @brief Tx and Rx Half Transfer callback
mbed_official 573:ad23fe03a082 1786 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 573:ad23fe03a082 1787 * the configuration information for SPI module.
mbed_official 573:ad23fe03a082 1788 * @retval None
mbed_official 573:ad23fe03a082 1789 */
mbed_official 573:ad23fe03a082 1790 __weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
mbed_official 573:ad23fe03a082 1791 {
mbed_official 573:ad23fe03a082 1792 /* NOTE : This function should not be modified, when the callback is needed,
mbed_official 573:ad23fe03a082 1793 the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user file
mbed_official 573:ad23fe03a082 1794 */
mbed_official 573:ad23fe03a082 1795 }
mbed_official 573:ad23fe03a082 1796
mbed_official 573:ad23fe03a082 1797 /**
mbed_official 573:ad23fe03a082 1798 * @brief SPI error callback
mbed_official 573:ad23fe03a082 1799 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 573:ad23fe03a082 1800 * the configuration information for SPI module.
mbed_official 573:ad23fe03a082 1801 * @retval None
mbed_official 573:ad23fe03a082 1802 */
mbed_official 573:ad23fe03a082 1803 __weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
mbed_official 573:ad23fe03a082 1804 {
mbed_official 573:ad23fe03a082 1805 /* NOTE : This function should not be modified, when the callback is needed,
mbed_official 573:ad23fe03a082 1806 the HAL_SPI_ErrorCallback should be implemented in the user file
mbed_official 573:ad23fe03a082 1807 */
mbed_official 573:ad23fe03a082 1808 /* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI processes
mbed_official 573:ad23fe03a082 1809 and user can use HAL_SPI_GetError() API to check the latest error occurred
mbed_official 573:ad23fe03a082 1810 */
mbed_official 573:ad23fe03a082 1811 }
mbed_official 573:ad23fe03a082 1812
mbed_official 573:ad23fe03a082 1813 /**
mbed_official 573:ad23fe03a082 1814 * @}
mbed_official 573:ad23fe03a082 1815 */
mbed_official 573:ad23fe03a082 1816
mbed_official 573:ad23fe03a082 1817 /**
mbed_official 573:ad23fe03a082 1818 * @}
mbed_official 573:ad23fe03a082 1819 */
mbed_official 573:ad23fe03a082 1820
mbed_official 573:ad23fe03a082 1821 /** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions
mbed_official 573:ad23fe03a082 1822 * @brief SPI control functions
mbed_official 573:ad23fe03a082 1823 *
mbed_official 573:ad23fe03a082 1824 @verbatim
mbed_official 573:ad23fe03a082 1825 ===============================================================================
mbed_official 573:ad23fe03a082 1826 ##### Peripheral State and Errors functions #####
mbed_official 573:ad23fe03a082 1827 ===============================================================================
mbed_official 573:ad23fe03a082 1828 [..]
mbed_official 573:ad23fe03a082 1829 This subsection provides a set of functions allowing to control the SPI.
mbed_official 573:ad23fe03a082 1830 (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral
mbed_official 573:ad23fe03a082 1831 (+) HAL_SPI_GetError() check in run-time Errors occurring during communication
mbed_official 573:ad23fe03a082 1832 @endverbatim
mbed_official 573:ad23fe03a082 1833 * @{
mbed_official 573:ad23fe03a082 1834 */
mbed_official 573:ad23fe03a082 1835
mbed_official 573:ad23fe03a082 1836 /**
mbed_official 573:ad23fe03a082 1837 * @brief Return the SPI state
mbed_official 573:ad23fe03a082 1838 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 573:ad23fe03a082 1839 * the configuration information for SPI module.
mbed_official 573:ad23fe03a082 1840 * @retval SPI state
mbed_official 573:ad23fe03a082 1841 */
mbed_official 573:ad23fe03a082 1842 HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
mbed_official 573:ad23fe03a082 1843 {
mbed_official 573:ad23fe03a082 1844 return hspi->State;
mbed_official 573:ad23fe03a082 1845 }
mbed_official 573:ad23fe03a082 1846
mbed_official 573:ad23fe03a082 1847 /**
mbed_official 573:ad23fe03a082 1848 * @brief Return the SPI error code
mbed_official 573:ad23fe03a082 1849 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 573:ad23fe03a082 1850 * the configuration information for SPI module.
mbed_official 573:ad23fe03a082 1851 * @retval SPI error code in bitmap format
mbed_official 573:ad23fe03a082 1852 */
mbed_official 573:ad23fe03a082 1853 uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
mbed_official 573:ad23fe03a082 1854 {
mbed_official 573:ad23fe03a082 1855 return hspi->ErrorCode;
mbed_official 573:ad23fe03a082 1856 }
mbed_official 573:ad23fe03a082 1857
mbed_official 573:ad23fe03a082 1858 /**
mbed_official 573:ad23fe03a082 1859 * @}
mbed_official 573:ad23fe03a082 1860 */
mbed_official 573:ad23fe03a082 1861
mbed_official 573:ad23fe03a082 1862 /**
mbed_official 573:ad23fe03a082 1863 * @}
mbed_official 573:ad23fe03a082 1864 */
mbed_official 573:ad23fe03a082 1865
mbed_official 573:ad23fe03a082 1866 /** @defgroup SPI_Private_Functions SPI Private Functions
mbed_official 573:ad23fe03a082 1867 * @{
mbed_official 573:ad23fe03a082 1868 */
mbed_official 573:ad23fe03a082 1869
mbed_official 573:ad23fe03a082 1870 /**
mbed_official 573:ad23fe03a082 1871 * @brief DMA SPI transmit process complete callback
mbed_official 573:ad23fe03a082 1872 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
mbed_official 573:ad23fe03a082 1873 * the configuration information for the specified DMA module.
mbed_official 573:ad23fe03a082 1874 * @retval None
mbed_official 573:ad23fe03a082 1875 */
mbed_official 573:ad23fe03a082 1876 static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
mbed_official 573:ad23fe03a082 1877 {
mbed_official 573:ad23fe03a082 1878 SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official 573:ad23fe03a082 1879
mbed_official 573:ad23fe03a082 1880 /* DMA Normal Mode */
mbed_official 573:ad23fe03a082 1881 if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
mbed_official 573:ad23fe03a082 1882 {
mbed_official 573:ad23fe03a082 1883 /* Disable Tx DMA Request */
mbed_official 573:ad23fe03a082 1884 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
mbed_official 573:ad23fe03a082 1885
mbed_official 573:ad23fe03a082 1886 /* Clear OVERUN flag in 2 Lines communication mode because received data is not read */
mbed_official 573:ad23fe03a082 1887 if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
mbed_official 573:ad23fe03a082 1888 {
mbed_official 573:ad23fe03a082 1889 __HAL_SPI_CLEAR_OVRFLAG(hspi);
mbed_official 573:ad23fe03a082 1890 }
mbed_official 573:ad23fe03a082 1891
mbed_official 573:ad23fe03a082 1892 hspi->TxXferCount = 0;
mbed_official 573:ad23fe03a082 1893 hspi->State = HAL_SPI_STATE_READY;
mbed_official 573:ad23fe03a082 1894
mbed_official 573:ad23fe03a082 1895 if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
mbed_official 573:ad23fe03a082 1896 {
mbed_official 573:ad23fe03a082 1897 HAL_SPI_ErrorCallback(hspi);
mbed_official 573:ad23fe03a082 1898 return;
mbed_official 573:ad23fe03a082 1899 }
mbed_official 573:ad23fe03a082 1900 }
mbed_official 573:ad23fe03a082 1901 HAL_SPI_TxCpltCallback(hspi);
mbed_official 573:ad23fe03a082 1902 }
mbed_official 573:ad23fe03a082 1903
mbed_official 573:ad23fe03a082 1904 /**
mbed_official 573:ad23fe03a082 1905 * @brief DMA SPI receive process complete callback
mbed_official 573:ad23fe03a082 1906 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
mbed_official 573:ad23fe03a082 1907 * the configuration information for the specified DMA module.
mbed_official 573:ad23fe03a082 1908 * @retval None
mbed_official 573:ad23fe03a082 1909 */
mbed_official 573:ad23fe03a082 1910 static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
mbed_official 573:ad23fe03a082 1911 {
mbed_official 573:ad23fe03a082 1912 __IO uint16_t tmpreg;
mbed_official 573:ad23fe03a082 1913 SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official 573:ad23fe03a082 1914
mbed_official 573:ad23fe03a082 1915 /* DMA Normal mode */
mbed_official 573:ad23fe03a082 1916 if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
mbed_official 573:ad23fe03a082 1917 {
mbed_official 573:ad23fe03a082 1918 /* CRC handling */
mbed_official 573:ad23fe03a082 1919 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official 573:ad23fe03a082 1920 {
mbed_official 573:ad23fe03a082 1921 /* Wait until TXE flag */
mbed_official 573:ad23fe03a082 1922 if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT) != HAL_OK)
mbed_official 573:ad23fe03a082 1923 {
mbed_official 573:ad23fe03a082 1924 /* Error on the CRC reception */
mbed_official 573:ad23fe03a082 1925 hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
mbed_official 573:ad23fe03a082 1926 }
mbed_official 573:ad23fe03a082 1927 if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
mbed_official 573:ad23fe03a082 1928 {
mbed_official 573:ad23fe03a082 1929 tmpreg = hspi->Instance->DR;
mbed_official 573:ad23fe03a082 1930 UNUSED(tmpreg); /* To avoid GCC warning */
mbed_official 573:ad23fe03a082 1931 }
mbed_official 573:ad23fe03a082 1932 else
mbed_official 573:ad23fe03a082 1933 {
mbed_official 573:ad23fe03a082 1934 tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
mbed_official 573:ad23fe03a082 1935 UNUSED(tmpreg); /* To avoid GCC warning */
mbed_official 573:ad23fe03a082 1936
mbed_official 573:ad23fe03a082 1937 if(hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
mbed_official 573:ad23fe03a082 1938 {
mbed_official 573:ad23fe03a082 1939 if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT) != HAL_OK)
mbed_official 573:ad23fe03a082 1940 {
mbed_official 573:ad23fe03a082 1941 /* Error on the CRC reception */
mbed_official 573:ad23fe03a082 1942 hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
mbed_official 573:ad23fe03a082 1943 }
mbed_official 573:ad23fe03a082 1944 tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
mbed_official 573:ad23fe03a082 1945 UNUSED(tmpreg); /* To avoid GCC warning */
mbed_official 573:ad23fe03a082 1946 }
mbed_official 573:ad23fe03a082 1947 }
mbed_official 573:ad23fe03a082 1948 }
mbed_official 573:ad23fe03a082 1949
mbed_official 573:ad23fe03a082 1950 /* Disable Rx DMA Request */
mbed_official 573:ad23fe03a082 1951 hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
mbed_official 573:ad23fe03a082 1952 /* Disable Tx DMA Request (done by default to handle the case master rx direction 2 lines) */
mbed_official 573:ad23fe03a082 1953 hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
mbed_official 573:ad23fe03a082 1954
mbed_official 573:ad23fe03a082 1955 /* Check the end of the transaction */
mbed_official 573:ad23fe03a082 1956 SPI_EndRxTransaction(hspi,SPI_DEFAULT_TIMEOUT);
mbed_official 573:ad23fe03a082 1957
mbed_official 573:ad23fe03a082 1958 hspi->RxXferCount = 0;
mbed_official 573:ad23fe03a082 1959 hspi->State = HAL_SPI_STATE_READY;
mbed_official 573:ad23fe03a082 1960
mbed_official 573:ad23fe03a082 1961 /* Check if CRC error occurred */
mbed_official 573:ad23fe03a082 1962 if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
mbed_official 573:ad23fe03a082 1963 {
mbed_official 573:ad23fe03a082 1964 hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
mbed_official 573:ad23fe03a082 1965 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
mbed_official 573:ad23fe03a082 1966 HAL_SPI_RxCpltCallback(hspi);
mbed_official 573:ad23fe03a082 1967 }
mbed_official 573:ad23fe03a082 1968 else
mbed_official 573:ad23fe03a082 1969 {
mbed_official 573:ad23fe03a082 1970 if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
mbed_official 573:ad23fe03a082 1971 {
mbed_official 573:ad23fe03a082 1972 HAL_SPI_RxCpltCallback(hspi);
mbed_official 573:ad23fe03a082 1973 }
mbed_official 573:ad23fe03a082 1974 else
mbed_official 573:ad23fe03a082 1975 {
mbed_official 573:ad23fe03a082 1976 HAL_SPI_ErrorCallback(hspi);
mbed_official 573:ad23fe03a082 1977 }
mbed_official 573:ad23fe03a082 1978 }
mbed_official 573:ad23fe03a082 1979 }
mbed_official 573:ad23fe03a082 1980 else
mbed_official 573:ad23fe03a082 1981 {
mbed_official 573:ad23fe03a082 1982 HAL_SPI_RxCpltCallback(hspi);
mbed_official 573:ad23fe03a082 1983 }
mbed_official 573:ad23fe03a082 1984 }
mbed_official 573:ad23fe03a082 1985
mbed_official 573:ad23fe03a082 1986 /**
mbed_official 573:ad23fe03a082 1987 * @brief DMA SPI transmit receive process complete callback
mbed_official 573:ad23fe03a082 1988 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
mbed_official 573:ad23fe03a082 1989 * the configuration information for the specified DMA module.
mbed_official 573:ad23fe03a082 1990 * @retval None
mbed_official 573:ad23fe03a082 1991 */
mbed_official 573:ad23fe03a082 1992 static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
mbed_official 573:ad23fe03a082 1993 {
mbed_official 573:ad23fe03a082 1994 __IO int16_t tmpreg;
mbed_official 573:ad23fe03a082 1995 SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official 573:ad23fe03a082 1996
mbed_official 573:ad23fe03a082 1997 /* CRC handling */
mbed_official 573:ad23fe03a082 1998 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official 573:ad23fe03a082 1999 {
mbed_official 573:ad23fe03a082 2000 if((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_8BIT))
mbed_official 573:ad23fe03a082 2001 {
mbed_official 573:ad23fe03a082 2002 if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_QUARTER_FULL, SPI_DEFAULT_TIMEOUT) != HAL_OK)
mbed_official 573:ad23fe03a082 2003 {
mbed_official 573:ad23fe03a082 2004 /* Error on the CRC reception */
mbed_official 573:ad23fe03a082 2005 hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
mbed_official 573:ad23fe03a082 2006 }
mbed_official 573:ad23fe03a082 2007 tmpreg = *(__IO uint8_t *)&hspi->Instance->DR;
mbed_official 573:ad23fe03a082 2008 UNUSED(tmpreg); /* To avoid GCC warning */
mbed_official 573:ad23fe03a082 2009 }
mbed_official 573:ad23fe03a082 2010 else
mbed_official 573:ad23fe03a082 2011 {
mbed_official 573:ad23fe03a082 2012 if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_HALF_FULL, SPI_DEFAULT_TIMEOUT) != HAL_OK)
mbed_official 573:ad23fe03a082 2013 {
mbed_official 573:ad23fe03a082 2014 /* Error on the CRC reception */
mbed_official 573:ad23fe03a082 2015 hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
mbed_official 573:ad23fe03a082 2016 }
mbed_official 573:ad23fe03a082 2017 tmpreg = hspi->Instance->DR;
mbed_official 573:ad23fe03a082 2018 UNUSED(tmpreg); /* To avoid GCC warning */
mbed_official 573:ad23fe03a082 2019 }
mbed_official 573:ad23fe03a082 2020 }
mbed_official 573:ad23fe03a082 2021
mbed_official 573:ad23fe03a082 2022 /* Check the end of the transaction */
mbed_official 573:ad23fe03a082 2023 SPI_EndRxTxTransaction(hspi,SPI_DEFAULT_TIMEOUT);
mbed_official 573:ad23fe03a082 2024
mbed_official 573:ad23fe03a082 2025 /* Disable Tx DMA Request */
mbed_official 573:ad23fe03a082 2026 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
mbed_official 573:ad23fe03a082 2027
mbed_official 573:ad23fe03a082 2028 /* Disable Rx DMA Request */
mbed_official 573:ad23fe03a082 2029 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
mbed_official 573:ad23fe03a082 2030
mbed_official 573:ad23fe03a082 2031 hspi->TxXferCount = 0;
mbed_official 573:ad23fe03a082 2032 hspi->RxXferCount = 0;
mbed_official 573:ad23fe03a082 2033 hspi->State = HAL_SPI_STATE_READY;
mbed_official 573:ad23fe03a082 2034
mbed_official 573:ad23fe03a082 2035 /* Check if CRC error occurred */
mbed_official 573:ad23fe03a082 2036 if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
mbed_official 573:ad23fe03a082 2037 {
mbed_official 573:ad23fe03a082 2038 hspi->ErrorCode = HAL_SPI_ERROR_CRC;
mbed_official 573:ad23fe03a082 2039 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
mbed_official 573:ad23fe03a082 2040 HAL_SPI_ErrorCallback(hspi);
mbed_official 573:ad23fe03a082 2041 }
mbed_official 573:ad23fe03a082 2042 else
mbed_official 573:ad23fe03a082 2043 {
mbed_official 573:ad23fe03a082 2044 if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
mbed_official 573:ad23fe03a082 2045 {
mbed_official 573:ad23fe03a082 2046 HAL_SPI_TxRxCpltCallback(hspi);
mbed_official 573:ad23fe03a082 2047 }
mbed_official 573:ad23fe03a082 2048 else
mbed_official 573:ad23fe03a082 2049 {
mbed_official 573:ad23fe03a082 2050 HAL_SPI_ErrorCallback(hspi);
mbed_official 573:ad23fe03a082 2051 }
mbed_official 573:ad23fe03a082 2052 }
mbed_official 573:ad23fe03a082 2053 }
mbed_official 573:ad23fe03a082 2054
mbed_official 573:ad23fe03a082 2055 /**
mbed_official 573:ad23fe03a082 2056 * @brief DMA SPI half transmit process complete callback
mbed_official 573:ad23fe03a082 2057 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
mbed_official 573:ad23fe03a082 2058 * the configuration information for the specified DMA module.
mbed_official 573:ad23fe03a082 2059 * @retval None
mbed_official 573:ad23fe03a082 2060 */
mbed_official 573:ad23fe03a082 2061 static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)
mbed_official 573:ad23fe03a082 2062 {
mbed_official 573:ad23fe03a082 2063 SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official 573:ad23fe03a082 2064
mbed_official 573:ad23fe03a082 2065 HAL_SPI_TxHalfCpltCallback(hspi);
mbed_official 573:ad23fe03a082 2066 }
mbed_official 573:ad23fe03a082 2067
mbed_official 573:ad23fe03a082 2068 /**
mbed_official 573:ad23fe03a082 2069 * @brief DMA SPI half receive process complete callback
mbed_official 573:ad23fe03a082 2070 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
mbed_official 573:ad23fe03a082 2071 * the configuration information for the specified DMA module.
mbed_official 573:ad23fe03a082 2072 * @retval None
mbed_official 573:ad23fe03a082 2073 */
mbed_official 573:ad23fe03a082 2074 static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)
mbed_official 573:ad23fe03a082 2075 {
mbed_official 573:ad23fe03a082 2076 SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official 573:ad23fe03a082 2077
mbed_official 573:ad23fe03a082 2078 HAL_SPI_RxHalfCpltCallback(hspi);
mbed_official 573:ad23fe03a082 2079 }
mbed_official 573:ad23fe03a082 2080
mbed_official 573:ad23fe03a082 2081 /**
mbed_official 573:ad23fe03a082 2082 * @brief DMA SPI Half transmit receive process complete callback
mbed_official 573:ad23fe03a082 2083 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
mbed_official 573:ad23fe03a082 2084 * the configuration information for the specified DMA module.
mbed_official 573:ad23fe03a082 2085 * @retval None
mbed_official 573:ad23fe03a082 2086 */
mbed_official 573:ad23fe03a082 2087 static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)
mbed_official 573:ad23fe03a082 2088 {
mbed_official 573:ad23fe03a082 2089 SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official 573:ad23fe03a082 2090
mbed_official 573:ad23fe03a082 2091 HAL_SPI_TxRxHalfCpltCallback(hspi);
mbed_official 573:ad23fe03a082 2092 }
mbed_official 573:ad23fe03a082 2093
mbed_official 573:ad23fe03a082 2094 /**
mbed_official 573:ad23fe03a082 2095 * @brief DMA SPI communication error callback
mbed_official 573:ad23fe03a082 2096 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
mbed_official 573:ad23fe03a082 2097 * the configuration information for the specified DMA module.
mbed_official 573:ad23fe03a082 2098 * @retval None
mbed_official 573:ad23fe03a082 2099 */
mbed_official 573:ad23fe03a082 2100 static void SPI_DMAError(DMA_HandleTypeDef *hdma)
mbed_official 573:ad23fe03a082 2101 {
mbed_official 573:ad23fe03a082 2102 SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official 573:ad23fe03a082 2103
mbed_official 573:ad23fe03a082 2104 /* Stop the disable DMA transfer on SPI side */
mbed_official 573:ad23fe03a082 2105 CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
mbed_official 573:ad23fe03a082 2106
mbed_official 573:ad23fe03a082 2107 hspi->ErrorCode|= HAL_SPI_ERROR_DMA;
mbed_official 573:ad23fe03a082 2108 hspi->State = HAL_SPI_STATE_READY;
mbed_official 573:ad23fe03a082 2109 HAL_SPI_ErrorCallback(hspi);
mbed_official 573:ad23fe03a082 2110 }
mbed_official 573:ad23fe03a082 2111
mbed_official 573:ad23fe03a082 2112 /**
mbed_official 573:ad23fe03a082 2113 * @brief Rx Handler for Transmit and Receive in Interrupt mode
mbed_official 573:ad23fe03a082 2114 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 573:ad23fe03a082 2115 * the configuration information for SPI module.
mbed_official 573:ad23fe03a082 2116 * @retval None
mbed_official 573:ad23fe03a082 2117 */
mbed_official 573:ad23fe03a082 2118 static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
mbed_official 573:ad23fe03a082 2119 {
mbed_official 573:ad23fe03a082 2120 /* Receive data in packing mode */
mbed_official 573:ad23fe03a082 2121 if(hspi->RxXferCount > 1)
mbed_official 573:ad23fe03a082 2122 {
mbed_official 573:ad23fe03a082 2123 *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
mbed_official 573:ad23fe03a082 2124 hspi->pRxBuffPtr += sizeof(uint16_t);
mbed_official 573:ad23fe03a082 2125 hspi->RxXferCount -= 2;
mbed_official 573:ad23fe03a082 2126 if(hspi->RxXferCount == 1)
mbed_official 573:ad23fe03a082 2127 {
mbed_official 573:ad23fe03a082 2128 /* set fiforxthreshold according the reception data length: 8bit */
mbed_official 573:ad23fe03a082 2129 SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
mbed_official 573:ad23fe03a082 2130 }
mbed_official 573:ad23fe03a082 2131 }
mbed_official 573:ad23fe03a082 2132 /* Receive data in 8 Bit mode */
mbed_official 573:ad23fe03a082 2133 else
mbed_official 573:ad23fe03a082 2134 {
mbed_official 573:ad23fe03a082 2135 *hspi->pRxBuffPtr++ = *((__IO uint8_t *)&hspi->Instance->DR);
mbed_official 573:ad23fe03a082 2136 hspi->RxXferCount--;
mbed_official 573:ad23fe03a082 2137 }
mbed_official 573:ad23fe03a082 2138
mbed_official 573:ad23fe03a082 2139 /* check end of the reception */
mbed_official 573:ad23fe03a082 2140 if(hspi->RxXferCount == 0)
mbed_official 573:ad23fe03a082 2141 {
mbed_official 573:ad23fe03a082 2142 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official 573:ad23fe03a082 2143 {
mbed_official 573:ad23fe03a082 2144 hspi->RxISR = SPI_2linesRxISR_8BITCRC;
mbed_official 573:ad23fe03a082 2145 return;
mbed_official 573:ad23fe03a082 2146 }
mbed_official 573:ad23fe03a082 2147
mbed_official 573:ad23fe03a082 2148 /* Disable RXNE interrupt */
mbed_official 573:ad23fe03a082 2149 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
mbed_official 573:ad23fe03a082 2150
mbed_official 573:ad23fe03a082 2151 if(hspi->TxXferCount == 0)
mbed_official 573:ad23fe03a082 2152 {
mbed_official 573:ad23fe03a082 2153 SPI_CloseRxTx_ISR(hspi);
mbed_official 573:ad23fe03a082 2154 }
mbed_official 573:ad23fe03a082 2155 }
mbed_official 573:ad23fe03a082 2156 }
mbed_official 573:ad23fe03a082 2157
mbed_official 573:ad23fe03a082 2158 /**
mbed_official 573:ad23fe03a082 2159 * @brief Rx Handler for Transmit and Receive in Interrupt mode
mbed_official 573:ad23fe03a082 2160 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 573:ad23fe03a082 2161 * the configuration information for SPI module.
mbed_official 573:ad23fe03a082 2162 * @retval None
mbed_official 573:ad23fe03a082 2163 */
mbed_official 573:ad23fe03a082 2164 static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
mbed_official 573:ad23fe03a082 2165 {
mbed_official 573:ad23fe03a082 2166 __IO uint8_t tmpreg;
mbed_official 573:ad23fe03a082 2167
mbed_official 573:ad23fe03a082 2168 tmpreg = *((__IO uint8_t *)&hspi->Instance->DR);
mbed_official 573:ad23fe03a082 2169 UNUSED(tmpreg); /* To avoid GCC warning */
mbed_official 573:ad23fe03a082 2170
mbed_official 573:ad23fe03a082 2171 hspi->CRCSize--;
mbed_official 573:ad23fe03a082 2172
mbed_official 573:ad23fe03a082 2173 /* check end of the reception */
mbed_official 573:ad23fe03a082 2174 if(hspi->CRCSize == 0)
mbed_official 573:ad23fe03a082 2175 {
mbed_official 573:ad23fe03a082 2176 /* Disable RXNE interrupt */
mbed_official 573:ad23fe03a082 2177 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
mbed_official 573:ad23fe03a082 2178
mbed_official 573:ad23fe03a082 2179 if(hspi->TxXferCount == 0)
mbed_official 573:ad23fe03a082 2180 {
mbed_official 573:ad23fe03a082 2181 SPI_CloseRxTx_ISR(hspi);
mbed_official 573:ad23fe03a082 2182 }
mbed_official 573:ad23fe03a082 2183 }
mbed_official 573:ad23fe03a082 2184 }
mbed_official 573:ad23fe03a082 2185
mbed_official 573:ad23fe03a082 2186 /**
mbed_official 573:ad23fe03a082 2187 * @brief Tx Handler for Transmit and Receive in Interrupt mode
mbed_official 573:ad23fe03a082 2188 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 573:ad23fe03a082 2189 * the configuration information for SPI module.
mbed_official 573:ad23fe03a082 2190 * @retval None
mbed_official 573:ad23fe03a082 2191 */
mbed_official 573:ad23fe03a082 2192 static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
mbed_official 573:ad23fe03a082 2193 {
mbed_official 573:ad23fe03a082 2194 /* Transmit data in packing Bit mode */
mbed_official 573:ad23fe03a082 2195 if(hspi->TxXferCount >= 2)
mbed_official 573:ad23fe03a082 2196 {
mbed_official 573:ad23fe03a082 2197 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
mbed_official 573:ad23fe03a082 2198 hspi->pTxBuffPtr += sizeof(uint16_t);
mbed_official 573:ad23fe03a082 2199 hspi->TxXferCount -= 2;
mbed_official 573:ad23fe03a082 2200 }
mbed_official 573:ad23fe03a082 2201 /* Transmit data in 8 Bit mode */
mbed_official 573:ad23fe03a082 2202 else
mbed_official 573:ad23fe03a082 2203 {
mbed_official 573:ad23fe03a082 2204 *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
mbed_official 573:ad23fe03a082 2205 hspi->TxXferCount--;
mbed_official 573:ad23fe03a082 2206 }
mbed_official 573:ad23fe03a082 2207
mbed_official 573:ad23fe03a082 2208 /* check the end of the transmission */
mbed_official 573:ad23fe03a082 2209 if(hspi->TxXferCount == 0)
mbed_official 573:ad23fe03a082 2210 {
mbed_official 573:ad23fe03a082 2211 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official 573:ad23fe03a082 2212 {
mbed_official 573:ad23fe03a082 2213 hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
mbed_official 573:ad23fe03a082 2214 }
mbed_official 573:ad23fe03a082 2215 /* Disable TXE interrupt */
mbed_official 573:ad23fe03a082 2216 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
mbed_official 573:ad23fe03a082 2217
mbed_official 573:ad23fe03a082 2218 if(hspi->RxXferCount == 0)
mbed_official 573:ad23fe03a082 2219 {
mbed_official 573:ad23fe03a082 2220 SPI_CloseRxTx_ISR(hspi);
mbed_official 573:ad23fe03a082 2221 }
mbed_official 573:ad23fe03a082 2222 }
mbed_official 573:ad23fe03a082 2223 }
mbed_official 573:ad23fe03a082 2224
mbed_official 573:ad23fe03a082 2225 /**
mbed_official 573:ad23fe03a082 2226 * @brief Rx 16Bit Handler for Transmit and Receive in Interrupt mode
mbed_official 573:ad23fe03a082 2227 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 573:ad23fe03a082 2228 * the configuration information for SPI module.
mbed_official 573:ad23fe03a082 2229 * @retval None
mbed_official 573:ad23fe03a082 2230 */
mbed_official 573:ad23fe03a082 2231 static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
mbed_official 573:ad23fe03a082 2232 {
mbed_official 573:ad23fe03a082 2233 /* Receive data in 16 Bit mode */
mbed_official 573:ad23fe03a082 2234 *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
mbed_official 573:ad23fe03a082 2235 hspi->pRxBuffPtr += sizeof(uint16_t);
mbed_official 573:ad23fe03a082 2236 hspi->RxXferCount--;
mbed_official 573:ad23fe03a082 2237
mbed_official 573:ad23fe03a082 2238 if(hspi->RxXferCount == 0)
mbed_official 573:ad23fe03a082 2239 {
mbed_official 573:ad23fe03a082 2240 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official 573:ad23fe03a082 2241 {
mbed_official 573:ad23fe03a082 2242 hspi->RxISR = SPI_2linesRxISR_16BITCRC;
mbed_official 573:ad23fe03a082 2243 return;
mbed_official 573:ad23fe03a082 2244 }
mbed_official 573:ad23fe03a082 2245
mbed_official 573:ad23fe03a082 2246 /* Disable RXNE interrupt */
mbed_official 573:ad23fe03a082 2247 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
mbed_official 573:ad23fe03a082 2248
mbed_official 573:ad23fe03a082 2249 if(hspi->TxXferCount == 0)
mbed_official 573:ad23fe03a082 2250 {
mbed_official 573:ad23fe03a082 2251 SPI_CloseRxTx_ISR(hspi);
mbed_official 573:ad23fe03a082 2252 }
mbed_official 573:ad23fe03a082 2253 }
mbed_official 573:ad23fe03a082 2254 }
mbed_official 573:ad23fe03a082 2255
mbed_official 573:ad23fe03a082 2256 /**
mbed_official 573:ad23fe03a082 2257 * @brief Manage the CRC 16bit receive for Transmit and Receive in Interrupt mode
mbed_official 573:ad23fe03a082 2258 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 573:ad23fe03a082 2259 * the configuration information for SPI module.
mbed_official 573:ad23fe03a082 2260 * @retval None
mbed_official 573:ad23fe03a082 2261 */
mbed_official 573:ad23fe03a082 2262 static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
mbed_official 573:ad23fe03a082 2263 {
mbed_official 573:ad23fe03a082 2264 /* Receive data in 16 Bit mode */
mbed_official 573:ad23fe03a082 2265 __IO uint16_t tmpreg = hspi->Instance->DR;
mbed_official 573:ad23fe03a082 2266 UNUSED(tmpreg); /* To avoid GCC warning */
mbed_official 573:ad23fe03a082 2267
mbed_official 573:ad23fe03a082 2268 /* Disable RXNE interrupt */
mbed_official 573:ad23fe03a082 2269 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
mbed_official 573:ad23fe03a082 2270
mbed_official 573:ad23fe03a082 2271 SPI_CloseRxTx_ISR(hspi);
mbed_official 573:ad23fe03a082 2272 }
mbed_official 573:ad23fe03a082 2273
mbed_official 573:ad23fe03a082 2274 /**
mbed_official 573:ad23fe03a082 2275 * @brief Tx Handler for Transmit and Receive in Interrupt mode
mbed_official 573:ad23fe03a082 2276 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 573:ad23fe03a082 2277 * the configuration information for SPI module.
mbed_official 573:ad23fe03a082 2278 * @retval None
mbed_official 573:ad23fe03a082 2279 */
mbed_official 573:ad23fe03a082 2280 static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
mbed_official 573:ad23fe03a082 2281 {
mbed_official 573:ad23fe03a082 2282 /* Transmit data in 16 Bit mode */
mbed_official 573:ad23fe03a082 2283 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
mbed_official 573:ad23fe03a082 2284 hspi->pTxBuffPtr += sizeof(uint16_t);
mbed_official 573:ad23fe03a082 2285 hspi->TxXferCount--;
mbed_official 573:ad23fe03a082 2286
mbed_official 573:ad23fe03a082 2287 /* Enable CRC Transmission */
mbed_official 573:ad23fe03a082 2288 if(hspi->TxXferCount == 0)
mbed_official 573:ad23fe03a082 2289 {
mbed_official 573:ad23fe03a082 2290 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official 573:ad23fe03a082 2291 {
mbed_official 573:ad23fe03a082 2292 hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
mbed_official 573:ad23fe03a082 2293 }
mbed_official 573:ad23fe03a082 2294 /* Disable TXE interrupt */
mbed_official 573:ad23fe03a082 2295 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
mbed_official 573:ad23fe03a082 2296
mbed_official 573:ad23fe03a082 2297 if(hspi->RxXferCount == 0)
mbed_official 573:ad23fe03a082 2298 {
mbed_official 573:ad23fe03a082 2299 SPI_CloseRxTx_ISR(hspi);
mbed_official 573:ad23fe03a082 2300 }
mbed_official 573:ad23fe03a082 2301 }
mbed_official 573:ad23fe03a082 2302 }
mbed_official 573:ad23fe03a082 2303
mbed_official 573:ad23fe03a082 2304 /**
mbed_official 573:ad23fe03a082 2305 * @brief Manage the CRC receive in Interrupt context
mbed_official 573:ad23fe03a082 2306 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 573:ad23fe03a082 2307 * the configuration information for SPI module.
mbed_official 573:ad23fe03a082 2308 * @retval None
mbed_official 573:ad23fe03a082 2309 */
mbed_official 573:ad23fe03a082 2310 static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
mbed_official 573:ad23fe03a082 2311 {
mbed_official 573:ad23fe03a082 2312 __IO uint8_t tmpreg;
mbed_official 573:ad23fe03a082 2313 tmpreg = *((__IO uint8_t*)&hspi->Instance->DR);
mbed_official 573:ad23fe03a082 2314 UNUSED(tmpreg); /* To avoid GCC warning */
mbed_official 573:ad23fe03a082 2315
mbed_official 573:ad23fe03a082 2316 hspi->CRCSize--;
mbed_official 573:ad23fe03a082 2317
mbed_official 573:ad23fe03a082 2318 if(hspi->CRCSize == 0)
mbed_official 573:ad23fe03a082 2319 {
mbed_official 573:ad23fe03a082 2320 SPI_CloseRx_ISR(hspi);
mbed_official 573:ad23fe03a082 2321 }
mbed_official 573:ad23fe03a082 2322 }
mbed_official 573:ad23fe03a082 2323
mbed_official 573:ad23fe03a082 2324 /**
mbed_official 573:ad23fe03a082 2325 * @brief Manage the receive in Interrupt context
mbed_official 573:ad23fe03a082 2326 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 573:ad23fe03a082 2327 * the configuration information for SPI module.
mbed_official 573:ad23fe03a082 2328 * @retval None
mbed_official 573:ad23fe03a082 2329 */
mbed_official 573:ad23fe03a082 2330 static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
mbed_official 573:ad23fe03a082 2331 {
mbed_official 573:ad23fe03a082 2332 *hspi->pRxBuffPtr++ = (*(__IO uint8_t *)&hspi->Instance->DR);
mbed_official 573:ad23fe03a082 2333 hspi->RxXferCount--;
mbed_official 573:ad23fe03a082 2334
mbed_official 573:ad23fe03a082 2335 /* Enable CRC Transmission */
mbed_official 573:ad23fe03a082 2336 if((hspi->RxXferCount == 1) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
mbed_official 573:ad23fe03a082 2337 {
mbed_official 573:ad23fe03a082 2338 hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
mbed_official 573:ad23fe03a082 2339 }
mbed_official 573:ad23fe03a082 2340
mbed_official 573:ad23fe03a082 2341 if(hspi->RxXferCount == 0)
mbed_official 573:ad23fe03a082 2342 {
mbed_official 573:ad23fe03a082 2343 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official 573:ad23fe03a082 2344 {
mbed_official 573:ad23fe03a082 2345 hspi->RxISR = SPI_RxISR_8BITCRC;
mbed_official 573:ad23fe03a082 2346 return;
mbed_official 573:ad23fe03a082 2347 }
mbed_official 573:ad23fe03a082 2348 SPI_CloseRx_ISR(hspi);
mbed_official 573:ad23fe03a082 2349 }
mbed_official 573:ad23fe03a082 2350 }
mbed_official 573:ad23fe03a082 2351
mbed_official 573:ad23fe03a082 2352 /**
mbed_official 573:ad23fe03a082 2353 * @brief Manage the CRC 16bit receive in Interrupt context
mbed_official 573:ad23fe03a082 2354 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 573:ad23fe03a082 2355 * the configuration information for SPI module.
mbed_official 573:ad23fe03a082 2356 * @retval None
mbed_official 573:ad23fe03a082 2357 */
mbed_official 573:ad23fe03a082 2358 static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
mbed_official 573:ad23fe03a082 2359 {
mbed_official 573:ad23fe03a082 2360 __IO uint16_t tmpreg;
mbed_official 573:ad23fe03a082 2361
mbed_official 573:ad23fe03a082 2362 tmpreg = hspi->Instance->DR;
mbed_official 573:ad23fe03a082 2363 UNUSED(tmpreg); /* To avoid GCC warning */
mbed_official 573:ad23fe03a082 2364
mbed_official 573:ad23fe03a082 2365 /* Disable RXNE and ERR interrupt */
mbed_official 573:ad23fe03a082 2366 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
mbed_official 573:ad23fe03a082 2367
mbed_official 573:ad23fe03a082 2368 SPI_CloseRx_ISR(hspi);
mbed_official 573:ad23fe03a082 2369 }
mbed_official 573:ad23fe03a082 2370
mbed_official 573:ad23fe03a082 2371 /**
mbed_official 573:ad23fe03a082 2372 * @brief Manage the 16Bit receive in Interrupt context
mbed_official 573:ad23fe03a082 2373 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 573:ad23fe03a082 2374 * the configuration information for SPI module.
mbed_official 573:ad23fe03a082 2375 * @retval None
mbed_official 573:ad23fe03a082 2376 */
mbed_official 573:ad23fe03a082 2377 static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
mbed_official 573:ad23fe03a082 2378 {
mbed_official 573:ad23fe03a082 2379 *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR;
mbed_official 573:ad23fe03a082 2380 hspi->pRxBuffPtr += sizeof(uint16_t);
mbed_official 573:ad23fe03a082 2381 hspi->RxXferCount--;
mbed_official 573:ad23fe03a082 2382
mbed_official 573:ad23fe03a082 2383 /* Enable CRC Transmission */
mbed_official 573:ad23fe03a082 2384 if((hspi->RxXferCount == 1) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
mbed_official 573:ad23fe03a082 2385 {
mbed_official 573:ad23fe03a082 2386 hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
mbed_official 573:ad23fe03a082 2387 }
mbed_official 573:ad23fe03a082 2388
mbed_official 573:ad23fe03a082 2389 if(hspi->RxXferCount == 0)
mbed_official 573:ad23fe03a082 2390 {
mbed_official 573:ad23fe03a082 2391 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official 573:ad23fe03a082 2392 {
mbed_official 573:ad23fe03a082 2393 hspi->RxISR = SPI_RxISR_16BITCRC;
mbed_official 573:ad23fe03a082 2394 return;
mbed_official 573:ad23fe03a082 2395 }
mbed_official 573:ad23fe03a082 2396 SPI_CloseRx_ISR(hspi);
mbed_official 573:ad23fe03a082 2397 }
mbed_official 573:ad23fe03a082 2398 }
mbed_official 573:ad23fe03a082 2399
mbed_official 573:ad23fe03a082 2400 /**
mbed_official 573:ad23fe03a082 2401 * @brief Handle the data 8Bit transmit in Interrupt mode
mbed_official 573:ad23fe03a082 2402 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 573:ad23fe03a082 2403 * the configuration information for SPI module.
mbed_official 573:ad23fe03a082 2404 * @retval None
mbed_official 573:ad23fe03a082 2405 */
mbed_official 573:ad23fe03a082 2406 static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
mbed_official 573:ad23fe03a082 2407 {
mbed_official 573:ad23fe03a082 2408 *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
mbed_official 573:ad23fe03a082 2409 hspi->TxXferCount--;
mbed_official 573:ad23fe03a082 2410
mbed_official 573:ad23fe03a082 2411 if(hspi->TxXferCount == 0)
mbed_official 573:ad23fe03a082 2412 {
mbed_official 573:ad23fe03a082 2413 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official 573:ad23fe03a082 2414 {
mbed_official 573:ad23fe03a082 2415 /* Enable CRC Transmission */
mbed_official 573:ad23fe03a082 2416 hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
mbed_official 573:ad23fe03a082 2417 }
mbed_official 573:ad23fe03a082 2418 SPI_CloseTx_ISR(hspi);
mbed_official 573:ad23fe03a082 2419 }
mbed_official 573:ad23fe03a082 2420 }
mbed_official 573:ad23fe03a082 2421
mbed_official 573:ad23fe03a082 2422 /**
mbed_official 573:ad23fe03a082 2423 * @brief Handle the data 16Bit transmit in Interrupt mode
mbed_official 573:ad23fe03a082 2424 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 573:ad23fe03a082 2425 * the configuration information for SPI module.
mbed_official 573:ad23fe03a082 2426 * @retval None
mbed_official 573:ad23fe03a082 2427 */
mbed_official 573:ad23fe03a082 2428 static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
mbed_official 573:ad23fe03a082 2429 {
mbed_official 573:ad23fe03a082 2430 /* Transmit data in 16 Bit mode */
mbed_official 573:ad23fe03a082 2431 hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
mbed_official 573:ad23fe03a082 2432 hspi->pTxBuffPtr += sizeof(uint16_t);
mbed_official 573:ad23fe03a082 2433 hspi->TxXferCount--;
mbed_official 573:ad23fe03a082 2434
mbed_official 573:ad23fe03a082 2435 if(hspi->TxXferCount == 0)
mbed_official 573:ad23fe03a082 2436 {
mbed_official 573:ad23fe03a082 2437 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official 573:ad23fe03a082 2438 {
mbed_official 573:ad23fe03a082 2439 /* Enable CRC Transmission */
mbed_official 573:ad23fe03a082 2440 hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
mbed_official 573:ad23fe03a082 2441 }
mbed_official 573:ad23fe03a082 2442 SPI_CloseTx_ISR(hspi);
mbed_official 573:ad23fe03a082 2443 }
mbed_official 573:ad23fe03a082 2444 }
mbed_official 573:ad23fe03a082 2445
mbed_official 573:ad23fe03a082 2446 /**
mbed_official 573:ad23fe03a082 2447 * @brief This function handles SPI Communication Timeout.
mbed_official 573:ad23fe03a082 2448 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 573:ad23fe03a082 2449 * the configuration information for SPI module.
mbed_official 573:ad23fe03a082 2450 * @param Flag : SPI flag to check
mbed_official 573:ad23fe03a082 2451 * @param State : flag state to check
mbed_official 573:ad23fe03a082 2452 * @param Timeout : Timeout duration
mbed_official 573:ad23fe03a082 2453 * @retval HAL status
mbed_official 573:ad23fe03a082 2454 */
mbed_official 573:ad23fe03a082 2455 static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout)
mbed_official 573:ad23fe03a082 2456 {
mbed_official 573:ad23fe03a082 2457 uint32_t tickstart = HAL_GetTick();
mbed_official 573:ad23fe03a082 2458
mbed_official 573:ad23fe03a082 2459 while((hspi->Instance->SR & Flag) != State)
mbed_official 573:ad23fe03a082 2460 {
mbed_official 573:ad23fe03a082 2461 if(Timeout != HAL_MAX_DELAY)
mbed_official 573:ad23fe03a082 2462 {
mbed_official 573:ad23fe03a082 2463 if((Timeout == 0) || ((HAL_GetTick()-tickstart) >= Timeout))
mbed_official 573:ad23fe03a082 2464 {
mbed_official 573:ad23fe03a082 2465 /* Disable the SPI and reset the CRC: the CRC value should be cleared
mbed_official 573:ad23fe03a082 2466 on both master and slave sides in order to resynchronize the master
mbed_official 573:ad23fe03a082 2467 and slave for their respective CRC calculation */
mbed_official 573:ad23fe03a082 2468
mbed_official 573:ad23fe03a082 2469 /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
mbed_official 573:ad23fe03a082 2470 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
mbed_official 573:ad23fe03a082 2471
mbed_official 573:ad23fe03a082 2472 if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
mbed_official 573:ad23fe03a082 2473 {
mbed_official 573:ad23fe03a082 2474 /* Disable SPI peripheral */
mbed_official 573:ad23fe03a082 2475 __HAL_SPI_DISABLE(hspi);
mbed_official 573:ad23fe03a082 2476 }
mbed_official 573:ad23fe03a082 2477
mbed_official 573:ad23fe03a082 2478 /* Reset CRC Calculation */
mbed_official 573:ad23fe03a082 2479 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official 573:ad23fe03a082 2480 {
mbed_official 573:ad23fe03a082 2481 SPI_RESET_CRC(hspi);
mbed_official 573:ad23fe03a082 2482 }
mbed_official 573:ad23fe03a082 2483
mbed_official 573:ad23fe03a082 2484 hspi->State= HAL_SPI_STATE_READY;
mbed_official 573:ad23fe03a082 2485
mbed_official 573:ad23fe03a082 2486 /* Process Unlocked */
mbed_official 573:ad23fe03a082 2487 __HAL_UNLOCK(hspi);
mbed_official 573:ad23fe03a082 2488
mbed_official 573:ad23fe03a082 2489 return HAL_TIMEOUT;
mbed_official 573:ad23fe03a082 2490 }
mbed_official 573:ad23fe03a082 2491 }
mbed_official 573:ad23fe03a082 2492 }
mbed_official 573:ad23fe03a082 2493
mbed_official 573:ad23fe03a082 2494 return HAL_OK;
mbed_official 573:ad23fe03a082 2495 }
mbed_official 573:ad23fe03a082 2496
mbed_official 573:ad23fe03a082 2497 /**
mbed_official 573:ad23fe03a082 2498 * @brief This function handles SPI Communication Timeout.
mbed_official 573:ad23fe03a082 2499 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 573:ad23fe03a082 2500 * the configuration information for SPI module.
mbed_official 573:ad23fe03a082 2501 * @param Fifo : Fifo to check
mbed_official 573:ad23fe03a082 2502 * @param State : Fifo state to check
mbed_official 573:ad23fe03a082 2503 * @param Timeout : Timeout duration
mbed_official 573:ad23fe03a082 2504 * @retval HAL status
mbed_official 573:ad23fe03a082 2505 */
mbed_official 573:ad23fe03a082 2506 static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, uint32_t Timeout)
mbed_official 573:ad23fe03a082 2507 {
mbed_official 573:ad23fe03a082 2508 __IO uint8_t tmpreg;
mbed_official 573:ad23fe03a082 2509 uint32_t tickstart = HAL_GetTick();
mbed_official 573:ad23fe03a082 2510
mbed_official 573:ad23fe03a082 2511 while((hspi->Instance->SR & Fifo) != State)
mbed_official 573:ad23fe03a082 2512 {
mbed_official 573:ad23fe03a082 2513 if((Fifo == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY))
mbed_official 573:ad23fe03a082 2514 {
mbed_official 573:ad23fe03a082 2515 tmpreg = *((__IO uint8_t*)&hspi->Instance->DR);
mbed_official 573:ad23fe03a082 2516 UNUSED(tmpreg); /* To avoid GCC warning */
mbed_official 573:ad23fe03a082 2517 }
mbed_official 573:ad23fe03a082 2518
mbed_official 573:ad23fe03a082 2519 if(Timeout != HAL_MAX_DELAY)
mbed_official 573:ad23fe03a082 2520 {
mbed_official 573:ad23fe03a082 2521 if((Timeout == 0) || ((HAL_GetTick()-tickstart) >= Timeout))
mbed_official 573:ad23fe03a082 2522 {
mbed_official 573:ad23fe03a082 2523 /* Disable the SPI and reset the CRC: the CRC value should be cleared
mbed_official 573:ad23fe03a082 2524 on both master and slave sides in order to resynchronize the master
mbed_official 573:ad23fe03a082 2525 and slave for their respective CRC calculation */
mbed_official 573:ad23fe03a082 2526
mbed_official 573:ad23fe03a082 2527 /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
mbed_official 573:ad23fe03a082 2528 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
mbed_official 573:ad23fe03a082 2529
mbed_official 573:ad23fe03a082 2530 if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
mbed_official 573:ad23fe03a082 2531 {
mbed_official 573:ad23fe03a082 2532 /* Disable SPI peripheral */
mbed_official 573:ad23fe03a082 2533 __HAL_SPI_DISABLE(hspi);
mbed_official 573:ad23fe03a082 2534 }
mbed_official 573:ad23fe03a082 2535
mbed_official 573:ad23fe03a082 2536 /* Reset CRC Calculation */
mbed_official 573:ad23fe03a082 2537 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official 573:ad23fe03a082 2538 {
mbed_official 573:ad23fe03a082 2539 SPI_RESET_CRC(hspi);
mbed_official 573:ad23fe03a082 2540 }
mbed_official 573:ad23fe03a082 2541
mbed_official 573:ad23fe03a082 2542 hspi->State = HAL_SPI_STATE_READY;
mbed_official 573:ad23fe03a082 2543
mbed_official 573:ad23fe03a082 2544 /* Process Unlocked */
mbed_official 573:ad23fe03a082 2545 __HAL_UNLOCK(hspi);
mbed_official 573:ad23fe03a082 2546
mbed_official 573:ad23fe03a082 2547 return HAL_TIMEOUT;
mbed_official 573:ad23fe03a082 2548 }
mbed_official 573:ad23fe03a082 2549 }
mbed_official 573:ad23fe03a082 2550 }
mbed_official 573:ad23fe03a082 2551
mbed_official 573:ad23fe03a082 2552 return HAL_OK;
mbed_official 573:ad23fe03a082 2553 }
mbed_official 573:ad23fe03a082 2554
mbed_official 573:ad23fe03a082 2555 /**
mbed_official 573:ad23fe03a082 2556 * @brief This function handles the check of the RX transaction complete.
mbed_official 573:ad23fe03a082 2557 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 573:ad23fe03a082 2558 * the configuration information for SPI module.
mbed_official 573:ad23fe03a082 2559 * @param Timeout : Timeout duration
mbed_official 573:ad23fe03a082 2560 * @retval None
mbed_official 573:ad23fe03a082 2561 */
mbed_official 573:ad23fe03a082 2562 static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout)
mbed_official 573:ad23fe03a082 2563 {
mbed_official 573:ad23fe03a082 2564 if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
mbed_official 573:ad23fe03a082 2565 {
mbed_official 573:ad23fe03a082 2566 /* Disable SPI peripheral */
mbed_official 573:ad23fe03a082 2567 __HAL_SPI_DISABLE(hspi);
mbed_official 573:ad23fe03a082 2568 }
mbed_official 573:ad23fe03a082 2569 if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout) != HAL_OK)
mbed_official 573:ad23fe03a082 2570 {
mbed_official 573:ad23fe03a082 2571 hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
mbed_official 573:ad23fe03a082 2572 return HAL_TIMEOUT;
mbed_official 573:ad23fe03a082 2573 }
mbed_official 573:ad23fe03a082 2574 if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout) != HAL_OK)
mbed_official 573:ad23fe03a082 2575 {
mbed_official 573:ad23fe03a082 2576 hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
mbed_official 573:ad23fe03a082 2577 return HAL_TIMEOUT;
mbed_official 573:ad23fe03a082 2578 }
mbed_official 573:ad23fe03a082 2579
mbed_official 573:ad23fe03a082 2580 return HAL_OK;
mbed_official 573:ad23fe03a082 2581 }
mbed_official 573:ad23fe03a082 2582
mbed_official 573:ad23fe03a082 2583 /**
mbed_official 573:ad23fe03a082 2584 * @brief This function handles the check of the RXTX or TX transaction complete.
mbed_official 573:ad23fe03a082 2585 * @param hspi: SPI handle
mbed_official 573:ad23fe03a082 2586 * @param Timeout : Timeout duration
mbed_official 573:ad23fe03a082 2587 */
mbed_official 573:ad23fe03a082 2588 static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout)
mbed_official 573:ad23fe03a082 2589 {
mbed_official 573:ad23fe03a082 2590 /* Procedure to check the transaction complete */
mbed_official 573:ad23fe03a082 2591 if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FTLVL, SPI_FTLVL_EMPTY, Timeout) != HAL_OK)
mbed_official 573:ad23fe03a082 2592 {
mbed_official 573:ad23fe03a082 2593 hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
mbed_official 573:ad23fe03a082 2594 return HAL_TIMEOUT;
mbed_official 573:ad23fe03a082 2595 }
mbed_official 573:ad23fe03a082 2596 if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout) != HAL_OK)
mbed_official 573:ad23fe03a082 2597 {
mbed_official 573:ad23fe03a082 2598 hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
mbed_official 573:ad23fe03a082 2599 return HAL_TIMEOUT;
mbed_official 573:ad23fe03a082 2600 }
mbed_official 573:ad23fe03a082 2601 if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout) != HAL_OK)
mbed_official 573:ad23fe03a082 2602 {
mbed_official 573:ad23fe03a082 2603 hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
mbed_official 573:ad23fe03a082 2604 return HAL_TIMEOUT;
mbed_official 573:ad23fe03a082 2605 }
mbed_official 573:ad23fe03a082 2606 return HAL_OK;
mbed_official 573:ad23fe03a082 2607 }
mbed_official 573:ad23fe03a082 2608
mbed_official 573:ad23fe03a082 2609 /**
mbed_official 573:ad23fe03a082 2610 * @brief This function handles the close of the RXTX transaction.
mbed_official 573:ad23fe03a082 2611 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 573:ad23fe03a082 2612 * the configuration information for SPI module.
mbed_official 573:ad23fe03a082 2613 * @retval None
mbed_official 573:ad23fe03a082 2614 */
mbed_official 573:ad23fe03a082 2615 static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)
mbed_official 573:ad23fe03a082 2616 {
mbed_official 573:ad23fe03a082 2617 /* Disable ERR interrupt */
mbed_official 573:ad23fe03a082 2618 __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
mbed_official 573:ad23fe03a082 2619
mbed_official 573:ad23fe03a082 2620 /* Check if CRC error occurred */
mbed_official 573:ad23fe03a082 2621 if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
mbed_official 573:ad23fe03a082 2622 {
mbed_official 573:ad23fe03a082 2623 hspi->State = HAL_SPI_STATE_READY;
mbed_official 573:ad23fe03a082 2624 hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
mbed_official 573:ad23fe03a082 2625 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
mbed_official 573:ad23fe03a082 2626 HAL_SPI_ErrorCallback(hspi);
mbed_official 573:ad23fe03a082 2627 }
mbed_official 573:ad23fe03a082 2628 else
mbed_official 573:ad23fe03a082 2629 {
mbed_official 573:ad23fe03a082 2630 if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
mbed_official 573:ad23fe03a082 2631 {
mbed_official 573:ad23fe03a082 2632 if(hspi->State == HAL_SPI_STATE_BUSY_RX)
mbed_official 573:ad23fe03a082 2633 {
mbed_official 573:ad23fe03a082 2634 hspi->State = HAL_SPI_STATE_READY;
mbed_official 573:ad23fe03a082 2635 HAL_SPI_RxCpltCallback(hspi);
mbed_official 573:ad23fe03a082 2636 }
mbed_official 573:ad23fe03a082 2637 else
mbed_official 573:ad23fe03a082 2638 {
mbed_official 573:ad23fe03a082 2639 hspi->State = HAL_SPI_STATE_READY;
mbed_official 573:ad23fe03a082 2640 HAL_SPI_TxRxCpltCallback(hspi);
mbed_official 573:ad23fe03a082 2641 }
mbed_official 573:ad23fe03a082 2642 }
mbed_official 573:ad23fe03a082 2643 else
mbed_official 573:ad23fe03a082 2644 {
mbed_official 573:ad23fe03a082 2645 hspi->State = HAL_SPI_STATE_READY;
mbed_official 573:ad23fe03a082 2646 HAL_SPI_ErrorCallback(hspi);
mbed_official 573:ad23fe03a082 2647 }
mbed_official 573:ad23fe03a082 2648 }
mbed_official 573:ad23fe03a082 2649 }
mbed_official 573:ad23fe03a082 2650
mbed_official 573:ad23fe03a082 2651 /**
mbed_official 573:ad23fe03a082 2652 * @brief This function handles the close of the RX transaction.
mbed_official 573:ad23fe03a082 2653 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 573:ad23fe03a082 2654 * the configuration information for SPI module.
mbed_official 573:ad23fe03a082 2655 * @retval None
mbed_official 573:ad23fe03a082 2656 */
mbed_official 573:ad23fe03a082 2657 static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi)
mbed_official 573:ad23fe03a082 2658 {
mbed_official 573:ad23fe03a082 2659 /* Disable RXNE and ERR interrupt */
mbed_official 573:ad23fe03a082 2660 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
mbed_official 573:ad23fe03a082 2661
mbed_official 573:ad23fe03a082 2662 /* Check the end of the transaction */
mbed_official 573:ad23fe03a082 2663 SPI_EndRxTransaction(hspi,SPI_DEFAULT_TIMEOUT);
mbed_official 573:ad23fe03a082 2664
mbed_official 573:ad23fe03a082 2665 hspi->State = HAL_SPI_STATE_READY;
mbed_official 573:ad23fe03a082 2666
mbed_official 573:ad23fe03a082 2667 /* Check if CRC error occurred */
mbed_official 573:ad23fe03a082 2668 if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
mbed_official 573:ad23fe03a082 2669 {
mbed_official 573:ad23fe03a082 2670 hspi->ErrorCode|= HAL_SPI_ERROR_CRC;
mbed_official 573:ad23fe03a082 2671 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
mbed_official 573:ad23fe03a082 2672 HAL_SPI_ErrorCallback(hspi);
mbed_official 573:ad23fe03a082 2673 }
mbed_official 573:ad23fe03a082 2674 else
mbed_official 573:ad23fe03a082 2675 {
mbed_official 573:ad23fe03a082 2676 if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
mbed_official 573:ad23fe03a082 2677 {
mbed_official 573:ad23fe03a082 2678 HAL_SPI_RxCpltCallback(hspi);
mbed_official 573:ad23fe03a082 2679 }
mbed_official 573:ad23fe03a082 2680 else
mbed_official 573:ad23fe03a082 2681 {
mbed_official 573:ad23fe03a082 2682 HAL_SPI_ErrorCallback(hspi);
mbed_official 573:ad23fe03a082 2683 }
mbed_official 573:ad23fe03a082 2684 }
mbed_official 573:ad23fe03a082 2685 }
mbed_official 573:ad23fe03a082 2686
mbed_official 573:ad23fe03a082 2687 /**
mbed_official 573:ad23fe03a082 2688 * @brief This function handles the close of the TX transaction.
mbed_official 573:ad23fe03a082 2689 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 573:ad23fe03a082 2690 * the configuration information for SPI module.
mbed_official 573:ad23fe03a082 2691 * @retval None
mbed_official 573:ad23fe03a082 2692 */
mbed_official 573:ad23fe03a082 2693 static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi)
mbed_official 573:ad23fe03a082 2694 {
mbed_official 573:ad23fe03a082 2695 /* Disable TXE and ERR interrupt */
mbed_official 573:ad23fe03a082 2696 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
mbed_official 573:ad23fe03a082 2697
mbed_official 573:ad23fe03a082 2698 /* Clear OVERUN flag in 2 Lines communication mode because received is not read */
mbed_official 573:ad23fe03a082 2699 if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
mbed_official 573:ad23fe03a082 2700 {
mbed_official 573:ad23fe03a082 2701 __HAL_SPI_CLEAR_OVRFLAG(hspi);
mbed_official 573:ad23fe03a082 2702 }
mbed_official 573:ad23fe03a082 2703
mbed_official 573:ad23fe03a082 2704 hspi->State = HAL_SPI_STATE_READY;
mbed_official 573:ad23fe03a082 2705 if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
mbed_official 573:ad23fe03a082 2706 {
mbed_official 573:ad23fe03a082 2707 HAL_SPI_ErrorCallback(hspi);
mbed_official 573:ad23fe03a082 2708 }
mbed_official 573:ad23fe03a082 2709 else
mbed_official 573:ad23fe03a082 2710 {
mbed_official 573:ad23fe03a082 2711 HAL_SPI_TxCpltCallback(hspi);
mbed_official 573:ad23fe03a082 2712 }
mbed_official 573:ad23fe03a082 2713 }
mbed_official 573:ad23fe03a082 2714
mbed_official 573:ad23fe03a082 2715 /**
mbed_official 573:ad23fe03a082 2716 * @}
mbed_official 573:ad23fe03a082 2717 */
mbed_official 573:ad23fe03a082 2718
mbed_official 573:ad23fe03a082 2719 #endif /* HAL_SPI_MODULE_ENABLED */
mbed_official 573:ad23fe03a082 2720 /**
mbed_official 573:ad23fe03a082 2721 * @}
mbed_official 573:ad23fe03a082 2722 */
mbed_official 573:ad23fe03a082 2723
mbed_official 573:ad23fe03a082 2724 /**
mbed_official 573:ad23fe03a082 2725 * @}
mbed_official 573:ad23fe03a082 2726 */
mbed_official 573:ad23fe03a082 2727
mbed_official 573:ad23fe03a082 2728 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/