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Last commit 20 Feb 2019 by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F7/TARGET_DISCO_F746NG/system_stm32f7xx.c@579:53297373a894, 2015-07-01 (annotated)

Committer:
mbed_official
Date:
Wed Jul 01 09:45:11 2015 +0100
Revision:
579:53297373a894
Parent:
573:ad23fe03a082
Child:
582:a89625bcd809
Synchronized with git revision d5b4d2ab9c47edb4dc5776e7177b0c2263459081



Full URL: https://github.com/mbedmicro/mbed/commit/d5b4d2ab9c47edb4dc5776e7177b0c2263459081/



Initial version of drivers for SAMR21

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 573:ad23fe03a082 1 /**
mbed_official 573:ad23fe03a082 2 ******************************************************************************
mbed_official 573:ad23fe03a082 3 * @file system_stm32f7xx.c
mbed_official 573:ad23fe03a082 4 * @author MCD Application Team
mbed_official 573:ad23fe03a082 5 * @version V1.0.0
mbed_official 573:ad23fe03a082 6 * @date 28-April-2015
mbed_official 573:ad23fe03a082 7 * @brief CMSIS Cortex-M7 Device Peripheral Access Layer System Source File.
mbed_official 573:ad23fe03a082 8 *
mbed_official 573:ad23fe03a082 9 * This file provides two functions and one global variable to be called from
mbed_official 573:ad23fe03a082 10 * user application:
mbed_official 573:ad23fe03a082 11 * - SystemInit(): This function is called at startup just after reset and
mbed_official 573:ad23fe03a082 12 * before branch to main program. This call is made inside
mbed_official 573:ad23fe03a082 13 * the "startup_stm32f7xx.s" file.
mbed_official 573:ad23fe03a082 14 *
mbed_official 573:ad23fe03a082 15 * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
mbed_official 573:ad23fe03a082 16 * by the user application to setup the SysTick
mbed_official 573:ad23fe03a082 17 * timer or configure other parameters.
mbed_official 573:ad23fe03a082 18 *
mbed_official 573:ad23fe03a082 19 * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
mbed_official 573:ad23fe03a082 20 * be called whenever the core clock is changed
mbed_official 573:ad23fe03a082 21 * during program execution.
mbed_official 573:ad23fe03a082 22 *
mbed_official 573:ad23fe03a082 23 * This file configures the system clock as follows:
mbed_official 573:ad23fe03a082 24 *-----------------------------------------------------------------------------
mbed_official 573:ad23fe03a082 25 * System clock source | [1] PLL_HSE_XTAL | [2] PLL_HSI if [1] fails
mbed_official 573:ad23fe03a082 26 * | (external 25MHz xtal) | (internal 16MHz clock)
mbed_official 573:ad23fe03a082 27 *-----------------------------------------------------------------------------
mbed_official 573:ad23fe03a082 28 * SYSCLK(MHz) | 216 | 216
mbed_official 573:ad23fe03a082 29 *-----------------------------------------------------------------------------
mbed_official 573:ad23fe03a082 30 * AHBCLK (MHz) | 216 | 216
mbed_official 573:ad23fe03a082 31 *-----------------------------------------------------------------------------
mbed_official 573:ad23fe03a082 32 * APB1CLK (MHz) | 54 | 54
mbed_official 573:ad23fe03a082 33 *-----------------------------------------------------------------------------
mbed_official 573:ad23fe03a082 34 * APB2CLK (MHz) | 108 | 108
mbed_official 573:ad23fe03a082 35 *-----------------------------------------------------------------------------
mbed_official 573:ad23fe03a082 36 * USB capable | YES | NO
mbed_official 573:ad23fe03a082 37 * with 48 MHz precise clock | |
mbed_official 573:ad23fe03a082 38 *-----------------------------------------------------------------------------
mbed_official 573:ad23fe03a082 39 ******************************************************************************
mbed_official 573:ad23fe03a082 40 * @attention
mbed_official 573:ad23fe03a082 41 *
mbed_official 573:ad23fe03a082 42 * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>
mbed_official 573:ad23fe03a082 43 *
mbed_official 573:ad23fe03a082 44 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 573:ad23fe03a082 45 * are permitted provided that the following conditions are met:
mbed_official 573:ad23fe03a082 46 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 573:ad23fe03a082 47 * this list of conditions and the following disclaimer.
mbed_official 573:ad23fe03a082 48 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 573:ad23fe03a082 49 * this list of conditions and the following disclaimer in the documentation
mbed_official 573:ad23fe03a082 50 * and/or other materials provided with the distribution.
mbed_official 573:ad23fe03a082 51 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 573:ad23fe03a082 52 * may be used to endorse or promote products derived from this software
mbed_official 573:ad23fe03a082 53 * without specific prior written permission.
mbed_official 573:ad23fe03a082 54 *
mbed_official 573:ad23fe03a082 55 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 573:ad23fe03a082 56 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 573:ad23fe03a082 57 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 573:ad23fe03a082 58 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 573:ad23fe03a082 59 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 573:ad23fe03a082 60 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 573:ad23fe03a082 61 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 573:ad23fe03a082 62 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 573:ad23fe03a082 63 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 573:ad23fe03a082 64 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 573:ad23fe03a082 65 *
mbed_official 573:ad23fe03a082 66 ******************************************************************************
mbed_official 573:ad23fe03a082 67 */
mbed_official 573:ad23fe03a082 68
mbed_official 573:ad23fe03a082 69 /** @addtogroup CMSIS
mbed_official 573:ad23fe03a082 70 * @{
mbed_official 573:ad23fe03a082 71 */
mbed_official 573:ad23fe03a082 72
mbed_official 573:ad23fe03a082 73 /** @addtogroup stm32f7xx_system
mbed_official 573:ad23fe03a082 74 * @{
mbed_official 573:ad23fe03a082 75 */
mbed_official 573:ad23fe03a082 76
mbed_official 573:ad23fe03a082 77 /** @addtogroup STM32F7xx_System_Private_Includes
mbed_official 573:ad23fe03a082 78 * @{
mbed_official 573:ad23fe03a082 79 */
mbed_official 573:ad23fe03a082 80
mbed_official 573:ad23fe03a082 81 #include "stm32f7xx.h"
mbed_official 573:ad23fe03a082 82 #include "hal_tick.h"
mbed_official 573:ad23fe03a082 83
mbed_official 573:ad23fe03a082 84 HAL_StatusTypeDef HAL_Init(void);
mbed_official 573:ad23fe03a082 85
mbed_official 573:ad23fe03a082 86 #if !defined (HSE_VALUE)
mbed_official 573:ad23fe03a082 87 #define HSE_VALUE ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */
mbed_official 573:ad23fe03a082 88 #endif /* HSE_VALUE */
mbed_official 573:ad23fe03a082 89
mbed_official 573:ad23fe03a082 90 #if !defined (HSI_VALUE)
mbed_official 573:ad23fe03a082 91 #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
mbed_official 573:ad23fe03a082 92 #endif /* HSI_VALUE */
mbed_official 573:ad23fe03a082 93
mbed_official 573:ad23fe03a082 94 /**
mbed_official 573:ad23fe03a082 95 * @}
mbed_official 573:ad23fe03a082 96 */
mbed_official 573:ad23fe03a082 97
mbed_official 573:ad23fe03a082 98 /** @addtogroup STM32F7xx_System_Private_TypesDefinitions
mbed_official 573:ad23fe03a082 99 * @{
mbed_official 573:ad23fe03a082 100 */
mbed_official 573:ad23fe03a082 101
mbed_official 573:ad23fe03a082 102 /**
mbed_official 573:ad23fe03a082 103 * @}
mbed_official 573:ad23fe03a082 104 */
mbed_official 573:ad23fe03a082 105
mbed_official 573:ad23fe03a082 106 /** @addtogroup STM32F7xx_System_Private_Defines
mbed_official 573:ad23fe03a082 107 * @{
mbed_official 573:ad23fe03a082 108 */
mbed_official 573:ad23fe03a082 109
mbed_official 573:ad23fe03a082 110 /************************* Miscellaneous Configuration ************************/
mbed_official 573:ad23fe03a082 111 /*!< Uncomment the following line if you need to use external SRAM or SDRAM mounted
mbed_official 573:ad23fe03a082 112 on EVAL board as data memory */
mbed_official 573:ad23fe03a082 113 /* #define DATA_IN_ExtSRAM */
mbed_official 573:ad23fe03a082 114 /* #define DATA_IN_ExtSDRAM */
mbed_official 573:ad23fe03a082 115
mbed_official 573:ad23fe03a082 116 #if defined(DATA_IN_ExtSRAM) && defined(DATA_IN_ExtSDRAM)
mbed_official 573:ad23fe03a082 117 #error "Please select DATA_IN_ExtSRAM or DATA_IN_ExtSDRAM "
mbed_official 573:ad23fe03a082 118 #endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */
mbed_official 573:ad23fe03a082 119
mbed_official 573:ad23fe03a082 120 /*!< Uncomment the following line if you need to relocate your vector Table in
mbed_official 573:ad23fe03a082 121 Internal SRAM. */
mbed_official 573:ad23fe03a082 122 /* #define VECT_TAB_SRAM */
mbed_official 573:ad23fe03a082 123 #define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
mbed_official 573:ad23fe03a082 124 This value must be a multiple of 0x200. */
mbed_official 573:ad23fe03a082 125 /******************************************************************************/
mbed_official 573:ad23fe03a082 126
mbed_official 573:ad23fe03a082 127 /**
mbed_official 573:ad23fe03a082 128 * @}
mbed_official 573:ad23fe03a082 129 */
mbed_official 573:ad23fe03a082 130
mbed_official 573:ad23fe03a082 131 /** @addtogroup STM32F7xx_System_Private_Macros
mbed_official 573:ad23fe03a082 132 * @{
mbed_official 573:ad23fe03a082 133 */
mbed_official 573:ad23fe03a082 134
mbed_official 573:ad23fe03a082 135 /* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
mbed_official 573:ad23fe03a082 136 #define USE_PLL_HSE_EXTC (0) /* Use external clock --> NOT USED ON THIS BOARD */
mbed_official 573:ad23fe03a082 137 #define USE_PLL_HSE_XTAL (1) /* Use external xtal */
mbed_official 573:ad23fe03a082 138
mbed_official 573:ad23fe03a082 139 /**
mbed_official 573:ad23fe03a082 140 * @}
mbed_official 573:ad23fe03a082 141 */
mbed_official 573:ad23fe03a082 142
mbed_official 573:ad23fe03a082 143 /** @addtogroup STM32F7xx_System_Private_Variables
mbed_official 573:ad23fe03a082 144 * @{
mbed_official 573:ad23fe03a082 145 */
mbed_official 573:ad23fe03a082 146
mbed_official 573:ad23fe03a082 147 /* This variable is updated in three ways:
mbed_official 573:ad23fe03a082 148 1) by calling CMSIS function SystemCoreClockUpdate()
mbed_official 573:ad23fe03a082 149 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
mbed_official 573:ad23fe03a082 150 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
mbed_official 573:ad23fe03a082 151 Note: If you use this function to configure the system clock; then there
mbed_official 573:ad23fe03a082 152 is no need to call the 2 first functions listed above, since SystemCoreClock
mbed_official 573:ad23fe03a082 153 variable is updated automatically.
mbed_official 573:ad23fe03a082 154 */
mbed_official 573:ad23fe03a082 155 uint32_t SystemCoreClock = HSI_VALUE;
mbed_official 573:ad23fe03a082 156 const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
mbed_official 573:ad23fe03a082 157
mbed_official 573:ad23fe03a082 158 /**
mbed_official 573:ad23fe03a082 159 * @}
mbed_official 573:ad23fe03a082 160 */
mbed_official 573:ad23fe03a082 161
mbed_official 573:ad23fe03a082 162 /** @addtogroup STM32F7xx_System_Private_FunctionPrototypes
mbed_official 573:ad23fe03a082 163 * @{
mbed_official 573:ad23fe03a082 164 */
mbed_official 573:ad23fe03a082 165 #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
mbed_official 573:ad23fe03a082 166 static void SystemInit_ExtMemCtl(void);
mbed_official 573:ad23fe03a082 167 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
mbed_official 573:ad23fe03a082 168
mbed_official 573:ad23fe03a082 169 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
mbed_official 573:ad23fe03a082 170 uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
mbed_official 573:ad23fe03a082 171 #endif
mbed_official 573:ad23fe03a082 172
mbed_official 573:ad23fe03a082 173 uint8_t SetSysClock_PLL_HSI(void);
mbed_official 573:ad23fe03a082 174
mbed_official 573:ad23fe03a082 175 /**
mbed_official 573:ad23fe03a082 176 * @}
mbed_official 573:ad23fe03a082 177 */
mbed_official 573:ad23fe03a082 178
mbed_official 573:ad23fe03a082 179 /** @addtogroup STM32F7xx_System_Private_Functions
mbed_official 573:ad23fe03a082 180 * @{
mbed_official 573:ad23fe03a082 181 */
mbed_official 573:ad23fe03a082 182
mbed_official 573:ad23fe03a082 183 /**
mbed_official 573:ad23fe03a082 184 * @brief Setup the microcontroller system
mbed_official 573:ad23fe03a082 185 * Initialize the Embedded Flash Interface, the PLL and update the
mbed_official 573:ad23fe03a082 186 * SystemFrequency variable.
mbed_official 573:ad23fe03a082 187 * @param None
mbed_official 573:ad23fe03a082 188 * @retval None
mbed_official 573:ad23fe03a082 189 */
mbed_official 573:ad23fe03a082 190 void SystemInit(void)
mbed_official 573:ad23fe03a082 191 {
mbed_official 573:ad23fe03a082 192 /* FPU settings ------------------------------------------------------------*/
mbed_official 573:ad23fe03a082 193 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
mbed_official 573:ad23fe03a082 194 SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
mbed_official 573:ad23fe03a082 195 #endif
mbed_official 573:ad23fe03a082 196 /* Reset the RCC clock configuration to the default reset state ------------*/
mbed_official 573:ad23fe03a082 197 /* Set HSION bit */
mbed_official 573:ad23fe03a082 198 RCC->CR |= (uint32_t)0x00000001;
mbed_official 573:ad23fe03a082 199
mbed_official 573:ad23fe03a082 200 /* Reset CFGR register */
mbed_official 573:ad23fe03a082 201 RCC->CFGR = 0x00000000;
mbed_official 573:ad23fe03a082 202
mbed_official 573:ad23fe03a082 203 /* Reset HSEON, CSSON and PLLON bits */
mbed_official 573:ad23fe03a082 204 RCC->CR &= (uint32_t)0xFEF6FFFF;
mbed_official 573:ad23fe03a082 205
mbed_official 573:ad23fe03a082 206 /* Reset PLLCFGR register */
mbed_official 573:ad23fe03a082 207 RCC->PLLCFGR = 0x24003010;
mbed_official 573:ad23fe03a082 208
mbed_official 573:ad23fe03a082 209 /* Reset HSEBYP bit */
mbed_official 573:ad23fe03a082 210 RCC->CR &= (uint32_t)0xFFFBFFFF;
mbed_official 573:ad23fe03a082 211
mbed_official 573:ad23fe03a082 212 /* Disable all interrupts */
mbed_official 573:ad23fe03a082 213 RCC->CIR = 0x00000000;
mbed_official 573:ad23fe03a082 214
mbed_official 573:ad23fe03a082 215 #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
mbed_official 573:ad23fe03a082 216 SystemInit_ExtMemCtl();
mbed_official 573:ad23fe03a082 217 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
mbed_official 573:ad23fe03a082 218
mbed_official 573:ad23fe03a082 219 /* Configure the Vector Table location add offset address ------------------*/
mbed_official 573:ad23fe03a082 220 #ifdef VECT_TAB_SRAM
mbed_official 573:ad23fe03a082 221 SCB->VTOR = SRAM1_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
mbed_official 573:ad23fe03a082 222 #else
mbed_official 573:ad23fe03a082 223 SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
mbed_official 573:ad23fe03a082 224 #endif
mbed_official 573:ad23fe03a082 225
mbed_official 573:ad23fe03a082 226 /* Configure the Cube driver */
mbed_official 573:ad23fe03a082 227 SystemCoreClock = HSI_VALUE; // At this stage the HSI is used as system clock
mbed_official 573:ad23fe03a082 228 HAL_Init();
mbed_official 573:ad23fe03a082 229
mbed_official 573:ad23fe03a082 230 /* Configure the System clock source, PLL Multiplier and Divider factors,
mbed_official 573:ad23fe03a082 231 AHB/APBx prescalers and Flash settings */
mbed_official 573:ad23fe03a082 232 SetSysClock();
mbed_official 573:ad23fe03a082 233
mbed_official 573:ad23fe03a082 234 /* Reset the timer to avoid issues after the RAM initialization */
mbed_official 573:ad23fe03a082 235 TIM_MST_RESET_ON;
mbed_official 573:ad23fe03a082 236 TIM_MST_RESET_OFF;
mbed_official 573:ad23fe03a082 237 }
mbed_official 573:ad23fe03a082 238
mbed_official 573:ad23fe03a082 239 /**
mbed_official 573:ad23fe03a082 240 * @brief Update SystemCoreClock variable according to Clock Register Values.
mbed_official 573:ad23fe03a082 241 * The SystemCoreClock variable contains the core clock (HCLK), it can
mbed_official 573:ad23fe03a082 242 * be used by the user application to setup the SysTick timer or configure
mbed_official 573:ad23fe03a082 243 * other parameters.
mbed_official 573:ad23fe03a082 244 *
mbed_official 573:ad23fe03a082 245 * @note Each time the core clock (HCLK) changes, this function must be called
mbed_official 573:ad23fe03a082 246 * to update SystemCoreClock variable value. Otherwise, any configuration
mbed_official 573:ad23fe03a082 247 * based on this variable will be incorrect.
mbed_official 573:ad23fe03a082 248 *
mbed_official 573:ad23fe03a082 249 * @note - The system frequency computed by this function is not the real
mbed_official 573:ad23fe03a082 250 * frequency in the chip. It is calculated based on the predefined
mbed_official 573:ad23fe03a082 251 * constant and the selected clock source:
mbed_official 573:ad23fe03a082 252 *
mbed_official 573:ad23fe03a082 253 * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
mbed_official 573:ad23fe03a082 254 *
mbed_official 573:ad23fe03a082 255 * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
mbed_official 573:ad23fe03a082 256 *
mbed_official 573:ad23fe03a082 257 * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
mbed_official 573:ad23fe03a082 258 * or HSI_VALUE(*) multiplied/divided by the PLL factors.
mbed_official 573:ad23fe03a082 259 *
mbed_official 573:ad23fe03a082 260 * (*) HSI_VALUE is a constant defined in stm32f7xx.h file (default value
mbed_official 573:ad23fe03a082 261 * 16 MHz) but the real value may vary depending on the variations
mbed_official 573:ad23fe03a082 262 * in voltage and temperature.
mbed_official 573:ad23fe03a082 263 *
mbed_official 573:ad23fe03a082 264 * (**) HSE_VALUE is a constant defined in stm32f7xx.h file (default value
mbed_official 573:ad23fe03a082 265 * 25 MHz), user has to ensure that HSE_VALUE is same as the real
mbed_official 573:ad23fe03a082 266 * frequency of the crystal used. Otherwise, this function may
mbed_official 573:ad23fe03a082 267 * have wrong result.
mbed_official 573:ad23fe03a082 268 *
mbed_official 573:ad23fe03a082 269 * - The result of this function could be not correct when using fractional
mbed_official 573:ad23fe03a082 270 * value for HSE crystal.
mbed_official 573:ad23fe03a082 271 *
mbed_official 573:ad23fe03a082 272 * @param None
mbed_official 573:ad23fe03a082 273 * @retval None
mbed_official 573:ad23fe03a082 274 */
mbed_official 573:ad23fe03a082 275 void SystemCoreClockUpdate(void)
mbed_official 573:ad23fe03a082 276 {
mbed_official 573:ad23fe03a082 277 uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
mbed_official 573:ad23fe03a082 278
mbed_official 573:ad23fe03a082 279 /* Get SYSCLK source -------------------------------------------------------*/
mbed_official 573:ad23fe03a082 280 tmp = RCC->CFGR & RCC_CFGR_SWS;
mbed_official 573:ad23fe03a082 281
mbed_official 573:ad23fe03a082 282 switch (tmp)
mbed_official 573:ad23fe03a082 283 {
mbed_official 573:ad23fe03a082 284 case 0x00: /* HSI used as system clock source */
mbed_official 573:ad23fe03a082 285 SystemCoreClock = HSI_VALUE;
mbed_official 573:ad23fe03a082 286 break;
mbed_official 573:ad23fe03a082 287 case 0x04: /* HSE used as system clock source */
mbed_official 573:ad23fe03a082 288 SystemCoreClock = HSE_VALUE;
mbed_official 573:ad23fe03a082 289 break;
mbed_official 573:ad23fe03a082 290 case 0x08: /* PLL used as system clock source */
mbed_official 573:ad23fe03a082 291
mbed_official 573:ad23fe03a082 292 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
mbed_official 573:ad23fe03a082 293 SYSCLK = PLL_VCO / PLL_P
mbed_official 573:ad23fe03a082 294 */
mbed_official 573:ad23fe03a082 295 pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
mbed_official 573:ad23fe03a082 296 pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
mbed_official 573:ad23fe03a082 297
mbed_official 573:ad23fe03a082 298 if (pllsource != 0)
mbed_official 573:ad23fe03a082 299 {
mbed_official 573:ad23fe03a082 300 /* HSE used as PLL clock source */
mbed_official 573:ad23fe03a082 301 pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
mbed_official 573:ad23fe03a082 302 }
mbed_official 573:ad23fe03a082 303 else
mbed_official 573:ad23fe03a082 304 {
mbed_official 573:ad23fe03a082 305 /* HSI used as PLL clock source */
mbed_official 573:ad23fe03a082 306 pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
mbed_official 573:ad23fe03a082 307 }
mbed_official 573:ad23fe03a082 308
mbed_official 573:ad23fe03a082 309 pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
mbed_official 573:ad23fe03a082 310 SystemCoreClock = pllvco/pllp;
mbed_official 573:ad23fe03a082 311 break;
mbed_official 573:ad23fe03a082 312 default:
mbed_official 573:ad23fe03a082 313 SystemCoreClock = HSI_VALUE;
mbed_official 573:ad23fe03a082 314 break;
mbed_official 573:ad23fe03a082 315 }
mbed_official 573:ad23fe03a082 316 /* Compute HCLK frequency --------------------------------------------------*/
mbed_official 573:ad23fe03a082 317 /* Get HCLK prescaler */
mbed_official 573:ad23fe03a082 318 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
mbed_official 573:ad23fe03a082 319 /* HCLK frequency */
mbed_official 573:ad23fe03a082 320 SystemCoreClock >>= tmp;
mbed_official 573:ad23fe03a082 321 }
mbed_official 573:ad23fe03a082 322
mbed_official 573:ad23fe03a082 323 #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
mbed_official 573:ad23fe03a082 324 /**
mbed_official 573:ad23fe03a082 325 * @brief Setup the external memory controller.
mbed_official 573:ad23fe03a082 326 * Called in startup_stm32f7xx.s before jump to main.
mbed_official 573:ad23fe03a082 327 * This function configures the external memories (SRAM/SDRAM)
mbed_official 573:ad23fe03a082 328 * This SRAM/SDRAM will be used as program data memory (including heap and stack).
mbed_official 573:ad23fe03a082 329 * @param None
mbed_official 573:ad23fe03a082 330 * @retval None
mbed_official 573:ad23fe03a082 331 */
mbed_official 573:ad23fe03a082 332 void SystemInit_ExtMemCtl(void)
mbed_official 573:ad23fe03a082 333 {
mbed_official 573:ad23fe03a082 334 #if defined (DATA_IN_ExtSDRAM)
mbed_official 573:ad23fe03a082 335 register uint32_t tmpreg = 0, timeout = 0xFFFF;
mbed_official 573:ad23fe03a082 336 register uint32_t index;
mbed_official 573:ad23fe03a082 337
mbed_official 573:ad23fe03a082 338 /* Enable GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface
mbed_official 573:ad23fe03a082 339 clock */
mbed_official 573:ad23fe03a082 340 RCC->AHB1ENR |= 0x000001F8;
mbed_official 573:ad23fe03a082 341
mbed_official 573:ad23fe03a082 342 /* Connect PDx pins to FMC Alternate function */
mbed_official 573:ad23fe03a082 343 GPIOD->AFR[0] = 0x000000CC;
mbed_official 573:ad23fe03a082 344 GPIOD->AFR[1] = 0xCC000CCC;
mbed_official 573:ad23fe03a082 345 /* Configure PDx pins in Alternate function mode */
mbed_official 573:ad23fe03a082 346 GPIOD->MODER = 0xA02A000A;
mbed_official 573:ad23fe03a082 347 /* Configure PDx pins speed to 50 MHz */
mbed_official 573:ad23fe03a082 348 GPIOD->OSPEEDR = 0xA02A000A;
mbed_official 573:ad23fe03a082 349 /* Configure PDx pins Output type to push-pull */
mbed_official 573:ad23fe03a082 350 GPIOD->OTYPER = 0x00000000;
mbed_official 573:ad23fe03a082 351 /* No pull-up, pull-down for PDx pins */
mbed_official 573:ad23fe03a082 352 GPIOD->PUPDR = 0x50150005;
mbed_official 573:ad23fe03a082 353
mbed_official 573:ad23fe03a082 354 /* Connect PEx pins to FMC Alternate function */
mbed_official 573:ad23fe03a082 355 GPIOE->AFR[0] = 0xC00000CC;
mbed_official 573:ad23fe03a082 356 GPIOE->AFR[1] = 0xCCCCCCCC;
mbed_official 573:ad23fe03a082 357 /* Configure PEx pins in Alternate function mode */
mbed_official 573:ad23fe03a082 358 GPIOE->MODER = 0xAAAA800A;
mbed_official 573:ad23fe03a082 359 /* Configure PEx pins speed to 50 MHz */
mbed_official 573:ad23fe03a082 360 GPIOE->OSPEEDR = 0xAAAA800A;
mbed_official 573:ad23fe03a082 361 /* Configure PEx pins Output type to push-pull */
mbed_official 573:ad23fe03a082 362 GPIOE->OTYPER = 0x00000000;
mbed_official 573:ad23fe03a082 363 /* No pull-up, pull-down for PEx pins */
mbed_official 573:ad23fe03a082 364 GPIOE->PUPDR = 0x55554005;
mbed_official 573:ad23fe03a082 365
mbed_official 573:ad23fe03a082 366 /* Connect PFx pins to FMC Alternate function */
mbed_official 573:ad23fe03a082 367 GPIOF->AFR[0] = 0x00CCCCCC;
mbed_official 573:ad23fe03a082 368 GPIOF->AFR[1] = 0xCCCCC000;
mbed_official 573:ad23fe03a082 369 /* Configure PFx pins in Alternate function mode */
mbed_official 573:ad23fe03a082 370 GPIOF->MODER = 0xAA800AAA;
mbed_official 573:ad23fe03a082 371 /* Configure PFx pins speed to 50 MHz */
mbed_official 573:ad23fe03a082 372 GPIOF->OSPEEDR = 0xAA800AAA;
mbed_official 573:ad23fe03a082 373 /* Configure PFx pins Output type to push-pull */
mbed_official 573:ad23fe03a082 374 GPIOF->OTYPER = 0x00000000;
mbed_official 573:ad23fe03a082 375 /* No pull-up, pull-down for PFx pins */
mbed_official 573:ad23fe03a082 376 GPIOF->PUPDR = 0x55400555;
mbed_official 573:ad23fe03a082 377
mbed_official 573:ad23fe03a082 378 /* Connect PGx pins to FMC Alternate function */
mbed_official 573:ad23fe03a082 379 GPIOG->AFR[0] = 0x00CC00CC;
mbed_official 573:ad23fe03a082 380 GPIOG->AFR[1] = 0xC000000C;
mbed_official 573:ad23fe03a082 381 /* Configure PGx pins in Alternate function mode */
mbed_official 573:ad23fe03a082 382 GPIOG->MODER = 0x80020A0A;
mbed_official 573:ad23fe03a082 383 /* Configure PGx pins speed to 50 MHz */
mbed_official 573:ad23fe03a082 384 GPIOG->OSPEEDR = 0x80020A0A;
mbed_official 573:ad23fe03a082 385 /* Configure PGx pins Output type to push-pull */
mbed_official 573:ad23fe03a082 386 GPIOG->OTYPER = 0x00000000;
mbed_official 573:ad23fe03a082 387 /* No pull-up, pull-down for PGx pins */
mbed_official 573:ad23fe03a082 388 GPIOG->PUPDR = 0x40010505;
mbed_official 573:ad23fe03a082 389
mbed_official 573:ad23fe03a082 390 /* Connect PHx pins to FMC Alternate function */
mbed_official 573:ad23fe03a082 391 GPIOH->AFR[0] = 0x00C0CC00;
mbed_official 573:ad23fe03a082 392 GPIOH->AFR[1] = 0xCCCCCCCC;
mbed_official 573:ad23fe03a082 393 /* Configure PHx pins in Alternate function mode */
mbed_official 573:ad23fe03a082 394 GPIOH->MODER = 0xAAAA08A0;
mbed_official 573:ad23fe03a082 395 /* Configure PHx pins speed to 50 MHz */
mbed_official 573:ad23fe03a082 396 GPIOH->OSPEEDR = 0xAAAA08A0;
mbed_official 573:ad23fe03a082 397 /* Configure PHx pins Output type to push-pull */
mbed_official 573:ad23fe03a082 398 GPIOH->OTYPER = 0x00000000;
mbed_official 573:ad23fe03a082 399 /* No pull-up, pull-down for PHx pins */
mbed_official 573:ad23fe03a082 400 GPIOH->PUPDR = 0x55550450;
mbed_official 573:ad23fe03a082 401
mbed_official 573:ad23fe03a082 402 /* Connect PIx pins to FMC Alternate function */
mbed_official 573:ad23fe03a082 403 GPIOI->AFR[0] = 0xCCCCCCCC;
mbed_official 573:ad23fe03a082 404 GPIOI->AFR[1] = 0x00000CC0;
mbed_official 573:ad23fe03a082 405 /* Configure PIx pins in Alternate function mode */
mbed_official 573:ad23fe03a082 406 GPIOI->MODER = 0x0028AAAA;
mbed_official 573:ad23fe03a082 407 /* Configure PIx pins speed to 50 MHz */
mbed_official 573:ad23fe03a082 408 GPIOI->OSPEEDR = 0x0028AAAA;
mbed_official 573:ad23fe03a082 409 /* Configure PIx pins Output type to push-pull */
mbed_official 573:ad23fe03a082 410 GPIOI->OTYPER = 0x00000000;
mbed_official 573:ad23fe03a082 411 /* No pull-up, pull-down for PIx pins */
mbed_official 573:ad23fe03a082 412 GPIOI->PUPDR = 0x00145555;
mbed_official 573:ad23fe03a082 413
mbed_official 573:ad23fe03a082 414 /*-- FMC Configuration ------------------------------------------------------*/
mbed_official 573:ad23fe03a082 415 /* Enable the FMC interface clock */
mbed_official 573:ad23fe03a082 416 RCC->AHB3ENR |= 0x00000001;
mbed_official 573:ad23fe03a082 417
mbed_official 573:ad23fe03a082 418 /* Configure and enable SDRAM bank1 */
mbed_official 573:ad23fe03a082 419 FMC_Bank5_6->SDCR[0] = 0x000019E5;
mbed_official 573:ad23fe03a082 420 FMC_Bank5_6->SDTR[0] = 0x01116361;
mbed_official 573:ad23fe03a082 421
mbed_official 573:ad23fe03a082 422 /* SDRAM initialization sequence */
mbed_official 573:ad23fe03a082 423 /* Clock enable command */
mbed_official 573:ad23fe03a082 424 FMC_Bank5_6->SDCMR = 0x00000011;
mbed_official 573:ad23fe03a082 425 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
mbed_official 573:ad23fe03a082 426 while((tmpreg != 0) && (timeout-- > 0))
mbed_official 573:ad23fe03a082 427 {
mbed_official 573:ad23fe03a082 428 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
mbed_official 573:ad23fe03a082 429 }
mbed_official 573:ad23fe03a082 430
mbed_official 573:ad23fe03a082 431 /* Delay */
mbed_official 573:ad23fe03a082 432 for (index = 0; index<1000; index++);
mbed_official 573:ad23fe03a082 433
mbed_official 573:ad23fe03a082 434 /* PALL command */
mbed_official 573:ad23fe03a082 435 FMC_Bank5_6->SDCMR = 0x00000012;
mbed_official 573:ad23fe03a082 436 timeout = 0xFFFF;
mbed_official 573:ad23fe03a082 437 while((tmpreg != 0) && (timeout-- > 0))
mbed_official 573:ad23fe03a082 438 {
mbed_official 573:ad23fe03a082 439 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
mbed_official 573:ad23fe03a082 440 }
mbed_official 573:ad23fe03a082 441
mbed_official 573:ad23fe03a082 442 /* Auto refresh command */
mbed_official 573:ad23fe03a082 443 FMC_Bank5_6->SDCMR = 0x000000F3;
mbed_official 573:ad23fe03a082 444 timeout = 0xFFFF;
mbed_official 573:ad23fe03a082 445 while((tmpreg != 0) && (timeout-- > 0))
mbed_official 573:ad23fe03a082 446 {
mbed_official 573:ad23fe03a082 447 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
mbed_official 573:ad23fe03a082 448 }
mbed_official 573:ad23fe03a082 449
mbed_official 573:ad23fe03a082 450 /* MRD register program */
mbed_official 573:ad23fe03a082 451 FMC_Bank5_6->SDCMR = 0x00046014;
mbed_official 573:ad23fe03a082 452 timeout = 0xFFFF;
mbed_official 573:ad23fe03a082 453 while((tmpreg != 0) && (timeout-- > 0))
mbed_official 573:ad23fe03a082 454 {
mbed_official 573:ad23fe03a082 455 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
mbed_official 573:ad23fe03a082 456 }
mbed_official 573:ad23fe03a082 457
mbed_official 573:ad23fe03a082 458 /* Set refresh count */
mbed_official 573:ad23fe03a082 459 tmpreg = FMC_Bank5_6->SDRTR;
mbed_official 573:ad23fe03a082 460 FMC_Bank5_6->SDRTR = (tmpreg | (0x00000603<<1));
mbed_official 573:ad23fe03a082 461
mbed_official 573:ad23fe03a082 462 /* Disable write protection */
mbed_official 573:ad23fe03a082 463 tmpreg = FMC_Bank5_6->SDCR[0];
mbed_official 573:ad23fe03a082 464 FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
mbed_official 573:ad23fe03a082 465 #endif /* DATA_IN_ExtSDRAM */
mbed_official 573:ad23fe03a082 466
mbed_official 573:ad23fe03a082 467 #if defined(DATA_IN_ExtSRAM)
mbed_official 573:ad23fe03a082 468 /*-- GPIOs Configuration -----------------------------------------------------*/
mbed_official 573:ad23fe03a082 469 /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
mbed_official 573:ad23fe03a082 470 RCC->AHB1ENR |= 0x00000078;
mbed_official 573:ad23fe03a082 471
mbed_official 573:ad23fe03a082 472 /* Connect PDx pins to FMC Alternate function */
mbed_official 573:ad23fe03a082 473 GPIOD->AFR[0] = 0x00CCC0CC;
mbed_official 573:ad23fe03a082 474 GPIOD->AFR[1] = 0xCCCCCCCC;
mbed_official 573:ad23fe03a082 475 /* Configure PDx pins in Alternate function mode */
mbed_official 573:ad23fe03a082 476 GPIOD->MODER = 0xAAAA0A8A;
mbed_official 573:ad23fe03a082 477 /* Configure PDx pins speed to 100 MHz */
mbed_official 573:ad23fe03a082 478 GPIOD->OSPEEDR = 0xFFFF0FCF;
mbed_official 573:ad23fe03a082 479 /* Configure PDx pins Output type to push-pull */
mbed_official 573:ad23fe03a082 480 GPIOD->OTYPER = 0x00000000;
mbed_official 573:ad23fe03a082 481 /* No pull-up, pull-down for PDx pins */
mbed_official 573:ad23fe03a082 482 GPIOD->PUPDR = 0x55550545;
mbed_official 573:ad23fe03a082 483
mbed_official 573:ad23fe03a082 484 /* Connect PEx pins to FMC Alternate function */
mbed_official 573:ad23fe03a082 485 GPIOE->AFR[0] = 0xC00CC0CC;
mbed_official 573:ad23fe03a082 486 GPIOE->AFR[1] = 0xCCCCCCCC;
mbed_official 573:ad23fe03a082 487 /* Configure PEx pins in Alternate function mode */
mbed_official 573:ad23fe03a082 488 GPIOE->MODER = 0xAAAA828A;
mbed_official 573:ad23fe03a082 489 /* Configure PEx pins speed to 100 MHz */
mbed_official 573:ad23fe03a082 490 GPIOE->OSPEEDR = 0xFFFFC3CF;
mbed_official 573:ad23fe03a082 491 /* Configure PEx pins Output type to push-pull */
mbed_official 573:ad23fe03a082 492 GPIOE->OTYPER = 0x00000000;
mbed_official 573:ad23fe03a082 493 /* No pull-up, pull-down for PEx pins */
mbed_official 573:ad23fe03a082 494 GPIOE->PUPDR = 0x55554145;
mbed_official 573:ad23fe03a082 495
mbed_official 573:ad23fe03a082 496 /* Connect PFx pins to FMC Alternate function */
mbed_official 573:ad23fe03a082 497 GPIOF->AFR[0] = 0x00CCCCCC;
mbed_official 573:ad23fe03a082 498 GPIOF->AFR[1] = 0xCCCC0000;
mbed_official 573:ad23fe03a082 499 /* Configure PFx pins in Alternate function mode */
mbed_official 573:ad23fe03a082 500 GPIOF->MODER = 0xAA000AAA;
mbed_official 573:ad23fe03a082 501 /* Configure PFx pins speed to 100 MHz */
mbed_official 573:ad23fe03a082 502 GPIOF->OSPEEDR = 0xFF000FFF;
mbed_official 573:ad23fe03a082 503 /* Configure PFx pins Output type to push-pull */
mbed_official 573:ad23fe03a082 504 GPIOF->OTYPER = 0x00000000;
mbed_official 573:ad23fe03a082 505 /* No pull-up, pull-down for PFx pins */
mbed_official 573:ad23fe03a082 506 GPIOF->PUPDR = 0x55000555;
mbed_official 573:ad23fe03a082 507
mbed_official 573:ad23fe03a082 508 /* Connect PGx pins to FMC Alternate function */
mbed_official 573:ad23fe03a082 509 GPIOG->AFR[0] = 0x00CCCCCC;
mbed_official 573:ad23fe03a082 510 GPIOG->AFR[1] = 0x000000C0;
mbed_official 573:ad23fe03a082 511 /* Configure PGx pins in Alternate function mode */
mbed_official 573:ad23fe03a082 512 GPIOG->MODER = 0x00200AAA;
mbed_official 573:ad23fe03a082 513 /* Configure PGx pins speed to 100 MHz */
mbed_official 573:ad23fe03a082 514 GPIOG->OSPEEDR = 0x00300FFF;
mbed_official 573:ad23fe03a082 515 /* Configure PGx pins Output type to push-pull */
mbed_official 573:ad23fe03a082 516 GPIOG->OTYPER = 0x00000000;
mbed_official 573:ad23fe03a082 517 /* No pull-up, pull-down for PGx pins */
mbed_official 573:ad23fe03a082 518 GPIOG->PUPDR = 0x00100555;
mbed_official 573:ad23fe03a082 519
mbed_official 573:ad23fe03a082 520 /*-- FMC/FSMC Configuration --------------------------------------------------*/
mbed_official 573:ad23fe03a082 521 /* Enable the FMC/FSMC interface clock */
mbed_official 573:ad23fe03a082 522 RCC->AHB3ENR |= 0x00000001;
mbed_official 573:ad23fe03a082 523
mbed_official 573:ad23fe03a082 524 /* Configure and enable Bank1_SRAM2 */
mbed_official 573:ad23fe03a082 525 FMC_Bank1->BTCR[4] = 0x00001091;
mbed_official 573:ad23fe03a082 526 FMC_Bank1->BTCR[5] = 0x00110212;
mbed_official 573:ad23fe03a082 527 FMC_Bank1E->BWTR[4] = 0x0FFFFFFF;
mbed_official 573:ad23fe03a082 528
mbed_official 573:ad23fe03a082 529 #endif /* DATA_IN_ExtSRAM */
mbed_official 573:ad23fe03a082 530 }
mbed_official 573:ad23fe03a082 531 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
mbed_official 573:ad23fe03a082 532
mbed_official 573:ad23fe03a082 533 /**
mbed_official 573:ad23fe03a082 534 * @brief Configures the System clock source, PLL Multiplier and Divider factors,
mbed_official 573:ad23fe03a082 535 * AHB/APBx prescalers and Flash settings
mbed_official 573:ad23fe03a082 536 * @note This function should be called only once the RCC clock configuration
mbed_official 573:ad23fe03a082 537 * is reset to the default reset state (done in SystemInit() function).
mbed_official 573:ad23fe03a082 538 * @param None
mbed_official 573:ad23fe03a082 539 * @retval None
mbed_official 573:ad23fe03a082 540 */
mbed_official 573:ad23fe03a082 541 void SetSysClock(void)
mbed_official 573:ad23fe03a082 542 {
mbed_official 573:ad23fe03a082 543 /* 1- Try to start with HSE and external clock */
mbed_official 573:ad23fe03a082 544 #if USE_PLL_HSE_EXTC != 0
mbed_official 573:ad23fe03a082 545 if (SetSysClock_PLL_HSE(1) == 0)
mbed_official 573:ad23fe03a082 546 #endif
mbed_official 573:ad23fe03a082 547 {
mbed_official 573:ad23fe03a082 548 /* 2- If fail try to start with HSE and external xtal */
mbed_official 573:ad23fe03a082 549 #if USE_PLL_HSE_XTAL != 0
mbed_official 573:ad23fe03a082 550 if (SetSysClock_PLL_HSE(0) == 0)
mbed_official 573:ad23fe03a082 551 #endif
mbed_official 573:ad23fe03a082 552 {
mbed_official 573:ad23fe03a082 553 /* 3- If fail start with HSI clock */
mbed_official 573:ad23fe03a082 554 if (SetSysClock_PLL_HSI() == 0)
mbed_official 573:ad23fe03a082 555 {
mbed_official 573:ad23fe03a082 556 while(1)
mbed_official 573:ad23fe03a082 557 {
mbed_official 573:ad23fe03a082 558 // [TODO] Put something here to tell the user that a problem occured...
mbed_official 573:ad23fe03a082 559 }
mbed_official 573:ad23fe03a082 560 }
mbed_official 573:ad23fe03a082 561 }
mbed_official 573:ad23fe03a082 562 }
mbed_official 573:ad23fe03a082 563
mbed_official 573:ad23fe03a082 564 // Output clock on MCO2 pin(PC9) for debugging purpose
mbed_official 573:ad23fe03a082 565 // Can be visualized on uSD card CN3 connector pin 8
mbed_official 573:ad23fe03a082 566 //HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_4); // 216 MHz / 4 = 54 MHz
mbed_official 573:ad23fe03a082 567 }
mbed_official 573:ad23fe03a082 568
mbed_official 573:ad23fe03a082 569 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
mbed_official 573:ad23fe03a082 570 /******************************************************************************/
mbed_official 573:ad23fe03a082 571 /* PLL (clocked by HSE) used as System clock source */
mbed_official 573:ad23fe03a082 572 /******************************************************************************/
mbed_official 573:ad23fe03a082 573 uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
mbed_official 573:ad23fe03a082 574 {
mbed_official 573:ad23fe03a082 575 RCC_ClkInitTypeDef RCC_ClkInitStruct;
mbed_official 573:ad23fe03a082 576 RCC_OscInitTypeDef RCC_OscInitStruct;
mbed_official 573:ad23fe03a082 577
mbed_official 573:ad23fe03a082 578 // Enable CPU L1-Cache
mbed_official 573:ad23fe03a082 579 SCB_EnableICache();
mbed_official 573:ad23fe03a082 580 SCB_EnableDCache();
mbed_official 573:ad23fe03a082 581
mbed_official 573:ad23fe03a082 582 // Enable power clock
mbed_official 573:ad23fe03a082 583 __PWR_CLK_ENABLE();
mbed_official 573:ad23fe03a082 584
mbed_official 573:ad23fe03a082 585 // Enable HSE oscillator and activate PLL with HSE as source
mbed_official 573:ad23fe03a082 586 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
mbed_official 573:ad23fe03a082 587 if (bypass == 0)
mbed_official 573:ad23fe03a082 588 {
mbed_official 573:ad23fe03a082 589 RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External xtal on OSC_IN/OSC_OUT */
mbed_official 573:ad23fe03a082 590 }
mbed_official 573:ad23fe03a082 591 else
mbed_official 573:ad23fe03a082 592 {
mbed_official 573:ad23fe03a082 593 RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External clock on OSC_IN */
mbed_official 573:ad23fe03a082 594 }
mbed_official 573:ad23fe03a082 595 // Warning: this configuration is for a 25 MHz xtal clock only
mbed_official 573:ad23fe03a082 596 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
mbed_official 573:ad23fe03a082 597 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
mbed_official 573:ad23fe03a082 598 RCC_OscInitStruct.PLL.PLLM = 25; // VCO input clock = 1 MHz (25 MHz / 25)
mbed_official 573:ad23fe03a082 599 RCC_OscInitStruct.PLL.PLLN = 432; // VCO output clock = 432 MHz (1 MHz * 432)
mbed_official 573:ad23fe03a082 600 RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // PLLCLK = 216 MHz (432 MHz / 2)
mbed_official 573:ad23fe03a082 601 RCC_OscInitStruct.PLL.PLLQ = 9; // USB clock = 48 MHz (432 MHz / 9) --> OK for USB
mbed_official 573:ad23fe03a082 602
mbed_official 573:ad23fe03a082 603 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
mbed_official 573:ad23fe03a082 604 {
mbed_official 573:ad23fe03a082 605 return 0; // FAIL
mbed_official 573:ad23fe03a082 606 }
mbed_official 573:ad23fe03a082 607
mbed_official 573:ad23fe03a082 608 // Activate the OverDrive to reach the 216 MHz Frequency
mbed_official 573:ad23fe03a082 609 if (HAL_PWREx_EnableOverDrive() != HAL_OK)
mbed_official 573:ad23fe03a082 610 {
mbed_official 573:ad23fe03a082 611 return 0; // FAIL
mbed_official 573:ad23fe03a082 612 }
mbed_official 573:ad23fe03a082 613
mbed_official 573:ad23fe03a082 614 // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
mbed_official 573:ad23fe03a082 615 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
mbed_official 573:ad23fe03a082 616 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 216 MHz
mbed_official 573:ad23fe03a082 617 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 216 MHz
mbed_official 573:ad23fe03a082 618 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; // 54 MHz
mbed_official 573:ad23fe03a082 619 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; // 108 MHz
mbed_official 573:ad23fe03a082 620
mbed_official 573:ad23fe03a082 621 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7) != HAL_OK)
mbed_official 573:ad23fe03a082 622 {
mbed_official 573:ad23fe03a082 623 return 0; // FAIL
mbed_official 573:ad23fe03a082 624 }
mbed_official 573:ad23fe03a082 625
mbed_official 573:ad23fe03a082 626 return 1; // OK
mbed_official 573:ad23fe03a082 627 }
mbed_official 573:ad23fe03a082 628 #endif
mbed_official 573:ad23fe03a082 629
mbed_official 573:ad23fe03a082 630 /******************************************************************************/
mbed_official 573:ad23fe03a082 631 /* PLL (clocked by HSI) used as System clock source */
mbed_official 573:ad23fe03a082 632 /******************************************************************************/
mbed_official 573:ad23fe03a082 633 uint8_t SetSysClock_PLL_HSI(void)
mbed_official 573:ad23fe03a082 634 {
mbed_official 573:ad23fe03a082 635 RCC_ClkInitTypeDef RCC_ClkInitStruct;
mbed_official 573:ad23fe03a082 636 RCC_OscInitTypeDef RCC_OscInitStruct;
mbed_official 573:ad23fe03a082 637
mbed_official 573:ad23fe03a082 638 // Enable CPU L1-Cache
mbed_official 573:ad23fe03a082 639 SCB_EnableICache();
mbed_official 573:ad23fe03a082 640 SCB_EnableDCache();
mbed_official 573:ad23fe03a082 641
mbed_official 573:ad23fe03a082 642 // Enable power clock
mbed_official 573:ad23fe03a082 643 __PWR_CLK_ENABLE();
mbed_official 573:ad23fe03a082 644
mbed_official 573:ad23fe03a082 645 // Enable HSI oscillator and activate PLL with HSI as source
mbed_official 573:ad23fe03a082 646 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
mbed_official 573:ad23fe03a082 647 RCC_OscInitStruct.HSIState = RCC_HSI_ON;
mbed_official 573:ad23fe03a082 648 RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
mbed_official 573:ad23fe03a082 649 RCC_OscInitStruct.HSICalibrationValue = 16;
mbed_official 573:ad23fe03a082 650 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
mbed_official 573:ad23fe03a082 651 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
mbed_official 573:ad23fe03a082 652 RCC_OscInitStruct.PLL.PLLM = 16; // VCO input clock = 1 MHz (16 MHz / 16)
mbed_official 573:ad23fe03a082 653 RCC_OscInitStruct.PLL.PLLN = 432; // VCO output clock = 432 MHz (1 MHz * 432)
mbed_official 573:ad23fe03a082 654 RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // PLLCLK = 216 MHz (432 MHz / 2)
mbed_official 573:ad23fe03a082 655 RCC_OscInitStruct.PLL.PLLQ = 9; // USB clock = 48 MHz (432 MHz / 9) --> OK for USB
mbed_official 573:ad23fe03a082 656
mbed_official 573:ad23fe03a082 657 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
mbed_official 573:ad23fe03a082 658 {
mbed_official 573:ad23fe03a082 659 return 0; // FAIL
mbed_official 573:ad23fe03a082 660 }
mbed_official 573:ad23fe03a082 661
mbed_official 573:ad23fe03a082 662 // Activate the OverDrive to reach the 216 MHz Frequency
mbed_official 573:ad23fe03a082 663 if (HAL_PWREx_EnableOverDrive() != HAL_OK)
mbed_official 573:ad23fe03a082 664 {
mbed_official 573:ad23fe03a082 665 return 0; // FAIL
mbed_official 573:ad23fe03a082 666 }
mbed_official 573:ad23fe03a082 667
mbed_official 573:ad23fe03a082 668 // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
mbed_official 573:ad23fe03a082 669 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
mbed_official 573:ad23fe03a082 670 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 216 MHz
mbed_official 573:ad23fe03a082 671 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 216 MHz
mbed_official 573:ad23fe03a082 672 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; // 54 MHz
mbed_official 573:ad23fe03a082 673 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; // 108 MHz
mbed_official 573:ad23fe03a082 674
mbed_official 573:ad23fe03a082 675 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7) != HAL_OK)
mbed_official 573:ad23fe03a082 676 {
mbed_official 573:ad23fe03a082 677 return 0; // FAIL
mbed_official 573:ad23fe03a082 678 }
mbed_official 573:ad23fe03a082 679
mbed_official 573:ad23fe03a082 680 return 1; // OK
mbed_official 573:ad23fe03a082 681 }
mbed_official 573:ad23fe03a082 682
mbed_official 573:ad23fe03a082 683 /**
mbed_official 573:ad23fe03a082 684 * @}
mbed_official 573:ad23fe03a082 685 */
mbed_official 573:ad23fe03a082 686
mbed_official 573:ad23fe03a082 687 /**
mbed_official 573:ad23fe03a082 688 * @}
mbed_official 573:ad23fe03a082 689 */
mbed_official 573:ad23fe03a082 690
mbed_official 573:ad23fe03a082 691 /**
mbed_official 573:ad23fe03a082 692 * @}
mbed_official 573:ad23fe03a082 693 */
mbed_official 573:ad23fe03a082 694 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/