mbed official / mbed-src

mbed library sources

Dependents:   Encrypted my_mbed lklk CyaSSL_DTLS_Cellular ... more

Superseded

This library was superseded by mbed-dev - https://os.mbed.com/users/mbed_official/code/mbed-dev/.

Development branch of the mbed library sources. This library is kept in synch with the latest changes from the mbed SDK and it is not guaranteed to work.

If you are looking for a stable and tested release, please import one of the official mbed library releases:

Import librarymbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Last commit 20 Feb 2019 by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F334C8/system_stm32f3xx.c@579:53297373a894, 2015-07-01 (annotated)

Committer:
mbed_official
Date:
Wed Jul 01 09:45:11 2015 +0100
Revision:
579:53297373a894
Parent:
386:ea0442aaf784 
Synchronized with git revision d5b4d2ab9c47edb4dc5776e7177b0c2263459081



Full URL: https://github.com/mbedmicro/mbed/commit/d5b4d2ab9c47edb4dc5776e7177b0c2263459081/



Initial version of drivers for SAMR21

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 381:5460fc57b6e4 1 /**
mbed_official 381:5460fc57b6e4 2 ******************************************************************************
mbed_official 381:5460fc57b6e4 3 * @file system_stm32f3xx.c
mbed_official 381:5460fc57b6e4 4 * @author MCD Application Team
mbed_official 381:5460fc57b6e4 5 * @version V2.1.0
mbed_official 381:5460fc57b6e4 6 * @date 12-Sept-2014
mbed_official 381:5460fc57b6e4 7 * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
mbed_official 381:5460fc57b6e4 8 *
mbed_official 381:5460fc57b6e4 9 * 1. This file provides two functions and one global variable to be called from
mbed_official 381:5460fc57b6e4 10 * user application:
mbed_official 381:5460fc57b6e4 11 * - SystemInit(): This function is called at startup just after reset and
mbed_official 381:5460fc57b6e4 12 * before branch to main program. This call is made inside
mbed_official 381:5460fc57b6e4 13 * the "startup_stm32f3xx.s" file.
mbed_official 381:5460fc57b6e4 14 *
mbed_official 381:5460fc57b6e4 15 * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
mbed_official 381:5460fc57b6e4 16 * by the user application to setup the SysTick
mbed_official 381:5460fc57b6e4 17 * timer or configure other parameters.
mbed_official 381:5460fc57b6e4 18 *
mbed_official 381:5460fc57b6e4 19 * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
mbed_official 381:5460fc57b6e4 20 * be called whenever the core clock is changed
mbed_official 381:5460fc57b6e4 21 * during program execution.
mbed_official 381:5460fc57b6e4 22 *
mbed_official 381:5460fc57b6e4 23 * 2. After each device reset the HSI (8 MHz) is used as system clock source.
mbed_official 381:5460fc57b6e4 24 * Then SystemInit() function is called, in "startup_stm32f3xx.s" file, to
mbed_official 381:5460fc57b6e4 25 * configure the system clock before to branch to main program.
mbed_official 381:5460fc57b6e4 26 *
mbed_official 381:5460fc57b6e4 27 * 3. This file configures the system clock as follows:
mbed_official 381:5460fc57b6e4 28 *-----------------------------------------------------------------------------
mbed_official 381:5460fc57b6e4 29 * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI
mbed_official 381:5460fc57b6e4 30 * | (external 8 MHz clock) | (internal 8 MHz)
mbed_official 381:5460fc57b6e4 31 * | 2- PLL_HSE_XTAL |
mbed_official 381:5460fc57b6e4 32 * | (external 8 MHz xtal) |
mbed_official 381:5460fc57b6e4 33 *-----------------------------------------------------------------------------
mbed_official 381:5460fc57b6e4 34 * SYSCLK(MHz) | 72 | 64
mbed_official 381:5460fc57b6e4 35 *-----------------------------------------------------------------------------
mbed_official 381:5460fc57b6e4 36 * AHBCLK (MHz) | 72 | 64
mbed_official 381:5460fc57b6e4 37 *-----------------------------------------------------------------------------
mbed_official 381:5460fc57b6e4 38 * APB1CLK (MHz) | 36 | 32
mbed_official 381:5460fc57b6e4 39 *-----------------------------------------------------------------------------
mbed_official 381:5460fc57b6e4 40 * APB2CLK (MHz) | 72 | 64
mbed_official 381:5460fc57b6e4 41 *-----------------------------------------------------------------------------
mbed_official 381:5460fc57b6e4 42 * USB capable (48 MHz precise clock) | NO | NO
mbed_official 381:5460fc57b6e4 43 *-----------------------------------------------------------------------------
mbed_official 381:5460fc57b6e4 44 ******************************************************************************
mbed_official 381:5460fc57b6e4 45 * @attention
mbed_official 381:5460fc57b6e4 46 *
mbed_official 381:5460fc57b6e4 47 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
mbed_official 381:5460fc57b6e4 48 *
mbed_official 381:5460fc57b6e4 49 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 381:5460fc57b6e4 50 * are permitted provided that the following conditions are met:
mbed_official 381:5460fc57b6e4 51 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 381:5460fc57b6e4 52 * this list of conditions and the following disclaimer.
mbed_official 381:5460fc57b6e4 53 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 381:5460fc57b6e4 54 * this list of conditions and the following disclaimer in the documentation
mbed_official 381:5460fc57b6e4 55 * and/or other materials provided with the distribution.
mbed_official 381:5460fc57b6e4 56 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 381:5460fc57b6e4 57 * may be used to endorse or promote products derived from this software
mbed_official 381:5460fc57b6e4 58 * without specific prior written permission.
mbed_official 381:5460fc57b6e4 59 *
mbed_official 381:5460fc57b6e4 60 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 381:5460fc57b6e4 61 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 381:5460fc57b6e4 62 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 381:5460fc57b6e4 63 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 381:5460fc57b6e4 64 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 381:5460fc57b6e4 65 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 381:5460fc57b6e4 66 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 381:5460fc57b6e4 67 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 381:5460fc57b6e4 68 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 381:5460fc57b6e4 69 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 381:5460fc57b6e4 70 *
mbed_official 381:5460fc57b6e4 71 ******************************************************************************
mbed_official 381:5460fc57b6e4 72 */
mbed_official 381:5460fc57b6e4 73
mbed_official 381:5460fc57b6e4 74 /** @addtogroup CMSIS
mbed_official 381:5460fc57b6e4 75 * @{
mbed_official 381:5460fc57b6e4 76 */
mbed_official 381:5460fc57b6e4 77
mbed_official 381:5460fc57b6e4 78 /** @addtogroup stm32f3xx_system
mbed_official 381:5460fc57b6e4 79 * @{
mbed_official 381:5460fc57b6e4 80 */
mbed_official 381:5460fc57b6e4 81
mbed_official 381:5460fc57b6e4 82 /** @addtogroup STM32F3xx_System_Private_Includes
mbed_official 381:5460fc57b6e4 83 * @{
mbed_official 381:5460fc57b6e4 84 */
mbed_official 381:5460fc57b6e4 85
mbed_official 381:5460fc57b6e4 86 #include "stm32f3xx.h"
mbed_official 381:5460fc57b6e4 87 #include "hal_tick.h"
mbed_official 381:5460fc57b6e4 88
mbed_official 381:5460fc57b6e4 89 /**
mbed_official 381:5460fc57b6e4 90 * @}
mbed_official 381:5460fc57b6e4 91 */
mbed_official 381:5460fc57b6e4 92
mbed_official 381:5460fc57b6e4 93 /** @addtogroup STM32F3xx_System_Private_TypesDefinitions
mbed_official 381:5460fc57b6e4 94 * @{
mbed_official 381:5460fc57b6e4 95 */
mbed_official 381:5460fc57b6e4 96
mbed_official 381:5460fc57b6e4 97 /**
mbed_official 381:5460fc57b6e4 98 * @}
mbed_official 381:5460fc57b6e4 99 */
mbed_official 381:5460fc57b6e4 100
mbed_official 381:5460fc57b6e4 101 /** @addtogroup STM32F3xx_System_Private_Defines
mbed_official 381:5460fc57b6e4 102 * @{
mbed_official 381:5460fc57b6e4 103 */
mbed_official 381:5460fc57b6e4 104 #if !defined (HSE_VALUE)
mbed_official 381:5460fc57b6e4 105 #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz.
mbed_official 381:5460fc57b6e4 106 This value can be provided and adapted by the user application. */
mbed_official 381:5460fc57b6e4 107 #endif /* HSE_VALUE */
mbed_official 381:5460fc57b6e4 108
mbed_official 381:5460fc57b6e4 109 #if !defined (HSI_VALUE)
mbed_official 381:5460fc57b6e4 110 #define HSI_VALUE ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz.
mbed_official 381:5460fc57b6e4 111 This value can be provided and adapted by the user application. */
mbed_official 381:5460fc57b6e4 112 #endif /* HSI_VALUE */
mbed_official 381:5460fc57b6e4 113
mbed_official 381:5460fc57b6e4 114 /*!< Uncomment the following line if you need to relocate your vector Table in
mbed_official 381:5460fc57b6e4 115 Internal SRAM. */
mbed_official 381:5460fc57b6e4 116 /* #define VECT_TAB_SRAM */
mbed_official 381:5460fc57b6e4 117 #define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field.
mbed_official 381:5460fc57b6e4 118 This value must be a multiple of 0x200. */
mbed_official 381:5460fc57b6e4 119 /**
mbed_official 381:5460fc57b6e4 120 * @}
mbed_official 381:5460fc57b6e4 121 */
mbed_official 381:5460fc57b6e4 122
mbed_official 381:5460fc57b6e4 123 /** @addtogroup STM32F3xx_System_Private_Macros
mbed_official 381:5460fc57b6e4 124 * @{
mbed_official 381:5460fc57b6e4 125 */
mbed_official 381:5460fc57b6e4 126
mbed_official 381:5460fc57b6e4 127 /* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
mbed_official 381:5460fc57b6e4 128 #define USE_PLL_HSE_EXTC (1) /* Use external clock */
mbed_official 381:5460fc57b6e4 129 #define USE_PLL_HSE_XTAL (1) /* Use external xtal */
mbed_official 381:5460fc57b6e4 130
mbed_official 381:5460fc57b6e4 131 /**
mbed_official 381:5460fc57b6e4 132 * @}
mbed_official 381:5460fc57b6e4 133 */
mbed_official 381:5460fc57b6e4 134
mbed_official 381:5460fc57b6e4 135 /** @addtogroup STM32F3xx_System_Private_Variables
mbed_official 381:5460fc57b6e4 136 * @{
mbed_official 381:5460fc57b6e4 137 */
mbed_official 381:5460fc57b6e4 138 /* This variable is updated in three ways:
mbed_official 381:5460fc57b6e4 139 1) by calling CMSIS function SystemCoreClockUpdate()
mbed_official 381:5460fc57b6e4 140 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
mbed_official 381:5460fc57b6e4 141 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
mbed_official 381:5460fc57b6e4 142 Note: If you use this function to configure the system clock there is no need to
mbed_official 381:5460fc57b6e4 143 call the 2 first functions listed above, since SystemCoreClock variable is
mbed_official 381:5460fc57b6e4 144 updated automatically.
mbed_official 381:5460fc57b6e4 145 */
mbed_official 381:5460fc57b6e4 146 uint32_t SystemCoreClock = 72000000;
mbed_official 381:5460fc57b6e4 147 const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
mbed_official 381:5460fc57b6e4 148
mbed_official 381:5460fc57b6e4 149 /**
mbed_official 381:5460fc57b6e4 150 * @}
mbed_official 381:5460fc57b6e4 151 */
mbed_official 381:5460fc57b6e4 152
mbed_official 381:5460fc57b6e4 153 /** @addtogroup STM32F3xx_System_Private_FunctionPrototypes
mbed_official 381:5460fc57b6e4 154 * @{
mbed_official 381:5460fc57b6e4 155 */
mbed_official 381:5460fc57b6e4 156
mbed_official 381:5460fc57b6e4 157 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
mbed_official 381:5460fc57b6e4 158 uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
mbed_official 381:5460fc57b6e4 159 #endif
mbed_official 381:5460fc57b6e4 160
mbed_official 381:5460fc57b6e4 161 uint8_t SetSysClock_PLL_HSI(void);
mbed_official 381:5460fc57b6e4 162
mbed_official 381:5460fc57b6e4 163 /**
mbed_official 381:5460fc57b6e4 164 * @}
mbed_official 381:5460fc57b6e4 165 */
mbed_official 381:5460fc57b6e4 166
mbed_official 381:5460fc57b6e4 167 /** @addtogroup STM32F3xx_System_Private_Functions
mbed_official 381:5460fc57b6e4 168 * @{
mbed_official 381:5460fc57b6e4 169 */
mbed_official 381:5460fc57b6e4 170
mbed_official 381:5460fc57b6e4 171 /**
mbed_official 381:5460fc57b6e4 172 * @brief Setup the microcontroller system
mbed_official 381:5460fc57b6e4 173 * Initialize the FPU setting, vector table location and the PLL configuration is reset.
mbed_official 381:5460fc57b6e4 174 * @param None
mbed_official 381:5460fc57b6e4 175 * @retval None
mbed_official 381:5460fc57b6e4 176 */
mbed_official 381:5460fc57b6e4 177 void SystemInit(void)
mbed_official 381:5460fc57b6e4 178 {
mbed_official 381:5460fc57b6e4 179 /* FPU settings ------------------------------------------------------------*/
mbed_official 381:5460fc57b6e4 180 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
mbed_official 381:5460fc57b6e4 181 SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
mbed_official 381:5460fc57b6e4 182 #endif
mbed_official 381:5460fc57b6e4 183
mbed_official 381:5460fc57b6e4 184 /* Reset the RCC clock configuration to the default reset state ------------*/
mbed_official 381:5460fc57b6e4 185 /* Set HSION bit */
mbed_official 381:5460fc57b6e4 186 RCC->CR |= (uint32_t)0x00000001;
mbed_official 381:5460fc57b6e4 187
mbed_official 381:5460fc57b6e4 188 /* Reset CFGR register */
mbed_official 381:5460fc57b6e4 189 RCC->CFGR &= 0xF87FC00C;
mbed_official 381:5460fc57b6e4 190
mbed_official 381:5460fc57b6e4 191 /* Reset HSEON, CSSON and PLLON bits */
mbed_official 381:5460fc57b6e4 192 RCC->CR &= (uint32_t)0xFEF6FFFF;
mbed_official 381:5460fc57b6e4 193
mbed_official 381:5460fc57b6e4 194 /* Reset HSEBYP bit */
mbed_official 381:5460fc57b6e4 195 RCC->CR &= (uint32_t)0xFFFBFFFF;
mbed_official 381:5460fc57b6e4 196
mbed_official 381:5460fc57b6e4 197 /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE bits */
mbed_official 381:5460fc57b6e4 198 RCC->CFGR &= (uint32_t)0xFF80FFFF;
mbed_official 381:5460fc57b6e4 199
mbed_official 381:5460fc57b6e4 200 /* Reset PREDIV1[3:0] bits */
mbed_official 381:5460fc57b6e4 201 RCC->CFGR2 &= (uint32_t)0xFFFFFFF0;
mbed_official 381:5460fc57b6e4 202
mbed_official 381:5460fc57b6e4 203 /* Reset USARTSW[1:0], I2CSW and TIMs bits */
mbed_official 381:5460fc57b6e4 204 RCC->CFGR3 &= (uint32_t)0xFF00FCCC;
mbed_official 381:5460fc57b6e4 205
mbed_official 381:5460fc57b6e4 206 /* Disable all interrupts */
mbed_official 381:5460fc57b6e4 207 RCC->CIR = 0x00000000;
mbed_official 381:5460fc57b6e4 208
mbed_official 381:5460fc57b6e4 209 #ifdef VECT_TAB_SRAM
mbed_official 381:5460fc57b6e4 210 SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
mbed_official 381:5460fc57b6e4 211 #else
mbed_official 381:5460fc57b6e4 212 SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
mbed_official 381:5460fc57b6e4 213 #endif
mbed_official 381:5460fc57b6e4 214
mbed_official 381:5460fc57b6e4 215 /* Configure the Cube driver */
mbed_official 381:5460fc57b6e4 216 SystemCoreClock = 8000000; // At this stage the HSI is used as system clock
mbed_official 381:5460fc57b6e4 217 HAL_Init();
mbed_official 381:5460fc57b6e4 218
mbed_official 381:5460fc57b6e4 219 /* Configure the System clock source, PLL Multiplier and Divider factors,
mbed_official 381:5460fc57b6e4 220 AHB/APBx prescalers and Flash settings */
mbed_official 381:5460fc57b6e4 221 SetSysClock();
mbed_official 381:5460fc57b6e4 222
mbed_official 381:5460fc57b6e4 223 /* Reset the timer to avoid issues after the RAM initialization */
mbed_official 381:5460fc57b6e4 224 TIM_MST_RESET_ON;
mbed_official 381:5460fc57b6e4 225 TIM_MST_RESET_OFF;
mbed_official 381:5460fc57b6e4 226 }
mbed_official 381:5460fc57b6e4 227
mbed_official 381:5460fc57b6e4 228 /**
mbed_official 381:5460fc57b6e4 229 * @brief Update SystemCoreClock variable according to Clock Register Values.
mbed_official 381:5460fc57b6e4 230 * The SystemCoreClock variable contains the core clock (HCLK), it can
mbed_official 381:5460fc57b6e4 231 * be used by the user application to setup the SysTick timer or configure
mbed_official 381:5460fc57b6e4 232 * other parameters.
mbed_official 381:5460fc57b6e4 233 *
mbed_official 381:5460fc57b6e4 234 * @note Each time the core clock (HCLK) changes, this function must be called
mbed_official 381:5460fc57b6e4 235 * to update SystemCoreClock variable value. Otherwise, any configuration
mbed_official 381:5460fc57b6e4 236 * based on this variable will be incorrect.
mbed_official 381:5460fc57b6e4 237 *
mbed_official 381:5460fc57b6e4 238 * @note - The system frequency computed by this function is not the real
mbed_official 381:5460fc57b6e4 239 * frequency in the chip. It is calculated based on the predefined
mbed_official 381:5460fc57b6e4 240 * constant and the selected clock source:
mbed_official 381:5460fc57b6e4 241 *
mbed_official 381:5460fc57b6e4 242 * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
mbed_official 381:5460fc57b6e4 243 *
mbed_official 381:5460fc57b6e4 244 * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
mbed_official 381:5460fc57b6e4 245 *
mbed_official 381:5460fc57b6e4 246 * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
mbed_official 381:5460fc57b6e4 247 * or HSI_VALUE(*) multiplied/divided by the PLL factors.
mbed_official 381:5460fc57b6e4 248 *
mbed_official 381:5460fc57b6e4 249 * (*) HSI_VALUE is a constant defined in stm32f3xx_hal.h file (default value
mbed_official 381:5460fc57b6e4 250 * 8 MHz) but the real value may vary depending on the variations
mbed_official 381:5460fc57b6e4 251 * in voltage and temperature.
mbed_official 381:5460fc57b6e4 252 *
mbed_official 381:5460fc57b6e4 253 * (**) HSE_VALUE is a constant defined in stm32f3xx_hal.h file (default value
mbed_official 381:5460fc57b6e4 254 * 8 MHz), user has to ensure that HSE_VALUE is same as the real
mbed_official 381:5460fc57b6e4 255 * frequency of the crystal used. Otherwise, this function may
mbed_official 381:5460fc57b6e4 256 * have wrong result.
mbed_official 381:5460fc57b6e4 257 *
mbed_official 381:5460fc57b6e4 258 * - The result of this function could be not correct when using fractional
mbed_official 381:5460fc57b6e4 259 * value for HSE crystal.
mbed_official 381:5460fc57b6e4 260 *
mbed_official 381:5460fc57b6e4 261 * @param None
mbed_official 381:5460fc57b6e4 262 * @retval None
mbed_official 381:5460fc57b6e4 263 */
mbed_official 381:5460fc57b6e4 264 void SystemCoreClockUpdate (void)
mbed_official 381:5460fc57b6e4 265 {
mbed_official 381:5460fc57b6e4 266 uint32_t tmp = 0, pllmull = 0, pllsource = 0, predivfactor = 0;
mbed_official 381:5460fc57b6e4 267
mbed_official 381:5460fc57b6e4 268 /* Get SYSCLK source -------------------------------------------------------*/
mbed_official 381:5460fc57b6e4 269 tmp = RCC->CFGR & RCC_CFGR_SWS;
mbed_official 381:5460fc57b6e4 270
mbed_official 381:5460fc57b6e4 271 switch (tmp)
mbed_official 381:5460fc57b6e4 272 {
mbed_official 381:5460fc57b6e4 273 case RCC_CFGR_SWS_HSI: /* HSI used as system clock */
mbed_official 381:5460fc57b6e4 274 SystemCoreClock = HSI_VALUE;
mbed_official 381:5460fc57b6e4 275 break;
mbed_official 381:5460fc57b6e4 276 case RCC_CFGR_SWS_HSE: /* HSE used as system clock */
mbed_official 381:5460fc57b6e4 277 SystemCoreClock = HSE_VALUE;
mbed_official 381:5460fc57b6e4 278 break;
mbed_official 381:5460fc57b6e4 279 case RCC_CFGR_SWS_PLL: /* PLL used as system clock */
mbed_official 381:5460fc57b6e4 280 /* Get PLL clock source and multiplication factor ----------------------*/
mbed_official 381:5460fc57b6e4 281 pllmull = RCC->CFGR & RCC_CFGR_PLLMUL;
mbed_official 381:5460fc57b6e4 282 pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
mbed_official 381:5460fc57b6e4 283 pllmull = ( pllmull >> 18) + 2;
mbed_official 381:5460fc57b6e4 284
mbed_official 381:5460fc57b6e4 285 #if defined (STM32F302xE) || defined (STM32F303xE) || defined (STM32F398xx)
mbed_official 381:5460fc57b6e4 286 predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
mbed_official 381:5460fc57b6e4 287 if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV)
mbed_official 381:5460fc57b6e4 288 {
mbed_official 381:5460fc57b6e4 289 /* HSE oscillator clock selected as PREDIV1 clock entry */
mbed_official 381:5460fc57b6e4 290 SystemCoreClock = (HSE_VALUE / predivfactor) * pllmull;
mbed_official 381:5460fc57b6e4 291 }
mbed_official 381:5460fc57b6e4 292 else
mbed_official 381:5460fc57b6e4 293 {
mbed_official 381:5460fc57b6e4 294 /* HSI oscillator clock selected as PREDIV1 clock entry */
mbed_official 381:5460fc57b6e4 295 SystemCoreClock = (HSI_VALUE / predivfactor) * pllmull;
mbed_official 381:5460fc57b6e4 296 }
mbed_official 381:5460fc57b6e4 297 #else
mbed_official 381:5460fc57b6e4 298 if (pllsource == RCC_CFGR_PLLSRC_HSI_DIV2)
mbed_official 381:5460fc57b6e4 299 {
mbed_official 381:5460fc57b6e4 300 /* HSI oscillator clock divided by 2 selected as PLL clock entry */
mbed_official 381:5460fc57b6e4 301 SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
mbed_official 381:5460fc57b6e4 302 }
mbed_official 381:5460fc57b6e4 303 else
mbed_official 381:5460fc57b6e4 304 {
mbed_official 381:5460fc57b6e4 305 predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
mbed_official 381:5460fc57b6e4 306 /* HSE oscillator clock selected as PREDIV1 clock entry */
mbed_official 381:5460fc57b6e4 307 SystemCoreClock = (HSE_VALUE / predivfactor) * pllmull;
mbed_official 381:5460fc57b6e4 308 }
mbed_official 381:5460fc57b6e4 309 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
mbed_official 381:5460fc57b6e4 310 break;
mbed_official 381:5460fc57b6e4 311 default: /* HSI used as system clock */
mbed_official 381:5460fc57b6e4 312 SystemCoreClock = HSI_VALUE;
mbed_official 381:5460fc57b6e4 313 break;
mbed_official 381:5460fc57b6e4 314 }
mbed_official 381:5460fc57b6e4 315 /* Compute HCLK clock frequency ----------------*/
mbed_official 381:5460fc57b6e4 316 /* Get HCLK prescaler */
mbed_official 381:5460fc57b6e4 317 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
mbed_official 381:5460fc57b6e4 318 /* HCLK clock frequency */
mbed_official 381:5460fc57b6e4 319 SystemCoreClock >>= tmp;
mbed_official 381:5460fc57b6e4 320 }
mbed_official 381:5460fc57b6e4 321
mbed_official 381:5460fc57b6e4 322 /**
mbed_official 381:5460fc57b6e4 323 * @brief Configures the System clock source, PLL Multiplier and Divider factors,
mbed_official 381:5460fc57b6e4 324 * AHB/APBx prescalers and Flash settings
mbed_official 381:5460fc57b6e4 325 * @note This function should be called only once the RCC clock configuration
mbed_official 381:5460fc57b6e4 326 * is reset to the default reset state (done in SystemInit() function).
mbed_official 381:5460fc57b6e4 327 * @param None
mbed_official 381:5460fc57b6e4 328 * @retval None
mbed_official 381:5460fc57b6e4 329 */
mbed_official 381:5460fc57b6e4 330 void SetSysClock(void)
mbed_official 381:5460fc57b6e4 331 {
mbed_official 381:5460fc57b6e4 332 /* 1- Try to start with HSE and external clock */
mbed_official 381:5460fc57b6e4 333 #if USE_PLL_HSE_EXTC != 0
mbed_official 381:5460fc57b6e4 334 if (SetSysClock_PLL_HSE(1) == 0)
mbed_official 381:5460fc57b6e4 335 #endif
mbed_official 381:5460fc57b6e4 336 {
mbed_official 381:5460fc57b6e4 337 /* 2- If fail try to start with HSE and external xtal */
mbed_official 381:5460fc57b6e4 338 #if USE_PLL_HSE_XTAL != 0
mbed_official 381:5460fc57b6e4 339 if (SetSysClock_PLL_HSE(0) == 0)
mbed_official 381:5460fc57b6e4 340 #endif
mbed_official 381:5460fc57b6e4 341 {
mbed_official 381:5460fc57b6e4 342 /* 3- If fail start with HSI clock */
mbed_official 381:5460fc57b6e4 343 if (SetSysClock_PLL_HSI() == 0)
mbed_official 381:5460fc57b6e4 344 {
mbed_official 381:5460fc57b6e4 345 while(1)
mbed_official 381:5460fc57b6e4 346 {
mbed_official 381:5460fc57b6e4 347 // [TODO] Put something here to tell the user that a problem occured...
mbed_official 381:5460fc57b6e4 348 }
mbed_official 381:5460fc57b6e4 349 }
mbed_official 381:5460fc57b6e4 350 }
mbed_official 381:5460fc57b6e4 351 }
mbed_official 381:5460fc57b6e4 352
mbed_official 381:5460fc57b6e4 353 /* Output clock on MCO1 pin(PA8) for debugging purpose */
mbed_official 381:5460fc57b6e4 354 //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_SYSCLK, RCC_MCO_DIV1); // 72 MHz or 64 MHz
mbed_official 381:5460fc57b6e4 355 }
mbed_official 381:5460fc57b6e4 356
mbed_official 381:5460fc57b6e4 357 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
mbed_official 381:5460fc57b6e4 358 /******************************************************************************/
mbed_official 381:5460fc57b6e4 359 /* PLL (clocked by HSE) used as System clock source */
mbed_official 381:5460fc57b6e4 360 /******************************************************************************/
mbed_official 381:5460fc57b6e4 361 uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
mbed_official 381:5460fc57b6e4 362 {
mbed_official 381:5460fc57b6e4 363 RCC_ClkInitTypeDef RCC_ClkInitStruct;
mbed_official 381:5460fc57b6e4 364 RCC_OscInitTypeDef RCC_OscInitStruct;
mbed_official 381:5460fc57b6e4 365
mbed_official 381:5460fc57b6e4 366 /* Enable HSE oscillator and activate PLL with HSE as source */
mbed_official 381:5460fc57b6e4 367 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
mbed_official 381:5460fc57b6e4 368 if (bypass == 0)
mbed_official 381:5460fc57b6e4 369 {
mbed_official 381:5460fc57b6e4 370 RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */
mbed_official 381:5460fc57b6e4 371 }
mbed_official 381:5460fc57b6e4 372 else
mbed_official 381:5460fc57b6e4 373 {
mbed_official 381:5460fc57b6e4 374 RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
mbed_official 381:5460fc57b6e4 375 }
mbed_official 381:5460fc57b6e4 376 RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1;
mbed_official 381:5460fc57b6e4 377 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
mbed_official 381:5460fc57b6e4 378 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
mbed_official 381:5460fc57b6e4 379 RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9; // 72 MHz (8 MHz * 9)
mbed_official 381:5460fc57b6e4 380 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
mbed_official 381:5460fc57b6e4 381 {
mbed_official 381:5460fc57b6e4 382 return 0; // FAIL
mbed_official 381:5460fc57b6e4 383 }
mbed_official 381:5460fc57b6e4 384
mbed_official 381:5460fc57b6e4 385 /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
mbed_official 381:5460fc57b6e4 386 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
mbed_official 381:5460fc57b6e4 387 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 72 MHz
mbed_official 381:5460fc57b6e4 388 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 72 MHz
mbed_official 381:5460fc57b6e4 389 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 36 MHz
mbed_official 381:5460fc57b6e4 390 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 72 MHz
mbed_official 381:5460fc57b6e4 391 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
mbed_official 381:5460fc57b6e4 392 {
mbed_official 381:5460fc57b6e4 393 return 0; // FAIL
mbed_official 381:5460fc57b6e4 394 }
mbed_official 381:5460fc57b6e4 395
mbed_official 381:5460fc57b6e4 396 /* Output clock on MCO1 pin(PA8) for debugging purpose */
mbed_official 381:5460fc57b6e4 397 //if (bypass == 0)
mbed_official 381:5460fc57b6e4 398 // HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV2); // 4 MHz with xtal
mbed_official 381:5460fc57b6e4 399 //else
mbed_official 381:5460fc57b6e4 400 // HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV1); // 8 MHz with ext clock
mbed_official 381:5460fc57b6e4 401
mbed_official 381:5460fc57b6e4 402 return 1; // OK
mbed_official 381:5460fc57b6e4 403 }
mbed_official 381:5460fc57b6e4 404 #endif
mbed_official 381:5460fc57b6e4 405
mbed_official 381:5460fc57b6e4 406 /******************************************************************************/
mbed_official 381:5460fc57b6e4 407 /* PLL (clocked by HSI) used as System clock source */
mbed_official 381:5460fc57b6e4 408 /******************************************************************************/
mbed_official 381:5460fc57b6e4 409 uint8_t SetSysClock_PLL_HSI(void)
mbed_official 381:5460fc57b6e4 410 {
mbed_official 381:5460fc57b6e4 411 RCC_ClkInitTypeDef RCC_ClkInitStruct;
mbed_official 381:5460fc57b6e4 412 RCC_OscInitTypeDef RCC_OscInitStruct;
mbed_official 381:5460fc57b6e4 413
mbed_official 381:5460fc57b6e4 414 /* Enable HSI oscillator and activate PLL with HSI as source */
mbed_official 381:5460fc57b6e4 415 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
mbed_official 381:5460fc57b6e4 416 RCC_OscInitStruct.HSIState = RCC_HSI_ON;
mbed_official 381:5460fc57b6e4 417 RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
mbed_official 381:5460fc57b6e4 418 RCC_OscInitStruct.HSICalibrationValue = 16;
mbed_official 381:5460fc57b6e4 419 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
mbed_official 381:5460fc57b6e4 420 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
mbed_official 381:5460fc57b6e4 421 RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL16; // 64 MHz (8 MHz/2 * 16)
mbed_official 381:5460fc57b6e4 422 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
mbed_official 381:5460fc57b6e4 423 {
mbed_official 381:5460fc57b6e4 424 return 0; // FAIL
mbed_official 381:5460fc57b6e4 425 }
mbed_official 381:5460fc57b6e4 426
mbed_official 381:5460fc57b6e4 427 /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
mbed_official 381:5460fc57b6e4 428 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
mbed_official 381:5460fc57b6e4 429 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 64 MHz
mbed_official 381:5460fc57b6e4 430 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 64 MHz
mbed_official 381:5460fc57b6e4 431 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 32 MHz
mbed_official 381:5460fc57b6e4 432 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 64 MHz
mbed_official 381:5460fc57b6e4 433 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
mbed_official 381:5460fc57b6e4 434 {
mbed_official 381:5460fc57b6e4 435 return 0; // FAIL
mbed_official 381:5460fc57b6e4 436 }
mbed_official 381:5460fc57b6e4 437
mbed_official 381:5460fc57b6e4 438 /* Output clock on MCO1 pin(PA8) for debugging purpose */
mbed_official 381:5460fc57b6e4 439 //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSI, RCC_MCO_DIV1); // 8 MHz
mbed_official 381:5460fc57b6e4 440
mbed_official 381:5460fc57b6e4 441 return 1; // OK
mbed_official 381:5460fc57b6e4 442 }
mbed_official 381:5460fc57b6e4 443
mbed_official 381:5460fc57b6e4 444 /**
mbed_official 381:5460fc57b6e4 445 * @}
mbed_official 381:5460fc57b6e4 446 */
mbed_official 381:5460fc57b6e4 447
mbed_official 381:5460fc57b6e4 448 /**
mbed_official 381:5460fc57b6e4 449 * @}
mbed_official 381:5460fc57b6e4 450 */
mbed_official 381:5460fc57b6e4 451
mbed_official 381:5460fc57b6e4 452 /**
mbed_official 381:5460fc57b6e4 453 * @}
mbed_official 381:5460fc57b6e4 454 */
mbed_official 381:5460fc57b6e4 455
mbed_official 381:5460fc57b6e4 456 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
mbed_official 381:5460fc57b6e4 457