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Last commit 20 Feb 2019 by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F303VC/system_stm32f3xx.c@579:53297373a894, 2015-07-01 (annotated)

Committer:
mbed_official
Date:
Wed Jul 01 09:45:11 2015 +0100
Revision:
579:53297373a894
Parent:
403:91a4bea587f4 
Synchronized with git revision d5b4d2ab9c47edb4dc5776e7177b0c2263459081



Full URL: https://github.com/mbedmicro/mbed/commit/d5b4d2ab9c47edb4dc5776e7177b0c2263459081/



Initial version of drivers for SAMR21

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 403:91a4bea587f4 1 /**
mbed_official 403:91a4bea587f4 2 ******************************************************************************
mbed_official 403:91a4bea587f4 3 * @file system_stm32f3xx.c
mbed_official 403:91a4bea587f4 4 * @author MCD Application Team
mbed_official 403:91a4bea587f4 5 * @version V2.1.0
mbed_official 403:91a4bea587f4 6 * @date 12-Sept-2014
mbed_official 403:91a4bea587f4 7 * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
mbed_official 403:91a4bea587f4 8 *
mbed_official 403:91a4bea587f4 9 * 1. This file provides two functions and one global variable to be called from
mbed_official 403:91a4bea587f4 10 * user application:
mbed_official 403:91a4bea587f4 11 * - SystemInit(): This function is called at startup just after reset and
mbed_official 403:91a4bea587f4 12 * before branch to main program. This call is made inside
mbed_official 403:91a4bea587f4 13 * the "startup_stm32f3xx.s" file.
mbed_official 403:91a4bea587f4 14 *
mbed_official 403:91a4bea587f4 15 * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
mbed_official 403:91a4bea587f4 16 * by the user application to setup the SysTick
mbed_official 403:91a4bea587f4 17 * timer or configure other parameters.
mbed_official 403:91a4bea587f4 18 *
mbed_official 403:91a4bea587f4 19 * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
mbed_official 403:91a4bea587f4 20 * be called whenever the core clock is changed
mbed_official 403:91a4bea587f4 21 * during program execution.
mbed_official 403:91a4bea587f4 22 *
mbed_official 403:91a4bea587f4 23 * 2. After each device reset the HSI (8 MHz) is used as system clock source.
mbed_official 403:91a4bea587f4 24 * Then SystemInit() function is called, in "startup_stm32f3xx.s" file, to
mbed_official 403:91a4bea587f4 25 * configure the system clock before to branch to main program.
mbed_official 403:91a4bea587f4 26 *
mbed_official 403:91a4bea587f4 27 * 3. This file configures the system clock as follows:
mbed_official 403:91a4bea587f4 28 *-----------------------------------------------------------------------------
mbed_official 403:91a4bea587f4 29 * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI
mbed_official 403:91a4bea587f4 30 * | (external 8 MHz clock) | (internal 8 MHz)
mbed_official 403:91a4bea587f4 31 * | 2- PLL_HSE_XTAL |
mbed_official 403:91a4bea587f4 32 * | (external 8 MHz xtal) |
mbed_official 403:91a4bea587f4 33 *-----------------------------------------------------------------------------
mbed_official 403:91a4bea587f4 34 * SYSCLK(MHz) | 72 | 64
mbed_official 403:91a4bea587f4 35 *-----------------------------------------------------------------------------
mbed_official 403:91a4bea587f4 36 * AHBCLK (MHz) | 72 | 64
mbed_official 403:91a4bea587f4 37 *-----------------------------------------------------------------------------
mbed_official 403:91a4bea587f4 38 * APB1CLK (MHz) | 36 | 32
mbed_official 403:91a4bea587f4 39 *-----------------------------------------------------------------------------
mbed_official 403:91a4bea587f4 40 * APB2CLK (MHz) | 72 | 64
mbed_official 403:91a4bea587f4 41 *-----------------------------------------------------------------------------
mbed_official 403:91a4bea587f4 42 * USB capable (48 MHz precise clock) | NO | NO
mbed_official 403:91a4bea587f4 43 *-----------------------------------------------------------------------------
mbed_official 403:91a4bea587f4 44 ******************************************************************************
mbed_official 403:91a4bea587f4 45 * @attention
mbed_official 403:91a4bea587f4 46 *
mbed_official 403:91a4bea587f4 47 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
mbed_official 403:91a4bea587f4 48 *
mbed_official 403:91a4bea587f4 49 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 403:91a4bea587f4 50 * are permitted provided that the following conditions are met:
mbed_official 403:91a4bea587f4 51 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 403:91a4bea587f4 52 * this list of conditions and the following disclaimer.
mbed_official 403:91a4bea587f4 53 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 403:91a4bea587f4 54 * this list of conditions and the following disclaimer in the documentation
mbed_official 403:91a4bea587f4 55 * and/or other materials provided with the distribution.
mbed_official 403:91a4bea587f4 56 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 403:91a4bea587f4 57 * may be used to endorse or promote products derived from this software
mbed_official 403:91a4bea587f4 58 * without specific prior written permission.
mbed_official 403:91a4bea587f4 59 *
mbed_official 403:91a4bea587f4 60 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 403:91a4bea587f4 61 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 403:91a4bea587f4 62 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 403:91a4bea587f4 63 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 403:91a4bea587f4 64 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 403:91a4bea587f4 65 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 403:91a4bea587f4 66 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 403:91a4bea587f4 67 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 403:91a4bea587f4 68 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 403:91a4bea587f4 69 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 403:91a4bea587f4 70 *
mbed_official 403:91a4bea587f4 71 ******************************************************************************
mbed_official 403:91a4bea587f4 72 */
mbed_official 403:91a4bea587f4 73
mbed_official 403:91a4bea587f4 74 /** @addtogroup CMSIS
mbed_official 403:91a4bea587f4 75 * @{
mbed_official 403:91a4bea587f4 76 */
mbed_official 403:91a4bea587f4 77
mbed_official 403:91a4bea587f4 78 /** @addtogroup stm32f3xx_system
mbed_official 403:91a4bea587f4 79 * @{
mbed_official 403:91a4bea587f4 80 */
mbed_official 403:91a4bea587f4 81
mbed_official 403:91a4bea587f4 82 /** @addtogroup STM32F3xx_System_Private_Includes
mbed_official 403:91a4bea587f4 83 * @{
mbed_official 403:91a4bea587f4 84 */
mbed_official 403:91a4bea587f4 85
mbed_official 403:91a4bea587f4 86 #include "stm32f3xx.h"
mbed_official 403:91a4bea587f4 87 #include "hal_tick.h"
mbed_official 403:91a4bea587f4 88
mbed_official 403:91a4bea587f4 89 #include "stm32f3xx_hal.h"
mbed_official 403:91a4bea587f4 90
mbed_official 403:91a4bea587f4 91 /**
mbed_official 403:91a4bea587f4 92 * @}
mbed_official 403:91a4bea587f4 93 */
mbed_official 403:91a4bea587f4 94
mbed_official 403:91a4bea587f4 95 /** @addtogroup STM32F3xx_System_Private_TypesDefinitions
mbed_official 403:91a4bea587f4 96 * @{
mbed_official 403:91a4bea587f4 97 */
mbed_official 403:91a4bea587f4 98
mbed_official 403:91a4bea587f4 99 /**
mbed_official 403:91a4bea587f4 100 * @}
mbed_official 403:91a4bea587f4 101 */
mbed_official 403:91a4bea587f4 102
mbed_official 403:91a4bea587f4 103 /** @addtogroup STM32F3xx_System_Private_Defines
mbed_official 403:91a4bea587f4 104 * @{
mbed_official 403:91a4bea587f4 105 */
mbed_official 403:91a4bea587f4 106 #if !defined (HSE_VALUE)
mbed_official 403:91a4bea587f4 107 #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz.
mbed_official 403:91a4bea587f4 108 This value can be provided and adapted by the user application. */
mbed_official 403:91a4bea587f4 109 #endif /* HSE_VALUE */
mbed_official 403:91a4bea587f4 110
mbed_official 403:91a4bea587f4 111 #if !defined (HSI_VALUE)
mbed_official 403:91a4bea587f4 112 #define HSI_VALUE ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz.
mbed_official 403:91a4bea587f4 113 This value can be provided and adapted by the user application. */
mbed_official 403:91a4bea587f4 114 #endif /* HSI_VALUE */
mbed_official 403:91a4bea587f4 115
mbed_official 403:91a4bea587f4 116 /*!< Uncomment the following line if you need to relocate your vector Table in
mbed_official 403:91a4bea587f4 117 Internal SRAM. */
mbed_official 403:91a4bea587f4 118 /* #define VECT_TAB_SRAM */
mbed_official 403:91a4bea587f4 119 #define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field.
mbed_official 403:91a4bea587f4 120 This value must be a multiple of 0x200. */
mbed_official 403:91a4bea587f4 121 /**
mbed_official 403:91a4bea587f4 122 * @}
mbed_official 403:91a4bea587f4 123 */
mbed_official 403:91a4bea587f4 124
mbed_official 403:91a4bea587f4 125 /** @addtogroup STM32F3xx_System_Private_Macros
mbed_official 403:91a4bea587f4 126 * @{
mbed_official 403:91a4bea587f4 127 */
mbed_official 403:91a4bea587f4 128
mbed_official 403:91a4bea587f4 129 /* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
mbed_official 403:91a4bea587f4 130 #define USE_PLL_HSE_EXTC (1) /* Use external clock */
mbed_official 403:91a4bea587f4 131 #define USE_PLL_HSE_XTAL (1) /* Use external xtal */
mbed_official 403:91a4bea587f4 132
mbed_official 403:91a4bea587f4 133 /**
mbed_official 403:91a4bea587f4 134 * @}
mbed_official 403:91a4bea587f4 135 */
mbed_official 403:91a4bea587f4 136
mbed_official 403:91a4bea587f4 137 /** @addtogroup STM32F3xx_System_Private_Variables
mbed_official 403:91a4bea587f4 138 * @{
mbed_official 403:91a4bea587f4 139 */
mbed_official 403:91a4bea587f4 140 /* This variable is updated in three ways:
mbed_official 403:91a4bea587f4 141 1) by calling CMSIS function SystemCoreClockUpdate()
mbed_official 403:91a4bea587f4 142 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
mbed_official 403:91a4bea587f4 143 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
mbed_official 403:91a4bea587f4 144 Note: If you use this function to configure the system clock there is no need to
mbed_official 403:91a4bea587f4 145 call the 2 first functions listed above, since SystemCoreClock variable is
mbed_official 403:91a4bea587f4 146 updated automatically.
mbed_official 403:91a4bea587f4 147 */
mbed_official 403:91a4bea587f4 148 uint32_t SystemCoreClock = 72000000;
mbed_official 403:91a4bea587f4 149 const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
mbed_official 403:91a4bea587f4 150
mbed_official 403:91a4bea587f4 151 /**
mbed_official 403:91a4bea587f4 152 * @}
mbed_official 403:91a4bea587f4 153 */
mbed_official 403:91a4bea587f4 154
mbed_official 403:91a4bea587f4 155 /** @addtogroup STM32F3xx_System_Private_FunctionPrototypes
mbed_official 403:91a4bea587f4 156 * @{
mbed_official 403:91a4bea587f4 157 */
mbed_official 403:91a4bea587f4 158
mbed_official 403:91a4bea587f4 159 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
mbed_official 403:91a4bea587f4 160 uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
mbed_official 403:91a4bea587f4 161 #endif
mbed_official 403:91a4bea587f4 162
mbed_official 403:91a4bea587f4 163 uint8_t SetSysClock_PLL_HSI(void);
mbed_official 403:91a4bea587f4 164
mbed_official 403:91a4bea587f4 165 /**
mbed_official 403:91a4bea587f4 166 * @}
mbed_official 403:91a4bea587f4 167 */
mbed_official 403:91a4bea587f4 168
mbed_official 403:91a4bea587f4 169 /** @addtogroup STM32F3xx_System_Private_Functions
mbed_official 403:91a4bea587f4 170 * @{
mbed_official 403:91a4bea587f4 171 */
mbed_official 403:91a4bea587f4 172
mbed_official 403:91a4bea587f4 173 /**
mbed_official 403:91a4bea587f4 174 * @brief Setup the microcontroller system
mbed_official 403:91a4bea587f4 175 * Initialize the FPU setting, vector table location and the PLL configuration is reset.
mbed_official 403:91a4bea587f4 176 * @param None
mbed_official 403:91a4bea587f4 177 * @retval None
mbed_official 403:91a4bea587f4 178 */
mbed_official 403:91a4bea587f4 179 void SystemInit(void)
mbed_official 403:91a4bea587f4 180 {
mbed_official 403:91a4bea587f4 181 /* FPU settings ------------------------------------------------------------*/
mbed_official 403:91a4bea587f4 182 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
mbed_official 403:91a4bea587f4 183 SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
mbed_official 403:91a4bea587f4 184 #endif
mbed_official 403:91a4bea587f4 185
mbed_official 403:91a4bea587f4 186 /* Reset the RCC clock configuration to the default reset state ------------*/
mbed_official 403:91a4bea587f4 187 /* Set HSION bit */
mbed_official 403:91a4bea587f4 188 RCC->CR |= (uint32_t)0x00000001;
mbed_official 403:91a4bea587f4 189
mbed_official 403:91a4bea587f4 190 /* Reset CFGR register */
mbed_official 403:91a4bea587f4 191 RCC->CFGR &= 0xF87FC00C;
mbed_official 403:91a4bea587f4 192
mbed_official 403:91a4bea587f4 193 /* Reset HSEON, CSSON and PLLON bits */
mbed_official 403:91a4bea587f4 194 RCC->CR &= (uint32_t)0xFEF6FFFF;
mbed_official 403:91a4bea587f4 195
mbed_official 403:91a4bea587f4 196 /* Reset HSEBYP bit */
mbed_official 403:91a4bea587f4 197 RCC->CR &= (uint32_t)0xFFFBFFFF;
mbed_official 403:91a4bea587f4 198
mbed_official 403:91a4bea587f4 199 /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE bits */
mbed_official 403:91a4bea587f4 200 RCC->CFGR &= (uint32_t)0xFF80FFFF;
mbed_official 403:91a4bea587f4 201
mbed_official 403:91a4bea587f4 202 /* Reset PREDIV1[3:0] bits */
mbed_official 403:91a4bea587f4 203 RCC->CFGR2 &= (uint32_t)0xFFFFFFF0;
mbed_official 403:91a4bea587f4 204
mbed_official 403:91a4bea587f4 205 /* Reset USARTSW[1:0], I2CSW and TIMs bits */
mbed_official 403:91a4bea587f4 206 RCC->CFGR3 &= (uint32_t)0xFF00FCCC;
mbed_official 403:91a4bea587f4 207
mbed_official 403:91a4bea587f4 208 /* Disable all interrupts */
mbed_official 403:91a4bea587f4 209 RCC->CIR = 0x00000000;
mbed_official 403:91a4bea587f4 210
mbed_official 403:91a4bea587f4 211 #ifdef VECT_TAB_SRAM
mbed_official 403:91a4bea587f4 212 SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
mbed_official 403:91a4bea587f4 213 #else
mbed_official 403:91a4bea587f4 214 SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
mbed_official 403:91a4bea587f4 215 #endif
mbed_official 403:91a4bea587f4 216
mbed_official 403:91a4bea587f4 217 /* Configure the Cube driver */
mbed_official 403:91a4bea587f4 218 SystemCoreClock = 8000000; // At this stage the HSI is used as system clock
mbed_official 403:91a4bea587f4 219 HAL_Init();
mbed_official 403:91a4bea587f4 220
mbed_official 403:91a4bea587f4 221 /* Configure the System clock source, PLL Multiplier and Divider factors,
mbed_official 403:91a4bea587f4 222 AHB/APBx prescalers and Flash settings */
mbed_official 403:91a4bea587f4 223 SetSysClock();
mbed_official 403:91a4bea587f4 224
mbed_official 403:91a4bea587f4 225 /* Reset the timer to avoid issues after the RAM initialization */
mbed_official 403:91a4bea587f4 226 TIM_MST_RESET_ON;
mbed_official 403:91a4bea587f4 227 TIM_MST_RESET_OFF;
mbed_official 403:91a4bea587f4 228 }
mbed_official 403:91a4bea587f4 229
mbed_official 403:91a4bea587f4 230 /**
mbed_official 403:91a4bea587f4 231 * @brief Update SystemCoreClock variable according to Clock Register Values.
mbed_official 403:91a4bea587f4 232 * The SystemCoreClock variable contains the core clock (HCLK), it can
mbed_official 403:91a4bea587f4 233 * be used by the user application to setup the SysTick timer or configure
mbed_official 403:91a4bea587f4 234 * other parameters.
mbed_official 403:91a4bea587f4 235 *
mbed_official 403:91a4bea587f4 236 * @note Each time the core clock (HCLK) changes, this function must be called
mbed_official 403:91a4bea587f4 237 * to update SystemCoreClock variable value. Otherwise, any configuration
mbed_official 403:91a4bea587f4 238 * based on this variable will be incorrect.
mbed_official 403:91a4bea587f4 239 *
mbed_official 403:91a4bea587f4 240 * @note - The system frequency computed by this function is not the real
mbed_official 403:91a4bea587f4 241 * frequency in the chip. It is calculated based on the predefined
mbed_official 403:91a4bea587f4 242 * constant and the selected clock source:
mbed_official 403:91a4bea587f4 243 *
mbed_official 403:91a4bea587f4 244 * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
mbed_official 403:91a4bea587f4 245 *
mbed_official 403:91a4bea587f4 246 * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
mbed_official 403:91a4bea587f4 247 *
mbed_official 403:91a4bea587f4 248 * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
mbed_official 403:91a4bea587f4 249 * or HSI_VALUE(*) multiplied/divided by the PLL factors.
mbed_official 403:91a4bea587f4 250 *
mbed_official 403:91a4bea587f4 251 * (*) HSI_VALUE is a constant defined in stm32f3xx_hal.h file (default value
mbed_official 403:91a4bea587f4 252 * 8 MHz) but the real value may vary depending on the variations
mbed_official 403:91a4bea587f4 253 * in voltage and temperature.
mbed_official 403:91a4bea587f4 254 *
mbed_official 403:91a4bea587f4 255 * (**) HSE_VALUE is a constant defined in stm32f3xx_hal.h file (default value
mbed_official 403:91a4bea587f4 256 * 8 MHz), user has to ensure that HSE_VALUE is same as the real
mbed_official 403:91a4bea587f4 257 * frequency of the crystal used. Otherwise, this function may
mbed_official 403:91a4bea587f4 258 * have wrong result.
mbed_official 403:91a4bea587f4 259 *
mbed_official 403:91a4bea587f4 260 * - The result of this function could be not correct when using fractional
mbed_official 403:91a4bea587f4 261 * value for HSE crystal.
mbed_official 403:91a4bea587f4 262 *
mbed_official 403:91a4bea587f4 263 * @param None
mbed_official 403:91a4bea587f4 264 * @retval None
mbed_official 403:91a4bea587f4 265 */
mbed_official 403:91a4bea587f4 266 void SystemCoreClockUpdate (void)
mbed_official 403:91a4bea587f4 267 {
mbed_official 403:91a4bea587f4 268 uint32_t tmp = 0, pllmull = 0, pllsource = 0, predivfactor = 0;
mbed_official 403:91a4bea587f4 269
mbed_official 403:91a4bea587f4 270 /* Get SYSCLK source -------------------------------------------------------*/
mbed_official 403:91a4bea587f4 271 tmp = RCC->CFGR & RCC_CFGR_SWS;
mbed_official 403:91a4bea587f4 272
mbed_official 403:91a4bea587f4 273 switch (tmp)
mbed_official 403:91a4bea587f4 274 {
mbed_official 403:91a4bea587f4 275 case RCC_CFGR_SWS_HSI: /* HSI used as system clock */
mbed_official 403:91a4bea587f4 276 SystemCoreClock = HSI_VALUE;
mbed_official 403:91a4bea587f4 277 break;
mbed_official 403:91a4bea587f4 278 case RCC_CFGR_SWS_HSE: /* HSE used as system clock */
mbed_official 403:91a4bea587f4 279 SystemCoreClock = HSE_VALUE;
mbed_official 403:91a4bea587f4 280 break;
mbed_official 403:91a4bea587f4 281 case RCC_CFGR_SWS_PLL: /* PLL used as system clock */
mbed_official 403:91a4bea587f4 282 /* Get PLL clock source and multiplication factor ----------------------*/
mbed_official 403:91a4bea587f4 283 pllmull = RCC->CFGR & RCC_CFGR_PLLMUL;
mbed_official 403:91a4bea587f4 284 pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
mbed_official 403:91a4bea587f4 285 pllmull = ( pllmull >> 18) + 2;
mbed_official 403:91a4bea587f4 286
mbed_official 403:91a4bea587f4 287 #if defined (STM32F302xE) || defined (STM32F303xE) || defined (STM32F398xx)
mbed_official 403:91a4bea587f4 288 predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
mbed_official 403:91a4bea587f4 289 if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV)
mbed_official 403:91a4bea587f4 290 {
mbed_official 403:91a4bea587f4 291 /* HSE oscillator clock selected as PREDIV1 clock entry */
mbed_official 403:91a4bea587f4 292 SystemCoreClock = (HSE_VALUE / predivfactor) * pllmull;
mbed_official 403:91a4bea587f4 293 }
mbed_official 403:91a4bea587f4 294 else
mbed_official 403:91a4bea587f4 295 {
mbed_official 403:91a4bea587f4 296 /* HSI oscillator clock selected as PREDIV1 clock entry */
mbed_official 403:91a4bea587f4 297 SystemCoreClock = (HSI_VALUE / predivfactor) * pllmull;
mbed_official 403:91a4bea587f4 298 }
mbed_official 403:91a4bea587f4 299 #else
mbed_official 403:91a4bea587f4 300 if (pllsource == RCC_CFGR_PLLSRC_HSI_DIV2)
mbed_official 403:91a4bea587f4 301 {
mbed_official 403:91a4bea587f4 302 /* HSI oscillator clock divided by 2 selected as PLL clock entry */
mbed_official 403:91a4bea587f4 303 SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
mbed_official 403:91a4bea587f4 304 }
mbed_official 403:91a4bea587f4 305 else
mbed_official 403:91a4bea587f4 306 {
mbed_official 403:91a4bea587f4 307 predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
mbed_official 403:91a4bea587f4 308 /* HSE oscillator clock selected as PREDIV1 clock entry */
mbed_official 403:91a4bea587f4 309 SystemCoreClock = (HSE_VALUE / predivfactor) * pllmull;
mbed_official 403:91a4bea587f4 310 }
mbed_official 403:91a4bea587f4 311 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
mbed_official 403:91a4bea587f4 312 break;
mbed_official 403:91a4bea587f4 313 default: /* HSI used as system clock */
mbed_official 403:91a4bea587f4 314 SystemCoreClock = HSI_VALUE;
mbed_official 403:91a4bea587f4 315 break;
mbed_official 403:91a4bea587f4 316 }
mbed_official 403:91a4bea587f4 317 /* Compute HCLK clock frequency ----------------*/
mbed_official 403:91a4bea587f4 318 /* Get HCLK prescaler */
mbed_official 403:91a4bea587f4 319 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
mbed_official 403:91a4bea587f4 320 /* HCLK clock frequency */
mbed_official 403:91a4bea587f4 321 SystemCoreClock >>= tmp;
mbed_official 403:91a4bea587f4 322 }
mbed_official 403:91a4bea587f4 323
mbed_official 403:91a4bea587f4 324 /**
mbed_official 403:91a4bea587f4 325 * @brief Configures the System clock source, PLL Multiplier and Divider factors,
mbed_official 403:91a4bea587f4 326 * AHB/APBx prescalers and Flash settings
mbed_official 403:91a4bea587f4 327 * @note This function should be called only once the RCC clock configuration
mbed_official 403:91a4bea587f4 328 * is reset to the default reset state (done in SystemInit() function).
mbed_official 403:91a4bea587f4 329 * @param None
mbed_official 403:91a4bea587f4 330 * @retval None
mbed_official 403:91a4bea587f4 331 */
mbed_official 403:91a4bea587f4 332 void SetSysClock(void)
mbed_official 403:91a4bea587f4 333 {
mbed_official 403:91a4bea587f4 334 /* 1- Try to start with HSE and external clock */
mbed_official 403:91a4bea587f4 335 #if USE_PLL_HSE_EXTC != 0
mbed_official 403:91a4bea587f4 336 if (SetSysClock_PLL_HSE(1) == 0)
mbed_official 403:91a4bea587f4 337 #endif
mbed_official 403:91a4bea587f4 338 {
mbed_official 403:91a4bea587f4 339 /* 2- If fail try to start with HSE and external xtal */
mbed_official 403:91a4bea587f4 340 #if USE_PLL_HSE_XTAL != 0
mbed_official 403:91a4bea587f4 341 if (SetSysClock_PLL_HSE(0) == 0)
mbed_official 403:91a4bea587f4 342 #endif
mbed_official 403:91a4bea587f4 343 {
mbed_official 403:91a4bea587f4 344 /* 3- If fail start with HSI clock */
mbed_official 403:91a4bea587f4 345 if (SetSysClock_PLL_HSI() == 0)
mbed_official 403:91a4bea587f4 346 {
mbed_official 403:91a4bea587f4 347 while(1)
mbed_official 403:91a4bea587f4 348 {
mbed_official 403:91a4bea587f4 349 // [TODO] Put something here to tell the user that a problem occured...
mbed_official 403:91a4bea587f4 350 }
mbed_official 403:91a4bea587f4 351 }
mbed_official 403:91a4bea587f4 352 }
mbed_official 403:91a4bea587f4 353 }
mbed_official 403:91a4bea587f4 354
mbed_official 403:91a4bea587f4 355 /* Output clock on MCO1 pin(PA8) for debugging purpose */
mbed_official 403:91a4bea587f4 356 //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_SYSCLK, RCC_MCO_DIV1); // 72 MHz or 64 MHz
mbed_official 403:91a4bea587f4 357 }
mbed_official 403:91a4bea587f4 358
mbed_official 403:91a4bea587f4 359 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
mbed_official 403:91a4bea587f4 360 /******************************************************************************/
mbed_official 403:91a4bea587f4 361 /* PLL (clocked by HSE) used as System clock source */
mbed_official 403:91a4bea587f4 362 /******************************************************************************/
mbed_official 403:91a4bea587f4 363 uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
mbed_official 403:91a4bea587f4 364 {
mbed_official 403:91a4bea587f4 365 RCC_ClkInitTypeDef RCC_ClkInitStruct;
mbed_official 403:91a4bea587f4 366 RCC_OscInitTypeDef RCC_OscInitStruct;
mbed_official 403:91a4bea587f4 367
mbed_official 403:91a4bea587f4 368 /* Enable HSE oscillator and activate PLL with HSE as source */
mbed_official 403:91a4bea587f4 369 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
mbed_official 403:91a4bea587f4 370 if (bypass == 0)
mbed_official 403:91a4bea587f4 371 {
mbed_official 403:91a4bea587f4 372 RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */
mbed_official 403:91a4bea587f4 373 }
mbed_official 403:91a4bea587f4 374 else
mbed_official 403:91a4bea587f4 375 {
mbed_official 403:91a4bea587f4 376 RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
mbed_official 403:91a4bea587f4 377 }
mbed_official 403:91a4bea587f4 378 RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1;
mbed_official 403:91a4bea587f4 379 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
mbed_official 403:91a4bea587f4 380 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
mbed_official 403:91a4bea587f4 381 RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9; // 72 MHz (8 MHz * 9)
mbed_official 403:91a4bea587f4 382 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
mbed_official 403:91a4bea587f4 383 {
mbed_official 403:91a4bea587f4 384 return 0; // FAIL
mbed_official 403:91a4bea587f4 385 }
mbed_official 403:91a4bea587f4 386
mbed_official 403:91a4bea587f4 387 /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
mbed_official 403:91a4bea587f4 388 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
mbed_official 403:91a4bea587f4 389 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 72 MHz
mbed_official 403:91a4bea587f4 390 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 72 MHz
mbed_official 403:91a4bea587f4 391 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 36 MHz
mbed_official 403:91a4bea587f4 392 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 72 MHz
mbed_official 403:91a4bea587f4 393 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
mbed_official 403:91a4bea587f4 394 {
mbed_official 403:91a4bea587f4 395 return 0; // FAIL
mbed_official 403:91a4bea587f4 396 }
mbed_official 403:91a4bea587f4 397
mbed_official 403:91a4bea587f4 398 /* Output clock on MCO1 pin(PA8) for debugging purpose */
mbed_official 403:91a4bea587f4 399 //if (bypass == 0)
mbed_official 403:91a4bea587f4 400 // HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV2); // 4 MHz with xtal
mbed_official 403:91a4bea587f4 401 //else
mbed_official 403:91a4bea587f4 402 // HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV1); // 8 MHz with ext clock
mbed_official 403:91a4bea587f4 403
mbed_official 403:91a4bea587f4 404 return 1; // OK
mbed_official 403:91a4bea587f4 405 }
mbed_official 403:91a4bea587f4 406 #endif
mbed_official 403:91a4bea587f4 407
mbed_official 403:91a4bea587f4 408 /******************************************************************************/
mbed_official 403:91a4bea587f4 409 /* PLL (clocked by HSI) used as System clock source */
mbed_official 403:91a4bea587f4 410 /******************************************************************************/
mbed_official 403:91a4bea587f4 411 uint8_t SetSysClock_PLL_HSI(void)
mbed_official 403:91a4bea587f4 412 {
mbed_official 403:91a4bea587f4 413 RCC_ClkInitTypeDef RCC_ClkInitStruct;
mbed_official 403:91a4bea587f4 414 RCC_OscInitTypeDef RCC_OscInitStruct;
mbed_official 403:91a4bea587f4 415
mbed_official 403:91a4bea587f4 416 /* Enable HSI oscillator and activate PLL with HSI as source */
mbed_official 403:91a4bea587f4 417 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
mbed_official 403:91a4bea587f4 418 RCC_OscInitStruct.HSIState = RCC_HSI_ON;
mbed_official 403:91a4bea587f4 419 RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
mbed_official 403:91a4bea587f4 420 RCC_OscInitStruct.HSICalibrationValue = 16;
mbed_official 403:91a4bea587f4 421 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
mbed_official 403:91a4bea587f4 422 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
mbed_official 403:91a4bea587f4 423 RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL16; // 64 MHz (8 MHz/2 * 16)
mbed_official 403:91a4bea587f4 424 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
mbed_official 403:91a4bea587f4 425 {
mbed_official 403:91a4bea587f4 426 return 0; // FAIL
mbed_official 403:91a4bea587f4 427 }
mbed_official 403:91a4bea587f4 428
mbed_official 403:91a4bea587f4 429 /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
mbed_official 403:91a4bea587f4 430 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
mbed_official 403:91a4bea587f4 431 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 64 MHz
mbed_official 403:91a4bea587f4 432 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 64 MHz
mbed_official 403:91a4bea587f4 433 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 32 MHz
mbed_official 403:91a4bea587f4 434 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 64 MHz
mbed_official 403:91a4bea587f4 435 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
mbed_official 403:91a4bea587f4 436 {
mbed_official 403:91a4bea587f4 437 return 0; // FAIL
mbed_official 403:91a4bea587f4 438 }
mbed_official 403:91a4bea587f4 439
mbed_official 403:91a4bea587f4 440 /* Output clock on MCO1 pin(PA8) for debugging purpose */
mbed_official 403:91a4bea587f4 441 //HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSI, RCC_MCO_DIV1); // 8 MHz
mbed_official 403:91a4bea587f4 442
mbed_official 403:91a4bea587f4 443 return 1; // OK
mbed_official 403:91a4bea587f4 444 }
mbed_official 403:91a4bea587f4 445
mbed_official 403:91a4bea587f4 446 /**
mbed_official 403:91a4bea587f4 447 * @}
mbed_official 403:91a4bea587f4 448 */
mbed_official 403:91a4bea587f4 449
mbed_official 403:91a4bea587f4 450 /**
mbed_official 403:91a4bea587f4 451 * @}
mbed_official 403:91a4bea587f4 452 */
mbed_official 403:91a4bea587f4 453
mbed_official 403:91a4bea587f4 454 /**
mbed_official 403:91a4bea587f4 455 * @}
mbed_official 403:91a4bea587f4 456 */
mbed_official 403:91a4bea587f4 457
mbed_official 403:91a4bea587f4 458 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
mbed_official 403:91a4bea587f4 459