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Last commit 20 Feb 2019 by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F3/TARGET_DISCO_F303VC/stm32f303xc.h@579:53297373a894, 2015-07-01 (annotated)

Committer:
mbed_official
Date:
Wed Jul 01 09:45:11 2015 +0100
Revision:
579:53297373a894
Parent:
403:91a4bea587f4 
Synchronized with git revision d5b4d2ab9c47edb4dc5776e7177b0c2263459081



Full URL: https://github.com/mbedmicro/mbed/commit/d5b4d2ab9c47edb4dc5776e7177b0c2263459081/



Initial version of drivers for SAMR21

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 403:91a4bea587f4 1 /**
mbed_official 403:91a4bea587f4 2 ******************************************************************************
mbed_official 403:91a4bea587f4 3 * @file stm32f303xc.h
mbed_official 403:91a4bea587f4 4 * @author MCD Application Team
mbed_official 403:91a4bea587f4 5 * @version V2.0.1
mbed_official 403:91a4bea587f4 6 * @date 18-June-2014
mbed_official 403:91a4bea587f4 7 * @brief CMSIS STM32F303xB/STM32F303xC Devices Peripheral Access Layer Header File.
mbed_official 403:91a4bea587f4 8 *
mbed_official 403:91a4bea587f4 9 * This file contains:
mbed_official 403:91a4bea587f4 10 * - Data structures and the address mapping for all peripherals
mbed_official 403:91a4bea587f4 11 * - Peripheral's registers declarations and bits definition
mbed_official 403:91a4bea587f4 12 * - Macros to access peripheral’s registers hardware
mbed_official 403:91a4bea587f4 13 *
mbed_official 403:91a4bea587f4 14 ******************************************************************************
mbed_official 403:91a4bea587f4 15 * @attention
mbed_official 403:91a4bea587f4 16 *
mbed_official 403:91a4bea587f4 17 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
mbed_official 403:91a4bea587f4 18 *
mbed_official 403:91a4bea587f4 19 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 403:91a4bea587f4 20 * are permitted provided that the following conditions are met:
mbed_official 403:91a4bea587f4 21 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 403:91a4bea587f4 22 * this list of conditions and the following disclaimer.
mbed_official 403:91a4bea587f4 23 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 403:91a4bea587f4 24 * this list of conditions and the following disclaimer in the documentation
mbed_official 403:91a4bea587f4 25 * and/or other materials provided with the distribution.
mbed_official 403:91a4bea587f4 26 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 403:91a4bea587f4 27 * may be used to endorse or promote products derived from this software
mbed_official 403:91a4bea587f4 28 * without specific prior written permission.
mbed_official 403:91a4bea587f4 29 *
mbed_official 403:91a4bea587f4 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 403:91a4bea587f4 31 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 403:91a4bea587f4 32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 403:91a4bea587f4 33 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 403:91a4bea587f4 34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 403:91a4bea587f4 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 403:91a4bea587f4 36 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 403:91a4bea587f4 37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 403:91a4bea587f4 38 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 403:91a4bea587f4 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 403:91a4bea587f4 40 *
mbed_official 403:91a4bea587f4 41 ******************************************************************************
mbed_official 403:91a4bea587f4 42 */
mbed_official 403:91a4bea587f4 43
mbed_official 403:91a4bea587f4 44 /** @addtogroup CMSIS_Device
mbed_official 403:91a4bea587f4 45 * @{
mbed_official 403:91a4bea587f4 46 */
mbed_official 403:91a4bea587f4 47
mbed_official 403:91a4bea587f4 48 /** @addtogroup stm32f303xc
mbed_official 403:91a4bea587f4 49 * @{
mbed_official 403:91a4bea587f4 50 */
mbed_official 403:91a4bea587f4 51
mbed_official 403:91a4bea587f4 52 #ifndef __STM32F303xC_H
mbed_official 403:91a4bea587f4 53 #define __STM32F303xC_H
mbed_official 403:91a4bea587f4 54
mbed_official 403:91a4bea587f4 55 #ifdef __cplusplus
mbed_official 403:91a4bea587f4 56 extern "C" {
mbed_official 403:91a4bea587f4 57 #endif /* __cplusplus */
mbed_official 403:91a4bea587f4 58
mbed_official 403:91a4bea587f4 59 /** @addtogroup Configuration_section_for_CMSIS
mbed_official 403:91a4bea587f4 60 * @{
mbed_official 403:91a4bea587f4 61 */
mbed_official 403:91a4bea587f4 62
mbed_official 403:91a4bea587f4 63 /**
mbed_official 403:91a4bea587f4 64 * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
mbed_official 403:91a4bea587f4 65 */
mbed_official 403:91a4bea587f4 66 #define __CM4_REV 0x0001 /*!< Core revision r0p1 */
mbed_official 403:91a4bea587f4 67 #define __MPU_PRESENT 1 /*!< STM32F303xB/STM32F303xC devices provide an MPU */
mbed_official 403:91a4bea587f4 68 #define __NVIC_PRIO_BITS 4 /*!< STM32F303xB/STM32F303xC devices use 4 Bits for the Priority Levels */
mbed_official 403:91a4bea587f4 69 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
mbed_official 403:91a4bea587f4 70 #define __FPU_PRESENT 1 /*!< STM32F303xB/STM32F303xC devices provide an FPU */
mbed_official 403:91a4bea587f4 71
mbed_official 403:91a4bea587f4 72 /**
mbed_official 403:91a4bea587f4 73 * @}
mbed_official 403:91a4bea587f4 74 */
mbed_official 403:91a4bea587f4 75
mbed_official 403:91a4bea587f4 76 /** @addtogroup Peripheral_interrupt_number_definition
mbed_official 403:91a4bea587f4 77 * @{
mbed_official 403:91a4bea587f4 78 */
mbed_official 403:91a4bea587f4 79
mbed_official 403:91a4bea587f4 80 /**
mbed_official 403:91a4bea587f4 81 * @brief STM32F303xB/STM32F303xC devices Interrupt Number Definition, according to the selected device
mbed_official 403:91a4bea587f4 82 * in @ref Library_configuration_section
mbed_official 403:91a4bea587f4 83 */
mbed_official 403:91a4bea587f4 84 typedef enum
mbed_official 403:91a4bea587f4 85 {
mbed_official 403:91a4bea587f4 86 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
mbed_official 403:91a4bea587f4 87 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
mbed_official 403:91a4bea587f4 88 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
mbed_official 403:91a4bea587f4 89 BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
mbed_official 403:91a4bea587f4 90 UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
mbed_official 403:91a4bea587f4 91 SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
mbed_official 403:91a4bea587f4 92 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
mbed_official 403:91a4bea587f4 93 PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
mbed_official 403:91a4bea587f4 94 SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
mbed_official 403:91a4bea587f4 95 /****** STM32 specific Interrupt Numbers **********************************************************************/
mbed_official 403:91a4bea587f4 96 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
mbed_official 403:91a4bea587f4 97 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
mbed_official 403:91a4bea587f4 98 TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line 19 */
mbed_official 403:91a4bea587f4 99 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line 20 */
mbed_official 403:91a4bea587f4 100 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
mbed_official 403:91a4bea587f4 101 RCC_IRQn = 5, /*!< RCC global Interrupt */
mbed_official 403:91a4bea587f4 102 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
mbed_official 403:91a4bea587f4 103 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
mbed_official 403:91a4bea587f4 104 EXTI2_TSC_IRQn = 8, /*!< EXTI Line2 Interrupt and Touch Sense Controller Interrupt */
mbed_official 403:91a4bea587f4 105 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
mbed_official 403:91a4bea587f4 106 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
mbed_official 403:91a4bea587f4 107 DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 Interrupt */
mbed_official 403:91a4bea587f4 108 DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 Interrupt */
mbed_official 403:91a4bea587f4 109 DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 Interrupt */
mbed_official 403:91a4bea587f4 110 DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 Interrupt */
mbed_official 403:91a4bea587f4 111 DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 Interrupt */
mbed_official 403:91a4bea587f4 112 DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 Interrupt */
mbed_official 403:91a4bea587f4 113 DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 Interrupt */
mbed_official 403:91a4bea587f4 114 ADC1_2_IRQn = 18, /*!< ADC1 & ADC2 Interrupts */
mbed_official 403:91a4bea587f4 115 USB_HP_CAN_TX_IRQn = 19, /*!< USB Device High Priority or CAN TX Interrupts */
mbed_official 403:91a4bea587f4 116 USB_LP_CAN_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN RX0 Interrupts */
mbed_official 403:91a4bea587f4 117 CAN_RX1_IRQn = 21, /*!< CAN RX1 Interrupt */
mbed_official 403:91a4bea587f4 118 CAN_SCE_IRQn = 22, /*!< CAN SCE Interrupt */
mbed_official 403:91a4bea587f4 119 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
mbed_official 403:91a4bea587f4 120 TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */
mbed_official 403:91a4bea587f4 121 TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */
mbed_official 403:91a4bea587f4 122 TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */
mbed_official 403:91a4bea587f4 123 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
mbed_official 403:91a4bea587f4 124 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
mbed_official 403:91a4bea587f4 125 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
mbed_official 403:91a4bea587f4 126 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
mbed_official 403:91a4bea587f4 127 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup) */
mbed_official 403:91a4bea587f4 128 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
mbed_official 403:91a4bea587f4 129 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt & EXTI Line24 Interrupt (I2C2 wakeup) */
mbed_official 403:91a4bea587f4 130 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
mbed_official 403:91a4bea587f4 131 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
mbed_official 403:91a4bea587f4 132 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
mbed_official 403:91a4bea587f4 133 USART1_IRQn = 37, /*!< USART1 global Interrupt & EXTI Line25 Interrupt (USART1 wakeup) */
mbed_official 403:91a4bea587f4 134 USART2_IRQn = 38, /*!< USART2 global Interrupt & EXTI Line26 Interrupt (USART2 wakeup) */
mbed_official 403:91a4bea587f4 135 USART3_IRQn = 39, /*!< USART3 global Interrupt & EXTI Line28 Interrupt (USART3 wakeup) */
mbed_official 403:91a4bea587f4 136 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
mbed_official 403:91a4bea587f4 137 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line 17 Interrupt */
mbed_official 403:91a4bea587f4 138 USBWakeUp_IRQn = 42, /*!< USB Wakeup Interrupt */
mbed_official 403:91a4bea587f4 139 TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */
mbed_official 403:91a4bea587f4 140 TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */
mbed_official 403:91a4bea587f4 141 TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */
mbed_official 403:91a4bea587f4 142 TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
mbed_official 403:91a4bea587f4 143 ADC3_IRQn = 47, /*!< ADC3 global Interrupt */
mbed_official 403:91a4bea587f4 144 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
mbed_official 403:91a4bea587f4 145 UART4_IRQn = 52, /*!< UART4 global Interrupt & EXTI Line34 Interrupt (UART4 wakeup) */
mbed_official 403:91a4bea587f4 146 UART5_IRQn = 53, /*!< UART5 global Interrupt & EXTI Line35 Interrupt (UART5 wakeup) */
mbed_official 403:91a4bea587f4 147 TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC channel 1&2 underrun error interrupts */
mbed_official 403:91a4bea587f4 148 TIM7_IRQn = 55, /*!< TIM7 global Interrupt */
mbed_official 403:91a4bea587f4 149 DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */
mbed_official 403:91a4bea587f4 150 DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */
mbed_official 403:91a4bea587f4 151 DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */
mbed_official 403:91a4bea587f4 152 DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */
mbed_official 403:91a4bea587f4 153 DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */
mbed_official 403:91a4bea587f4 154 ADC4_IRQn = 61, /*!< ADC4 global Interrupt */
mbed_official 403:91a4bea587f4 155 COMP1_2_3_IRQn = 64, /*!< COMP1, COMP2 and COMP3 global Interrupt via EXTI Line21, 22 and 29*/
mbed_official 403:91a4bea587f4 156 COMP4_5_6_IRQn = 65, /*!< COMP4, COMP5 and COMP6 global Interrupt via EXTI Line30, 31 and 32*/
mbed_official 403:91a4bea587f4 157 COMP7_IRQn = 66, /*!< COMP7 global Interrupt via EXTI Line33 */
mbed_official 403:91a4bea587f4 158 USB_HP_IRQn = 74, /*!< USB High Priority global Interrupt remap */
mbed_official 403:91a4bea587f4 159 USB_LP_IRQn = 75, /*!< USB Low Priority global Interrupt remap */
mbed_official 403:91a4bea587f4 160 USBWakeUp_RMP_IRQn = 76, /*!< USB Wakeup Interrupt remap */
mbed_official 403:91a4bea587f4 161 FPU_IRQn = 81 /*!< Floating point Interrupt */
mbed_official 403:91a4bea587f4 162 } IRQn_Type;
mbed_official 403:91a4bea587f4 163
mbed_official 403:91a4bea587f4 164 /**
mbed_official 403:91a4bea587f4 165 * @}
mbed_official 403:91a4bea587f4 166 */
mbed_official 403:91a4bea587f4 167
mbed_official 403:91a4bea587f4 168 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
mbed_official 403:91a4bea587f4 169 #include "system_stm32f3xx.h" /* STM32F3xx System Header */
mbed_official 403:91a4bea587f4 170 #include <stdint.h>
mbed_official 403:91a4bea587f4 171
mbed_official 403:91a4bea587f4 172 /** @addtogroup Peripheral_registers_structures
mbed_official 403:91a4bea587f4 173 * @{
mbed_official 403:91a4bea587f4 174 */
mbed_official 403:91a4bea587f4 175
mbed_official 403:91a4bea587f4 176 /**
mbed_official 403:91a4bea587f4 177 * @brief Analog to Digital Converter
mbed_official 403:91a4bea587f4 178 */
mbed_official 403:91a4bea587f4 179
mbed_official 403:91a4bea587f4 180 typedef struct
mbed_official 403:91a4bea587f4 181 {
mbed_official 403:91a4bea587f4 182 __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */
mbed_official 403:91a4bea587f4 183 __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */
mbed_official 403:91a4bea587f4 184 __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */
mbed_official 403:91a4bea587f4 185 __IO uint32_t CFGR; /*!< ADC Configuration register, Address offset: 0x0C */
mbed_official 403:91a4bea587f4 186 uint32_t RESERVED0; /*!< Reserved, 0x010 */
mbed_official 403:91a4bea587f4 187 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */
mbed_official 403:91a4bea587f4 188 __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */
mbed_official 403:91a4bea587f4 189 uint32_t RESERVED1; /*!< Reserved, 0x01C */
mbed_official 403:91a4bea587f4 190 __IO uint32_t TR1; /*!< ADC watchdog threshold register 1, Address offset: 0x20 */
mbed_official 403:91a4bea587f4 191 __IO uint32_t TR2; /*!< ADC watchdog threshold register 2, Address offset: 0x24 */
mbed_official 403:91a4bea587f4 192 __IO uint32_t TR3; /*!< ADC watchdog threshold register 3, Address offset: 0x28 */
mbed_official 403:91a4bea587f4 193 uint32_t RESERVED2; /*!< Reserved, 0x02C */
mbed_official 403:91a4bea587f4 194 __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */
mbed_official 403:91a4bea587f4 195 __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */
mbed_official 403:91a4bea587f4 196 __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */
mbed_official 403:91a4bea587f4 197 __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */
mbed_official 403:91a4bea587f4 198 __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */
mbed_official 403:91a4bea587f4 199 uint32_t RESERVED3; /*!< Reserved, 0x044 */
mbed_official 403:91a4bea587f4 200 uint32_t RESERVED4; /*!< Reserved, 0x048 */
mbed_official 403:91a4bea587f4 201 __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */
mbed_official 403:91a4bea587f4 202 uint32_t RESERVED5[4]; /*!< Reserved, 0x050 - 0x05C */
mbed_official 403:91a4bea587f4 203 __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */
mbed_official 403:91a4bea587f4 204 __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */
mbed_official 403:91a4bea587f4 205 __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */
mbed_official 403:91a4bea587f4 206 __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */
mbed_official 403:91a4bea587f4 207 uint32_t RESERVED6[4]; /*!< Reserved, 0x070 - 0x07C */
mbed_official 403:91a4bea587f4 208 __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */
mbed_official 403:91a4bea587f4 209 __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */
mbed_official 403:91a4bea587f4 210 __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */
mbed_official 403:91a4bea587f4 211 __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */
mbed_official 403:91a4bea587f4 212 uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */
mbed_official 403:91a4bea587f4 213 __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */
mbed_official 403:91a4bea587f4 214 __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */
mbed_official 403:91a4bea587f4 215 uint32_t RESERVED8; /*!< Reserved, 0x0A8 */
mbed_official 403:91a4bea587f4 216 uint32_t RESERVED9; /*!< Reserved, 0x0AC */
mbed_official 403:91a4bea587f4 217 __IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xB0 */
mbed_official 403:91a4bea587f4 218 __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xB4 */
mbed_official 403:91a4bea587f4 219
mbed_official 403:91a4bea587f4 220 } ADC_TypeDef;
mbed_official 403:91a4bea587f4 221
mbed_official 403:91a4bea587f4 222 typedef struct
mbed_official 403:91a4bea587f4 223 {
mbed_official 403:91a4bea587f4 224 __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */
mbed_official 403:91a4bea587f4 225 uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */
mbed_official 403:91a4bea587f4 226 __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */
mbed_official 403:91a4bea587f4 227 __IO uint32_t CDR; /*!< ADC common regular data register for dual
mbed_official 403:91a4bea587f4 228 AND triple modes, Address offset: ADC1/3 base address + 0x30C */
mbed_official 403:91a4bea587f4 229 } ADC_Common_TypeDef;
mbed_official 403:91a4bea587f4 230
mbed_official 403:91a4bea587f4 231 /**
mbed_official 403:91a4bea587f4 232 * @brief Controller Area Network TxMailBox
mbed_official 403:91a4bea587f4 233 */
mbed_official 403:91a4bea587f4 234 typedef struct
mbed_official 403:91a4bea587f4 235 {
mbed_official 403:91a4bea587f4 236 __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
mbed_official 403:91a4bea587f4 237 __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
mbed_official 403:91a4bea587f4 238 __IO uint32_t TDLR; /*!< CAN mailbox data low register */
mbed_official 403:91a4bea587f4 239 __IO uint32_t TDHR; /*!< CAN mailbox data high register */
mbed_official 403:91a4bea587f4 240 } CAN_TxMailBox_TypeDef;
mbed_official 403:91a4bea587f4 241
mbed_official 403:91a4bea587f4 242 /**
mbed_official 403:91a4bea587f4 243 * @brief Controller Area Network FIFOMailBox
mbed_official 403:91a4bea587f4 244 */
mbed_official 403:91a4bea587f4 245 typedef struct
mbed_official 403:91a4bea587f4 246 {
mbed_official 403:91a4bea587f4 247 __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
mbed_official 403:91a4bea587f4 248 __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
mbed_official 403:91a4bea587f4 249 __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
mbed_official 403:91a4bea587f4 250 __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
mbed_official 403:91a4bea587f4 251 } CAN_FIFOMailBox_TypeDef;
mbed_official 403:91a4bea587f4 252
mbed_official 403:91a4bea587f4 253 /**
mbed_official 403:91a4bea587f4 254 * @brief Controller Area Network FilterRegister
mbed_official 403:91a4bea587f4 255 */
mbed_official 403:91a4bea587f4 256 typedef struct
mbed_official 403:91a4bea587f4 257 {
mbed_official 403:91a4bea587f4 258 __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
mbed_official 403:91a4bea587f4 259 __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
mbed_official 403:91a4bea587f4 260 } CAN_FilterRegister_TypeDef;
mbed_official 403:91a4bea587f4 261
mbed_official 403:91a4bea587f4 262 /**
mbed_official 403:91a4bea587f4 263 * @brief Controller Area Network
mbed_official 403:91a4bea587f4 264 */
mbed_official 403:91a4bea587f4 265 typedef struct
mbed_official 403:91a4bea587f4 266 {
mbed_official 403:91a4bea587f4 267 __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
mbed_official 403:91a4bea587f4 268 __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
mbed_official 403:91a4bea587f4 269 __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
mbed_official 403:91a4bea587f4 270 __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
mbed_official 403:91a4bea587f4 271 __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
mbed_official 403:91a4bea587f4 272 __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
mbed_official 403:91a4bea587f4 273 __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
mbed_official 403:91a4bea587f4 274 __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
mbed_official 403:91a4bea587f4 275 uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
mbed_official 403:91a4bea587f4 276 CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
mbed_official 403:91a4bea587f4 277 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
mbed_official 403:91a4bea587f4 278 uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
mbed_official 403:91a4bea587f4 279 __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
mbed_official 403:91a4bea587f4 280 __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
mbed_official 403:91a4bea587f4 281 uint32_t RESERVED2; /*!< Reserved, 0x208 */
mbed_official 403:91a4bea587f4 282 __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
mbed_official 403:91a4bea587f4 283 uint32_t RESERVED3; /*!< Reserved, 0x210 */
mbed_official 403:91a4bea587f4 284 __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
mbed_official 403:91a4bea587f4 285 uint32_t RESERVED4; /*!< Reserved, 0x218 */
mbed_official 403:91a4bea587f4 286 __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
mbed_official 403:91a4bea587f4 287 uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
mbed_official 403:91a4bea587f4 288 CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
mbed_official 403:91a4bea587f4 289 } CAN_TypeDef;
mbed_official 403:91a4bea587f4 290
mbed_official 403:91a4bea587f4 291 /**
mbed_official 403:91a4bea587f4 292 * @brief Analog Comparators
mbed_official 403:91a4bea587f4 293 */
mbed_official 403:91a4bea587f4 294
mbed_official 403:91a4bea587f4 295 typedef struct
mbed_official 403:91a4bea587f4 296 {
mbed_official 403:91a4bea587f4 297 __IO uint32_t CSR; /*!< Comparator control Status register, Address offset: 0x00 */
mbed_official 403:91a4bea587f4 298 } COMP_TypeDef;
mbed_official 403:91a4bea587f4 299
mbed_official 403:91a4bea587f4 300 /**
mbed_official 403:91a4bea587f4 301 * @brief CRC calculation unit
mbed_official 403:91a4bea587f4 302 */
mbed_official 403:91a4bea587f4 303
mbed_official 403:91a4bea587f4 304 typedef struct
mbed_official 403:91a4bea587f4 305 {
mbed_official 403:91a4bea587f4 306 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
mbed_official 403:91a4bea587f4 307 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
mbed_official 403:91a4bea587f4 308 uint8_t RESERVED0; /*!< Reserved, 0x05 */
mbed_official 403:91a4bea587f4 309 uint16_t RESERVED1; /*!< Reserved, 0x06 */
mbed_official 403:91a4bea587f4 310 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
mbed_official 403:91a4bea587f4 311 uint32_t RESERVED2; /*!< Reserved, 0x0C */
mbed_official 403:91a4bea587f4 312 __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
mbed_official 403:91a4bea587f4 313 __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
mbed_official 403:91a4bea587f4 314 } CRC_TypeDef;
mbed_official 403:91a4bea587f4 315
mbed_official 403:91a4bea587f4 316 /**
mbed_official 403:91a4bea587f4 317 * @brief Digital to Analog Converter
mbed_official 403:91a4bea587f4 318 */
mbed_official 403:91a4bea587f4 319
mbed_official 403:91a4bea587f4 320 typedef struct
mbed_official 403:91a4bea587f4 321 {
mbed_official 403:91a4bea587f4 322 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
mbed_official 403:91a4bea587f4 323 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
mbed_official 403:91a4bea587f4 324 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
mbed_official 403:91a4bea587f4 325 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
mbed_official 403:91a4bea587f4 326 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
mbed_official 403:91a4bea587f4 327 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
mbed_official 403:91a4bea587f4 328 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
mbed_official 403:91a4bea587f4 329 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
mbed_official 403:91a4bea587f4 330 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
mbed_official 403:91a4bea587f4 331 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
mbed_official 403:91a4bea587f4 332 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
mbed_official 403:91a4bea587f4 333 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
mbed_official 403:91a4bea587f4 334 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
mbed_official 403:91a4bea587f4 335 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
mbed_official 403:91a4bea587f4 336 } DAC_TypeDef;
mbed_official 403:91a4bea587f4 337
mbed_official 403:91a4bea587f4 338 /**
mbed_official 403:91a4bea587f4 339 * @brief Debug MCU
mbed_official 403:91a4bea587f4 340 */
mbed_official 403:91a4bea587f4 341
mbed_official 403:91a4bea587f4 342 typedef struct
mbed_official 403:91a4bea587f4 343 {
mbed_official 403:91a4bea587f4 344 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
mbed_official 403:91a4bea587f4 345 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
mbed_official 403:91a4bea587f4 346 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
mbed_official 403:91a4bea587f4 347 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
mbed_official 403:91a4bea587f4 348 }DBGMCU_TypeDef;
mbed_official 403:91a4bea587f4 349
mbed_official 403:91a4bea587f4 350 /**
mbed_official 403:91a4bea587f4 351 * @brief DMA Controller
mbed_official 403:91a4bea587f4 352 */
mbed_official 403:91a4bea587f4 353
mbed_official 403:91a4bea587f4 354 typedef struct
mbed_official 403:91a4bea587f4 355 {
mbed_official 403:91a4bea587f4 356 __IO uint32_t CCR; /*!< DMA channel x configuration register */
mbed_official 403:91a4bea587f4 357 __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
mbed_official 403:91a4bea587f4 358 __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
mbed_official 403:91a4bea587f4 359 __IO uint32_t CMAR; /*!< DMA channel x memory address register */
mbed_official 403:91a4bea587f4 360 } DMA_Channel_TypeDef;
mbed_official 403:91a4bea587f4 361
mbed_official 403:91a4bea587f4 362 typedef struct
mbed_official 403:91a4bea587f4 363 {
mbed_official 403:91a4bea587f4 364 __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
mbed_official 403:91a4bea587f4 365 __IO uint32_t IFCR; /*!< DMA interrupt clear flag register, Address offset: 0x04 */
mbed_official 403:91a4bea587f4 366 } DMA_TypeDef;
mbed_official 403:91a4bea587f4 367
mbed_official 403:91a4bea587f4 368 /**
mbed_official 403:91a4bea587f4 369 * @brief External Interrupt/Event Controller
mbed_official 403:91a4bea587f4 370 */
mbed_official 403:91a4bea587f4 371
mbed_official 403:91a4bea587f4 372 typedef struct
mbed_official 403:91a4bea587f4 373 {
mbed_official 403:91a4bea587f4 374 __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
mbed_official 403:91a4bea587f4 375 __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
mbed_official 403:91a4bea587f4 376 __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
mbed_official 403:91a4bea587f4 377 __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
mbed_official 403:91a4bea587f4 378 __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
mbed_official 403:91a4bea587f4 379 __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
mbed_official 403:91a4bea587f4 380 uint32_t RESERVED1; /*!< Reserved, 0x18 */
mbed_official 403:91a4bea587f4 381 uint32_t RESERVED2; /*!< Reserved, 0x1C */
mbed_official 403:91a4bea587f4 382 __IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x20 */
mbed_official 403:91a4bea587f4 383 __IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x24 */
mbed_official 403:91a4bea587f4 384 __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x28 */
mbed_official 403:91a4bea587f4 385 __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x2C */
mbed_official 403:91a4bea587f4 386 __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x30 */
mbed_official 403:91a4bea587f4 387 __IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x34 */
mbed_official 403:91a4bea587f4 388 }EXTI_TypeDef;
mbed_official 403:91a4bea587f4 389
mbed_official 403:91a4bea587f4 390 /**
mbed_official 403:91a4bea587f4 391 * @brief FLASH Registers
mbed_official 403:91a4bea587f4 392 */
mbed_official 403:91a4bea587f4 393
mbed_official 403:91a4bea587f4 394 typedef struct
mbed_official 403:91a4bea587f4 395 {
mbed_official 403:91a4bea587f4 396 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
mbed_official 403:91a4bea587f4 397 __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
mbed_official 403:91a4bea587f4 398 __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
mbed_official 403:91a4bea587f4 399 __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
mbed_official 403:91a4bea587f4 400 __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
mbed_official 403:91a4bea587f4 401 __IO uint32_t AR; /*!< FLASH address register, Address offset: 0x14 */
mbed_official 403:91a4bea587f4 402 uint32_t RESERVED; /*!< Reserved, 0x18 */
mbed_official 403:91a4bea587f4 403 __IO uint32_t OBR; /*!< FLASH Option byte register, Address offset: 0x1C */
mbed_official 403:91a4bea587f4 404 __IO uint32_t WRPR; /*!< FLASH Write register, Address offset: 0x20 */
mbed_official 403:91a4bea587f4 405
mbed_official 403:91a4bea587f4 406 } FLASH_TypeDef;
mbed_official 403:91a4bea587f4 407
mbed_official 403:91a4bea587f4 408 /**
mbed_official 403:91a4bea587f4 409 * @brief Option Bytes Registers
mbed_official 403:91a4bea587f4 410 */
mbed_official 403:91a4bea587f4 411 typedef struct
mbed_official 403:91a4bea587f4 412 {
mbed_official 403:91a4bea587f4 413 __IO uint16_t RDP; /*!<FLASH option byte Read protection, Address offset: 0x00 */
mbed_official 403:91a4bea587f4 414 __IO uint16_t USER; /*!<FLASH option byte user options, Address offset: 0x02 */
mbed_official 403:91a4bea587f4 415 uint16_t RESERVED0; /*!< Reserved, 0x04 */
mbed_official 403:91a4bea587f4 416 uint16_t RESERVED1; /*!< Reserved, 0x06 */
mbed_official 403:91a4bea587f4 417 __IO uint16_t WRP0; /*!<FLASH option byte write protection 0, Address offset: 0x08 */
mbed_official 403:91a4bea587f4 418 __IO uint16_t WRP1; /*!<FLASH option byte write protection 1, Address offset: 0x0C */
mbed_official 403:91a4bea587f4 419 __IO uint16_t WRP2; /*!<FLASH option byte write protection 2, Address offset: 0x10 */
mbed_official 403:91a4bea587f4 420 __IO uint16_t WRP3; /*!<FLASH option byte write protection 3, Address offset: 0x12 */
mbed_official 403:91a4bea587f4 421 } OB_TypeDef;
mbed_official 403:91a4bea587f4 422
mbed_official 403:91a4bea587f4 423 /**
mbed_official 403:91a4bea587f4 424 * @brief General Purpose I/O
mbed_official 403:91a4bea587f4 425 */
mbed_official 403:91a4bea587f4 426
mbed_official 403:91a4bea587f4 427 typedef struct
mbed_official 403:91a4bea587f4 428 {
mbed_official 403:91a4bea587f4 429 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
mbed_official 403:91a4bea587f4 430 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
mbed_official 403:91a4bea587f4 431 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
mbed_official 403:91a4bea587f4 432 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
mbed_official 403:91a4bea587f4 433 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
mbed_official 403:91a4bea587f4 434 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
mbed_official 403:91a4bea587f4 435 __IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */
mbed_official 403:91a4bea587f4 436 __IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */
mbed_official 403:91a4bea587f4 437 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
mbed_official 403:91a4bea587f4 438 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
mbed_official 403:91a4bea587f4 439 __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
mbed_official 403:91a4bea587f4 440 }GPIO_TypeDef;
mbed_official 403:91a4bea587f4 441
mbed_official 403:91a4bea587f4 442 /**
mbed_official 403:91a4bea587f4 443 * @brief Operational Amplifier (OPAMP)
mbed_official 403:91a4bea587f4 444 */
mbed_official 403:91a4bea587f4 445
mbed_official 403:91a4bea587f4 446 typedef struct
mbed_official 403:91a4bea587f4 447 {
mbed_official 403:91a4bea587f4 448 __IO uint32_t CSR; /*!< OPAMP control and status register, Address offset: 0x00 */
mbed_official 403:91a4bea587f4 449 } OPAMP_TypeDef;
mbed_official 403:91a4bea587f4 450
mbed_official 403:91a4bea587f4 451 /**
mbed_official 403:91a4bea587f4 452 * @brief System configuration controller
mbed_official 403:91a4bea587f4 453 */
mbed_official 403:91a4bea587f4 454
mbed_official 403:91a4bea587f4 455 typedef struct
mbed_official 403:91a4bea587f4 456 {
mbed_official 403:91a4bea587f4 457 __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
mbed_official 403:91a4bea587f4 458 __IO uint32_t RCR; /*!< SYSCFG CCM SRAM protection register, Address offset: 0x04 */
mbed_official 403:91a4bea587f4 459 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x14-0x08 */
mbed_official 403:91a4bea587f4 460 __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */
mbed_official 403:91a4bea587f4 461 } SYSCFG_TypeDef;
mbed_official 403:91a4bea587f4 462
mbed_official 403:91a4bea587f4 463 /**
mbed_official 403:91a4bea587f4 464 * @brief Inter-integrated Circuit Interface
mbed_official 403:91a4bea587f4 465 */
mbed_official 403:91a4bea587f4 466
mbed_official 403:91a4bea587f4 467 typedef struct
mbed_official 403:91a4bea587f4 468 {
mbed_official 403:91a4bea587f4 469 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
mbed_official 403:91a4bea587f4 470 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
mbed_official 403:91a4bea587f4 471 __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
mbed_official 403:91a4bea587f4 472 __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
mbed_official 403:91a4bea587f4 473 __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
mbed_official 403:91a4bea587f4 474 __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
mbed_official 403:91a4bea587f4 475 __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
mbed_official 403:91a4bea587f4 476 __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
mbed_official 403:91a4bea587f4 477 __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
mbed_official 403:91a4bea587f4 478 __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
mbed_official 403:91a4bea587f4 479 __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
mbed_official 403:91a4bea587f4 480 }I2C_TypeDef;
mbed_official 403:91a4bea587f4 481
mbed_official 403:91a4bea587f4 482 /**
mbed_official 403:91a4bea587f4 483 * @brief Independent WATCHDOG
mbed_official 403:91a4bea587f4 484 */
mbed_official 403:91a4bea587f4 485
mbed_official 403:91a4bea587f4 486 typedef struct
mbed_official 403:91a4bea587f4 487 {
mbed_official 403:91a4bea587f4 488 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
mbed_official 403:91a4bea587f4 489 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
mbed_official 403:91a4bea587f4 490 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
mbed_official 403:91a4bea587f4 491 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
mbed_official 403:91a4bea587f4 492 __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
mbed_official 403:91a4bea587f4 493 } IWDG_TypeDef;
mbed_official 403:91a4bea587f4 494
mbed_official 403:91a4bea587f4 495 /**
mbed_official 403:91a4bea587f4 496 * @brief Power Control
mbed_official 403:91a4bea587f4 497 */
mbed_official 403:91a4bea587f4 498
mbed_official 403:91a4bea587f4 499 typedef struct
mbed_official 403:91a4bea587f4 500 {
mbed_official 403:91a4bea587f4 501 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
mbed_official 403:91a4bea587f4 502 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
mbed_official 403:91a4bea587f4 503 } PWR_TypeDef;
mbed_official 403:91a4bea587f4 504
mbed_official 403:91a4bea587f4 505 /**
mbed_official 403:91a4bea587f4 506 * @brief Reset and Clock Control
mbed_official 403:91a4bea587f4 507 */
mbed_official 403:91a4bea587f4 508 typedef struct
mbed_official 403:91a4bea587f4 509 {
mbed_official 403:91a4bea587f4 510 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
mbed_official 403:91a4bea587f4 511 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x04 */
mbed_official 403:91a4bea587f4 512 __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x08 */
mbed_official 403:91a4bea587f4 513 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x0C */
mbed_official 403:91a4bea587f4 514 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x10 */
mbed_official 403:91a4bea587f4 515 __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock register, Address offset: 0x14 */
mbed_official 403:91a4bea587f4 516 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x18 */
mbed_official 403:91a4bea587f4 517 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x1C */
mbed_official 403:91a4bea587f4 518 __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x20 */
mbed_official 403:91a4bea587f4 519 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x24 */
mbed_official 403:91a4bea587f4 520 __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x28 */
mbed_official 403:91a4bea587f4 521 __IO uint32_t CFGR2; /*!< RCC clock configuration register 2, Address offset: 0x2C */
mbed_official 403:91a4bea587f4 522 __IO uint32_t CFGR3; /*!< RCC clock configuration register 3, Address offset: 0x30 */
mbed_official 403:91a4bea587f4 523 } RCC_TypeDef;
mbed_official 403:91a4bea587f4 524
mbed_official 403:91a4bea587f4 525 /**
mbed_official 403:91a4bea587f4 526 * @brief Real-Time Clock
mbed_official 403:91a4bea587f4 527 */
mbed_official 403:91a4bea587f4 528
mbed_official 403:91a4bea587f4 529 typedef struct
mbed_official 403:91a4bea587f4 530 {
mbed_official 403:91a4bea587f4 531 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
mbed_official 403:91a4bea587f4 532 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
mbed_official 403:91a4bea587f4 533 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
mbed_official 403:91a4bea587f4 534 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
mbed_official 403:91a4bea587f4 535 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
mbed_official 403:91a4bea587f4 536 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
mbed_official 403:91a4bea587f4 537 uint32_t RESERVED0; /*!< Reserved, 0x18 */
mbed_official 403:91a4bea587f4 538 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
mbed_official 403:91a4bea587f4 539 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
mbed_official 403:91a4bea587f4 540 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
mbed_official 403:91a4bea587f4 541 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
mbed_official 403:91a4bea587f4 542 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
mbed_official 403:91a4bea587f4 543 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
mbed_official 403:91a4bea587f4 544 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
mbed_official 403:91a4bea587f4 545 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
mbed_official 403:91a4bea587f4 546 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
mbed_official 403:91a4bea587f4 547 __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
mbed_official 403:91a4bea587f4 548 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
mbed_official 403:91a4bea587f4 549 __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */
mbed_official 403:91a4bea587f4 550 uint32_t RESERVED7; /*!< Reserved, 0x4C */
mbed_official 403:91a4bea587f4 551 __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
mbed_official 403:91a4bea587f4 552 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
mbed_official 403:91a4bea587f4 553 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
mbed_official 403:91a4bea587f4 554 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
mbed_official 403:91a4bea587f4 555 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
mbed_official 403:91a4bea587f4 556 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
mbed_official 403:91a4bea587f4 557 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
mbed_official 403:91a4bea587f4 558 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
mbed_official 403:91a4bea587f4 559 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
mbed_official 403:91a4bea587f4 560 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
mbed_official 403:91a4bea587f4 561 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
mbed_official 403:91a4bea587f4 562 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
mbed_official 403:91a4bea587f4 563 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
mbed_official 403:91a4bea587f4 564 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
mbed_official 403:91a4bea587f4 565 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
mbed_official 403:91a4bea587f4 566 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
mbed_official 403:91a4bea587f4 567 } RTC_TypeDef;
mbed_official 403:91a4bea587f4 568
mbed_official 403:91a4bea587f4 569
mbed_official 403:91a4bea587f4 570 /**
mbed_official 403:91a4bea587f4 571 * @brief Serial Peripheral Interface
mbed_official 403:91a4bea587f4 572 */
mbed_official 403:91a4bea587f4 573
mbed_official 403:91a4bea587f4 574 typedef struct
mbed_official 403:91a4bea587f4 575 {
mbed_official 403:91a4bea587f4 576 __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */
mbed_official 403:91a4bea587f4 577 __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
mbed_official 403:91a4bea587f4 578 __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
mbed_official 403:91a4bea587f4 579 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
mbed_official 403:91a4bea587f4 580 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
mbed_official 403:91a4bea587f4 581 __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */
mbed_official 403:91a4bea587f4 582 __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */
mbed_official 403:91a4bea587f4 583 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
mbed_official 403:91a4bea587f4 584 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
mbed_official 403:91a4bea587f4 585 } SPI_TypeDef;
mbed_official 403:91a4bea587f4 586
mbed_official 403:91a4bea587f4 587 /**
mbed_official 403:91a4bea587f4 588 * @brief TIM
mbed_official 403:91a4bea587f4 589 */
mbed_official 403:91a4bea587f4 590 typedef struct
mbed_official 403:91a4bea587f4 591 {
mbed_official 403:91a4bea587f4 592 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
mbed_official 403:91a4bea587f4 593 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
mbed_official 403:91a4bea587f4 594 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
mbed_official 403:91a4bea587f4 595 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
mbed_official 403:91a4bea587f4 596 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
mbed_official 403:91a4bea587f4 597 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
mbed_official 403:91a4bea587f4 598 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
mbed_official 403:91a4bea587f4 599 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
mbed_official 403:91a4bea587f4 600 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
mbed_official 403:91a4bea587f4 601 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
mbed_official 403:91a4bea587f4 602 __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
mbed_official 403:91a4bea587f4 603 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
mbed_official 403:91a4bea587f4 604 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
mbed_official 403:91a4bea587f4 605 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
mbed_official 403:91a4bea587f4 606 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
mbed_official 403:91a4bea587f4 607 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
mbed_official 403:91a4bea587f4 608 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
mbed_official 403:91a4bea587f4 609 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
mbed_official 403:91a4bea587f4 610 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
mbed_official 403:91a4bea587f4 611 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
mbed_official 403:91a4bea587f4 612 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
mbed_official 403:91a4bea587f4 613 __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */
mbed_official 403:91a4bea587f4 614 __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */
mbed_official 403:91a4bea587f4 615 __IO uint32_t CCR6; /*!< TIM capture/compare register 4, Address offset: 0x5C */
mbed_official 403:91a4bea587f4 616 } TIM_TypeDef;
mbed_official 403:91a4bea587f4 617
mbed_official 403:91a4bea587f4 618 /**
mbed_official 403:91a4bea587f4 619 * @brief Touch Sensing Controller (TSC)
mbed_official 403:91a4bea587f4 620 */
mbed_official 403:91a4bea587f4 621 typedef struct
mbed_official 403:91a4bea587f4 622 {
mbed_official 403:91a4bea587f4 623 __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */
mbed_official 403:91a4bea587f4 624 __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */
mbed_official 403:91a4bea587f4 625 __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */
mbed_official 403:91a4bea587f4 626 __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */
mbed_official 403:91a4bea587f4 627 __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */
mbed_official 403:91a4bea587f4 628 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
mbed_official 403:91a4bea587f4 629 __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */
mbed_official 403:91a4bea587f4 630 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */
mbed_official 403:91a4bea587f4 631 __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */
mbed_official 403:91a4bea587f4 632 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */
mbed_official 403:91a4bea587f4 633 __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */
mbed_official 403:91a4bea587f4 634 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */
mbed_official 403:91a4bea587f4 635 __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */
mbed_official 403:91a4bea587f4 636 __IO uint32_t IOGXCR[8]; /*!< TSC I/O group x counter register, Address offset: 0x34-50 */
mbed_official 403:91a4bea587f4 637 } TSC_TypeDef;
mbed_official 403:91a4bea587f4 638
mbed_official 403:91a4bea587f4 639 /**
mbed_official 403:91a4bea587f4 640 * @brief Universal Synchronous Asynchronous Receiver Transmitter
mbed_official 403:91a4bea587f4 641 */
mbed_official 403:91a4bea587f4 642
mbed_official 403:91a4bea587f4 643 typedef struct
mbed_official 403:91a4bea587f4 644 {
mbed_official 403:91a4bea587f4 645 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
mbed_official 403:91a4bea587f4 646 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
mbed_official 403:91a4bea587f4 647 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
mbed_official 403:91a4bea587f4 648 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
mbed_official 403:91a4bea587f4 649 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
mbed_official 403:91a4bea587f4 650 __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
mbed_official 403:91a4bea587f4 651 __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
mbed_official 403:91a4bea587f4 652 __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
mbed_official 403:91a4bea587f4 653 __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
mbed_official 403:91a4bea587f4 654 __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
mbed_official 403:91a4bea587f4 655 uint16_t RESERVED1; /*!< Reserved, 0x26 */
mbed_official 403:91a4bea587f4 656 __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
mbed_official 403:91a4bea587f4 657 uint16_t RESERVED2; /*!< Reserved, 0x2A */
mbed_official 403:91a4bea587f4 658 } USART_TypeDef;
mbed_official 403:91a4bea587f4 659
mbed_official 403:91a4bea587f4 660 /**
mbed_official 403:91a4bea587f4 661 * @brief Universal Serial Bus Full Speed Device
mbed_official 403:91a4bea587f4 662 */
mbed_official 403:91a4bea587f4 663
mbed_official 403:91a4bea587f4 664 typedef struct
mbed_official 403:91a4bea587f4 665 {
mbed_official 403:91a4bea587f4 666 __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */
mbed_official 403:91a4bea587f4 667 __IO uint16_t RESERVED0; /*!< Reserved */
mbed_official 403:91a4bea587f4 668 __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */
mbed_official 403:91a4bea587f4 669 __IO uint16_t RESERVED1; /*!< Reserved */
mbed_official 403:91a4bea587f4 670 __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */
mbed_official 403:91a4bea587f4 671 __IO uint16_t RESERVED2; /*!< Reserved */
mbed_official 403:91a4bea587f4 672 __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */
mbed_official 403:91a4bea587f4 673 __IO uint16_t RESERVED3; /*!< Reserved */
mbed_official 403:91a4bea587f4 674 __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */
mbed_official 403:91a4bea587f4 675 __IO uint16_t RESERVED4; /*!< Reserved */
mbed_official 403:91a4bea587f4 676 __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */
mbed_official 403:91a4bea587f4 677 __IO uint16_t RESERVED5; /*!< Reserved */
mbed_official 403:91a4bea587f4 678 __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */
mbed_official 403:91a4bea587f4 679 __IO uint16_t RESERVED6; /*!< Reserved */
mbed_official 403:91a4bea587f4 680 __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */
mbed_official 403:91a4bea587f4 681 __IO uint16_t RESERVED7[17]; /*!< Reserved */
mbed_official 403:91a4bea587f4 682 __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */
mbed_official 403:91a4bea587f4 683 __IO uint16_t RESERVED8; /*!< Reserved */
mbed_official 403:91a4bea587f4 684 __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */
mbed_official 403:91a4bea587f4 685 __IO uint16_t RESERVED9; /*!< Reserved */
mbed_official 403:91a4bea587f4 686 __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */
mbed_official 403:91a4bea587f4 687 __IO uint16_t RESERVEDA; /*!< Reserved */
mbed_official 403:91a4bea587f4 688 __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */
mbed_official 403:91a4bea587f4 689 __IO uint16_t RESERVEDB; /*!< Reserved */
mbed_official 403:91a4bea587f4 690 __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */
mbed_official 403:91a4bea587f4 691 __IO uint16_t RESERVEDC; /*!< Reserved */
mbed_official 403:91a4bea587f4 692 } USB_TypeDef;
mbed_official 403:91a4bea587f4 693
mbed_official 403:91a4bea587f4 694 /**
mbed_official 403:91a4bea587f4 695 * @brief Window WATCHDOG
mbed_official 403:91a4bea587f4 696 */
mbed_official 403:91a4bea587f4 697 typedef struct
mbed_official 403:91a4bea587f4 698 {
mbed_official 403:91a4bea587f4 699 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
mbed_official 403:91a4bea587f4 700 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
mbed_official 403:91a4bea587f4 701 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
mbed_official 403:91a4bea587f4 702 } WWDG_TypeDef;
mbed_official 403:91a4bea587f4 703
mbed_official 403:91a4bea587f4 704 /** @addtogroup Peripheral_memory_map
mbed_official 403:91a4bea587f4 705 * @{
mbed_official 403:91a4bea587f4 706 */
mbed_official 403:91a4bea587f4 707
mbed_official 403:91a4bea587f4 708 #define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH(up to 256KB) base address in the alias region */
mbed_official 403:91a4bea587f4 709 #define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(8 KB) base address in the alias region */
mbed_official 403:91a4bea587f4 710 #define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM(up to 40KB) base address in the alias region */
mbed_official 403:91a4bea587f4 711 #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
mbed_official 403:91a4bea587f4 712
mbed_official 403:91a4bea587f4 713 #define CCMDATARAM_BB_BASE ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM(8 KB) base address in the bit-band region */
mbed_official 403:91a4bea587f4 714 #define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM(up to 40KB) base address in the bit-band region */
mbed_official 403:91a4bea587f4 715 #define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
mbed_official 403:91a4bea587f4 716
mbed_official 403:91a4bea587f4 717
mbed_official 403:91a4bea587f4 718 /*!< Peripheral memory map */
mbed_official 403:91a4bea587f4 719 #define APB1PERIPH_BASE PERIPH_BASE
mbed_official 403:91a4bea587f4 720 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000)
mbed_official 403:91a4bea587f4 721 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000)
mbed_official 403:91a4bea587f4 722 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000)
mbed_official 403:91a4bea587f4 723 #define AHB3PERIPH_BASE (PERIPH_BASE + 0x10000000)
mbed_official 403:91a4bea587f4 724
mbed_official 403:91a4bea587f4 725 /*!< APB1 peripherals */
mbed_official 403:91a4bea587f4 726 #define TIM2_BASE (APB1PERIPH_BASE + 0x00000000)
mbed_official 403:91a4bea587f4 727 #define TIM3_BASE (APB1PERIPH_BASE + 0x00000400)
mbed_official 403:91a4bea587f4 728 #define TIM4_BASE (APB1PERIPH_BASE + 0x00000800)
mbed_official 403:91a4bea587f4 729 #define TIM6_BASE (APB1PERIPH_BASE + 0x00001000)
mbed_official 403:91a4bea587f4 730 #define TIM7_BASE (APB1PERIPH_BASE + 0x00001400)
mbed_official 403:91a4bea587f4 731 #define RTC_BASE (APB1PERIPH_BASE + 0x00002800)
mbed_official 403:91a4bea587f4 732 #define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00)
mbed_official 403:91a4bea587f4 733 #define IWDG_BASE (APB1PERIPH_BASE + 0x00003000)
mbed_official 403:91a4bea587f4 734 #define I2S2ext_BASE (APB1PERIPH_BASE + 0x00003400)
mbed_official 403:91a4bea587f4 735 #define SPI2_BASE (APB1PERIPH_BASE + 0x00003800)
mbed_official 403:91a4bea587f4 736 #define SPI3_BASE (APB1PERIPH_BASE + 0x00003C00)
mbed_official 403:91a4bea587f4 737 #define I2S3ext_BASE (APB1PERIPH_BASE + 0x00004000)
mbed_official 403:91a4bea587f4 738 #define USART2_BASE (APB1PERIPH_BASE + 0x00004400)
mbed_official 403:91a4bea587f4 739 #define USART3_BASE (APB1PERIPH_BASE + 0x00004800)
mbed_official 403:91a4bea587f4 740 #define UART4_BASE (APB1PERIPH_BASE + 0x00004C00)
mbed_official 403:91a4bea587f4 741 #define UART5_BASE (APB1PERIPH_BASE + 0x00005000)
mbed_official 403:91a4bea587f4 742 #define I2C1_BASE (APB1PERIPH_BASE + 0x00005400)
mbed_official 403:91a4bea587f4 743 #define I2C2_BASE (APB1PERIPH_BASE + 0x00005800)
mbed_official 403:91a4bea587f4 744 #define USB_BASE (APB1PERIPH_BASE + 0x00005C00) /*!< USB_IP Peripheral Registers base address */
mbed_official 403:91a4bea587f4 745 #define USB_PMAADDR (APB1PERIPH_BASE + 0x00006000) /*!< USB_IP Packet Memory Area base address */
mbed_official 403:91a4bea587f4 746 #define CAN_BASE (APB1PERIPH_BASE + 0x00006400)
mbed_official 403:91a4bea587f4 747 #define PWR_BASE (APB1PERIPH_BASE + 0x00007000)
mbed_official 403:91a4bea587f4 748 #define DAC1_BASE (APB1PERIPH_BASE + 0x00007400)
mbed_official 403:91a4bea587f4 749 #define DAC_BASE DAC1_BASE
mbed_official 403:91a4bea587f4 750
mbed_official 403:91a4bea587f4 751 /*!< APB2 peripherals */
mbed_official 403:91a4bea587f4 752 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x00000000)
mbed_official 403:91a4bea587f4 753 #define COMP1_BASE (APB2PERIPH_BASE + 0x0000001C)
mbed_official 403:91a4bea587f4 754 #define COMP2_BASE (APB2PERIPH_BASE + 0x00000020)
mbed_official 403:91a4bea587f4 755 #define COMP3_BASE (APB2PERIPH_BASE + 0x00000024)
mbed_official 403:91a4bea587f4 756 #define COMP4_BASE (APB2PERIPH_BASE + 0x00000028)
mbed_official 403:91a4bea587f4 757 #define COMP5_BASE (APB2PERIPH_BASE + 0x0000002C)
mbed_official 403:91a4bea587f4 758 #define COMP6_BASE (APB2PERIPH_BASE + 0x00000030)
mbed_official 403:91a4bea587f4 759 #define COMP7_BASE (APB2PERIPH_BASE + 0x00000034)
mbed_official 403:91a4bea587f4 760 #define COMP_BASE COMP1_BASE
mbed_official 403:91a4bea587f4 761 #define OPAMP1_BASE (APB2PERIPH_BASE + 0x00000038)
mbed_official 403:91a4bea587f4 762 #define OPAMP2_BASE (APB2PERIPH_BASE + 0x0000003C)
mbed_official 403:91a4bea587f4 763 #define OPAMP3_BASE (APB2PERIPH_BASE + 0x00000040)
mbed_official 403:91a4bea587f4 764 #define OPAMP4_BASE (APB2PERIPH_BASE + 0x00000044)
mbed_official 403:91a4bea587f4 765 #define OPAMP_BASE OPAMP1_BASE
mbed_official 403:91a4bea587f4 766 #define EXTI_BASE (APB2PERIPH_BASE + 0x00000400)
mbed_official 403:91a4bea587f4 767 #define TIM1_BASE (APB2PERIPH_BASE + 0x00002C00)
mbed_official 403:91a4bea587f4 768 #define SPI1_BASE (APB2PERIPH_BASE + 0x00003000)
mbed_official 403:91a4bea587f4 769 #define TIM8_BASE (APB2PERIPH_BASE + 0x00003400)
mbed_official 403:91a4bea587f4 770 #define USART1_BASE (APB2PERIPH_BASE + 0x00003800)
mbed_official 403:91a4bea587f4 771 #define TIM15_BASE (APB2PERIPH_BASE + 0x00004000)
mbed_official 403:91a4bea587f4 772 #define TIM16_BASE (APB2PERIPH_BASE + 0x00004400)
mbed_official 403:91a4bea587f4 773 #define TIM17_BASE (APB2PERIPH_BASE + 0x00004800)
mbed_official 403:91a4bea587f4 774
mbed_official 403:91a4bea587f4 775 /*!< AHB1 peripherals */
mbed_official 403:91a4bea587f4 776 #define DMA1_BASE (AHB1PERIPH_BASE + 0x00000000)
mbed_official 403:91a4bea587f4 777 #define DMA1_Channel1_BASE (AHB1PERIPH_BASE + 0x00000008)
mbed_official 403:91a4bea587f4 778 #define DMA1_Channel2_BASE (AHB1PERIPH_BASE + 0x0000001C)
mbed_official 403:91a4bea587f4 779 #define DMA1_Channel3_BASE (AHB1PERIPH_BASE + 0x00000030)
mbed_official 403:91a4bea587f4 780 #define DMA1_Channel4_BASE (AHB1PERIPH_BASE + 0x00000044)
mbed_official 403:91a4bea587f4 781 #define DMA1_Channel5_BASE (AHB1PERIPH_BASE + 0x00000058)
mbed_official 403:91a4bea587f4 782 #define DMA1_Channel6_BASE (AHB1PERIPH_BASE + 0x0000006C)
mbed_official 403:91a4bea587f4 783 #define DMA1_Channel7_BASE (AHB1PERIPH_BASE + 0x00000080)
mbed_official 403:91a4bea587f4 784 #define DMA2_BASE (AHB1PERIPH_BASE + 0x00000400)
mbed_official 403:91a4bea587f4 785 #define DMA2_Channel1_BASE (AHB1PERIPH_BASE + 0x00000408)
mbed_official 403:91a4bea587f4 786 #define DMA2_Channel2_BASE (AHB1PERIPH_BASE + 0x0000041C)
mbed_official 403:91a4bea587f4 787 #define DMA2_Channel3_BASE (AHB1PERIPH_BASE + 0x00000430)
mbed_official 403:91a4bea587f4 788 #define DMA2_Channel4_BASE (AHB1PERIPH_BASE + 0x00000444)
mbed_official 403:91a4bea587f4 789 #define DMA2_Channel5_BASE (AHB1PERIPH_BASE + 0x00000458)
mbed_official 403:91a4bea587f4 790 #define RCC_BASE (AHB1PERIPH_BASE + 0x00001000)
mbed_official 403:91a4bea587f4 791 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x00002000) /*!< Flash registers base address */
mbed_official 403:91a4bea587f4 792 #define OB_BASE ((uint32_t)0x1FFFF800) /*!< Flash Option Bytes base address */
mbed_official 403:91a4bea587f4 793 #define CRC_BASE (AHB1PERIPH_BASE + 0x00003000)
mbed_official 403:91a4bea587f4 794 #define TSC_BASE (AHB1PERIPH_BASE + 0x00004000)
mbed_official 403:91a4bea587f4 795
mbed_official 403:91a4bea587f4 796 /*!< AHB2 peripherals */
mbed_official 403:91a4bea587f4 797 #define GPIOA_BASE (AHB2PERIPH_BASE + 0x00000000)
mbed_official 403:91a4bea587f4 798 #define GPIOB_BASE (AHB2PERIPH_BASE + 0x00000400)
mbed_official 403:91a4bea587f4 799 #define GPIOC_BASE (AHB2PERIPH_BASE + 0x00000800)
mbed_official 403:91a4bea587f4 800 #define GPIOD_BASE (AHB2PERIPH_BASE + 0x00000C00)
mbed_official 403:91a4bea587f4 801 #define GPIOE_BASE (AHB2PERIPH_BASE + 0x00001000)
mbed_official 403:91a4bea587f4 802 #define GPIOF_BASE (AHB2PERIPH_BASE + 0x00001400)
mbed_official 403:91a4bea587f4 803
mbed_official 403:91a4bea587f4 804 /*!< AHB3 peripherals */
mbed_official 403:91a4bea587f4 805 #define ADC1_BASE (AHB3PERIPH_BASE + 0x00000000)
mbed_official 403:91a4bea587f4 806 #define ADC2_BASE (AHB3PERIPH_BASE + 0x00000100)
mbed_official 403:91a4bea587f4 807 #define ADC1_2_COMMON_BASE (AHB3PERIPH_BASE + 0x00000300)
mbed_official 403:91a4bea587f4 808 #define ADC3_BASE (AHB3PERIPH_BASE + 0x00000400)
mbed_official 403:91a4bea587f4 809 #define ADC4_BASE (AHB3PERIPH_BASE + 0x00000500)
mbed_official 403:91a4bea587f4 810 #define ADC3_4_COMMON_BASE (AHB3PERIPH_BASE + 0x00000700)
mbed_official 403:91a4bea587f4 811
mbed_official 403:91a4bea587f4 812 #define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
mbed_official 403:91a4bea587f4 813 /**
mbed_official 403:91a4bea587f4 814 * @}
mbed_official 403:91a4bea587f4 815 */
mbed_official 403:91a4bea587f4 816
mbed_official 403:91a4bea587f4 817 /** @addtogroup Peripheral_declaration
mbed_official 403:91a4bea587f4 818 * @{
mbed_official 403:91a4bea587f4 819 */
mbed_official 403:91a4bea587f4 820 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
mbed_official 403:91a4bea587f4 821 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
mbed_official 403:91a4bea587f4 822 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
mbed_official 403:91a4bea587f4 823 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
mbed_official 403:91a4bea587f4 824 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
mbed_official 403:91a4bea587f4 825 #define RTC ((RTC_TypeDef *) RTC_BASE)
mbed_official 403:91a4bea587f4 826 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
mbed_official 403:91a4bea587f4 827 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
mbed_official 403:91a4bea587f4 828 #define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
mbed_official 403:91a4bea587f4 829 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
mbed_official 403:91a4bea587f4 830 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
mbed_official 403:91a4bea587f4 831 #define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
mbed_official 403:91a4bea587f4 832 #define USART2 ((USART_TypeDef *) USART2_BASE)
mbed_official 403:91a4bea587f4 833 #define USART3 ((USART_TypeDef *) USART3_BASE)
mbed_official 403:91a4bea587f4 834 #define UART4 ((USART_TypeDef *) UART4_BASE)
mbed_official 403:91a4bea587f4 835 #define UART5 ((USART_TypeDef *) UART5_BASE)
mbed_official 403:91a4bea587f4 836 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
mbed_official 403:91a4bea587f4 837 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
mbed_official 403:91a4bea587f4 838 #define CAN ((CAN_TypeDef *) CAN_BASE)
mbed_official 403:91a4bea587f4 839 #define PWR ((PWR_TypeDef *) PWR_BASE)
mbed_official 403:91a4bea587f4 840 #define DAC1 ((DAC_TypeDef *) DAC1_BASE)
mbed_official 403:91a4bea587f4 841 #define DAC ((DAC_TypeDef *) DAC_BASE)
mbed_official 403:91a4bea587f4 842 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
mbed_official 403:91a4bea587f4 843 #define COMP1 ((COMP_TypeDef *) COMP1_BASE)
mbed_official 403:91a4bea587f4 844 #define COMP2 ((COMP_TypeDef *) COMP2_BASE)
mbed_official 403:91a4bea587f4 845 #define COMP3 ((COMP_TypeDef *) COMP3_BASE)
mbed_official 403:91a4bea587f4 846 #define COMP4 ((COMP_TypeDef *) COMP4_BASE)
mbed_official 403:91a4bea587f4 847 #define COMP5 ((COMP_TypeDef *) COMP5_BASE)
mbed_official 403:91a4bea587f4 848 #define COMP6 ((COMP_TypeDef *) COMP6_BASE)
mbed_official 403:91a4bea587f4 849 #define COMP7 ((COMP_TypeDef *) COMP7_BASE)
mbed_official 403:91a4bea587f4 850 #define COMP ((COMP_TypeDef *) COMP_BASE)
mbed_official 403:91a4bea587f4 851 #define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE)
mbed_official 403:91a4bea587f4 852 #define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)
mbed_official 403:91a4bea587f4 853 #define OPAMP3 ((OPAMP_TypeDef *) OPAMP3_BASE)
mbed_official 403:91a4bea587f4 854 #define OPAMP4 ((OPAMP_TypeDef *) OPAMP4_BASE)
mbed_official 403:91a4bea587f4 855 #define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
mbed_official 403:91a4bea587f4 856 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
mbed_official 403:91a4bea587f4 857 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
mbed_official 403:91a4bea587f4 858 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
mbed_official 403:91a4bea587f4 859 #define TIM8 ((TIM_TypeDef *) TIM8_BASE)
mbed_official 403:91a4bea587f4 860 #define USART1 ((USART_TypeDef *) USART1_BASE)
mbed_official 403:91a4bea587f4 861 #define TIM15 ((TIM_TypeDef *) TIM15_BASE)
mbed_official 403:91a4bea587f4 862 #define TIM16 ((TIM_TypeDef *) TIM16_BASE)
mbed_official 403:91a4bea587f4 863 #define TIM17 ((TIM_TypeDef *) TIM17_BASE)
mbed_official 403:91a4bea587f4 864 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
mbed_official 403:91a4bea587f4 865 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
mbed_official 403:91a4bea587f4 866 #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
mbed_official 403:91a4bea587f4 867 #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
mbed_official 403:91a4bea587f4 868 #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
mbed_official 403:91a4bea587f4 869 #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
mbed_official 403:91a4bea587f4 870 #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
mbed_official 403:91a4bea587f4 871 #define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
mbed_official 403:91a4bea587f4 872 #define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
mbed_official 403:91a4bea587f4 873 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
mbed_official 403:91a4bea587f4 874 #define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
mbed_official 403:91a4bea587f4 875 #define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
mbed_official 403:91a4bea587f4 876 #define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
mbed_official 403:91a4bea587f4 877 #define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
mbed_official 403:91a4bea587f4 878 #define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
mbed_official 403:91a4bea587f4 879 #define RCC ((RCC_TypeDef *) RCC_BASE)
mbed_official 403:91a4bea587f4 880 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
mbed_official 403:91a4bea587f4 881 #define OB ((OB_TypeDef *) OB_BASE)
mbed_official 403:91a4bea587f4 882 #define CRC ((CRC_TypeDef *) CRC_BASE)
mbed_official 403:91a4bea587f4 883 #define TSC ((TSC_TypeDef *) TSC_BASE)
mbed_official 403:91a4bea587f4 884 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
mbed_official 403:91a4bea587f4 885 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
mbed_official 403:91a4bea587f4 886 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
mbed_official 403:91a4bea587f4 887 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
mbed_official 403:91a4bea587f4 888 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
mbed_official 403:91a4bea587f4 889 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
mbed_official 403:91a4bea587f4 890 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
mbed_official 403:91a4bea587f4 891 #define ADC2 ((ADC_TypeDef *) ADC2_BASE)
mbed_official 403:91a4bea587f4 892 #define ADC3 ((ADC_TypeDef *) ADC3_BASE)
mbed_official 403:91a4bea587f4 893 #define ADC4 ((ADC_TypeDef *) ADC4_BASE)
mbed_official 403:91a4bea587f4 894 #define ADC1_2_COMMON ((ADC_Common_TypeDef *) ADC1_2_COMMON_BASE)
mbed_official 403:91a4bea587f4 895 #define ADC3_4_COMMON ((ADC_Common_TypeDef *) ADC3_4_COMMON_BASE)
mbed_official 403:91a4bea587f4 896 #define USB ((USB_TypeDef *) USB_BASE)
mbed_official 403:91a4bea587f4 897 /**
mbed_official 403:91a4bea587f4 898 * @}
mbed_official 403:91a4bea587f4 899 */
mbed_official 403:91a4bea587f4 900
mbed_official 403:91a4bea587f4 901 /** @addtogroup Exported_constants
mbed_official 403:91a4bea587f4 902 * @{
mbed_official 403:91a4bea587f4 903 */
mbed_official 403:91a4bea587f4 904
mbed_official 403:91a4bea587f4 905 /** @addtogroup Peripheral_Registers_Bits_Definition
mbed_official 403:91a4bea587f4 906 * @{
mbed_official 403:91a4bea587f4 907 */
mbed_official 403:91a4bea587f4 908
mbed_official 403:91a4bea587f4 909 /******************************************************************************/
mbed_official 403:91a4bea587f4 910 /* Peripheral Registers_Bits_Definition */
mbed_official 403:91a4bea587f4 911 /******************************************************************************/
mbed_official 403:91a4bea587f4 912
mbed_official 403:91a4bea587f4 913 /******************************************************************************/
mbed_official 403:91a4bea587f4 914 /* */
mbed_official 403:91a4bea587f4 915 /* Analog to Digital Converter SAR (ADC) */
mbed_official 403:91a4bea587f4 916 /* */
mbed_official 403:91a4bea587f4 917 /******************************************************************************/
mbed_official 403:91a4bea587f4 918 /******************** Bit definition for ADC_ISR register ********************/
mbed_official 403:91a4bea587f4 919 #define ADC_ISR_ADRD ((uint32_t)0x00000001) /*!< ADC Ready (ADRDY) flag */
mbed_official 403:91a4bea587f4 920 #define ADC_ISR_EOSMP ((uint32_t)0x00000002) /*!< ADC End of Sampling flag */
mbed_official 403:91a4bea587f4 921 #define ADC_ISR_EOC ((uint32_t)0x00000004) /*!< ADC End of Regular Conversion flag */
mbed_official 403:91a4bea587f4 922 #define ADC_ISR_EOS ((uint32_t)0x00000008) /*!< ADC End of Regular sequence of Conversions flag */
mbed_official 403:91a4bea587f4 923 #define ADC_ISR_OVR ((uint32_t)0x00000010) /*!< ADC overrun flag */
mbed_official 403:91a4bea587f4 924 #define ADC_ISR_JEOC ((uint32_t)0x00000020) /*!< ADC End of Injected Conversion flag */
mbed_official 403:91a4bea587f4 925 #define ADC_ISR_JEOS ((uint32_t)0x00000040) /*!< ADC End of Injected sequence of Conversions flag */
mbed_official 403:91a4bea587f4 926 #define ADC_ISR_AWD1 ((uint32_t)0x00000080) /*!< ADC Analog watchdog 1 flag */
mbed_official 403:91a4bea587f4 927 #define ADC_ISR_AWD2 ((uint32_t)0x00000100) /*!< ADC Analog watchdog 2 flag */
mbed_official 403:91a4bea587f4 928 #define ADC_ISR_AWD3 ((uint32_t)0x00000200) /*!< ADC Analog watchdog 3 flag */
mbed_official 403:91a4bea587f4 929 #define ADC_ISR_JQOVF ((uint32_t)0x00000400) /*!< ADC Injected Context Queue Overflow flag */
mbed_official 403:91a4bea587f4 930
mbed_official 403:91a4bea587f4 931 /******************** Bit definition for ADC_IER register ********************/
mbed_official 403:91a4bea587f4 932 #define ADC_IER_RDY ((uint32_t)0x00000001) /*!< ADC Ready (ADRDY) interrupt source */
mbed_official 403:91a4bea587f4 933 #define ADC_IER_EOSMP ((uint32_t)0x00000002) /*!< ADC End of Sampling interrupt source */
mbed_official 403:91a4bea587f4 934 #define ADC_IER_EOC ((uint32_t)0x00000004) /*!< ADC End of Regular Conversion interrupt source */
mbed_official 403:91a4bea587f4 935 #define ADC_IER_EOS ((uint32_t)0x00000008) /*!< ADC End of Regular sequence of Conversions interrupt source */
mbed_official 403:91a4bea587f4 936 #define ADC_IER_OVR ((uint32_t)0x00000010) /*!< ADC overrun interrupt source */
mbed_official 403:91a4bea587f4 937 #define ADC_IER_JEOC ((uint32_t)0x00000020) /*!< ADC End of Injected Conversion interrupt source */
mbed_official 403:91a4bea587f4 938 #define ADC_IER_JEOS ((uint32_t)0x00000040) /*!< ADC End of Injected sequence of Conversions interrupt source */
mbed_official 403:91a4bea587f4 939 #define ADC_IER_AWD1 ((uint32_t)0x00000080) /*!< ADC Analog watchdog 1 interrupt source */
mbed_official 403:91a4bea587f4 940 #define ADC_IER_AWD2 ((uint32_t)0x00000100) /*!< ADC Analog watchdog 2 interrupt source */
mbed_official 403:91a4bea587f4 941 #define ADC_IER_AWD3 ((uint32_t)0x00000200) /*!< ADC Analog watchdog 3 interrupt source */
mbed_official 403:91a4bea587f4 942 #define ADC_IER_JQOVF ((uint32_t)0x00000400) /*!< ADC Injected Context Queue Overflow interrupt source */
mbed_official 403:91a4bea587f4 943
mbed_official 403:91a4bea587f4 944 /******************** Bit definition for ADC_CR register ********************/
mbed_official 403:91a4bea587f4 945 #define ADC_CR_ADEN ((uint32_t)0x00000001) /*!< ADC Enable control */
mbed_official 403:91a4bea587f4 946 #define ADC_CR_ADDIS ((uint32_t)0x00000002) /*!< ADC Disable command */
mbed_official 403:91a4bea587f4 947 #define ADC_CR_ADSTART ((uint32_t)0x00000004) /*!< ADC Start of Regular conversion */
mbed_official 403:91a4bea587f4 948 #define ADC_CR_JADSTART ((uint32_t)0x00000008) /*!< ADC Start of injected conversion */
mbed_official 403:91a4bea587f4 949 #define ADC_CR_ADSTP ((uint32_t)0x00000010) /*!< ADC Stop of Regular conversion */
mbed_official 403:91a4bea587f4 950 #define ADC_CR_JADSTP ((uint32_t)0x00000020) /*!< ADC Stop of injected conversion */
mbed_official 403:91a4bea587f4 951 #define ADC_CR_ADVREGEN ((uint32_t)0x30000000) /*!< ADC Voltage regulator Enable */
mbed_official 403:91a4bea587f4 952 #define ADC_CR_ADVREGEN_0 ((uint32_t)0x10000000) /*!< ADC ADVREGEN bit 0 */
mbed_official 403:91a4bea587f4 953 #define ADC_CR_ADVREGEN_1 ((uint32_t)0x20000000) /*!< ADC ADVREGEN bit 1 */
mbed_official 403:91a4bea587f4 954 #define ADC_CR_ADCALDIF ((uint32_t)0x40000000) /*!< ADC Differential Mode for calibration */
mbed_official 403:91a4bea587f4 955 #define ADC_CR_ADCAL ((uint32_t)0x80000000) /*!< ADC Calibration */
mbed_official 403:91a4bea587f4 956
mbed_official 403:91a4bea587f4 957 /******************** Bit definition for ADC_CFGR register ********************/
mbed_official 403:91a4bea587f4 958 #define ADC_CFGR_DMAEN ((uint32_t)0x00000001) /*!< ADC DMA Enable */
mbed_official 403:91a4bea587f4 959 #define ADC_CFGR_DMACFG ((uint32_t)0x00000002) /*!< ADC DMA configuration */
mbed_official 403:91a4bea587f4 960
mbed_official 403:91a4bea587f4 961 #define ADC_CFGR_RES ((uint32_t)0x00000018) /*!< ADC Data resolution */
mbed_official 403:91a4bea587f4 962 #define ADC_CFGR_RES_0 ((uint32_t)0x00000008) /*!< ADC RES bit 0 */
mbed_official 403:91a4bea587f4 963 #define ADC_CFGR_RES_1 ((uint32_t)0x00000010) /*!< ADC RES bit 1 */
mbed_official 403:91a4bea587f4 964
mbed_official 403:91a4bea587f4 965 #define ADC_CFGR_ALIGN ((uint32_t)0x00000020) /*!< ADC Data Alignement */
mbed_official 403:91a4bea587f4 966
mbed_official 403:91a4bea587f4 967 #define ADC_CFGR_EXTSEL ((uint32_t)0x000003C0) /*!< ADC External trigger selection for regular group */
mbed_official 403:91a4bea587f4 968 #define ADC_CFGR_EXTSEL_0 ((uint32_t)0x00000040) /*!< ADC EXTSEL bit 0 */
mbed_official 403:91a4bea587f4 969 #define ADC_CFGR_EXTSEL_1 ((uint32_t)0x00000080) /*!< ADC EXTSEL bit 1 */
mbed_official 403:91a4bea587f4 970 #define ADC_CFGR_EXTSEL_2 ((uint32_t)0x00000100) /*!< ADC EXTSEL bit 2 */
mbed_official 403:91a4bea587f4 971 #define ADC_CFGR_EXTSEL_3 ((uint32_t)0x00000200) /*!< ADC EXTSEL bit 3 */
mbed_official 403:91a4bea587f4 972
mbed_official 403:91a4bea587f4 973 #define ADC_CFGR_EXTEN ((uint32_t)0x00000C00) /*!< ADC External trigger enable and polarity selection for regular channels */
mbed_official 403:91a4bea587f4 974 #define ADC_CFGR_EXTEN_0 ((uint32_t)0x00000400) /*!< ADC EXTEN bit 0 */
mbed_official 403:91a4bea587f4 975 #define ADC_CFGR_EXTEN_1 ((uint32_t)0x00000800) /*!< ADC EXTEN bit 1 */
mbed_official 403:91a4bea587f4 976
mbed_official 403:91a4bea587f4 977 #define ADC_CFGR_OVRMOD ((uint32_t)0x00001000) /*!< ADC overrun mode */
mbed_official 403:91a4bea587f4 978 #define ADC_CFGR_CONT ((uint32_t)0x00002000) /*!< ADC Single/continuous conversion mode for regular conversion */
mbed_official 403:91a4bea587f4 979 #define ADC_CFGR_AUTDLY ((uint32_t)0x00004000) /*!< ADC Delayed conversion mode */
mbed_official 403:91a4bea587f4 980 #define ADC_CFGR_AUTOFF ((uint32_t)0x00008000) /*!< ADC Auto power OFF */
mbed_official 403:91a4bea587f4 981 #define ADC_CFGR_DISCEN ((uint32_t)0x00010000) /*!< ADC Discontinuous mode for regular channels */
mbed_official 403:91a4bea587f4 982
mbed_official 403:91a4bea587f4 983 #define ADC_CFGR_DISCNUM ((uint32_t)0x000E0000) /*!< ADC Discontinuous mode channel count */
mbed_official 403:91a4bea587f4 984 #define ADC_CFGR_DISCNUM_0 ((uint32_t)0x00020000) /*!< ADC DISCNUM bit 0 */
mbed_official 403:91a4bea587f4 985 #define ADC_CFGR_DISCNUM_1 ((uint32_t)0x00040000) /*!< ADC DISCNUM bit 1 */
mbed_official 403:91a4bea587f4 986 #define ADC_CFGR_DISCNUM_2 ((uint32_t)0x00080000) /*!< ADC DISCNUM bit 2 */
mbed_official 403:91a4bea587f4 987
mbed_official 403:91a4bea587f4 988 #define ADC_CFGR_JDISCEN ((uint32_t)0x00100000) /*!< ADC Discontinous mode on injected channels */
mbed_official 403:91a4bea587f4 989 #define ADC_CFGR_JQM ((uint32_t)0x00200000) /*!< ADC JSQR Queue mode */
mbed_official 403:91a4bea587f4 990 #define ADC_CFGR_AWD1SGL ((uint32_t)0x00400000) /*!< Eanble the watchdog 1 on a single channel or on all channels */
mbed_official 403:91a4bea587f4 991 #define ADC_CFGR_AWD1EN ((uint32_t)0x00800000) /*!< ADC Analog watchdog 1 enable on regular Channels */
mbed_official 403:91a4bea587f4 992 #define ADC_CFGR_JAWD1EN ((uint32_t)0x01000000) /*!< ADC Analog watchdog 1 enable on injected Channels */
mbed_official 403:91a4bea587f4 993 #define ADC_CFGR_JAUTO ((uint32_t)0x02000000) /*!< ADC Automatic injected group conversion */
mbed_official 403:91a4bea587f4 994
mbed_official 403:91a4bea587f4 995 #define ADC_CFGR_AWD1CH ((uint32_t)0x7C000000) /*!< ADC Analog watchdog 1 Channel selection */
mbed_official 403:91a4bea587f4 996 #define ADC_CFGR_AWD1CH_0 ((uint32_t)0x04000000) /*!< ADC AWD1CH bit 0 */
mbed_official 403:91a4bea587f4 997 #define ADC_CFGR_AWD1CH_1 ((uint32_t)0x08000000) /*!< ADC AWD1CH bit 1 */
mbed_official 403:91a4bea587f4 998 #define ADC_CFGR_AWD1CH_2 ((uint32_t)0x10000000) /*!< ADC AWD1CH bit 2 */
mbed_official 403:91a4bea587f4 999 #define ADC_CFGR_AWD1CH_3 ((uint32_t)0x20000000) /*!< ADC AWD1CH bit 3 */
mbed_official 403:91a4bea587f4 1000 #define ADC_CFGR_AWD1CH_4 ((uint32_t)0x40000000) /*!< ADC AWD1CH bit 4 */
mbed_official 403:91a4bea587f4 1001
mbed_official 403:91a4bea587f4 1002 /******************** Bit definition for ADC_SMPR1 register ********************/
mbed_official 403:91a4bea587f4 1003 #define ADC_SMPR1_SMP0 ((uint32_t)0x00000007) /*!< ADC Channel 0 Sampling time selection */
mbed_official 403:91a4bea587f4 1004 #define ADC_SMPR1_SMP0_0 ((uint32_t)0x00000001) /*!< ADC SMP0 bit 0 */
mbed_official 403:91a4bea587f4 1005 #define ADC_SMPR1_SMP0_1 ((uint32_t)0x00000002) /*!< ADC SMP0 bit 1 */
mbed_official 403:91a4bea587f4 1006 #define ADC_SMPR1_SMP0_2 ((uint32_t)0x00000004) /*!< ADC SMP0 bit 2 */
mbed_official 403:91a4bea587f4 1007
mbed_official 403:91a4bea587f4 1008 #define ADC_SMPR1_SMP1 ((uint32_t)0x00000038) /*!< ADC Channel 1 Sampling time selection */
mbed_official 403:91a4bea587f4 1009 #define ADC_SMPR1_SMP1_0 ((uint32_t)0x00000008) /*!< ADC SMP1 bit 0 */
mbed_official 403:91a4bea587f4 1010 #define ADC_SMPR1_SMP1_1 ((uint32_t)0x00000010) /*!< ADC SMP1 bit 1 */
mbed_official 403:91a4bea587f4 1011 #define ADC_SMPR1_SMP1_2 ((uint32_t)0x00000020) /*!< ADC SMP1 bit 2 */
mbed_official 403:91a4bea587f4 1012
mbed_official 403:91a4bea587f4 1013 #define ADC_SMPR1_SMP2 ((uint32_t)0x000001C0) /*!< ADC Channel 2 Sampling time selection */
mbed_official 403:91a4bea587f4 1014 #define ADC_SMPR1_SMP2_0 ((uint32_t)0x00000040) /*!< ADC SMP2 bit 0 */
mbed_official 403:91a4bea587f4 1015 #define ADC_SMPR1_SMP2_1 ((uint32_t)0x00000080) /*!< ADC SMP2 bit 1 */
mbed_official 403:91a4bea587f4 1016 #define ADC_SMPR1_SMP2_2 ((uint32_t)0x00000100) /*!< ADC SMP2 bit 2 */
mbed_official 403:91a4bea587f4 1017
mbed_official 403:91a4bea587f4 1018 #define ADC_SMPR1_SMP3 ((uint32_t)0x00000E00) /*!< ADC Channel 3 Sampling time selection */
mbed_official 403:91a4bea587f4 1019 #define ADC_SMPR1_SMP3_0 ((uint32_t)0x00000200) /*!< ADC SMP3 bit 0 */
mbed_official 403:91a4bea587f4 1020 #define ADC_SMPR1_SMP3_1 ((uint32_t)0x00000400) /*!< ADC SMP3 bit 1 */
mbed_official 403:91a4bea587f4 1021 #define ADC_SMPR1_SMP3_2 ((uint32_t)0x00000800) /*!< ADC SMP3 bit 2 */
mbed_official 403:91a4bea587f4 1022
mbed_official 403:91a4bea587f4 1023 #define ADC_SMPR1_SMP4 ((uint32_t)0x00007000) /*!< ADC Channel 4 Sampling time selection */
mbed_official 403:91a4bea587f4 1024 #define ADC_SMPR1_SMP4_0 ((uint32_t)0x00001000) /*!< ADC SMP4 bit 0 */
mbed_official 403:91a4bea587f4 1025 #define ADC_SMPR1_SMP4_1 ((uint32_t)0x00002000) /*!< ADC SMP4 bit 1 */
mbed_official 403:91a4bea587f4 1026 #define ADC_SMPR1_SMP4_2 ((uint32_t)0x00004000) /*!< ADC SMP4 bit 2 */
mbed_official 403:91a4bea587f4 1027
mbed_official 403:91a4bea587f4 1028 #define ADC_SMPR1_SMP5 ((uint32_t)0x00038000) /*!< ADC Channel 5 Sampling time selection */
mbed_official 403:91a4bea587f4 1029 #define ADC_SMPR1_SMP5_0 ((uint32_t)0x00008000) /*!< ADC SMP5 bit 0 */
mbed_official 403:91a4bea587f4 1030 #define ADC_SMPR1_SMP5_1 ((uint32_t)0x00010000) /*!< ADC SMP5 bit 1 */
mbed_official 403:91a4bea587f4 1031 #define ADC_SMPR1_SMP5_2 ((uint32_t)0x00020000) /*!< ADC SMP5 bit 2 */
mbed_official 403:91a4bea587f4 1032
mbed_official 403:91a4bea587f4 1033 #define ADC_SMPR1_SMP6 ((uint32_t)0x001C0000) /*!< ADC Channel 6 Sampling time selection */
mbed_official 403:91a4bea587f4 1034 #define ADC_SMPR1_SMP6_0 ((uint32_t)0x00040000) /*!< ADC SMP6 bit 0 */
mbed_official 403:91a4bea587f4 1035 #define ADC_SMPR1_SMP6_1 ((uint32_t)0x00080000) /*!< ADC SMP6 bit 1 */
mbed_official 403:91a4bea587f4 1036 #define ADC_SMPR1_SMP6_2 ((uint32_t)0x00100000) /*!< ADC SMP6 bit 2 */
mbed_official 403:91a4bea587f4 1037
mbed_official 403:91a4bea587f4 1038 #define ADC_SMPR1_SMP7 ((uint32_t)0x00E00000) /*!< ADC Channel 7 Sampling time selection */
mbed_official 403:91a4bea587f4 1039 #define ADC_SMPR1_SMP7_0 ((uint32_t)0x00200000) /*!< ADC SMP7 bit 0 */
mbed_official 403:91a4bea587f4 1040 #define ADC_SMPR1_SMP7_1 ((uint32_t)0x00400000) /*!< ADC SMP7 bit 1 */
mbed_official 403:91a4bea587f4 1041 #define ADC_SMPR1_SMP7_2 ((uint32_t)0x00800000) /*!< ADC SMP7 bit 2 */
mbed_official 403:91a4bea587f4 1042
mbed_official 403:91a4bea587f4 1043 #define ADC_SMPR1_SMP8 ((uint32_t)0x07000000) /*!< ADC Channel 8 Sampling time selection */
mbed_official 403:91a4bea587f4 1044 #define ADC_SMPR1_SMP8_0 ((uint32_t)0x01000000) /*!< ADC SMP8 bit 0 */
mbed_official 403:91a4bea587f4 1045 #define ADC_SMPR1_SMP8_1 ((uint32_t)0x02000000) /*!< ADC SMP8 bit 1 */
mbed_official 403:91a4bea587f4 1046 #define ADC_SMPR1_SMP8_2 ((uint32_t)0x04000000) /*!< ADC SMP8 bit 2 */
mbed_official 403:91a4bea587f4 1047
mbed_official 403:91a4bea587f4 1048 #define ADC_SMPR1_SMP9 ((uint32_t)0x38000000) /*!< ADC Channel 9 Sampling time selection */
mbed_official 403:91a4bea587f4 1049 #define ADC_SMPR1_SMP9_0 ((uint32_t)0x08000000) /*!< ADC SMP9 bit 0 */
mbed_official 403:91a4bea587f4 1050 #define ADC_SMPR1_SMP9_1 ((uint32_t)0x10000000) /*!< ADC SMP9 bit 1 */
mbed_official 403:91a4bea587f4 1051 #define ADC_SMPR1_SMP9_2 ((uint32_t)0x20000000) /*!< ADC SMP9 bit 2 */
mbed_official 403:91a4bea587f4 1052
mbed_official 403:91a4bea587f4 1053 /******************** Bit definition for ADC_SMPR2 register ********************/
mbed_official 403:91a4bea587f4 1054 #define ADC_SMPR2_SMP10 ((uint32_t)0x00000007) /*!< ADC Channel 10 Sampling time selection */
mbed_official 403:91a4bea587f4 1055 #define ADC_SMPR2_SMP10_0 ((uint32_t)0x00000001) /*!< ADC SMP10 bit 0 */
mbed_official 403:91a4bea587f4 1056 #define ADC_SMPR2_SMP10_1 ((uint32_t)0x00000002) /*!< ADC SMP10 bit 1 */
mbed_official 403:91a4bea587f4 1057 #define ADC_SMPR2_SMP10_2 ((uint32_t)0x00000004) /*!< ADC SMP10 bit 2 */
mbed_official 403:91a4bea587f4 1058
mbed_official 403:91a4bea587f4 1059 #define ADC_SMPR2_SMP11 ((uint32_t)0x00000038) /*!< ADC Channel 11 Sampling time selection */
mbed_official 403:91a4bea587f4 1060 #define ADC_SMPR2_SMP11_0 ((uint32_t)0x00000008) /*!< ADC SMP11 bit 0 */
mbed_official 403:91a4bea587f4 1061 #define ADC_SMPR2_SMP11_1 ((uint32_t)0x00000010) /*!< ADC SMP11 bit 1 */
mbed_official 403:91a4bea587f4 1062 #define ADC_SMPR2_SMP11_2 ((uint32_t)0x00000020) /*!< ADC SMP11 bit 2 */
mbed_official 403:91a4bea587f4 1063
mbed_official 403:91a4bea587f4 1064 #define ADC_SMPR2_SMP12 ((uint32_t)0x000001C0) /*!< ADC Channel 12 Sampling time selection */
mbed_official 403:91a4bea587f4 1065 #define ADC_SMPR2_SMP12_0 ((uint32_t)0x00000040) /*!< ADC SMP12 bit 0 */
mbed_official 403:91a4bea587f4 1066 #define ADC_SMPR2_SMP12_1 ((uint32_t)0x00000080) /*!< ADC SMP12 bit 1 */
mbed_official 403:91a4bea587f4 1067 #define ADC_SMPR2_SMP12_2 ((uint32_t)0x00000100) /*!< ADC SMP12 bit 2 */
mbed_official 403:91a4bea587f4 1068
mbed_official 403:91a4bea587f4 1069 #define ADC_SMPR2_SMP13 ((uint32_t)0x00000E00) /*!< ADC Channel 13 Sampling time selection */
mbed_official 403:91a4bea587f4 1070 #define ADC_SMPR2_SMP13_0 ((uint32_t)0x00000200) /*!< ADC SMP13 bit 0 */
mbed_official 403:91a4bea587f4 1071 #define ADC_SMPR2_SMP13_1 ((uint32_t)0x00000400) /*!< ADC SMP13 bit 1 */
mbed_official 403:91a4bea587f4 1072 #define ADC_SMPR2_SMP13_2 ((uint32_t)0x00000800) /*!< ADC SMP13 bit 2 */
mbed_official 403:91a4bea587f4 1073
mbed_official 403:91a4bea587f4 1074 #define ADC_SMPR2_SMP14 ((uint32_t)0x00007000) /*!< ADC Channel 14 Sampling time selection */
mbed_official 403:91a4bea587f4 1075 #define ADC_SMPR2_SMP14_0 ((uint32_t)0x00001000) /*!< ADC SMP14 bit 0 */
mbed_official 403:91a4bea587f4 1076 #define ADC_SMPR2_SMP14_1 ((uint32_t)0x00002000) /*!< ADC SMP14 bit 1 */
mbed_official 403:91a4bea587f4 1077 #define ADC_SMPR2_SMP14_2 ((uint32_t)0x00004000) /*!< ADC SMP14 bit 2 */
mbed_official 403:91a4bea587f4 1078
mbed_official 403:91a4bea587f4 1079 #define ADC_SMPR2_SMP15 ((uint32_t)0x00038000) /*!< ADC Channel 15 Sampling time selection */
mbed_official 403:91a4bea587f4 1080 #define ADC_SMPR2_SMP15_0 ((uint32_t)0x00008000) /*!< ADC SMP15 bit 0 */
mbed_official 403:91a4bea587f4 1081 #define ADC_SMPR2_SMP15_1 ((uint32_t)0x00010000) /*!< ADC SMP15 bit 1 */
mbed_official 403:91a4bea587f4 1082 #define ADC_SMPR2_SMP15_2 ((uint32_t)0x00020000) /*!< ADC SMP15 bit 2 */
mbed_official 403:91a4bea587f4 1083
mbed_official 403:91a4bea587f4 1084 #define ADC_SMPR2_SMP16 ((uint32_t)0x001C0000) /*!< ADC Channel 16 Sampling time selection */
mbed_official 403:91a4bea587f4 1085 #define ADC_SMPR2_SMP16_0 ((uint32_t)0x00040000) /*!< ADC SMP16 bit 0 */
mbed_official 403:91a4bea587f4 1086 #define ADC_SMPR2_SMP16_1 ((uint32_t)0x00080000) /*!< ADC SMP16 bit 1 */
mbed_official 403:91a4bea587f4 1087 #define ADC_SMPR2_SMP16_2 ((uint32_t)0x00100000) /*!< ADC SMP16 bit 2 */
mbed_official 403:91a4bea587f4 1088
mbed_official 403:91a4bea587f4 1089 #define ADC_SMPR2_SMP17 ((uint32_t)0x00E00000) /*!< ADC Channel 17 Sampling time selection */
mbed_official 403:91a4bea587f4 1090 #define ADC_SMPR2_SMP17_0 ((uint32_t)0x00200000) /*!< ADC SMP17 bit 0 */
mbed_official 403:91a4bea587f4 1091 #define ADC_SMPR2_SMP17_1 ((uint32_t)0x00400000) /*!< ADC SMP17 bit 1 */
mbed_official 403:91a4bea587f4 1092 #define ADC_SMPR2_SMP17_2 ((uint32_t)0x00800000) /*!< ADC SMP17 bit 2 */
mbed_official 403:91a4bea587f4 1093
mbed_official 403:91a4bea587f4 1094 #define ADC_SMPR2_SMP18 ((uint32_t)0x07000000) /*!< ADC Channel 18 Sampling time selection */
mbed_official 403:91a4bea587f4 1095 #define ADC_SMPR2_SMP18_0 ((uint32_t)0x01000000) /*!< ADC SMP18 bit 0 */
mbed_official 403:91a4bea587f4 1096 #define ADC_SMPR2_SMP18_1 ((uint32_t)0x02000000) /*!< ADC SMP18 bit 1 */
mbed_official 403:91a4bea587f4 1097 #define ADC_SMPR2_SMP18_2 ((uint32_t)0x04000000) /*!< ADC SMP18 bit 2 */
mbed_official 403:91a4bea587f4 1098
mbed_official 403:91a4bea587f4 1099 /******************** Bit definition for ADC_TR1 register ********************/
mbed_official 403:91a4bea587f4 1100 #define ADC_TR1_LT1 ((uint32_t)0x00000FFF) /*!< ADC Analog watchdog 1 lower threshold */
mbed_official 403:91a4bea587f4 1101 #define ADC_TR1_LT1_0 ((uint32_t)0x00000001) /*!< ADC LT1 bit 0 */
mbed_official 403:91a4bea587f4 1102 #define ADC_TR1_LT1_1 ((uint32_t)0x00000002) /*!< ADC LT1 bit 1 */
mbed_official 403:91a4bea587f4 1103 #define ADC_TR1_LT1_2 ((uint32_t)0x00000004) /*!< ADC LT1 bit 2 */
mbed_official 403:91a4bea587f4 1104 #define ADC_TR1_LT1_3 ((uint32_t)0x00000008) /*!< ADC LT1 bit 3 */
mbed_official 403:91a4bea587f4 1105 #define ADC_TR1_LT1_4 ((uint32_t)0x00000010) /*!< ADC LT1 bit 4 */
mbed_official 403:91a4bea587f4 1106 #define ADC_TR1_LT1_5 ((uint32_t)0x00000020) /*!< ADC LT1 bit 5 */
mbed_official 403:91a4bea587f4 1107 #define ADC_TR1_LT1_6 ((uint32_t)0x00000040) /*!< ADC LT1 bit 6 */
mbed_official 403:91a4bea587f4 1108 #define ADC_TR1_LT1_7 ((uint32_t)0x00000080) /*!< ADC LT1 bit 7 */
mbed_official 403:91a4bea587f4 1109 #define ADC_TR1_LT1_8 ((uint32_t)0x00000100) /*!< ADC LT1 bit 8 */
mbed_official 403:91a4bea587f4 1110 #define ADC_TR1_LT1_9 ((uint32_t)0x00000200) /*!< ADC LT1 bit 9 */
mbed_official 403:91a4bea587f4 1111 #define ADC_TR1_LT1_10 ((uint32_t)0x00000400) /*!< ADC LT1 bit 10 */
mbed_official 403:91a4bea587f4 1112 #define ADC_TR1_LT1_11 ((uint32_t)0x00000800) /*!< ADC LT1 bit 11 */
mbed_official 403:91a4bea587f4 1113
mbed_official 403:91a4bea587f4 1114 #define ADC_TR1_HT1 ((uint32_t)0x0FFF0000) /*!< ADC Analog watchdog 1 higher threshold */
mbed_official 403:91a4bea587f4 1115 #define ADC_TR1_HT1_0 ((uint32_t)0x00010000) /*!< ADC HT1 bit 0 */
mbed_official 403:91a4bea587f4 1116 #define ADC_TR1_HT1_1 ((uint32_t)0x00020000) /*!< ADC HT1 bit 1 */
mbed_official 403:91a4bea587f4 1117 #define ADC_TR1_HT1_2 ((uint32_t)0x00040000) /*!< ADC HT1 bit 2 */
mbed_official 403:91a4bea587f4 1118 #define ADC_TR1_HT1_3 ((uint32_t)0x00080000) /*!< ADC HT1 bit 3 */
mbed_official 403:91a4bea587f4 1119 #define ADC_TR1_HT1_4 ((uint32_t)0x00100000) /*!< ADC HT1 bit 4 */
mbed_official 403:91a4bea587f4 1120 #define ADC_TR1_HT1_5 ((uint32_t)0x00200000) /*!< ADC HT1 bit 5 */
mbed_official 403:91a4bea587f4 1121 #define ADC_TR1_HT1_6 ((uint32_t)0x00400000) /*!< ADC HT1 bit 6 */
mbed_official 403:91a4bea587f4 1122 #define ADC_TR1_HT1_7 ((uint32_t)0x00800000) /*!< ADC HT1 bit 7 */
mbed_official 403:91a4bea587f4 1123 #define ADC_TR1_HT1_8 ((uint32_t)0x01000000) /*!< ADC HT1 bit 8 */
mbed_official 403:91a4bea587f4 1124 #define ADC_TR1_HT1_9 ((uint32_t)0x02000000) /*!< ADC HT1 bit 9 */
mbed_official 403:91a4bea587f4 1125 #define ADC_TR1_HT1_10 ((uint32_t)0x04000000) /*!< ADC HT1 bit 10 */
mbed_official 403:91a4bea587f4 1126 #define ADC_TR1_HT1_11 ((uint32_t)0x08000000) /*!< ADC HT1 bit 11 */
mbed_official 403:91a4bea587f4 1127
mbed_official 403:91a4bea587f4 1128 /******************** Bit definition for ADC_TR2 register ********************/
mbed_official 403:91a4bea587f4 1129 #define ADC_TR2_LT2 ((uint32_t)0x000000FF) /*!< ADC Analog watchdog 2 lower threshold */
mbed_official 403:91a4bea587f4 1130 #define ADC_TR2_LT2_0 ((uint32_t)0x00000001) /*!< ADC LT2 bit 0 */
mbed_official 403:91a4bea587f4 1131 #define ADC_TR2_LT2_1 ((uint32_t)0x00000002) /*!< ADC LT2 bit 1 */
mbed_official 403:91a4bea587f4 1132 #define ADC_TR2_LT2_2 ((uint32_t)0x00000004) /*!< ADC LT2 bit 2 */
mbed_official 403:91a4bea587f4 1133 #define ADC_TR2_LT2_3 ((uint32_t)0x00000008) /*!< ADC LT2 bit 3 */
mbed_official 403:91a4bea587f4 1134 #define ADC_TR2_LT2_4 ((uint32_t)0x00000010) /*!< ADC LT2 bit 4 */
mbed_official 403:91a4bea587f4 1135 #define ADC_TR2_LT2_5 ((uint32_t)0x00000020) /*!< ADC LT2 bit 5 */
mbed_official 403:91a4bea587f4 1136 #define ADC_TR2_LT2_6 ((uint32_t)0x00000040) /*!< ADC LT2 bit 6 */
mbed_official 403:91a4bea587f4 1137 #define ADC_TR2_LT2_7 ((uint32_t)0x00000080) /*!< ADC LT2 bit 7 */
mbed_official 403:91a4bea587f4 1138
mbed_official 403:91a4bea587f4 1139 #define ADC_TR2_HT2 ((uint32_t)0x00FF0000) /*!< ADC Analog watchdog 2 higher threshold */
mbed_official 403:91a4bea587f4 1140 #define ADC_TR2_HT2_0 ((uint32_t)0x00010000) /*!< ADC HT2 bit 0 */
mbed_official 403:91a4bea587f4 1141 #define ADC_TR2_HT2_1 ((uint32_t)0x00020000) /*!< ADC HT2 bit 1 */
mbed_official 403:91a4bea587f4 1142 #define ADC_TR2_HT2_2 ((uint32_t)0x00040000) /*!< ADC HT2 bit 2 */
mbed_official 403:91a4bea587f4 1143 #define ADC_TR2_HT2_3 ((uint32_t)0x00080000) /*!< ADC HT2 bit 3 */
mbed_official 403:91a4bea587f4 1144 #define ADC_TR2_HT2_4 ((uint32_t)0x00100000) /*!< ADC HT2 bit 4 */
mbed_official 403:91a4bea587f4 1145 #define ADC_TR2_HT2_5 ((uint32_t)0x00200000) /*!< ADC HT2 bit 5 */
mbed_official 403:91a4bea587f4 1146 #define ADC_TR2_HT2_6 ((uint32_t)0x00400000) /*!< ADC HT2 bit 6 */
mbed_official 403:91a4bea587f4 1147 #define ADC_TR2_HT2_7 ((uint32_t)0x00800000) /*!< ADC HT2 bit 7 */
mbed_official 403:91a4bea587f4 1148
mbed_official 403:91a4bea587f4 1149 /******************** Bit definition for ADC_TR3 register ********************/
mbed_official 403:91a4bea587f4 1150 #define ADC_TR3_LT3 ((uint32_t)0x000000FF) /*!< ADC Analog watchdog 3 lower threshold */
mbed_official 403:91a4bea587f4 1151 #define ADC_TR3_LT3_0 ((uint32_t)0x00000001) /*!< ADC LT3 bit 0 */
mbed_official 403:91a4bea587f4 1152 #define ADC_TR3_LT3_1 ((uint32_t)0x00000002) /*!< ADC LT3 bit 1 */
mbed_official 403:91a4bea587f4 1153 #define ADC_TR3_LT3_2 ((uint32_t)0x00000004) /*!< ADC LT3 bit 2 */
mbed_official 403:91a4bea587f4 1154 #define ADC_TR3_LT3_3 ((uint32_t)0x00000008) /*!< ADC LT3 bit 3 */
mbed_official 403:91a4bea587f4 1155 #define ADC_TR3_LT3_4 ((uint32_t)0x00000010) /*!< ADC LT3 bit 4 */
mbed_official 403:91a4bea587f4 1156 #define ADC_TR3_LT3_5 ((uint32_t)0x00000020) /*!< ADC LT3 bit 5 */
mbed_official 403:91a4bea587f4 1157 #define ADC_TR3_LT3_6 ((uint32_t)0x00000040) /*!< ADC LT3 bit 6 */
mbed_official 403:91a4bea587f4 1158 #define ADC_TR3_LT3_7 ((uint32_t)0x00000080) /*!< ADC LT3 bit 7 */
mbed_official 403:91a4bea587f4 1159
mbed_official 403:91a4bea587f4 1160 #define ADC_TR3_HT3 ((uint32_t)0x00FF0000) /*!< ADC Analog watchdog 3 higher threshold */
mbed_official 403:91a4bea587f4 1161 #define ADC_TR3_HT3_0 ((uint32_t)0x00010000) /*!< ADC HT3 bit 0 */
mbed_official 403:91a4bea587f4 1162 #define ADC_TR3_HT3_1 ((uint32_t)0x00020000) /*!< ADC HT3 bit 1 */
mbed_official 403:91a4bea587f4 1163 #define ADC_TR3_HT3_2 ((uint32_t)0x00040000) /*!< ADC HT3 bit 2 */
mbed_official 403:91a4bea587f4 1164 #define ADC_TR3_HT3_3 ((uint32_t)0x00080000) /*!< ADC HT3 bit 3 */
mbed_official 403:91a4bea587f4 1165 #define ADC_TR3_HT3_4 ((uint32_t)0x00100000) /*!< ADC HT3 bit 4 */
mbed_official 403:91a4bea587f4 1166 #define ADC_TR3_HT3_5 ((uint32_t)0x00200000) /*!< ADC HT3 bit 5 */
mbed_official 403:91a4bea587f4 1167 #define ADC_TR3_HT3_6 ((uint32_t)0x00400000) /*!< ADC HT3 bit 6 */
mbed_official 403:91a4bea587f4 1168 #define ADC_TR3_HT3_7 ((uint32_t)0x00800000) /*!< ADC HT3 bit 7 */
mbed_official 403:91a4bea587f4 1169
mbed_official 403:91a4bea587f4 1170 /******************** Bit definition for ADC_SQR1 register ********************/
mbed_official 403:91a4bea587f4 1171 #define ADC_SQR1_L ((uint32_t)0x0000000F) /*!< ADC regular channel sequence lenght */
mbed_official 403:91a4bea587f4 1172 #define ADC_SQR1_L_0 ((uint32_t)0x00000001) /*!< ADC L bit 0 */
mbed_official 403:91a4bea587f4 1173 #define ADC_SQR1_L_1 ((uint32_t)0x00000002) /*!< ADC L bit 1 */
mbed_official 403:91a4bea587f4 1174 #define ADC_SQR1_L_2 ((uint32_t)0x00000004) /*!< ADC L bit 2 */
mbed_official 403:91a4bea587f4 1175 #define ADC_SQR1_L_3 ((uint32_t)0x00000008) /*!< ADC L bit 3 */
mbed_official 403:91a4bea587f4 1176
mbed_official 403:91a4bea587f4 1177 #define ADC_SQR1_SQ1 ((uint32_t)0x000007C0) /*!< ADC 1st conversion in regular sequence */
mbed_official 403:91a4bea587f4 1178 #define ADC_SQR1_SQ1_0 ((uint32_t)0x00000040) /*!< ADC SQ1 bit 0 */
mbed_official 403:91a4bea587f4 1179 #define ADC_SQR1_SQ1_1 ((uint32_t)0x00000080) /*!< ADC SQ1 bit 1 */
mbed_official 403:91a4bea587f4 1180 #define ADC_SQR1_SQ1_2 ((uint32_t)0x00000100) /*!< ADC SQ1 bit 2 */
mbed_official 403:91a4bea587f4 1181 #define ADC_SQR1_SQ1_3 ((uint32_t)0x00000200) /*!< ADC SQ1 bit 3 */
mbed_official 403:91a4bea587f4 1182 #define ADC_SQR1_SQ1_4 ((uint32_t)0x00000400) /*!< ADC SQ1 bit 4 */
mbed_official 403:91a4bea587f4 1183
mbed_official 403:91a4bea587f4 1184 #define ADC_SQR1_SQ2 ((uint32_t)0x0001F000) /*!< ADC 2nd conversion in regular sequence */
mbed_official 403:91a4bea587f4 1185 #define ADC_SQR1_SQ2_0 ((uint32_t)0x00001000) /*!< ADC SQ2 bit 0 */
mbed_official 403:91a4bea587f4 1186 #define ADC_SQR1_SQ2_1 ((uint32_t)0x00002000) /*!< ADC SQ2 bit 1 */
mbed_official 403:91a4bea587f4 1187 #define ADC_SQR1_SQ2_2 ((uint32_t)0x00004000) /*!< ADC SQ2 bit 2 */
mbed_official 403:91a4bea587f4 1188 #define ADC_SQR1_SQ2_3 ((uint32_t)0x00008000) /*!< ADC SQ2 bit 3 */
mbed_official 403:91a4bea587f4 1189 #define ADC_SQR1_SQ2_4 ((uint32_t)0x00010000) /*!< ADC SQ2 bit 4 */
mbed_official 403:91a4bea587f4 1190
mbed_official 403:91a4bea587f4 1191 #define ADC_SQR1_SQ3 ((uint32_t)0x007C0000) /*!< ADC 3rd conversion in regular sequence */
mbed_official 403:91a4bea587f4 1192 #define ADC_SQR1_SQ3_0 ((uint32_t)0x00040000) /*!< ADC SQ3 bit 0 */
mbed_official 403:91a4bea587f4 1193 #define ADC_SQR1_SQ3_1 ((uint32_t)0x00080000) /*!< ADC SQ3 bit 1 */
mbed_official 403:91a4bea587f4 1194 #define ADC_SQR1_SQ3_2 ((uint32_t)0x00100000) /*!< ADC SQ3 bit 2 */
mbed_official 403:91a4bea587f4 1195 #define ADC_SQR1_SQ3_3 ((uint32_t)0x00200000) /*!< ADC SQ3 bit 3 */
mbed_official 403:91a4bea587f4 1196 #define ADC_SQR1_SQ3_4 ((uint32_t)0x00400000) /*!< ADC SQ3 bit 4 */
mbed_official 403:91a4bea587f4 1197
mbed_official 403:91a4bea587f4 1198 #define ADC_SQR1_SQ4 ((uint32_t)0x1F000000) /*!< ADC 4th conversion in regular sequence */
mbed_official 403:91a4bea587f4 1199 #define ADC_SQR1_SQ4_0 ((uint32_t)0x01000000) /*!< ADC SQ4 bit 0 */
mbed_official 403:91a4bea587f4 1200 #define ADC_SQR1_SQ4_1 ((uint32_t)0x02000000) /*!< ADC SQ4 bit 1 */
mbed_official 403:91a4bea587f4 1201 #define ADC_SQR1_SQ4_2 ((uint32_t)0x04000000) /*!< ADC SQ4 bit 2 */
mbed_official 403:91a4bea587f4 1202 #define ADC_SQR1_SQ4_3 ((uint32_t)0x08000000) /*!< ADC SQ4 bit 3 */
mbed_official 403:91a4bea587f4 1203 #define ADC_SQR1_SQ4_4 ((uint32_t)0x10000000) /*!< ADC SQ4 bit 4 */
mbed_official 403:91a4bea587f4 1204
mbed_official 403:91a4bea587f4 1205 /******************** Bit definition for ADC_SQR2 register ********************/
mbed_official 403:91a4bea587f4 1206 #define ADC_SQR2_SQ5 ((uint32_t)0x0000001F) /*!< ADC 5th conversion in regular sequence */
mbed_official 403:91a4bea587f4 1207 #define ADC_SQR2_SQ5_0 ((uint32_t)0x00000001) /*!< ADC SQ5 bit 0 */
mbed_official 403:91a4bea587f4 1208 #define ADC_SQR2_SQ5_1 ((uint32_t)0x00000002) /*!< ADC SQ5 bit 1 */
mbed_official 403:91a4bea587f4 1209 #define ADC_SQR2_SQ5_2 ((uint32_t)0x00000004) /*!< ADC SQ5 bit 2 */
mbed_official 403:91a4bea587f4 1210 #define ADC_SQR2_SQ5_3 ((uint32_t)0x00000008) /*!< ADC SQ5 bit 3 */
mbed_official 403:91a4bea587f4 1211 #define ADC_SQR2_SQ5_4 ((uint32_t)0x00000010) /*!< ADC SQ5 bit 4 */
mbed_official 403:91a4bea587f4 1212
mbed_official 403:91a4bea587f4 1213 #define ADC_SQR2_SQ6 ((uint32_t)0x000007C0) /*!< ADC 6th conversion in regular sequence */
mbed_official 403:91a4bea587f4 1214 #define ADC_SQR2_SQ6_0 ((uint32_t)0x00000040) /*!< ADC SQ6 bit 0 */
mbed_official 403:91a4bea587f4 1215 #define ADC_SQR2_SQ6_1 ((uint32_t)0x00000080) /*!< ADC SQ6 bit 1 */
mbed_official 403:91a4bea587f4 1216 #define ADC_SQR2_SQ6_2 ((uint32_t)0x00000100) /*!< ADC SQ6 bit 2 */
mbed_official 403:91a4bea587f4 1217 #define ADC_SQR2_SQ6_3 ((uint32_t)0x00000200) /*!< ADC SQ6 bit 3 */
mbed_official 403:91a4bea587f4 1218 #define ADC_SQR2_SQ6_4 ((uint32_t)0x00000400) /*!< ADC SQ6 bit 4 */
mbed_official 403:91a4bea587f4 1219
mbed_official 403:91a4bea587f4 1220 #define ADC_SQR2_SQ7 ((uint32_t)0x0001F000) /*!< ADC 7th conversion in regular sequence */
mbed_official 403:91a4bea587f4 1221 #define ADC_SQR2_SQ7_0 ((uint32_t)0x00001000) /*!< ADC SQ7 bit 0 */
mbed_official 403:91a4bea587f4 1222 #define ADC_SQR2_SQ7_1 ((uint32_t)0x00002000) /*!< ADC SQ7 bit 1 */
mbed_official 403:91a4bea587f4 1223 #define ADC_SQR2_SQ7_2 ((uint32_t)0x00004000) /*!< ADC SQ7 bit 2 */
mbed_official 403:91a4bea587f4 1224 #define ADC_SQR2_SQ7_3 ((uint32_t)0x00008000) /*!< ADC SQ7 bit 3 */
mbed_official 403:91a4bea587f4 1225 #define ADC_SQR2_SQ7_4 ((uint32_t)0x00010000) /*!< ADC SQ7 bit 4 */
mbed_official 403:91a4bea587f4 1226
mbed_official 403:91a4bea587f4 1227 #define ADC_SQR2_SQ8 ((uint32_t)0x007C0000) /*!< ADC 8th conversion in regular sequence */
mbed_official 403:91a4bea587f4 1228 #define ADC_SQR2_SQ8_0 ((uint32_t)0x00040000) /*!< ADC SQ8 bit 0 */
mbed_official 403:91a4bea587f4 1229 #define ADC_SQR2_SQ8_1 ((uint32_t)0x00080000) /*!< ADC SQ8 bit 1 */
mbed_official 403:91a4bea587f4 1230 #define ADC_SQR2_SQ8_2 ((uint32_t)0x00100000) /*!< ADC SQ8 bit 2 */
mbed_official 403:91a4bea587f4 1231 #define ADC_SQR2_SQ8_3 ((uint32_t)0x00200000) /*!< ADC SQ8 bit 3 */
mbed_official 403:91a4bea587f4 1232 #define ADC_SQR2_SQ8_4 ((uint32_t)0x00400000) /*!< ADC SQ8 bit 4 */
mbed_official 403:91a4bea587f4 1233
mbed_official 403:91a4bea587f4 1234 #define ADC_SQR2_SQ9 ((uint32_t)0x1F000000) /*!< ADC 9th conversion in regular sequence */
mbed_official 403:91a4bea587f4 1235 #define ADC_SQR2_SQ9_0 ((uint32_t)0x01000000) /*!< ADC SQ9 bit 0 */
mbed_official 403:91a4bea587f4 1236 #define ADC_SQR2_SQ9_1 ((uint32_t)0x02000000) /*!< ADC SQ9 bit 1 */
mbed_official 403:91a4bea587f4 1237 #define ADC_SQR2_SQ9_2 ((uint32_t)0x04000000) /*!< ADC SQ9 bit 2 */
mbed_official 403:91a4bea587f4 1238 #define ADC_SQR2_SQ9_3 ((uint32_t)0x08000000) /*!< ADC SQ9 bit 3 */
mbed_official 403:91a4bea587f4 1239 #define ADC_SQR2_SQ9_4 ((uint32_t)0x10000000) /*!< ADC SQ9 bit 4 */
mbed_official 403:91a4bea587f4 1240
mbed_official 403:91a4bea587f4 1241 /******************** Bit definition for ADC_SQR3 register ********************/
mbed_official 403:91a4bea587f4 1242 #define ADC_SQR3_SQ10 ((uint32_t)0x0000001F) /*!< ADC 10th conversion in regular sequence */
mbed_official 403:91a4bea587f4 1243 #define ADC_SQR3_SQ10_0 ((uint32_t)0x00000001) /*!< ADC SQ10 bit 0 */
mbed_official 403:91a4bea587f4 1244 #define ADC_SQR3_SQ10_1 ((uint32_t)0x00000002) /*!< ADC SQ10 bit 1 */
mbed_official 403:91a4bea587f4 1245 #define ADC_SQR3_SQ10_2 ((uint32_t)0x00000004) /*!< ADC SQ10 bit 2 */
mbed_official 403:91a4bea587f4 1246 #define ADC_SQR3_SQ10_3 ((uint32_t)0x00000008) /*!< ADC SQ10 bit 3 */
mbed_official 403:91a4bea587f4 1247 #define ADC_SQR3_SQ10_4 ((uint32_t)0x00000010) /*!< ADC SQ10 bit 4 */
mbed_official 403:91a4bea587f4 1248
mbed_official 403:91a4bea587f4 1249 #define ADC_SQR3_SQ11 ((uint32_t)0x000007C0) /*!< ADC 11th conversion in regular sequence */
mbed_official 403:91a4bea587f4 1250 #define ADC_SQR3_SQ11_0 ((uint32_t)0x00000040) /*!< ADC SQ11 bit 0 */
mbed_official 403:91a4bea587f4 1251 #define ADC_SQR3_SQ11_1 ((uint32_t)0x00000080) /*!< ADC SQ11 bit 1 */
mbed_official 403:91a4bea587f4 1252 #define ADC_SQR3_SQ11_2 ((uint32_t)0x00000100) /*!< ADC SQ11 bit 2 */
mbed_official 403:91a4bea587f4 1253 #define ADC_SQR3_SQ11_3 ((uint32_t)0x00000200) /*!< ADC SQ11 bit 3 */
mbed_official 403:91a4bea587f4 1254 #define ADC_SQR3_SQ11_4 ((uint32_t)0x00000400) /*!< ADC SQ11 bit 4 */
mbed_official 403:91a4bea587f4 1255
mbed_official 403:91a4bea587f4 1256 #define ADC_SQR3_SQ12 ((uint32_t)0x0001F000) /*!< ADC 12th conversion in regular sequence */
mbed_official 403:91a4bea587f4 1257 #define ADC_SQR3_SQ12_0 ((uint32_t)0x00001000) /*!< ADC SQ12 bit 0 */
mbed_official 403:91a4bea587f4 1258 #define ADC_SQR3_SQ12_1 ((uint32_t)0x00002000) /*!< ADC SQ12 bit 1 */
mbed_official 403:91a4bea587f4 1259 #define ADC_SQR3_SQ12_2 ((uint32_t)0x00004000) /*!< ADC SQ12 bit 2 */
mbed_official 403:91a4bea587f4 1260 #define ADC_SQR3_SQ12_3 ((uint32_t)0x00008000) /*!< ADC SQ12 bit 3 */
mbed_official 403:91a4bea587f4 1261 #define ADC_SQR3_SQ12_4 ((uint32_t)0x00010000) /*!< ADC SQ12 bit 4 */
mbed_official 403:91a4bea587f4 1262
mbed_official 403:91a4bea587f4 1263 #define ADC_SQR3_SQ13 ((uint32_t)0x007C0000) /*!< ADC 13th conversion in regular sequence */
mbed_official 403:91a4bea587f4 1264 #define ADC_SQR3_SQ13_0 ((uint32_t)0x00040000) /*!< ADC SQ13 bit 0 */
mbed_official 403:91a4bea587f4 1265 #define ADC_SQR3_SQ13_1 ((uint32_t)0x00080000) /*!< ADC SQ13 bit 1 */
mbed_official 403:91a4bea587f4 1266 #define ADC_SQR3_SQ13_2 ((uint32_t)0x00100000) /*!< ADC SQ13 bit 2 */
mbed_official 403:91a4bea587f4 1267 #define ADC_SQR3_SQ13_3 ((uint32_t)0x00200000) /*!< ADC SQ13 bit 3 */
mbed_official 403:91a4bea587f4 1268 #define ADC_SQR3_SQ13_4 ((uint32_t)0x00400000) /*!< ADC SQ13 bit 4 */
mbed_official 403:91a4bea587f4 1269
mbed_official 403:91a4bea587f4 1270 #define ADC_SQR3_SQ14 ((uint32_t)0x1F000000) /*!< ADC 14th conversion in regular sequence */
mbed_official 403:91a4bea587f4 1271 #define ADC_SQR3_SQ14_0 ((uint32_t)0x01000000) /*!< ADC SQ14 bit 0 */
mbed_official 403:91a4bea587f4 1272 #define ADC_SQR3_SQ14_1 ((uint32_t)0x02000000) /*!< ADC SQ14 bit 1 */
mbed_official 403:91a4bea587f4 1273 #define ADC_SQR3_SQ14_2 ((uint32_t)0x04000000) /*!< ADC SQ14 bit 2 */
mbed_official 403:91a4bea587f4 1274 #define ADC_SQR3_SQ14_3 ((uint32_t)0x08000000) /*!< ADC SQ14 bit 3 */
mbed_official 403:91a4bea587f4 1275 #define ADC_SQR3_SQ14_4 ((uint32_t)0x10000000) /*!< ADC SQ14 bit 4 */
mbed_official 403:91a4bea587f4 1276
mbed_official 403:91a4bea587f4 1277 /******************** Bit definition for ADC_SQR4 register ********************/
mbed_official 403:91a4bea587f4 1278 #define ADC_SQR4_SQ15 ((uint32_t)0x0000001F) /*!< ADC 15th conversion in regular sequence */
mbed_official 403:91a4bea587f4 1279 #define ADC_SQR4_SQ15_0 ((uint32_t)0x00000001) /*!< ADC SQ15 bit 0 */
mbed_official 403:91a4bea587f4 1280 #define ADC_SQR4_SQ15_1 ((uint32_t)0x00000002) /*!< ADC SQ15 bit 1 */
mbed_official 403:91a4bea587f4 1281 #define ADC_SQR4_SQ15_2 ((uint32_t)0x00000004) /*!< ADC SQ15 bit 2 */
mbed_official 403:91a4bea587f4 1282 #define ADC_SQR4_SQ15_3 ((uint32_t)0x00000008) /*!< ADC SQ15 bit 3 */
mbed_official 403:91a4bea587f4 1283 #define ADC_SQR4_SQ15_4 ((uint32_t)0x00000010) /*!< ADC SQ105 bit 4 */
mbed_official 403:91a4bea587f4 1284
mbed_official 403:91a4bea587f4 1285 #define ADC_SQR4_SQ16 ((uint32_t)0x000007C0) /*!< ADC 16th conversion in regular sequence */
mbed_official 403:91a4bea587f4 1286 #define ADC_SQR4_SQ16_0 ((uint32_t)0x00000040) /*!< ADC SQ16 bit 0 */
mbed_official 403:91a4bea587f4 1287 #define ADC_SQR4_SQ16_1 ((uint32_t)0x00000080) /*!< ADC SQ16 bit 1 */
mbed_official 403:91a4bea587f4 1288 #define ADC_SQR4_SQ16_2 ((uint32_t)0x00000100) /*!< ADC SQ16 bit 2 */
mbed_official 403:91a4bea587f4 1289 #define ADC_SQR4_SQ16_3 ((uint32_t)0x00000200) /*!< ADC SQ16 bit 3 */
mbed_official 403:91a4bea587f4 1290 #define ADC_SQR4_SQ16_4 ((uint32_t)0x00000400) /*!< ADC SQ16 bit 4 */
mbed_official 403:91a4bea587f4 1291 /******************** Bit definition for ADC_DR register ********************/
mbed_official 403:91a4bea587f4 1292 #define ADC_DR_RDATA ((uint32_t)0x0000FFFF) /*!< ADC regular Data converted */
mbed_official 403:91a4bea587f4 1293 #define ADC_DR_RDATA_0 ((uint32_t)0x00000001) /*!< ADC RDATA bit 0 */
mbed_official 403:91a4bea587f4 1294 #define ADC_DR_RDATA_1 ((uint32_t)0x00000002) /*!< ADC RDATA bit 1 */
mbed_official 403:91a4bea587f4 1295 #define ADC_DR_RDATA_2 ((uint32_t)0x00000004) /*!< ADC RDATA bit 2 */
mbed_official 403:91a4bea587f4 1296 #define ADC_DR_RDATA_3 ((uint32_t)0x00000008) /*!< ADC RDATA bit 3 */
mbed_official 403:91a4bea587f4 1297 #define ADC_DR_RDATA_4 ((uint32_t)0x00000010) /*!< ADC RDATA bit 4 */
mbed_official 403:91a4bea587f4 1298 #define ADC_DR_RDATA_5 ((uint32_t)0x00000020) /*!< ADC RDATA bit 5 */
mbed_official 403:91a4bea587f4 1299 #define ADC_DR_RDATA_6 ((uint32_t)0x00000040) /*!< ADC RDATA bit 6 */
mbed_official 403:91a4bea587f4 1300 #define ADC_DR_RDATA_7 ((uint32_t)0x00000080) /*!< ADC RDATA bit 7 */
mbed_official 403:91a4bea587f4 1301 #define ADC_DR_RDATA_8 ((uint32_t)0x00000100) /*!< ADC RDATA bit 8 */
mbed_official 403:91a4bea587f4 1302 #define ADC_DR_RDATA_9 ((uint32_t)0x00000200) /*!< ADC RDATA bit 9 */
mbed_official 403:91a4bea587f4 1303 #define ADC_DR_RDATA_10 ((uint32_t)0x00000400) /*!< ADC RDATA bit 10 */
mbed_official 403:91a4bea587f4 1304 #define ADC_DR_RDATA_11 ((uint32_t)0x00000800) /*!< ADC RDATA bit 11 */
mbed_official 403:91a4bea587f4 1305 #define ADC_DR_RDATA_12 ((uint32_t)0x00001000) /*!< ADC RDATA bit 12 */
mbed_official 403:91a4bea587f4 1306 #define ADC_DR_RDATA_13 ((uint32_t)0x00002000) /*!< ADC RDATA bit 13 */
mbed_official 403:91a4bea587f4 1307 #define ADC_DR_RDATA_14 ((uint32_t)0x00004000) /*!< ADC RDATA bit 14 */
mbed_official 403:91a4bea587f4 1308 #define ADC_DR_RDATA_15 ((uint32_t)0x00008000) /*!< ADC RDATA bit 15 */
mbed_official 403:91a4bea587f4 1309
mbed_official 403:91a4bea587f4 1310 /******************** Bit definition for ADC_JSQR register ********************/
mbed_official 403:91a4bea587f4 1311 #define ADC_JSQR_JL ((uint32_t)0x00000003) /*!< ADC injected channel sequence length */
mbed_official 403:91a4bea587f4 1312 #define ADC_JSQR_JL_0 ((uint32_t)0x00000001) /*!< ADC JL bit 0 */
mbed_official 403:91a4bea587f4 1313 #define ADC_JSQR_JL_1 ((uint32_t)0x00000002) /*!< ADC JL bit 1 */
mbed_official 403:91a4bea587f4 1314
mbed_official 403:91a4bea587f4 1315 #define ADC_JSQR_JEXTSEL ((uint32_t)0x0000003C) /*!< ADC external trigger selection for injected group */
mbed_official 403:91a4bea587f4 1316 #define ADC_JSQR_JEXTSEL_0 ((uint32_t)0x00000004) /*!< ADC JEXTSEL bit 0 */
mbed_official 403:91a4bea587f4 1317 #define ADC_JSQR_JEXTSEL_1 ((uint32_t)0x00000008) /*!< ADC JEXTSEL bit 1 */
mbed_official 403:91a4bea587f4 1318 #define ADC_JSQR_JEXTSEL_2 ((uint32_t)0x00000010) /*!< ADC JEXTSEL bit 2 */
mbed_official 403:91a4bea587f4 1319 #define ADC_JSQR_JEXTSEL_3 ((uint32_t)0x00000020) /*!< ADC JEXTSEL bit 3 */
mbed_official 403:91a4bea587f4 1320
mbed_official 403:91a4bea587f4 1321 #define ADC_JSQR_JEXTEN ((uint32_t)0x000000C0) /*!< ADC external trigger enable and polarity selection for injected channels */
mbed_official 403:91a4bea587f4 1322 #define ADC_JSQR_JEXTEN_0 ((uint32_t)0x00000040) /*!< ADC JEXTEN bit 0 */
mbed_official 403:91a4bea587f4 1323 #define ADC_JSQR_JEXTEN_1 ((uint32_t)0x00000080) /*!< ADC JEXTEN bit 1 */
mbed_official 403:91a4bea587f4 1324
mbed_official 403:91a4bea587f4 1325 #define ADC_JSQR_JSQ1 ((uint32_t)0x00001F00) /*!< ADC 1st conversion in injected sequence */
mbed_official 403:91a4bea587f4 1326 #define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000100) /*!< ADC JSQ1 bit 0 */
mbed_official 403:91a4bea587f4 1327 #define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000200) /*!< ADC JSQ1 bit 1 */
mbed_official 403:91a4bea587f4 1328 #define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000400) /*!< ADC JSQ1 bit 2 */
mbed_official 403:91a4bea587f4 1329 #define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000800) /*!< ADC JSQ1 bit 3 */
mbed_official 403:91a4bea587f4 1330 #define ADC_JSQR_JSQ1_4 ((uint32_t)0x00001000) /*!< ADC JSQ1 bit 4 */
mbed_official 403:91a4bea587f4 1331
mbed_official 403:91a4bea587f4 1332 #define ADC_JSQR_JSQ2 ((uint32_t)0x0007C000) /*!< ADC 2nd conversion in injected sequence */
mbed_official 403:91a4bea587f4 1333 #define ADC_JSQR_JSQ2_0 ((uint32_t)0x00004000) /*!< ADC JSQ2 bit 0 */
mbed_official 403:91a4bea587f4 1334 #define ADC_JSQR_JSQ2_1 ((uint32_t)0x00008000) /*!< ADC JSQ2 bit 1 */
mbed_official 403:91a4bea587f4 1335 #define ADC_JSQR_JSQ2_2 ((uint32_t)0x00010000) /*!< ADC JSQ2 bit 2 */
mbed_official 403:91a4bea587f4 1336 #define ADC_JSQR_JSQ2_3 ((uint32_t)0x00020000) /*!< ADC JSQ2 bit 3 */
mbed_official 403:91a4bea587f4 1337 #define ADC_JSQR_JSQ2_4 ((uint32_t)0x00040000) /*!< ADC JSQ2 bit 4 */
mbed_official 403:91a4bea587f4 1338
mbed_official 403:91a4bea587f4 1339 #define ADC_JSQR_JSQ3 ((uint32_t)0x01F00000) /*!< ADC 3rd conversion in injected sequence */
mbed_official 403:91a4bea587f4 1340 #define ADC_JSQR_JSQ3_0 ((uint32_t)0x00100000) /*!< ADC JSQ3 bit 0 */
mbed_official 403:91a4bea587f4 1341 #define ADC_JSQR_JSQ3_1 ((uint32_t)0x00200000) /*!< ADC JSQ3 bit 1 */
mbed_official 403:91a4bea587f4 1342 #define ADC_JSQR_JSQ3_2 ((uint32_t)0x00400000) /*!< ADC JSQ3 bit 2 */
mbed_official 403:91a4bea587f4 1343 #define ADC_JSQR_JSQ3_3 ((uint32_t)0x00800000) /*!< ADC JSQ3 bit 3 */
mbed_official 403:91a4bea587f4 1344 #define ADC_JSQR_JSQ3_4 ((uint32_t)0x01000000) /*!< ADC JSQ3 bit 4 */
mbed_official 403:91a4bea587f4 1345
mbed_official 403:91a4bea587f4 1346 #define ADC_JSQR_JSQ4 ((uint32_t)0x7C000000) /*!< ADC 4th conversion in injected sequence */
mbed_official 403:91a4bea587f4 1347 #define ADC_JSQR_JSQ4_0 ((uint32_t)0x04000000) /*!< ADC JSQ4 bit 0 */
mbed_official 403:91a4bea587f4 1348 #define ADC_JSQR_JSQ4_1 ((uint32_t)0x08000000) /*!< ADC JSQ4 bit 1 */
mbed_official 403:91a4bea587f4 1349 #define ADC_JSQR_JSQ4_2 ((uint32_t)0x10000000) /*!< ADC JSQ4 bit 2 */
mbed_official 403:91a4bea587f4 1350 #define ADC_JSQR_JSQ4_3 ((uint32_t)0x20000000) /*!< ADC JSQ4 bit 3 */
mbed_official 403:91a4bea587f4 1351 #define ADC_JSQR_JSQ4_4 ((uint32_t)0x40000000) /*!< ADC JSQ4 bit 4 */
mbed_official 403:91a4bea587f4 1352
mbed_official 403:91a4bea587f4 1353 /******************** Bit definition for ADC_OFR1 register ********************/
mbed_official 403:91a4bea587f4 1354 #define ADC_OFR1_OFFSET1 ((uint32_t)0x00000FFF) /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */
mbed_official 403:91a4bea587f4 1355 #define ADC_OFR1_OFFSET1_0 ((uint32_t)0x00000001) /*!< ADC OFFSET1 bit 0 */
mbed_official 403:91a4bea587f4 1356 #define ADC_OFR1_OFFSET1_1 ((uint32_t)0x00000002) /*!< ADC OFFSET1 bit 1 */
mbed_official 403:91a4bea587f4 1357 #define ADC_OFR1_OFFSET1_2 ((uint32_t)0x00000004) /*!< ADC OFFSET1 bit 2 */
mbed_official 403:91a4bea587f4 1358 #define ADC_OFR1_OFFSET1_3 ((uint32_t)0x00000008) /*!< ADC OFFSET1 bit 3 */
mbed_official 403:91a4bea587f4 1359 #define ADC_OFR1_OFFSET1_4 ((uint32_t)0x00000010) /*!< ADC OFFSET1 bit 4 */
mbed_official 403:91a4bea587f4 1360 #define ADC_OFR1_OFFSET1_5 ((uint32_t)0x00000020) /*!< ADC OFFSET1 bit 5 */
mbed_official 403:91a4bea587f4 1361 #define ADC_OFR1_OFFSET1_6 ((uint32_t)0x00000040) /*!< ADC OFFSET1 bit 6 */
mbed_official 403:91a4bea587f4 1362 #define ADC_OFR1_OFFSET1_7 ((uint32_t)0x00000080) /*!< ADC OFFSET1 bit 7 */
mbed_official 403:91a4bea587f4 1363 #define ADC_OFR1_OFFSET1_8 ((uint32_t)0x00000100) /*!< ADC OFFSET1 bit 8 */
mbed_official 403:91a4bea587f4 1364 #define ADC_OFR1_OFFSET1_9 ((uint32_t)0x00000200) /*!< ADC OFFSET1 bit 9 */
mbed_official 403:91a4bea587f4 1365 #define ADC_OFR1_OFFSET1_10 ((uint32_t)0x00000400) /*!< ADC OFFSET1 bit 10 */
mbed_official 403:91a4bea587f4 1366 #define ADC_OFR1_OFFSET1_11 ((uint32_t)0x00000800) /*!< ADC OFFSET1 bit 11 */
mbed_official 403:91a4bea587f4 1367
mbed_official 403:91a4bea587f4 1368 #define ADC_OFR1_OFFSET1_CH ((uint32_t)0x7C000000) /*!< ADC Channel selection for the data offset 1 */
mbed_official 403:91a4bea587f4 1369 #define ADC_OFR1_OFFSET1_CH_0 ((uint32_t)0x04000000) /*!< ADC OFFSET1_CH bit 0 */
mbed_official 403:91a4bea587f4 1370 #define ADC_OFR1_OFFSET1_CH_1 ((uint32_t)0x08000000) /*!< ADC OFFSET1_CH bit 1 */
mbed_official 403:91a4bea587f4 1371 #define ADC_OFR1_OFFSET1_CH_2 ((uint32_t)0x10000000) /*!< ADC OFFSET1_CH bit 2 */
mbed_official 403:91a4bea587f4 1372 #define ADC_OFR1_OFFSET1_CH_3 ((uint32_t)0x20000000) /*!< ADC OFFSET1_CH bit 3 */
mbed_official 403:91a4bea587f4 1373 #define ADC_OFR1_OFFSET1_CH_4 ((uint32_t)0x40000000) /*!< ADC OFFSET1_CH bit 4 */
mbed_official 403:91a4bea587f4 1374
mbed_official 403:91a4bea587f4 1375 #define ADC_OFR1_OFFSET1_EN ((uint32_t)0x80000000) /*!< ADC offset 1 enable */
mbed_official 403:91a4bea587f4 1376
mbed_official 403:91a4bea587f4 1377 /******************** Bit definition for ADC_OFR2 register ********************/
mbed_official 403:91a4bea587f4 1378 #define ADC_OFR2_OFFSET2 ((uint32_t)0x00000FFF) /*!< ADC data offset 2 for channel programmed into bits OFFSET2_CH[4:0] */
mbed_official 403:91a4bea587f4 1379 #define ADC_OFR2_OFFSET2_0 ((uint32_t)0x00000001) /*!< ADC OFFSET2 bit 0 */
mbed_official 403:91a4bea587f4 1380 #define ADC_OFR2_OFFSET2_1 ((uint32_t)0x00000002) /*!< ADC OFFSET2 bit 1 */
mbed_official 403:91a4bea587f4 1381 #define ADC_OFR2_OFFSET2_2 ((uint32_t)0x00000004) /*!< ADC OFFSET2 bit 2 */
mbed_official 403:91a4bea587f4 1382 #define ADC_OFR2_OFFSET2_3 ((uint32_t)0x00000008) /*!< ADC OFFSET2 bit 3 */
mbed_official 403:91a4bea587f4 1383 #define ADC_OFR2_OFFSET2_4 ((uint32_t)0x00000010) /*!< ADC OFFSET2 bit 4 */
mbed_official 403:91a4bea587f4 1384 #define ADC_OFR2_OFFSET2_5 ((uint32_t)0x00000020) /*!< ADC OFFSET2 bit 5 */
mbed_official 403:91a4bea587f4 1385 #define ADC_OFR2_OFFSET2_6 ((uint32_t)0x00000040) /*!< ADC OFFSET2 bit 6 */
mbed_official 403:91a4bea587f4 1386 #define ADC_OFR2_OFFSET2_7 ((uint32_t)0x00000080) /*!< ADC OFFSET2 bit 7 */
mbed_official 403:91a4bea587f4 1387 #define ADC_OFR2_OFFSET2_8 ((uint32_t)0x00000100) /*!< ADC OFFSET2 bit 8 */
mbed_official 403:91a4bea587f4 1388 #define ADC_OFR2_OFFSET2_9 ((uint32_t)0x00000200) /*!< ADC OFFSET2 bit 9 */
mbed_official 403:91a4bea587f4 1389 #define ADC_OFR2_OFFSET2_10 ((uint32_t)0x00000400) /*!< ADC OFFSET2 bit 10 */
mbed_official 403:91a4bea587f4 1390 #define ADC_OFR2_OFFSET2_11 ((uint32_t)0x00000800) /*!< ADC OFFSET2 bit 11 */
mbed_official 403:91a4bea587f4 1391
mbed_official 403:91a4bea587f4 1392 #define ADC_OFR2_OFFSET2_CH ((uint32_t)0x7C000000) /*!< ADC Channel selection for the data offset 2 */
mbed_official 403:91a4bea587f4 1393 #define ADC_OFR2_OFFSET2_CH_0 ((uint32_t)0x04000000) /*!< ADC OFFSET2_CH bit 0 */
mbed_official 403:91a4bea587f4 1394 #define ADC_OFR2_OFFSET2_CH_1 ((uint32_t)0x08000000) /*!< ADC OFFSET2_CH bit 1 */
mbed_official 403:91a4bea587f4 1395 #define ADC_OFR2_OFFSET2_CH_2 ((uint32_t)0x10000000) /*!< ADC OFFSET2_CH bit 2 */
mbed_official 403:91a4bea587f4 1396 #define ADC_OFR2_OFFSET2_CH_3 ((uint32_t)0x20000000) /*!< ADC OFFSET2_CH bit 3 */
mbed_official 403:91a4bea587f4 1397 #define ADC_OFR2_OFFSET2_CH_4 ((uint32_t)0x40000000) /*!< ADC OFFSET2_CH bit 4 */
mbed_official 403:91a4bea587f4 1398
mbed_official 403:91a4bea587f4 1399 #define ADC_OFR2_OFFSET2_EN ((uint32_t)0x80000000) /*!< ADC offset 2 enable */
mbed_official 403:91a4bea587f4 1400
mbed_official 403:91a4bea587f4 1401 /******************** Bit definition for ADC_OFR3 register ********************/
mbed_official 403:91a4bea587f4 1402 #define ADC_OFR3_OFFSET3 ((uint32_t)0x00000FFF) /*!< ADC data offset 3 for channel programmed into bits OFFSET3_CH[4:0] */
mbed_official 403:91a4bea587f4 1403 #define ADC_OFR3_OFFSET3_0 ((uint32_t)0x00000001) /*!< ADC OFFSET3 bit 0 */
mbed_official 403:91a4bea587f4 1404 #define ADC_OFR3_OFFSET3_1 ((uint32_t)0x00000002) /*!< ADC OFFSET3 bit 1 */
mbed_official 403:91a4bea587f4 1405 #define ADC_OFR3_OFFSET3_2 ((uint32_t)0x00000004) /*!< ADC OFFSET3 bit 2 */
mbed_official 403:91a4bea587f4 1406 #define ADC_OFR3_OFFSET3_3 ((uint32_t)0x00000008) /*!< ADC OFFSET3 bit 3 */
mbed_official 403:91a4bea587f4 1407 #define ADC_OFR3_OFFSET3_4 ((uint32_t)0x00000010) /*!< ADC OFFSET3 bit 4 */
mbed_official 403:91a4bea587f4 1408 #define ADC_OFR3_OFFSET3_5 ((uint32_t)0x00000020) /*!< ADC OFFSET3 bit 5 */
mbed_official 403:91a4bea587f4 1409 #define ADC_OFR3_OFFSET3_6 ((uint32_t)0x00000040) /*!< ADC OFFSET3 bit 6 */
mbed_official 403:91a4bea587f4 1410 #define ADC_OFR3_OFFSET3_7 ((uint32_t)0x00000080) /*!< ADC OFFSET3 bit 7 */
mbed_official 403:91a4bea587f4 1411 #define ADC_OFR3_OFFSET3_8 ((uint32_t)0x00000100) /*!< ADC OFFSET3 bit 8 */
mbed_official 403:91a4bea587f4 1412 #define ADC_OFR3_OFFSET3_9 ((uint32_t)0x00000200) /*!< ADC OFFSET3 bit 9 */
mbed_official 403:91a4bea587f4 1413 #define ADC_OFR3_OFFSET3_10 ((uint32_t)0x00000400) /*!< ADC OFFSET3 bit 10 */
mbed_official 403:91a4bea587f4 1414 #define ADC_OFR3_OFFSET3_11 ((uint32_t)0x00000800) /*!< ADC OFFSET3 bit 11 */
mbed_official 403:91a4bea587f4 1415
mbed_official 403:91a4bea587f4 1416 #define ADC_OFR3_OFFSET3_CH ((uint32_t)0x7C000000) /*!< ADC Channel selection for the data offset 3 */
mbed_official 403:91a4bea587f4 1417 #define ADC_OFR3_OFFSET3_CH_0 ((uint32_t)0x04000000) /*!< ADC OFFSET3_CH bit 0 */
mbed_official 403:91a4bea587f4 1418 #define ADC_OFR3_OFFSET3_CH_1 ((uint32_t)0x08000000) /*!< ADC OFFSET3_CH bit 1 */
mbed_official 403:91a4bea587f4 1419 #define ADC_OFR3_OFFSET3_CH_2 ((uint32_t)0x10000000) /*!< ADC OFFSET3_CH bit 2 */
mbed_official 403:91a4bea587f4 1420 #define ADC_OFR3_OFFSET3_CH_3 ((uint32_t)0x20000000) /*!< ADC OFFSET3_CH bit 3 */
mbed_official 403:91a4bea587f4 1421 #define ADC_OFR3_OFFSET3_CH_4 ((uint32_t)0x40000000) /*!< ADC OFFSET3_CH bit 4 */
mbed_official 403:91a4bea587f4 1422
mbed_official 403:91a4bea587f4 1423 #define ADC_OFR3_OFFSET3_EN ((uint32_t)0x80000000) /*!< ADC offset 3 enable */
mbed_official 403:91a4bea587f4 1424
mbed_official 403:91a4bea587f4 1425 /******************** Bit definition for ADC_OFR4 register ********************/
mbed_official 403:91a4bea587f4 1426 #define ADC_OFR4_OFFSET4 ((uint32_t)0x00000FFF) /*!< ADC data offset 4 for channel programmed into bits OFFSET4_CH[4:0] */
mbed_official 403:91a4bea587f4 1427 #define ADC_OFR4_OFFSET4_0 ((uint32_t)0x00000001) /*!< ADC OFFSET4 bit 0 */
mbed_official 403:91a4bea587f4 1428 #define ADC_OFR4_OFFSET4_1 ((uint32_t)0x00000002) /*!< ADC OFFSET4 bit 1 */
mbed_official 403:91a4bea587f4 1429 #define ADC_OFR4_OFFSET4_2 ((uint32_t)0x00000004) /*!< ADC OFFSET4 bit 2 */
mbed_official 403:91a4bea587f4 1430 #define ADC_OFR4_OFFSET4_3 ((uint32_t)0x00000008) /*!< ADC OFFSET4 bit 3 */
mbed_official 403:91a4bea587f4 1431 #define ADC_OFR4_OFFSET4_4 ((uint32_t)0x00000010) /*!< ADC OFFSET4 bit 4 */
mbed_official 403:91a4bea587f4 1432 #define ADC_OFR4_OFFSET4_5 ((uint32_t)0x00000020) /*!< ADC OFFSET4 bit 5 */
mbed_official 403:91a4bea587f4 1433 #define ADC_OFR4_OFFSET4_6 ((uint32_t)0x00000040) /*!< ADC OFFSET4 bit 6 */
mbed_official 403:91a4bea587f4 1434 #define ADC_OFR4_OFFSET4_7 ((uint32_t)0x00000080) /*!< ADC OFFSET4 bit 7 */
mbed_official 403:91a4bea587f4 1435 #define ADC_OFR4_OFFSET4_8 ((uint32_t)0x00000100) /*!< ADC OFFSET4 bit 8 */
mbed_official 403:91a4bea587f4 1436 #define ADC_OFR4_OFFSET4_9 ((uint32_t)0x00000200) /*!< ADC OFFSET4 bit 9 */
mbed_official 403:91a4bea587f4 1437 #define ADC_OFR4_OFFSET4_10 ((uint32_t)0x00000400) /*!< ADC OFFSET4 bit 10 */
mbed_official 403:91a4bea587f4 1438 #define ADC_OFR4_OFFSET4_11 ((uint32_t)0x00000800) /*!< ADC OFFSET4 bit 11 */
mbed_official 403:91a4bea587f4 1439
mbed_official 403:91a4bea587f4 1440 #define ADC_OFR4_OFFSET4_CH ((uint32_t)0x7C000000) /*!< ADC Channel selection for the data offset 4 */
mbed_official 403:91a4bea587f4 1441 #define ADC_OFR4_OFFSET4_CH_0 ((uint32_t)0x04000000) /*!< ADC OFFSET4_CH bit 0 */
mbed_official 403:91a4bea587f4 1442 #define ADC_OFR4_OFFSET4_CH_1 ((uint32_t)0x08000000) /*!< ADC OFFSET4_CH bit 1 */
mbed_official 403:91a4bea587f4 1443 #define ADC_OFR4_OFFSET4_CH_2 ((uint32_t)0x10000000) /*!< ADC OFFSET4_CH bit 2 */
mbed_official 403:91a4bea587f4 1444 #define ADC_OFR4_OFFSET4_CH_3 ((uint32_t)0x20000000) /*!< ADC OFFSET4_CH bit 3 */
mbed_official 403:91a4bea587f4 1445 #define ADC_OFR4_OFFSET4_CH_4 ((uint32_t)0x40000000) /*!< ADC OFFSET4_CH bit 4 */
mbed_official 403:91a4bea587f4 1446
mbed_official 403:91a4bea587f4 1447 #define ADC_OFR4_OFFSET4_EN ((uint32_t)0x80000000) /*!< ADC offset 4 enable */
mbed_official 403:91a4bea587f4 1448
mbed_official 403:91a4bea587f4 1449 /******************** Bit definition for ADC_JDR1 register ********************/
mbed_official 403:91a4bea587f4 1450 #define ADC_JDR1_JDATA ((uint32_t)0x0000FFFF) /*!< ADC Injected DATA */
mbed_official 403:91a4bea587f4 1451 #define ADC_JDR1_JDATA_0 ((uint32_t)0x00000001) /*!< ADC JDATA bit 0 */
mbed_official 403:91a4bea587f4 1452 #define ADC_JDR1_JDATA_1 ((uint32_t)0x00000002) /*!< ADC JDATA bit 1 */
mbed_official 403:91a4bea587f4 1453 #define ADC_JDR1_JDATA_2 ((uint32_t)0x00000004) /*!< ADC JDATA bit 2 */
mbed_official 403:91a4bea587f4 1454 #define ADC_JDR1_JDATA_3 ((uint32_t)0x00000008) /*!< ADC JDATA bit 3 */
mbed_official 403:91a4bea587f4 1455 #define ADC_JDR1_JDATA_4 ((uint32_t)0x00000010) /*!< ADC JDATA bit 4 */
mbed_official 403:91a4bea587f4 1456 #define ADC_JDR1_JDATA_5 ((uint32_t)0x00000020) /*!< ADC JDATA bit 5 */
mbed_official 403:91a4bea587f4 1457 #define ADC_JDR1_JDATA_6 ((uint32_t)0x00000040) /*!< ADC JDATA bit 6 */
mbed_official 403:91a4bea587f4 1458 #define ADC_JDR1_JDATA_7 ((uint32_t)0x00000080) /*!< ADC JDATA bit 7 */
mbed_official 403:91a4bea587f4 1459 #define ADC_JDR1_JDATA_8 ((uint32_t)0x00000100) /*!< ADC JDATA bit 8 */
mbed_official 403:91a4bea587f4 1460 #define ADC_JDR1_JDATA_9 ((uint32_t)0x00000200) /*!< ADC JDATA bit 9 */
mbed_official 403:91a4bea587f4 1461 #define ADC_JDR1_JDATA_10 ((uint32_t)0x00000400) /*!< ADC JDATA bit 10 */
mbed_official 403:91a4bea587f4 1462 #define ADC_JDR1_JDATA_11 ((uint32_t)0x00000800) /*!< ADC JDATA bit 11 */
mbed_official 403:91a4bea587f4 1463 #define ADC_JDR1_JDATA_12 ((uint32_t)0x00001000) /*!< ADC JDATA bit 12 */
mbed_official 403:91a4bea587f4 1464 #define ADC_JDR1_JDATA_13 ((uint32_t)0x00002000) /*!< ADC JDATA bit 13 */
mbed_official 403:91a4bea587f4 1465 #define ADC_JDR1_JDATA_14 ((uint32_t)0x00004000) /*!< ADC JDATA bit 14 */
mbed_official 403:91a4bea587f4 1466 #define ADC_JDR1_JDATA_15 ((uint32_t)0x00008000) /*!< ADC JDATA bit 15 */
mbed_official 403:91a4bea587f4 1467
mbed_official 403:91a4bea587f4 1468 /******************** Bit definition for ADC_JDR2 register ********************/
mbed_official 403:91a4bea587f4 1469 #define ADC_JDR2_JDATA ((uint32_t)0x0000FFFF) /*!< ADC Injected DATA */
mbed_official 403:91a4bea587f4 1470 #define ADC_JDR2_JDATA_0 ((uint32_t)0x00000001) /*!< ADC JDATA bit 0 */
mbed_official 403:91a4bea587f4 1471 #define ADC_JDR2_JDATA_1 ((uint32_t)0x00000002) /*!< ADC JDATA bit 1 */
mbed_official 403:91a4bea587f4 1472 #define ADC_JDR2_JDATA_2 ((uint32_t)0x00000004) /*!< ADC JDATA bit 2 */
mbed_official 403:91a4bea587f4 1473 #define ADC_JDR2_JDATA_3 ((uint32_t)0x00000008) /*!< ADC JDATA bit 3 */
mbed_official 403:91a4bea587f4 1474 #define ADC_JDR2_JDATA_4 ((uint32_t)0x00000010) /*!< ADC JDATA bit 4 */
mbed_official 403:91a4bea587f4 1475 #define ADC_JDR2_JDATA_5 ((uint32_t)0x00000020) /*!< ADC JDATA bit 5 */
mbed_official 403:91a4bea587f4 1476 #define ADC_JDR2_JDATA_6 ((uint32_t)0x00000040) /*!< ADC JDATA bit 6 */
mbed_official 403:91a4bea587f4 1477 #define ADC_JDR2_JDATA_7 ((uint32_t)0x00000080) /*!< ADC JDATA bit 7 */
mbed_official 403:91a4bea587f4 1478 #define ADC_JDR2_JDATA_8 ((uint32_t)0x00000100) /*!< ADC JDATA bit 8 */
mbed_official 403:91a4bea587f4 1479 #define ADC_JDR2_JDATA_9 ((uint32_t)0x00000200) /*!< ADC JDATA bit 9 */
mbed_official 403:91a4bea587f4 1480 #define ADC_JDR2_JDATA_10 ((uint32_t)0x00000400) /*!< ADC JDATA bit 10 */
mbed_official 403:91a4bea587f4 1481 #define ADC_JDR2_JDATA_11 ((uint32_t)0x00000800) /*!< ADC JDATA bit 11 */
mbed_official 403:91a4bea587f4 1482 #define ADC_JDR2_JDATA_12 ((uint32_t)0x00001000) /*!< ADC JDATA bit 12 */
mbed_official 403:91a4bea587f4 1483 #define ADC_JDR2_JDATA_13 ((uint32_t)0x00002000) /*!< ADC JDATA bit 13 */
mbed_official 403:91a4bea587f4 1484 #define ADC_JDR2_JDATA_14 ((uint32_t)0x00004000) /*!< ADC JDATA bit 14 */
mbed_official 403:91a4bea587f4 1485 #define ADC_JDR2_JDATA_15 ((uint32_t)0x00008000) /*!< ADC JDATA bit 15 */
mbed_official 403:91a4bea587f4 1486
mbed_official 403:91a4bea587f4 1487 /******************** Bit definition for ADC_JDR3 register ********************/
mbed_official 403:91a4bea587f4 1488 #define ADC_JDR3_JDATA ((uint32_t)0x0000FFFF) /*!< ADC Injected DATA */
mbed_official 403:91a4bea587f4 1489 #define ADC_JDR3_JDATA_0 ((uint32_t)0x00000001) /*!< ADC JDATA bit 0 */
mbed_official 403:91a4bea587f4 1490 #define ADC_JDR3_JDATA_1 ((uint32_t)0x00000002) /*!< ADC JDATA bit 1 */
mbed_official 403:91a4bea587f4 1491 #define ADC_JDR3_JDATA_2 ((uint32_t)0x00000004) /*!< ADC JDATA bit 2 */
mbed_official 403:91a4bea587f4 1492 #define ADC_JDR3_JDATA_3 ((uint32_t)0x00000008) /*!< ADC JDATA bit 3 */
mbed_official 403:91a4bea587f4 1493 #define ADC_JDR3_JDATA_4 ((uint32_t)0x00000010) /*!< ADC JDATA bit 4 */
mbed_official 403:91a4bea587f4 1494 #define ADC_JDR3_JDATA_5 ((uint32_t)0x00000020) /*!< ADC JDATA bit 5 */
mbed_official 403:91a4bea587f4 1495 #define ADC_JDR3_JDATA_6 ((uint32_t)0x00000040) /*!< ADC JDATA bit 6 */
mbed_official 403:91a4bea587f4 1496 #define ADC_JDR3_JDATA_7 ((uint32_t)0x00000080) /*!< ADC JDATA bit 7 */
mbed_official 403:91a4bea587f4 1497 #define ADC_JDR3_JDATA_8 ((uint32_t)0x00000100) /*!< ADC JDATA bit 8 */
mbed_official 403:91a4bea587f4 1498 #define ADC_JDR3_JDATA_9 ((uint32_t)0x00000200) /*!< ADC JDATA bit 9 */
mbed_official 403:91a4bea587f4 1499 #define ADC_JDR3_JDATA_10 ((uint32_t)0x00000400) /*!< ADC JDATA bit 10 */
mbed_official 403:91a4bea587f4 1500 #define ADC_JDR3_JDATA_11 ((uint32_t)0x00000800) /*!< ADC JDATA bit 11 */
mbed_official 403:91a4bea587f4 1501 #define ADC_JDR3_JDATA_12 ((uint32_t)0x00001000) /*!< ADC JDATA bit 12 */
mbed_official 403:91a4bea587f4 1502 #define ADC_JDR3_JDATA_13 ((uint32_t)0x00002000) /*!< ADC JDATA bit 13 */
mbed_official 403:91a4bea587f4 1503 #define ADC_JDR3_JDATA_14 ((uint32_t)0x00004000) /*!< ADC JDATA bit 14 */
mbed_official 403:91a4bea587f4 1504 #define ADC_JDR3_JDATA_15 ((uint32_t)0x00008000) /*!< ADC JDATA bit 15 */
mbed_official 403:91a4bea587f4 1505
mbed_official 403:91a4bea587f4 1506 /******************** Bit definition for ADC_JDR4 register ********************/
mbed_official 403:91a4bea587f4 1507 #define ADC_JDR4_JDATA ((uint32_t)0x0000FFFF) /*!< ADC Injected DATA */
mbed_official 403:91a4bea587f4 1508 #define ADC_JDR4_JDATA_0 ((uint32_t)0x00000001) /*!< ADC JDATA bit 0 */
mbed_official 403:91a4bea587f4 1509 #define ADC_JDR4_JDATA_1 ((uint32_t)0x00000002) /*!< ADC JDATA bit 1 */
mbed_official 403:91a4bea587f4 1510 #define ADC_JDR4_JDATA_2 ((uint32_t)0x00000004) /*!< ADC JDATA bit 2 */
mbed_official 403:91a4bea587f4 1511 #define ADC_JDR4_JDATA_3 ((uint32_t)0x00000008) /*!< ADC JDATA bit 3 */
mbed_official 403:91a4bea587f4 1512 #define ADC_JDR4_JDATA_4 ((uint32_t)0x00000010) /*!< ADC JDATA bit 4 */
mbed_official 403:91a4bea587f4 1513 #define ADC_JDR4_JDATA_5 ((uint32_t)0x00000020) /*!< ADC JDATA bit 5 */
mbed_official 403:91a4bea587f4 1514 #define ADC_JDR4_JDATA_6 ((uint32_t)0x00000040) /*!< ADC JDATA bit 6 */
mbed_official 403:91a4bea587f4 1515 #define ADC_JDR4_JDATA_7 ((uint32_t)0x00000080) /*!< ADC JDATA bit 7 */
mbed_official 403:91a4bea587f4 1516 #define ADC_JDR4_JDATA_8 ((uint32_t)0x00000100) /*!< ADC JDATA bit 8 */
mbed_official 403:91a4bea587f4 1517 #define ADC_JDR4_JDATA_9 ((uint32_t)0x00000200) /*!< ADC JDATA bit 9 */
mbed_official 403:91a4bea587f4 1518 #define ADC_JDR4_JDATA_10 ((uint32_t)0x00000400) /*!< ADC JDATA bit 10 */
mbed_official 403:91a4bea587f4 1519 #define ADC_JDR4_JDATA_11 ((uint32_t)0x00000800) /*!< ADC JDATA bit 11 */
mbed_official 403:91a4bea587f4 1520 #define ADC_JDR4_JDATA_12 ((uint32_t)0x00001000) /*!< ADC JDATA bit 12 */
mbed_official 403:91a4bea587f4 1521 #define ADC_JDR4_JDATA_13 ((uint32_t)0x00002000) /*!< ADC JDATA bit 13 */
mbed_official 403:91a4bea587f4 1522 #define ADC_JDR4_JDATA_14 ((uint32_t)0x00004000) /*!< ADC JDATA bit 14 */
mbed_official 403:91a4bea587f4 1523 #define ADC_JDR4_JDATA_15 ((uint32_t)0x00008000) /*!< ADC JDATA bit 15 */
mbed_official 403:91a4bea587f4 1524
mbed_official 403:91a4bea587f4 1525 /******************** Bit definition for ADC_AWD2CR register ********************/
mbed_official 403:91a4bea587f4 1526 #define ADC_AWD2CR_AWD2CH ((uint32_t)0x0007FFFE) /*!< ADC Analog watchdog 2 channel selection */
mbed_official 403:91a4bea587f4 1527 #define ADC_AWD2CR_AWD2CH_0 ((uint32_t)0x00000002) /*!< ADC AWD2CH bit 0 */
mbed_official 403:91a4bea587f4 1528 #define ADC_AWD2CR_AWD2CH_1 ((uint32_t)0x00000004) /*!< ADC AWD2CH bit 1 */
mbed_official 403:91a4bea587f4 1529 #define ADC_AWD2CR_AWD2CH_2 ((uint32_t)0x00000008) /*!< ADC AWD2CH bit 2 */
mbed_official 403:91a4bea587f4 1530 #define ADC_AWD2CR_AWD2CH_3 ((uint32_t)0x00000010) /*!< ADC AWD2CH bit 3 */
mbed_official 403:91a4bea587f4 1531 #define ADC_AWD2CR_AWD2CH_4 ((uint32_t)0x00000020) /*!< ADC AWD2CH bit 4 */
mbed_official 403:91a4bea587f4 1532 #define ADC_AWD2CR_AWD2CH_5 ((uint32_t)0x00000040) /*!< ADC AWD2CH bit 5 */
mbed_official 403:91a4bea587f4 1533 #define ADC_AWD2CR_AWD2CH_6 ((uint32_t)0x00000080) /*!< ADC AWD2CH bit 6 */
mbed_official 403:91a4bea587f4 1534 #define ADC_AWD2CR_AWD2CH_7 ((uint32_t)0x00000100) /*!< ADC AWD2CH bit 7 */
mbed_official 403:91a4bea587f4 1535 #define ADC_AWD2CR_AWD2CH_8 ((uint32_t)0x00000200) /*!< ADC AWD2CH bit 8 */
mbed_official 403:91a4bea587f4 1536 #define ADC_AWD2CR_AWD2CH_9 ((uint32_t)0x00000400) /*!< ADC AWD2CH bit 9 */
mbed_official 403:91a4bea587f4 1537 #define ADC_AWD2CR_AWD2CH_10 ((uint32_t)0x00000800) /*!< ADC AWD2CH bit 10 */
mbed_official 403:91a4bea587f4 1538 #define ADC_AWD2CR_AWD2CH_11 ((uint32_t)0x00001000) /*!< ADC AWD2CH bit 11 */
mbed_official 403:91a4bea587f4 1539 #define ADC_AWD2CR_AWD2CH_12 ((uint32_t)0x00002000) /*!< ADC AWD2CH bit 12 */
mbed_official 403:91a4bea587f4 1540 #define ADC_AWD2CR_AWD2CH_13 ((uint32_t)0x00004000) /*!< ADC AWD2CH bit 13 */
mbed_official 403:91a4bea587f4 1541 #define ADC_AWD2CR_AWD2CH_14 ((uint32_t)0x00008000) /*!< ADC AWD2CH bit 14 */
mbed_official 403:91a4bea587f4 1542 #define ADC_AWD2CR_AWD2CH_15 ((uint32_t)0x00010000) /*!< ADC AWD2CH bit 15 */
mbed_official 403:91a4bea587f4 1543 #define ADC_AWD2CR_AWD2CH_16 ((uint32_t)0x00020000) /*!< ADC AWD2CH bit 16 */
mbed_official 403:91a4bea587f4 1544 #define ADC_AWD2CR_AWD2CH_17 ((uint32_t)0x00030000) /*!< ADC AWD2CH bit 17 */
mbed_official 403:91a4bea587f4 1545
mbed_official 403:91a4bea587f4 1546 /******************** Bit definition for ADC_AWD3CR register ********************/
mbed_official 403:91a4bea587f4 1547 #define ADC_AWD3CR_AWD3CH ((uint32_t)0x0007FFFE) /*!< ADC Analog watchdog 2 channel selection */
mbed_official 403:91a4bea587f4 1548 #define ADC_AWD3CR_AWD3CH_0 ((uint32_t)0x00000002) /*!< ADC AWD3CH bit 0 */
mbed_official 403:91a4bea587f4 1549 #define ADC_AWD3CR_AWD3CH_1 ((uint32_t)0x00000004) /*!< ADC AWD3CH bit 1 */
mbed_official 403:91a4bea587f4 1550 #define ADC_AWD3CR_AWD3CH_2 ((uint32_t)0x00000008) /*!< ADC AWD3CH bit 2 */
mbed_official 403:91a4bea587f4 1551 #define ADC_AWD3CR_AWD3CH_3 ((uint32_t)0x00000010) /*!< ADC AWD3CH bit 3 */
mbed_official 403:91a4bea587f4 1552 #define ADC_AWD3CR_AWD3CH_4 ((uint32_t)0x00000020) /*!< ADC AWD3CH bit 4 */
mbed_official 403:91a4bea587f4 1553 #define ADC_AWD3CR_AWD3CH_5 ((uint32_t)0x00000040) /*!< ADC AWD3CH bit 5 */
mbed_official 403:91a4bea587f4 1554 #define ADC_AWD3CR_AWD3CH_6 ((uint32_t)0x00000080) /*!< ADC AWD3CH bit 6 */
mbed_official 403:91a4bea587f4 1555 #define ADC_AWD3CR_AWD3CH_7 ((uint32_t)0x00000100) /*!< ADC AWD3CH bit 7 */
mbed_official 403:91a4bea587f4 1556 #define ADC_AWD3CR_AWD3CH_8 ((uint32_t)0x00000200) /*!< ADC AWD3CH bit 8 */
mbed_official 403:91a4bea587f4 1557 #define ADC_AWD3CR_AWD3CH_9 ((uint32_t)0x00000400) /*!< ADC AWD3CH bit 9 */
mbed_official 403:91a4bea587f4 1558 #define ADC_AWD3CR_AWD3CH_10 ((uint32_t)0x00000800) /*!< ADC AWD3CH bit 10 */
mbed_official 403:91a4bea587f4 1559 #define ADC_AWD3CR_AWD3CH_11 ((uint32_t)0x00001000) /*!< ADC AWD3CH bit 11 */
mbed_official 403:91a4bea587f4 1560 #define ADC_AWD3CR_AWD3CH_12 ((uint32_t)0x00002000) /*!< ADC AWD3CH bit 12 */
mbed_official 403:91a4bea587f4 1561 #define ADC_AWD3CR_AWD3CH_13 ((uint32_t)0x00004000) /*!< ADC AWD3CH bit 13 */
mbed_official 403:91a4bea587f4 1562 #define ADC_AWD3CR_AWD3CH_14 ((uint32_t)0x00008000) /*!< ADC AWD3CH bit 14 */
mbed_official 403:91a4bea587f4 1563 #define ADC_AWD3CR_AWD3CH_15 ((uint32_t)0x00010000) /*!< ADC AWD3CH bit 15 */
mbed_official 403:91a4bea587f4 1564 #define ADC_AWD3CR_AWD3CH_16 ((uint32_t)0x00020000) /*!< ADC AWD3CH bit 16 */
mbed_official 403:91a4bea587f4 1565 #define ADC_AWD3CR_AWD3CH_17 ((uint32_t)0x00030000) /*!< ADC AWD3CH bit 17 */
mbed_official 403:91a4bea587f4 1566
mbed_official 403:91a4bea587f4 1567 /******************** Bit definition for ADC_DIFSEL register ********************/
mbed_official 403:91a4bea587f4 1568 #define ADC_DIFSEL_DIFSEL ((uint32_t)0x0007FFFE) /*!< ADC differential modes for channels 1 to 18 */
mbed_official 403:91a4bea587f4 1569 #define ADC_DIFSEL_DIFSEL_0 ((uint32_t)0x00000002) /*!< ADC DIFSEL bit 0 */
mbed_official 403:91a4bea587f4 1570 #define ADC_DIFSEL_DIFSEL_1 ((uint32_t)0x00000004) /*!< ADC DIFSEL bit 1 */
mbed_official 403:91a4bea587f4 1571 #define ADC_DIFSEL_DIFSEL_2 ((uint32_t)0x00000008) /*!< ADC DIFSEL bit 2 */
mbed_official 403:91a4bea587f4 1572 #define ADC_DIFSEL_DIFSEL_3 ((uint32_t)0x00000010) /*!< ADC DIFSEL bit 3 */
mbed_official 403:91a4bea587f4 1573 #define ADC_DIFSEL_DIFSEL_4 ((uint32_t)0x00000020) /*!< ADC DIFSEL bit 4 */
mbed_official 403:91a4bea587f4 1574 #define ADC_DIFSEL_DIFSEL_5 ((uint32_t)0x00000040) /*!< ADC DIFSEL bit 5 */
mbed_official 403:91a4bea587f4 1575 #define ADC_DIFSEL_DIFSEL_6 ((uint32_t)0x00000080) /*!< ADC DIFSEL bit 6 */
mbed_official 403:91a4bea587f4 1576 #define ADC_DIFSEL_DIFSEL_7 ((uint32_t)0x00000100) /*!< ADC DIFSEL bit 7 */
mbed_official 403:91a4bea587f4 1577 #define ADC_DIFSEL_DIFSEL_8 ((uint32_t)0x00000200) /*!< ADC DIFSEL bit 8 */
mbed_official 403:91a4bea587f4 1578 #define ADC_DIFSEL_DIFSEL_9 ((uint32_t)0x00000400) /*!< ADC DIFSEL bit 9 */
mbed_official 403:91a4bea587f4 1579 #define ADC_DIFSEL_DIFSEL_10 ((uint32_t)0x00000800) /*!< ADC DIFSEL bit 10 */
mbed_official 403:91a4bea587f4 1580 #define ADC_DIFSEL_DIFSEL_11 ((uint32_t)0x00001000) /*!< ADC DIFSEL bit 11 */
mbed_official 403:91a4bea587f4 1581 #define ADC_DIFSEL_DIFSEL_12 ((uint32_t)0x00002000) /*!< ADC DIFSEL bit 12 */
mbed_official 403:91a4bea587f4 1582 #define ADC_DIFSEL_DIFSEL_13 ((uint32_t)0x00004000) /*!< ADC DIFSEL bit 13 */
mbed_official 403:91a4bea587f4 1583 #define ADC_DIFSEL_DIFSEL_14 ((uint32_t)0x00008000) /*!< ADC DIFSEL bit 14 */
mbed_official 403:91a4bea587f4 1584 #define ADC_DIFSEL_DIFSEL_15 ((uint32_t)0x00010000) /*!< ADC DIFSEL bit 15 */
mbed_official 403:91a4bea587f4 1585 #define ADC_DIFSEL_DIFSEL_16 ((uint32_t)0x00020000) /*!< ADC DIFSEL bit 16 */
mbed_official 403:91a4bea587f4 1586 #define ADC_DIFSEL_DIFSEL_17 ((uint32_t)0x00030000) /*!< ADC DIFSEL bit 17 */
mbed_official 403:91a4bea587f4 1587
mbed_official 403:91a4bea587f4 1588 /******************** Bit definition for ADC_CALFACT register ********************/
mbed_official 403:91a4bea587f4 1589 #define ADC_CALFACT_CALFACT_S ((uint32_t)0x0000007F) /*!< ADC calibration factors in single-ended mode */
mbed_official 403:91a4bea587f4 1590 #define ADC_CALFACT_CALFACT_S_0 ((uint32_t)0x00000001) /*!< ADC CALFACT_S bit 0 */
mbed_official 403:91a4bea587f4 1591 #define ADC_CALFACT_CALFACT_S_1 ((uint32_t)0x00000002) /*!< ADC CALFACT_S bit 1 */
mbed_official 403:91a4bea587f4 1592 #define ADC_CALFACT_CALFACT_S_2 ((uint32_t)0x00000004) /*!< ADC CALFACT_S bit 2 */
mbed_official 403:91a4bea587f4 1593 #define ADC_CALFACT_CALFACT_S_3 ((uint32_t)0x00000008) /*!< ADC CALFACT_S bit 3 */
mbed_official 403:91a4bea587f4 1594 #define ADC_CALFACT_CALFACT_S_4 ((uint32_t)0x00000010) /*!< ADC CALFACT_S bit 4 */
mbed_official 403:91a4bea587f4 1595 #define ADC_CALFACT_CALFACT_S_5 ((uint32_t)0x00000020) /*!< ADC CALFACT_S bit 5 */
mbed_official 403:91a4bea587f4 1596 #define ADC_CALFACT_CALFACT_S_6 ((uint32_t)0x00000040) /*!< ADC CALFACT_S bit 6 */
mbed_official 403:91a4bea587f4 1597 #define ADC_CALFACT_CALFACT_D ((uint32_t)0x007F0000) /*!< ADC calibration factors in differential mode */
mbed_official 403:91a4bea587f4 1598 #define ADC_CALFACT_CALFACT_D_0 ((uint32_t)0x00010000) /*!< ADC CALFACT_D bit 0 */
mbed_official 403:91a4bea587f4 1599 #define ADC_CALFACT_CALFACT_D_1 ((uint32_t)0x00020000) /*!< ADC CALFACT_D bit 1 */
mbed_official 403:91a4bea587f4 1600 #define ADC_CALFACT_CALFACT_D_2 ((uint32_t)0x00040000) /*!< ADC CALFACT_D bit 2 */
mbed_official 403:91a4bea587f4 1601 #define ADC_CALFACT_CALFACT_D_3 ((uint32_t)0x00080000) /*!< ADC CALFACT_D bit 3 */
mbed_official 403:91a4bea587f4 1602 #define ADC_CALFACT_CALFACT_D_4 ((uint32_t)0x00100000) /*!< ADC CALFACT_D bit 4 */
mbed_official 403:91a4bea587f4 1603 #define ADC_CALFACT_CALFACT_D_5 ((uint32_t)0x00200000) /*!< ADC CALFACT_D bit 5 */
mbed_official 403:91a4bea587f4 1604 #define ADC_CALFACT_CALFACT_D_6 ((uint32_t)0x00400000) /*!< ADC CALFACT_D bit 6 */
mbed_official 403:91a4bea587f4 1605
mbed_official 403:91a4bea587f4 1606 /************************* ADC Common registers *****************************/
mbed_official 403:91a4bea587f4 1607 /******************** Bit definition for ADC12_CSR register ********************/
mbed_official 403:91a4bea587f4 1608 #define ADC12_CSR_ADRDY_MST ((uint32_t)0x00000001) /*!< Master ADC ready */
mbed_official 403:91a4bea587f4 1609 #define ADC12_CSR_ADRDY_EOSMP_MST ((uint32_t)0x00000002) /*!< End of sampling phase flag of the master ADC */
mbed_official 403:91a4bea587f4 1610 #define ADC12_CSR_ADRDY_EOC_MST ((uint32_t)0x00000004) /*!< End of regular conversion of the master ADC */
mbed_official 403:91a4bea587f4 1611 #define ADC12_CSR_ADRDY_EOS_MST ((uint32_t)0x00000008) /*!< End of regular sequence flag of the master ADC */
mbed_official 403:91a4bea587f4 1612 #define ADC12_CSR_ADRDY_OVR_MST ((uint32_t)0x00000010) /*!< Overrun flag of the master ADC */
mbed_official 403:91a4bea587f4 1613 #define ADC12_CSR_ADRDY_JEOC_MST ((uint32_t)0x00000020) /*!< End of injected conversion of the master ADC */
mbed_official 403:91a4bea587f4 1614 #define ADC12_CSR_ADRDY_JEOS_MST ((uint32_t)0x00000040) /*!< End of injected sequence flag of the master ADC */
mbed_official 403:91a4bea587f4 1615 #define ADC12_CSR_AWD1_MST ((uint32_t)0x00000080) /*!< Analog watchdog 1 flag of the master ADC */
mbed_official 403:91a4bea587f4 1616 #define ADC12_CSR_AWD2_MST ((uint32_t)0x00000100) /*!< Analog watchdog 2 flag of the master ADC */
mbed_official 403:91a4bea587f4 1617 #define ADC12_CSR_AWD3_MST ((uint32_t)0x00000200) /*!< Analog watchdog 3 flag of the master ADC */
mbed_official 403:91a4bea587f4 1618 #define ADC12_CSR_JQOVF_MST ((uint32_t)0x00000400) /*!< Injected context queue overflow flag of the master ADC */
mbed_official 403:91a4bea587f4 1619 #define ADC12_CSR_ADRDY_SLV ((uint32_t)0x00010000) /*!< Slave ADC ready */
mbed_official 403:91a4bea587f4 1620 #define ADC12_CSR_ADRDY_EOSMP_SLV ((uint32_t)0x00020000) /*!< End of sampling phase flag of the slave ADC */
mbed_official 403:91a4bea587f4 1621 #define ADC12_CSR_ADRDY_EOC_SLV ((uint32_t)0x00040000) /*!< End of regular conversion of the slave ADC */
mbed_official 403:91a4bea587f4 1622 #define ADC12_CSR_ADRDY_EOS_SLV ((uint32_t)0x00080000) /*!< End of regular sequence flag of the slave ADC */
mbed_official 403:91a4bea587f4 1623 #define ADC12_CSR_ADRDY_OVR_SLV ((uint32_t)0x00100000) /*!< Overrun flag of the slave ADC */
mbed_official 403:91a4bea587f4 1624 #define ADC12_CSR_ADRDY_JEOC_SLV ((uint32_t)0x00200000) /*!< End of injected conversion of the slave ADC */
mbed_official 403:91a4bea587f4 1625 #define ADC12_CSR_ADRDY_JEOS_SLV ((uint32_t)0x00400000) /*!< End of injected sequence flag of the slave ADC */
mbed_official 403:91a4bea587f4 1626 #define ADC12_CSR_AWD1_SLV ((uint32_t)0x00800000) /*!< Analog watchdog 1 flag of the slave ADC */
mbed_official 403:91a4bea587f4 1627 #define ADC12_CSR_AWD2_SLV ((uint32_t)0x01000000) /*!< Analog watchdog 2 flag of the slave ADC */
mbed_official 403:91a4bea587f4 1628 #define ADC12_CSR_AWD3_SLV ((uint32_t)0x02000000) /*!< Analog watchdog 3 flag of the slave ADC */
mbed_official 403:91a4bea587f4 1629 #define ADC12_CSR_JQOVF_SLV ((uint32_t)0x04000000) /*!< Injected context queue overflow flag of the slave ADC */
mbed_official 403:91a4bea587f4 1630
mbed_official 403:91a4bea587f4 1631 /******************** Bit definition for ADC34_CSR register ********************/
mbed_official 403:91a4bea587f4 1632 #define ADC34_CSR_ADRDY_MST ((uint32_t)0x00000001) /*!< Master ADC ready */
mbed_official 403:91a4bea587f4 1633 #define ADC34_CSR_ADRDY_EOSMP_MST ((uint32_t)0x00000002) /*!< End of sampling phase flag of the master ADC */
mbed_official 403:91a4bea587f4 1634 #define ADC34_CSR_ADRDY_EOC_MST ((uint32_t)0x00000004) /*!< End of regular conversion of the master ADC */
mbed_official 403:91a4bea587f4 1635 #define ADC34_CSR_ADRDY_EOS_MST ((uint32_t)0x00000008) /*!< End of regular sequence flag of the master ADC */
mbed_official 403:91a4bea587f4 1636 #define ADC34_CSR_ADRDY_OVR_MST ((uint32_t)0x00000010) /*!< Overrun flag of the master ADC */
mbed_official 403:91a4bea587f4 1637 #define ADC34_CSR_ADRDY_JEOC_MST ((uint32_t)0x00000020) /*!< End of injected conversion of the master ADC */
mbed_official 403:91a4bea587f4 1638 #define ADC34_CSR_ADRDY_JEOS_MST ((uint32_t)0x00000040) /*!< End of injected sequence flag of the master ADC */
mbed_official 403:91a4bea587f4 1639 #define ADC34_CSR_AWD1_MST ((uint32_t)0x00000080) /*!< Analog watchdog 1 flag of the master ADC */
mbed_official 403:91a4bea587f4 1640 #define ADC34_CSR_AWD2_MST ((uint32_t)0x00000100) /*!< Analog watchdog 2 flag of the master ADC */
mbed_official 403:91a4bea587f4 1641 #define ADC34_CSR_AWD3_MST ((uint32_t)0x00000200) /*!< Analog watchdog 3 flag of the master ADC */
mbed_official 403:91a4bea587f4 1642 #define ADC34_CSR_JQOVF_MST ((uint32_t)0x00000400) /*!< Injected context queue overflow flag of the master ADC */
mbed_official 403:91a4bea587f4 1643 #define ADC34_CSR_ADRDY_SLV ((uint32_t)0x00010000) /*!< Slave ADC ready */
mbed_official 403:91a4bea587f4 1644 #define ADC34_CSR_ADRDY_EOSMP_SLV ((uint32_t)0x00020000) /*!< End of sampling phase flag of the slave ADC */
mbed_official 403:91a4bea587f4 1645 #define ADC34_CSR_ADRDY_EOC_SLV ((uint32_t)0x00040000) /*!< End of regular conversion of the slave ADC */
mbed_official 403:91a4bea587f4 1646 #define ADC34_CSR_ADRDY_EOS_SLV ((uint32_t)0x00080000) /*!< End of regular sequence flag of the slave ADC */
mbed_official 403:91a4bea587f4 1647 #define ADC12_CSR_ADRDY_OVR_SLV ((uint32_t)0x00100000) /*!< Overrun flag of the slave ADC */
mbed_official 403:91a4bea587f4 1648 #define ADC34_CSR_ADRDY_JEOC_SLV ((uint32_t)0x00200000) /*!< End of injected conversion of the slave ADC */
mbed_official 403:91a4bea587f4 1649 #define ADC34_CSR_ADRDY_JEOS_SLV ((uint32_t)0x00400000) /*!< End of injected sequence flag of the slave ADC */
mbed_official 403:91a4bea587f4 1650 #define ADC34_CSR_AWD1_SLV ((uint32_t)0x00800000) /*!< Analog watchdog 1 flag of the slave ADC */
mbed_official 403:91a4bea587f4 1651 #define ADC34_CSR_AWD2_SLV ((uint32_t)0x01000000) /*!< Analog watchdog 2 flag of the slave ADC */
mbed_official 403:91a4bea587f4 1652 #define ADC34_CSR_AWD3_SLV ((uint32_t)0x02000000) /*!< Analog watchdog 3 flag of the slave ADC */
mbed_official 403:91a4bea587f4 1653 #define ADC34_CSR_JQOVF_SLV ((uint32_t)0x04000000) /*!< Injected context queue overflow flag of the slave ADC */
mbed_official 403:91a4bea587f4 1654
mbed_official 403:91a4bea587f4 1655 /******************** Bit definition for ADC_CCR register ********************/
mbed_official 403:91a4bea587f4 1656 #define ADC12_CCR_MULTI ((uint32_t)0x0000001F) /*!< Multi ADC mode selection */
mbed_official 403:91a4bea587f4 1657 #define ADC12_CCR_MULTI_0 ((uint32_t)0x00000001) /*!< MULTI bit 0 */
mbed_official 403:91a4bea587f4 1658 #define ADC12_CCR_MULTI_1 ((uint32_t)0x00000002) /*!< MULTI bit 1 */
mbed_official 403:91a4bea587f4 1659 #define ADC12_CCR_MULTI_2 ((uint32_t)0x00000004) /*!< MULTI bit 2 */
mbed_official 403:91a4bea587f4 1660 #define ADC12_CCR_MULTI_3 ((uint32_t)0x00000008) /*!< MULTI bit 3 */
mbed_official 403:91a4bea587f4 1661 #define ADC12_CCR_MULTI_4 ((uint32_t)0x00000010) /*!< MULTI bit 4 */
mbed_official 403:91a4bea587f4 1662 #define ADC12_CCR_DELAY ((uint32_t)0x00000F00) /*!< Delay between 2 sampling phases */
mbed_official 403:91a4bea587f4 1663 #define ADC12_CCR_DELAY_0 ((uint32_t)0x00000100) /*!< DELAY bit 0 */
mbed_official 403:91a4bea587f4 1664 #define ADC12_CCR_DELAY_1 ((uint32_t)0x00000200) /*!< DELAY bit 1 */
mbed_official 403:91a4bea587f4 1665 #define ADC12_CCR_DELAY_2 ((uint32_t)0x00000400) /*!< DELAY bit 2 */
mbed_official 403:91a4bea587f4 1666 #define ADC12_CCR_DELAY_3 ((uint32_t)0x00000800) /*!< DELAY bit 3 */
mbed_official 403:91a4bea587f4 1667 #define ADC12_CCR_DMACFG ((uint32_t)0x00002000) /*!< DMA configuration for multi-ADC mode */
mbed_official 403:91a4bea587f4 1668 #define ADC12_CCR_MDMA ((uint32_t)0x0000C000) /*!< DMA mode for multi-ADC mode */
mbed_official 403:91a4bea587f4 1669 #define ADC12_CCR_MDMA_0 ((uint32_t)0x00004000) /*!< MDMA bit 0 */
mbed_official 403:91a4bea587f4 1670 #define ADC12_CCR_MDMA_1 ((uint32_t)0x00008000) /*!< MDMA bit 1 */
mbed_official 403:91a4bea587f4 1671 #define ADC12_CCR_CKMODE ((uint32_t)0x00030000) /*!< ADC clock mode */
mbed_official 403:91a4bea587f4 1672 #define ADC12_CCR_CKMODE_0 ((uint32_t)0x00010000) /*!< CKMODE bit 0 */
mbed_official 403:91a4bea587f4 1673 #define ADC12_CCR_CKMODE_1 ((uint32_t)0x00020000) /*!< CKMODE bit 1 */
mbed_official 403:91a4bea587f4 1674 #define ADC12_CCR_VREFEN ((uint32_t)0x00400000) /*!< VREFINT enable */
mbed_official 403:91a4bea587f4 1675 #define ADC12_CCR_TSEN ((uint32_t)0x00800000) /*!< Temperature sensor enable */
mbed_official 403:91a4bea587f4 1676 #define ADC12_CCR_VBATEN ((uint32_t)0x01000000) /*!< VBAT enable */
mbed_official 403:91a4bea587f4 1677
mbed_official 403:91a4bea587f4 1678 /******************** Bit definition for ADC_CCR register ********************/
mbed_official 403:91a4bea587f4 1679 #define ADC34_CCR_MULTI ((uint32_t)0x0000001F) /*!< Multi ADC mode selection */
mbed_official 403:91a4bea587f4 1680 #define ADC34_CCR_MULTI_0 ((uint32_t)0x00000001) /*!< MULTI bit 0 */
mbed_official 403:91a4bea587f4 1681 #define ADC34_CCR_MULTI_1 ((uint32_t)0x00000002) /*!< MULTI bit 1 */
mbed_official 403:91a4bea587f4 1682 #define ADC34_CCR_MULTI_2 ((uint32_t)0x00000004) /*!< MULTI bit 2 */
mbed_official 403:91a4bea587f4 1683 #define ADC34_CCR_MULTI_3 ((uint32_t)0x00000008) /*!< MULTI bit 3 */
mbed_official 403:91a4bea587f4 1684 #define ADC34_CCR_MULTI_4 ((uint32_t)0x00000010) /*!< MULTI bit 4 */
mbed_official 403:91a4bea587f4 1685
mbed_official 403:91a4bea587f4 1686 #define ADC34_CCR_DELAY ((uint32_t)0x00000F00) /*!< Delay between 2 sampling phases */
mbed_official 403:91a4bea587f4 1687 #define ADC34_CCR_DELAY_0 ((uint32_t)0x00000100) /*!< DELAY bit 0 */
mbed_official 403:91a4bea587f4 1688 #define ADC34_CCR_DELAY_1 ((uint32_t)0x00000200) /*!< DELAY bit 1 */
mbed_official 403:91a4bea587f4 1689 #define ADC34_CCR_DELAY_2 ((uint32_t)0x00000400) /*!< DELAY bit 2 */
mbed_official 403:91a4bea587f4 1690 #define ADC34_CCR_DELAY_3 ((uint32_t)0x00000800) /*!< DELAY bit 3 */
mbed_official 403:91a4bea587f4 1691
mbed_official 403:91a4bea587f4 1692 #define ADC34_CCR_DMACFG ((uint32_t)0x00002000) /*!< DMA configuration for multi-ADC mode */
mbed_official 403:91a4bea587f4 1693 #define ADC34_CCR_MDMA ((uint32_t)0x0000C000) /*!< DMA mode for multi-ADC mode */
mbed_official 403:91a4bea587f4 1694 #define ADC34_CCR_MDMA_0 ((uint32_t)0x00004000) /*!< MDMA bit 0 */
mbed_official 403:91a4bea587f4 1695 #define ADC34_CCR_MDMA_1 ((uint32_t)0x00008000) /*!< MDMA bit 1 */
mbed_official 403:91a4bea587f4 1696
mbed_official 403:91a4bea587f4 1697 #define ADC34_CCR_CKMODE ((uint32_t)0x00030000) /*!< ADC clock mode */
mbed_official 403:91a4bea587f4 1698 #define ADC34_CCR_CKMODE_0 ((uint32_t)0x00010000) /*!< CKMODE bit 0 */
mbed_official 403:91a4bea587f4 1699 #define ADC34_CCR_CKMODE_1 ((uint32_t)0x00020000) /*!< CKMODE bit 1 */
mbed_official 403:91a4bea587f4 1700
mbed_official 403:91a4bea587f4 1701 #define ADC34_CCR_VREFEN ((uint32_t)0x00400000) /*!< VREFINT enable */
mbed_official 403:91a4bea587f4 1702 #define ADC34_CCR_TSEN ((uint32_t)0x00800000) /*!< Temperature sensor enable */
mbed_official 403:91a4bea587f4 1703 #define ADC34_CCR_VBATEN ((uint32_t)0x01000000) /*!< VBAT enable */
mbed_official 403:91a4bea587f4 1704
mbed_official 403:91a4bea587f4 1705 /******************** Bit definition for ADC_CDR register ********************/
mbed_official 403:91a4bea587f4 1706 #define ADC12_CDR_RDATA_MST ((uint32_t)0x0000FFFF) /*!< Regular Data of the master ADC */
mbed_official 403:91a4bea587f4 1707 #define ADC12_CDR_RDATA_MST_0 ((uint32_t)0x00000001) /*!< RDATA_MST bit 0 */
mbed_official 403:91a4bea587f4 1708 #define ADC12_CDR_RDATA_MST_1 ((uint32_t)0x00000002) /*!< RDATA_MST bit 1 */
mbed_official 403:91a4bea587f4 1709 #define ADC12_CDR_RDATA_MST_2 ((uint32_t)0x00000004) /*!< RDATA_MST bit 2 */
mbed_official 403:91a4bea587f4 1710 #define ADC12_CDR_RDATA_MST_3 ((uint32_t)0x00000008) /*!< RDATA_MST bit 3 */
mbed_official 403:91a4bea587f4 1711 #define ADC12_CDR_RDATA_MST_4 ((uint32_t)0x00000010) /*!< RDATA_MST bit 4 */
mbed_official 403:91a4bea587f4 1712 #define ADC12_CDR_RDATA_MST_5 ((uint32_t)0x00000020) /*!< RDATA_MST bit 5 */
mbed_official 403:91a4bea587f4 1713 #define ADC12_CDR_RDATA_MST_6 ((uint32_t)0x00000040) /*!< RDATA_MST bit 6 */
mbed_official 403:91a4bea587f4 1714 #define ADC12_CDR_RDATA_MST_7 ((uint32_t)0x00000080) /*!< RDATA_MST bit 7 */
mbed_official 403:91a4bea587f4 1715 #define ADC12_CDR_RDATA_MST_8 ((uint32_t)0x00000100) /*!< RDATA_MST bit 8 */
mbed_official 403:91a4bea587f4 1716 #define ADC12_CDR_RDATA_MST_9 ((uint32_t)0x00000200) /*!< RDATA_MST bit 9 */
mbed_official 403:91a4bea587f4 1717 #define ADC12_CDR_RDATA_MST_10 ((uint32_t)0x00000400) /*!< RDATA_MST bit 10 */
mbed_official 403:91a4bea587f4 1718 #define ADC12_CDR_RDATA_MST_11 ((uint32_t)0x00000800) /*!< RDATA_MST bit 11 */
mbed_official 403:91a4bea587f4 1719 #define ADC12_CDR_RDATA_MST_12 ((uint32_t)0x00001000) /*!< RDATA_MST bit 12 */
mbed_official 403:91a4bea587f4 1720 #define ADC12_CDR_RDATA_MST_13 ((uint32_t)0x00002000) /*!< RDATA_MST bit 13 */
mbed_official 403:91a4bea587f4 1721 #define ADC12_CDR_RDATA_MST_14 ((uint32_t)0x00004000) /*!< RDATA_MST bit 14 */
mbed_official 403:91a4bea587f4 1722 #define ADC12_CDR_RDATA_MST_15 ((uint32_t)0x00008000) /*!< RDATA_MST bit 15 */
mbed_official 403:91a4bea587f4 1723
mbed_official 403:91a4bea587f4 1724 #define ADC12_CDR_RDATA_SLV ((uint32_t)0xFFFF0000) /*!< Regular Data of the master ADC */
mbed_official 403:91a4bea587f4 1725 #define ADC12_CDR_RDATA_SLV_0 ((uint32_t)0x00010000) /*!< RDATA_SLV bit 0 */
mbed_official 403:91a4bea587f4 1726 #define ADC12_CDR_RDATA_SLV_1 ((uint32_t)0x00020000) /*!< RDATA_SLV bit 1 */
mbed_official 403:91a4bea587f4 1727 #define ADC12_CDR_RDATA_SLV_2 ((uint32_t)0x00040000) /*!< RDATA_SLV bit 2 */
mbed_official 403:91a4bea587f4 1728 #define ADC12_CDR_RDATA_SLV_3 ((uint32_t)0x00080000) /*!< RDATA_SLV bit 3 */
mbed_official 403:91a4bea587f4 1729 #define ADC12_CDR_RDATA_SLV_4 ((uint32_t)0x00100000) /*!< RDATA_SLV bit 4 */
mbed_official 403:91a4bea587f4 1730 #define ADC12_CDR_RDATA_SLV_5 ((uint32_t)0x00200000) /*!< RDATA_SLV bit 5 */
mbed_official 403:91a4bea587f4 1731 #define ADC12_CDR_RDATA_SLV_6 ((uint32_t)0x00400000) /*!< RDATA_SLV bit 6 */
mbed_official 403:91a4bea587f4 1732 #define ADC12_CDR_RDATA_SLV_7 ((uint32_t)0x00800000) /*!< RDATA_SLV bit 7 */
mbed_official 403:91a4bea587f4 1733 #define ADC12_CDR_RDATA_SLV_8 ((uint32_t)0x01000000) /*!< RDATA_SLV bit 8 */
mbed_official 403:91a4bea587f4 1734 #define ADC12_CDR_RDATA_SLV_9 ((uint32_t)0x02000000) /*!< RDATA_SLV bit 9 */
mbed_official 403:91a4bea587f4 1735 #define ADC12_CDR_RDATA_SLV_10 ((uint32_t)0x04000000) /*!< RDATA_SLV bit 10 */
mbed_official 403:91a4bea587f4 1736 #define ADC12_CDR_RDATA_SLV_11 ((uint32_t)0x08000000) /*!< RDATA_SLV bit 11 */
mbed_official 403:91a4bea587f4 1737 #define ADC12_CDR_RDATA_SLV_12 ((uint32_t)0x10000000) /*!< RDATA_SLV bit 12 */
mbed_official 403:91a4bea587f4 1738 #define ADC12_CDR_RDATA_SLV_13 ((uint32_t)0x20000000) /*!< RDATA_SLV bit 13 */
mbed_official 403:91a4bea587f4 1739 #define ADC12_CDR_RDATA_SLV_14 ((uint32_t)0x40000000) /*!< RDATA_SLV bit 14 */
mbed_official 403:91a4bea587f4 1740 #define ADC12_CDR_RDATA_SLV_15 ((uint32_t)0x80000000) /*!< RDATA_SLV bit 15 */
mbed_official 403:91a4bea587f4 1741
mbed_official 403:91a4bea587f4 1742 /******************** Bit definition for ADC_CDR register ********************/
mbed_official 403:91a4bea587f4 1743 #define ADC34_CDR_RDATA_MST ((uint32_t)0x0000FFFF) /*!< Regular Data of the master ADC */
mbed_official 403:91a4bea587f4 1744 #define ADC34_CDR_RDATA_MST_0 ((uint32_t)0x00000001) /*!< RDATA_MST bit 0 */
mbed_official 403:91a4bea587f4 1745 #define ADC34_CDR_RDATA_MST_1 ((uint32_t)0x00000002) /*!< RDATA_MST bit 1 */
mbed_official 403:91a4bea587f4 1746 #define ADC34_CDR_RDATA_MST_2 ((uint32_t)0x00000004) /*!< RDATA_MST bit 2 */
mbed_official 403:91a4bea587f4 1747 #define ADC34_CDR_RDATA_MST_3 ((uint32_t)0x00000008) /*!< RDATA_MST bit 3 */
mbed_official 403:91a4bea587f4 1748 #define ADC34_CDR_RDATA_MST_4 ((uint32_t)0x00000010) /*!< RDATA_MST bit 4 */
mbed_official 403:91a4bea587f4 1749 #define ADC34_CDR_RDATA_MST_5 ((uint32_t)0x00000020) /*!< RDATA_MST bit 5 */
mbed_official 403:91a4bea587f4 1750 #define ADC34_CDR_RDATA_MST_6 ((uint32_t)0x00000040) /*!< RDATA_MST bit 6 */
mbed_official 403:91a4bea587f4 1751 #define ADC34_CDR_RDATA_MST_7 ((uint32_t)0x00000080) /*!< RDATA_MST bit 7 */
mbed_official 403:91a4bea587f4 1752 #define ADC34_CDR_RDATA_MST_8 ((uint32_t)0x00000100) /*!< RDATA_MST bit 8 */
mbed_official 403:91a4bea587f4 1753 #define ADC34_CDR_RDATA_MST_9 ((uint32_t)0x00000200) /*!< RDATA_MST bit 9 */
mbed_official 403:91a4bea587f4 1754 #define ADC34_CDR_RDATA_MST_10 ((uint32_t)0x00000400) /*!< RDATA_MST bit 10 */
mbed_official 403:91a4bea587f4 1755 #define ADC34_CDR_RDATA_MST_11 ((uint32_t)0x00000800) /*!< RDATA_MST bit 11 */
mbed_official 403:91a4bea587f4 1756 #define ADC34_CDR_RDATA_MST_12 ((uint32_t)0x00001000) /*!< RDATA_MST bit 12 */
mbed_official 403:91a4bea587f4 1757 #define ADC34_CDR_RDATA_MST_13 ((uint32_t)0x00002000) /*!< RDATA_MST bit 13 */
mbed_official 403:91a4bea587f4 1758 #define ADC34_CDR_RDATA_MST_14 ((uint32_t)0x00004000) /*!< RDATA_MST bit 14 */
mbed_official 403:91a4bea587f4 1759 #define ADC34_CDR_RDATA_MST_15 ((uint32_t)0x00008000) /*!< RDATA_MST bit 15 */
mbed_official 403:91a4bea587f4 1760
mbed_official 403:91a4bea587f4 1761 #define ADC34_CDR_RDATA_SLV ((uint32_t)0xFFFF0000) /*!< Regular Data of the master ADC */
mbed_official 403:91a4bea587f4 1762 #define ADC34_CDR_RDATA_SLV_0 ((uint32_t)0x00010000) /*!< RDATA_SLV bit 0 */
mbed_official 403:91a4bea587f4 1763 #define ADC34_CDR_RDATA_SLV_1 ((uint32_t)0x00020000) /*!< RDATA_SLV bit 1 */
mbed_official 403:91a4bea587f4 1764 #define ADC34_CDR_RDATA_SLV_2 ((uint32_t)0x00040000) /*!< RDATA_SLV bit 2 */
mbed_official 403:91a4bea587f4 1765 #define ADC34_CDR_RDATA_SLV_3 ((uint32_t)0x00080000) /*!< RDATA_SLV bit 3 */
mbed_official 403:91a4bea587f4 1766 #define ADC34_CDR_RDATA_SLV_4 ((uint32_t)0x00100000) /*!< RDATA_SLV bit 4 */
mbed_official 403:91a4bea587f4 1767 #define ADC34_CDR_RDATA_SLV_5 ((uint32_t)0x00200000) /*!< RDATA_SLV bit 5 */
mbed_official 403:91a4bea587f4 1768 #define ADC34_CDR_RDATA_SLV_6 ((uint32_t)0x00400000) /*!< RDATA_SLV bit 6 */
mbed_official 403:91a4bea587f4 1769 #define ADC34_CDR_RDATA_SLV_7 ((uint32_t)0x00800000) /*!< RDATA_SLV bit 7 */
mbed_official 403:91a4bea587f4 1770 #define ADC34_CDR_RDATA_SLV_8 ((uint32_t)0x01000000) /*!< RDATA_SLV bit 8 */
mbed_official 403:91a4bea587f4 1771 #define ADC34_CDR_RDATA_SLV_9 ((uint32_t)0x02000000) /*!< RDATA_SLV bit 9 */
mbed_official 403:91a4bea587f4 1772 #define ADC34_CDR_RDATA_SLV_10 ((uint32_t)0x04000000) /*!< RDATA_SLV bit 10 */
mbed_official 403:91a4bea587f4 1773 #define ADC34_CDR_RDATA_SLV_11 ((uint32_t)0x08000000) /*!< RDATA_SLV bit 11 */
mbed_official 403:91a4bea587f4 1774 #define ADC34_CDR_RDATA_SLV_12 ((uint32_t)0x10000000) /*!< RDATA_SLV bit 12 */
mbed_official 403:91a4bea587f4 1775 #define ADC34_CDR_RDATA_SLV_13 ((uint32_t)0x20000000) /*!< RDATA_SLV bit 13 */
mbed_official 403:91a4bea587f4 1776 #define ADC34_CDR_RDATA_SLV_14 ((uint32_t)0x40000000) /*!< RDATA_SLV bit 14 */
mbed_official 403:91a4bea587f4 1777 #define ADC34_CDR_RDATA_SLV_15 ((uint32_t)0x80000000) /*!< RDATA_SLV bit 15 */
mbed_official 403:91a4bea587f4 1778
mbed_official 403:91a4bea587f4 1779 /******************************************************************************/
mbed_official 403:91a4bea587f4 1780 /* */
mbed_official 403:91a4bea587f4 1781 /* Analog Comparators (COMP) */
mbed_official 403:91a4bea587f4 1782 /* */
mbed_official 403:91a4bea587f4 1783 /******************************************************************************/
mbed_official 403:91a4bea587f4 1784 /********************** Bit definition for COMP1_CSR register ***************/
mbed_official 403:91a4bea587f4 1785 #define COMP1_CSR_COMP1EN ((uint32_t)0x00000001) /*!< COMP1 enable */
mbed_official 403:91a4bea587f4 1786 #define COMP1_CSR_COMP1SW1 ((uint32_t)0x00000002) /*!< COMP1 SW1 switch control */
mbed_official 403:91a4bea587f4 1787 #define COMP1_CSR_COMP1MODE ((uint32_t)0x0000000C) /*!< COMP1 power mode */
mbed_official 403:91a4bea587f4 1788 #define COMP1_CSR_COMP1MODE_0 ((uint32_t)0x00000004) /*!< COMP1 power mode bit 0 */
mbed_official 403:91a4bea587f4 1789 #define COMP1_CSR_COMP1MODE_1 ((uint32_t)0x00000008) /*!< COMP1 power mode bit 1 */
mbed_official 403:91a4bea587f4 1790 #define COMP1_CSR_COMP1INSEL ((uint32_t)0x00000070) /*!< COMP1 inverting input select */
mbed_official 403:91a4bea587f4 1791 #define COMP1_CSR_COMP1INSEL_0 ((uint32_t)0x00000010) /*!< COMP1 inverting input select bit 0 */
mbed_official 403:91a4bea587f4 1792 #define COMP1_CSR_COMP1INSEL_1 ((uint32_t)0x00000020) /*!< COMP1 inverting input select bit 1 */
mbed_official 403:91a4bea587f4 1793 #define COMP1_CSR_COMP1INSEL_2 ((uint32_t)0x00000040) /*!< COMP1 inverting input select bit 2 */
mbed_official 403:91a4bea587f4 1794 #define COMP1_CSR_COMP1NONINSEL ((uint32_t)0x00000080) /*!< COMP1 non inverting input select */
mbed_official 403:91a4bea587f4 1795 #define COMP1_CSR_COMP1OUTSEL ((uint32_t)0x00003C00) /*!< COMP1 output select */
mbed_official 403:91a4bea587f4 1796 #define COMP1_CSR_COMP1OUTSEL_0 ((uint32_t)0x00000400) /*!< COMP1 output select bit 0 */
mbed_official 403:91a4bea587f4 1797 #define COMP1_CSR_COMP1OUTSEL_1 ((uint32_t)0x00000800) /*!< COMP1 output select bit 1 */
mbed_official 403:91a4bea587f4 1798 #define COMP1_CSR_COMP1OUTSEL_2 ((uint32_t)0x00001000) /*!< COMP1 output select bit 2 */
mbed_official 403:91a4bea587f4 1799 #define COMP1_CSR_COMP1OUTSEL_3 ((uint32_t)0x00002000) /*!< COMP1 output select bit 3 */
mbed_official 403:91a4bea587f4 1800 #define COMP1_CSR_COMP1POL ((uint32_t)0x00008000) /*!< COMP1 output polarity */
mbed_official 403:91a4bea587f4 1801 #define COMP1_CSR_COMP1HYST ((uint32_t)0x00030000) /*!< COMP1 hysteresis */
mbed_official 403:91a4bea587f4 1802 #define COMP1_CSR_COMP1HYST_0 ((uint32_t)0x00010000) /*!< COMP1 hysteresis bit 0 */
mbed_official 403:91a4bea587f4 1803 #define COMP1_CSR_COMP1HYST_1 ((uint32_t)0x00020000) /*!< COMP1 hysteresis bit 1 */
mbed_official 403:91a4bea587f4 1804 #define COMP1_CSR_COMP1BLANKING ((uint32_t)0x000C0000) /*!< COMP1 blanking */
mbed_official 403:91a4bea587f4 1805 #define COMP1_CSR_COMP1BLANKING_0 ((uint32_t)0x00040000) /*!< COMP1 blanking bit 0 */
mbed_official 403:91a4bea587f4 1806 #define COMP1_CSR_COMP1BLANKING_1 ((uint32_t)0x00080000) /*!< COMP1 blanking bit 1 */
mbed_official 403:91a4bea587f4 1807 #define COMP1_CSR_COMP1BLANKING_2 ((uint32_t)0x00100000) /*!< COMP1 blanking bit 2 */
mbed_official 403:91a4bea587f4 1808 #define COMP1_CSR_COMP1OUT ((uint32_t)0x40000000) /*!< COMP1 output level */
mbed_official 403:91a4bea587f4 1809 #define COMP1_CSR_COMP1LOCK ((uint32_t)0x80000000) /*!< COMP1 lock */
mbed_official 403:91a4bea587f4 1810
mbed_official 403:91a4bea587f4 1811 /********************** Bit definition for COMP2_CSR register ***************/
mbed_official 403:91a4bea587f4 1812 #define COMP2_CSR_COMP2EN ((uint32_t)0x00000001) /*!< COMP2 enable */
mbed_official 403:91a4bea587f4 1813 #define COMP2_CSR_COMP2MODE ((uint32_t)0x0000000C) /*!< COMP2 power mode */
mbed_official 403:91a4bea587f4 1814 #define COMP2_CSR_COMP2MODE_0 ((uint32_t)0x00000004) /*!< COMP2 power mode bit 0 */
mbed_official 403:91a4bea587f4 1815 #define COMP2_CSR_COMP2MODE_1 ((uint32_t)0x00000008) /*!< COMP2 power mode bit 1 */
mbed_official 403:91a4bea587f4 1816 #define COMP2_CSR_COMP2INSEL ((uint32_t)0x00400070) /*!< COMP2 inverting input select */
mbed_official 403:91a4bea587f4 1817 #define COMP2_CSR_COMP2INSEL_0 ((uint32_t)0x00000010) /*!< COMP2 inverting input select bit 0 */
mbed_official 403:91a4bea587f4 1818 #define COMP2_CSR_COMP2INSEL_1 ((uint32_t)0x00000020) /*!< COMP2 inverting input select bit 1 */
mbed_official 403:91a4bea587f4 1819 #define COMP2_CSR_COMP2INSEL_2 ((uint32_t)0x00000040) /*!< COMP2 inverting input select bit 2 */
mbed_official 403:91a4bea587f4 1820 #define COMP2_CSR_COMP2INSEL_3 ((uint32_t)0x00400000) /*!< COMP2 inverting input select bit 3 */
mbed_official 403:91a4bea587f4 1821 #define COMP2_CSR_COMP2NONINSEL ((uint32_t)0x00000080) /*!< COMP2 non inverting input select */
mbed_official 403:91a4bea587f4 1822 #define COMP2_CSR_COMP2WNDWEN ((uint32_t)0x00000200) /*!< COMP2 window mode enable */
mbed_official 403:91a4bea587f4 1823 #define COMP2_CSR_COMP2OUTSEL ((uint32_t)0x00003C00) /*!< COMP2 output select */
mbed_official 403:91a4bea587f4 1824 #define COMP2_CSR_COMP2OUTSEL_0 ((uint32_t)0x00000400) /*!< COMP2 output select bit 0 */
mbed_official 403:91a4bea587f4 1825 #define COMP2_CSR_COMP2OUTSEL_1 ((uint32_t)0x00000800) /*!< COMP2 output select bit 1 */
mbed_official 403:91a4bea587f4 1826 #define COMP2_CSR_COMP2OUTSEL_2 ((uint32_t)0x00001000) /*!< COMP2 output select bit 2 */
mbed_official 403:91a4bea587f4 1827 #define COMP2_CSR_COMP2OUTSEL_3 ((uint32_t)0x00002000) /*!< COMP2 output select bit 3 */
mbed_official 403:91a4bea587f4 1828 #define COMP2_CSR_COMP2POL ((uint32_t)0x00008000) /*!< COMP2 output polarity */
mbed_official 403:91a4bea587f4 1829 #define COMP2_CSR_COMP2HYST ((uint32_t)0x00030000) /*!< COMP2 hysteresis */
mbed_official 403:91a4bea587f4 1830 #define COMP2_CSR_COMP2HYST_0 ((uint32_t)0x00010000) /*!< COMP2 hysteresis bit 0 */
mbed_official 403:91a4bea587f4 1831 #define COMP2_CSR_COMP2HYST_1 ((uint32_t)0x00020000) /*!< COMP2 hysteresis bit 1 */
mbed_official 403:91a4bea587f4 1832 #define COMP2_CSR_COMP2BLANKING ((uint32_t)0x000C0000) /*!< COMP2 blanking */
mbed_official 403:91a4bea587f4 1833 #define COMP2_CSR_COMP2BLANKING_0 ((uint32_t)0x00040000) /*!< COMP2 blanking bit 0 */
mbed_official 403:91a4bea587f4 1834 #define COMP2_CSR_COMP2BLANKING_1 ((uint32_t)0x00080000) /*!< COMP2 blanking bit 1 */
mbed_official 403:91a4bea587f4 1835 #define COMP2_CSR_COMP2BLANKING_2 ((uint32_t)0x00100000) /*!< COMP2 blanking bit 2 */
mbed_official 403:91a4bea587f4 1836 #define COMP2_CSR_COMP2OUT ((uint32_t)0x40000000) /*!< COMP2 output level */
mbed_official 403:91a4bea587f4 1837 #define COMP2_CSR_COMP2LOCK ((uint32_t)0x80000000) /*!< COMP2 lock */
mbed_official 403:91a4bea587f4 1838
mbed_official 403:91a4bea587f4 1839 /********************** Bit definition for COMP3_CSR register ***************/
mbed_official 403:91a4bea587f4 1840 #define COMP3_CSR_COMP3EN ((uint32_t)0x00000001) /*!< COMP3 enable */
mbed_official 403:91a4bea587f4 1841 #define COMP3_CSR_COMP3MODE ((uint32_t)0x0000000C) /*!< COMP3 power mode */
mbed_official 403:91a4bea587f4 1842 #define COMP3_CSR_COMP3MODE_0 ((uint32_t)0x00000004) /*!< COMP3 power mode bit 0 */
mbed_official 403:91a4bea587f4 1843 #define COMP3_CSR_COMP3MODE_1 ((uint32_t)0x00000008) /*!< COMP3 power mode bit 1 */
mbed_official 403:91a4bea587f4 1844 #define COMP3_CSR_COMP3INSEL ((uint32_t)0x00000070) /*!< COMP3 inverting input select */
mbed_official 403:91a4bea587f4 1845 #define COMP3_CSR_COMP3INSEL_0 ((uint32_t)0x00000010) /*!< COMP3 inverting input select bit 0 */
mbed_official 403:91a4bea587f4 1846 #define COMP3_CSR_COMP3INSEL_1 ((uint32_t)0x00000020) /*!< COMP3 inverting input select bit 1 */
mbed_official 403:91a4bea587f4 1847 #define COMP3_CSR_COMP3INSEL_2 ((uint32_t)0x00000040) /*!< COMP3 inverting input select bit 2 */
mbed_official 403:91a4bea587f4 1848 #define COMP3_CSR_COMP3NONINSEL ((uint32_t)0x00000080) /*!< COMP3 non inverting input select */
mbed_official 403:91a4bea587f4 1849 #define COMP3_CSR_COMP3OUTSEL ((uint32_t)0x00003C00) /*!< COMP3 output select */
mbed_official 403:91a4bea587f4 1850 #define COMP3_CSR_COMP3OUTSEL_0 ((uint32_t)0x00000400) /*!< COMP3 output select bit 0 */
mbed_official 403:91a4bea587f4 1851 #define COMP3_CSR_COMP3OUTSEL_1 ((uint32_t)0x00000800) /*!< COMP3 output select bit 1 */
mbed_official 403:91a4bea587f4 1852 #define COMP3_CSR_COMP3OUTSEL_2 ((uint32_t)0x00001000) /*!< COMP3 output select bit 2 */
mbed_official 403:91a4bea587f4 1853 #define COMP3_CSR_COMP3OUTSEL_3 ((uint32_t)0x00002000) /*!< COMP3 output select bit 3 */
mbed_official 403:91a4bea587f4 1854 #define COMP3_CSR_COMP3POL ((uint32_t)0x00008000) /*!< COMP3 output polarity */
mbed_official 403:91a4bea587f4 1855 #define COMP3_CSR_COMP3HYST ((uint32_t)0x00030000) /*!< COMP3 hysteresis */
mbed_official 403:91a4bea587f4 1856 #define COMP3_CSR_COMP3HYST_0 ((uint32_t)0x00010000) /*!< COMP3 hysteresis bit 0 */
mbed_official 403:91a4bea587f4 1857 #define COMP3_CSR_COMP3HYST_1 ((uint32_t)0x00020000) /*!< COMP3 hysteresis bit 1 */
mbed_official 403:91a4bea587f4 1858 #define COMP3_CSR_COMP3BLANKING ((uint32_t)0x000C0000) /*!< COMP3 blanking */
mbed_official 403:91a4bea587f4 1859 #define COMP3_CSR_COMP3BLANKING_0 ((uint32_t)0x00040000) /*!< COMP3 blanking bit 0 */
mbed_official 403:91a4bea587f4 1860 #define COMP3_CSR_COMP3BLANKING_1 ((uint32_t)0x00080000) /*!< COMP3 blanking bit 1 */
mbed_official 403:91a4bea587f4 1861 #define COMP3_CSR_COMP3BLANKING_2 ((uint32_t)0x00100000) /*!< COMP3 blanking bit 2 */
mbed_official 403:91a4bea587f4 1862 #define COMP3_CSR_COMP3OUT ((uint32_t)0x40000000) /*!< COMP3 output level */
mbed_official 403:91a4bea587f4 1863 #define COMP3_CSR_COMP3LOCK ((uint32_t)0x80000000) /*!< COMP3 lock */
mbed_official 403:91a4bea587f4 1864
mbed_official 403:91a4bea587f4 1865 /********************** Bit definition for COMP4_CSR register ***************/
mbed_official 403:91a4bea587f4 1866 #define COMP4_CSR_COMP4EN ((uint32_t)0x00000001) /*!< COMP4 enable */
mbed_official 403:91a4bea587f4 1867 #define COMP4_CSR_COMP4MODE ((uint32_t)0x0000000C) /*!< COMP4 power mode */
mbed_official 403:91a4bea587f4 1868 #define COMP4_CSR_COMP4MODE_0 ((uint32_t)0x00000004) /*!< COMP4 power mode bit 0 */
mbed_official 403:91a4bea587f4 1869 #define COMP4_CSR_COMP4MODE_1 ((uint32_t)0x00000008) /*!< COMP4 power mode bit 1 */
mbed_official 403:91a4bea587f4 1870 #define COMP4_CSR_COMP4INSEL ((uint32_t)0x00400070) /*!< COMP4 inverting input select */
mbed_official 403:91a4bea587f4 1871 #define COMP4_CSR_COMP4INSEL_0 ((uint32_t)0x00000010) /*!< COMP4 inverting input select bit 0 */
mbed_official 403:91a4bea587f4 1872 #define COMP4_CSR_COMP4INSEL_1 ((uint32_t)0x00000020) /*!< COMP4 inverting input select bit 1 */
mbed_official 403:91a4bea587f4 1873 #define COMP4_CSR_COMP4INSEL_2 ((uint32_t)0x00000040) /*!< COMP4 inverting input select bit 2 */
mbed_official 403:91a4bea587f4 1874 #define COMP4_CSR_COMP4INSEL_3 ((uint32_t)0x00400000) /*!< COMP4 inverting input select bit 3 */
mbed_official 403:91a4bea587f4 1875 #define COMP4_CSR_COMP4NONINSEL ((uint32_t)0x00000080) /*!< COMP4 non inverting input select */
mbed_official 403:91a4bea587f4 1876 #define COMP4_CSR_COMP4WNDWEN ((uint32_t)0x00000200) /*!< COMP4 window mode enable */
mbed_official 403:91a4bea587f4 1877 #define COMP4_CSR_COMP4OUTSEL ((uint32_t)0x00003C00) /*!< COMP4 output select */
mbed_official 403:91a4bea587f4 1878 #define COMP4_CSR_COMP4OUTSEL_0 ((uint32_t)0x00000400) /*!< COMP4 output select bit 0 */
mbed_official 403:91a4bea587f4 1879 #define COMP4_CSR_COMP4OUTSEL_1 ((uint32_t)0x00000800) /*!< COMP4 output select bit 1 */
mbed_official 403:91a4bea587f4 1880 #define COMP4_CSR_COMP4OUTSEL_2 ((uint32_t)0x00001000) /*!< COMP4 output select bit 2 */
mbed_official 403:91a4bea587f4 1881 #define COMP4_CSR_COMP4OUTSEL_3 ((uint32_t)0x00002000) /*!< COMP4 output select bit 3 */
mbed_official 403:91a4bea587f4 1882 #define COMP4_CSR_COMP4POL ((uint32_t)0x00008000) /*!< COMP4 output polarity */
mbed_official 403:91a4bea587f4 1883 #define COMP4_CSR_COMP4HYST ((uint32_t)0x00030000) /*!< COMP4 hysteresis */
mbed_official 403:91a4bea587f4 1884 #define COMP4_CSR_COMP4HYST_0 ((uint32_t)0x00010000) /*!< COMP4 hysteresis bit 0 */
mbed_official 403:91a4bea587f4 1885 #define COMP4_CSR_COMP4HYST_1 ((uint32_t)0x00020000) /*!< COMP4 hysteresis bit 1 */
mbed_official 403:91a4bea587f4 1886 #define COMP4_CSR_COMP4BLANKING ((uint32_t)0x000C0000) /*!< COMP4 blanking */
mbed_official 403:91a4bea587f4 1887 #define COMP4_CSR_COMP4BLANKING_0 ((uint32_t)0x00040000) /*!< COMP4 blanking bit 0 */
mbed_official 403:91a4bea587f4 1888 #define COMP4_CSR_COMP4BLANKING_1 ((uint32_t)0x00080000) /*!< COMP4 blanking bit 1 */
mbed_official 403:91a4bea587f4 1889 #define COMP4_CSR_COMP4BLANKING_2 ((uint32_t)0x00100000) /*!< COMP4 blanking bit 2 */
mbed_official 403:91a4bea587f4 1890 #define COMP4_CSR_COMP4OUT ((uint32_t)0x40000000) /*!< COMP4 output level */
mbed_official 403:91a4bea587f4 1891 #define COMP4_CSR_COMP4LOCK ((uint32_t)0x80000000) /*!< COMP4 lock */
mbed_official 403:91a4bea587f4 1892
mbed_official 403:91a4bea587f4 1893 /********************** Bit definition for COMP5_CSR register ***************/
mbed_official 403:91a4bea587f4 1894 #define COMP5_CSR_COMP5EN ((uint32_t)0x00000001) /*!< COMP5 enable */
mbed_official 403:91a4bea587f4 1895 #define COMP5_CSR_COMP5MODE ((uint32_t)0x0000000C) /*!< COMP5 power mode */
mbed_official 403:91a4bea587f4 1896 #define COMP5_CSR_COMP5MODE_0 ((uint32_t)0x00000004) /*!< COMP5 power mode bit 0 */
mbed_official 403:91a4bea587f4 1897 #define COMP5_CSR_COMP5MODE_1 ((uint32_t)0x00000008) /*!< COMP5 power mode bit 1 */
mbed_official 403:91a4bea587f4 1898 #define COMP5_CSR_COMP5INSEL ((uint32_t)0x00000070) /*!< COMP5 inverting input select */
mbed_official 403:91a4bea587f4 1899 #define COMP5_CSR_COMP5INSEL_0 ((uint32_t)0x00000010) /*!< COMP5 inverting input select bit 0 */
mbed_official 403:91a4bea587f4 1900 #define COMP5_CSR_COMP5INSEL_1 ((uint32_t)0x00000020) /*!< COMP5 inverting input select bit 1 */
mbed_official 403:91a4bea587f4 1901 #define COMP5_CSR_COMP5INSEL_2 ((uint32_t)0x00000040) /*!< COMP5 inverting input select bit 2 */
mbed_official 403:91a4bea587f4 1902 #define COMP5_CSR_COMP5NONINSEL ((uint32_t)0x00000080) /*!< COMP5 non inverting input select */
mbed_official 403:91a4bea587f4 1903 #define COMP5_CSR_COMP5OUTSEL ((uint32_t)0x00003C00) /*!< COMP5 output select */
mbed_official 403:91a4bea587f4 1904 #define COMP5_CSR_COMP5OUTSEL_0 ((uint32_t)0x00000400) /*!< COMP5 output select bit 0 */
mbed_official 403:91a4bea587f4 1905 #define COMP5_CSR_COMP5OUTSEL_1 ((uint32_t)0x00000800) /*!< COMP5 output select bit 1 */
mbed_official 403:91a4bea587f4 1906 #define COMP5_CSR_COMP5OUTSEL_2 ((uint32_t)0x00001000) /*!< COMP5 output select bit 2 */
mbed_official 403:91a4bea587f4 1907 #define COMP5_CSR_COMP5OUTSEL_3 ((uint32_t)0x00002000) /*!< COMP5 output select bit 3 */
mbed_official 403:91a4bea587f4 1908 #define COMP5_CSR_COMP5POL ((uint32_t)0x00008000) /*!< COMP5 output polarity */
mbed_official 403:91a4bea587f4 1909 #define COMP5_CSR_COMP5HYST ((uint32_t)0x00030000) /*!< COMP5 hysteresis */
mbed_official 403:91a4bea587f4 1910 #define COMP5_CSR_COMP5HYST_0 ((uint32_t)0x00010000) /*!< COMP5 hysteresis bit 0 */
mbed_official 403:91a4bea587f4 1911 #define COMP5_CSR_COMP5HYST_1 ((uint32_t)0x00020000) /*!< COMP5 hysteresis bit 1 */
mbed_official 403:91a4bea587f4 1912 #define COMP5_CSR_COMP5BLANKING ((uint32_t)0x000C0000) /*!< COMP5 blanking */
mbed_official 403:91a4bea587f4 1913 #define COMP5_CSR_COMP5BLANKING_0 ((uint32_t)0x00040000) /*!< COMP5 blanking bit 0 */
mbed_official 403:91a4bea587f4 1914 #define COMP5_CSR_COMP5BLANKING_1 ((uint32_t)0x00080000) /*!< COMP5 blanking bit 1 */
mbed_official 403:91a4bea587f4 1915 #define COMP5_CSR_COMP5BLANKING_2 ((uint32_t)0x00100000) /*!< COMP5 blanking bit 2 */
mbed_official 403:91a4bea587f4 1916 #define COMP5_CSR_COMP5OUT ((uint32_t)0x40000000) /*!< COMP5 output level */
mbed_official 403:91a4bea587f4 1917 #define COMP5_CSR_COMP5LOCK ((uint32_t)0x80000000) /*!< COMP5 lock */
mbed_official 403:91a4bea587f4 1918
mbed_official 403:91a4bea587f4 1919 /********************** Bit definition for COMP6_CSR register ***************/
mbed_official 403:91a4bea587f4 1920 #define COMP6_CSR_COMP6EN ((uint32_t)0x00000001) /*!< COMP6 enable */
mbed_official 403:91a4bea587f4 1921 #define COMP6_CSR_COMP6MODE ((uint32_t)0x0000000C) /*!< COMP6 power mode */
mbed_official 403:91a4bea587f4 1922 #define COMP6_CSR_COMP6MODE_0 ((uint32_t)0x00000004) /*!< COMP6 power mode bit 0 */
mbed_official 403:91a4bea587f4 1923 #define COMP6_CSR_COMP6MODE_1 ((uint32_t)0x00000008) /*!< COMP6 power mode bit 1 */
mbed_official 403:91a4bea587f4 1924 #define COMP6_CSR_COMP6INSEL ((uint32_t)0x00400070) /*!< COMP6 inverting input select */
mbed_official 403:91a4bea587f4 1925 #define COMP6_CSR_COMP6INSEL_0 ((uint32_t)0x00000010) /*!< COMP6 inverting input select bit 0 */
mbed_official 403:91a4bea587f4 1926 #define COMP6_CSR_COMP6INSEL_1 ((uint32_t)0x00000020) /*!< COMP6 inverting input select bit 1 */
mbed_official 403:91a4bea587f4 1927 #define COMP6_CSR_COMP6INSEL_2 ((uint32_t)0x00000040) /*!< COMP6 inverting input select bit 2 */
mbed_official 403:91a4bea587f4 1928 #define COMP6_CSR_COMP6INSEL_3 ((uint32_t)0x00400000) /*!< COMP6 inverting input select bit 3 */
mbed_official 403:91a4bea587f4 1929 #define COMP6_CSR_COMP6NONINSEL ((uint32_t)0x00000080) /*!< COMP6 non inverting input select */
mbed_official 403:91a4bea587f4 1930 #define COMP6_CSR_COMP6WNDWEN ((uint32_t)0x00000200) /*!< COMP6 window mode enable */
mbed_official 403:91a4bea587f4 1931 #define COMP6_CSR_COMP6OUTSEL ((uint32_t)0x00003C00) /*!< COMP6 output select */
mbed_official 403:91a4bea587f4 1932 #define COMP6_CSR_COMP6OUTSEL_0 ((uint32_t)0x00000400) /*!< COMP6 output select bit 0 */
mbed_official 403:91a4bea587f4 1933 #define COMP6_CSR_COMP6OUTSEL_1 ((uint32_t)0x00000800) /*!< COMP6 output select bit 1 */
mbed_official 403:91a4bea587f4 1934 #define COMP6_CSR_COMP6OUTSEL_2 ((uint32_t)0x00001000) /*!< COMP6 output select bit 2 */
mbed_official 403:91a4bea587f4 1935 #define COMP6_CSR_COMP6OUTSEL_3 ((uint32_t)0x00002000) /*!< COMP6 output select bit 3 */
mbed_official 403:91a4bea587f4 1936 #define COMP6_CSR_COMP6POL ((uint32_t)0x00008000) /*!< COMP6 output polarity */
mbed_official 403:91a4bea587f4 1937 #define COMP6_CSR_COMP6HYST ((uint32_t)0x00030000) /*!< COMP6 hysteresis */
mbed_official 403:91a4bea587f4 1938 #define COMP6_CSR_COMP6HYST_0 ((uint32_t)0x00010000) /*!< COMP6 hysteresis bit 0 */
mbed_official 403:91a4bea587f4 1939 #define COMP6_CSR_COMP6HYST_1 ((uint32_t)0x00020000) /*!< COMP6 hysteresis bit 1 */
mbed_official 403:91a4bea587f4 1940 #define COMP6_CSR_COMP6BLANKING ((uint32_t)0x000C0000) /*!< COMP6 blanking */
mbed_official 403:91a4bea587f4 1941 #define COMP6_CSR_COMP6BLANKING_0 ((uint32_t)0x00040000) /*!< COMP6 blanking bit 0 */
mbed_official 403:91a4bea587f4 1942 #define COMP6_CSR_COMP6BLANKING_1 ((uint32_t)0x00080000) /*!< COMP6 blanking bit 1 */
mbed_official 403:91a4bea587f4 1943 #define COMP6_CSR_COMP6BLANKING_2 ((uint32_t)0x00100000) /*!< COMP6 blanking bit 2 */
mbed_official 403:91a4bea587f4 1944 #define COMP6_CSR_COMP6OUT ((uint32_t)0x40000000) /*!< COMP6 output level */
mbed_official 403:91a4bea587f4 1945 #define COMP6_CSR_COMP6LOCK ((uint32_t)0x80000000) /*!< COMP6 lock */
mbed_official 403:91a4bea587f4 1946
mbed_official 403:91a4bea587f4 1947 /********************** Bit definition for COMP7_CSR register ***************/
mbed_official 403:91a4bea587f4 1948 #define COMP7_CSR_COMP7EN ((uint32_t)0x00000001) /*!< COMP7 enable */
mbed_official 403:91a4bea587f4 1949 #define COMP7_CSR_COMP7MODE ((uint32_t)0x0000000C) /*!< COMP7 power mode */
mbed_official 403:91a4bea587f4 1950 #define COMP7_CSR_COMP7MODE_0 ((uint32_t)0x00000004) /*!< COMP7 power mode bit 0 */
mbed_official 403:91a4bea587f4 1951 #define COMP7_CSR_COMP7MODE_1 ((uint32_t)0x00000008) /*!< COMP7 power mode bit 1 */
mbed_official 403:91a4bea587f4 1952 #define COMP7_CSR_COMP7INSEL ((uint32_t)0x00000070) /*!< COMP7 inverting input select */
mbed_official 403:91a4bea587f4 1953 #define COMP7_CSR_COMP7INSEL_0 ((uint32_t)0x00000010) /*!< COMP7 inverting input select bit 0 */
mbed_official 403:91a4bea587f4 1954 #define COMP7_CSR_COMP7INSEL_1 ((uint32_t)0x00000020) /*!< COMP7 inverting input select bit 1 */
mbed_official 403:91a4bea587f4 1955 #define COMP7_CSR_COMP7INSEL_2 ((uint32_t)0x00000040) /*!< COMP7 inverting input select bit 2 */
mbed_official 403:91a4bea587f4 1956 #define COMP7_CSR_COMP7NONINSEL ((uint32_t)0x00000080) /*!< COMP7 non inverting input select */
mbed_official 403:91a4bea587f4 1957 #define COMP7_CSR_COMP7OUTSEL ((uint32_t)0x00003C00) /*!< COMP7 output select */
mbed_official 403:91a4bea587f4 1958 #define COMP7_CSR_COMP7OUTSEL_0 ((uint32_t)0x00000400) /*!< COMP7 output select bit 0 */
mbed_official 403:91a4bea587f4 1959 #define COMP7_CSR_COMP7OUTSEL_1 ((uint32_t)0x00000800) /*!< COMP7 output select bit 1 */
mbed_official 403:91a4bea587f4 1960 #define COMP7_CSR_COMP7OUTSEL_2 ((uint32_t)0x00001000) /*!< COMP7 output select bit 2 */
mbed_official 403:91a4bea587f4 1961 #define COMP7_CSR_COMP7OUTSEL_3 ((uint32_t)0x00002000) /*!< COMP7 output select bit 3 */
mbed_official 403:91a4bea587f4 1962 #define COMP7_CSR_COMP7POL ((uint32_t)0x00008000) /*!< COMP7 output polarity */
mbed_official 403:91a4bea587f4 1963 #define COMP7_CSR_COMP7HYST ((uint32_t)0x00030000) /*!< COMP7 hysteresis */
mbed_official 403:91a4bea587f4 1964 #define COMP7_CSR_COMP7HYST_0 ((uint32_t)0x00010000) /*!< COMP7 hysteresis bit 0 */
mbed_official 403:91a4bea587f4 1965 #define COMP7_CSR_COMP7HYST_1 ((uint32_t)0x00020000) /*!< COMP7 hysteresis bit 1 */
mbed_official 403:91a4bea587f4 1966 #define COMP7_CSR_COMP7BLANKING ((uint32_t)0x000C0000) /*!< COMP7 blanking */
mbed_official 403:91a4bea587f4 1967 #define COMP7_CSR_COMP7BLANKING_0 ((uint32_t)0x00040000) /*!< COMP7 blanking bit 0 */
mbed_official 403:91a4bea587f4 1968 #define COMP7_CSR_COMP7BLANKING_1 ((uint32_t)0x00080000) /*!< COMP7 blanking bit 1 */
mbed_official 403:91a4bea587f4 1969 #define COMP7_CSR_COMP7BLANKING_2 ((uint32_t)0x00100000) /*!< COMP7 blanking bit 2 */
mbed_official 403:91a4bea587f4 1970 #define COMP7_CSR_COMP7OUT ((uint32_t)0x40000000) /*!< COMP7 output level */
mbed_official 403:91a4bea587f4 1971 #define COMP7_CSR_COMP7LOCK ((uint32_t)0x80000000) /*!< COMP7 lock */
mbed_official 403:91a4bea587f4 1972
mbed_official 403:91a4bea587f4 1973 /********************** Bit definition for COMP_CSR register ****************/
mbed_official 403:91a4bea587f4 1974 #define COMP_CSR_COMPxEN ((uint32_t)0x00000001) /*!< COMPx enable */
mbed_official 403:91a4bea587f4 1975 #define COMP_CSR_COMP1SW1 ((uint32_t)0x00000002) /*!< COMP1 SW1 switch control */
mbed_official 403:91a4bea587f4 1976 #define COMP_CSR_COMPxMODE ((uint32_t)0x0000000C) /*!< COMPx power mode */
mbed_official 403:91a4bea587f4 1977 #define COMP_CSR_COMPxMODE_0 ((uint32_t)0x00000004) /*!< COMPx power mode bit 0 */
mbed_official 403:91a4bea587f4 1978 #define COMP_CSR_COMPxMODE_1 ((uint32_t)0x00000008) /*!< COMPx power mode bit 1 */
mbed_official 403:91a4bea587f4 1979 #define COMP_CSR_COMPxINSEL ((uint32_t)0x00400070) /*!< COMPx inverting input select */
mbed_official 403:91a4bea587f4 1980 #define COMP_CSR_COMPxINSEL_0 ((uint32_t)0x00000010) /*!< COMPx inverting input select bit 0 */
mbed_official 403:91a4bea587f4 1981 #define COMP_CSR_COMPxINSEL_1 ((uint32_t)0x00000020) /*!< COMPx inverting input select bit 1 */
mbed_official 403:91a4bea587f4 1982 #define COMP_CSR_COMPxINSEL_2 ((uint32_t)0x00000040) /*!< COMPx inverting input select bit 2 */
mbed_official 403:91a4bea587f4 1983 #define COMP_CSR_COMPxINSEL_3 ((uint32_t)0x00400000) /*!< COMPx inverting input select bit 3 */
mbed_official 403:91a4bea587f4 1984 #define COMP_CSR_COMPxNONINSEL ((uint32_t)0x00000080) /*!< COMPx non inverting input select */
mbed_official 403:91a4bea587f4 1985 #define COMP_CSR_COMPxWNDWEN ((uint32_t)0x00000200) /*!< COMPx window mode enable */
mbed_official 403:91a4bea587f4 1986 #define COMP_CSR_COMPxOUTSEL ((uint32_t)0x00003C00) /*!< COMPx output select */
mbed_official 403:91a4bea587f4 1987 #define COMP_CSR_COMPxOUTSEL_0 ((uint32_t)0x00000400) /*!< COMPx output select bit 0 */
mbed_official 403:91a4bea587f4 1988 #define COMP_CSR_COMPxOUTSEL_1 ((uint32_t)0x00000800) /*!< COMPx output select bit 1 */
mbed_official 403:91a4bea587f4 1989 #define COMP_CSR_COMPxOUTSEL_2 ((uint32_t)0x00001000) /*!< COMPx output select bit 2 */
mbed_official 403:91a4bea587f4 1990 #define COMP_CSR_COMPxOUTSEL_3 ((uint32_t)0x00002000) /*!< COMPx output select bit 3 */
mbed_official 403:91a4bea587f4 1991 #define COMP_CSR_COMPxPOL ((uint32_t)0x00008000) /*!< COMPx output polarity */
mbed_official 403:91a4bea587f4 1992 #define COMP_CSR_COMPxHYST ((uint32_t)0x00030000) /*!< COMPx hysteresis */
mbed_official 403:91a4bea587f4 1993 #define COMP_CSR_COMPxHYST_0 ((uint32_t)0x00010000) /*!< COMPx hysteresis bit 0 */
mbed_official 403:91a4bea587f4 1994 #define COMP_CSR_COMPxHYST_1 ((uint32_t)0x00020000) /*!< COMPx hysteresis bit 1 */
mbed_official 403:91a4bea587f4 1995 #define COMP_CSR_COMPxBLANKING ((uint32_t)0x000C0000) /*!< COMPx blanking */
mbed_official 403:91a4bea587f4 1996 #define COMP_CSR_COMPxBLANKING_0 ((uint32_t)0x00040000) /*!< COMPx blanking bit 0 */
mbed_official 403:91a4bea587f4 1997 #define COMP_CSR_COMPxBLANKING_1 ((uint32_t)0x00080000) /*!< COMPx blanking bit 1 */
mbed_official 403:91a4bea587f4 1998 #define COMP_CSR_COMPxBLANKING_2 ((uint32_t)0x00100000) /*!< COMPx blanking bit 2 */
mbed_official 403:91a4bea587f4 1999 #define COMP_CSR_COMPxINSEL_3 ((uint32_t)0x00400000) /*!< COMPx inverting input select bit 3 */
mbed_official 403:91a4bea587f4 2000 #define COMP_CSR_COMPxOUT ((uint32_t)0x40000000) /*!< COMPx output level */
mbed_official 403:91a4bea587f4 2001 #define COMP_CSR_COMPxLOCK ((uint32_t)0x80000000) /*!< COMPx lock */
mbed_official 403:91a4bea587f4 2002
mbed_official 403:91a4bea587f4 2003 /******************************************************************************/
mbed_official 403:91a4bea587f4 2004 /* */
mbed_official 403:91a4bea587f4 2005 /* Operational Amplifier (OPAMP) */
mbed_official 403:91a4bea587f4 2006 /* */
mbed_official 403:91a4bea587f4 2007 /******************************************************************************/
mbed_official 403:91a4bea587f4 2008 /********************* Bit definition for OPAMP1_CSR register ***************/
mbed_official 403:91a4bea587f4 2009 #define OPAMP1_CSR_OPAMP1EN ((uint32_t)0x00000001) /*!< OPAMP1 enable */
mbed_official 403:91a4bea587f4 2010 #define OPAMP1_CSR_FORCEVP ((uint32_t)0x00000002) /*!< Connect the internal references to the plus input of the OPAMPX */
mbed_official 403:91a4bea587f4 2011 #define OPAMP1_CSR_VPSEL ((uint32_t)0x0000000C) /*!< Non inverting input selection */
mbed_official 403:91a4bea587f4 2012 #define OPAMP1_CSR_VPSEL_0 ((uint32_t)0x00000004) /*!< Bit 0 */
mbed_official 403:91a4bea587f4 2013 #define OPAMP1_CSR_VPSEL_1 ((uint32_t)0x00000008) /*!< Bit 1 */
mbed_official 403:91a4bea587f4 2014 #define OPAMP1_CSR_VMSEL ((uint32_t)0x00000060) /*!< Inverting input selection */
mbed_official 403:91a4bea587f4 2015 #define OPAMP1_CSR_VMSEL_0 ((uint32_t)0x00000020) /*!< Bit 0 */
mbed_official 403:91a4bea587f4 2016 #define OPAMP1_CSR_VMSEL_1 ((uint32_t)0x00000040) /*!< Bit 1 */
mbed_official 403:91a4bea587f4 2017 #define OPAMP1_CSR_TCMEN ((uint32_t)0x00000080) /*!< Timer-Controlled Mux mode enable */
mbed_official 403:91a4bea587f4 2018 #define OPAMP1_CSR_VMSSEL ((uint32_t)0x00000100) /*!< Inverting input secondary selection */
mbed_official 403:91a4bea587f4 2019 #define OPAMP1_CSR_VPSSEL ((uint32_t)0x00000600) /*!< Non inverting input secondary selection */
mbed_official 403:91a4bea587f4 2020 #define OPAMP1_CSR_VPSSEL_0 ((uint32_t)0x00000200) /*!< Bit 0 */
mbed_official 403:91a4bea587f4 2021 #define OPAMP1_CSR_VPSSEL_1 ((uint32_t)0x00000400) /*!< Bit 1 */
mbed_official 403:91a4bea587f4 2022 #define OPAMP1_CSR_CALON ((uint32_t)0x00000800) /*!< Calibration mode enable */
mbed_official 403:91a4bea587f4 2023 #define OPAMP1_CSR_CALSEL ((uint32_t)0x00003000) /*!< Calibration selection */
mbed_official 403:91a4bea587f4 2024 #define OPAMP1_CSR_CALSEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
mbed_official 403:91a4bea587f4 2025 #define OPAMP1_CSR_CALSEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
mbed_official 403:91a4bea587f4 2026 #define OPAMP1_CSR_PGGAIN ((uint32_t)0x0003C000) /*!< Gain in PGA mode */
mbed_official 403:91a4bea587f4 2027 #define OPAMP1_CSR_PGGAIN_0 ((uint32_t)0x00004000) /*!< Bit 0 */
mbed_official 403:91a4bea587f4 2028 #define OPAMP1_CSR_PGGAIN_1 ((uint32_t)0x00008000) /*!< Bit 1 */
mbed_official 403:91a4bea587f4 2029 #define OPAMP1_CSR_PGGAIN_2 ((uint32_t)0x00010000) /*!< Bit 2 */
mbed_official 403:91a4bea587f4 2030 #define OPAMP1_CSR_PGGAIN_3 ((uint32_t)0x00020000) /*!< Bit 3 */
mbed_official 403:91a4bea587f4 2031 #define OPAMP1_CSR_USERTRIM ((uint32_t)0x00040000) /*!< User trimming enable */
mbed_official 403:91a4bea587f4 2032 #define OPAMP1_CSR_TRIMOFFSETP ((uint32_t)0x00F80000) /*!< Offset trimming value (PMOS) */
mbed_official 403:91a4bea587f4 2033 #define OPAMP1_CSR_TRIMOFFSETN ((uint32_t)0x1F000000) /*!< Offset trimming value (NMOS) */
mbed_official 403:91a4bea587f4 2034 #define OPAMP1_CSR_TSTREF ((uint32_t)0x20000000) /*!< It enables the switch to put out the internal reference */
mbed_official 403:91a4bea587f4 2035 #define OPAMP1_CSR_OUTCAL ((uint32_t)0x40000000) /*!< OPAMP ouput status flag */
mbed_official 403:91a4bea587f4 2036 #define OPAMP1_CSR_LOCK ((uint32_t)0x80000000) /*!< OPAMP lock */
mbed_official 403:91a4bea587f4 2037
mbed_official 403:91a4bea587f4 2038 /********************* Bit definition for OPAMP2_CSR register ***************/
mbed_official 403:91a4bea587f4 2039 #define OPAMP2_CSR_OPAMP2EN ((uint32_t)0x00000001) /*!< OPAMP2 enable */
mbed_official 403:91a4bea587f4 2040 #define OPAMP2_CSR_FORCEVP ((uint32_t)0x00000002) /*!< Connect the internal references to the plus input of the OPAMPX */
mbed_official 403:91a4bea587f4 2041 #define OPAMP2_CSR_VPSEL ((uint32_t)0x0000000C) /*!< Non inverting input selection */
mbed_official 403:91a4bea587f4 2042 #define OPAMP2_CSR_VPSEL_0 ((uint32_t)0x00000004) /*!< Bit 0 */
mbed_official 403:91a4bea587f4 2043 #define OPAMP2_CSR_VPSEL_1 ((uint32_t)0x00000008) /*!< Bit 1 */
mbed_official 403:91a4bea587f4 2044 #define OPAMP2_CSR_VMSEL ((uint32_t)0x00000060) /*!< Inverting input selection */
mbed_official 403:91a4bea587f4 2045 #define OPAMP2_CSR_VMSEL_0 ((uint32_t)0x00000020) /*!< Bit 0 */
mbed_official 403:91a4bea587f4 2046 #define OPAMP2_CSR_VMSEL_1 ((uint32_t)0x00000040) /*!< Bit 1 */
mbed_official 403:91a4bea587f4 2047 #define OPAMP2_CSR_TCMEN ((uint32_t)0x00000080) /*!< Timer-Controlled Mux mode enable */
mbed_official 403:91a4bea587f4 2048 #define OPAMP2_CSR_VMSSEL ((uint32_t)0x00000100) /*!< Inverting input secondary selection */
mbed_official 403:91a4bea587f4 2049 #define OPAMP2_CSR_VPSSEL ((uint32_t)0x00000600) /*!< Non inverting input secondary selection */
mbed_official 403:91a4bea587f4 2050 #define OPAMP2_CSR_VPSSEL_0 ((uint32_t)0x00000200) /*!< Bit 0 */
mbed_official 403:91a4bea587f4 2051 #define OPAMP2_CSR_VPSSEL_1 ((uint32_t)0x00000400) /*!< Bit 1 */
mbed_official 403:91a4bea587f4 2052 #define OPAMP2_CSR_CALON ((uint32_t)0x00000800) /*!< Calibration mode enable */
mbed_official 403:91a4bea587f4 2053 #define OPAMP2_CSR_CALSEL ((uint32_t)0x00003000) /*!< Calibration selection */
mbed_official 403:91a4bea587f4 2054 #define OPAMP2_CSR_CALSEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
mbed_official 403:91a4bea587f4 2055 #define OPAMP2_CSR_CALSEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
mbed_official 403:91a4bea587f4 2056 #define OPAMP2_CSR_PGGAIN ((uint32_t)0x0003C000) /*!< Gain in PGA mode */
mbed_official 403:91a4bea587f4 2057 #define OPAMP2_CSR_PGGAIN_0 ((uint32_t)0x00004000) /*!< Bit 0 */
mbed_official 403:91a4bea587f4 2058 #define OPAMP2_CSR_PGGAIN_1 ((uint32_t)0x00008000) /*!< Bit 1 */
mbed_official 403:91a4bea587f4 2059 #define OPAMP2_CSR_PGGAIN_2 ((uint32_t)0x00010000) /*!< Bit 2 */
mbed_official 403:91a4bea587f4 2060 #define OPAMP2_CSR_PGGAIN_3 ((uint32_t)0x00020000) /*!< Bit 3 */
mbed_official 403:91a4bea587f4 2061 #define OPAMP2_CSR_USERTRIM ((uint32_t)0x00040000) /*!< User trimming enable */
mbed_official 403:91a4bea587f4 2062 #define OPAMP2_CSR_TRIMOFFSETP ((uint32_t)0x00F80000) /*!< Offset trimming value (PMOS) */
mbed_official 403:91a4bea587f4 2063 #define OPAMP2_CSR_TRIMOFFSETN ((uint32_t)0x1F000000) /*!< Offset trimming value (NMOS) */
mbed_official 403:91a4bea587f4 2064 #define OPAMP2_CSR_TSTREF ((uint32_t)0x20000000) /*!< It enables the switch to put out the internal reference */
mbed_official 403:91a4bea587f4 2065 #define OPAMP2_CSR_OUTCAL ((uint32_t)0x40000000) /*!< OPAMP ouput status flag */
mbed_official 403:91a4bea587f4 2066 #define OPAMP2_CSR_LOCK ((uint32_t)0x80000000) /*!< OPAMP lock */
mbed_official 403:91a4bea587f4 2067
mbed_official 403:91a4bea587f4 2068 /********************* Bit definition for OPAMP3_CSR register ***************/
mbed_official 403:91a4bea587f4 2069 #define OPAMP3_CSR_OPAMP3EN ((uint32_t)0x00000001) /*!< OPAMP3 enable */
mbed_official 403:91a4bea587f4 2070 #define OPAMP3_CSR_FORCEVP ((uint32_t)0x00000002) /*!< Connect the internal references to the plus input of the OPAMPX */
mbed_official 403:91a4bea587f4 2071 #define OPAMP3_CSR_VPSEL ((uint32_t)0x0000000C) /*!< Non inverting input selection */
mbed_official 403:91a4bea587f4 2072 #define OPAMP3_CSR_VPSEL_0 ((uint32_t)0x00000004) /*!< Bit 0 */
mbed_official 403:91a4bea587f4 2073 #define OPAMP3_CSR_VPSEL_1 ((uint32_t)0x00000008) /*!< Bit 1 */
mbed_official 403:91a4bea587f4 2074 #define OPAMP3_CSR_VMSEL ((uint32_t)0x00000060) /*!< Inverting input selection */
mbed_official 403:91a4bea587f4 2075 #define OPAMP3_CSR_VMSEL_0 ((uint32_t)0x00000020) /*!< Bit 0 */
mbed_official 403:91a4bea587f4 2076 #define OPAMP3_CSR_VMSEL_1 ((uint32_t)0x00000040) /*!< Bit 1 */
mbed_official 403:91a4bea587f4 2077 #define OPAMP3_CSR_TCMEN ((uint32_t)0x00000080) /*!< Timer-Controlled Mux mode enable */
mbed_official 403:91a4bea587f4 2078 #define OPAMP3_CSR_VMSSEL ((uint32_t)0x00000100) /*!< Inverting input secondary selection */
mbed_official 403:91a4bea587f4 2079 #define OPAMP3_CSR_VPSSEL ((uint32_t)0x00000600) /*!< Non inverting input secondary selection */
mbed_official 403:91a4bea587f4 2080 #define OPAMP3_CSR_VPSSEL_0 ((uint32_t)0x00000200) /*!< Bit 0 */
mbed_official 403:91a4bea587f4 2081 #define OPAMP3_CSR_VPSSEL_1 ((uint32_t)0x00000400) /*!< Bit 1 */
mbed_official 403:91a4bea587f4 2082 #define OPAMP3_CSR_CALON ((uint32_t)0x00000800) /*!< Calibration mode enable */
mbed_official 403:91a4bea587f4 2083 #define OPAMP3_CSR_CALSEL ((uint32_t)0x00003000) /*!< Calibration selection */
mbed_official 403:91a4bea587f4 2084 #define OPAMP3_CSR_CALSEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
mbed_official 403:91a4bea587f4 2085 #define OPAMP3_CSR_CALSEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
mbed_official 403:91a4bea587f4 2086 #define OPAMP3_CSR_PGGAIN ((uint32_t)0x0003C000) /*!< Gain in PGA mode */
mbed_official 403:91a4bea587f4 2087 #define OPAMP3_CSR_PGGAIN_0 ((uint32_t)0x00004000) /*!< Bit 0 */
mbed_official 403:91a4bea587f4 2088 #define OPAMP3_CSR_PGGAIN_1 ((uint32_t)0x00008000) /*!< Bit 1 */
mbed_official 403:91a4bea587f4 2089 #define OPAMP3_CSR_PGGAIN_2 ((uint32_t)0x00010000) /*!< Bit 2 */
mbed_official 403:91a4bea587f4 2090 #define OPAMP3_CSR_PGGAIN_3 ((uint32_t)0x00020000) /*!< Bit 3 */
mbed_official 403:91a4bea587f4 2091 #define OPAMP3_CSR_USERTRIM ((uint32_t)0x00040000) /*!< User trimming enable */
mbed_official 403:91a4bea587f4 2092 #define OPAMP3_CSR_TRIMOFFSETP ((uint32_t)0x00F80000) /*!< Offset trimming value (PMOS) */
mbed_official 403:91a4bea587f4 2093 #define OPAMP3_CSR_TRIMOFFSETN ((uint32_t)0x1F000000) /*!< Offset trimming value (NMOS) */
mbed_official 403:91a4bea587f4 2094 #define OPAMP3_CSR_TSTREF ((uint32_t)0x20000000) /*!< It enables the switch to put out the internal reference */
mbed_official 403:91a4bea587f4 2095 #define OPAMP3_CSR_OUTCAL ((uint32_t)0x40000000) /*!< OPAMP ouput status flag */
mbed_official 403:91a4bea587f4 2096 #define OPAMP3_CSR_LOCK ((uint32_t)0x80000000) /*!< OPAMP lock */
mbed_official 403:91a4bea587f4 2097
mbed_official 403:91a4bea587f4 2098 /********************* Bit definition for OPAMP4_CSR register ***************/
mbed_official 403:91a4bea587f4 2099 #define OPAMP4_CSR_OPAMP4EN ((uint32_t)0x00000001) /*!< OPAMP4 enable */
mbed_official 403:91a4bea587f4 2100 #define OPAMP4_CSR_FORCEVP ((uint32_t)0x00000002) /*!< Connect the internal references to the plus input of the OPAMPX */
mbed_official 403:91a4bea587f4 2101 #define OPAMP4_CSR_VPSEL ((uint32_t)0x0000000C) /*!< Non inverting input selection */
mbed_official 403:91a4bea587f4 2102 #define OPAMP4_CSR_VPSEL_0 ((uint32_t)0x00000004) /*!< Bit 0 */
mbed_official 403:91a4bea587f4 2103 #define OPAMP4_CSR_VPSEL_1 ((uint32_t)0x00000008) /*!< Bit 1 */
mbed_official 403:91a4bea587f4 2104 #define OPAMP4_CSR_VMSEL ((uint32_t)0x00000060) /*!< Inverting input selection */
mbed_official 403:91a4bea587f4 2105 #define OPAMP4_CSR_VMSEL_0 ((uint32_t)0x00000020) /*!< Bit 0 */
mbed_official 403:91a4bea587f4 2106 #define OPAMP4_CSR_VMSEL_1 ((uint32_t)0x00000040) /*!< Bit 1 */
mbed_official 403:91a4bea587f4 2107 #define OPAMP4_CSR_TCMEN ((uint32_t)0x00000080) /*!< Timer-Controlled Mux mode enable */
mbed_official 403:91a4bea587f4 2108 #define OPAMP4_CSR_VMSSEL ((uint32_t)0x00000100) /*!< Inverting input secondary selection */
mbed_official 403:91a4bea587f4 2109 #define OPAMP4_CSR_VPSSEL ((uint32_t)0x00000600) /*!< Non inverting input secondary selection */
mbed_official 403:91a4bea587f4 2110 #define OPAMP4_CSR_VPSSEL_0 ((uint32_t)0x00000200) /*!< Bit 0 */
mbed_official 403:91a4bea587f4 2111 #define OPAMP4_CSR_VPSSEL_1 ((uint32_t)0x00000400) /*!< Bit 1 */
mbed_official 403:91a4bea587f4 2112 #define OPAMP4_CSR_CALON ((uint32_t)0x00000800) /*!< Calibration mode enable */
mbed_official 403:91a4bea587f4 2113 #define OPAMP4_CSR_CALSEL ((uint32_t)0x00003000) /*!< Calibration selection */
mbed_official 403:91a4bea587f4 2114 #define OPAMP4_CSR_CALSEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
mbed_official 403:91a4bea587f4 2115 #define OPAMP4_CSR_CALSEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
mbed_official 403:91a4bea587f4 2116 #define OPAMP4_CSR_PGGAIN ((uint32_t)0x0003C000) /*!< Gain in PGA mode */
mbed_official 403:91a4bea587f4 2117 #define OPAMP4_CSR_PGGAIN_0 ((uint32_t)0x00004000) /*!< Bit 0 */
mbed_official 403:91a4bea587f4 2118 #define OPAMP4_CSR_PGGAIN_1 ((uint32_t)0x00008000) /*!< Bit 1 */
mbed_official 403:91a4bea587f4 2119 #define OPAMP4_CSR_PGGAIN_2 ((uint32_t)0x00010000) /*!< Bit 2 */
mbed_official 403:91a4bea587f4 2120 #define OPAMP4_CSR_PGGAIN_3 ((uint32_t)0x00020000) /*!< Bit 3 */
mbed_official 403:91a4bea587f4 2121 #define OPAMP4_CSR_USERTRIM ((uint32_t)0x00040000) /*!< User trimming enable */
mbed_official 403:91a4bea587f4 2122 #define OPAMP4_CSR_TRIMOFFSETP ((uint32_t)0x00F80000) /*!< Offset trimming value (PMOS) */
mbed_official 403:91a4bea587f4 2123 #define OPAMP4_CSR_TRIMOFFSETN ((uint32_t)0x1F000000) /*!< Offset trimming value (NMOS) */
mbed_official 403:91a4bea587f4 2124 #define OPAMP4_CSR_TSTREF ((uint32_t)0x20000000) /*!< It enables the switch to put out the internal reference */
mbed_official 403:91a4bea587f4 2125 #define OPAMP4_CSR_OUTCAL ((uint32_t)0x40000000) /*!< OPAMP ouput status flag */
mbed_official 403:91a4bea587f4 2126 #define OPAMP4_CSR_LOCK ((uint32_t)0x80000000) /*!< OPAMP lock */
mbed_official 403:91a4bea587f4 2127
mbed_official 403:91a4bea587f4 2128 /********************* Bit definition for OPAMPx_CSR register ***************/
mbed_official 403:91a4bea587f4 2129 #define OPAMP_CSR_OPAMPxEN ((uint32_t)0x00000001) /*!< OPAMP enable */
mbed_official 403:91a4bea587f4 2130 #define OPAMP_CSR_FORCEVP ((uint32_t)0x00000002) /*!< Connect the internal references to the plus input of the OPAMPX */
mbed_official 403:91a4bea587f4 2131 #define OPAMP_CSR_VPSEL ((uint32_t)0x0000000C) /*!< Non inverting input selection */
mbed_official 403:91a4bea587f4 2132 #define OPAMP_CSR_VPSEL_0 ((uint32_t)0x00000004) /*!< Bit 0 */
mbed_official 403:91a4bea587f4 2133 #define OPAMP_CSR_VPSEL_1 ((uint32_t)0x00000008) /*!< Bit 1 */
mbed_official 403:91a4bea587f4 2134 #define OPAMP_CSR_VMSEL ((uint32_t)0x00000060) /*!< Inverting input selection */
mbed_official 403:91a4bea587f4 2135 #define OPAMP_CSR_VMSEL_0 ((uint32_t)0x00000020) /*!< Bit 0 */
mbed_official 403:91a4bea587f4 2136 #define OPAMP_CSR_VMSEL_1 ((uint32_t)0x00000040) /*!< Bit 1 */
mbed_official 403:91a4bea587f4 2137 #define OPAMP_CSR_TCMEN ((uint32_t)0x00000080) /*!< Timer-Controlled Mux mode enable */
mbed_official 403:91a4bea587f4 2138 #define OPAMP_CSR_VMSSEL ((uint32_t)0x00000100) /*!< Inverting input secondary selection */
mbed_official 403:91a4bea587f4 2139 #define OPAMP_CSR_VPSSEL ((uint32_t)0x00000600) /*!< Non inverting input secondary selection */
mbed_official 403:91a4bea587f4 2140 #define OPAMP_CSR_VPSSEL_0 ((uint32_t)0x00000200) /*!< Bit 0 */
mbed_official 403:91a4bea587f4 2141 #define OPAMP_CSR_VPSSEL_1 ((uint32_t)0x00000400) /*!< Bit 1 */
mbed_official 403:91a4bea587f4 2142 #define OPAMP_CSR_CALON ((uint32_t)0x00000800) /*!< Calibration mode enable */
mbed_official 403:91a4bea587f4 2143 #define OPAMP_CSR_CALSEL ((uint32_t)0x00003000) /*!< Calibration selection */
mbed_official 403:91a4bea587f4 2144 #define OPAMP_CSR_CALSEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
mbed_official 403:91a4bea587f4 2145 #define OPAMP_CSR_CALSEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
mbed_official 403:91a4bea587f4 2146 #define OPAMP_CSR_PGGAIN ((uint32_t)0x0003C000) /*!< Gain in PGA mode */
mbed_official 403:91a4bea587f4 2147 #define OPAMP_CSR_PGGAIN_0 ((uint32_t)0x00004000) /*!< Bit 0 */
mbed_official 403:91a4bea587f4 2148 #define OPAMP_CSR_PGGAIN_1 ((uint32_t)0x00008000) /*!< Bit 1 */
mbed_official 403:91a4bea587f4 2149 #define OPAMP_CSR_PGGAIN_2 ((uint32_t)0x00010000) /*!< Bit 2 */
mbed_official 403:91a4bea587f4 2150 #define OPAMP_CSR_PGGAIN_3 ((uint32_t)0x00020000) /*!< Bit 3 */
mbed_official 403:91a4bea587f4 2151 #define OPAMP_CSR_USERTRIM ((uint32_t)0x00040000) /*!< User trimming enable */
mbed_official 403:91a4bea587f4 2152 #define OPAMP_CSR_TRIMOFFSETP ((uint32_t)0x00F80000) /*!< Offset trimming value (PMOS) */
mbed_official 403:91a4bea587f4 2153 #define OPAMP_CSR_TRIMOFFSETN ((uint32_t)0x1F000000) /*!< Offset trimming value (NMOS) */
mbed_official 403:91a4bea587f4 2154 #define OPAMP_CSR_TSTREF ((uint32_t)0x20000000) /*!< It enables the switch to put out the internal reference */
mbed_official 403:91a4bea587f4 2155 #define OPAMP_CSR_OUTCAL ((uint32_t)0x40000000) /*!< OPAMP ouput status flag */
mbed_official 403:91a4bea587f4 2156 #define OPAMP_CSR_LOCK ((uint32_t)0x80000000) /*!< OPAMP lock */
mbed_official 403:91a4bea587f4 2157
mbed_official 403:91a4bea587f4 2158 /******************************************************************************/
mbed_official 403:91a4bea587f4 2159 /* */
mbed_official 403:91a4bea587f4 2160 /* Controller Area Network (CAN ) */
mbed_official 403:91a4bea587f4 2161 /* */
mbed_official 403:91a4bea587f4 2162 /******************************************************************************/
mbed_official 403:91a4bea587f4 2163 /******************* Bit definition for CAN_MCR register ********************/
mbed_official 403:91a4bea587f4 2164 #define CAN_MCR_INRQ ((uint32_t)0x00000001) /*!<Initialization Request */
mbed_official 403:91a4bea587f4 2165 #define CAN_MCR_SLEEP ((uint32_t)0x00000002) /*!<Sleep Mode Request */
mbed_official 403:91a4bea587f4 2166 #define CAN_MCR_TXFP ((uint32_t)0x00000004) /*!<Transmit FIFO Priority */
mbed_official 403:91a4bea587f4 2167 #define CAN_MCR_RFLM ((uint32_t)0x00000008) /*!<Receive FIFO Locked Mode */
mbed_official 403:91a4bea587f4 2168 #define CAN_MCR_NART ((uint32_t)0x00000010) /*!<No Automatic Retransmission */
mbed_official 403:91a4bea587f4 2169 #define CAN_MCR_AWUM ((uint32_t)0x00000020) /*!<Automatic Wakeup Mode */
mbed_official 403:91a4bea587f4 2170 #define CAN_MCR_ABOM ((uint32_t)0x00000040) /*!<Automatic Bus-Off Management */
mbed_official 403:91a4bea587f4 2171 #define CAN_MCR_TTCM ((uint32_t)0x00000080) /*!<Time Triggered Communication Mode */
mbed_official 403:91a4bea587f4 2172 #define CAN_MCR_RESET ((uint32_t)0x00008000) /*!<bxCAN software master reset */
mbed_official 403:91a4bea587f4 2173
mbed_official 403:91a4bea587f4 2174 /******************* Bit definition for CAN_MSR register ********************/
mbed_official 403:91a4bea587f4 2175 #define CAN_MSR_INAK ((uint32_t)0x00000001) /*!<Initialization Acknowledge */
mbed_official 403:91a4bea587f4 2176 #define CAN_MSR_SLAK ((uint32_t)0x00000002) /*!<Sleep Acknowledge */
mbed_official 403:91a4bea587f4 2177 #define CAN_MSR_ERRI ((uint32_t)0x00000004) /*!<Error Interrupt */
mbed_official 403:91a4bea587f4 2178 #define CAN_MSR_WKUI ((uint32_t)0x00000008) /*!<Wakeup Interrupt */
mbed_official 403:91a4bea587f4 2179 #define CAN_MSR_SLAKI ((uint32_t)0x00000010) /*!<Sleep Acknowledge Interrupt */
mbed_official 403:91a4bea587f4 2180 #define CAN_MSR_TXM ((uint32_t)0x00000100) /*!<Transmit Mode */
mbed_official 403:91a4bea587f4 2181 #define CAN_MSR_RXM ((uint32_t)0x00000200) /*!<Receive Mode */
mbed_official 403:91a4bea587f4 2182 #define CAN_MSR_SAMP ((uint32_t)0x00000400) /*!<Last Sample Point */
mbed_official 403:91a4bea587f4 2183 #define CAN_MSR_RX ((uint32_t)0x00000800) /*!<CAN Rx Signal */
mbed_official 403:91a4bea587f4 2184
mbed_official 403:91a4bea587f4 2185 /******************* Bit definition for CAN_TSR register ********************/
mbed_official 403:91a4bea587f4 2186 #define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /*!<Request Completed Mailbox0 */
mbed_official 403:91a4bea587f4 2187 #define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /*!<Transmission OK of Mailbox0 */
mbed_official 403:91a4bea587f4 2188 #define CAN_TSR_ALST0 ((uint32_t)0x00000004) /*!<Arbitration Lost for Mailbox0 */
mbed_official 403:91a4bea587f4 2189 #define CAN_TSR_TERR0 ((uint32_t)0x00000008) /*!<Transmission Error of Mailbox0 */
mbed_official 403:91a4bea587f4 2190 #define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /*!<Abort Request for Mailbox0 */
mbed_official 403:91a4bea587f4 2191 #define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /*!<Request Completed Mailbox1 */
mbed_official 403:91a4bea587f4 2192 #define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /*!<Transmission OK of Mailbox1 */
mbed_official 403:91a4bea587f4 2193 #define CAN_TSR_ALST1 ((uint32_t)0x00000400) /*!<Arbitration Lost for Mailbox1 */
mbed_official 403:91a4bea587f4 2194 #define CAN_TSR_TERR1 ((uint32_t)0x00000800) /*!<Transmission Error of Mailbox1 */
mbed_official 403:91a4bea587f4 2195 #define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /*!<Abort Request for Mailbox 1 */
mbed_official 403:91a4bea587f4 2196 #define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /*!<Request Completed Mailbox2 */
mbed_official 403:91a4bea587f4 2197 #define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /*!<Transmission OK of Mailbox 2 */
mbed_official 403:91a4bea587f4 2198 #define CAN_TSR_ALST2 ((uint32_t)0x00040000) /*!<Arbitration Lost for mailbox 2 */
mbed_official 403:91a4bea587f4 2199 #define CAN_TSR_TERR2 ((uint32_t)0x00080000) /*!<Transmission Error of Mailbox 2 */
mbed_official 403:91a4bea587f4 2200 #define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /*!<Abort Request for Mailbox 2 */
mbed_official 403:91a4bea587f4 2201 #define CAN_TSR_CODE ((uint32_t)0x03000000) /*!<Mailbox Code */
mbed_official 403:91a4bea587f4 2202
mbed_official 403:91a4bea587f4 2203 #define CAN_TSR_TME ((uint32_t)0x1C000000) /*!<TME[2:0] bits */
mbed_official 403:91a4bea587f4 2204 #define CAN_TSR_TME0 ((uint32_t)0x04000000) /*!<Transmit Mailbox 0 Empty */
mbed_official 403:91a4bea587f4 2205 #define CAN_TSR_TME1 ((uint32_t)0x08000000) /*!<Transmit Mailbox 1 Empty */
mbed_official 403:91a4bea587f4 2206 #define CAN_TSR_TME2 ((uint32_t)0x10000000) /*!<Transmit Mailbox 2 Empty */
mbed_official 403:91a4bea587f4 2207
mbed_official 403:91a4bea587f4 2208 #define CAN_TSR_LOW ((uint32_t)0xE0000000) /*!<LOW[2:0] bits */
mbed_official 403:91a4bea587f4 2209 #define CAN_TSR_LOW0 ((uint32_t)0x20000000) /*!<Lowest Priority Flag for Mailbox 0 */
mbed_official 403:91a4bea587f4 2210 #define CAN_TSR_LOW1 ((uint32_t)0x40000000) /*!<Lowest Priority Flag for Mailbox 1 */
mbed_official 403:91a4bea587f4 2211 #define CAN_TSR_LOW2 ((uint32_t)0x80000000) /*!<Lowest Priority Flag for Mailbox 2 */
mbed_official 403:91a4bea587f4 2212
mbed_official 403:91a4bea587f4 2213 /******************* Bit definition for CAN_RF0R register *******************/
mbed_official 403:91a4bea587f4 2214 #define CAN_RF0R_FMP0 ((uint32_t)0x00000003) /*!<FIFO 0 Message Pending */
mbed_official 403:91a4bea587f4 2215 #define CAN_RF0R_FULL0 ((uint32_t)0x00000008) /*!<FIFO 0 Full */
mbed_official 403:91a4bea587f4 2216 #define CAN_RF0R_FOVR0 ((uint32_t)0x00000010) /*!<FIFO 0 Overrun */
mbed_official 403:91a4bea587f4 2217 #define CAN_RF0R_RFOM0 ((uint32_t)0x00000020) /*!<Release FIFO 0 Output Mailbox */
mbed_official 403:91a4bea587f4 2218
mbed_official 403:91a4bea587f4 2219 /******************* Bit definition for CAN_RF1R register *******************/
mbed_official 403:91a4bea587f4 2220 #define CAN_RF1R_FMP1 ((uint32_t)0x00000003) /*!<FIFO 1 Message Pending */
mbed_official 403:91a4bea587f4 2221 #define CAN_RF1R_FULL1 ((uint32_t)0x00000008) /*!<FIFO 1 Full */
mbed_official 403:91a4bea587f4 2222 #define CAN_RF1R_FOVR1 ((uint32_t)0x00000010) /*!<FIFO 1 Overrun */
mbed_official 403:91a4bea587f4 2223 #define CAN_RF1R_RFOM1 ((uint32_t)0x00000020) /*!<Release FIFO 1 Output Mailbox */
mbed_official 403:91a4bea587f4 2224
mbed_official 403:91a4bea587f4 2225 /******************** Bit definition for CAN_IER register *******************/
mbed_official 403:91a4bea587f4 2226 #define CAN_IER_TMEIE ((uint32_t)0x00000001) /*!<Transmit Mailbox Empty Interrupt Enable */
mbed_official 403:91a4bea587f4 2227 #define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /*!<FIFO Message Pending Interrupt Enable */
mbed_official 403:91a4bea587f4 2228 #define CAN_IER_FFIE0 ((uint32_t)0x00000004) /*!<FIFO Full Interrupt Enable */
mbed_official 403:91a4bea587f4 2229 #define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /*!<FIFO Overrun Interrupt Enable */
mbed_official 403:91a4bea587f4 2230 #define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /*!<FIFO Message Pending Interrupt Enable */
mbed_official 403:91a4bea587f4 2231 #define CAN_IER_FFIE1 ((uint32_t)0x00000020) /*!<FIFO Full Interrupt Enable */
mbed_official 403:91a4bea587f4 2232 #define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /*!<FIFO Overrun Interrupt Enable */
mbed_official 403:91a4bea587f4 2233 #define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!<Error Warning Interrupt Enable */
mbed_official 403:91a4bea587f4 2234 #define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!<Error Passive Interrupt Enable */
mbed_official 403:91a4bea587f4 2235 #define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!<Bus-Off Interrupt Enable */
mbed_official 403:91a4bea587f4 2236 #define CAN_IER_LECIE ((uint32_t)0x00000800) /*!<Last Error Code Interrupt Enable */
mbed_official 403:91a4bea587f4 2237 #define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!<Error Interrupt Enable */
mbed_official 403:91a4bea587f4 2238 #define CAN_IER_WKUIE ((uint32_t)0x00010000) /*!<Wakeup Interrupt Enable */
mbed_official 403:91a4bea587f4 2239 #define CAN_IER_SLKIE ((uint32_t)0x00020000) /*!<Sleep Interrupt Enable */
mbed_official 403:91a4bea587f4 2240
mbed_official 403:91a4bea587f4 2241 /******************** Bit definition for CAN_ESR register *******************/
mbed_official 403:91a4bea587f4 2242 #define CAN_ESR_EWGF ((uint32_t)0x00000001) /*!<Error Warning Flag */
mbed_official 403:91a4bea587f4 2243 #define CAN_ESR_EPVF ((uint32_t)0x00000002) /*!<Error Passive Flag */
mbed_official 403:91a4bea587f4 2244 #define CAN_ESR_BOFF ((uint32_t)0x00000004) /*!<Bus-Off Flag */
mbed_official 403:91a4bea587f4 2245
mbed_official 403:91a4bea587f4 2246 #define CAN_ESR_LEC ((uint32_t)0x00000070) /*!<LEC[2:0] bits (Last Error Code) */
mbed_official 403:91a4bea587f4 2247 #define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 403:91a4bea587f4 2248 #define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 403:91a4bea587f4 2249 #define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 403:91a4bea587f4 2250
mbed_official 403:91a4bea587f4 2251 #define CAN_ESR_TEC ((uint32_t)0x00FF0000) /*!<Least significant byte of the 9-bit Transmit Error Counter */
mbed_official 403:91a4bea587f4 2252 #define CAN_ESR_REC ((uint32_t)0xFF000000) /*!<Receive Error Counter */
mbed_official 403:91a4bea587f4 2253
mbed_official 403:91a4bea587f4 2254 /******************* Bit definition for CAN_BTR register ********************/
mbed_official 403:91a4bea587f4 2255 #define CAN_BTR_BRP ((uint32_t)0x000003FF) /*!<Baud Rate Prescaler */
mbed_official 403:91a4bea587f4 2256 #define CAN_BTR_TS1 ((uint32_t)0x000F0000) /*!<Time Segment 1 */
mbed_official 403:91a4bea587f4 2257 #define CAN_BTR_TS1_0 ((uint32_t)0x00010000) /*!<Time Segment 1 (Bit 0) */
mbed_official 403:91a4bea587f4 2258 #define CAN_BTR_TS1_1 ((uint32_t)0x00020000) /*!<Time Segment 1 (Bit 1) */
mbed_official 403:91a4bea587f4 2259 #define CAN_BTR_TS1_2 ((uint32_t)0x00040000) /*!<Time Segment 1 (Bit 2) */
mbed_official 403:91a4bea587f4 2260 #define CAN_BTR_TS1_3 ((uint32_t)0x00080000) /*!<Time Segment 1 (Bit 3) */
mbed_official 403:91a4bea587f4 2261 #define CAN_BTR_TS2 ((uint32_t)0x00700000) /*!<Time Segment 2 */
mbed_official 403:91a4bea587f4 2262 #define CAN_BTR_TS2_0 ((uint32_t)0x00100000) /*!<Time Segment 2 (Bit 0) */
mbed_official 403:91a4bea587f4 2263 #define CAN_BTR_TS2_1 ((uint32_t)0x00200000) /*!<Time Segment 2 (Bit 1) */
mbed_official 403:91a4bea587f4 2264 #define CAN_BTR_TS2_2 ((uint32_t)0x00400000) /*!<Time Segment 2 (Bit 2) */
mbed_official 403:91a4bea587f4 2265 #define CAN_BTR_SJW ((uint32_t)0x03000000) /*!<Resynchronization Jump Width */
mbed_official 403:91a4bea587f4 2266 #define CAN_BTR_SJW_0 ((uint32_t)0x01000000) /*!<Resynchronization Jump Width (Bit 0) */
mbed_official 403:91a4bea587f4 2267 #define CAN_BTR_SJW_1 ((uint32_t)0x02000000) /*!<Resynchronization Jump Width (Bit 1) */
mbed_official 403:91a4bea587f4 2268 #define CAN_BTR_LBKM ((uint32_t)0x40000000) /*!<Loop Back Mode (Debug) */
mbed_official 403:91a4bea587f4 2269 #define CAN_BTR_SILM ((uint32_t)0x80000000) /*!<Silent Mode */
mbed_official 403:91a4bea587f4 2270
mbed_official 403:91a4bea587f4 2271 /*!<Mailbox registers */
mbed_official 403:91a4bea587f4 2272 /****************** Bit definition for CAN_TI0R register ********************/
mbed_official 403:91a4bea587f4 2273 #define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
mbed_official 403:91a4bea587f4 2274 #define CAN_TI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
mbed_official 403:91a4bea587f4 2275 #define CAN_TI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
mbed_official 403:91a4bea587f4 2276 #define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
mbed_official 403:91a4bea587f4 2277 #define CAN_TI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
mbed_official 403:91a4bea587f4 2278
mbed_official 403:91a4bea587f4 2279 /****************** Bit definition for CAN_TDT0R register *******************/
mbed_official 403:91a4bea587f4 2280 #define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
mbed_official 403:91a4bea587f4 2281 #define CAN_TDT0R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
mbed_official 403:91a4bea587f4 2282 #define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
mbed_official 403:91a4bea587f4 2283
mbed_official 403:91a4bea587f4 2284 /****************** Bit definition for CAN_TDL0R register *******************/
mbed_official 403:91a4bea587f4 2285 #define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
mbed_official 403:91a4bea587f4 2286 #define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
mbed_official 403:91a4bea587f4 2287 #define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
mbed_official 403:91a4bea587f4 2288 #define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
mbed_official 403:91a4bea587f4 2289
mbed_official 403:91a4bea587f4 2290 /****************** Bit definition for CAN_TDH0R register *******************/
mbed_official 403:91a4bea587f4 2291 #define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
mbed_official 403:91a4bea587f4 2292 #define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
mbed_official 403:91a4bea587f4 2293 #define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
mbed_official 403:91a4bea587f4 2294 #define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
mbed_official 403:91a4bea587f4 2295
mbed_official 403:91a4bea587f4 2296 /******************* Bit definition for CAN_TI1R register *******************/
mbed_official 403:91a4bea587f4 2297 #define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
mbed_official 403:91a4bea587f4 2298 #define CAN_TI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
mbed_official 403:91a4bea587f4 2299 #define CAN_TI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
mbed_official 403:91a4bea587f4 2300 #define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
mbed_official 403:91a4bea587f4 2301 #define CAN_TI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
mbed_official 403:91a4bea587f4 2302
mbed_official 403:91a4bea587f4 2303 /******************* Bit definition for CAN_TDT1R register ******************/
mbed_official 403:91a4bea587f4 2304 #define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
mbed_official 403:91a4bea587f4 2305 #define CAN_TDT1R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
mbed_official 403:91a4bea587f4 2306 #define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
mbed_official 403:91a4bea587f4 2307
mbed_official 403:91a4bea587f4 2308 /******************* Bit definition for CAN_TDL1R register ******************/
mbed_official 403:91a4bea587f4 2309 #define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
mbed_official 403:91a4bea587f4 2310 #define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
mbed_official 403:91a4bea587f4 2311 #define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
mbed_official 403:91a4bea587f4 2312 #define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
mbed_official 403:91a4bea587f4 2313
mbed_official 403:91a4bea587f4 2314 /******************* Bit definition for CAN_TDH1R register ******************/
mbed_official 403:91a4bea587f4 2315 #define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
mbed_official 403:91a4bea587f4 2316 #define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
mbed_official 403:91a4bea587f4 2317 #define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
mbed_official 403:91a4bea587f4 2318 #define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
mbed_official 403:91a4bea587f4 2319
mbed_official 403:91a4bea587f4 2320 /******************* Bit definition for CAN_TI2R register *******************/
mbed_official 403:91a4bea587f4 2321 #define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
mbed_official 403:91a4bea587f4 2322 #define CAN_TI2R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
mbed_official 403:91a4bea587f4 2323 #define CAN_TI2R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
mbed_official 403:91a4bea587f4 2324 #define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
mbed_official 403:91a4bea587f4 2325 #define CAN_TI2R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
mbed_official 403:91a4bea587f4 2326
mbed_official 403:91a4bea587f4 2327 /******************* Bit definition for CAN_TDT2R register ******************/
mbed_official 403:91a4bea587f4 2328 #define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
mbed_official 403:91a4bea587f4 2329 #define CAN_TDT2R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
mbed_official 403:91a4bea587f4 2330 #define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
mbed_official 403:91a4bea587f4 2331
mbed_official 403:91a4bea587f4 2332 /******************* Bit definition for CAN_TDL2R register ******************/
mbed_official 403:91a4bea587f4 2333 #define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
mbed_official 403:91a4bea587f4 2334 #define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
mbed_official 403:91a4bea587f4 2335 #define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
mbed_official 403:91a4bea587f4 2336 #define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
mbed_official 403:91a4bea587f4 2337
mbed_official 403:91a4bea587f4 2338 /******************* Bit definition for CAN_TDH2R register ******************/
mbed_official 403:91a4bea587f4 2339 #define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
mbed_official 403:91a4bea587f4 2340 #define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
mbed_official 403:91a4bea587f4 2341 #define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
mbed_official 403:91a4bea587f4 2342 #define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
mbed_official 403:91a4bea587f4 2343
mbed_official 403:91a4bea587f4 2344 /******************* Bit definition for CAN_RI0R register *******************/
mbed_official 403:91a4bea587f4 2345 #define CAN_RI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
mbed_official 403:91a4bea587f4 2346 #define CAN_RI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
mbed_official 403:91a4bea587f4 2347 #define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
mbed_official 403:91a4bea587f4 2348 #define CAN_RI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
mbed_official 403:91a4bea587f4 2349
mbed_official 403:91a4bea587f4 2350 /******************* Bit definition for CAN_RDT0R register ******************/
mbed_official 403:91a4bea587f4 2351 #define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
mbed_official 403:91a4bea587f4 2352 #define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
mbed_official 403:91a4bea587f4 2353 #define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
mbed_official 403:91a4bea587f4 2354
mbed_official 403:91a4bea587f4 2355 /******************* Bit definition for CAN_RDL0R register ******************/
mbed_official 403:91a4bea587f4 2356 #define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
mbed_official 403:91a4bea587f4 2357 #define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
mbed_official 403:91a4bea587f4 2358 #define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
mbed_official 403:91a4bea587f4 2359 #define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
mbed_official 403:91a4bea587f4 2360
mbed_official 403:91a4bea587f4 2361 /******************* Bit definition for CAN_RDH0R register ******************/
mbed_official 403:91a4bea587f4 2362 #define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
mbed_official 403:91a4bea587f4 2363 #define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
mbed_official 403:91a4bea587f4 2364 #define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
mbed_official 403:91a4bea587f4 2365 #define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
mbed_official 403:91a4bea587f4 2366
mbed_official 403:91a4bea587f4 2367 /******************* Bit definition for CAN_RI1R register *******************/
mbed_official 403:91a4bea587f4 2368 #define CAN_RI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
mbed_official 403:91a4bea587f4 2369 #define CAN_RI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
mbed_official 403:91a4bea587f4 2370 #define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
mbed_official 403:91a4bea587f4 2371 #define CAN_RI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
mbed_official 403:91a4bea587f4 2372
mbed_official 403:91a4bea587f4 2373 /******************* Bit definition for CAN_RDT1R register ******************/
mbed_official 403:91a4bea587f4 2374 #define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
mbed_official 403:91a4bea587f4 2375 #define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
mbed_official 403:91a4bea587f4 2376 #define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
mbed_official 403:91a4bea587f4 2377
mbed_official 403:91a4bea587f4 2378 /******************* Bit definition for CAN_RDL1R register ******************/
mbed_official 403:91a4bea587f4 2379 #define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
mbed_official 403:91a4bea587f4 2380 #define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
mbed_official 403:91a4bea587f4 2381 #define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
mbed_official 403:91a4bea587f4 2382 #define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
mbed_official 403:91a4bea587f4 2383
mbed_official 403:91a4bea587f4 2384 /******************* Bit definition for CAN_RDH1R register ******************/
mbed_official 403:91a4bea587f4 2385 #define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
mbed_official 403:91a4bea587f4 2386 #define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
mbed_official 403:91a4bea587f4 2387 #define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
mbed_official 403:91a4bea587f4 2388 #define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
mbed_official 403:91a4bea587f4 2389
mbed_official 403:91a4bea587f4 2390 /*!<CAN filter registers */
mbed_official 403:91a4bea587f4 2391 /******************* Bit definition for CAN_FMR register ********************/
mbed_official 403:91a4bea587f4 2392 #define CAN_FMR_FINIT ((uint32_t)0x00000001) /*!<Filter Init Mode */
mbed_official 403:91a4bea587f4 2393
mbed_official 403:91a4bea587f4 2394 /******************* Bit definition for CAN_FM1R register *******************/
mbed_official 403:91a4bea587f4 2395 #define CAN_FM1R_FBM ((uint32_t)0x00003FFF) /*!<Filter Mode */
mbed_official 403:91a4bea587f4 2396 #define CAN_FM1R_FBM0 ((uint32_t)0x00000001) /*!<Filter Init Mode bit 0 */
mbed_official 403:91a4bea587f4 2397 #define CAN_FM1R_FBM1 ((uint32_t)0x00000002) /*!<Filter Init Mode bit 1 */
mbed_official 403:91a4bea587f4 2398 #define CAN_FM1R_FBM2 ((uint32_t)0x00000004) /*!<Filter Init Mode bit 2 */
mbed_official 403:91a4bea587f4 2399 #define CAN_FM1R_FBM3 ((uint32_t)0x00000008) /*!<Filter Init Mode bit 3 */
mbed_official 403:91a4bea587f4 2400 #define CAN_FM1R_FBM4 ((uint32_t)0x00000010) /*!<Filter Init Mode bit 4 */
mbed_official 403:91a4bea587f4 2401 #define CAN_FM1R_FBM5 ((uint32_t)0x00000020) /*!<Filter Init Mode bit 5 */
mbed_official 403:91a4bea587f4 2402 #define CAN_FM1R_FBM6 ((uint32_t)0x00000040) /*!<Filter Init Mode bit 6 */
mbed_official 403:91a4bea587f4 2403 #define CAN_FM1R_FBM7 ((uint32_t)0x00000080) /*!<Filter Init Mode bit 7 */
mbed_official 403:91a4bea587f4 2404 #define CAN_FM1R_FBM8 ((uint32_t)0x00000100) /*!<Filter Init Mode bit 8 */
mbed_official 403:91a4bea587f4 2405 #define CAN_FM1R_FBM9 ((uint32_t)0x00000200) /*!<Filter Init Mode bit 9 */
mbed_official 403:91a4bea587f4 2406 #define CAN_FM1R_FBM10 ((uint32_t)0x00000400) /*!<Filter Init Mode bit 10 */
mbed_official 403:91a4bea587f4 2407 #define CAN_FM1R_FBM11 ((uint32_t)0x00000800) /*!<Filter Init Mode bit 11 */
mbed_official 403:91a4bea587f4 2408 #define CAN_FM1R_FBM12 ((uint32_t)0x00001000) /*!<Filter Init Mode bit 12 */
mbed_official 403:91a4bea587f4 2409 #define CAN_FM1R_FBM13 ((uint32_t)0x00002000) /*!<Filter Init Mode bit 13 */
mbed_official 403:91a4bea587f4 2410
mbed_official 403:91a4bea587f4 2411 /******************* Bit definition for CAN_FS1R register *******************/
mbed_official 403:91a4bea587f4 2412 #define CAN_FS1R_FSC ((uint32_t)0x00003FFF) /*!<Filter Scale Configuration */
mbed_official 403:91a4bea587f4 2413 #define CAN_FS1R_FSC0 ((uint32_t)0x00000001) /*!<Filter Scale Configuration bit 0 */
mbed_official 403:91a4bea587f4 2414 #define CAN_FS1R_FSC1 ((uint32_t)0x00000002) /*!<Filter Scale Configuration bit 1 */
mbed_official 403:91a4bea587f4 2415 #define CAN_FS1R_FSC2 ((uint32_t)0x00000004) /*!<Filter Scale Configuration bit 2 */
mbed_official 403:91a4bea587f4 2416 #define CAN_FS1R_FSC3 ((uint32_t)0x00000008) /*!<Filter Scale Configuration bit 3 */
mbed_official 403:91a4bea587f4 2417 #define CAN_FS1R_FSC4 ((uint32_t)0x00000010) /*!<Filter Scale Configuration bit 4 */
mbed_official 403:91a4bea587f4 2418 #define CAN_FS1R_FSC5 ((uint32_t)0x00000020) /*!<Filter Scale Configuration bit 5 */
mbed_official 403:91a4bea587f4 2419 #define CAN_FS1R_FSC6 ((uint32_t)0x00000040) /*!<Filter Scale Configuration bit 6 */
mbed_official 403:91a4bea587f4 2420 #define CAN_FS1R_FSC7 ((uint32_t)0x00000080) /*!<Filter Scale Configuration bit 7 */
mbed_official 403:91a4bea587f4 2421 #define CAN_FS1R_FSC8 ((uint32_t)0x00000100) /*!<Filter Scale Configuration bit 8 */
mbed_official 403:91a4bea587f4 2422 #define CAN_FS1R_FSC9 ((uint32_t)0x00000200) /*!<Filter Scale Configuration bit 9 */
mbed_official 403:91a4bea587f4 2423 #define CAN_FS1R_FSC10 ((uint32_t)0x00000400) /*!<Filter Scale Configuration bit 10 */
mbed_official 403:91a4bea587f4 2424 #define CAN_FS1R_FSC11 ((uint32_t)0x00000800) /*!<Filter Scale Configuration bit 11 */
mbed_official 403:91a4bea587f4 2425 #define CAN_FS1R_FSC12 ((uint32_t)0x00001000) /*!<Filter Scale Configuration bit 12 */
mbed_official 403:91a4bea587f4 2426 #define CAN_FS1R_FSC13 ((uint32_t)0x00002000) /*!<Filter Scale Configuration bit 13 */
mbed_official 403:91a4bea587f4 2427
mbed_official 403:91a4bea587f4 2428 /****************** Bit definition for CAN_FFA1R register *******************/
mbed_official 403:91a4bea587f4 2429 #define CAN_FFA1R_FFA ((uint32_t)0x00003FFF) /*!<Filter FIFO Assignment */
mbed_official 403:91a4bea587f4 2430 #define CAN_FFA1R_FFA0 ((uint32_t)0x00000001) /*!<Filter FIFO Assignment for Filter 0 */
mbed_official 403:91a4bea587f4 2431 #define CAN_FFA1R_FFA1 ((uint32_t)0x00000002) /*!<Filter FIFO Assignment for Filter 1 */
mbed_official 403:91a4bea587f4 2432 #define CAN_FFA1R_FFA2 ((uint32_t)0x00000004) /*!<Filter FIFO Assignment for Filter 2 */
mbed_official 403:91a4bea587f4 2433 #define CAN_FFA1R_FFA3 ((uint32_t)0x00000008) /*!<Filter FIFO Assignment for Filter 3 */
mbed_official 403:91a4bea587f4 2434 #define CAN_FFA1R_FFA4 ((uint32_t)0x00000010) /*!<Filter FIFO Assignment for Filter 4 */
mbed_official 403:91a4bea587f4 2435 #define CAN_FFA1R_FFA5 ((uint32_t)0x00000020) /*!<Filter FIFO Assignment for Filter 5 */
mbed_official 403:91a4bea587f4 2436 #define CAN_FFA1R_FFA6 ((uint32_t)0x00000040) /*!<Filter FIFO Assignment for Filter 6 */
mbed_official 403:91a4bea587f4 2437 #define CAN_FFA1R_FFA7 ((uint32_t)0x00000080) /*!<Filter FIFO Assignment for Filter 7 */
mbed_official 403:91a4bea587f4 2438 #define CAN_FFA1R_FFA8 ((uint32_t)0x00000100) /*!<Filter FIFO Assignment for Filter 8 */
mbed_official 403:91a4bea587f4 2439 #define CAN_FFA1R_FFA9 ((uint32_t)0x00000200) /*!<Filter FIFO Assignment for Filter 9 */
mbed_official 403:91a4bea587f4 2440 #define CAN_FFA1R_FFA10 ((uint32_t)0x00000400) /*!<Filter FIFO Assignment for Filter 10 */
mbed_official 403:91a4bea587f4 2441 #define CAN_FFA1R_FFA11 ((uint32_t)0x00000800) /*!<Filter FIFO Assignment for Filter 11 */
mbed_official 403:91a4bea587f4 2442 #define CAN_FFA1R_FFA12 ((uint32_t)0x00001000) /*!<Filter FIFO Assignment for Filter 12 */
mbed_official 403:91a4bea587f4 2443 #define CAN_FFA1R_FFA13 ((uint32_t)0x00002000) /*!<Filter FIFO Assignment for Filter 13 */
mbed_official 403:91a4bea587f4 2444
mbed_official 403:91a4bea587f4 2445 /******************* Bit definition for CAN_FA1R register *******************/
mbed_official 403:91a4bea587f4 2446 #define CAN_FA1R_FACT ((uint32_t)0x00003FFF) /*!<Filter Active */
mbed_official 403:91a4bea587f4 2447 #define CAN_FA1R_FACT0 ((uint32_t)0x00000001) /*!<Filter 0 Active */
mbed_official 403:91a4bea587f4 2448 #define CAN_FA1R_FACT1 ((uint32_t)0x00000002) /*!<Filter 1 Active */
mbed_official 403:91a4bea587f4 2449 #define CAN_FA1R_FACT2 ((uint32_t)0x00000004) /*!<Filter 2 Active */
mbed_official 403:91a4bea587f4 2450 #define CAN_FA1R_FACT3 ((uint32_t)0x00000008) /*!<Filter 3 Active */
mbed_official 403:91a4bea587f4 2451 #define CAN_FA1R_FACT4 ((uint32_t)0x00000010) /*!<Filter 4 Active */
mbed_official 403:91a4bea587f4 2452 #define CAN_FA1R_FACT5 ((uint32_t)0x00000020) /*!<Filter 5 Active */
mbed_official 403:91a4bea587f4 2453 #define CAN_FA1R_FACT6 ((uint32_t)0x00000040) /*!<Filter 6 Active */
mbed_official 403:91a4bea587f4 2454 #define CAN_FA1R_FACT7 ((uint32_t)0x00000080) /*!<Filter 7 Active */
mbed_official 403:91a4bea587f4 2455 #define CAN_FA1R_FACT8 ((uint32_t)0x00000100) /*!<Filter 8 Active */
mbed_official 403:91a4bea587f4 2456 #define CAN_FA1R_FACT9 ((uint32_t)0x00000200) /*!<Filter 9 Active */
mbed_official 403:91a4bea587f4 2457 #define CAN_FA1R_FACT10 ((uint32_t)0x00000400) /*!<Filter 10 Active */
mbed_official 403:91a4bea587f4 2458 #define CAN_FA1R_FACT11 ((uint32_t)0x00000800) /*!<Filter 11 Active */
mbed_official 403:91a4bea587f4 2459 #define CAN_FA1R_FACT12 ((uint32_t)0x00001000) /*!<Filter 12 Active */
mbed_official 403:91a4bea587f4 2460 #define CAN_FA1R_FACT13 ((uint32_t)0x00002000) /*!<Filter 13 Active */
mbed_official 403:91a4bea587f4 2461
mbed_official 403:91a4bea587f4 2462 /******************* Bit definition for CAN_F0R1 register *******************/
mbed_official 403:91a4bea587f4 2463 #define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 403:91a4bea587f4 2464 #define CAN_F0R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 403:91a4bea587f4 2465 #define CAN_F0R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 403:91a4bea587f4 2466 #define CAN_F0R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 403:91a4bea587f4 2467 #define CAN_F0R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 403:91a4bea587f4 2468 #define CAN_F0R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 403:91a4bea587f4 2469 #define CAN_F0R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 403:91a4bea587f4 2470 #define CAN_F0R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 403:91a4bea587f4 2471 #define CAN_F0R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 403:91a4bea587f4 2472 #define CAN_F0R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 403:91a4bea587f4 2473 #define CAN_F0R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 403:91a4bea587f4 2474 #define CAN_F0R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 403:91a4bea587f4 2475 #define CAN_F0R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 403:91a4bea587f4 2476 #define CAN_F0R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 403:91a4bea587f4 2477 #define CAN_F0R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 403:91a4bea587f4 2478 #define CAN_F0R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 403:91a4bea587f4 2479 #define CAN_F0R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 403:91a4bea587f4 2480 #define CAN_F0R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 403:91a4bea587f4 2481 #define CAN_F0R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 403:91a4bea587f4 2482 #define CAN_F0R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 403:91a4bea587f4 2483 #define CAN_F0R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 403:91a4bea587f4 2484 #define CAN_F0R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 403:91a4bea587f4 2485 #define CAN_F0R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 403:91a4bea587f4 2486 #define CAN_F0R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 403:91a4bea587f4 2487 #define CAN_F0R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 403:91a4bea587f4 2488 #define CAN_F0R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 403:91a4bea587f4 2489 #define CAN_F0R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 403:91a4bea587f4 2490 #define CAN_F0R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 403:91a4bea587f4 2491 #define CAN_F0R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 403:91a4bea587f4 2492 #define CAN_F0R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 403:91a4bea587f4 2493 #define CAN_F0R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 403:91a4bea587f4 2494 #define CAN_F0R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 403:91a4bea587f4 2495
mbed_official 403:91a4bea587f4 2496 /******************* Bit definition for CAN_F1R1 register *******************/
mbed_official 403:91a4bea587f4 2497 #define CAN_F1R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 403:91a4bea587f4 2498 #define CAN_F1R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 403:91a4bea587f4 2499 #define CAN_F1R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 403:91a4bea587f4 2500 #define CAN_F1R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 403:91a4bea587f4 2501 #define CAN_F1R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 403:91a4bea587f4 2502 #define CAN_F1R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 403:91a4bea587f4 2503 #define CAN_F1R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 403:91a4bea587f4 2504 #define CAN_F1R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 403:91a4bea587f4 2505 #define CAN_F1R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 403:91a4bea587f4 2506 #define CAN_F1R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 403:91a4bea587f4 2507 #define CAN_F1R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 403:91a4bea587f4 2508 #define CAN_F1R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 403:91a4bea587f4 2509 #define CAN_F1R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 403:91a4bea587f4 2510 #define CAN_F1R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 403:91a4bea587f4 2511 #define CAN_F1R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 403:91a4bea587f4 2512 #define CAN_F1R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 403:91a4bea587f4 2513 #define CAN_F1R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 403:91a4bea587f4 2514 #define CAN_F1R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 403:91a4bea587f4 2515 #define CAN_F1R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 403:91a4bea587f4 2516 #define CAN_F1R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 403:91a4bea587f4 2517 #define CAN_F1R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 403:91a4bea587f4 2518 #define CAN_F1R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 403:91a4bea587f4 2519 #define CAN_F1R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 403:91a4bea587f4 2520 #define CAN_F1R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 403:91a4bea587f4 2521 #define CAN_F1R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 403:91a4bea587f4 2522 #define CAN_F1R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 403:91a4bea587f4 2523 #define CAN_F1R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 403:91a4bea587f4 2524 #define CAN_F1R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 403:91a4bea587f4 2525 #define CAN_F1R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 403:91a4bea587f4 2526 #define CAN_F1R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 403:91a4bea587f4 2527 #define CAN_F1R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 403:91a4bea587f4 2528 #define CAN_F1R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 403:91a4bea587f4 2529
mbed_official 403:91a4bea587f4 2530 /******************* Bit definition for CAN_F2R1 register *******************/
mbed_official 403:91a4bea587f4 2531 #define CAN_F2R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 403:91a4bea587f4 2532 #define CAN_F2R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 403:91a4bea587f4 2533 #define CAN_F2R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 403:91a4bea587f4 2534 #define CAN_F2R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 403:91a4bea587f4 2535 #define CAN_F2R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 403:91a4bea587f4 2536 #define CAN_F2R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 403:91a4bea587f4 2537 #define CAN_F2R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 403:91a4bea587f4 2538 #define CAN_F2R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 403:91a4bea587f4 2539 #define CAN_F2R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 403:91a4bea587f4 2540 #define CAN_F2R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 403:91a4bea587f4 2541 #define CAN_F2R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 403:91a4bea587f4 2542 #define CAN_F2R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 403:91a4bea587f4 2543 #define CAN_F2R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 403:91a4bea587f4 2544 #define CAN_F2R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 403:91a4bea587f4 2545 #define CAN_F2R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 403:91a4bea587f4 2546 #define CAN_F2R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 403:91a4bea587f4 2547 #define CAN_F2R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 403:91a4bea587f4 2548 #define CAN_F2R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 403:91a4bea587f4 2549 #define CAN_F2R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 403:91a4bea587f4 2550 #define CAN_F2R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 403:91a4bea587f4 2551 #define CAN_F2R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 403:91a4bea587f4 2552 #define CAN_F2R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 403:91a4bea587f4 2553 #define CAN_F2R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 403:91a4bea587f4 2554 #define CAN_F2R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 403:91a4bea587f4 2555 #define CAN_F2R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 403:91a4bea587f4 2556 #define CAN_F2R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 403:91a4bea587f4 2557 #define CAN_F2R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 403:91a4bea587f4 2558 #define CAN_F2R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 403:91a4bea587f4 2559 #define CAN_F2R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 403:91a4bea587f4 2560 #define CAN_F2R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 403:91a4bea587f4 2561 #define CAN_F2R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 403:91a4bea587f4 2562 #define CAN_F2R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 403:91a4bea587f4 2563
mbed_official 403:91a4bea587f4 2564 /******************* Bit definition for CAN_F3R1 register *******************/
mbed_official 403:91a4bea587f4 2565 #define CAN_F3R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 403:91a4bea587f4 2566 #define CAN_F3R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 403:91a4bea587f4 2567 #define CAN_F3R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 403:91a4bea587f4 2568 #define CAN_F3R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 403:91a4bea587f4 2569 #define CAN_F3R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 403:91a4bea587f4 2570 #define CAN_F3R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 403:91a4bea587f4 2571 #define CAN_F3R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 403:91a4bea587f4 2572 #define CAN_F3R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 403:91a4bea587f4 2573 #define CAN_F3R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 403:91a4bea587f4 2574 #define CAN_F3R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 403:91a4bea587f4 2575 #define CAN_F3R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 403:91a4bea587f4 2576 #define CAN_F3R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 403:91a4bea587f4 2577 #define CAN_F3R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 403:91a4bea587f4 2578 #define CAN_F3R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 403:91a4bea587f4 2579 #define CAN_F3R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 403:91a4bea587f4 2580 #define CAN_F3R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 403:91a4bea587f4 2581 #define CAN_F3R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 403:91a4bea587f4 2582 #define CAN_F3R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 403:91a4bea587f4 2583 #define CAN_F3R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 403:91a4bea587f4 2584 #define CAN_F3R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 403:91a4bea587f4 2585 #define CAN_F3R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 403:91a4bea587f4 2586 #define CAN_F3R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 403:91a4bea587f4 2587 #define CAN_F3R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 403:91a4bea587f4 2588 #define CAN_F3R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 403:91a4bea587f4 2589 #define CAN_F3R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 403:91a4bea587f4 2590 #define CAN_F3R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 403:91a4bea587f4 2591 #define CAN_F3R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 403:91a4bea587f4 2592 #define CAN_F3R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 403:91a4bea587f4 2593 #define CAN_F3R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 403:91a4bea587f4 2594 #define CAN_F3R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 403:91a4bea587f4 2595 #define CAN_F3R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 403:91a4bea587f4 2596 #define CAN_F3R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 403:91a4bea587f4 2597
mbed_official 403:91a4bea587f4 2598 /******************* Bit definition for CAN_F4R1 register *******************/
mbed_official 403:91a4bea587f4 2599 #define CAN_F4R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 403:91a4bea587f4 2600 #define CAN_F4R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 403:91a4bea587f4 2601 #define CAN_F4R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 403:91a4bea587f4 2602 #define CAN_F4R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 403:91a4bea587f4 2603 #define CAN_F4R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 403:91a4bea587f4 2604 #define CAN_F4R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 403:91a4bea587f4 2605 #define CAN_F4R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 403:91a4bea587f4 2606 #define CAN_F4R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 403:91a4bea587f4 2607 #define CAN_F4R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 403:91a4bea587f4 2608 #define CAN_F4R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 403:91a4bea587f4 2609 #define CAN_F4R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 403:91a4bea587f4 2610 #define CAN_F4R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 403:91a4bea587f4 2611 #define CAN_F4R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 403:91a4bea587f4 2612 #define CAN_F4R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 403:91a4bea587f4 2613 #define CAN_F4R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 403:91a4bea587f4 2614 #define CAN_F4R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 403:91a4bea587f4 2615 #define CAN_F4R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 403:91a4bea587f4 2616 #define CAN_F4R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 403:91a4bea587f4 2617 #define CAN_F4R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 403:91a4bea587f4 2618 #define CAN_F4R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 403:91a4bea587f4 2619 #define CAN_F4R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 403:91a4bea587f4 2620 #define CAN_F4R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 403:91a4bea587f4 2621 #define CAN_F4R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 403:91a4bea587f4 2622 #define CAN_F4R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 403:91a4bea587f4 2623 #define CAN_F4R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 403:91a4bea587f4 2624 #define CAN_F4R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 403:91a4bea587f4 2625 #define CAN_F4R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 403:91a4bea587f4 2626 #define CAN_F4R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 403:91a4bea587f4 2627 #define CAN_F4R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 403:91a4bea587f4 2628 #define CAN_F4R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 403:91a4bea587f4 2629 #define CAN_F4R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 403:91a4bea587f4 2630 #define CAN_F4R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 403:91a4bea587f4 2631
mbed_official 403:91a4bea587f4 2632 /******************* Bit definition for CAN_F5R1 register *******************/
mbed_official 403:91a4bea587f4 2633 #define CAN_F5R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 403:91a4bea587f4 2634 #define CAN_F5R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 403:91a4bea587f4 2635 #define CAN_F5R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 403:91a4bea587f4 2636 #define CAN_F5R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 403:91a4bea587f4 2637 #define CAN_F5R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 403:91a4bea587f4 2638 #define CAN_F5R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 403:91a4bea587f4 2639 #define CAN_F5R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 403:91a4bea587f4 2640 #define CAN_F5R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 403:91a4bea587f4 2641 #define CAN_F5R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 403:91a4bea587f4 2642 #define CAN_F5R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 403:91a4bea587f4 2643 #define CAN_F5R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 403:91a4bea587f4 2644 #define CAN_F5R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 403:91a4bea587f4 2645 #define CAN_F5R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 403:91a4bea587f4 2646 #define CAN_F5R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 403:91a4bea587f4 2647 #define CAN_F5R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 403:91a4bea587f4 2648 #define CAN_F5R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 403:91a4bea587f4 2649 #define CAN_F5R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 403:91a4bea587f4 2650 #define CAN_F5R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 403:91a4bea587f4 2651 #define CAN_F5R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 403:91a4bea587f4 2652 #define CAN_F5R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 403:91a4bea587f4 2653 #define CAN_F5R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 403:91a4bea587f4 2654 #define CAN_F5R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 403:91a4bea587f4 2655 #define CAN_F5R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 403:91a4bea587f4 2656 #define CAN_F5R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 403:91a4bea587f4 2657 #define CAN_F5R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 403:91a4bea587f4 2658 #define CAN_F5R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 403:91a4bea587f4 2659 #define CAN_F5R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 403:91a4bea587f4 2660 #define CAN_F5R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 403:91a4bea587f4 2661 #define CAN_F5R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 403:91a4bea587f4 2662 #define CAN_F5R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 403:91a4bea587f4 2663 #define CAN_F5R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 403:91a4bea587f4 2664 #define CAN_F5R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 403:91a4bea587f4 2665
mbed_official 403:91a4bea587f4 2666 /******************* Bit definition for CAN_F6R1 register *******************/
mbed_official 403:91a4bea587f4 2667 #define CAN_F6R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 403:91a4bea587f4 2668 #define CAN_F6R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 403:91a4bea587f4 2669 #define CAN_F6R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 403:91a4bea587f4 2670 #define CAN_F6R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 403:91a4bea587f4 2671 #define CAN_F6R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 403:91a4bea587f4 2672 #define CAN_F6R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 403:91a4bea587f4 2673 #define CAN_F6R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 403:91a4bea587f4 2674 #define CAN_F6R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 403:91a4bea587f4 2675 #define CAN_F6R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 403:91a4bea587f4 2676 #define CAN_F6R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 403:91a4bea587f4 2677 #define CAN_F6R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 403:91a4bea587f4 2678 #define CAN_F6R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 403:91a4bea587f4 2679 #define CAN_F6R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 403:91a4bea587f4 2680 #define CAN_F6R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 403:91a4bea587f4 2681 #define CAN_F6R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 403:91a4bea587f4 2682 #define CAN_F6R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 403:91a4bea587f4 2683 #define CAN_F6R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 403:91a4bea587f4 2684 #define CAN_F6R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 403:91a4bea587f4 2685 #define CAN_F6R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 403:91a4bea587f4 2686 #define CAN_F6R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 403:91a4bea587f4 2687 #define CAN_F6R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 403:91a4bea587f4 2688 #define CAN_F6R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 403:91a4bea587f4 2689 #define CAN_F6R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 403:91a4bea587f4 2690 #define CAN_F6R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 403:91a4bea587f4 2691 #define CAN_F6R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 403:91a4bea587f4 2692 #define CAN_F6R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 403:91a4bea587f4 2693 #define CAN_F6R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 403:91a4bea587f4 2694 #define CAN_F6R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 403:91a4bea587f4 2695 #define CAN_F6R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 403:91a4bea587f4 2696 #define CAN_F6R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 403:91a4bea587f4 2697 #define CAN_F6R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 403:91a4bea587f4 2698 #define CAN_F6R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 403:91a4bea587f4 2699
mbed_official 403:91a4bea587f4 2700 /******************* Bit definition for CAN_F7R1 register *******************/
mbed_official 403:91a4bea587f4 2701 #define CAN_F7R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 403:91a4bea587f4 2702 #define CAN_F7R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 403:91a4bea587f4 2703 #define CAN_F7R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 403:91a4bea587f4 2704 #define CAN_F7R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 403:91a4bea587f4 2705 #define CAN_F7R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 403:91a4bea587f4 2706 #define CAN_F7R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 403:91a4bea587f4 2707 #define CAN_F7R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 403:91a4bea587f4 2708 #define CAN_F7R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 403:91a4bea587f4 2709 #define CAN_F7R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 403:91a4bea587f4 2710 #define CAN_F7R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 403:91a4bea587f4 2711 #define CAN_F7R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 403:91a4bea587f4 2712 #define CAN_F7R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 403:91a4bea587f4 2713 #define CAN_F7R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 403:91a4bea587f4 2714 #define CAN_F7R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 403:91a4bea587f4 2715 #define CAN_F7R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 403:91a4bea587f4 2716 #define CAN_F7R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 403:91a4bea587f4 2717 #define CAN_F7R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 403:91a4bea587f4 2718 #define CAN_F7R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 403:91a4bea587f4 2719 #define CAN_F7R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 403:91a4bea587f4 2720 #define CAN_F7R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 403:91a4bea587f4 2721 #define CAN_F7R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 403:91a4bea587f4 2722 #define CAN_F7R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 403:91a4bea587f4 2723 #define CAN_F7R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 403:91a4bea587f4 2724 #define CAN_F7R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 403:91a4bea587f4 2725 #define CAN_F7R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 403:91a4bea587f4 2726 #define CAN_F7R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 403:91a4bea587f4 2727 #define CAN_F7R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 403:91a4bea587f4 2728 #define CAN_F7R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 403:91a4bea587f4 2729 #define CAN_F7R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 403:91a4bea587f4 2730 #define CAN_F7R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 403:91a4bea587f4 2731 #define CAN_F7R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 403:91a4bea587f4 2732 #define CAN_F7R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 403:91a4bea587f4 2733
mbed_official 403:91a4bea587f4 2734 /******************* Bit definition for CAN_F8R1 register *******************/
mbed_official 403:91a4bea587f4 2735 #define CAN_F8R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 403:91a4bea587f4 2736 #define CAN_F8R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 403:91a4bea587f4 2737 #define CAN_F8R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 403:91a4bea587f4 2738 #define CAN_F8R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 403:91a4bea587f4 2739 #define CAN_F8R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 403:91a4bea587f4 2740 #define CAN_F8R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 403:91a4bea587f4 2741 #define CAN_F8R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 403:91a4bea587f4 2742 #define CAN_F8R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 403:91a4bea587f4 2743 #define CAN_F8R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 403:91a4bea587f4 2744 #define CAN_F8R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 403:91a4bea587f4 2745 #define CAN_F8R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 403:91a4bea587f4 2746 #define CAN_F8R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 403:91a4bea587f4 2747 #define CAN_F8R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 403:91a4bea587f4 2748 #define CAN_F8R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 403:91a4bea587f4 2749 #define CAN_F8R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 403:91a4bea587f4 2750 #define CAN_F8R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 403:91a4bea587f4 2751 #define CAN_F8R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 403:91a4bea587f4 2752 #define CAN_F8R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 403:91a4bea587f4 2753 #define CAN_F8R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 403:91a4bea587f4 2754 #define CAN_F8R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 403:91a4bea587f4 2755 #define CAN_F8R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 403:91a4bea587f4 2756 #define CAN_F8R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 403:91a4bea587f4 2757 #define CAN_F8R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 403:91a4bea587f4 2758 #define CAN_F8R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 403:91a4bea587f4 2759 #define CAN_F8R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 403:91a4bea587f4 2760 #define CAN_F8R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 403:91a4bea587f4 2761 #define CAN_F8R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 403:91a4bea587f4 2762 #define CAN_F8R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 403:91a4bea587f4 2763 #define CAN_F8R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 403:91a4bea587f4 2764 #define CAN_F8R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 403:91a4bea587f4 2765 #define CAN_F8R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 403:91a4bea587f4 2766 #define CAN_F8R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 403:91a4bea587f4 2767
mbed_official 403:91a4bea587f4 2768 /******************* Bit definition for CAN_F9R1 register *******************/
mbed_official 403:91a4bea587f4 2769 #define CAN_F9R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 403:91a4bea587f4 2770 #define CAN_F9R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 403:91a4bea587f4 2771 #define CAN_F9R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 403:91a4bea587f4 2772 #define CAN_F9R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 403:91a4bea587f4 2773 #define CAN_F9R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 403:91a4bea587f4 2774 #define CAN_F9R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 403:91a4bea587f4 2775 #define CAN_F9R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 403:91a4bea587f4 2776 #define CAN_F9R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 403:91a4bea587f4 2777 #define CAN_F9R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 403:91a4bea587f4 2778 #define CAN_F9R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 403:91a4bea587f4 2779 #define CAN_F9R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 403:91a4bea587f4 2780 #define CAN_F9R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 403:91a4bea587f4 2781 #define CAN_F9R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 403:91a4bea587f4 2782 #define CAN_F9R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 403:91a4bea587f4 2783 #define CAN_F9R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 403:91a4bea587f4 2784 #define CAN_F9R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 403:91a4bea587f4 2785 #define CAN_F9R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 403:91a4bea587f4 2786 #define CAN_F9R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 403:91a4bea587f4 2787 #define CAN_F9R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 403:91a4bea587f4 2788 #define CAN_F9R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 403:91a4bea587f4 2789 #define CAN_F9R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 403:91a4bea587f4 2790 #define CAN_F9R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 403:91a4bea587f4 2791 #define CAN_F9R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 403:91a4bea587f4 2792 #define CAN_F9R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 403:91a4bea587f4 2793 #define CAN_F9R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 403:91a4bea587f4 2794 #define CAN_F9R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 403:91a4bea587f4 2795 #define CAN_F9R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 403:91a4bea587f4 2796 #define CAN_F9R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 403:91a4bea587f4 2797 #define CAN_F9R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 403:91a4bea587f4 2798 #define CAN_F9R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 403:91a4bea587f4 2799 #define CAN_F9R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 403:91a4bea587f4 2800 #define CAN_F9R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 403:91a4bea587f4 2801
mbed_official 403:91a4bea587f4 2802 /******************* Bit definition for CAN_F10R1 register ******************/
mbed_official 403:91a4bea587f4 2803 #define CAN_F10R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 403:91a4bea587f4 2804 #define CAN_F10R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 403:91a4bea587f4 2805 #define CAN_F10R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 403:91a4bea587f4 2806 #define CAN_F10R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 403:91a4bea587f4 2807 #define CAN_F10R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 403:91a4bea587f4 2808 #define CAN_F10R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 403:91a4bea587f4 2809 #define CAN_F10R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 403:91a4bea587f4 2810 #define CAN_F10R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 403:91a4bea587f4 2811 #define CAN_F10R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 403:91a4bea587f4 2812 #define CAN_F10R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 403:91a4bea587f4 2813 #define CAN_F10R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 403:91a4bea587f4 2814 #define CAN_F10R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 403:91a4bea587f4 2815 #define CAN_F10R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 403:91a4bea587f4 2816 #define CAN_F10R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 403:91a4bea587f4 2817 #define CAN_F10R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 403:91a4bea587f4 2818 #define CAN_F10R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 403:91a4bea587f4 2819 #define CAN_F10R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 403:91a4bea587f4 2820 #define CAN_F10R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 403:91a4bea587f4 2821 #define CAN_F10R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 403:91a4bea587f4 2822 #define CAN_F10R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 403:91a4bea587f4 2823 #define CAN_F10R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 403:91a4bea587f4 2824 #define CAN_F10R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 403:91a4bea587f4 2825 #define CAN_F10R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 403:91a4bea587f4 2826 #define CAN_F10R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 403:91a4bea587f4 2827 #define CAN_F10R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 403:91a4bea587f4 2828 #define CAN_F10R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 403:91a4bea587f4 2829 #define CAN_F10R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 403:91a4bea587f4 2830 #define CAN_F10R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 403:91a4bea587f4 2831 #define CAN_F10R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 403:91a4bea587f4 2832 #define CAN_F10R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 403:91a4bea587f4 2833 #define CAN_F10R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 403:91a4bea587f4 2834 #define CAN_F10R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 403:91a4bea587f4 2835
mbed_official 403:91a4bea587f4 2836 /******************* Bit definition for CAN_F11R1 register ******************/
mbed_official 403:91a4bea587f4 2837 #define CAN_F11R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 403:91a4bea587f4 2838 #define CAN_F11R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 403:91a4bea587f4 2839 #define CAN_F11R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 403:91a4bea587f4 2840 #define CAN_F11R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 403:91a4bea587f4 2841 #define CAN_F11R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 403:91a4bea587f4 2842 #define CAN_F11R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 403:91a4bea587f4 2843 #define CAN_F11R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 403:91a4bea587f4 2844 #define CAN_F11R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 403:91a4bea587f4 2845 #define CAN_F11R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 403:91a4bea587f4 2846 #define CAN_F11R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 403:91a4bea587f4 2847 #define CAN_F11R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 403:91a4bea587f4 2848 #define CAN_F11R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 403:91a4bea587f4 2849 #define CAN_F11R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 403:91a4bea587f4 2850 #define CAN_F11R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 403:91a4bea587f4 2851 #define CAN_F11R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 403:91a4bea587f4 2852 #define CAN_F11R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 403:91a4bea587f4 2853 #define CAN_F11R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 403:91a4bea587f4 2854 #define CAN_F11R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 403:91a4bea587f4 2855 #define CAN_F11R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 403:91a4bea587f4 2856 #define CAN_F11R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 403:91a4bea587f4 2857 #define CAN_F11R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 403:91a4bea587f4 2858 #define CAN_F11R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 403:91a4bea587f4 2859 #define CAN_F11R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 403:91a4bea587f4 2860 #define CAN_F11R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 403:91a4bea587f4 2861 #define CAN_F11R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 403:91a4bea587f4 2862 #define CAN_F11R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 403:91a4bea587f4 2863 #define CAN_F11R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 403:91a4bea587f4 2864 #define CAN_F11R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 403:91a4bea587f4 2865 #define CAN_F11R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 403:91a4bea587f4 2866 #define CAN_F11R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 403:91a4bea587f4 2867 #define CAN_F11R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 403:91a4bea587f4 2868 #define CAN_F11R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 403:91a4bea587f4 2869
mbed_official 403:91a4bea587f4 2870 /******************* Bit definition for CAN_F12R1 register ******************/
mbed_official 403:91a4bea587f4 2871 #define CAN_F12R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 403:91a4bea587f4 2872 #define CAN_F12R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 403:91a4bea587f4 2873 #define CAN_F12R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 403:91a4bea587f4 2874 #define CAN_F12R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 403:91a4bea587f4 2875 #define CAN_F12R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 403:91a4bea587f4 2876 #define CAN_F12R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 403:91a4bea587f4 2877 #define CAN_F12R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 403:91a4bea587f4 2878 #define CAN_F12R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 403:91a4bea587f4 2879 #define CAN_F12R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 403:91a4bea587f4 2880 #define CAN_F12R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 403:91a4bea587f4 2881 #define CAN_F12R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 403:91a4bea587f4 2882 #define CAN_F12R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 403:91a4bea587f4 2883 #define CAN_F12R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 403:91a4bea587f4 2884 #define CAN_F12R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 403:91a4bea587f4 2885 #define CAN_F12R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 403:91a4bea587f4 2886 #define CAN_F12R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 403:91a4bea587f4 2887 #define CAN_F12R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 403:91a4bea587f4 2888 #define CAN_F12R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 403:91a4bea587f4 2889 #define CAN_F12R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 403:91a4bea587f4 2890 #define CAN_F12R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 403:91a4bea587f4 2891 #define CAN_F12R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 403:91a4bea587f4 2892 #define CAN_F12R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 403:91a4bea587f4 2893 #define CAN_F12R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 403:91a4bea587f4 2894 #define CAN_F12R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 403:91a4bea587f4 2895 #define CAN_F12R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 403:91a4bea587f4 2896 #define CAN_F12R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 403:91a4bea587f4 2897 #define CAN_F12R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 403:91a4bea587f4 2898 #define CAN_F12R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 403:91a4bea587f4 2899 #define CAN_F12R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 403:91a4bea587f4 2900 #define CAN_F12R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 403:91a4bea587f4 2901 #define CAN_F12R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 403:91a4bea587f4 2902 #define CAN_F12R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 403:91a4bea587f4 2903
mbed_official 403:91a4bea587f4 2904 /******************* Bit definition for CAN_F13R1 register ******************/
mbed_official 403:91a4bea587f4 2905 #define CAN_F13R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 403:91a4bea587f4 2906 #define CAN_F13R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 403:91a4bea587f4 2907 #define CAN_F13R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 403:91a4bea587f4 2908 #define CAN_F13R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 403:91a4bea587f4 2909 #define CAN_F13R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 403:91a4bea587f4 2910 #define CAN_F13R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 403:91a4bea587f4 2911 #define CAN_F13R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 403:91a4bea587f4 2912 #define CAN_F13R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 403:91a4bea587f4 2913 #define CAN_F13R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 403:91a4bea587f4 2914 #define CAN_F13R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 403:91a4bea587f4 2915 #define CAN_F13R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 403:91a4bea587f4 2916 #define CAN_F13R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 403:91a4bea587f4 2917 #define CAN_F13R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 403:91a4bea587f4 2918 #define CAN_F13R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 403:91a4bea587f4 2919 #define CAN_F13R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 403:91a4bea587f4 2920 #define CAN_F13R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 403:91a4bea587f4 2921 #define CAN_F13R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 403:91a4bea587f4 2922 #define CAN_F13R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 403:91a4bea587f4 2923 #define CAN_F13R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 403:91a4bea587f4 2924 #define CAN_F13R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 403:91a4bea587f4 2925 #define CAN_F13R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 403:91a4bea587f4 2926 #define CAN_F13R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 403:91a4bea587f4 2927 #define CAN_F13R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 403:91a4bea587f4 2928 #define CAN_F13R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 403:91a4bea587f4 2929 #define CAN_F13R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 403:91a4bea587f4 2930 #define CAN_F13R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 403:91a4bea587f4 2931 #define CAN_F13R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 403:91a4bea587f4 2932 #define CAN_F13R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 403:91a4bea587f4 2933 #define CAN_F13R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 403:91a4bea587f4 2934 #define CAN_F13R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 403:91a4bea587f4 2935 #define CAN_F13R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 403:91a4bea587f4 2936 #define CAN_F13R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 403:91a4bea587f4 2937
mbed_official 403:91a4bea587f4 2938 /******************* Bit definition for CAN_F0R2 register *******************/
mbed_official 403:91a4bea587f4 2939 #define CAN_F0R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 403:91a4bea587f4 2940 #define CAN_F0R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 403:91a4bea587f4 2941 #define CAN_F0R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 403:91a4bea587f4 2942 #define CAN_F0R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 403:91a4bea587f4 2943 #define CAN_F0R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 403:91a4bea587f4 2944 #define CAN_F0R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 403:91a4bea587f4 2945 #define CAN_F0R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 403:91a4bea587f4 2946 #define CAN_F0R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 403:91a4bea587f4 2947 #define CAN_F0R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 403:91a4bea587f4 2948 #define CAN_F0R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 403:91a4bea587f4 2949 #define CAN_F0R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 403:91a4bea587f4 2950 #define CAN_F0R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 403:91a4bea587f4 2951 #define CAN_F0R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 403:91a4bea587f4 2952 #define CAN_F0R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 403:91a4bea587f4 2953 #define CAN_F0R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 403:91a4bea587f4 2954 #define CAN_F0R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 403:91a4bea587f4 2955 #define CAN_F0R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 403:91a4bea587f4 2956 #define CAN_F0R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 403:91a4bea587f4 2957 #define CAN_F0R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 403:91a4bea587f4 2958 #define CAN_F0R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 403:91a4bea587f4 2959 #define CAN_F0R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 403:91a4bea587f4 2960 #define CAN_F0R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 403:91a4bea587f4 2961 #define CAN_F0R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 403:91a4bea587f4 2962 #define CAN_F0R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 403:91a4bea587f4 2963 #define CAN_F0R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 403:91a4bea587f4 2964 #define CAN_F0R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 403:91a4bea587f4 2965 #define CAN_F0R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 403:91a4bea587f4 2966 #define CAN_F0R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 403:91a4bea587f4 2967 #define CAN_F0R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 403:91a4bea587f4 2968 #define CAN_F0R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 403:91a4bea587f4 2969 #define CAN_F0R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 403:91a4bea587f4 2970 #define CAN_F0R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 403:91a4bea587f4 2971
mbed_official 403:91a4bea587f4 2972 /******************* Bit definition for CAN_F1R2 register *******************/
mbed_official 403:91a4bea587f4 2973 #define CAN_F1R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 403:91a4bea587f4 2974 #define CAN_F1R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 403:91a4bea587f4 2975 #define CAN_F1R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 403:91a4bea587f4 2976 #define CAN_F1R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 403:91a4bea587f4 2977 #define CAN_F1R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 403:91a4bea587f4 2978 #define CAN_F1R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 403:91a4bea587f4 2979 #define CAN_F1R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 403:91a4bea587f4 2980 #define CAN_F1R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 403:91a4bea587f4 2981 #define CAN_F1R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 403:91a4bea587f4 2982 #define CAN_F1R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 403:91a4bea587f4 2983 #define CAN_F1R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 403:91a4bea587f4 2984 #define CAN_F1R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 403:91a4bea587f4 2985 #define CAN_F1R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 403:91a4bea587f4 2986 #define CAN_F1R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 403:91a4bea587f4 2987 #define CAN_F1R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 403:91a4bea587f4 2988 #define CAN_F1R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 403:91a4bea587f4 2989 #define CAN_F1R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 403:91a4bea587f4 2990 #define CAN_F1R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 403:91a4bea587f4 2991 #define CAN_F1R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 403:91a4bea587f4 2992 #define CAN_F1R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 403:91a4bea587f4 2993 #define CAN_F1R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 403:91a4bea587f4 2994 #define CAN_F1R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 403:91a4bea587f4 2995 #define CAN_F1R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 403:91a4bea587f4 2996 #define CAN_F1R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 403:91a4bea587f4 2997 #define CAN_F1R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 403:91a4bea587f4 2998 #define CAN_F1R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 403:91a4bea587f4 2999 #define CAN_F1R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 403:91a4bea587f4 3000 #define CAN_F1R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 403:91a4bea587f4 3001 #define CAN_F1R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 403:91a4bea587f4 3002 #define CAN_F1R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 403:91a4bea587f4 3003 #define CAN_F1R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 403:91a4bea587f4 3004 #define CAN_F1R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 403:91a4bea587f4 3005
mbed_official 403:91a4bea587f4 3006 /******************* Bit definition for CAN_F2R2 register *******************/
mbed_official 403:91a4bea587f4 3007 #define CAN_F2R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 403:91a4bea587f4 3008 #define CAN_F2R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 403:91a4bea587f4 3009 #define CAN_F2R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 403:91a4bea587f4 3010 #define CAN_F2R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 403:91a4bea587f4 3011 #define CAN_F2R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 403:91a4bea587f4 3012 #define CAN_F2R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 403:91a4bea587f4 3013 #define CAN_F2R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 403:91a4bea587f4 3014 #define CAN_F2R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 403:91a4bea587f4 3015 #define CAN_F2R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 403:91a4bea587f4 3016 #define CAN_F2R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 403:91a4bea587f4 3017 #define CAN_F2R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 403:91a4bea587f4 3018 #define CAN_F2R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 403:91a4bea587f4 3019 #define CAN_F2R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 403:91a4bea587f4 3020 #define CAN_F2R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 403:91a4bea587f4 3021 #define CAN_F2R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 403:91a4bea587f4 3022 #define CAN_F2R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 403:91a4bea587f4 3023 #define CAN_F2R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 403:91a4bea587f4 3024 #define CAN_F2R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 403:91a4bea587f4 3025 #define CAN_F2R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 403:91a4bea587f4 3026 #define CAN_F2R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 403:91a4bea587f4 3027 #define CAN_F2R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 403:91a4bea587f4 3028 #define CAN_F2R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 403:91a4bea587f4 3029 #define CAN_F2R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 403:91a4bea587f4 3030 #define CAN_F2R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 403:91a4bea587f4 3031 #define CAN_F2R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 403:91a4bea587f4 3032 #define CAN_F2R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 403:91a4bea587f4 3033 #define CAN_F2R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 403:91a4bea587f4 3034 #define CAN_F2R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 403:91a4bea587f4 3035 #define CAN_F2R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 403:91a4bea587f4 3036 #define CAN_F2R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 403:91a4bea587f4 3037 #define CAN_F2R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 403:91a4bea587f4 3038 #define CAN_F2R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 403:91a4bea587f4 3039
mbed_official 403:91a4bea587f4 3040 /******************* Bit definition for CAN_F3R2 register *******************/
mbed_official 403:91a4bea587f4 3041 #define CAN_F3R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 403:91a4bea587f4 3042 #define CAN_F3R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 403:91a4bea587f4 3043 #define CAN_F3R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 403:91a4bea587f4 3044 #define CAN_F3R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 403:91a4bea587f4 3045 #define CAN_F3R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 403:91a4bea587f4 3046 #define CAN_F3R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 403:91a4bea587f4 3047 #define CAN_F3R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 403:91a4bea587f4 3048 #define CAN_F3R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 403:91a4bea587f4 3049 #define CAN_F3R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 403:91a4bea587f4 3050 #define CAN_F3R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 403:91a4bea587f4 3051 #define CAN_F3R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 403:91a4bea587f4 3052 #define CAN_F3R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 403:91a4bea587f4 3053 #define CAN_F3R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 403:91a4bea587f4 3054 #define CAN_F3R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 403:91a4bea587f4 3055 #define CAN_F3R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 403:91a4bea587f4 3056 #define CAN_F3R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 403:91a4bea587f4 3057 #define CAN_F3R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 403:91a4bea587f4 3058 #define CAN_F3R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 403:91a4bea587f4 3059 #define CAN_F3R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 403:91a4bea587f4 3060 #define CAN_F3R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 403:91a4bea587f4 3061 #define CAN_F3R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 403:91a4bea587f4 3062 #define CAN_F3R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 403:91a4bea587f4 3063 #define CAN_F3R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 403:91a4bea587f4 3064 #define CAN_F3R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 403:91a4bea587f4 3065 #define CAN_F3R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 403:91a4bea587f4 3066 #define CAN_F3R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 403:91a4bea587f4 3067 #define CAN_F3R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 403:91a4bea587f4 3068 #define CAN_F3R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 403:91a4bea587f4 3069 #define CAN_F3R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 403:91a4bea587f4 3070 #define CAN_F3R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 403:91a4bea587f4 3071 #define CAN_F3R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 403:91a4bea587f4 3072 #define CAN_F3R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 403:91a4bea587f4 3073
mbed_official 403:91a4bea587f4 3074 /******************* Bit definition for CAN_F4R2 register *******************/
mbed_official 403:91a4bea587f4 3075 #define CAN_F4R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 403:91a4bea587f4 3076 #define CAN_F4R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 403:91a4bea587f4 3077 #define CAN_F4R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 403:91a4bea587f4 3078 #define CAN_F4R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 403:91a4bea587f4 3079 #define CAN_F4R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 403:91a4bea587f4 3080 #define CAN_F4R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 403:91a4bea587f4 3081 #define CAN_F4R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 403:91a4bea587f4 3082 #define CAN_F4R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 403:91a4bea587f4 3083 #define CAN_F4R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 403:91a4bea587f4 3084 #define CAN_F4R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 403:91a4bea587f4 3085 #define CAN_F4R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 403:91a4bea587f4 3086 #define CAN_F4R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 403:91a4bea587f4 3087 #define CAN_F4R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 403:91a4bea587f4 3088 #define CAN_F4R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 403:91a4bea587f4 3089 #define CAN_F4R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 403:91a4bea587f4 3090 #define CAN_F4R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 403:91a4bea587f4 3091 #define CAN_F4R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 403:91a4bea587f4 3092 #define CAN_F4R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 403:91a4bea587f4 3093 #define CAN_F4R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 403:91a4bea587f4 3094 #define CAN_F4R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 403:91a4bea587f4 3095 #define CAN_F4R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 403:91a4bea587f4 3096 #define CAN_F4R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 403:91a4bea587f4 3097 #define CAN_F4R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 403:91a4bea587f4 3098 #define CAN_F4R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 403:91a4bea587f4 3099 #define CAN_F4R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 403:91a4bea587f4 3100 #define CAN_F4R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 403:91a4bea587f4 3101 #define CAN_F4R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 403:91a4bea587f4 3102 #define CAN_F4R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 403:91a4bea587f4 3103 #define CAN_F4R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 403:91a4bea587f4 3104 #define CAN_F4R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 403:91a4bea587f4 3105 #define CAN_F4R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 403:91a4bea587f4 3106 #define CAN_F4R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 403:91a4bea587f4 3107
mbed_official 403:91a4bea587f4 3108 /******************* Bit definition for CAN_F5R2 register *******************/
mbed_official 403:91a4bea587f4 3109 #define CAN_F5R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 403:91a4bea587f4 3110 #define CAN_F5R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 403:91a4bea587f4 3111 #define CAN_F5R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 403:91a4bea587f4 3112 #define CAN_F5R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 403:91a4bea587f4 3113 #define CAN_F5R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 403:91a4bea587f4 3114 #define CAN_F5R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 403:91a4bea587f4 3115 #define CAN_F5R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 403:91a4bea587f4 3116 #define CAN_F5R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 403:91a4bea587f4 3117 #define CAN_F5R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 403:91a4bea587f4 3118 #define CAN_F5R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 403:91a4bea587f4 3119 #define CAN_F5R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 403:91a4bea587f4 3120 #define CAN_F5R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 403:91a4bea587f4 3121 #define CAN_F5R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 403:91a4bea587f4 3122 #define CAN_F5R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 403:91a4bea587f4 3123 #define CAN_F5R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 403:91a4bea587f4 3124 #define CAN_F5R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 403:91a4bea587f4 3125 #define CAN_F5R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 403:91a4bea587f4 3126 #define CAN_F5R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 403:91a4bea587f4 3127 #define CAN_F5R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 403:91a4bea587f4 3128 #define CAN_F5R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 403:91a4bea587f4 3129 #define CAN_F5R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 403:91a4bea587f4 3130 #define CAN_F5R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 403:91a4bea587f4 3131 #define CAN_F5R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 403:91a4bea587f4 3132 #define CAN_F5R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 403:91a4bea587f4 3133 #define CAN_F5R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 403:91a4bea587f4 3134 #define CAN_F5R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 403:91a4bea587f4 3135 #define CAN_F5R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 403:91a4bea587f4 3136 #define CAN_F5R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 403:91a4bea587f4 3137 #define CAN_F5R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 403:91a4bea587f4 3138 #define CAN_F5R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 403:91a4bea587f4 3139 #define CAN_F5R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 403:91a4bea587f4 3140 #define CAN_F5R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 403:91a4bea587f4 3141
mbed_official 403:91a4bea587f4 3142 /******************* Bit definition for CAN_F6R2 register *******************/
mbed_official 403:91a4bea587f4 3143 #define CAN_F6R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 403:91a4bea587f4 3144 #define CAN_F6R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 403:91a4bea587f4 3145 #define CAN_F6R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 403:91a4bea587f4 3146 #define CAN_F6R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 403:91a4bea587f4 3147 #define CAN_F6R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 403:91a4bea587f4 3148 #define CAN_F6R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 403:91a4bea587f4 3149 #define CAN_F6R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 403:91a4bea587f4 3150 #define CAN_F6R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 403:91a4bea587f4 3151 #define CAN_F6R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 403:91a4bea587f4 3152 #define CAN_F6R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 403:91a4bea587f4 3153 #define CAN_F6R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 403:91a4bea587f4 3154 #define CAN_F6R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 403:91a4bea587f4 3155 #define CAN_F6R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 403:91a4bea587f4 3156 #define CAN_F6R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 403:91a4bea587f4 3157 #define CAN_F6R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 403:91a4bea587f4 3158 #define CAN_F6R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 403:91a4bea587f4 3159 #define CAN_F6R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 403:91a4bea587f4 3160 #define CAN_F6R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 403:91a4bea587f4 3161 #define CAN_F6R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 403:91a4bea587f4 3162 #define CAN_F6R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 403:91a4bea587f4 3163 #define CAN_F6R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 403:91a4bea587f4 3164 #define CAN_F6R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 403:91a4bea587f4 3165 #define CAN_F6R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 403:91a4bea587f4 3166 #define CAN_F6R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 403:91a4bea587f4 3167 #define CAN_F6R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 403:91a4bea587f4 3168 #define CAN_F6R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 403:91a4bea587f4 3169 #define CAN_F6R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 403:91a4bea587f4 3170 #define CAN_F6R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 403:91a4bea587f4 3171 #define CAN_F6R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 403:91a4bea587f4 3172 #define CAN_F6R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 403:91a4bea587f4 3173 #define CAN_F6R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 403:91a4bea587f4 3174 #define CAN_F6R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 403:91a4bea587f4 3175
mbed_official 403:91a4bea587f4 3176 /******************* Bit definition for CAN_F7R2 register *******************/
mbed_official 403:91a4bea587f4 3177 #define CAN_F7R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 403:91a4bea587f4 3178 #define CAN_F7R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 403:91a4bea587f4 3179 #define CAN_F7R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 403:91a4bea587f4 3180 #define CAN_F7R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 403:91a4bea587f4 3181 #define CAN_F7R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 403:91a4bea587f4 3182 #define CAN_F7R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 403:91a4bea587f4 3183 #define CAN_F7R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 403:91a4bea587f4 3184 #define CAN_F7R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 403:91a4bea587f4 3185 #define CAN_F7R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 403:91a4bea587f4 3186 #define CAN_F7R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 403:91a4bea587f4 3187 #define CAN_F7R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 403:91a4bea587f4 3188 #define CAN_F7R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 403:91a4bea587f4 3189 #define CAN_F7R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 403:91a4bea587f4 3190 #define CAN_F7R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 403:91a4bea587f4 3191 #define CAN_F7R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 403:91a4bea587f4 3192 #define CAN_F7R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 403:91a4bea587f4 3193 #define CAN_F7R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 403:91a4bea587f4 3194 #define CAN_F7R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 403:91a4bea587f4 3195 #define CAN_F7R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 403:91a4bea587f4 3196 #define CAN_F7R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 403:91a4bea587f4 3197 #define CAN_F7R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 403:91a4bea587f4 3198 #define CAN_F7R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 403:91a4bea587f4 3199 #define CAN_F7R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 403:91a4bea587f4 3200 #define CAN_F7R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 403:91a4bea587f4 3201 #define CAN_F7R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 403:91a4bea587f4 3202 #define CAN_F7R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 403:91a4bea587f4 3203 #define CAN_F7R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 403:91a4bea587f4 3204 #define CAN_F7R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 403:91a4bea587f4 3205 #define CAN_F7R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 403:91a4bea587f4 3206 #define CAN_F7R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 403:91a4bea587f4 3207 #define CAN_F7R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 403:91a4bea587f4 3208 #define CAN_F7R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 403:91a4bea587f4 3209
mbed_official 403:91a4bea587f4 3210 /******************* Bit definition for CAN_F8R2 register *******************/
mbed_official 403:91a4bea587f4 3211 #define CAN_F8R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 403:91a4bea587f4 3212 #define CAN_F8R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 403:91a4bea587f4 3213 #define CAN_F8R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 403:91a4bea587f4 3214 #define CAN_F8R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 403:91a4bea587f4 3215 #define CAN_F8R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 403:91a4bea587f4 3216 #define CAN_F8R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 403:91a4bea587f4 3217 #define CAN_F8R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 403:91a4bea587f4 3218 #define CAN_F8R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 403:91a4bea587f4 3219 #define CAN_F8R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 403:91a4bea587f4 3220 #define CAN_F8R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 403:91a4bea587f4 3221 #define CAN_F8R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 403:91a4bea587f4 3222 #define CAN_F8R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 403:91a4bea587f4 3223 #define CAN_F8R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 403:91a4bea587f4 3224 #define CAN_F8R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 403:91a4bea587f4 3225 #define CAN_F8R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 403:91a4bea587f4 3226 #define CAN_F8R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 403:91a4bea587f4 3227 #define CAN_F8R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 403:91a4bea587f4 3228 #define CAN_F8R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 403:91a4bea587f4 3229 #define CAN_F8R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 403:91a4bea587f4 3230 #define CAN_F8R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 403:91a4bea587f4 3231 #define CAN_F8R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 403:91a4bea587f4 3232 #define CAN_F8R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 403:91a4bea587f4 3233 #define CAN_F8R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 403:91a4bea587f4 3234 #define CAN_F8R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 403:91a4bea587f4 3235 #define CAN_F8R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 403:91a4bea587f4 3236 #define CAN_F8R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 403:91a4bea587f4 3237 #define CAN_F8R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 403:91a4bea587f4 3238 #define CAN_F8R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 403:91a4bea587f4 3239 #define CAN_F8R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 403:91a4bea587f4 3240 #define CAN_F8R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 403:91a4bea587f4 3241 #define CAN_F8R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 403:91a4bea587f4 3242 #define CAN_F8R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 403:91a4bea587f4 3243
mbed_official 403:91a4bea587f4 3244 /******************* Bit definition for CAN_F9R2 register *******************/
mbed_official 403:91a4bea587f4 3245 #define CAN_F9R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 403:91a4bea587f4 3246 #define CAN_F9R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 403:91a4bea587f4 3247 #define CAN_F9R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 403:91a4bea587f4 3248 #define CAN_F9R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 403:91a4bea587f4 3249 #define CAN_F9R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 403:91a4bea587f4 3250 #define CAN_F9R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 403:91a4bea587f4 3251 #define CAN_F9R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 403:91a4bea587f4 3252 #define CAN_F9R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 403:91a4bea587f4 3253 #define CAN_F9R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 403:91a4bea587f4 3254 #define CAN_F9R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 403:91a4bea587f4 3255 #define CAN_F9R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 403:91a4bea587f4 3256 #define CAN_F9R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 403:91a4bea587f4 3257 #define CAN_F9R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 403:91a4bea587f4 3258 #define CAN_F9R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 403:91a4bea587f4 3259 #define CAN_F9R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 403:91a4bea587f4 3260 #define CAN_F9R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 403:91a4bea587f4 3261 #define CAN_F9R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 403:91a4bea587f4 3262 #define CAN_F9R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 403:91a4bea587f4 3263 #define CAN_F9R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 403:91a4bea587f4 3264 #define CAN_F9R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 403:91a4bea587f4 3265 #define CAN_F9R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 403:91a4bea587f4 3266 #define CAN_F9R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 403:91a4bea587f4 3267 #define CAN_F9R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 403:91a4bea587f4 3268 #define CAN_F9R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 403:91a4bea587f4 3269 #define CAN_F9R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 403:91a4bea587f4 3270 #define CAN_F9R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 403:91a4bea587f4 3271 #define CAN_F9R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 403:91a4bea587f4 3272 #define CAN_F9R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 403:91a4bea587f4 3273 #define CAN_F9R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 403:91a4bea587f4 3274 #define CAN_F9R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 403:91a4bea587f4 3275 #define CAN_F9R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 403:91a4bea587f4 3276 #define CAN_F9R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 403:91a4bea587f4 3277
mbed_official 403:91a4bea587f4 3278 /******************* Bit definition for CAN_F10R2 register ******************/
mbed_official 403:91a4bea587f4 3279 #define CAN_F10R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 403:91a4bea587f4 3280 #define CAN_F10R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 403:91a4bea587f4 3281 #define CAN_F10R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 403:91a4bea587f4 3282 #define CAN_F10R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 403:91a4bea587f4 3283 #define CAN_F10R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 403:91a4bea587f4 3284 #define CAN_F10R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 403:91a4bea587f4 3285 #define CAN_F10R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 403:91a4bea587f4 3286 #define CAN_F10R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 403:91a4bea587f4 3287 #define CAN_F10R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 403:91a4bea587f4 3288 #define CAN_F10R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 403:91a4bea587f4 3289 #define CAN_F10R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 403:91a4bea587f4 3290 #define CAN_F10R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 403:91a4bea587f4 3291 #define CAN_F10R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 403:91a4bea587f4 3292 #define CAN_F10R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 403:91a4bea587f4 3293 #define CAN_F10R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 403:91a4bea587f4 3294 #define CAN_F10R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 403:91a4bea587f4 3295 #define CAN_F10R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 403:91a4bea587f4 3296 #define CAN_F10R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 403:91a4bea587f4 3297 #define CAN_F10R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 403:91a4bea587f4 3298 #define CAN_F10R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 403:91a4bea587f4 3299 #define CAN_F10R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 403:91a4bea587f4 3300 #define CAN_F10R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 403:91a4bea587f4 3301 #define CAN_F10R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 403:91a4bea587f4 3302 #define CAN_F10R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 403:91a4bea587f4 3303 #define CAN_F10R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 403:91a4bea587f4 3304 #define CAN_F10R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 403:91a4bea587f4 3305 #define CAN_F10R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 403:91a4bea587f4 3306 #define CAN_F10R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 403:91a4bea587f4 3307 #define CAN_F10R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 403:91a4bea587f4 3308 #define CAN_F10R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 403:91a4bea587f4 3309 #define CAN_F10R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 403:91a4bea587f4 3310 #define CAN_F10R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 403:91a4bea587f4 3311
mbed_official 403:91a4bea587f4 3312 /******************* Bit definition for CAN_F11R2 register ******************/
mbed_official 403:91a4bea587f4 3313 #define CAN_F11R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 403:91a4bea587f4 3314 #define CAN_F11R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 403:91a4bea587f4 3315 #define CAN_F11R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 403:91a4bea587f4 3316 #define CAN_F11R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 403:91a4bea587f4 3317 #define CAN_F11R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 403:91a4bea587f4 3318 #define CAN_F11R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 403:91a4bea587f4 3319 #define CAN_F11R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 403:91a4bea587f4 3320 #define CAN_F11R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 403:91a4bea587f4 3321 #define CAN_F11R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 403:91a4bea587f4 3322 #define CAN_F11R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 403:91a4bea587f4 3323 #define CAN_F11R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 403:91a4bea587f4 3324 #define CAN_F11R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 403:91a4bea587f4 3325 #define CAN_F11R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 403:91a4bea587f4 3326 #define CAN_F11R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 403:91a4bea587f4 3327 #define CAN_F11R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 403:91a4bea587f4 3328 #define CAN_F11R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 403:91a4bea587f4 3329 #define CAN_F11R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 403:91a4bea587f4 3330 #define CAN_F11R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 403:91a4bea587f4 3331 #define CAN_F11R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 403:91a4bea587f4 3332 #define CAN_F11R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 403:91a4bea587f4 3333 #define CAN_F11R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 403:91a4bea587f4 3334 #define CAN_F11R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 403:91a4bea587f4 3335 #define CAN_F11R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 403:91a4bea587f4 3336 #define CAN_F11R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 403:91a4bea587f4 3337 #define CAN_F11R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 403:91a4bea587f4 3338 #define CAN_F11R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 403:91a4bea587f4 3339 #define CAN_F11R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 403:91a4bea587f4 3340 #define CAN_F11R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 403:91a4bea587f4 3341 #define CAN_F11R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 403:91a4bea587f4 3342 #define CAN_F11R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 403:91a4bea587f4 3343 #define CAN_F11R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 403:91a4bea587f4 3344 #define CAN_F11R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 403:91a4bea587f4 3345
mbed_official 403:91a4bea587f4 3346 /******************* Bit definition for CAN_F12R2 register ******************/
mbed_official 403:91a4bea587f4 3347 #define CAN_F12R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 403:91a4bea587f4 3348 #define CAN_F12R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 403:91a4bea587f4 3349 #define CAN_F12R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 403:91a4bea587f4 3350 #define CAN_F12R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 403:91a4bea587f4 3351 #define CAN_F12R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 403:91a4bea587f4 3352 #define CAN_F12R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 403:91a4bea587f4 3353 #define CAN_F12R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 403:91a4bea587f4 3354 #define CAN_F12R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 403:91a4bea587f4 3355 #define CAN_F12R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 403:91a4bea587f4 3356 #define CAN_F12R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 403:91a4bea587f4 3357 #define CAN_F12R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 403:91a4bea587f4 3358 #define CAN_F12R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 403:91a4bea587f4 3359 #define CAN_F12R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 403:91a4bea587f4 3360 #define CAN_F12R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 403:91a4bea587f4 3361 #define CAN_F12R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 403:91a4bea587f4 3362 #define CAN_F12R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 403:91a4bea587f4 3363 #define CAN_F12R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 403:91a4bea587f4 3364 #define CAN_F12R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 403:91a4bea587f4 3365 #define CAN_F12R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 403:91a4bea587f4 3366 #define CAN_F12R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 403:91a4bea587f4 3367 #define CAN_F12R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 403:91a4bea587f4 3368 #define CAN_F12R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 403:91a4bea587f4 3369 #define CAN_F12R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 403:91a4bea587f4 3370 #define CAN_F12R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 403:91a4bea587f4 3371 #define CAN_F12R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 403:91a4bea587f4 3372 #define CAN_F12R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 403:91a4bea587f4 3373 #define CAN_F12R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 403:91a4bea587f4 3374 #define CAN_F12R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 403:91a4bea587f4 3375 #define CAN_F12R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 403:91a4bea587f4 3376 #define CAN_F12R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 403:91a4bea587f4 3377 #define CAN_F12R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 403:91a4bea587f4 3378 #define CAN_F12R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 403:91a4bea587f4 3379
mbed_official 403:91a4bea587f4 3380 /******************* Bit definition for CAN_F13R2 register ******************/
mbed_official 403:91a4bea587f4 3381 #define CAN_F13R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 403:91a4bea587f4 3382 #define CAN_F13R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 403:91a4bea587f4 3383 #define CAN_F13R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 403:91a4bea587f4 3384 #define CAN_F13R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 403:91a4bea587f4 3385 #define CAN_F13R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 403:91a4bea587f4 3386 #define CAN_F13R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 403:91a4bea587f4 3387 #define CAN_F13R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 403:91a4bea587f4 3388 #define CAN_F13R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 403:91a4bea587f4 3389 #define CAN_F13R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 403:91a4bea587f4 3390 #define CAN_F13R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 403:91a4bea587f4 3391 #define CAN_F13R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 403:91a4bea587f4 3392 #define CAN_F13R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 403:91a4bea587f4 3393 #define CAN_F13R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 403:91a4bea587f4 3394 #define CAN_F13R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 403:91a4bea587f4 3395 #define CAN_F13R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 403:91a4bea587f4 3396 #define CAN_F13R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 403:91a4bea587f4 3397 #define CAN_F13R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 403:91a4bea587f4 3398 #define CAN_F13R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 403:91a4bea587f4 3399 #define CAN_F13R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 403:91a4bea587f4 3400 #define CAN_F13R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 403:91a4bea587f4 3401 #define CAN_F13R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 403:91a4bea587f4 3402 #define CAN_F13R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 403:91a4bea587f4 3403 #define CAN_F13R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 403:91a4bea587f4 3404 #define CAN_F13R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 403:91a4bea587f4 3405 #define CAN_F13R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 403:91a4bea587f4 3406 #define CAN_F13R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 403:91a4bea587f4 3407 #define CAN_F13R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 403:91a4bea587f4 3408 #define CAN_F13R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 403:91a4bea587f4 3409 #define CAN_F13R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 403:91a4bea587f4 3410 #define CAN_F13R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 403:91a4bea587f4 3411 #define CAN_F13R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 403:91a4bea587f4 3412 #define CAN_F13R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 403:91a4bea587f4 3413
mbed_official 403:91a4bea587f4 3414 /******************************************************************************/
mbed_official 403:91a4bea587f4 3415 /* */
mbed_official 403:91a4bea587f4 3416 /* CRC calculation unit (CRC) */
mbed_official 403:91a4bea587f4 3417 /* */
mbed_official 403:91a4bea587f4 3418 /******************************************************************************/
mbed_official 403:91a4bea587f4 3419 /******************* Bit definition for CRC_DR register *********************/
mbed_official 403:91a4bea587f4 3420 #define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
mbed_official 403:91a4bea587f4 3421
mbed_official 403:91a4bea587f4 3422 /******************* Bit definition for CRC_IDR register ********************/
mbed_official 403:91a4bea587f4 3423 #define CRC_IDR_IDR ((uint32_t)0xFF) /*!< General-purpose 8-bit data register bits */
mbed_official 403:91a4bea587f4 3424
mbed_official 403:91a4bea587f4 3425 /******************** Bit definition for CRC_CR register ********************/
mbed_official 403:91a4bea587f4 3426 #define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET the CRC computation unit bit */
mbed_official 403:91a4bea587f4 3427 #define CRC_CR_POLYSIZE ((uint32_t)0x00000018) /*!< Polynomial size bits */
mbed_official 403:91a4bea587f4 3428 #define CRC_CR_POLYSIZE_0 ((uint32_t)0x00000008) /*!< Polynomial size bit 0 */
mbed_official 403:91a4bea587f4 3429 #define CRC_CR_POLYSIZE_1 ((uint32_t)0x00000010) /*!< Polynomial size bit 1 */
mbed_official 403:91a4bea587f4 3430 #define CRC_CR_REV_IN ((uint32_t)0x00000060) /*!< REV_IN Reverse Input Data bits */
mbed_official 403:91a4bea587f4 3431 #define CRC_CR_REV_IN_0 ((uint32_t)0x00000020) /*!< Bit 0 */
mbed_official 403:91a4bea587f4 3432 #define CRC_CR_REV_IN_1 ((uint32_t)0x00000040) /*!< Bit 1 */
mbed_official 403:91a4bea587f4 3433 #define CRC_CR_REV_OUT ((uint32_t)0x00000080) /*!< REV_OUT Reverse Output Data bits */
mbed_official 403:91a4bea587f4 3434
mbed_official 403:91a4bea587f4 3435 /******************* Bit definition for CRC_INIT register *******************/
mbed_official 403:91a4bea587f4 3436 #define CRC_INIT_INIT ((uint32_t)0xFFFFFFFF) /*!< Initial CRC value bits */
mbed_official 403:91a4bea587f4 3437
mbed_official 403:91a4bea587f4 3438 /******************* Bit definition for CRC_POL register ********************/
mbed_official 403:91a4bea587f4 3439 #define CRC_POL_POL ((uint32_t)0xFFFFFFFF) /*!< Coefficients of the polynomial */
mbed_official 403:91a4bea587f4 3440
mbed_official 403:91a4bea587f4 3441 /******************************************************************************/
mbed_official 403:91a4bea587f4 3442 /* */
mbed_official 403:91a4bea587f4 3443 /* Digital to Analog Converter (DAC) */
mbed_official 403:91a4bea587f4 3444 /* */
mbed_official 403:91a4bea587f4 3445 /******************************************************************************/
mbed_official 403:91a4bea587f4 3446 /******************** Bit definition for DAC_CR register ********************/
mbed_official 403:91a4bea587f4 3447 #define DAC_CR_EN1 ((uint32_t)0x00000001) /*!< DAC channel1 enable */
mbed_official 403:91a4bea587f4 3448 #define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!< DAC channel1 output buffer disable */
mbed_official 403:91a4bea587f4 3449 #define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!< DAC channel1 Trigger enable */
mbed_official 403:91a4bea587f4 3450
mbed_official 403:91a4bea587f4 3451 #define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */
mbed_official 403:91a4bea587f4 3452 #define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!< Bit 0 */
mbed_official 403:91a4bea587f4 3453 #define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!< Bit 1 */
mbed_official 403:91a4bea587f4 3454 #define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!< Bit 2 */
mbed_official 403:91a4bea587f4 3455
mbed_official 403:91a4bea587f4 3456 #define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
mbed_official 403:91a4bea587f4 3457 #define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!< Bit 0 */
mbed_official 403:91a4bea587f4 3458 #define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!< Bit 1 */
mbed_official 403:91a4bea587f4 3459
mbed_official 403:91a4bea587f4 3460 #define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
mbed_official 403:91a4bea587f4 3461 #define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!< Bit 0 */
mbed_official 403:91a4bea587f4 3462 #define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!< Bit 1 */
mbed_official 403:91a4bea587f4 3463 #define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!< Bit 2 */
mbed_official 403:91a4bea587f4 3464 #define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!< Bit 3 */
mbed_official 403:91a4bea587f4 3465
mbed_official 403:91a4bea587f4 3466 #define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!< DAC channel1 DMA enable */
mbed_official 403:91a4bea587f4 3467 #define DAC_CR_DMAUDRIE1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA underrun IT enable */
mbed_official 403:91a4bea587f4 3468 #define DAC_CR_EN2 ((uint32_t)0x00010000) /*!< DAC channel2 enable */
mbed_official 403:91a4bea587f4 3469 #define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!< DAC channel2 output buffer disable */
mbed_official 403:91a4bea587f4 3470 #define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!< DAC channel2 Trigger enable */
mbed_official 403:91a4bea587f4 3471
mbed_official 403:91a4bea587f4 3472 #define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */
mbed_official 403:91a4bea587f4 3473 #define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!< Bit 0 */
mbed_official 403:91a4bea587f4 3474 #define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!< Bit 1 */
mbed_official 403:91a4bea587f4 3475 #define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!< Bit 2 */
mbed_official 403:91a4bea587f4 3476
mbed_official 403:91a4bea587f4 3477 #define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
mbed_official 403:91a4bea587f4 3478 #define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!< Bit 0 */
mbed_official 403:91a4bea587f4 3479 #define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!< Bit 1 */
mbed_official 403:91a4bea587f4 3480
mbed_official 403:91a4bea587f4 3481 #define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
mbed_official 403:91a4bea587f4 3482 #define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!< Bit 0 */
mbed_official 403:91a4bea587f4 3483 #define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!< Bit 1 */
mbed_official 403:91a4bea587f4 3484 #define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!< Bit 2 */
mbed_official 403:91a4bea587f4 3485 #define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!< Bit 3 */
mbed_official 403:91a4bea587f4 3486
mbed_official 403:91a4bea587f4 3487 #define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!< DAC channel2 DMA enabled */
mbed_official 403:91a4bea587f4 3488 #define DAC_CR_DMAUDRIE2 ((uint32_t)0x20000000) /*!< DAC channel2 DMA underrun IT enable */
mbed_official 403:91a4bea587f4 3489
mbed_official 403:91a4bea587f4 3490 /***************** Bit definition for DAC_SWTRIGR register ******************/
mbed_official 403:91a4bea587f4 3491 #define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x00000001) /*!< DAC channel1 software trigger */
mbed_official 403:91a4bea587f4 3492 #define DAC_SWTRIGR_SWTRIG2 ((uint32_t)0x00000002) /*!< DAC channel2 software trigger */
mbed_official 403:91a4bea587f4 3493
mbed_official 403:91a4bea587f4 3494 /***************** Bit definition for DAC_DHR12R1 register ******************/
mbed_official 403:91a4bea587f4 3495 #define DAC_DHR12R1_DACC1DHR ((uint32_t)0x00000FFF) /*!< DAC channel1 12-bit Right aligned data */
mbed_official 403:91a4bea587f4 3496
mbed_official 403:91a4bea587f4 3497 /***************** Bit definition for DAC_DHR12L1 register ******************/
mbed_official 403:91a4bea587f4 3498 #define DAC_DHR12L1_DACC1DHR ((uint32_t)0x0000FFF0) /*!< DAC channel1 12-bit Left aligned data */
mbed_official 403:91a4bea587f4 3499
mbed_official 403:91a4bea587f4 3500 /****************** Bit definition for DAC_DHR8R1 register ******************/
mbed_official 403:91a4bea587f4 3501 #define DAC_DHR8R1_DACC1DHR ((uint32_t)0x000000FF) /*!< DAC channel1 8-bit Right aligned data */
mbed_official 403:91a4bea587f4 3502
mbed_official 403:91a4bea587f4 3503 /***************** Bit definition for DAC_DHR12R2 register ******************/
mbed_official 403:91a4bea587f4 3504 #define DAC_DHR12R2_DACC2DHR ((uint32_t)0x00000FFF) /*!< DAC channel2 12-bit Right aligned data */
mbed_official 403:91a4bea587f4 3505
mbed_official 403:91a4bea587f4 3506 /***************** Bit definition for DAC_DHR12L2 register ******************/
mbed_official 403:91a4bea587f4 3507 #define DAC_DHR12L2_DACC2DHR ((uint32_t)0x0000FFF0) /*!< DAC channel2 12-bit Left aligned data */
mbed_official 403:91a4bea587f4 3508
mbed_official 403:91a4bea587f4 3509 /****************** Bit definition for DAC_DHR8R2 register ******************/
mbed_official 403:91a4bea587f4 3510 #define DAC_DHR8R2_DACC2DHR ((uint32_t)0x000000FF) /*!< DAC channel2 8-bit Right aligned data */
mbed_official 403:91a4bea587f4 3511
mbed_official 403:91a4bea587f4 3512 /***************** Bit definition for DAC_DHR12RD register ******************/
mbed_official 403:91a4bea587f4 3513 #define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!< DAC channel1 12-bit Right aligned data */
mbed_official 403:91a4bea587f4 3514 #define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!< DAC channel2 12-bit Right aligned data */
mbed_official 403:91a4bea587f4 3515
mbed_official 403:91a4bea587f4 3516 /***************** Bit definition for DAC_DHR12LD register ******************/
mbed_official 403:91a4bea587f4 3517 #define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!< DAC channel1 12-bit Left aligned data */
mbed_official 403:91a4bea587f4 3518 #define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!< DAC channel2 12-bit Left aligned data */
mbed_official 403:91a4bea587f4 3519
mbed_official 403:91a4bea587f4 3520 /****************** Bit definition for DAC_DHR8RD register ******************/
mbed_official 403:91a4bea587f4 3521 #define DAC_DHR8RD_DACC1DHR ((uint32_t)0x000000FF) /*!< DAC channel1 8-bit Right aligned data */
mbed_official 403:91a4bea587f4 3522 #define DAC_DHR8RD_DACC2DHR ((uint32_t)0x0000FF00) /*!< DAC channel2 8-bit Right aligned data */
mbed_official 403:91a4bea587f4 3523
mbed_official 403:91a4bea587f4 3524 /******************* Bit definition for DAC_DOR1 register *******************/
mbed_official 403:91a4bea587f4 3525 #define DAC_DOR1_DACC1DOR ((uint32_t)0x00000FFF) /*!< DAC channel1 data output */
mbed_official 403:91a4bea587f4 3526
mbed_official 403:91a4bea587f4 3527 /******************* Bit definition for DAC_DOR2 register *******************/
mbed_official 403:91a4bea587f4 3528 #define DAC_DOR2_DACC2DOR ((uint32_t)0x00000FFF) /*!< DAC channel2 data output */
mbed_official 403:91a4bea587f4 3529
mbed_official 403:91a4bea587f4 3530 /******************** Bit definition for DAC_SR register ********************/
mbed_official 403:91a4bea587f4 3531 #define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA underrun flag */
mbed_official 403:91a4bea587f4 3532 #define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!< DAC channel2 DMA underrun flag */
mbed_official 403:91a4bea587f4 3533
mbed_official 403:91a4bea587f4 3534 /******************************************************************************/
mbed_official 403:91a4bea587f4 3535 /* */
mbed_official 403:91a4bea587f4 3536 /* Debug MCU (DBGMCU) */
mbed_official 403:91a4bea587f4 3537 /* */
mbed_official 403:91a4bea587f4 3538 /******************************************************************************/
mbed_official 403:91a4bea587f4 3539 /******************** Bit definition for DBGMCU_IDCODE register *************/
mbed_official 403:91a4bea587f4 3540 #define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF)
mbed_official 403:91a4bea587f4 3541 #define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000)
mbed_official 403:91a4bea587f4 3542
mbed_official 403:91a4bea587f4 3543 /******************** Bit definition for DBGMCU_CR register *****************/
mbed_official 403:91a4bea587f4 3544 #define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001)
mbed_official 403:91a4bea587f4 3545 #define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002)
mbed_official 403:91a4bea587f4 3546 #define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004)
mbed_official 403:91a4bea587f4 3547 #define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020)
mbed_official 403:91a4bea587f4 3548
mbed_official 403:91a4bea587f4 3549 #define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0)
mbed_official 403:91a4bea587f4 3550 #define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040)/*!<Bit 0 */
mbed_official 403:91a4bea587f4 3551 #define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080)/*!<Bit 1 */
mbed_official 403:91a4bea587f4 3552
mbed_official 403:91a4bea587f4 3553 /******************** Bit definition for DBGMCU_APB1_FZ register ************/
mbed_official 403:91a4bea587f4 3554 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001)
mbed_official 403:91a4bea587f4 3555 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002)
mbed_official 403:91a4bea587f4 3556 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP ((uint32_t)0x00000004)
mbed_official 403:91a4bea587f4 3557 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010)
mbed_official 403:91a4bea587f4 3558 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020)
mbed_official 403:91a4bea587f4 3559 #define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400)
mbed_official 403:91a4bea587f4 3560 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800)
mbed_official 403:91a4bea587f4 3561 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000)
mbed_official 403:91a4bea587f4 3562 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000)
mbed_official 403:91a4bea587f4 3563 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000)
mbed_official 403:91a4bea587f4 3564 #define DBGMCU_APB1_FZ_DBG_CAN_STOP ((uint32_t)0x02000000)
mbed_official 403:91a4bea587f4 3565
mbed_official 403:91a4bea587f4 3566 /******************** Bit definition for DBGMCU_APB2_FZ register ************/
mbed_official 403:91a4bea587f4 3567 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP ((uint32_t)0x00000001)
mbed_official 403:91a4bea587f4 3568 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP ((uint32_t)0x00000002)
mbed_official 403:91a4bea587f4 3569 #define DBGMCU_APB2_FZ_DBG_TIM15_STOP ((uint32_t)0x00000004)
mbed_official 403:91a4bea587f4 3570 #define DBGMCU_APB2_FZ_DBG_TIM16_STOP ((uint32_t)0x00000008)
mbed_official 403:91a4bea587f4 3571 #define DBGMCU_APB2_FZ_DBG_TIM17_STOP ((uint32_t)0x00000010)
mbed_official 403:91a4bea587f4 3572
mbed_official 403:91a4bea587f4 3573 /******************************************************************************/
mbed_official 403:91a4bea587f4 3574 /* */
mbed_official 403:91a4bea587f4 3575 /* DMA Controller (DMA) */
mbed_official 403:91a4bea587f4 3576 /* */
mbed_official 403:91a4bea587f4 3577 /******************************************************************************/
mbed_official 403:91a4bea587f4 3578 /******************* Bit definition for DMA_ISR register ********************/
mbed_official 403:91a4bea587f4 3579 #define DMA_ISR_GIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */
mbed_official 403:91a4bea587f4 3580 #define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */
mbed_official 403:91a4bea587f4 3581 #define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */
mbed_official 403:91a4bea587f4 3582 #define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */
mbed_official 403:91a4bea587f4 3583 #define DMA_ISR_GIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */
mbed_official 403:91a4bea587f4 3584 #define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */
mbed_official 403:91a4bea587f4 3585 #define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */
mbed_official 403:91a4bea587f4 3586 #define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */
mbed_official 403:91a4bea587f4 3587 #define DMA_ISR_GIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */
mbed_official 403:91a4bea587f4 3588 #define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */
mbed_official 403:91a4bea587f4 3589 #define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */
mbed_official 403:91a4bea587f4 3590 #define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */
mbed_official 403:91a4bea587f4 3591 #define DMA_ISR_GIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */
mbed_official 403:91a4bea587f4 3592 #define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */
mbed_official 403:91a4bea587f4 3593 #define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */
mbed_official 403:91a4bea587f4 3594 #define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */
mbed_official 403:91a4bea587f4 3595 #define DMA_ISR_GIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */
mbed_official 403:91a4bea587f4 3596 #define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */
mbed_official 403:91a4bea587f4 3597 #define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */
mbed_official 403:91a4bea587f4 3598 #define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */
mbed_official 403:91a4bea587f4 3599 #define DMA_ISR_GIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt flag */
mbed_official 403:91a4bea587f4 3600 #define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete flag */
mbed_official 403:91a4bea587f4 3601 #define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer flag */
mbed_official 403:91a4bea587f4 3602 #define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error flag */
mbed_official 403:91a4bea587f4 3603 #define DMA_ISR_GIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt flag */
mbed_official 403:91a4bea587f4 3604 #define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete flag */
mbed_official 403:91a4bea587f4 3605 #define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer flag */
mbed_official 403:91a4bea587f4 3606 #define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error flag */
mbed_official 403:91a4bea587f4 3607
mbed_official 403:91a4bea587f4 3608 /******************* Bit definition for DMA_IFCR register *******************/
mbed_official 403:91a4bea587f4 3609 #define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clear */
mbed_official 403:91a4bea587f4 3610 #define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */
mbed_official 403:91a4bea587f4 3611 #define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */
mbed_official 403:91a4bea587f4 3612 #define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */
mbed_official 403:91a4bea587f4 3613 #define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */
mbed_official 403:91a4bea587f4 3614 #define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */
mbed_official 403:91a4bea587f4 3615 #define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */
mbed_official 403:91a4bea587f4 3616 #define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */
mbed_official 403:91a4bea587f4 3617 #define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */
mbed_official 403:91a4bea587f4 3618 #define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */
mbed_official 403:91a4bea587f4 3619 #define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */
mbed_official 403:91a4bea587f4 3620 #define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */
mbed_official 403:91a4bea587f4 3621 #define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */
mbed_official 403:91a4bea587f4 3622 #define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */
mbed_official 403:91a4bea587f4 3623 #define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */
mbed_official 403:91a4bea587f4 3624 #define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */
mbed_official 403:91a4bea587f4 3625 #define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */
mbed_official 403:91a4bea587f4 3626 #define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */
mbed_official 403:91a4bea587f4 3627 #define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */
mbed_official 403:91a4bea587f4 3628 #define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */
mbed_official 403:91a4bea587f4 3629 #define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt clear */
mbed_official 403:91a4bea587f4 3630 #define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete clear */
mbed_official 403:91a4bea587f4 3631 #define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer clear */
mbed_official 403:91a4bea587f4 3632 #define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error clear */
mbed_official 403:91a4bea587f4 3633 #define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt clear */
mbed_official 403:91a4bea587f4 3634 #define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete clear */
mbed_official 403:91a4bea587f4 3635 #define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer clear */
mbed_official 403:91a4bea587f4 3636 #define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error clear */
mbed_official 403:91a4bea587f4 3637
mbed_official 403:91a4bea587f4 3638 /******************* Bit definition for DMA_CCR register ********************/
mbed_official 403:91a4bea587f4 3639 #define DMA_CCR_EN ((uint32_t)0x00000001) /*!< Channel enable */
mbed_official 403:91a4bea587f4 3640 #define DMA_CCR_TCIE ((uint32_t)0x00000002) /*!< Transfer complete interrupt enable */
mbed_official 403:91a4bea587f4 3641 #define DMA_CCR_HTIE ((uint32_t)0x00000004) /*!< Half Transfer interrupt enable */
mbed_official 403:91a4bea587f4 3642 #define DMA_CCR_TEIE ((uint32_t)0x00000008) /*!< Transfer error interrupt enable */
mbed_official 403:91a4bea587f4 3643 #define DMA_CCR_DIR ((uint32_t)0x00000010) /*!< Data transfer direction */
mbed_official 403:91a4bea587f4 3644 #define DMA_CCR_CIRC ((uint32_t)0x00000020) /*!< Circular mode */
mbed_official 403:91a4bea587f4 3645 #define DMA_CCR_PINC ((uint32_t)0x00000040) /*!< Peripheral increment mode */
mbed_official 403:91a4bea587f4 3646 #define DMA_CCR_MINC ((uint32_t)0x00000080) /*!< Memory increment mode */
mbed_official 403:91a4bea587f4 3647
mbed_official 403:91a4bea587f4 3648 #define DMA_CCR_PSIZE ((uint32_t)0x00000300) /*!< PSIZE[1:0] bits (Peripheral size) */
mbed_official 403:91a4bea587f4 3649 #define DMA_CCR_PSIZE_0 ((uint32_t)0x00000100) /*!< Bit 0 */
mbed_official 403:91a4bea587f4 3650 #define DMA_CCR_PSIZE_1 ((uint32_t)0x00000200) /*!< Bit 1 */
mbed_official 403:91a4bea587f4 3651
mbed_official 403:91a4bea587f4 3652 #define DMA_CCR_MSIZE ((uint32_t)0x00000C00) /*!< MSIZE[1:0] bits (Memory size) */
mbed_official 403:91a4bea587f4 3653 #define DMA_CCR_MSIZE_0 ((uint32_t)0x00000400) /*!< Bit 0 */
mbed_official 403:91a4bea587f4 3654 #define DMA_CCR_MSIZE_1 ((uint32_t)0x00000800) /*!< Bit 1 */
mbed_official 403:91a4bea587f4 3655
mbed_official 403:91a4bea587f4 3656 #define DMA_CCR_PL ((uint32_t)0x00003000) /*!< PL[1:0] bits(Channel Priority level)*/
mbed_official 403:91a4bea587f4 3657 #define DMA_CCR_PL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
mbed_official 403:91a4bea587f4 3658 #define DMA_CCR_PL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
mbed_official 403:91a4bea587f4 3659
mbed_official 403:91a4bea587f4 3660 #define DMA_CCR_MEM2MEM ((uint32_t)0x00004000) /*!< Memory to memory mode */
mbed_official 403:91a4bea587f4 3661
mbed_official 403:91a4bea587f4 3662 /****************** Bit definition for DMA_CNDTR register *******************/
mbed_official 403:91a4bea587f4 3663 #define DMA_CNDTR_NDT ((uint32_t)0x0000FFFF) /*!< Number of data to Transfer */
mbed_official 403:91a4bea587f4 3664
mbed_official 403:91a4bea587f4 3665 /****************** Bit definition for DMA_CPAR register ********************/
mbed_official 403:91a4bea587f4 3666 #define DMA_CPAR_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
mbed_official 403:91a4bea587f4 3667
mbed_official 403:91a4bea587f4 3668 /****************** Bit definition for DMA_CMAR register ********************/
mbed_official 403:91a4bea587f4 3669 #define DMA_CMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
mbed_official 403:91a4bea587f4 3670
mbed_official 403:91a4bea587f4 3671 /******************************************************************************/
mbed_official 403:91a4bea587f4 3672 /* */
mbed_official 403:91a4bea587f4 3673 /* External Interrupt/Event Controller (EXTI) */
mbed_official 403:91a4bea587f4 3674 /* */
mbed_official 403:91a4bea587f4 3675 /******************************************************************************/
mbed_official 403:91a4bea587f4 3676 /******************* Bit definition for EXTI_IMR1/EXTI_IMR2 register ********/
mbed_official 403:91a4bea587f4 3677 #define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
mbed_official 403:91a4bea587f4 3678 #define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
mbed_official 403:91a4bea587f4 3679 #define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
mbed_official 403:91a4bea587f4 3680 #define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
mbed_official 403:91a4bea587f4 3681 #define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
mbed_official 403:91a4bea587f4 3682 #define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
mbed_official 403:91a4bea587f4 3683 #define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
mbed_official 403:91a4bea587f4 3684 #define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
mbed_official 403:91a4bea587f4 3685 #define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
mbed_official 403:91a4bea587f4 3686 #define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
mbed_official 403:91a4bea587f4 3687 #define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
mbed_official 403:91a4bea587f4 3688 #define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
mbed_official 403:91a4bea587f4 3689 #define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
mbed_official 403:91a4bea587f4 3690 #define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
mbed_official 403:91a4bea587f4 3691 #define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
mbed_official 403:91a4bea587f4 3692 #define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
mbed_official 403:91a4bea587f4 3693 #define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
mbed_official 403:91a4bea587f4 3694 #define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
mbed_official 403:91a4bea587f4 3695 #define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
mbed_official 403:91a4bea587f4 3696 #define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
mbed_official 403:91a4bea587f4 3697 #define EXTI_IMR_MR20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */
mbed_official 403:91a4bea587f4 3698 #define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */
mbed_official 403:91a4bea587f4 3699 #define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */
mbed_official 403:91a4bea587f4 3700 #define EXTI_IMR_MR23 ((uint32_t)0x00800000) /*!< Interrupt Mask on line 23 */
mbed_official 403:91a4bea587f4 3701 #define EXTI_IMR_MR24 ((uint32_t)0x01000000) /*!< Interrupt Mask on line 24 */
mbed_official 403:91a4bea587f4 3702 #define EXTI_IMR_MR25 ((uint32_t)0x02000000) /*!< Interrupt Mask on line 25 */
mbed_official 403:91a4bea587f4 3703 #define EXTI_IMR_MR26 ((uint32_t)0x04000000) /*!< Interrupt Mask on line 26 */
mbed_official 403:91a4bea587f4 3704 #define EXTI_IMR_MR27 ((uint32_t)0x08000000) /*!< Interrupt Mask on line 27 */
mbed_official 403:91a4bea587f4 3705 #define EXTI_IMR_MR28 ((uint32_t)0x10000000) /*!< Interrupt Mask on line 28 */
mbed_official 403:91a4bea587f4 3706
mbed_official 403:91a4bea587f4 3707 /******************* Bit definition for EXTI_EMR1/EXTI_EMR2 register ********/
mbed_official 403:91a4bea587f4 3708 #define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
mbed_official 403:91a4bea587f4 3709 #define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
mbed_official 403:91a4bea587f4 3710 #define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
mbed_official 403:91a4bea587f4 3711 #define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
mbed_official 403:91a4bea587f4 3712 #define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
mbed_official 403:91a4bea587f4 3713 #define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
mbed_official 403:91a4bea587f4 3714 #define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
mbed_official 403:91a4bea587f4 3715 #define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
mbed_official 403:91a4bea587f4 3716 #define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
mbed_official 403:91a4bea587f4 3717 #define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
mbed_official 403:91a4bea587f4 3718 #define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
mbed_official 403:91a4bea587f4 3719 #define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
mbed_official 403:91a4bea587f4 3720 #define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
mbed_official 403:91a4bea587f4 3721 #define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
mbed_official 403:91a4bea587f4 3722 #define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
mbed_official 403:91a4bea587f4 3723 #define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
mbed_official 403:91a4bea587f4 3724 #define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
mbed_official 403:91a4bea587f4 3725 #define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
mbed_official 403:91a4bea587f4 3726 #define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
mbed_official 403:91a4bea587f4 3727 #define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
mbed_official 403:91a4bea587f4 3728 #define EXTI_EMR_MR20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */
mbed_official 403:91a4bea587f4 3729 #define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */
mbed_official 403:91a4bea587f4 3730 #define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */
mbed_official 403:91a4bea587f4 3731 #define EXTI_EMR_MR23 ((uint32_t)0x00800000) /*!< Event Mask on line 23 */
mbed_official 403:91a4bea587f4 3732 #define EXTI_EMR_MR24 ((uint32_t)0x01000000) /*!< Event Mask on line 24 */
mbed_official 403:91a4bea587f4 3733 #define EXTI_EMR_MR25 ((uint32_t)0x02000000) /*!< Event Mask on line 25 */
mbed_official 403:91a4bea587f4 3734 #define EXTI_EMR_MR26 ((uint32_t)0x04000000) /*!< Event Mask on line 26 */
mbed_official 403:91a4bea587f4 3735 #define EXTI_EMR_MR27 ((uint32_t)0x08000000) /*!< Event Mask on line 27 */
mbed_official 403:91a4bea587f4 3736 #define EXTI_EMR_MR28 ((uint32_t)0x10000000) /*!< Event Mask on line 28 */
mbed_official 403:91a4bea587f4 3737
mbed_official 403:91a4bea587f4 3738 /****************** Bit definition for EXTI_RTSR1/EXTI_RTSR2 register *******/
mbed_official 403:91a4bea587f4 3739 #define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
mbed_official 403:91a4bea587f4 3740 #define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
mbed_official 403:91a4bea587f4 3741 #define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
mbed_official 403:91a4bea587f4 3742 #define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
mbed_official 403:91a4bea587f4 3743 #define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
mbed_official 403:91a4bea587f4 3744 #define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
mbed_official 403:91a4bea587f4 3745 #define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
mbed_official 403:91a4bea587f4 3746 #define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
mbed_official 403:91a4bea587f4 3747 #define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
mbed_official 403:91a4bea587f4 3748 #define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
mbed_official 403:91a4bea587f4 3749 #define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
mbed_official 403:91a4bea587f4 3750 #define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
mbed_official 403:91a4bea587f4 3751 #define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
mbed_official 403:91a4bea587f4 3752 #define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
mbed_official 403:91a4bea587f4 3753 #define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
mbed_official 403:91a4bea587f4 3754 #define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
mbed_official 403:91a4bea587f4 3755 #define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
mbed_official 403:91a4bea587f4 3756 #define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
mbed_official 403:91a4bea587f4 3757 #define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
mbed_official 403:91a4bea587f4 3758 #define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
mbed_official 403:91a4bea587f4 3759 #define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
mbed_official 403:91a4bea587f4 3760 #define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
mbed_official 403:91a4bea587f4 3761 #define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
mbed_official 403:91a4bea587f4 3762 #define EXTI_RTSR_TR23 ((uint32_t)0x00800000) /*!< Rising trigger event configuration bit of line 23 */
mbed_official 403:91a4bea587f4 3763 #define EXTI_RTSR_TR24 ((uint32_t)0x01000000) /*!< Rising trigger event configuration bit of line 24 */
mbed_official 403:91a4bea587f4 3764 #define EXTI_RTSR_TR25 ((uint32_t)0x02000000) /*!< Rising trigger event configuration bit of line 25 */
mbed_official 403:91a4bea587f4 3765 #define EXTI_RTSR_TR26 ((uint32_t)0x04000000) /*!< Rising trigger event configuration bit of line 26 */
mbed_official 403:91a4bea587f4 3766 #define EXTI_RTSR_TR27 ((uint32_t)0x08000000) /*!< Rising trigger event configuration bit of line 27 */
mbed_official 403:91a4bea587f4 3767 #define EXTI_RTSR_TR28 ((uint32_t)0x10000000) /*!< Rising trigger event configuration bit of line 28 */
mbed_official 403:91a4bea587f4 3768
mbed_official 403:91a4bea587f4 3769 /****************** Bit definition for EXTI_FTSR1/EXTI_FTSR2 register *******/
mbed_official 403:91a4bea587f4 3770 #define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
mbed_official 403:91a4bea587f4 3771 #define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
mbed_official 403:91a4bea587f4 3772 #define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
mbed_official 403:91a4bea587f4 3773 #define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
mbed_official 403:91a4bea587f4 3774 #define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
mbed_official 403:91a4bea587f4 3775 #define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
mbed_official 403:91a4bea587f4 3776 #define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
mbed_official 403:91a4bea587f4 3777 #define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
mbed_official 403:91a4bea587f4 3778 #define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
mbed_official 403:91a4bea587f4 3779 #define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
mbed_official 403:91a4bea587f4 3780 #define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
mbed_official 403:91a4bea587f4 3781 #define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
mbed_official 403:91a4bea587f4 3782 #define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
mbed_official 403:91a4bea587f4 3783 #define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
mbed_official 403:91a4bea587f4 3784 #define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
mbed_official 403:91a4bea587f4 3785 #define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
mbed_official 403:91a4bea587f4 3786 #define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
mbed_official 403:91a4bea587f4 3787 #define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
mbed_official 403:91a4bea587f4 3788 #define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
mbed_official 403:91a4bea587f4 3789 #define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
mbed_official 403:91a4bea587f4 3790 #define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
mbed_official 403:91a4bea587f4 3791 #define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
mbed_official 403:91a4bea587f4 3792 #define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
mbed_official 403:91a4bea587f4 3793 #define EXTI_FTSR_TR23 ((uint32_t)0x00800000) /*!< Falling trigger event configuration bit of line 23 */
mbed_official 403:91a4bea587f4 3794 #define EXTI_FTSR_TR24 ((uint32_t)0x01000000) /*!< Falling trigger event configuration bit of line 24 */
mbed_official 403:91a4bea587f4 3795 #define EXTI_FTSR_TR25 ((uint32_t)0x02000000) /*!< Falling trigger event configuration bit of line 25 */
mbed_official 403:91a4bea587f4 3796 #define EXTI_FTSR_TR26 ((uint32_t)0x04000000) /*!< Falling trigger event configuration bit of line 26 */
mbed_official 403:91a4bea587f4 3797 #define EXTI_FTSR_TR27 ((uint32_t)0x08000000) /*!< Falling trigger event configuration bit of line 27 */
mbed_official 403:91a4bea587f4 3798 #define EXTI_FTSR_TR28 ((uint32_t)0x10000000) /*!< Falling trigger event configuration bit of line 28 */
mbed_official 403:91a4bea587f4 3799
mbed_official 403:91a4bea587f4 3800 /****************** Bit definition for EXTI_SWIER1/EXTI_SWIER2 register *****/
mbed_official 403:91a4bea587f4 3801 #define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
mbed_official 403:91a4bea587f4 3802 #define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
mbed_official 403:91a4bea587f4 3803 #define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
mbed_official 403:91a4bea587f4 3804 #define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
mbed_official 403:91a4bea587f4 3805 #define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
mbed_official 403:91a4bea587f4 3806 #define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
mbed_official 403:91a4bea587f4 3807 #define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
mbed_official 403:91a4bea587f4 3808 #define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
mbed_official 403:91a4bea587f4 3809 #define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
mbed_official 403:91a4bea587f4 3810 #define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
mbed_official 403:91a4bea587f4 3811 #define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
mbed_official 403:91a4bea587f4 3812 #define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
mbed_official 403:91a4bea587f4 3813 #define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
mbed_official 403:91a4bea587f4 3814 #define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
mbed_official 403:91a4bea587f4 3815 #define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
mbed_official 403:91a4bea587f4 3816 #define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
mbed_official 403:91a4bea587f4 3817 #define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
mbed_official 403:91a4bea587f4 3818 #define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
mbed_official 403:91a4bea587f4 3819 #define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
mbed_official 403:91a4bea587f4 3820 #define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
mbed_official 403:91a4bea587f4 3821 #define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
mbed_official 403:91a4bea587f4 3822 #define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
mbed_official 403:91a4bea587f4 3823 #define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
mbed_official 403:91a4bea587f4 3824 #define EXTI_SWIER_SWIER23 ((uint32_t)0x00800000) /*!< Software Interrupt on line 23 */
mbed_official 403:91a4bea587f4 3825 #define EXTI_SWIER_SWIER24 ((uint32_t)0x01000000) /*!< Software Interrupt on line 24 */
mbed_official 403:91a4bea587f4 3826 #define EXTI_SWIER_SWIER25 ((uint32_t)0x02000000) /*!< Software Interrupt on line 25 */
mbed_official 403:91a4bea587f4 3827 #define EXTI_SWIER_SWIER26 ((uint32_t)0x04000000) /*!< Software Interrupt on line 26 */
mbed_official 403:91a4bea587f4 3828 #define EXTI_SWIER_SWIER27 ((uint32_t)0x08000000) /*!< Software Interrupt on line 27 */
mbed_official 403:91a4bea587f4 3829 #define EXTI_SWIER_SWIER28 ((uint32_t)0x10000000) /*!< Software Interrupt on line 28 */
mbed_official 403:91a4bea587f4 3830
mbed_official 403:91a4bea587f4 3831 /******************* Bit definition for EXTI_PR1/EXTI_PR2 register **********/
mbed_official 403:91a4bea587f4 3832 #define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
mbed_official 403:91a4bea587f4 3833 #define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */
mbed_official 403:91a4bea587f4 3834 #define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */
mbed_official 403:91a4bea587f4 3835 #define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */
mbed_official 403:91a4bea587f4 3836 #define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */
mbed_official 403:91a4bea587f4 3837 #define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */
mbed_official 403:91a4bea587f4 3838 #define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */
mbed_official 403:91a4bea587f4 3839 #define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */
mbed_official 403:91a4bea587f4 3840 #define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */
mbed_official 403:91a4bea587f4 3841 #define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */
mbed_official 403:91a4bea587f4 3842 #define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */
mbed_official 403:91a4bea587f4 3843 #define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */
mbed_official 403:91a4bea587f4 3844 #define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */
mbed_official 403:91a4bea587f4 3845 #define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */
mbed_official 403:91a4bea587f4 3846 #define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */
mbed_official 403:91a4bea587f4 3847 #define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */
mbed_official 403:91a4bea587f4 3848 #define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */
mbed_official 403:91a4bea587f4 3849 #define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */
mbed_official 403:91a4bea587f4 3850 #define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */
mbed_official 403:91a4bea587f4 3851 #define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */
mbed_official 403:91a4bea587f4 3852 #define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit for line 20 */
mbed_official 403:91a4bea587f4 3853 #define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit for line 21 */
mbed_official 403:91a4bea587f4 3854 #define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit for line 22 */
mbed_official 403:91a4bea587f4 3855 #define EXTI_PR_PR23 ((uint32_t)0x00800000) /*!< Pending bit for line 23 */
mbed_official 403:91a4bea587f4 3856 #define EXTI_PR_PR24 ((uint32_t)0x01000000) /*!< Pending bit for line 24 */
mbed_official 403:91a4bea587f4 3857 #define EXTI_PR_PR25 ((uint32_t)0x02000000) /*!< Pending bit for line 25 */
mbed_official 403:91a4bea587f4 3858 #define EXTI_PR_PR26 ((uint32_t)0x04000000) /*!< Pending bit for line 26 */
mbed_official 403:91a4bea587f4 3859 #define EXTI_PR_PR27 ((uint32_t)0x08000000) /*!< Pending bit for line 27 */
mbed_official 403:91a4bea587f4 3860 #define EXTI_PR_PR28 ((uint32_t)0x10000000) /*!< Pending bit for line 28 */
mbed_official 403:91a4bea587f4 3861
mbed_official 403:91a4bea587f4 3862 /******************************************************************************/
mbed_official 403:91a4bea587f4 3863 /* */
mbed_official 403:91a4bea587f4 3864 /* FLASH */
mbed_official 403:91a4bea587f4 3865 /* */
mbed_official 403:91a4bea587f4 3866 /******************************************************************************/
mbed_official 403:91a4bea587f4 3867 /******************* Bit definition for FLASH_ACR register ******************/
mbed_official 403:91a4bea587f4 3868 #define FLASH_ACR_LATENCY ((uint32_t)0x00000007) /*!< LATENCY[2:0] bits (Latency) */
mbed_official 403:91a4bea587f4 3869 #define FLASH_ACR_LATENCY_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 403:91a4bea587f4 3870 #define FLASH_ACR_LATENCY_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 403:91a4bea587f4 3871 #define FLASH_ACR_LATENCY_2 ((uint32_t)0x00000004) /*!< Bit 2 */
mbed_official 403:91a4bea587f4 3872
mbed_official 403:91a4bea587f4 3873 #define FLASH_ACR_HLFCYA ((uint32_t)0x00000008) /*!< Flash Half Cycle Access Enable */
mbed_official 403:91a4bea587f4 3874 #define FLASH_ACR_PRFTBE ((uint32_t)0x00000010) /*!< Prefetch Buffer Enable */
mbed_official 403:91a4bea587f4 3875 #define FLASH_ACR_PRFTBS ((uint32_t)0x00000020) /*!< Prefetch Buffer Status */
mbed_official 403:91a4bea587f4 3876
mbed_official 403:91a4bea587f4 3877 /****************** Bit definition for FLASH_KEYR register ******************/
mbed_official 403:91a4bea587f4 3878 #define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /*!< FPEC Key */
mbed_official 403:91a4bea587f4 3879
mbed_official 403:91a4bea587f4 3880 #define RDP_KEY ((uint32_t)0x000000A5) /*!< RDP Key */
mbed_official 403:91a4bea587f4 3881 #define FLASH_KEY1 ((uint32_t)0x45670123) /*!< FPEC Key1 */
mbed_official 403:91a4bea587f4 3882 #define FLASH_KEY2 ((uint32_t)0xCDEF89AB) /*!< FPEC Key2 */
mbed_official 403:91a4bea587f4 3883
mbed_official 403:91a4bea587f4 3884 /***************** Bit definition for FLASH_OPTKEYR register ****************/
mbed_official 403:91a4bea587f4 3885 #define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!< Option Byte Key */
mbed_official 403:91a4bea587f4 3886
mbed_official 403:91a4bea587f4 3887 #define FLASH_OPTKEY1 FLASH_KEY1 /*!< Option Byte Key1 */
mbed_official 403:91a4bea587f4 3888 #define FLASH_OPTKEY2 FLASH_KEY2 /*!< Option Byte Key2 */
mbed_official 403:91a4bea587f4 3889
mbed_official 403:91a4bea587f4 3890 /****************** Bit definition for FLASH_SR register *******************/
mbed_official 403:91a4bea587f4 3891 #define FLASH_SR_BSY ((uint32_t)0x00000001) /*!< Busy */
mbed_official 403:91a4bea587f4 3892 #define FLASH_SR_PGERR ((uint32_t)0x00000004) /*!< Programming Error */
mbed_official 403:91a4bea587f4 3893 #define FLASH_SR_WRPERR ((uint32_t)0x00000010) /*!< Write Protection Error */
mbed_official 403:91a4bea587f4 3894 #define FLASH_SR_EOP ((uint32_t)0x00000020) /*!< End of operation */
mbed_official 403:91a4bea587f4 3895
mbed_official 403:91a4bea587f4 3896 /******************* Bit definition for FLASH_CR register *******************/
mbed_official 403:91a4bea587f4 3897 #define FLASH_CR_PG ((uint32_t)0x00000001) /*!< Programming */
mbed_official 403:91a4bea587f4 3898 #define FLASH_CR_PER ((uint32_t)0x00000002) /*!< Page Erase */
mbed_official 403:91a4bea587f4 3899 #define FLASH_CR_MER ((uint32_t)0x00000004) /*!< Mass Erase */
mbed_official 403:91a4bea587f4 3900 #define FLASH_CR_OPTPG ((uint32_t)0x00000010) /*!< Option Byte Programming */
mbed_official 403:91a4bea587f4 3901 #define FLASH_CR_OPTER ((uint32_t)0x00000020) /*!< Option Byte Erase */
mbed_official 403:91a4bea587f4 3902 #define FLASH_CR_STRT ((uint32_t)0x00000040) /*!< Start */
mbed_official 403:91a4bea587f4 3903 #define FLASH_CR_LOCK ((uint32_t)0x00000080) /*!< Lock */
mbed_official 403:91a4bea587f4 3904 #define FLASH_CR_OPTWRE ((uint32_t)0x00000200) /*!< Option Bytes Write Enable */
mbed_official 403:91a4bea587f4 3905 #define FLASH_CR_ERRIE ((uint32_t)0x00000400) /*!< Error Interrupt Enable */
mbed_official 403:91a4bea587f4 3906 #define FLASH_CR_EOPIE ((uint32_t)0x00001000) /*!< End of operation interrupt enable */
mbed_official 403:91a4bea587f4 3907 #define FLASH_CR_OBL_LAUNCH ((uint32_t)0x00002000) /*!< OptionBytes Loader Launch */
mbed_official 403:91a4bea587f4 3908
mbed_official 403:91a4bea587f4 3909 /******************* Bit definition for FLASH_AR register *******************/
mbed_official 403:91a4bea587f4 3910 #define FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) /*!< Flash Address */
mbed_official 403:91a4bea587f4 3911
mbed_official 403:91a4bea587f4 3912 /****************** Bit definition for FLASH_OBR register *******************/
mbed_official 403:91a4bea587f4 3913 #define FLASH_OBR_OPTERR ((uint32_t)0x00000001) /*!< Option Byte Error */
mbed_official 403:91a4bea587f4 3914 #define FLASH_OBR_RDPRT ((uint32_t)0x00000006) /*!< Read protection */
mbed_official 403:91a4bea587f4 3915 #define FLASH_OBR_RDPRT_1 ((uint32_t)0x00000002) /*!< Read protection Level 1 */
mbed_official 403:91a4bea587f4 3916 #define FLASH_OBR_RDPRT_2 ((uint32_t)0x00000006) /*!< Read protection Level 2 */
mbed_official 403:91a4bea587f4 3917
mbed_official 403:91a4bea587f4 3918 #define FLASH_OBR_USER ((uint32_t)0x00007700) /*!< User Option Bytes */
mbed_official 403:91a4bea587f4 3919 #define FLASH_OBR_IWDG_SW ((uint32_t)0x00000100) /*!< IWDG SW */
mbed_official 403:91a4bea587f4 3920 #define FLASH_OBR_nRST_STOP ((uint32_t)0x00000200) /*!< nRST_STOP */
mbed_official 403:91a4bea587f4 3921 #define FLASH_OBR_nRST_STDBY ((uint32_t)0x00000400) /*!< nRST_STDBY */
mbed_official 403:91a4bea587f4 3922 #define FLASH_OBR_nBOOT1 ((uint32_t)0x00001000) /*!< nBOOT1 */
mbed_official 403:91a4bea587f4 3923 #define FLASH_OBR_VDDA_MONITOR ((uint32_t)0x00002000) /*!< VDDA_MONITOR */
mbed_official 403:91a4bea587f4 3924 #define FLASH_OBR_SRAM_PE ((uint32_t)0x00004000) /*!< SRAM_PE */
mbed_official 403:91a4bea587f4 3925
mbed_official 403:91a4bea587f4 3926 /****************** Bit definition for FLASH_WRPR register ******************/
mbed_official 403:91a4bea587f4 3927 #define FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) /*!< Write Protect */
mbed_official 403:91a4bea587f4 3928
mbed_official 403:91a4bea587f4 3929 /*----------------------------------------------------------------------------*/
mbed_official 403:91a4bea587f4 3930
mbed_official 403:91a4bea587f4 3931 /****************** Bit definition for OB_RDP register **********************/
mbed_official 403:91a4bea587f4 3932 #define OB_RDP_RDP ((uint32_t)0x000000FF) /*!< Read protection option byte */
mbed_official 403:91a4bea587f4 3933 #define OB_RDP_nRDP ((uint32_t)0x0000FF00) /*!< Read protection complemented option byte */
mbed_official 403:91a4bea587f4 3934
mbed_official 403:91a4bea587f4 3935 /****************** Bit definition for OB_USER register *********************/
mbed_official 403:91a4bea587f4 3936 #define OB_USER_USER ((uint32_t)0x00FF0000) /*!< User option byte */
mbed_official 403:91a4bea587f4 3937 #define OB_USER_nUSER ((uint32_t)0xFF000000) /*!< User complemented option byte */
mbed_official 403:91a4bea587f4 3938
mbed_official 403:91a4bea587f4 3939 /****************** Bit definition for FLASH_WRP0 register ******************/
mbed_official 403:91a4bea587f4 3940 #define OB_WRP0_WRP0 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */
mbed_official 403:91a4bea587f4 3941 #define OB_WRP0_nWRP0 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */
mbed_official 403:91a4bea587f4 3942
mbed_official 403:91a4bea587f4 3943 /****************** Bit definition for FLASH_WRP1 register ******************/
mbed_official 403:91a4bea587f4 3944 #define OB_WRP1_WRP1 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */
mbed_official 403:91a4bea587f4 3945 #define OB_WRP1_nWRP1 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */
mbed_official 403:91a4bea587f4 3946
mbed_official 403:91a4bea587f4 3947 /****************** Bit definition for FLASH_WRP2 register ******************/
mbed_official 403:91a4bea587f4 3948 #define OB_WRP2_WRP2 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */
mbed_official 403:91a4bea587f4 3949 #define OB_WRP2_nWRP2 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */
mbed_official 403:91a4bea587f4 3950
mbed_official 403:91a4bea587f4 3951 /****************** Bit definition for FLASH_WRP3 register ******************/
mbed_official 403:91a4bea587f4 3952 #define OB_WRP3_WRP3 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */
mbed_official 403:91a4bea587f4 3953 #define OB_WRP3_nWRP3 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */
mbed_official 403:91a4bea587f4 3954 /******************************************************************************/
mbed_official 403:91a4bea587f4 3955 /* */
mbed_official 403:91a4bea587f4 3956 /* General Purpose I/O (GPIO) */
mbed_official 403:91a4bea587f4 3957 /* */
mbed_official 403:91a4bea587f4 3958 /******************************************************************************/
mbed_official 403:91a4bea587f4 3959 /******************* Bit definition for GPIO_MODER register *****************/
mbed_official 403:91a4bea587f4 3960 #define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
mbed_official 403:91a4bea587f4 3961 #define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
mbed_official 403:91a4bea587f4 3962 #define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
mbed_official 403:91a4bea587f4 3963 #define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
mbed_official 403:91a4bea587f4 3964 #define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
mbed_official 403:91a4bea587f4 3965 #define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
mbed_official 403:91a4bea587f4 3966 #define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
mbed_official 403:91a4bea587f4 3967 #define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
mbed_official 403:91a4bea587f4 3968 #define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
mbed_official 403:91a4bea587f4 3969 #define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
mbed_official 403:91a4bea587f4 3970 #define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
mbed_official 403:91a4bea587f4 3971 #define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
mbed_official 403:91a4bea587f4 3972 #define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
mbed_official 403:91a4bea587f4 3973 #define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
mbed_official 403:91a4bea587f4 3974 #define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
mbed_official 403:91a4bea587f4 3975 #define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
mbed_official 403:91a4bea587f4 3976 #define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
mbed_official 403:91a4bea587f4 3977 #define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
mbed_official 403:91a4bea587f4 3978 #define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
mbed_official 403:91a4bea587f4 3979 #define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
mbed_official 403:91a4bea587f4 3980 #define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
mbed_official 403:91a4bea587f4 3981 #define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
mbed_official 403:91a4bea587f4 3982 #define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
mbed_official 403:91a4bea587f4 3983 #define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
mbed_official 403:91a4bea587f4 3984 #define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
mbed_official 403:91a4bea587f4 3985 #define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
mbed_official 403:91a4bea587f4 3986 #define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
mbed_official 403:91a4bea587f4 3987 #define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
mbed_official 403:91a4bea587f4 3988 #define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
mbed_official 403:91a4bea587f4 3989 #define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
mbed_official 403:91a4bea587f4 3990 #define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
mbed_official 403:91a4bea587f4 3991 #define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
mbed_official 403:91a4bea587f4 3992 #define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
mbed_official 403:91a4bea587f4 3993 #define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
mbed_official 403:91a4bea587f4 3994 #define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
mbed_official 403:91a4bea587f4 3995 #define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
mbed_official 403:91a4bea587f4 3996 #define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
mbed_official 403:91a4bea587f4 3997 #define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
mbed_official 403:91a4bea587f4 3998 #define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
mbed_official 403:91a4bea587f4 3999 #define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
mbed_official 403:91a4bea587f4 4000 #define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
mbed_official 403:91a4bea587f4 4001 #define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
mbed_official 403:91a4bea587f4 4002 #define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
mbed_official 403:91a4bea587f4 4003 #define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
mbed_official 403:91a4bea587f4 4004 #define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
mbed_official 403:91a4bea587f4 4005 #define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
mbed_official 403:91a4bea587f4 4006 #define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
mbed_official 403:91a4bea587f4 4007 #define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
mbed_official 403:91a4bea587f4 4008
mbed_official 403:91a4bea587f4 4009 /****************** Bit definition for GPIO_OTYPER register *****************/
mbed_official 403:91a4bea587f4 4010 #define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
mbed_official 403:91a4bea587f4 4011 #define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
mbed_official 403:91a4bea587f4 4012 #define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
mbed_official 403:91a4bea587f4 4013 #define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
mbed_official 403:91a4bea587f4 4014 #define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
mbed_official 403:91a4bea587f4 4015 #define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
mbed_official 403:91a4bea587f4 4016 #define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
mbed_official 403:91a4bea587f4 4017 #define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
mbed_official 403:91a4bea587f4 4018 #define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
mbed_official 403:91a4bea587f4 4019 #define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
mbed_official 403:91a4bea587f4 4020 #define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
mbed_official 403:91a4bea587f4 4021 #define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
mbed_official 403:91a4bea587f4 4022 #define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
mbed_official 403:91a4bea587f4 4023 #define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
mbed_official 403:91a4bea587f4 4024 #define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
mbed_official 403:91a4bea587f4 4025 #define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
mbed_official 403:91a4bea587f4 4026
mbed_official 403:91a4bea587f4 4027 /**************** Bit definition for GPIO_OSPEEDR register ******************/
mbed_official 403:91a4bea587f4 4028 #define GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003)
mbed_official 403:91a4bea587f4 4029 #define GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001)
mbed_official 403:91a4bea587f4 4030 #define GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002)
mbed_official 403:91a4bea587f4 4031 #define GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C)
mbed_official 403:91a4bea587f4 4032 #define GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004)
mbed_official 403:91a4bea587f4 4033 #define GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008)
mbed_official 403:91a4bea587f4 4034 #define GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030)
mbed_official 403:91a4bea587f4 4035 #define GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010)
mbed_official 403:91a4bea587f4 4036 #define GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020)
mbed_official 403:91a4bea587f4 4037 #define GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0)
mbed_official 403:91a4bea587f4 4038 #define GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040)
mbed_official 403:91a4bea587f4 4039 #define GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080)
mbed_official 403:91a4bea587f4 4040 #define GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300)
mbed_official 403:91a4bea587f4 4041 #define GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100)
mbed_official 403:91a4bea587f4 4042 #define GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200)
mbed_official 403:91a4bea587f4 4043 #define GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00)
mbed_official 403:91a4bea587f4 4044 #define GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400)
mbed_official 403:91a4bea587f4 4045 #define GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800)
mbed_official 403:91a4bea587f4 4046 #define GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000)
mbed_official 403:91a4bea587f4 4047 #define GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000)
mbed_official 403:91a4bea587f4 4048 #define GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000)
mbed_official 403:91a4bea587f4 4049 #define GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000)
mbed_official 403:91a4bea587f4 4050 #define GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000)
mbed_official 403:91a4bea587f4 4051 #define GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000)
mbed_official 403:91a4bea587f4 4052 #define GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000)
mbed_official 403:91a4bea587f4 4053 #define GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000)
mbed_official 403:91a4bea587f4 4054 #define GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000)
mbed_official 403:91a4bea587f4 4055 #define GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000)
mbed_official 403:91a4bea587f4 4056 #define GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000)
mbed_official 403:91a4bea587f4 4057 #define GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000)
mbed_official 403:91a4bea587f4 4058 #define GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000)
mbed_official 403:91a4bea587f4 4059 #define GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000)
mbed_official 403:91a4bea587f4 4060 #define GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000)
mbed_official 403:91a4bea587f4 4061 #define GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000)
mbed_official 403:91a4bea587f4 4062 #define GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000)
mbed_official 403:91a4bea587f4 4063 #define GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000)
mbed_official 403:91a4bea587f4 4064 #define GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000)
mbed_official 403:91a4bea587f4 4065 #define GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000)
mbed_official 403:91a4bea587f4 4066 #define GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000)
mbed_official 403:91a4bea587f4 4067 #define GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000)
mbed_official 403:91a4bea587f4 4068 #define GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000)
mbed_official 403:91a4bea587f4 4069 #define GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000)
mbed_official 403:91a4bea587f4 4070 #define GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000)
mbed_official 403:91a4bea587f4 4071 #define GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000)
mbed_official 403:91a4bea587f4 4072 #define GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000)
mbed_official 403:91a4bea587f4 4073 #define GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000)
mbed_official 403:91a4bea587f4 4074 #define GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000)
mbed_official 403:91a4bea587f4 4075 #define GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000)
mbed_official 403:91a4bea587f4 4076
mbed_official 403:91a4bea587f4 4077 /******************* Bit definition for GPIO_PUPDR register ******************/
mbed_official 403:91a4bea587f4 4078 #define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
mbed_official 403:91a4bea587f4 4079 #define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
mbed_official 403:91a4bea587f4 4080 #define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
mbed_official 403:91a4bea587f4 4081 #define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
mbed_official 403:91a4bea587f4 4082 #define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
mbed_official 403:91a4bea587f4 4083 #define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
mbed_official 403:91a4bea587f4 4084 #define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
mbed_official 403:91a4bea587f4 4085 #define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
mbed_official 403:91a4bea587f4 4086 #define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
mbed_official 403:91a4bea587f4 4087 #define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
mbed_official 403:91a4bea587f4 4088 #define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
mbed_official 403:91a4bea587f4 4089 #define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
mbed_official 403:91a4bea587f4 4090 #define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
mbed_official 403:91a4bea587f4 4091 #define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
mbed_official 403:91a4bea587f4 4092 #define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
mbed_official 403:91a4bea587f4 4093 #define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
mbed_official 403:91a4bea587f4 4094 #define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
mbed_official 403:91a4bea587f4 4095 #define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
mbed_official 403:91a4bea587f4 4096 #define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
mbed_official 403:91a4bea587f4 4097 #define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
mbed_official 403:91a4bea587f4 4098 #define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
mbed_official 403:91a4bea587f4 4099 #define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
mbed_official 403:91a4bea587f4 4100 #define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
mbed_official 403:91a4bea587f4 4101 #define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
mbed_official 403:91a4bea587f4 4102 #define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
mbed_official 403:91a4bea587f4 4103 #define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
mbed_official 403:91a4bea587f4 4104 #define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
mbed_official 403:91a4bea587f4 4105 #define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
mbed_official 403:91a4bea587f4 4106 #define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
mbed_official 403:91a4bea587f4 4107 #define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
mbed_official 403:91a4bea587f4 4108 #define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
mbed_official 403:91a4bea587f4 4109 #define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
mbed_official 403:91a4bea587f4 4110 #define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
mbed_official 403:91a4bea587f4 4111 #define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
mbed_official 403:91a4bea587f4 4112 #define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
mbed_official 403:91a4bea587f4 4113 #define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
mbed_official 403:91a4bea587f4 4114 #define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
mbed_official 403:91a4bea587f4 4115 #define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
mbed_official 403:91a4bea587f4 4116 #define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
mbed_official 403:91a4bea587f4 4117 #define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
mbed_official 403:91a4bea587f4 4118 #define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
mbed_official 403:91a4bea587f4 4119 #define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
mbed_official 403:91a4bea587f4 4120 #define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
mbed_official 403:91a4bea587f4 4121 #define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
mbed_official 403:91a4bea587f4 4122 #define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
mbed_official 403:91a4bea587f4 4123 #define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
mbed_official 403:91a4bea587f4 4124 #define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
mbed_official 403:91a4bea587f4 4125 #define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
mbed_official 403:91a4bea587f4 4126
mbed_official 403:91a4bea587f4 4127 /******************* Bit definition for GPIO_IDR register *******************/
mbed_official 403:91a4bea587f4 4128 #define GPIO_IDR_0 ((uint32_t)0x00000001)
mbed_official 403:91a4bea587f4 4129 #define GPIO_IDR_1 ((uint32_t)0x00000002)
mbed_official 403:91a4bea587f4 4130 #define GPIO_IDR_2 ((uint32_t)0x00000004)
mbed_official 403:91a4bea587f4 4131 #define GPIO_IDR_3 ((uint32_t)0x00000008)
mbed_official 403:91a4bea587f4 4132 #define GPIO_IDR_4 ((uint32_t)0x00000010)
mbed_official 403:91a4bea587f4 4133 #define GPIO_IDR_5 ((uint32_t)0x00000020)
mbed_official 403:91a4bea587f4 4134 #define GPIO_IDR_6 ((uint32_t)0x00000040)
mbed_official 403:91a4bea587f4 4135 #define GPIO_IDR_7 ((uint32_t)0x00000080)
mbed_official 403:91a4bea587f4 4136 #define GPIO_IDR_8 ((uint32_t)0x00000100)
mbed_official 403:91a4bea587f4 4137 #define GPIO_IDR_9 ((uint32_t)0x00000200)
mbed_official 403:91a4bea587f4 4138 #define GPIO_IDR_10 ((uint32_t)0x00000400)
mbed_official 403:91a4bea587f4 4139 #define GPIO_IDR_11 ((uint32_t)0x00000800)
mbed_official 403:91a4bea587f4 4140 #define GPIO_IDR_12 ((uint32_t)0x00001000)
mbed_official 403:91a4bea587f4 4141 #define GPIO_IDR_13 ((uint32_t)0x00002000)
mbed_official 403:91a4bea587f4 4142 #define GPIO_IDR_14 ((uint32_t)0x00004000)
mbed_official 403:91a4bea587f4 4143 #define GPIO_IDR_15 ((uint32_t)0x00008000)
mbed_official 403:91a4bea587f4 4144
mbed_official 403:91a4bea587f4 4145 /****************** Bit definition for GPIO_ODR register ********************/
mbed_official 403:91a4bea587f4 4146 #define GPIO_ODR_0 ((uint32_t)0x00000001)
mbed_official 403:91a4bea587f4 4147 #define GPIO_ODR_1 ((uint32_t)0x00000002)
mbed_official 403:91a4bea587f4 4148 #define GPIO_ODR_2 ((uint32_t)0x00000004)
mbed_official 403:91a4bea587f4 4149 #define GPIO_ODR_3 ((uint32_t)0x00000008)
mbed_official 403:91a4bea587f4 4150 #define GPIO_ODR_4 ((uint32_t)0x00000010)
mbed_official 403:91a4bea587f4 4151 #define GPIO_ODR_5 ((uint32_t)0x00000020)
mbed_official 403:91a4bea587f4 4152 #define GPIO_ODR_6 ((uint32_t)0x00000040)
mbed_official 403:91a4bea587f4 4153 #define GPIO_ODR_7 ((uint32_t)0x00000080)
mbed_official 403:91a4bea587f4 4154 #define GPIO_ODR_8 ((uint32_t)0x00000100)
mbed_official 403:91a4bea587f4 4155 #define GPIO_ODR_9 ((uint32_t)0x00000200)
mbed_official 403:91a4bea587f4 4156 #define GPIO_ODR_10 ((uint32_t)0x00000400)
mbed_official 403:91a4bea587f4 4157 #define GPIO_ODR_11 ((uint32_t)0x00000800)
mbed_official 403:91a4bea587f4 4158 #define GPIO_ODR_12 ((uint32_t)0x00001000)
mbed_official 403:91a4bea587f4 4159 #define GPIO_ODR_13 ((uint32_t)0x00002000)
mbed_official 403:91a4bea587f4 4160 #define GPIO_ODR_14 ((uint32_t)0x00004000)
mbed_official 403:91a4bea587f4 4161 #define GPIO_ODR_15 ((uint32_t)0x00008000)
mbed_official 403:91a4bea587f4 4162
mbed_official 403:91a4bea587f4 4163 /****************** Bit definition for GPIO_BSRR register ********************/
mbed_official 403:91a4bea587f4 4164 #define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
mbed_official 403:91a4bea587f4 4165 #define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
mbed_official 403:91a4bea587f4 4166 #define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
mbed_official 403:91a4bea587f4 4167 #define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
mbed_official 403:91a4bea587f4 4168 #define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
mbed_official 403:91a4bea587f4 4169 #define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
mbed_official 403:91a4bea587f4 4170 #define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
mbed_official 403:91a4bea587f4 4171 #define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
mbed_official 403:91a4bea587f4 4172 #define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
mbed_official 403:91a4bea587f4 4173 #define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
mbed_official 403:91a4bea587f4 4174 #define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
mbed_official 403:91a4bea587f4 4175 #define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
mbed_official 403:91a4bea587f4 4176 #define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
mbed_official 403:91a4bea587f4 4177 #define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
mbed_official 403:91a4bea587f4 4178 #define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
mbed_official 403:91a4bea587f4 4179 #define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
mbed_official 403:91a4bea587f4 4180 #define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
mbed_official 403:91a4bea587f4 4181 #define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
mbed_official 403:91a4bea587f4 4182 #define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
mbed_official 403:91a4bea587f4 4183 #define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
mbed_official 403:91a4bea587f4 4184 #define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
mbed_official 403:91a4bea587f4 4185 #define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
mbed_official 403:91a4bea587f4 4186 #define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
mbed_official 403:91a4bea587f4 4187 #define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
mbed_official 403:91a4bea587f4 4188 #define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
mbed_official 403:91a4bea587f4 4189 #define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
mbed_official 403:91a4bea587f4 4190 #define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
mbed_official 403:91a4bea587f4 4191 #define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
mbed_official 403:91a4bea587f4 4192 #define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
mbed_official 403:91a4bea587f4 4193 #define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
mbed_official 403:91a4bea587f4 4194 #define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
mbed_official 403:91a4bea587f4 4195 #define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
mbed_official 403:91a4bea587f4 4196
mbed_official 403:91a4bea587f4 4197 /****************** Bit definition for GPIO_LCKR register ********************/
mbed_official 403:91a4bea587f4 4198 #define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
mbed_official 403:91a4bea587f4 4199 #define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
mbed_official 403:91a4bea587f4 4200 #define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
mbed_official 403:91a4bea587f4 4201 #define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
mbed_official 403:91a4bea587f4 4202 #define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
mbed_official 403:91a4bea587f4 4203 #define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
mbed_official 403:91a4bea587f4 4204 #define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
mbed_official 403:91a4bea587f4 4205 #define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
mbed_official 403:91a4bea587f4 4206 #define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
mbed_official 403:91a4bea587f4 4207 #define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
mbed_official 403:91a4bea587f4 4208 #define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
mbed_official 403:91a4bea587f4 4209 #define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
mbed_official 403:91a4bea587f4 4210 #define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
mbed_official 403:91a4bea587f4 4211 #define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
mbed_official 403:91a4bea587f4 4212 #define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
mbed_official 403:91a4bea587f4 4213 #define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
mbed_official 403:91a4bea587f4 4214 #define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
mbed_official 403:91a4bea587f4 4215
mbed_official 403:91a4bea587f4 4216 /****************** Bit definition for GPIO_AFRL register ********************/
mbed_official 403:91a4bea587f4 4217 #define GPIO_AFRL_AFRL0 ((uint32_t)0x0000000F)
mbed_official 403:91a4bea587f4 4218 #define GPIO_AFRL_AFRL1 ((uint32_t)0x000000F0)
mbed_official 403:91a4bea587f4 4219 #define GPIO_AFRL_AFRL2 ((uint32_t)0x00000F00)
mbed_official 403:91a4bea587f4 4220 #define GPIO_AFRL_AFRL3 ((uint32_t)0x0000F000)
mbed_official 403:91a4bea587f4 4221 #define GPIO_AFRL_AFRL4 ((uint32_t)0x000F0000)
mbed_official 403:91a4bea587f4 4222 #define GPIO_AFRL_AFRL5 ((uint32_t)0x00F00000)
mbed_official 403:91a4bea587f4 4223 #define GPIO_AFRL_AFRL6 ((uint32_t)0x0F000000)
mbed_official 403:91a4bea587f4 4224 #define GPIO_AFRL_AFRL7 ((uint32_t)0xF0000000)
mbed_official 403:91a4bea587f4 4225
mbed_official 403:91a4bea587f4 4226 /****************** Bit definition for GPIO_AFRH register ********************/
mbed_official 403:91a4bea587f4 4227 #define GPIO_AFRH_AFRH0 ((uint32_t)0x0000000F)
mbed_official 403:91a4bea587f4 4228 #define GPIO_AFRH_AFRH1 ((uint32_t)0x000000F0)
mbed_official 403:91a4bea587f4 4229 #define GPIO_AFRH_AFRH2 ((uint32_t)0x00000F00)
mbed_official 403:91a4bea587f4 4230 #define GPIO_AFRH_AFRH3 ((uint32_t)0x0000F000)
mbed_official 403:91a4bea587f4 4231 #define GPIO_AFRH_AFRH4 ((uint32_t)0x000F0000)
mbed_official 403:91a4bea587f4 4232 #define GPIO_AFRH_AFRH5 ((uint32_t)0x00F00000)
mbed_official 403:91a4bea587f4 4233 #define GPIO_AFRH_AFRH6 ((uint32_t)0x0F000000)
mbed_official 403:91a4bea587f4 4234 #define GPIO_AFRH_AFRH7 ((uint32_t)0xF0000000)
mbed_official 403:91a4bea587f4 4235
mbed_official 403:91a4bea587f4 4236 /****************** Bit definition for GPIO_BRR register *********************/
mbed_official 403:91a4bea587f4 4237 #define GPIO_BRR_BR_0 ((uint32_t)0x00000001)
mbed_official 403:91a4bea587f4 4238 #define GPIO_BRR_BR_1 ((uint32_t)0x00000002)
mbed_official 403:91a4bea587f4 4239 #define GPIO_BRR_BR_2 ((uint32_t)0x00000004)
mbed_official 403:91a4bea587f4 4240 #define GPIO_BRR_BR_3 ((uint32_t)0x00000008)
mbed_official 403:91a4bea587f4 4241 #define GPIO_BRR_BR_4 ((uint32_t)0x00000010)
mbed_official 403:91a4bea587f4 4242 #define GPIO_BRR_BR_5 ((uint32_t)0x00000020)
mbed_official 403:91a4bea587f4 4243 #define GPIO_BRR_BR_6 ((uint32_t)0x00000040)
mbed_official 403:91a4bea587f4 4244 #define GPIO_BRR_BR_7 ((uint32_t)0x00000080)
mbed_official 403:91a4bea587f4 4245 #define GPIO_BRR_BR_8 ((uint32_t)0x00000100)
mbed_official 403:91a4bea587f4 4246 #define GPIO_BRR_BR_9 ((uint32_t)0x00000200)
mbed_official 403:91a4bea587f4 4247 #define GPIO_BRR_BR_10 ((uint32_t)0x00000400)
mbed_official 403:91a4bea587f4 4248 #define GPIO_BRR_BR_11 ((uint32_t)0x00000800)
mbed_official 403:91a4bea587f4 4249 #define GPIO_BRR_BR_12 ((uint32_t)0x00001000)
mbed_official 403:91a4bea587f4 4250 #define GPIO_BRR_BR_13 ((uint32_t)0x00002000)
mbed_official 403:91a4bea587f4 4251 #define GPIO_BRR_BR_14 ((uint32_t)0x00004000)
mbed_official 403:91a4bea587f4 4252 #define GPIO_BRR_BR_15 ((uint32_t)0x00008000)
mbed_official 403:91a4bea587f4 4253
mbed_official 403:91a4bea587f4 4254 /******************************************************************************/
mbed_official 403:91a4bea587f4 4255 /* */
mbed_official 403:91a4bea587f4 4256 /* Inter-integrated Circuit Interface (I2C) */
mbed_official 403:91a4bea587f4 4257 /* */
mbed_official 403:91a4bea587f4 4258 /******************************************************************************/
mbed_official 403:91a4bea587f4 4259 /******************* Bit definition for I2C_CR1 register *******************/
mbed_official 403:91a4bea587f4 4260 #define I2C_CR1_PE ((uint32_t)0x00000001) /*!< Peripheral enable */
mbed_official 403:91a4bea587f4 4261 #define I2C_CR1_TXIE ((uint32_t)0x00000002) /*!< TX interrupt enable */
mbed_official 403:91a4bea587f4 4262 #define I2C_CR1_RXIE ((uint32_t)0x00000004) /*!< RX interrupt enable */
mbed_official 403:91a4bea587f4 4263 #define I2C_CR1_ADDRIE ((uint32_t)0x00000008) /*!< Address match interrupt enable */
mbed_official 403:91a4bea587f4 4264 #define I2C_CR1_NACKIE ((uint32_t)0x00000010) /*!< NACK received interrupt enable */
mbed_official 403:91a4bea587f4 4265 #define I2C_CR1_STOPIE ((uint32_t)0x00000020) /*!< STOP detection interrupt enable */
mbed_official 403:91a4bea587f4 4266 #define I2C_CR1_TCIE ((uint32_t)0x00000040) /*!< Transfer complete interrupt enable */
mbed_official 403:91a4bea587f4 4267 #define I2C_CR1_ERRIE ((uint32_t)0x00000080) /*!< Errors interrupt enable */
mbed_official 403:91a4bea587f4 4268 #define I2C_CR1_DFN ((uint32_t)0x00000F00) /*!< Digital noise filter */
mbed_official 403:91a4bea587f4 4269 #define I2C_CR1_ANFOFF ((uint32_t)0x00001000) /*!< Analog noise filter OFF */
mbed_official 403:91a4bea587f4 4270 #define I2C_CR1_SWRST ((uint32_t)0x00002000) /*!< Software reset */
mbed_official 403:91a4bea587f4 4271 #define I2C_CR1_TXDMAEN ((uint32_t)0x00004000) /*!< DMA transmission requests enable */
mbed_official 403:91a4bea587f4 4272 #define I2C_CR1_RXDMAEN ((uint32_t)0x00008000) /*!< DMA reception requests enable */
mbed_official 403:91a4bea587f4 4273 #define I2C_CR1_SBC ((uint32_t)0x00010000) /*!< Slave byte control */
mbed_official 403:91a4bea587f4 4274 #define I2C_CR1_NOSTRETCH ((uint32_t)0x00020000) /*!< Clock stretching disable */
mbed_official 403:91a4bea587f4 4275 #define I2C_CR1_WUPEN ((uint32_t)0x00040000) /*!< Wakeup from STOP enable */
mbed_official 403:91a4bea587f4 4276 #define I2C_CR1_GCEN ((uint32_t)0x00080000) /*!< General call enable */
mbed_official 403:91a4bea587f4 4277 #define I2C_CR1_SMBHEN ((uint32_t)0x00100000) /*!< SMBus host address enable */
mbed_official 403:91a4bea587f4 4278 #define I2C_CR1_SMBDEN ((uint32_t)0x00200000) /*!< SMBus device default address enable */
mbed_official 403:91a4bea587f4 4279 #define I2C_CR1_ALERTEN ((uint32_t)0x00400000) /*!< SMBus alert enable */
mbed_official 403:91a4bea587f4 4280 #define I2C_CR1_PECEN ((uint32_t)0x00800000) /*!< PEC enable */
mbed_official 403:91a4bea587f4 4281
mbed_official 403:91a4bea587f4 4282 /****************** Bit definition for I2C_CR2 register ********************/
mbed_official 403:91a4bea587f4 4283 #define I2C_CR2_SADD ((uint32_t)0x000003FF) /*!< Slave address (master mode) */
mbed_official 403:91a4bea587f4 4284 #define I2C_CR2_RD_WRN ((uint32_t)0x00000400) /*!< Transfer direction (master mode) */
mbed_official 403:91a4bea587f4 4285 #define I2C_CR2_ADD10 ((uint32_t)0x00000800) /*!< 10-bit addressing mode (master mode) */
mbed_official 403:91a4bea587f4 4286 #define I2C_CR2_HEAD10R ((uint32_t)0x00001000) /*!< 10-bit address header only read direction (master mode) */
mbed_official 403:91a4bea587f4 4287 #define I2C_CR2_START ((uint32_t)0x00002000) /*!< START generation */
mbed_official 403:91a4bea587f4 4288 #define I2C_CR2_STOP ((uint32_t)0x00004000) /*!< STOP generation (master mode) */
mbed_official 403:91a4bea587f4 4289 #define I2C_CR2_NACK ((uint32_t)0x00008000) /*!< NACK generation (slave mode) */
mbed_official 403:91a4bea587f4 4290 #define I2C_CR2_NBYTES ((uint32_t)0x00FF0000) /*!< Number of bytes */
mbed_official 403:91a4bea587f4 4291 #define I2C_CR2_RELOAD ((uint32_t)0x01000000) /*!< NBYTES reload mode */
mbed_official 403:91a4bea587f4 4292 #define I2C_CR2_AUTOEND ((uint32_t)0x02000000) /*!< Automatic end mode (master mode) */
mbed_official 403:91a4bea587f4 4293 #define I2C_CR2_PECBYTE ((uint32_t)0x04000000) /*!< Packet error checking byte */
mbed_official 403:91a4bea587f4 4294
mbed_official 403:91a4bea587f4 4295 /******************* Bit definition for I2C_OAR1 register ******************/
mbed_official 403:91a4bea587f4 4296 #define I2C_OAR1_OA1 ((uint32_t)0x000003FF) /*!< Interface own address 1 */
mbed_official 403:91a4bea587f4 4297 #define I2C_OAR1_OA1MODE ((uint32_t)0x00000400) /*!< Own address 1 10-bit mode */
mbed_official 403:91a4bea587f4 4298 #define I2C_OAR1_OA1EN ((uint32_t)0x00008000) /*!< Own address 1 enable */
mbed_official 403:91a4bea587f4 4299
mbed_official 403:91a4bea587f4 4300 /******************* Bit definition for I2C_OAR2 register *******************/
mbed_official 403:91a4bea587f4 4301 #define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /*!< Interface own address 2 */
mbed_official 403:91a4bea587f4 4302 #define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /*!< Own address 2 masks */
mbed_official 403:91a4bea587f4 4303 #define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /*!< Own address 2 enable */
mbed_official 403:91a4bea587f4 4304
mbed_official 403:91a4bea587f4 4305 /******************* Bit definition for I2C_TIMINGR register *****************/
mbed_official 403:91a4bea587f4 4306 #define I2C_TIMINGR_SCLL ((uint32_t)0x000000FF) /*!< SCL low period (master mode) */
mbed_official 403:91a4bea587f4 4307 #define I2C_TIMINGR_SCLH ((uint32_t)0x0000FF00) /*!< SCL high period (master mode) */
mbed_official 403:91a4bea587f4 4308 #define I2C_TIMINGR_SDADEL ((uint32_t)0x000F0000) /*!< Data hold time */
mbed_official 403:91a4bea587f4 4309 #define I2C_TIMINGR_SCLDEL ((uint32_t)0x00F00000) /*!< Data setup time */
mbed_official 403:91a4bea587f4 4310 #define I2C_TIMINGR_PRESC ((uint32_t)0xF0000000) /*!< Timings prescaler */
mbed_official 403:91a4bea587f4 4311
mbed_official 403:91a4bea587f4 4312 /******************* Bit definition for I2C_TIMEOUTR register *****************/
mbed_official 403:91a4bea587f4 4313 #define I2C_TIMEOUTR_TIMEOUTA ((uint32_t)0x00000FFF) /*!< Bus timeout A */
mbed_official 403:91a4bea587f4 4314 #define I2C_TIMEOUTR_TIDLE ((uint32_t)0x00001000) /*!< Idle clock timeout detection */
mbed_official 403:91a4bea587f4 4315 #define I2C_TIMEOUTR_TIMOUTEN ((uint32_t)0x00008000) /*!< Clock timeout enable */
mbed_official 403:91a4bea587f4 4316 #define I2C_TIMEOUTR_TIMEOUTB ((uint32_t)0x0FFF0000) /*!< Bus timeout B*/
mbed_official 403:91a4bea587f4 4317 #define I2C_TIMEOUTR_TEXTEN ((uint32_t)0x80000000) /*!< Extended clock timeout enable */
mbed_official 403:91a4bea587f4 4318
mbed_official 403:91a4bea587f4 4319 /****************** Bit definition for I2C_ISR register *********************/
mbed_official 403:91a4bea587f4 4320 #define I2C_ISR_TXE ((uint32_t)0x00000001) /*!< Transmit data register empty */
mbed_official 403:91a4bea587f4 4321 #define I2C_ISR_TXIS ((uint32_t)0x00000002) /*!< Transmit interrupt status */
mbed_official 403:91a4bea587f4 4322 #define I2C_ISR_RXNE ((uint32_t)0x00000004) /*!< Receive data register not empty */
mbed_official 403:91a4bea587f4 4323 #define I2C_ISR_ADDR ((uint32_t)0x00000008) /*!< Address matched (slave mode)*/
mbed_official 403:91a4bea587f4 4324 #define I2C_ISR_NACKF ((uint32_t)0x00000010) /*!< NACK received flag */
mbed_official 403:91a4bea587f4 4325 #define I2C_ISR_STOPF ((uint32_t)0x00000020) /*!< STOP detection flag */
mbed_official 403:91a4bea587f4 4326 #define I2C_ISR_TC ((uint32_t)0x00000040) /*!< Transfer complete (master mode) */
mbed_official 403:91a4bea587f4 4327 #define I2C_ISR_TCR ((uint32_t)0x00000080) /*!< Transfer complete reload */
mbed_official 403:91a4bea587f4 4328 #define I2C_ISR_BERR ((uint32_t)0x00000100) /*!< Bus error */
mbed_official 403:91a4bea587f4 4329 #define I2C_ISR_ARLO ((uint32_t)0x00000200) /*!< Arbitration lost */
mbed_official 403:91a4bea587f4 4330 #define I2C_ISR_OVR ((uint32_t)0x00000400) /*!< Overrun/Underrun */
mbed_official 403:91a4bea587f4 4331 #define I2C_ISR_PECERR ((uint32_t)0x00000800) /*!< PEC error in reception */
mbed_official 403:91a4bea587f4 4332 #define I2C_ISR_TIMEOUT ((uint32_t)0x00001000) /*!< Timeout or Tlow detection flag */
mbed_official 403:91a4bea587f4 4333 #define I2C_ISR_ALERT ((uint32_t)0x00002000) /*!< SMBus alert */
mbed_official 403:91a4bea587f4 4334 #define I2C_ISR_BUSY ((uint32_t)0x00008000) /*!< Bus busy */
mbed_official 403:91a4bea587f4 4335 #define I2C_ISR_DIR ((uint32_t)0x00010000) /*!< Transfer direction (slave mode) */
mbed_official 403:91a4bea587f4 4336 #define I2C_ISR_ADDCODE ((uint32_t)0x00FE0000) /*!< Address match code (slave mode) */
mbed_official 403:91a4bea587f4 4337
mbed_official 403:91a4bea587f4 4338 /****************** Bit definition for I2C_ICR register *********************/
mbed_official 403:91a4bea587f4 4339 #define I2C_ICR_ADDRCF ((uint32_t)0x00000008) /*!< Address matched clear flag */
mbed_official 403:91a4bea587f4 4340 #define I2C_ICR_NACKCF ((uint32_t)0x00000010) /*!< NACK clear flag */
mbed_official 403:91a4bea587f4 4341 #define I2C_ICR_STOPCF ((uint32_t)0x00000020) /*!< STOP detection clear flag */
mbed_official 403:91a4bea587f4 4342 #define I2C_ICR_BERRCF ((uint32_t)0x00000100) /*!< Bus error clear flag */
mbed_official 403:91a4bea587f4 4343 #define I2C_ICR_ARLOCF ((uint32_t)0x00000200) /*!< Arbitration lost clear flag */
mbed_official 403:91a4bea587f4 4344 #define I2C_ICR_OVRCF ((uint32_t)0x00000400) /*!< Overrun/Underrun clear flag */
mbed_official 403:91a4bea587f4 4345 #define I2C_ICR_PECCF ((uint32_t)0x00000800) /*!< PAC error clear flag */
mbed_official 403:91a4bea587f4 4346 #define I2C_ICR_TIMOUTCF ((uint32_t)0x00001000) /*!< Timeout clear flag */
mbed_official 403:91a4bea587f4 4347 #define I2C_ICR_ALERTCF ((uint32_t)0x00002000) /*!< Alert clear flag */
mbed_official 403:91a4bea587f4 4348
mbed_official 403:91a4bea587f4 4349 /****************** Bit definition for I2C_PECR register ********************/
mbed_official 403:91a4bea587f4 4350 #define I2C_PECR_PEC ((uint32_t)0x000000FF) /*!< PEC register */
mbed_official 403:91a4bea587f4 4351
mbed_official 403:91a4bea587f4 4352 /****************** Bit definition for I2C_RXDR register *********************/
mbed_official 403:91a4bea587f4 4353 #define I2C_RXDR_RXDATA ((uint32_t)0x000000FF) /*!< 8-bit receive data */
mbed_official 403:91a4bea587f4 4354
mbed_official 403:91a4bea587f4 4355 /****************** Bit definition for I2C_TXDR register *********************/
mbed_official 403:91a4bea587f4 4356 #define I2C_TXDR_TXDATA ((uint32_t)0x000000FF) /*!< 8-bit transmit data */
mbed_official 403:91a4bea587f4 4357
mbed_official 403:91a4bea587f4 4358
mbed_official 403:91a4bea587f4 4359 /******************************************************************************/
mbed_official 403:91a4bea587f4 4360 /* */
mbed_official 403:91a4bea587f4 4361 /* Independent WATCHDOG (IWDG) */
mbed_official 403:91a4bea587f4 4362 /* */
mbed_official 403:91a4bea587f4 4363 /******************************************************************************/
mbed_official 403:91a4bea587f4 4364 /******************* Bit definition for IWDG_KR register ********************/
mbed_official 403:91a4bea587f4 4365 #define IWDG_KR_KEY ((uint32_t)0x0000FFFF) /*!< Key value (write only, read 0000h) */
mbed_official 403:91a4bea587f4 4366
mbed_official 403:91a4bea587f4 4367 /******************* Bit definition for IWDG_PR register ********************/
mbed_official 403:91a4bea587f4 4368 #define IWDG_PR_PR ((uint32_t)0x00000007) /*!< PR[2:0] (Prescaler divider) */
mbed_official 403:91a4bea587f4 4369 #define IWDG_PR_PR_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 403:91a4bea587f4 4370 #define IWDG_PR_PR_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 403:91a4bea587f4 4371 #define IWDG_PR_PR_2 ((uint32_t)0x00000004) /*!< Bit 2 */
mbed_official 403:91a4bea587f4 4372
mbed_official 403:91a4bea587f4 4373 /******************* Bit definition for IWDG_RLR register *******************/
mbed_official 403:91a4bea587f4 4374 #define IWDG_RLR_RL ((uint32_t)0x00000FFF) /*!< Watchdog counter reload value */
mbed_official 403:91a4bea587f4 4375
mbed_official 403:91a4bea587f4 4376 /******************* Bit definition for IWDG_SR register ********************/
mbed_official 403:91a4bea587f4 4377 #define IWDG_SR_PVU ((uint32_t)0x00000001) /*!< Watchdog prescaler value update */
mbed_official 403:91a4bea587f4 4378 #define IWDG_SR_RVU ((uint32_t)0x00000002) /*!< Watchdog counter reload value update */
mbed_official 403:91a4bea587f4 4379 #define IWDG_SR_WVU ((uint32_t)0x00000004) /*!< Watchdog counter window value update */
mbed_official 403:91a4bea587f4 4380
mbed_official 403:91a4bea587f4 4381 /******************* Bit definition for IWDG_KR register ********************/
mbed_official 403:91a4bea587f4 4382 #define IWDG_WINR_WIN ((uint32_t)0x00000FFF) /*!< Watchdog counter window value */
mbed_official 403:91a4bea587f4 4383
mbed_official 403:91a4bea587f4 4384 /******************************************************************************/
mbed_official 403:91a4bea587f4 4385 /* */
mbed_official 403:91a4bea587f4 4386 /* Power Control */
mbed_official 403:91a4bea587f4 4387 /* */
mbed_official 403:91a4bea587f4 4388 /******************************************************************************/
mbed_official 403:91a4bea587f4 4389 /******************** Bit definition for PWR_CR register ********************/
mbed_official 403:91a4bea587f4 4390 #define PWR_CR_LPDS ((uint32_t)0x00000001) /*!< Low-power Deepsleep */
mbed_official 403:91a4bea587f4 4391 #define PWR_CR_PDDS ((uint32_t)0x00000002) /*!< Power Down Deepsleep */
mbed_official 403:91a4bea587f4 4392 #define PWR_CR_CWUF ((uint32_t)0x00000004) /*!< Clear Wakeup Flag */
mbed_official 403:91a4bea587f4 4393 #define PWR_CR_CSBF ((uint32_t)0x00000008) /*!< Clear Standby Flag */
mbed_official 403:91a4bea587f4 4394 #define PWR_CR_PVDE ((uint32_t)0x00000010) /*!< Power Voltage Detector Enable */
mbed_official 403:91a4bea587f4 4395
mbed_official 403:91a4bea587f4 4396 #define PWR_CR_PLS ((uint32_t)0x000000E0) /*!< PLS[2:0] bits (PVD Level Selection) */
mbed_official 403:91a4bea587f4 4397 #define PWR_CR_PLS_0 ((uint32_t)0x00000020) /*!< Bit 0 */
mbed_official 403:91a4bea587f4 4398 #define PWR_CR_PLS_1 ((uint32_t)0x00000040) /*!< Bit 1 */
mbed_official 403:91a4bea587f4 4399 #define PWR_CR_PLS_2 ((uint32_t)0x00000080) /*!< Bit 2 */
mbed_official 403:91a4bea587f4 4400
mbed_official 403:91a4bea587f4 4401 /*!< PVD level configuration */
mbed_official 403:91a4bea587f4 4402 #define PWR_CR_PLS_LEV0 ((uint32_t)0x00000000) /*!< PVD level 0 */
mbed_official 403:91a4bea587f4 4403 #define PWR_CR_PLS_LEV1 ((uint32_t)0x00000020) /*!< PVD level 1 */
mbed_official 403:91a4bea587f4 4404 #define PWR_CR_PLS_LEV2 ((uint32_t)0x00000040) /*!< PVD level 2 */
mbed_official 403:91a4bea587f4 4405 #define PWR_CR_PLS_LEV3 ((uint32_t)0x00000060) /*!< PVD level 3 */
mbed_official 403:91a4bea587f4 4406 #define PWR_CR_PLS_LEV4 ((uint32_t)0x00000080) /*!< PVD level 4 */
mbed_official 403:91a4bea587f4 4407 #define PWR_CR_PLS_LEV5 ((uint32_t)0x000000A0) /*!< PVD level 5 */
mbed_official 403:91a4bea587f4 4408 #define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0) /*!< PVD level 6 */
mbed_official 403:91a4bea587f4 4409 #define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0) /*!< PVD level 7 */
mbed_official 403:91a4bea587f4 4410
mbed_official 403:91a4bea587f4 4411 #define PWR_CR_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */
mbed_official 403:91a4bea587f4 4412
mbed_official 403:91a4bea587f4 4413 /******************* Bit definition for PWR_CSR register ********************/
mbed_official 403:91a4bea587f4 4414 #define PWR_CSR_WUF ((uint32_t)0x00000001) /*!< Wakeup Flag */
mbed_official 403:91a4bea587f4 4415 #define PWR_CSR_SBF ((uint32_t)0x00000002) /*!< Standby Flag */
mbed_official 403:91a4bea587f4 4416 #define PWR_CSR_PVDO ((uint32_t)0x00000004) /*!< PVD Output */
mbed_official 403:91a4bea587f4 4417 #define PWR_CSR_VREFINTRDYF ((uint32_t)0x00000008) /*!< Internal voltage reference (VREFINT) ready flag */
mbed_official 403:91a4bea587f4 4418
mbed_official 403:91a4bea587f4 4419 #define PWR_CSR_EWUP1 ((uint32_t)0x00000100) /*!< Enable WKUP pin 1 */
mbed_official 403:91a4bea587f4 4420 #define PWR_CSR_EWUP2 ((uint32_t)0x00000200) /*!< Enable WKUP pin 2 */
mbed_official 403:91a4bea587f4 4421 #define PWR_CSR_EWUP3 ((uint32_t)0x00000400) /*!< Enable WKUP pin 3 */
mbed_official 403:91a4bea587f4 4422
mbed_official 403:91a4bea587f4 4423 /******************************************************************************/
mbed_official 403:91a4bea587f4 4424 /* */
mbed_official 403:91a4bea587f4 4425 /* Reset and Clock Control */
mbed_official 403:91a4bea587f4 4426 /* */
mbed_official 403:91a4bea587f4 4427 /******************************************************************************/
mbed_official 403:91a4bea587f4 4428 /******************** Bit definition for RCC_CR register ********************/
mbed_official 403:91a4bea587f4 4429 #define RCC_CR_HSION ((uint32_t)0x00000001)
mbed_official 403:91a4bea587f4 4430 #define RCC_CR_HSIRDY ((uint32_t)0x00000002)
mbed_official 403:91a4bea587f4 4431
mbed_official 403:91a4bea587f4 4432 #define RCC_CR_HSITRIM ((uint32_t)0x000000F8)
mbed_official 403:91a4bea587f4 4433 #define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008)/*!<Bit 0 */
mbed_official 403:91a4bea587f4 4434 #define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010)/*!<Bit 1 */
mbed_official 403:91a4bea587f4 4435 #define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020)/*!<Bit 2 */
mbed_official 403:91a4bea587f4 4436 #define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040)/*!<Bit 3 */
mbed_official 403:91a4bea587f4 4437 #define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080)/*!<Bit 4 */
mbed_official 403:91a4bea587f4 4438
mbed_official 403:91a4bea587f4 4439 #define RCC_CR_HSICAL ((uint32_t)0x0000FF00)
mbed_official 403:91a4bea587f4 4440 #define RCC_CR_HSICAL_0 ((uint32_t)0x00000100)/*!<Bit 0 */
mbed_official 403:91a4bea587f4 4441 #define RCC_CR_HSICAL_1 ((uint32_t)0x00000200)/*!<Bit 1 */
mbed_official 403:91a4bea587f4 4442 #define RCC_CR_HSICAL_2 ((uint32_t)0x00000400)/*!<Bit 2 */
mbed_official 403:91a4bea587f4 4443 #define RCC_CR_HSICAL_3 ((uint32_t)0x00000800)/*!<Bit 3 */
mbed_official 403:91a4bea587f4 4444 #define RCC_CR_HSICAL_4 ((uint32_t)0x00001000)/*!<Bit 4 */
mbed_official 403:91a4bea587f4 4445 #define RCC_CR_HSICAL_5 ((uint32_t)0x00002000)/*!<Bit 5 */
mbed_official 403:91a4bea587f4 4446 #define RCC_CR_HSICAL_6 ((uint32_t)0x00004000)/*!<Bit 6 */
mbed_official 403:91a4bea587f4 4447 #define RCC_CR_HSICAL_7 ((uint32_t)0x00008000)/*!<Bit 7 */
mbed_official 403:91a4bea587f4 4448
mbed_official 403:91a4bea587f4 4449 #define RCC_CR_HSEON ((uint32_t)0x00010000)
mbed_official 403:91a4bea587f4 4450 #define RCC_CR_HSERDY ((uint32_t)0x00020000)
mbed_official 403:91a4bea587f4 4451 #define RCC_CR_HSEBYP ((uint32_t)0x00040000)
mbed_official 403:91a4bea587f4 4452 #define RCC_CR_CSSON ((uint32_t)0x00080000)
mbed_official 403:91a4bea587f4 4453 #define RCC_CR_PLLON ((uint32_t)0x01000000)
mbed_official 403:91a4bea587f4 4454 #define RCC_CR_PLLRDY ((uint32_t)0x02000000)
mbed_official 403:91a4bea587f4 4455
mbed_official 403:91a4bea587f4 4456 /******************** Bit definition for RCC_CFGR register ******************/
mbed_official 403:91a4bea587f4 4457 /*!< SW configuration */
mbed_official 403:91a4bea587f4 4458 #define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
mbed_official 403:91a4bea587f4 4459 #define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 403:91a4bea587f4 4460 #define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 403:91a4bea587f4 4461
mbed_official 403:91a4bea587f4 4462 #define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
mbed_official 403:91a4bea587f4 4463 #define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
mbed_official 403:91a4bea587f4 4464 #define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
mbed_official 403:91a4bea587f4 4465
mbed_official 403:91a4bea587f4 4466 /*!< SWS configuration */
mbed_official 403:91a4bea587f4 4467 #define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
mbed_official 403:91a4bea587f4 4468 #define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
mbed_official 403:91a4bea587f4 4469 #define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
mbed_official 403:91a4bea587f4 4470
mbed_official 403:91a4bea587f4 4471 #define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
mbed_official 403:91a4bea587f4 4472 #define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
mbed_official 403:91a4bea587f4 4473 #define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
mbed_official 403:91a4bea587f4 4474
mbed_official 403:91a4bea587f4 4475 /*!< HPRE configuration */
mbed_official 403:91a4bea587f4 4476 #define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
mbed_official 403:91a4bea587f4 4477 #define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
mbed_official 403:91a4bea587f4 4478 #define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
mbed_official 403:91a4bea587f4 4479 #define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
mbed_official 403:91a4bea587f4 4480 #define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
mbed_official 403:91a4bea587f4 4481
mbed_official 403:91a4bea587f4 4482 #define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
mbed_official 403:91a4bea587f4 4483 #define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
mbed_official 403:91a4bea587f4 4484 #define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
mbed_official 403:91a4bea587f4 4485 #define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
mbed_official 403:91a4bea587f4 4486 #define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
mbed_official 403:91a4bea587f4 4487 #define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
mbed_official 403:91a4bea587f4 4488 #define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
mbed_official 403:91a4bea587f4 4489 #define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
mbed_official 403:91a4bea587f4 4490 #define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
mbed_official 403:91a4bea587f4 4491
mbed_official 403:91a4bea587f4 4492 /*!< PPRE1 configuration */
mbed_official 403:91a4bea587f4 4493 #define RCC_CFGR_PPRE1 ((uint32_t)0x00000700) /*!< PRE1[2:0] bits (APB1 prescaler) */
mbed_official 403:91a4bea587f4 4494 #define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) /*!< Bit 0 */
mbed_official 403:91a4bea587f4 4495 #define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) /*!< Bit 1 */
mbed_official 403:91a4bea587f4 4496 #define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) /*!< Bit 2 */
mbed_official 403:91a4bea587f4 4497
mbed_official 403:91a4bea587f4 4498 #define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
mbed_official 403:91a4bea587f4 4499 #define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */
mbed_official 403:91a4bea587f4 4500 #define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */
mbed_official 403:91a4bea587f4 4501 #define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */
mbed_official 403:91a4bea587f4 4502 #define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */
mbed_official 403:91a4bea587f4 4503
mbed_official 403:91a4bea587f4 4504 /*!< PPRE2 configuration */
mbed_official 403:91a4bea587f4 4505 #define RCC_CFGR_PPRE2 ((uint32_t)0x00003800) /*!< PRE2[2:0] bits (APB2 prescaler) */
mbed_official 403:91a4bea587f4 4506 #define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) /*!< Bit 0 */
mbed_official 403:91a4bea587f4 4507 #define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) /*!< Bit 1 */
mbed_official 403:91a4bea587f4 4508 #define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) /*!< Bit 2 */
mbed_official 403:91a4bea587f4 4509
mbed_official 403:91a4bea587f4 4510 #define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
mbed_official 403:91a4bea587f4 4511 #define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */
mbed_official 403:91a4bea587f4 4512 #define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */
mbed_official 403:91a4bea587f4 4513 #define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */
mbed_official 403:91a4bea587f4 4514 #define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */
mbed_official 403:91a4bea587f4 4515
mbed_official 403:91a4bea587f4 4516 #define RCC_CFGR_PLLSRC ((uint32_t)0x00010000) /*!< PLL entry clock source */
mbed_official 403:91a4bea587f4 4517 #define RCC_CFGR_PLLSRC_HSI_DIV2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */
mbed_official 403:91a4bea587f4 4518 #define RCC_CFGR_PLLSRC_HSE_PREDIV ((uint32_t)0x00010000) /*!< HSE/PREDIV clock selected as PLL entry clock source */
mbed_official 403:91a4bea587f4 4519
mbed_official 403:91a4bea587f4 4520 #define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) /*!< HSE divider for PLL entry */
mbed_official 403:91a4bea587f4 4521 #define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV1 ((uint32_t)0x00000000) /*!< HSE/PREDIV clock not divided for PLL entry */
mbed_official 403:91a4bea587f4 4522 #define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV2 ((uint32_t)0x00020000) /*!< HSE/PREDIV clock divided by 2 for PLL entry */
mbed_official 403:91a4bea587f4 4523
mbed_official 403:91a4bea587f4 4524 /*!< PLLMUL configuration */
mbed_official 403:91a4bea587f4 4525 #define RCC_CFGR_PLLMUL ((uint32_t)0x003C0000) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
mbed_official 403:91a4bea587f4 4526 #define RCC_CFGR_PLLMUL_0 ((uint32_t)0x00040000) /*!< Bit 0 */
mbed_official 403:91a4bea587f4 4527 #define RCC_CFGR_PLLMUL_1 ((uint32_t)0x00080000) /*!< Bit 1 */
mbed_official 403:91a4bea587f4 4528 #define RCC_CFGR_PLLMUL_2 ((uint32_t)0x00100000) /*!< Bit 2 */
mbed_official 403:91a4bea587f4 4529 #define RCC_CFGR_PLLMUL_3 ((uint32_t)0x00200000) /*!< Bit 3 */
mbed_official 403:91a4bea587f4 4530
mbed_official 403:91a4bea587f4 4531 #define RCC_CFGR_PLLMUL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */
mbed_official 403:91a4bea587f4 4532 #define RCC_CFGR_PLLMUL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */
mbed_official 403:91a4bea587f4 4533 #define RCC_CFGR_PLLMUL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */
mbed_official 403:91a4bea587f4 4534 #define RCC_CFGR_PLLMUL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */
mbed_official 403:91a4bea587f4 4535 #define RCC_CFGR_PLLMUL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */
mbed_official 403:91a4bea587f4 4536 #define RCC_CFGR_PLLMUL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */
mbed_official 403:91a4bea587f4 4537 #define RCC_CFGR_PLLMUL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */
mbed_official 403:91a4bea587f4 4538 #define RCC_CFGR_PLLMUL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */
mbed_official 403:91a4bea587f4 4539 #define RCC_CFGR_PLLMUL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */
mbed_official 403:91a4bea587f4 4540 #define RCC_CFGR_PLLMUL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */
mbed_official 403:91a4bea587f4 4541 #define RCC_CFGR_PLLMUL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */
mbed_official 403:91a4bea587f4 4542 #define RCC_CFGR_PLLMUL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */
mbed_official 403:91a4bea587f4 4543 #define RCC_CFGR_PLLMUL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */
mbed_official 403:91a4bea587f4 4544 #define RCC_CFGR_PLLMUL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */
mbed_official 403:91a4bea587f4 4545 #define RCC_CFGR_PLLMUL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */
mbed_official 403:91a4bea587f4 4546
mbed_official 403:91a4bea587f4 4547 /*!< USB configuration */
mbed_official 403:91a4bea587f4 4548 #define RCC_CFGR_USBPRE ((uint32_t)0x00400000) /*!< USB prescaler */
mbed_official 403:91a4bea587f4 4549
mbed_official 403:91a4bea587f4 4550 #define RCC_CFGR_USBPRE_DIV1_5 ((uint32_t)0x00000000) /*!< USB prescaler is PLL clock divided by 1.5 */
mbed_official 403:91a4bea587f4 4551 #define RCC_CFGR_USBPRE_DIV1 ((uint32_t)0x00400000) /*!< USB prescaler is PLL clock divided by 1 */
mbed_official 403:91a4bea587f4 4552
mbed_official 403:91a4bea587f4 4553 /*!< I2S configuration */
mbed_official 403:91a4bea587f4 4554 #define RCC_CFGR_I2SSRC ((uint32_t)0x00800000) /*!< I2S external clock source selection */
mbed_official 403:91a4bea587f4 4555
mbed_official 403:91a4bea587f4 4556 #define RCC_CFGR_I2SSRC_SYSCLK ((uint32_t)0x00000000) /*!< System clock selected as I2S clock source */
mbed_official 403:91a4bea587f4 4557 #define RCC_CFGR_I2SSRC_EXT ((uint32_t)0x00800000) /*!< External clock selected as I2S clock source */
mbed_official 403:91a4bea587f4 4558
mbed_official 403:91a4bea587f4 4559 /*!< MCO configuration */
mbed_official 403:91a4bea587f4 4560 #define RCC_CFGR_MCO ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */
mbed_official 403:91a4bea587f4 4561 #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */
mbed_official 403:91a4bea587f4 4562 #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */
mbed_official 403:91a4bea587f4 4563 #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */
mbed_official 403:91a4bea587f4 4564
mbed_official 403:91a4bea587f4 4565 #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
mbed_official 403:91a4bea587f4 4566 #define RCC_CFGR_MCO_LSI ((uint32_t)0x02000000) /*!< LSI clock selected as MCO source */
mbed_official 403:91a4bea587f4 4567 #define RCC_CFGR_MCO_LSE ((uint32_t)0x03000000) /*!< LSE clock selected as MCO source */
mbed_official 403:91a4bea587f4 4568 #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */
mbed_official 403:91a4bea587f4 4569 #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */
mbed_official 403:91a4bea587f4 4570 #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */
mbed_official 403:91a4bea587f4 4571 #define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */
mbed_official 403:91a4bea587f4 4572
mbed_official 403:91a4bea587f4 4573 #define RCC_CFGR_MCOF ((uint32_t)0x10000000) /*!< Microcontroller Clock Output Flag */
mbed_official 403:91a4bea587f4 4574 #define RCC_CFGR_PLLNODIV ((uint32_t)0x80000000) /*!< PLL is not divided to MCO */
mbed_official 403:91a4bea587f4 4575
mbed_official 403:91a4bea587f4 4576 /********************* Bit definition for RCC_CIR register ********************/
mbed_official 403:91a4bea587f4 4577 #define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */
mbed_official 403:91a4bea587f4 4578 #define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */
mbed_official 403:91a4bea587f4 4579 #define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */
mbed_official 403:91a4bea587f4 4580 #define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */
mbed_official 403:91a4bea587f4 4581 #define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */
mbed_official 403:91a4bea587f4 4582 #define RCC_CIR_CSSF ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */
mbed_official 403:91a4bea587f4 4583 #define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */
mbed_official 403:91a4bea587f4 4584 #define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */
mbed_official 403:91a4bea587f4 4585 #define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */
mbed_official 403:91a4bea587f4 4586 #define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */
mbed_official 403:91a4bea587f4 4587 #define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */
mbed_official 403:91a4bea587f4 4588 #define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */
mbed_official 403:91a4bea587f4 4589 #define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */
mbed_official 403:91a4bea587f4 4590 #define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */
mbed_official 403:91a4bea587f4 4591 #define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */
mbed_official 403:91a4bea587f4 4592 #define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */
mbed_official 403:91a4bea587f4 4593 #define RCC_CIR_CSSC ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */
mbed_official 403:91a4bea587f4 4594
mbed_official 403:91a4bea587f4 4595 /****************** Bit definition for RCC_APB2RSTR register *****************/
mbed_official 403:91a4bea587f4 4596 #define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00000001) /*!< SYSCFG reset */
mbed_official 403:91a4bea587f4 4597 #define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) /*!< TIM1 reset */
mbed_official 403:91a4bea587f4 4598 #define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /*!< SPI1 reset */
mbed_official 403:91a4bea587f4 4599 #define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00002000) /*!< TIM8 reset */
mbed_official 403:91a4bea587f4 4600 #define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /*!< USART1 reset */
mbed_official 403:91a4bea587f4 4601 #define RCC_APB2RSTR_TIM15RST ((uint32_t)0x00010000) /*!< TIM15 reset */
mbed_official 403:91a4bea587f4 4602 #define RCC_APB2RSTR_TIM16RST ((uint32_t)0x00020000) /*!< TIM16 reset */
mbed_official 403:91a4bea587f4 4603 #define RCC_APB2RSTR_TIM17RST ((uint32_t)0x00040000) /*!< TIM17 reset */
mbed_official 403:91a4bea587f4 4604
mbed_official 403:91a4bea587f4 4605 /****************** Bit definition for RCC_APB1RSTR register ******************/
mbed_official 403:91a4bea587f4 4606 #define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 reset */
mbed_official 403:91a4bea587f4 4607 #define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /*!< Timer 3 reset */
mbed_official 403:91a4bea587f4 4608 #define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) /*!< Timer 4 reset */
mbed_official 403:91a4bea587f4 4609 #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */
mbed_official 403:91a4bea587f4 4610 #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */
mbed_official 403:91a4bea587f4 4611 #define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog reset */
mbed_official 403:91a4bea587f4 4612 #define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /*!< SPI2 reset */
mbed_official 403:91a4bea587f4 4613 #define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) /*!< SPI3 reset */
mbed_official 403:91a4bea587f4 4614 #define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /*!< USART 2 reset */
mbed_official 403:91a4bea587f4 4615 #define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /*!< USART 3 reset */
mbed_official 403:91a4bea587f4 4616 #define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) /*!< UART 4 reset */
mbed_official 403:91a4bea587f4 4617 #define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) /*!< UART 5 reset */
mbed_official 403:91a4bea587f4 4618 #define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 reset */
mbed_official 403:91a4bea587f4 4619 #define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 reset */
mbed_official 403:91a4bea587f4 4620 #define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) /*!< USB reset */
mbed_official 403:91a4bea587f4 4621 #define RCC_APB1RSTR_CANRST ((uint32_t)0x02000000) /*!< CAN reset */
mbed_official 403:91a4bea587f4 4622 #define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< PWR reset */
mbed_official 403:91a4bea587f4 4623 #define RCC_APB1RSTR_DAC1RST ((uint32_t)0x20000000) /*!< DAC 1 reset */
mbed_official 403:91a4bea587f4 4624
mbed_official 403:91a4bea587f4 4625 /****************** Bit definition for RCC_AHBENR register ******************/
mbed_official 403:91a4bea587f4 4626 #define RCC_AHBENR_DMA1EN ((uint32_t)0x00000001) /*!< DMA1 clock enable */
mbed_official 403:91a4bea587f4 4627 #define RCC_AHBENR_DMA2EN ((uint32_t)0x00000002) /*!< DMA2 clock enable */
mbed_official 403:91a4bea587f4 4628 #define RCC_AHBENR_SRAMEN ((uint32_t)0x00000004) /*!< SRAM interface clock enable */
mbed_official 403:91a4bea587f4 4629 #define RCC_AHBENR_FLITFEN ((uint32_t)0x00000010) /*!< FLITF clock enable */
mbed_official 403:91a4bea587f4 4630 #define RCC_AHBENR_CRCEN ((uint32_t)0x00000040) /*!< CRC clock enable */
mbed_official 403:91a4bea587f4 4631 #define RCC_AHBENR_GPIOAEN ((uint32_t)0x00020000) /*!< GPIOA clock enable */
mbed_official 403:91a4bea587f4 4632 #define RCC_AHBENR_GPIOBEN ((uint32_t)0x00040000) /*!< GPIOB clock enable */
mbed_official 403:91a4bea587f4 4633 #define RCC_AHBENR_GPIOCEN ((uint32_t)0x00080000) /*!< GPIOC clock enable */
mbed_official 403:91a4bea587f4 4634 #define RCC_AHBENR_GPIODEN ((uint32_t)0x00100000) /*!< GPIOD clock enable */
mbed_official 403:91a4bea587f4 4635 #define RCC_AHBENR_GPIOEEN ((uint32_t)0x00200000) /*!< GPIOE clock enable */
mbed_official 403:91a4bea587f4 4636 #define RCC_AHBENR_GPIOFEN ((uint32_t)0x00400000) /*!< GPIOF clock enable */
mbed_official 403:91a4bea587f4 4637 #define RCC_AHBENR_TSCEN ((uint32_t)0x01000000) /*!< TS clock enable */
mbed_official 403:91a4bea587f4 4638 #define RCC_AHBENR_ADC12EN ((uint32_t)0x10000000) /*!< ADC1/ ADC2 clock enable */
mbed_official 403:91a4bea587f4 4639 #define RCC_AHBENR_ADC34EN ((uint32_t)0x20000000) /*!< ADC3/ ADC4 clock enable */
mbed_official 403:91a4bea587f4 4640
mbed_official 403:91a4bea587f4 4641 /***************** Bit definition for RCC_APB2ENR register ******************/
mbed_official 403:91a4bea587f4 4642 #define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00000001) /*!< SYSCFG clock enable */
mbed_official 403:91a4bea587f4 4643 #define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) /*!< TIM1 clock enable */
mbed_official 403:91a4bea587f4 4644 #define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /*!< SPI1 clock enable */
mbed_official 403:91a4bea587f4 4645 #define RCC_APB2ENR_TIM8EN ((uint32_t)0x00002000) /*!< TIM8 clock enable */
mbed_official 403:91a4bea587f4 4646 #define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable */
mbed_official 403:91a4bea587f4 4647 #define RCC_APB2ENR_TIM15EN ((uint32_t)0x00010000) /*!< TIM15 clock enable */
mbed_official 403:91a4bea587f4 4648 #define RCC_APB2ENR_TIM16EN ((uint32_t)0x00020000) /*!< TIM16 clock enable */
mbed_official 403:91a4bea587f4 4649 #define RCC_APB2ENR_TIM17EN ((uint32_t)0x00040000) /*!< TIM17 clock enable */
mbed_official 403:91a4bea587f4 4650
mbed_official 403:91a4bea587f4 4651 /****************** Bit definition for RCC_APB1ENR register ******************/
mbed_official 403:91a4bea587f4 4652 #define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enable */
mbed_official 403:91a4bea587f4 4653 #define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /*!< Timer 3 clock enable */
mbed_official 403:91a4bea587f4 4654 #define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) /*!< Timer 4 clock enable */
mbed_official 403:91a4bea587f4 4655 #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */
mbed_official 403:91a4bea587f4 4656 #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */
mbed_official 403:91a4bea587f4 4657 #define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */
mbed_official 403:91a4bea587f4 4658 #define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /*!< SPI2 clock enable */
mbed_official 403:91a4bea587f4 4659 #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) /*!< SPI3 clock enable */
mbed_official 403:91a4bea587f4 4660 #define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /*!< USART 2 clock enable */
mbed_official 403:91a4bea587f4 4661 #define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /*!< USART 3 clock enable */
mbed_official 403:91a4bea587f4 4662 #define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) /*!< UART 4 clock enable */
mbed_official 403:91a4bea587f4 4663 #define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) /*!< UART 5 clock enable */
mbed_official 403:91a4bea587f4 4664 #define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C 1 clock enable */
mbed_official 403:91a4bea587f4 4665 #define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /*!< I2C 2 clock enable */
mbed_official 403:91a4bea587f4 4666 #define RCC_APB1ENR_USBEN ((uint32_t)0x00800000) /*!< USB clock enable */
mbed_official 403:91a4bea587f4 4667 #define RCC_APB1ENR_CANEN ((uint32_t)0x02000000) /*!< CAN clock enable */
mbed_official 403:91a4bea587f4 4668 #define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< PWR clock enable */
mbed_official 403:91a4bea587f4 4669 #define RCC_APB1ENR_DAC1EN ((uint32_t)0x20000000) /*!< DAC 1 clock enable */
mbed_official 403:91a4bea587f4 4670
mbed_official 403:91a4bea587f4 4671 /******************** Bit definition for RCC_BDCR register ******************/
mbed_official 403:91a4bea587f4 4672 #define RCC_BDCR_LSE ((uint32_t)0x00000007) /*!< External Low Speed oscillator [2:0] bits */
mbed_official 403:91a4bea587f4 4673 #define RCC_BDCR_LSEON ((uint32_t)0x00000001) /*!< External Low Speed oscillator enable */
mbed_official 403:91a4bea587f4 4674 #define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /*!< External Low Speed oscillator Ready */
mbed_official 403:91a4bea587f4 4675 #define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) /*!< External Low Speed oscillator Bypass */
mbed_official 403:91a4bea587f4 4676
mbed_official 403:91a4bea587f4 4677 #define RCC_BDCR_LSEDRV ((uint32_t)0x00000018) /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
mbed_official 403:91a4bea587f4 4678 #define RCC_BDCR_LSEDRV_0 ((uint32_t)0x00000008) /*!< Bit 0 */
mbed_official 403:91a4bea587f4 4679 #define RCC_BDCR_LSEDRV_1 ((uint32_t)0x00000010) /*!< Bit 1 */
mbed_official 403:91a4bea587f4 4680
mbed_official 403:91a4bea587f4 4681 #define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) /*!< RTCSEL[1:0] bits (RTC clock source selection) */
mbed_official 403:91a4bea587f4 4682 #define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */
mbed_official 403:91a4bea587f4 4683 #define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */
mbed_official 403:91a4bea587f4 4684
mbed_official 403:91a4bea587f4 4685 /*!< RTC configuration */
mbed_official 403:91a4bea587f4 4686 #define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
mbed_official 403:91a4bea587f4 4687 #define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */
mbed_official 403:91a4bea587f4 4688 #define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */
mbed_official 403:91a4bea587f4 4689 #define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 32 used as RTC clock */
mbed_official 403:91a4bea587f4 4690
mbed_official 403:91a4bea587f4 4691 #define RCC_BDCR_RTCEN ((uint32_t)0x00008000) /*!< RTC clock enable */
mbed_official 403:91a4bea587f4 4692 #define RCC_BDCR_BDRST ((uint32_t)0x00010000) /*!< Backup domain software reset */
mbed_official 403:91a4bea587f4 4693
mbed_official 403:91a4bea587f4 4694 /******************** Bit definition for RCC_CSR register *******************/
mbed_official 403:91a4bea587f4 4695 #define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */
mbed_official 403:91a4bea587f4 4696 #define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */
mbed_official 403:91a4bea587f4 4697 #define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */
mbed_official 403:91a4bea587f4 4698 #define RCC_CSR_OBLRSTF ((uint32_t)0x02000000) /*!< OBL reset flag */
mbed_official 403:91a4bea587f4 4699 #define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */
mbed_official 403:91a4bea587f4 4700 #define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /*!< POR/PDR reset flag */
mbed_official 403:91a4bea587f4 4701 #define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */
mbed_official 403:91a4bea587f4 4702 #define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */
mbed_official 403:91a4bea587f4 4703 #define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */
mbed_official 403:91a4bea587f4 4704 #define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */
mbed_official 403:91a4bea587f4 4705
mbed_official 403:91a4bea587f4 4706 /******************* Bit definition for RCC_AHBRSTR register ****************/
mbed_official 403:91a4bea587f4 4707 #define RCC_AHBRSTR_GPIOARST ((uint32_t)0x00020000) /*!< GPIOA reset */
mbed_official 403:91a4bea587f4 4708 #define RCC_AHBRSTR_GPIOBRST ((uint32_t)0x00040000) /*!< GPIOB reset */
mbed_official 403:91a4bea587f4 4709 #define RCC_AHBRSTR_GPIOCRST ((uint32_t)0x00080000) /*!< GPIOC reset */
mbed_official 403:91a4bea587f4 4710 #define RCC_AHBRSTR_GPIODRST ((uint32_t)0x00100000) /*!< GPIOD reset */
mbed_official 403:91a4bea587f4 4711 #define RCC_AHBRSTR_GPIOERST ((uint32_t)0x00200000) /*!< GPIOE reset */
mbed_official 403:91a4bea587f4 4712 #define RCC_AHBRSTR_GPIOFRST ((uint32_t)0x00400000) /*!< GPIOF reset */
mbed_official 403:91a4bea587f4 4713 #define RCC_AHBRSTR_TSCRST ((uint32_t)0x01000000) /*!< TSC reset */
mbed_official 403:91a4bea587f4 4714 #define RCC_AHBRSTR_ADC12RST ((uint32_t)0x10000000) /*!< ADC1 & ADC2 reset */
mbed_official 403:91a4bea587f4 4715 #define RCC_AHBRSTR_ADC34RST ((uint32_t)0x20000000) /*!< ADC3 & ADC4 reset */
mbed_official 403:91a4bea587f4 4716
mbed_official 403:91a4bea587f4 4717 /******************* Bit definition for RCC_CFGR2 register ******************/
mbed_official 403:91a4bea587f4 4718 /*!< PREDIV configuration */
mbed_official 403:91a4bea587f4 4719 #define RCC_CFGR2_PREDIV ((uint32_t)0x0000000F) /*!< PREDIV[3:0] bits */
mbed_official 403:91a4bea587f4 4720 #define RCC_CFGR2_PREDIV_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 403:91a4bea587f4 4721 #define RCC_CFGR2_PREDIV_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 403:91a4bea587f4 4722 #define RCC_CFGR2_PREDIV_2 ((uint32_t)0x00000004) /*!< Bit 2 */
mbed_official 403:91a4bea587f4 4723 #define RCC_CFGR2_PREDIV_3 ((uint32_t)0x00000008) /*!< Bit 3 */
mbed_official 403:91a4bea587f4 4724
mbed_official 403:91a4bea587f4 4725 #define RCC_CFGR2_PREDIV_DIV1 ((uint32_t)0x00000000) /*!< PREDIV input clock not divided */
mbed_official 403:91a4bea587f4 4726 #define RCC_CFGR2_PREDIV_DIV2 ((uint32_t)0x00000001) /*!< PREDIV input clock divided by 2 */
mbed_official 403:91a4bea587f4 4727 #define RCC_CFGR2_PREDIV_DIV3 ((uint32_t)0x00000002) /*!< PREDIV input clock divided by 3 */
mbed_official 403:91a4bea587f4 4728 #define RCC_CFGR2_PREDIV_DIV4 ((uint32_t)0x00000003) /*!< PREDIV input clock divided by 4 */
mbed_official 403:91a4bea587f4 4729 #define RCC_CFGR2_PREDIV_DIV5 ((uint32_t)0x00000004) /*!< PREDIV input clock divided by 5 */
mbed_official 403:91a4bea587f4 4730 #define RCC_CFGR2_PREDIV_DIV6 ((uint32_t)0x00000005) /*!< PREDIV input clock divided by 6 */
mbed_official 403:91a4bea587f4 4731 #define RCC_CFGR2_PREDIV_DIV7 ((uint32_t)0x00000006) /*!< PREDIV input clock divided by 7 */
mbed_official 403:91a4bea587f4 4732 #define RCC_CFGR2_PREDIV_DIV8 ((uint32_t)0x00000007) /*!< PREDIV input clock divided by 8 */
mbed_official 403:91a4bea587f4 4733 #define RCC_CFGR2_PREDIV_DIV9 ((uint32_t)0x00000008) /*!< PREDIV input clock divided by 9 */
mbed_official 403:91a4bea587f4 4734 #define RCC_CFGR2_PREDIV_DIV10 ((uint32_t)0x00000009) /*!< PREDIV input clock divided by 10 */
mbed_official 403:91a4bea587f4 4735 #define RCC_CFGR2_PREDIV_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV input clock divided by 11 */
mbed_official 403:91a4bea587f4 4736 #define RCC_CFGR2_PREDIV_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV input clock divided by 12 */
mbed_official 403:91a4bea587f4 4737 #define RCC_CFGR2_PREDIV_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV input clock divided by 13 */
mbed_official 403:91a4bea587f4 4738 #define RCC_CFGR2_PREDIV_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV input clock divided by 14 */
mbed_official 403:91a4bea587f4 4739 #define RCC_CFGR2_PREDIV_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV input clock divided by 15 */
mbed_official 403:91a4bea587f4 4740 #define RCC_CFGR2_PREDIV_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV input clock divided by 16 */
mbed_official 403:91a4bea587f4 4741
mbed_official 403:91a4bea587f4 4742 /*!< ADCPRE12 configuration */
mbed_official 403:91a4bea587f4 4743 #define RCC_CFGR2_ADCPRE12 ((uint32_t)0x000001F0) /*!< ADCPRE12[8:4] bits */
mbed_official 403:91a4bea587f4 4744 #define RCC_CFGR2_ADCPRE12_0 ((uint32_t)0x00000010) /*!< Bit 0 */
mbed_official 403:91a4bea587f4 4745 #define RCC_CFGR2_ADCPRE12_1 ((uint32_t)0x00000020) /*!< Bit 1 */
mbed_official 403:91a4bea587f4 4746 #define RCC_CFGR2_ADCPRE12_2 ((uint32_t)0x00000040) /*!< Bit 2 */
mbed_official 403:91a4bea587f4 4747 #define RCC_CFGR2_ADCPRE12_3 ((uint32_t)0x00000080) /*!< Bit 3 */
mbed_official 403:91a4bea587f4 4748 #define RCC_CFGR2_ADCPRE12_4 ((uint32_t)0x00000100) /*!< Bit 4 */
mbed_official 403:91a4bea587f4 4749
mbed_official 403:91a4bea587f4 4750 #define RCC_CFGR2_ADCPRE12_NO ((uint32_t)0x00000000) /*!< ADC12 clock disabled, ADC12 can use AHB clock */
mbed_official 403:91a4bea587f4 4751 #define RCC_CFGR2_ADCPRE12_DIV1 ((uint32_t)0x00000100) /*!< ADC12 PLL clock divided by 1 */
mbed_official 403:91a4bea587f4 4752 #define RCC_CFGR2_ADCPRE12_DIV2 ((uint32_t)0x00000110) /*!< ADC12 PLL clock divided by 2 */
mbed_official 403:91a4bea587f4 4753 #define RCC_CFGR2_ADCPRE12_DIV4 ((uint32_t)0x00000120) /*!< ADC12 PLL clock divided by 4 */
mbed_official 403:91a4bea587f4 4754 #define RCC_CFGR2_ADCPRE12_DIV6 ((uint32_t)0x00000130) /*!< ADC12 PLL clock divided by 6 */
mbed_official 403:91a4bea587f4 4755 #define RCC_CFGR2_ADCPRE12_DIV8 ((uint32_t)0x00000140) /*!< ADC12 PLL clock divided by 8 */
mbed_official 403:91a4bea587f4 4756 #define RCC_CFGR2_ADCPRE12_DIV10 ((uint32_t)0x00000150) /*!< ADC12 PLL clock divided by 10 */
mbed_official 403:91a4bea587f4 4757 #define RCC_CFGR2_ADCPRE12_DIV12 ((uint32_t)0x00000160) /*!< ADC12 PLL clock divided by 12 */
mbed_official 403:91a4bea587f4 4758 #define RCC_CFGR2_ADCPRE12_DIV16 ((uint32_t)0x00000170) /*!< ADC12 PLL clock divided by 16 */
mbed_official 403:91a4bea587f4 4759 #define RCC_CFGR2_ADCPRE12_DIV32 ((uint32_t)0x00000180) /*!< ADC12 PLL clock divided by 32 */
mbed_official 403:91a4bea587f4 4760 #define RCC_CFGR2_ADCPRE12_DIV64 ((uint32_t)0x00000190) /*!< ADC12 PLL clock divided by 64 */
mbed_official 403:91a4bea587f4 4761 #define RCC_CFGR2_ADCPRE12_DIV128 ((uint32_t)0x000001A0) /*!< ADC12 PLL clock divided by 128 */
mbed_official 403:91a4bea587f4 4762 #define RCC_CFGR2_ADCPRE12_DIV256 ((uint32_t)0x000001B0) /*!< ADC12 PLL clock divided by 256 */
mbed_official 403:91a4bea587f4 4763
mbed_official 403:91a4bea587f4 4764 /*!< ADCPRE34 configuration */
mbed_official 403:91a4bea587f4 4765 #define RCC_CFGR2_ADCPRE34 ((uint32_t)0x00003E00) /*!< ADCPRE34[13:5] bits */
mbed_official 403:91a4bea587f4 4766 #define RCC_CFGR2_ADCPRE34_0 ((uint32_t)0x00000200) /*!< Bit 0 */
mbed_official 403:91a4bea587f4 4767 #define RCC_CFGR2_ADCPRE34_1 ((uint32_t)0x00000400) /*!< Bit 1 */
mbed_official 403:91a4bea587f4 4768 #define RCC_CFGR2_ADCPRE34_2 ((uint32_t)0x00000800) /*!< Bit 2 */
mbed_official 403:91a4bea587f4 4769 #define RCC_CFGR2_ADCPRE34_3 ((uint32_t)0x00001000) /*!< Bit 3 */
mbed_official 403:91a4bea587f4 4770 #define RCC_CFGR2_ADCPRE34_4 ((uint32_t)0x00002000) /*!< Bit 4 */
mbed_official 403:91a4bea587f4 4771
mbed_official 403:91a4bea587f4 4772 #define RCC_CFGR2_ADCPRE34_NO ((uint32_t)0x00000000) /*!< ADC34 clock disabled, ADC34 can use AHB clock */
mbed_official 403:91a4bea587f4 4773 #define RCC_CFGR2_ADCPRE34_DIV1 ((uint32_t)0x00002000) /*!< ADC34 PLL clock divided by 1 */
mbed_official 403:91a4bea587f4 4774 #define RCC_CFGR2_ADCPRE34_DIV2 ((uint32_t)0x00002200) /*!< ADC34 PLL clock divided by 2 */
mbed_official 403:91a4bea587f4 4775 #define RCC_CFGR2_ADCPRE34_DIV4 ((uint32_t)0x00002400) /*!< ADC34 PLL clock divided by 4 */
mbed_official 403:91a4bea587f4 4776 #define RCC_CFGR2_ADCPRE34_DIV6 ((uint32_t)0x00002600) /*!< ADC34 PLL clock divided by 6 */
mbed_official 403:91a4bea587f4 4777 #define RCC_CFGR2_ADCPRE34_DIV8 ((uint32_t)0x00002800) /*!< ADC34 PLL clock divided by 8 */
mbed_official 403:91a4bea587f4 4778 #define RCC_CFGR2_ADCPRE34_DIV10 ((uint32_t)0x00002A00) /*!< ADC34 PLL clock divided by 10 */
mbed_official 403:91a4bea587f4 4779 #define RCC_CFGR2_ADCPRE34_DIV12 ((uint32_t)0x00002C00) /*!< ADC34 PLL clock divided by 12 */
mbed_official 403:91a4bea587f4 4780 #define RCC_CFGR2_ADCPRE34_DIV16 ((uint32_t)0x00002E00) /*!< ADC34 PLL clock divided by 16 */
mbed_official 403:91a4bea587f4 4781 #define RCC_CFGR2_ADCPRE34_DIV32 ((uint32_t)0x00003000) /*!< ADC34 PLL clock divided by 32 */
mbed_official 403:91a4bea587f4 4782 #define RCC_CFGR2_ADCPRE34_DIV64 ((uint32_t)0x00003200) /*!< ADC34 PLL clock divided by 64 */
mbed_official 403:91a4bea587f4 4783 #define RCC_CFGR2_ADCPRE34_DIV128 ((uint32_t)0x00003400) /*!< ADC34 PLL clock divided by 128 */
mbed_official 403:91a4bea587f4 4784 #define RCC_CFGR2_ADCPRE34_DIV256 ((uint32_t)0x00003600) /*!< ADC34 PLL clock divided by 256 */
mbed_official 403:91a4bea587f4 4785
mbed_official 403:91a4bea587f4 4786 /******************* Bit definition for RCC_CFGR3 register ******************/
mbed_official 403:91a4bea587f4 4787 #define RCC_CFGR3_USART1SW ((uint32_t)0x00000003) /*!< USART1SW[1:0] bits */
mbed_official 403:91a4bea587f4 4788 #define RCC_CFGR3_USART1SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 403:91a4bea587f4 4789 #define RCC_CFGR3_USART1SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 403:91a4bea587f4 4790
mbed_official 403:91a4bea587f4 4791 #define RCC_CFGR3_USART1SW_PCLK ((uint32_t)0x00000000) /*!< PCLK1 clock used as USART1 clock source */
mbed_official 403:91a4bea587f4 4792 #define RCC_CFGR3_USART1SW_SYSCLK ((uint32_t)0x00000001) /*!< System clock selected as USART1 clock source */
mbed_official 403:91a4bea587f4 4793 #define RCC_CFGR3_USART1SW_LSE ((uint32_t)0x00000002) /*!< LSE oscillator clock used as USART1 clock source */
mbed_official 403:91a4bea587f4 4794 #define RCC_CFGR3_USART1SW_HSI ((uint32_t)0x00000003) /*!< HSI oscillator clock used as USART1 clock source */
mbed_official 403:91a4bea587f4 4795
mbed_official 403:91a4bea587f4 4796 #define RCC_CFGR3_I2CSW ((uint32_t)0x00000030) /*!< I2CSW bits */
mbed_official 403:91a4bea587f4 4797 #define RCC_CFGR3_I2C1SW ((uint32_t)0x00000010) /*!< I2C1SW bits */
mbed_official 403:91a4bea587f4 4798 #define RCC_CFGR3_I2C2SW ((uint32_t)0x00000020) /*!< I2C2SW bits */
mbed_official 403:91a4bea587f4 4799
mbed_official 403:91a4bea587f4 4800 #define RCC_CFGR3_I2C1SW_HSI ((uint32_t)0x00000000) /*!< HSI oscillator clock used as I2C1 clock source */
mbed_official 403:91a4bea587f4 4801 #define RCC_CFGR3_I2C1SW_SYSCLK ((uint32_t)0x00000010) /*!< System clock selected as I2C1 clock source */
mbed_official 403:91a4bea587f4 4802 #define RCC_CFGR3_I2C2SW_HSI ((uint32_t)0x00000000) /*!< HSI oscillator clock used as I2C2 clock source */
mbed_official 403:91a4bea587f4 4803 #define RCC_CFGR3_I2C2SW_SYSCLK ((uint32_t)0x00000020) /*!< System clock selected as I2C2 clock source */
mbed_official 403:91a4bea587f4 4804
mbed_official 403:91a4bea587f4 4805 #define RCC_CFGR3_TIMSW ((uint32_t)0x00000300) /*!< TIMSW bits */
mbed_official 403:91a4bea587f4 4806 #define RCC_CFGR3_TIM1SW ((uint32_t)0x00000100) /*!< TIM1SW bits */
mbed_official 403:91a4bea587f4 4807 #define RCC_CFGR3_TIM8SW ((uint32_t)0x00000200) /*!< TIM8SW bits */
mbed_official 403:91a4bea587f4 4808
mbed_official 403:91a4bea587f4 4809 #define RCC_CFGR3_TIM1SW_HCLK ((uint32_t)0x00000000) /*!< HCLK used as TIM1 clock source */
mbed_official 403:91a4bea587f4 4810 #define RCC_CFGR3_TIM1SW_PLL ((uint32_t)0x00000100) /*!< PLL clock used as TIM1 clock source */
mbed_official 403:91a4bea587f4 4811
mbed_official 403:91a4bea587f4 4812 #define RCC_CFGR3_TIM8SW_HCLK ((uint32_t)0x00000000) /*!< HCLK used as TIM8 clock source */
mbed_official 403:91a4bea587f4 4813 #define RCC_CFGR3_TIM8SW_PLL ((uint32_t)0x00000200) /*!< PLL clock used as TIM8 clock source */
mbed_official 403:91a4bea587f4 4814
mbed_official 403:91a4bea587f4 4815 #define RCC_CFGR3_USART2SW ((uint32_t)0x00030000) /*!< USART2SW[1:0] bits */
mbed_official 403:91a4bea587f4 4816 #define RCC_CFGR3_USART2SW_0 ((uint32_t)0x00010000) /*!< Bit 0 */
mbed_official 403:91a4bea587f4 4817 #define RCC_CFGR3_USART2SW_1 ((uint32_t)0x00020000) /*!< Bit 1 */
mbed_official 403:91a4bea587f4 4818
mbed_official 403:91a4bea587f4 4819 #define RCC_CFGR3_USART2SW_PCLK ((uint32_t)0x00000000) /*!< PCLK2 clock used as USART2 clock source */
mbed_official 403:91a4bea587f4 4820 #define RCC_CFGR3_USART2SW_SYSCLK ((uint32_t)0x00010000) /*!< System clock selected as USART2 clock source */
mbed_official 403:91a4bea587f4 4821 #define RCC_CFGR3_USART2SW_LSE ((uint32_t)0x00020000) /*!< LSE oscillator clock used as USART2 clock source */
mbed_official 403:91a4bea587f4 4822 #define RCC_CFGR3_USART2SW_HSI ((uint32_t)0x00030000) /*!< HSI oscillator clock used as USART2 clock source */
mbed_official 403:91a4bea587f4 4823
mbed_official 403:91a4bea587f4 4824 #define RCC_CFGR3_USART3SW ((uint32_t)0x000C0000) /*!< USART3SW[1:0] bits */
mbed_official 403:91a4bea587f4 4825 #define RCC_CFGR3_USART3SW_0 ((uint32_t)0x00040000) /*!< Bit 0 */
mbed_official 403:91a4bea587f4 4826 #define RCC_CFGR3_USART3SW_1 ((uint32_t)0x00080000) /*!< Bit 1 */
mbed_official 403:91a4bea587f4 4827
mbed_official 403:91a4bea587f4 4828 #define RCC_CFGR3_USART3SW_PCLK ((uint32_t)0x00000000) /*!< PCLK2 clock used as USART3 clock source */
mbed_official 403:91a4bea587f4 4829 #define RCC_CFGR3_USART3SW_SYSCLK ((uint32_t)0x00040000) /*!< System clock selected as USART3 clock source */
mbed_official 403:91a4bea587f4 4830 #define RCC_CFGR3_USART3SW_LSE ((uint32_t)0x00080000) /*!< LSE oscillator clock used as USART3 clock source */
mbed_official 403:91a4bea587f4 4831 #define RCC_CFGR3_USART3SW_HSI ((uint32_t)0x000C0000) /*!< HSI oscillator clock used as USART3 clock source */
mbed_official 403:91a4bea587f4 4832
mbed_official 403:91a4bea587f4 4833 #define RCC_CFGR3_UART4SW ((uint32_t)0x00300000) /*!< UART4SW[1:0] bits */
mbed_official 403:91a4bea587f4 4834 #define RCC_CFGR3_UART4SW_0 ((uint32_t)0x00100000) /*!< Bit 0 */
mbed_official 403:91a4bea587f4 4835 #define RCC_CFGR3_UART4SW_1 ((uint32_t)0x00200000) /*!< Bit 1 */
mbed_official 403:91a4bea587f4 4836
mbed_official 403:91a4bea587f4 4837 #define RCC_CFGR3_UART4SW_PCLK ((uint32_t)0x00000000) /*!< PCLK2 clock used as UART4 clock source */
mbed_official 403:91a4bea587f4 4838 #define RCC_CFGR3_UART4SW_SYSCLK ((uint32_t)0x00100000) /*!< System clock selected as UART4 clock source */
mbed_official 403:91a4bea587f4 4839 #define RCC_CFGR3_UART4SW_LSE ((uint32_t)0x00200000) /*!< LSE oscillator clock used as UART4 clock source */
mbed_official 403:91a4bea587f4 4840 #define RCC_CFGR3_UART4SW_HSI ((uint32_t)0x00300000) /*!< HSI oscillator clock used as UART4 clock source */
mbed_official 403:91a4bea587f4 4841
mbed_official 403:91a4bea587f4 4842 #define RCC_CFGR3_UART5SW ((uint32_t)0x00C00000) /*!< UART5SW[1:0] bits */
mbed_official 403:91a4bea587f4 4843 #define RCC_CFGR3_UART5SW_0 ((uint32_t)0x00400000) /*!< Bit 0 */
mbed_official 403:91a4bea587f4 4844 #define RCC_CFGR3_UART5SW_1 ((uint32_t)0x00800000) /*!< Bit 1 */
mbed_official 403:91a4bea587f4 4845
mbed_official 403:91a4bea587f4 4846 #define RCC_CFGR3_UART5SW_PCLK ((uint32_t)0x00000000) /*!< PCLK2 clock used as UART5 clock source */
mbed_official 403:91a4bea587f4 4847 #define RCC_CFGR3_UART5SW_SYSCLK ((uint32_t)0x00400000) /*!< System clock selected as UART5 clock source */
mbed_official 403:91a4bea587f4 4848 #define RCC_CFGR3_UART5SW_LSE ((uint32_t)0x00800000) /*!< LSE oscillator clock used as UART5 clock source */
mbed_official 403:91a4bea587f4 4849 #define RCC_CFGR3_UART5SW_HSI ((uint32_t)0x00C00000) /*!< HSI oscillator clock used as UART5 clock source */
mbed_official 403:91a4bea587f4 4850
mbed_official 403:91a4bea587f4 4851 /******************************************************************************/
mbed_official 403:91a4bea587f4 4852 /* */
mbed_official 403:91a4bea587f4 4853 /* Real-Time Clock (RTC) */
mbed_official 403:91a4bea587f4 4854 /* */
mbed_official 403:91a4bea587f4 4855 /******************************************************************************/
mbed_official 403:91a4bea587f4 4856 /******************** Bits definition for RTC_TR register *******************/
mbed_official 403:91a4bea587f4 4857 #define RTC_TR_PM ((uint32_t)0x00400000)
mbed_official 403:91a4bea587f4 4858 #define RTC_TR_HT ((uint32_t)0x00300000)
mbed_official 403:91a4bea587f4 4859 #define RTC_TR_HT_0 ((uint32_t)0x00100000)
mbed_official 403:91a4bea587f4 4860 #define RTC_TR_HT_1 ((uint32_t)0x00200000)
mbed_official 403:91a4bea587f4 4861 #define RTC_TR_HU ((uint32_t)0x000F0000)
mbed_official 403:91a4bea587f4 4862 #define RTC_TR_HU_0 ((uint32_t)0x00010000)
mbed_official 403:91a4bea587f4 4863 #define RTC_TR_HU_1 ((uint32_t)0x00020000)
mbed_official 403:91a4bea587f4 4864 #define RTC_TR_HU_2 ((uint32_t)0x00040000)
mbed_official 403:91a4bea587f4 4865 #define RTC_TR_HU_3 ((uint32_t)0x00080000)
mbed_official 403:91a4bea587f4 4866 #define RTC_TR_MNT ((uint32_t)0x00007000)
mbed_official 403:91a4bea587f4 4867 #define RTC_TR_MNT_0 ((uint32_t)0x00001000)
mbed_official 403:91a4bea587f4 4868 #define RTC_TR_MNT_1 ((uint32_t)0x00002000)
mbed_official 403:91a4bea587f4 4869 #define RTC_TR_MNT_2 ((uint32_t)0x00004000)
mbed_official 403:91a4bea587f4 4870 #define RTC_TR_MNU ((uint32_t)0x00000F00)
mbed_official 403:91a4bea587f4 4871 #define RTC_TR_MNU_0 ((uint32_t)0x00000100)
mbed_official 403:91a4bea587f4 4872 #define RTC_TR_MNU_1 ((uint32_t)0x00000200)
mbed_official 403:91a4bea587f4 4873 #define RTC_TR_MNU_2 ((uint32_t)0x00000400)
mbed_official 403:91a4bea587f4 4874 #define RTC_TR_MNU_3 ((uint32_t)0x00000800)
mbed_official 403:91a4bea587f4 4875 #define RTC_TR_ST ((uint32_t)0x00000070)
mbed_official 403:91a4bea587f4 4876 #define RTC_TR_ST_0 ((uint32_t)0x00000010)
mbed_official 403:91a4bea587f4 4877 #define RTC_TR_ST_1 ((uint32_t)0x00000020)
mbed_official 403:91a4bea587f4 4878 #define RTC_TR_ST_2 ((uint32_t)0x00000040)
mbed_official 403:91a4bea587f4 4879 #define RTC_TR_SU ((uint32_t)0x0000000F)
mbed_official 403:91a4bea587f4 4880 #define RTC_TR_SU_0 ((uint32_t)0x00000001)
mbed_official 403:91a4bea587f4 4881 #define RTC_TR_SU_1 ((uint32_t)0x00000002)
mbed_official 403:91a4bea587f4 4882 #define RTC_TR_SU_2 ((uint32_t)0x00000004)
mbed_official 403:91a4bea587f4 4883 #define RTC_TR_SU_3 ((uint32_t)0x00000008)
mbed_official 403:91a4bea587f4 4884
mbed_official 403:91a4bea587f4 4885 /******************** Bits definition for RTC_DR register *******************/
mbed_official 403:91a4bea587f4 4886 #define RTC_DR_YT ((uint32_t)0x00F00000)
mbed_official 403:91a4bea587f4 4887 #define RTC_DR_YT_0 ((uint32_t)0x00100000)
mbed_official 403:91a4bea587f4 4888 #define RTC_DR_YT_1 ((uint32_t)0x00200000)
mbed_official 403:91a4bea587f4 4889 #define RTC_DR_YT_2 ((uint32_t)0x00400000)
mbed_official 403:91a4bea587f4 4890 #define RTC_DR_YT_3 ((uint32_t)0x00800000)
mbed_official 403:91a4bea587f4 4891 #define RTC_DR_YU ((uint32_t)0x000F0000)
mbed_official 403:91a4bea587f4 4892 #define RTC_DR_YU_0 ((uint32_t)0x00010000)
mbed_official 403:91a4bea587f4 4893 #define RTC_DR_YU_1 ((uint32_t)0x00020000)
mbed_official 403:91a4bea587f4 4894 #define RTC_DR_YU_2 ((uint32_t)0x00040000)
mbed_official 403:91a4bea587f4 4895 #define RTC_DR_YU_3 ((uint32_t)0x00080000)
mbed_official 403:91a4bea587f4 4896 #define RTC_DR_WDU ((uint32_t)0x0000E000)
mbed_official 403:91a4bea587f4 4897 #define RTC_DR_WDU_0 ((uint32_t)0x00002000)
mbed_official 403:91a4bea587f4 4898 #define RTC_DR_WDU_1 ((uint32_t)0x00004000)
mbed_official 403:91a4bea587f4 4899 #define RTC_DR_WDU_2 ((uint32_t)0x00008000)
mbed_official 403:91a4bea587f4 4900 #define RTC_DR_MT ((uint32_t)0x00001000)
mbed_official 403:91a4bea587f4 4901 #define RTC_DR_MU ((uint32_t)0x00000F00)
mbed_official 403:91a4bea587f4 4902 #define RTC_DR_MU_0 ((uint32_t)0x00000100)
mbed_official 403:91a4bea587f4 4903 #define RTC_DR_MU_1 ((uint32_t)0x00000200)
mbed_official 403:91a4bea587f4 4904 #define RTC_DR_MU_2 ((uint32_t)0x00000400)
mbed_official 403:91a4bea587f4 4905 #define RTC_DR_MU_3 ((uint32_t)0x00000800)
mbed_official 403:91a4bea587f4 4906 #define RTC_DR_DT ((uint32_t)0x00000030)
mbed_official 403:91a4bea587f4 4907 #define RTC_DR_DT_0 ((uint32_t)0x00000010)
mbed_official 403:91a4bea587f4 4908 #define RTC_DR_DT_1 ((uint32_t)0x00000020)
mbed_official 403:91a4bea587f4 4909 #define RTC_DR_DU ((uint32_t)0x0000000F)
mbed_official 403:91a4bea587f4 4910 #define RTC_DR_DU_0 ((uint32_t)0x00000001)
mbed_official 403:91a4bea587f4 4911 #define RTC_DR_DU_1 ((uint32_t)0x00000002)
mbed_official 403:91a4bea587f4 4912 #define RTC_DR_DU_2 ((uint32_t)0x00000004)
mbed_official 403:91a4bea587f4 4913 #define RTC_DR_DU_3 ((uint32_t)0x00000008)
mbed_official 403:91a4bea587f4 4914
mbed_official 403:91a4bea587f4 4915 /******************** Bits definition for RTC_CR register *******************/
mbed_official 403:91a4bea587f4 4916 #define RTC_CR_COE ((uint32_t)0x00800000)
mbed_official 403:91a4bea587f4 4917 #define RTC_CR_OSEL ((uint32_t)0x00600000)
mbed_official 403:91a4bea587f4 4918 #define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
mbed_official 403:91a4bea587f4 4919 #define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
mbed_official 403:91a4bea587f4 4920 #define RTC_CR_POL ((uint32_t)0x00100000)
mbed_official 403:91a4bea587f4 4921 #define RTC_CR_COSEL ((uint32_t)0x00080000)
mbed_official 403:91a4bea587f4 4922 #define RTC_CR_BCK ((uint32_t)0x00040000)
mbed_official 403:91a4bea587f4 4923 #define RTC_CR_SUB1H ((uint32_t)0x00020000)
mbed_official 403:91a4bea587f4 4924 #define RTC_CR_ADD1H ((uint32_t)0x00010000)
mbed_official 403:91a4bea587f4 4925 #define RTC_CR_TSIE ((uint32_t)0x00008000)
mbed_official 403:91a4bea587f4 4926 #define RTC_CR_WUTIE ((uint32_t)0x00004000)
mbed_official 403:91a4bea587f4 4927 #define RTC_CR_ALRBIE ((uint32_t)0x00002000)
mbed_official 403:91a4bea587f4 4928 #define RTC_CR_ALRAIE ((uint32_t)0x00001000)
mbed_official 403:91a4bea587f4 4929 #define RTC_CR_TSE ((uint32_t)0x00000800)
mbed_official 403:91a4bea587f4 4930 #define RTC_CR_WUTE ((uint32_t)0x00000400)
mbed_official 403:91a4bea587f4 4931 #define RTC_CR_ALRBE ((uint32_t)0x00000200)
mbed_official 403:91a4bea587f4 4932 #define RTC_CR_ALRAE ((uint32_t)0x00000100)
mbed_official 403:91a4bea587f4 4933 #define RTC_CR_FMT ((uint32_t)0x00000040)
mbed_official 403:91a4bea587f4 4934 #define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
mbed_official 403:91a4bea587f4 4935 #define RTC_CR_REFCKON ((uint32_t)0x00000010)
mbed_official 403:91a4bea587f4 4936 #define RTC_CR_TSEDGE ((uint32_t)0x00000008)
mbed_official 403:91a4bea587f4 4937 #define RTC_CR_WUCKSEL ((uint32_t)0x00000007)
mbed_official 403:91a4bea587f4 4938 #define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001)
mbed_official 403:91a4bea587f4 4939 #define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002)
mbed_official 403:91a4bea587f4 4940 #define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004)
mbed_official 403:91a4bea587f4 4941
mbed_official 403:91a4bea587f4 4942 /******************** Bits definition for RTC_ISR register ******************/
mbed_official 403:91a4bea587f4 4943 #define RTC_ISR_RECALPF ((uint32_t)0x00010000)
mbed_official 403:91a4bea587f4 4944 #define RTC_ISR_TAMP3F ((uint32_t)0x00008000)
mbed_official 403:91a4bea587f4 4945 #define RTC_ISR_TAMP2F ((uint32_t)0x00004000)
mbed_official 403:91a4bea587f4 4946 #define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
mbed_official 403:91a4bea587f4 4947 #define RTC_ISR_TSOVF ((uint32_t)0x00001000)
mbed_official 403:91a4bea587f4 4948 #define RTC_ISR_TSF ((uint32_t)0x00000800)
mbed_official 403:91a4bea587f4 4949 #define RTC_ISR_WUTF ((uint32_t)0x00000400)
mbed_official 403:91a4bea587f4 4950 #define RTC_ISR_ALRBF ((uint32_t)0x00000200)
mbed_official 403:91a4bea587f4 4951 #define RTC_ISR_ALRAF ((uint32_t)0x00000100)
mbed_official 403:91a4bea587f4 4952 #define RTC_ISR_INIT ((uint32_t)0x00000080)
mbed_official 403:91a4bea587f4 4953 #define RTC_ISR_INITF ((uint32_t)0x00000040)
mbed_official 403:91a4bea587f4 4954 #define RTC_ISR_RSF ((uint32_t)0x00000020)
mbed_official 403:91a4bea587f4 4955 #define RTC_ISR_INITS ((uint32_t)0x00000010)
mbed_official 403:91a4bea587f4 4956 #define RTC_ISR_SHPF ((uint32_t)0x00000008)
mbed_official 403:91a4bea587f4 4957 #define RTC_ISR_WUTWF ((uint32_t)0x00000004)
mbed_official 403:91a4bea587f4 4958 #define RTC_ISR_ALRBWF ((uint32_t)0x00000002)
mbed_official 403:91a4bea587f4 4959 #define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
mbed_official 403:91a4bea587f4 4960
mbed_official 403:91a4bea587f4 4961 /******************** Bits definition for RTC_PRER register *****************/
mbed_official 403:91a4bea587f4 4962 #define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
mbed_official 403:91a4bea587f4 4963 #define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF)
mbed_official 403:91a4bea587f4 4964
mbed_official 403:91a4bea587f4 4965 /******************** Bits definition for RTC_WUTR register *****************/
mbed_official 403:91a4bea587f4 4966 #define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
mbed_official 403:91a4bea587f4 4967
mbed_official 403:91a4bea587f4 4968 /******************** Bits definition for RTC_ALRMAR register ***************/
mbed_official 403:91a4bea587f4 4969 #define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
mbed_official 403:91a4bea587f4 4970 #define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
mbed_official 403:91a4bea587f4 4971 #define RTC_ALRMAR_DT ((uint32_t)0x30000000)
mbed_official 403:91a4bea587f4 4972 #define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
mbed_official 403:91a4bea587f4 4973 #define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
mbed_official 403:91a4bea587f4 4974 #define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
mbed_official 403:91a4bea587f4 4975 #define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
mbed_official 403:91a4bea587f4 4976 #define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
mbed_official 403:91a4bea587f4 4977 #define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
mbed_official 403:91a4bea587f4 4978 #define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
mbed_official 403:91a4bea587f4 4979 #define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
mbed_official 403:91a4bea587f4 4980 #define RTC_ALRMAR_PM ((uint32_t)0x00400000)
mbed_official 403:91a4bea587f4 4981 #define RTC_ALRMAR_HT ((uint32_t)0x00300000)
mbed_official 403:91a4bea587f4 4982 #define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
mbed_official 403:91a4bea587f4 4983 #define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
mbed_official 403:91a4bea587f4 4984 #define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
mbed_official 403:91a4bea587f4 4985 #define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
mbed_official 403:91a4bea587f4 4986 #define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
mbed_official 403:91a4bea587f4 4987 #define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
mbed_official 403:91a4bea587f4 4988 #define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
mbed_official 403:91a4bea587f4 4989 #define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
mbed_official 403:91a4bea587f4 4990 #define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
mbed_official 403:91a4bea587f4 4991 #define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
mbed_official 403:91a4bea587f4 4992 #define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
mbed_official 403:91a4bea587f4 4993 #define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
mbed_official 403:91a4bea587f4 4994 #define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
mbed_official 403:91a4bea587f4 4995 #define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
mbed_official 403:91a4bea587f4 4996 #define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
mbed_official 403:91a4bea587f4 4997 #define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
mbed_official 403:91a4bea587f4 4998 #define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
mbed_official 403:91a4bea587f4 4999 #define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
mbed_official 403:91a4bea587f4 5000 #define RTC_ALRMAR_ST ((uint32_t)0x00000070)
mbed_official 403:91a4bea587f4 5001 #define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
mbed_official 403:91a4bea587f4 5002 #define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
mbed_official 403:91a4bea587f4 5003 #define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
mbed_official 403:91a4bea587f4 5004 #define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
mbed_official 403:91a4bea587f4 5005 #define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
mbed_official 403:91a4bea587f4 5006 #define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
mbed_official 403:91a4bea587f4 5007 #define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
mbed_official 403:91a4bea587f4 5008 #define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
mbed_official 403:91a4bea587f4 5009
mbed_official 403:91a4bea587f4 5010 /******************** Bits definition for RTC_ALRMBR register ***************/
mbed_official 403:91a4bea587f4 5011 #define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000)
mbed_official 403:91a4bea587f4 5012 #define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000)
mbed_official 403:91a4bea587f4 5013 #define RTC_ALRMBR_DT ((uint32_t)0x30000000)
mbed_official 403:91a4bea587f4 5014 #define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000)
mbed_official 403:91a4bea587f4 5015 #define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000)
mbed_official 403:91a4bea587f4 5016 #define RTC_ALRMBR_DU ((uint32_t)0x0F000000)
mbed_official 403:91a4bea587f4 5017 #define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000)
mbed_official 403:91a4bea587f4 5018 #define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000)
mbed_official 403:91a4bea587f4 5019 #define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000)
mbed_official 403:91a4bea587f4 5020 #define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000)
mbed_official 403:91a4bea587f4 5021 #define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000)
mbed_official 403:91a4bea587f4 5022 #define RTC_ALRMBR_PM ((uint32_t)0x00400000)
mbed_official 403:91a4bea587f4 5023 #define RTC_ALRMBR_HT ((uint32_t)0x00300000)
mbed_official 403:91a4bea587f4 5024 #define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000)
mbed_official 403:91a4bea587f4 5025 #define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000)
mbed_official 403:91a4bea587f4 5026 #define RTC_ALRMBR_HU ((uint32_t)0x000F0000)
mbed_official 403:91a4bea587f4 5027 #define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000)
mbed_official 403:91a4bea587f4 5028 #define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000)
mbed_official 403:91a4bea587f4 5029 #define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000)
mbed_official 403:91a4bea587f4 5030 #define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000)
mbed_official 403:91a4bea587f4 5031 #define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000)
mbed_official 403:91a4bea587f4 5032 #define RTC_ALRMBR_MNT ((uint32_t)0x00007000)
mbed_official 403:91a4bea587f4 5033 #define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000)
mbed_official 403:91a4bea587f4 5034 #define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000)
mbed_official 403:91a4bea587f4 5035 #define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000)
mbed_official 403:91a4bea587f4 5036 #define RTC_ALRMBR_MNU ((uint32_t)0x00000F00)
mbed_official 403:91a4bea587f4 5037 #define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100)
mbed_official 403:91a4bea587f4 5038 #define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200)
mbed_official 403:91a4bea587f4 5039 #define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400)
mbed_official 403:91a4bea587f4 5040 #define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800)
mbed_official 403:91a4bea587f4 5041 #define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080)
mbed_official 403:91a4bea587f4 5042 #define RTC_ALRMBR_ST ((uint32_t)0x00000070)
mbed_official 403:91a4bea587f4 5043 #define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010)
mbed_official 403:91a4bea587f4 5044 #define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020)
mbed_official 403:91a4bea587f4 5045 #define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040)
mbed_official 403:91a4bea587f4 5046 #define RTC_ALRMBR_SU ((uint32_t)0x0000000F)
mbed_official 403:91a4bea587f4 5047 #define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001)
mbed_official 403:91a4bea587f4 5048 #define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002)
mbed_official 403:91a4bea587f4 5049 #define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004)
mbed_official 403:91a4bea587f4 5050 #define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008)
mbed_official 403:91a4bea587f4 5051
mbed_official 403:91a4bea587f4 5052 /******************** Bits definition for RTC_WPR register ******************/
mbed_official 403:91a4bea587f4 5053 #define RTC_WPR_KEY ((uint32_t)0x000000FF)
mbed_official 403:91a4bea587f4 5054
mbed_official 403:91a4bea587f4 5055 /******************** Bits definition for RTC_SSR register ******************/
mbed_official 403:91a4bea587f4 5056 #define RTC_SSR_SS ((uint32_t)0x0000FFFF)
mbed_official 403:91a4bea587f4 5057
mbed_official 403:91a4bea587f4 5058 /******************** Bits definition for RTC_SHIFTR register ***************/
mbed_official 403:91a4bea587f4 5059 #define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
mbed_official 403:91a4bea587f4 5060 #define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
mbed_official 403:91a4bea587f4 5061
mbed_official 403:91a4bea587f4 5062 /******************** Bits definition for RTC_TSTR register *****************/
mbed_official 403:91a4bea587f4 5063 #define RTC_TSTR_PM ((uint32_t)0x00400000)
mbed_official 403:91a4bea587f4 5064 #define RTC_TSTR_HT ((uint32_t)0x00300000)
mbed_official 403:91a4bea587f4 5065 #define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
mbed_official 403:91a4bea587f4 5066 #define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
mbed_official 403:91a4bea587f4 5067 #define RTC_TSTR_HU ((uint32_t)0x000F0000)
mbed_official 403:91a4bea587f4 5068 #define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
mbed_official 403:91a4bea587f4 5069 #define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
mbed_official 403:91a4bea587f4 5070 #define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
mbed_official 403:91a4bea587f4 5071 #define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
mbed_official 403:91a4bea587f4 5072 #define RTC_TSTR_MNT ((uint32_t)0x00007000)
mbed_official 403:91a4bea587f4 5073 #define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
mbed_official 403:91a4bea587f4 5074 #define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
mbed_official 403:91a4bea587f4 5075 #define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
mbed_official 403:91a4bea587f4 5076 #define RTC_TSTR_MNU ((uint32_t)0x00000F00)
mbed_official 403:91a4bea587f4 5077 #define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
mbed_official 403:91a4bea587f4 5078 #define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
mbed_official 403:91a4bea587f4 5079 #define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
mbed_official 403:91a4bea587f4 5080 #define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
mbed_official 403:91a4bea587f4 5081 #define RTC_TSTR_ST ((uint32_t)0x00000070)
mbed_official 403:91a4bea587f4 5082 #define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
mbed_official 403:91a4bea587f4 5083 #define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
mbed_official 403:91a4bea587f4 5084 #define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
mbed_official 403:91a4bea587f4 5085 #define RTC_TSTR_SU ((uint32_t)0x0000000F)
mbed_official 403:91a4bea587f4 5086 #define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
mbed_official 403:91a4bea587f4 5087 #define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
mbed_official 403:91a4bea587f4 5088 #define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
mbed_official 403:91a4bea587f4 5089 #define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
mbed_official 403:91a4bea587f4 5090
mbed_official 403:91a4bea587f4 5091 /******************** Bits definition for RTC_TSDR register *****************/
mbed_official 403:91a4bea587f4 5092 #define RTC_TSDR_WDU ((uint32_t)0x0000E000)
mbed_official 403:91a4bea587f4 5093 #define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
mbed_official 403:91a4bea587f4 5094 #define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
mbed_official 403:91a4bea587f4 5095 #define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
mbed_official 403:91a4bea587f4 5096 #define RTC_TSDR_MT ((uint32_t)0x00001000)
mbed_official 403:91a4bea587f4 5097 #define RTC_TSDR_MU ((uint32_t)0x00000F00)
mbed_official 403:91a4bea587f4 5098 #define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
mbed_official 403:91a4bea587f4 5099 #define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
mbed_official 403:91a4bea587f4 5100 #define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
mbed_official 403:91a4bea587f4 5101 #define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
mbed_official 403:91a4bea587f4 5102 #define RTC_TSDR_DT ((uint32_t)0x00000030)
mbed_official 403:91a4bea587f4 5103 #define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
mbed_official 403:91a4bea587f4 5104 #define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
mbed_official 403:91a4bea587f4 5105 #define RTC_TSDR_DU ((uint32_t)0x0000000F)
mbed_official 403:91a4bea587f4 5106 #define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
mbed_official 403:91a4bea587f4 5107 #define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
mbed_official 403:91a4bea587f4 5108 #define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
mbed_official 403:91a4bea587f4 5109 #define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
mbed_official 403:91a4bea587f4 5110
mbed_official 403:91a4bea587f4 5111 /******************** Bits definition for RTC_TSSSR register ****************/
mbed_official 403:91a4bea587f4 5112 #define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)
mbed_official 403:91a4bea587f4 5113
mbed_official 403:91a4bea587f4 5114 /******************** Bits definition for RTC_CAL register *****************/
mbed_official 403:91a4bea587f4 5115 #define RTC_CALR_CALP ((uint32_t)0x00008000)
mbed_official 403:91a4bea587f4 5116 #define RTC_CALR_CALW8 ((uint32_t)0x00004000)
mbed_official 403:91a4bea587f4 5117 #define RTC_CALR_CALW16 ((uint32_t)0x00002000)
mbed_official 403:91a4bea587f4 5118 #define RTC_CALR_CALM ((uint32_t)0x000001FF)
mbed_official 403:91a4bea587f4 5119 #define RTC_CALR_CALM_0 ((uint32_t)0x00000001)
mbed_official 403:91a4bea587f4 5120 #define RTC_CALR_CALM_1 ((uint32_t)0x00000002)
mbed_official 403:91a4bea587f4 5121 #define RTC_CALR_CALM_2 ((uint32_t)0x00000004)
mbed_official 403:91a4bea587f4 5122 #define RTC_CALR_CALM_3 ((uint32_t)0x00000008)
mbed_official 403:91a4bea587f4 5123 #define RTC_CALR_CALM_4 ((uint32_t)0x00000010)
mbed_official 403:91a4bea587f4 5124 #define RTC_CALR_CALM_5 ((uint32_t)0x00000020)
mbed_official 403:91a4bea587f4 5125 #define RTC_CALR_CALM_6 ((uint32_t)0x00000040)
mbed_official 403:91a4bea587f4 5126 #define RTC_CALR_CALM_7 ((uint32_t)0x00000080)
mbed_official 403:91a4bea587f4 5127 #define RTC_CALR_CALM_8 ((uint32_t)0x00000100)
mbed_official 403:91a4bea587f4 5128
mbed_official 403:91a4bea587f4 5129 /******************** Bits definition for RTC_TAFCR register ****************/
mbed_official 403:91a4bea587f4 5130 #define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)
mbed_official 403:91a4bea587f4 5131 #define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)
mbed_official 403:91a4bea587f4 5132 #define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)
mbed_official 403:91a4bea587f4 5133 #define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)
mbed_official 403:91a4bea587f4 5134 #define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)
mbed_official 403:91a4bea587f4 5135 #define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)
mbed_official 403:91a4bea587f4 5136 #define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)
mbed_official 403:91a4bea587f4 5137 #define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)
mbed_official 403:91a4bea587f4 5138 #define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)
mbed_official 403:91a4bea587f4 5139 #define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)
mbed_official 403:91a4bea587f4 5140 #define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)
mbed_official 403:91a4bea587f4 5141 #define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)
mbed_official 403:91a4bea587f4 5142 #define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)
mbed_official 403:91a4bea587f4 5143 #define RTC_TAFCR_TAMP3TRG ((uint32_t)0x00000040)
mbed_official 403:91a4bea587f4 5144 #define RTC_TAFCR_TAMP3E ((uint32_t)0x00000020)
mbed_official 403:91a4bea587f4 5145 #define RTC_TAFCR_TAMP2TRG ((uint32_t)0x00000010)
mbed_official 403:91a4bea587f4 5146 #define RTC_TAFCR_TAMP2E ((uint32_t)0x00000008)
mbed_official 403:91a4bea587f4 5147 #define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)
mbed_official 403:91a4bea587f4 5148 #define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)
mbed_official 403:91a4bea587f4 5149 #define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)
mbed_official 403:91a4bea587f4 5150
mbed_official 403:91a4bea587f4 5151 /******************** Bits definition for RTC_ALRMASSR register *************/
mbed_official 403:91a4bea587f4 5152 #define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
mbed_official 403:91a4bea587f4 5153 #define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
mbed_official 403:91a4bea587f4 5154 #define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
mbed_official 403:91a4bea587f4 5155 #define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
mbed_official 403:91a4bea587f4 5156 #define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
mbed_official 403:91a4bea587f4 5157 #define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
mbed_official 403:91a4bea587f4 5158
mbed_official 403:91a4bea587f4 5159 /******************** Bits definition for RTC_ALRMBSSR register *************/
mbed_official 403:91a4bea587f4 5160 #define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000)
mbed_official 403:91a4bea587f4 5161 #define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000)
mbed_official 403:91a4bea587f4 5162 #define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000)
mbed_official 403:91a4bea587f4 5163 #define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000)
mbed_official 403:91a4bea587f4 5164 #define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000)
mbed_official 403:91a4bea587f4 5165 #define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFF)
mbed_official 403:91a4bea587f4 5166
mbed_official 403:91a4bea587f4 5167 /******************** Bits definition for RTC_BKP0R register ****************/
mbed_official 403:91a4bea587f4 5168 #define RTC_BKP0R ((uint32_t)0xFFFFFFFF)
mbed_official 403:91a4bea587f4 5169
mbed_official 403:91a4bea587f4 5170 /******************** Bits definition for RTC_BKP1R register ****************/
mbed_official 403:91a4bea587f4 5171 #define RTC_BKP1R ((uint32_t)0xFFFFFFFF)
mbed_official 403:91a4bea587f4 5172
mbed_official 403:91a4bea587f4 5173 /******************** Bits definition for RTC_BKP2R register ****************/
mbed_official 403:91a4bea587f4 5174 #define RTC_BKP2R ((uint32_t)0xFFFFFFFF)
mbed_official 403:91a4bea587f4 5175
mbed_official 403:91a4bea587f4 5176 /******************** Bits definition for RTC_BKP3R register ****************/
mbed_official 403:91a4bea587f4 5177 #define RTC_BKP3R ((uint32_t)0xFFFFFFFF)
mbed_official 403:91a4bea587f4 5178
mbed_official 403:91a4bea587f4 5179 /******************** Bits definition for RTC_BKP4R register ****************/
mbed_official 403:91a4bea587f4 5180 #define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
mbed_official 403:91a4bea587f4 5181
mbed_official 403:91a4bea587f4 5182 /******************** Bits definition for RTC_BKP5R register ****************/
mbed_official 403:91a4bea587f4 5183 #define RTC_BKP5R ((uint32_t)0xFFFFFFFF)
mbed_official 403:91a4bea587f4 5184
mbed_official 403:91a4bea587f4 5185 /******************** Bits definition for RTC_BKP6R register ****************/
mbed_official 403:91a4bea587f4 5186 #define RTC_BKP6R ((uint32_t)0xFFFFFFFF)
mbed_official 403:91a4bea587f4 5187
mbed_official 403:91a4bea587f4 5188 /******************** Bits definition for RTC_BKP7R register ****************/
mbed_official 403:91a4bea587f4 5189 #define RTC_BKP7R ((uint32_t)0xFFFFFFFF)
mbed_official 403:91a4bea587f4 5190
mbed_official 403:91a4bea587f4 5191 /******************** Bits definition for RTC_BKP8R register ****************/
mbed_official 403:91a4bea587f4 5192 #define RTC_BKP8R ((uint32_t)0xFFFFFFFF)
mbed_official 403:91a4bea587f4 5193
mbed_official 403:91a4bea587f4 5194 /******************** Bits definition for RTC_BKP9R register ****************/
mbed_official 403:91a4bea587f4 5195 #define RTC_BKP9R ((uint32_t)0xFFFFFFFF)
mbed_official 403:91a4bea587f4 5196
mbed_official 403:91a4bea587f4 5197 /******************** Bits definition for RTC_BKP10R register ***************/
mbed_official 403:91a4bea587f4 5198 #define RTC_BKP10R ((uint32_t)0xFFFFFFFF)
mbed_official 403:91a4bea587f4 5199
mbed_official 403:91a4bea587f4 5200 /******************** Bits definition for RTC_BKP11R register ***************/
mbed_official 403:91a4bea587f4 5201 #define RTC_BKP11R ((uint32_t)0xFFFFFFFF)
mbed_official 403:91a4bea587f4 5202
mbed_official 403:91a4bea587f4 5203 /******************** Bits definition for RTC_BKP12R register ***************/
mbed_official 403:91a4bea587f4 5204 #define RTC_BKP12R ((uint32_t)0xFFFFFFFF)
mbed_official 403:91a4bea587f4 5205
mbed_official 403:91a4bea587f4 5206 /******************** Bits definition for RTC_BKP13R register ***************/
mbed_official 403:91a4bea587f4 5207 #define RTC_BKP13R ((uint32_t)0xFFFFFFFF)
mbed_official 403:91a4bea587f4 5208
mbed_official 403:91a4bea587f4 5209 /******************** Bits definition for RTC_BKP14R register ***************/
mbed_official 403:91a4bea587f4 5210 #define RTC_BKP14R ((uint32_t)0xFFFFFFFF)
mbed_official 403:91a4bea587f4 5211
mbed_official 403:91a4bea587f4 5212 /******************** Bits definition for RTC_BKP15R register ***************/
mbed_official 403:91a4bea587f4 5213 #define RTC_BKP15R ((uint32_t)0xFFFFFFFF)
mbed_official 403:91a4bea587f4 5214
mbed_official 403:91a4bea587f4 5215 /******************** Number of backup registers ******************************/
mbed_official 403:91a4bea587f4 5216 #define RTC_BKP_NUMBER ((uint32_t)0x00000010)
mbed_official 403:91a4bea587f4 5217
mbed_official 403:91a4bea587f4 5218 /******************************************************************************/
mbed_official 403:91a4bea587f4 5219 /* */
mbed_official 403:91a4bea587f4 5220 /* Serial Peripheral Interface (SPI) */
mbed_official 403:91a4bea587f4 5221 /* */
mbed_official 403:91a4bea587f4 5222 /******************************************************************************/
mbed_official 403:91a4bea587f4 5223 /******************* Bit definition for SPI_CR1 register ********************/
mbed_official 403:91a4bea587f4 5224 #define SPI_CR1_CPHA ((uint32_t)0x00000001) /*!< Clock Phase */
mbed_official 403:91a4bea587f4 5225 #define SPI_CR1_CPOL ((uint32_t)0x00000002) /*!< Clock Polarity */
mbed_official 403:91a4bea587f4 5226 #define SPI_CR1_MSTR ((uint32_t)0x00000004) /*!< Master Selection */
mbed_official 403:91a4bea587f4 5227 #define SPI_CR1_BR ((uint32_t)0x00000038) /*!< BR[2:0] bits (Baud Rate Control) */
mbed_official 403:91a4bea587f4 5228 #define SPI_CR1_BR_0 ((uint32_t)0x00000008) /*!< Bit 0 */
mbed_official 403:91a4bea587f4 5229 #define SPI_CR1_BR_1 ((uint32_t)0x00000010) /*!< Bit 1 */
mbed_official 403:91a4bea587f4 5230 #define SPI_CR1_BR_2 ((uint32_t)0x00000020) /*!< Bit 2 */
mbed_official 403:91a4bea587f4 5231 #define SPI_CR1_SPE ((uint32_t)0x00000040) /*!< SPI Enable */
mbed_official 403:91a4bea587f4 5232 #define SPI_CR1_LSBFIRST ((uint32_t)0x00000080) /*!< Frame Format */
mbed_official 403:91a4bea587f4 5233 #define SPI_CR1_SSI ((uint32_t)0x00000100) /*!< Internal slave select */
mbed_official 403:91a4bea587f4 5234 #define SPI_CR1_SSM ((uint32_t)0x00000200) /*!< Software slave management */
mbed_official 403:91a4bea587f4 5235 #define SPI_CR1_RXONLY ((uint32_t)0x00000400) /*!< Receive only */
mbed_official 403:91a4bea587f4 5236 #define SPI_CR1_CRCL ((uint32_t)0x00000800) /*!< CRC Length */
mbed_official 403:91a4bea587f4 5237 #define SPI_CR1_CRCNEXT ((uint32_t)0x00001000) /*!< Transmit CRC next */
mbed_official 403:91a4bea587f4 5238 #define SPI_CR1_CRCEN ((uint32_t)0x00002000) /*!< Hardware CRC calculation enable */
mbed_official 403:91a4bea587f4 5239 #define SPI_CR1_BIDIOE ((uint32_t)0x00004000) /*!< Output enable in bidirectional mode */
mbed_official 403:91a4bea587f4 5240 #define SPI_CR1_BIDIMODE ((uint32_t)0x00008000) /*!< Bidirectional data mode enable */
mbed_official 403:91a4bea587f4 5241
mbed_official 403:91a4bea587f4 5242 /******************* Bit definition for SPI_CR2 register ********************/
mbed_official 403:91a4bea587f4 5243 #define SPI_CR2_RXDMAEN ((uint32_t)0x00000001) /*!< Rx Buffer DMA Enable */
mbed_official 403:91a4bea587f4 5244 #define SPI_CR2_TXDMAEN ((uint32_t)0x00000002) /*!< Tx Buffer DMA Enable */
mbed_official 403:91a4bea587f4 5245 #define SPI_CR2_SSOE ((uint32_t)0x00000004) /*!< SS Output Enable */
mbed_official 403:91a4bea587f4 5246 #define SPI_CR2_NSSP ((uint32_t)0x00000008) /*!< NSS pulse management Enable */
mbed_official 403:91a4bea587f4 5247 #define SPI_CR2_FRF ((uint32_t)0x00000010) /*!< Frame Format Enable */
mbed_official 403:91a4bea587f4 5248 #define SPI_CR2_ERRIE ((uint32_t)0x00000020) /*!< Error Interrupt Enable */
mbed_official 403:91a4bea587f4 5249 #define SPI_CR2_RXNEIE ((uint32_t)0x00000040) /*!< RX buffer Not Empty Interrupt Enable */
mbed_official 403:91a4bea587f4 5250 #define SPI_CR2_TXEIE ((uint32_t)0x00000080) /*!< Tx buffer Empty Interrupt Enable */
mbed_official 403:91a4bea587f4 5251 #define SPI_CR2_DS ((uint32_t)0x00000F00) /*!< DS[3:0] Data Size */
mbed_official 403:91a4bea587f4 5252 #define SPI_CR2_DS_0 ((uint32_t)0x00000100) /*!< Bit 0 */
mbed_official 403:91a4bea587f4 5253 #define SPI_CR2_DS_1 ((uint32_t)0x00000200) /*!< Bit 1 */
mbed_official 403:91a4bea587f4 5254 #define SPI_CR2_DS_2 ((uint32_t)0x00000400) /*!< Bit 2 */
mbed_official 403:91a4bea587f4 5255 #define SPI_CR2_DS_3 ((uint32_t)0x00000800) /*!< Bit 3 */
mbed_official 403:91a4bea587f4 5256 #define SPI_CR2_FRXTH ((uint32_t)0x00001000) /*!< FIFO reception Threshold */
mbed_official 403:91a4bea587f4 5257 #define SPI_CR2_LDMARX ((uint32_t)0x00002000) /*!< Last DMA transfer for reception */
mbed_official 403:91a4bea587f4 5258 #define SPI_CR2_LDMATX ((uint32_t)0x00004000) /*!< Last DMA transfer for transmission */
mbed_official 403:91a4bea587f4 5259
mbed_official 403:91a4bea587f4 5260 /******************** Bit definition for SPI_SR register ********************/
mbed_official 403:91a4bea587f4 5261 #define SPI_SR_RXNE ((uint32_t)0x00000001) /*!< Receive buffer Not Empty */
mbed_official 403:91a4bea587f4 5262 #define SPI_SR_TXE ((uint32_t)0x00000002) /*!< Transmit buffer Empty */
mbed_official 403:91a4bea587f4 5263 #define SPI_SR_CHSIDE ((uint32_t)0x00000004) /*!< Channel side */
mbed_official 403:91a4bea587f4 5264 #define SPI_SR_UDR ((uint32_t)0x00000008) /*!< Underrun flag */
mbed_official 403:91a4bea587f4 5265 #define SPI_SR_CRCERR ((uint32_t)0x00000010) /*!< CRC Error flag */
mbed_official 403:91a4bea587f4 5266 #define SPI_SR_MODF ((uint32_t)0x00000020) /*!< Mode fault */
mbed_official 403:91a4bea587f4 5267 #define SPI_SR_OVR ((uint32_t)0x00000040) /*!< Overrun flag */
mbed_official 403:91a4bea587f4 5268 #define SPI_SR_BSY ((uint32_t)0x00000080) /*!< Busy flag */
mbed_official 403:91a4bea587f4 5269 #define SPI_SR_FRE ((uint32_t)0x00000100) /*!< TI frame format error */
mbed_official 403:91a4bea587f4 5270 #define SPI_SR_FRLVL ((uint32_t)0x00000600) /*!< FIFO Reception Level */
mbed_official 403:91a4bea587f4 5271 #define SPI_SR_FRLVL_0 ((uint32_t)0x00000200) /*!< Bit 0 */
mbed_official 403:91a4bea587f4 5272 #define SPI_SR_FRLVL_1 ((uint32_t)0x00000400) /*!< Bit 1 */
mbed_official 403:91a4bea587f4 5273 #define SPI_SR_FTLVL ((uint32_t)0x00001800) /*!< FIFO Transmission Level */
mbed_official 403:91a4bea587f4 5274 #define SPI_SR_FTLVL_0 ((uint32_t)0x00000800) /*!< Bit 0 */
mbed_official 403:91a4bea587f4 5275 #define SPI_SR_FTLVL_1 ((uint32_t)0x00001000) /*!< Bit 1 */
mbed_official 403:91a4bea587f4 5276
mbed_official 403:91a4bea587f4 5277 /******************** Bit definition for SPI_DR register ********************/
mbed_official 403:91a4bea587f4 5278 #define SPI_DR_DR ((uint32_t)0x0000FFFF) /*!< Data Register */
mbed_official 403:91a4bea587f4 5279
mbed_official 403:91a4bea587f4 5280 /******************* Bit definition for SPI_CRCPR register ******************/
mbed_official 403:91a4bea587f4 5281 #define SPI_CRCPR_CRCPOLY ((uint32_t)0x0000FFFF) /*!< CRC polynomial register */
mbed_official 403:91a4bea587f4 5282
mbed_official 403:91a4bea587f4 5283 /****************** Bit definition for SPI_RXCRCR register ******************/
mbed_official 403:91a4bea587f4 5284 #define SPI_RXCRCR_RXCRC ((uint32_t)0x0000FFFF) /*!< Rx CRC Register */
mbed_official 403:91a4bea587f4 5285
mbed_official 403:91a4bea587f4 5286 /****************** Bit definition for SPI_TXCRCR register ******************/
mbed_official 403:91a4bea587f4 5287 #define SPI_TXCRCR_TXCRC ((uint32_t)0x0000FFFF) /*!< Tx CRC Register */
mbed_official 403:91a4bea587f4 5288
mbed_official 403:91a4bea587f4 5289 /****************** Bit definition for SPI_I2SCFGR register *****************/
mbed_official 403:91a4bea587f4 5290 #define SPI_I2SCFGR_CHLEN ((uint32_t)0x00000001) /*!<Channel length (number of bits per audio channel) */
mbed_official 403:91a4bea587f4 5291 #define SPI_I2SCFGR_DATLEN ((uint32_t)0x00000006) /*!<DATLEN[1:0] bits (Data length to be transferred) */
mbed_official 403:91a4bea587f4 5292 #define SPI_I2SCFGR_DATLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */
mbed_official 403:91a4bea587f4 5293 #define SPI_I2SCFGR_DATLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */
mbed_official 403:91a4bea587f4 5294 #define SPI_I2SCFGR_CKPOL ((uint32_t)0x00000008) /*!<steady state clock polarity */
mbed_official 403:91a4bea587f4 5295 #define SPI_I2SCFGR_I2SSTD ((uint32_t)0x00000030) /*!<I2SSTD[1:0] bits (I2S standard selection) */
mbed_official 403:91a4bea587f4 5296 #define SPI_I2SCFGR_I2SSTD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 403:91a4bea587f4 5297 #define SPI_I2SCFGR_I2SSTD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 403:91a4bea587f4 5298 #define SPI_I2SCFGR_PCMSYNC ((uint32_t)0x00000080) /*!<PCM frame synchronization */
mbed_official 403:91a4bea587f4 5299 #define SPI_I2SCFGR_I2SCFG ((uint32_t)0x00000300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */
mbed_official 403:91a4bea587f4 5300 #define SPI_I2SCFGR_I2SCFG_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 403:91a4bea587f4 5301 #define SPI_I2SCFGR_I2SCFG_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 403:91a4bea587f4 5302 #define SPI_I2SCFGR_I2SE ((uint32_t)0x00000400) /*!<I2S Enable */
mbed_official 403:91a4bea587f4 5303 #define SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) /*!<I2S mode selection */
mbed_official 403:91a4bea587f4 5304
mbed_official 403:91a4bea587f4 5305 /****************** Bit definition for SPI_I2SPR register *******************/
mbed_official 403:91a4bea587f4 5306 #define SPI_I2SPR_I2SDIV ((uint32_t)0x000000FF) /*!<I2S Linear prescaler */
mbed_official 403:91a4bea587f4 5307 #define SPI_I2SPR_ODD ((uint32_t)0x00000100) /*!<Odd factor for the prescaler */
mbed_official 403:91a4bea587f4 5308 #define SPI_I2SPR_MCKOE ((uint32_t)0x00000200) /*!<Master Clock Output Enable */
mbed_official 403:91a4bea587f4 5309
mbed_official 403:91a4bea587f4 5310 /******************************************************************************/
mbed_official 403:91a4bea587f4 5311 /* */
mbed_official 403:91a4bea587f4 5312 /* System Configuration(SYSCFG) */
mbed_official 403:91a4bea587f4 5313 /* */
mbed_official 403:91a4bea587f4 5314 /******************************************************************************/
mbed_official 403:91a4bea587f4 5315 /***************** Bit definition for SYSCFG_CFGR1 register *****************/
mbed_official 403:91a4bea587f4 5316 #define SYSCFG_CFGR1_MEM_MODE ((uint32_t)0x00000003) /*!< SYSCFG_Memory Remap Config */
mbed_official 403:91a4bea587f4 5317 #define SYSCFG_CFGR1_MEM_MODE_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 403:91a4bea587f4 5318 #define SYSCFG_CFGR1_MEM_MODE_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 403:91a4bea587f4 5319 #define SYSCFG_CFGR1_USB_IT_RMP ((uint32_t)0x00000020) /*!< USB interrupt remap */
mbed_official 403:91a4bea587f4 5320 #define SYSCFG_CFGR1_TIM1_ITR3_RMP ((uint32_t)0x00000040) /*!< Timer 1 ITR3 selection */
mbed_official 403:91a4bea587f4 5321 #define SYSCFG_CFGR1_DAC1_TRIG1_RMP ((uint32_t)0x00000080) /*!< DAC1 Trigger1 remap */
mbed_official 403:91a4bea587f4 5322 #define SYSCFG_CFGR1_DMA_RMP ((uint32_t)0x00007900) /*!< DMA remap mask */
mbed_official 403:91a4bea587f4 5323 #define SYSCFG_CFGR1_ADC24_DMA_RMP ((uint32_t)0x00000100) /*!< ADC2 and ADC4 DMA remap */
mbed_official 403:91a4bea587f4 5324 #define SYSCFG_CFGR1_TIM16_DMA_RMP ((uint32_t)0x00000800) /*!< Timer 16 DMA remap */
mbed_official 403:91a4bea587f4 5325 #define SYSCFG_CFGR1_TIM17_DMA_RMP ((uint32_t)0x00001000) /*!< Timer 17 DMA remap */
mbed_official 403:91a4bea587f4 5326 #define SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP ((uint32_t)0x00002000) /*!< Timer 6 / DAC1 CH1 DMA remap */
mbed_official 403:91a4bea587f4 5327 #define SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP ((uint32_t)0x00004000) /*!< Timer 7 / DAC1 CH2 DMA remap */
mbed_official 403:91a4bea587f4 5328 #define SYSCFG_CFGR1_I2C_PB6_FMP ((uint32_t)0x00010000) /*!< I2C PB6 Fast mode plus */
mbed_official 403:91a4bea587f4 5329 #define SYSCFG_CFGR1_I2C_PB7_FMP ((uint32_t)0x00020000) /*!< I2C PB7 Fast mode plus */
mbed_official 403:91a4bea587f4 5330 #define SYSCFG_CFGR1_I2C_PB8_FMP ((uint32_t)0x00040000) /*!< I2C PB8 Fast mode plus */
mbed_official 403:91a4bea587f4 5331 #define SYSCFG_CFGR1_I2C_PB9_FMP ((uint32_t)0x00080000) /*!< I2C PB9 Fast mode plus */
mbed_official 403:91a4bea587f4 5332 #define SYSCFG_CFGR1_I2C1_FMP ((uint32_t)0x00100000) /*!< I2C1 Fast mode plus */
mbed_official 403:91a4bea587f4 5333 #define SYSCFG_CFGR1_I2C2_FMP ((uint32_t)0x00200000) /*!< I2C2 Fast mode plus */
mbed_official 403:91a4bea587f4 5334 #define SYSCFG_CFGR1_ENCODER_MODE ((uint32_t)0x00C00000) /*!< Encoder Mode */
mbed_official 403:91a4bea587f4 5335 #define SYSCFG_CFGR1_ENCODER_MODE_0 ((uint32_t)0x00400000) /*!< Encoder Mode 0 */
mbed_official 403:91a4bea587f4 5336 #define SYSCFG_CFGR1_ENCODER_MODE_1 ((uint32_t)0x00800000) /*!< Encoder Mode 1 */
mbed_official 403:91a4bea587f4 5337 #define SYSCFG_CFGR1_FPU_IE ((uint32_t)0xFC000000) /*!< Floating Point Unit Interrupt Enable */
mbed_official 403:91a4bea587f4 5338 #define SYSCFG_CFGR1_FPU_IE_0 ((uint32_t)0x04000000) /*!< Floating Point Unit Interrupt Enable 0 */
mbed_official 403:91a4bea587f4 5339 #define SYSCFG_CFGR1_FPU_IE_1 ((uint32_t)0x08000000) /*!< Floating Point Unit Interrupt Enable 1 */
mbed_official 403:91a4bea587f4 5340 #define SYSCFG_CFGR1_FPU_IE_2 ((uint32_t)0x10000000) /*!< Floating Point Unit Interrupt Enable 2 */
mbed_official 403:91a4bea587f4 5341 #define SYSCFG_CFGR1_FPU_IE_3 ((uint32_t)0x20000000) /*!< Floating Point Unit Interrupt Enable 3 */
mbed_official 403:91a4bea587f4 5342 #define SYSCFG_CFGR1_FPU_IE_4 ((uint32_t)0x40000000) /*!< Floating Point Unit Interrupt Enable 4 */
mbed_official 403:91a4bea587f4 5343 #define SYSCFG_CFGR1_FPU_IE_5 ((uint32_t)0x80000000) /*!< Floating Point Unit Interrupt Enable 5 */
mbed_official 403:91a4bea587f4 5344
mbed_official 403:91a4bea587f4 5345 /***************** Bit definition for SYSCFG_RCR register *******************/
mbed_official 403:91a4bea587f4 5346 #define SYSCFG_RCR_PAGE0 ((uint32_t)0x00000001) /*!< ICODE SRAM Write protection page 0 */
mbed_official 403:91a4bea587f4 5347 #define SYSCFG_RCR_PAGE1 ((uint32_t)0x00000002) /*!< ICODE SRAM Write protection page 1 */
mbed_official 403:91a4bea587f4 5348 #define SYSCFG_RCR_PAGE2 ((uint32_t)0x00000004) /*!< ICODE SRAM Write protection page 2 */
mbed_official 403:91a4bea587f4 5349 #define SYSCFG_RCR_PAGE3 ((uint32_t)0x00000008) /*!< ICODE SRAM Write protection page 3 */
mbed_official 403:91a4bea587f4 5350 #define SYSCFG_RCR_PAGE4 ((uint32_t)0x00000010) /*!< ICODE SRAM Write protection page 4 */
mbed_official 403:91a4bea587f4 5351 #define SYSCFG_RCR_PAGE5 ((uint32_t)0x00000020) /*!< ICODE SRAM Write protection page 5 */
mbed_official 403:91a4bea587f4 5352 #define SYSCFG_RCR_PAGE6 ((uint32_t)0x00000040) /*!< ICODE SRAM Write protection page 6 */
mbed_official 403:91a4bea587f4 5353 #define SYSCFG_RCR_PAGE7 ((uint32_t)0x00000080) /*!< ICODE SRAM Write protection page 7 */
mbed_official 403:91a4bea587f4 5354
mbed_official 403:91a4bea587f4 5355 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
mbed_official 403:91a4bea587f4 5356 #define SYSCFG_EXTICR1_EXTI0 ((uint32_t)0x0000000F) /*!< EXTI 0 configuration */
mbed_official 403:91a4bea587f4 5357 #define SYSCFG_EXTICR1_EXTI1 ((uint32_t)0x000000F0) /*!< EXTI 1 configuration */
mbed_official 403:91a4bea587f4 5358 #define SYSCFG_EXTICR1_EXTI2 ((uint32_t)0x00000F00) /*!< EXTI 2 configuration */
mbed_official 403:91a4bea587f4 5359 #define SYSCFG_EXTICR1_EXTI3 ((uint32_t)0x0000F000) /*!< EXTI 3 configuration */
mbed_official 403:91a4bea587f4 5360
mbed_official 403:91a4bea587f4 5361 /*!<*
mbed_official 403:91a4bea587f4 5362 * @brief EXTI0 configuration
mbed_official 403:91a4bea587f4 5363 */
mbed_official 403:91a4bea587f4 5364 #define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!< PA[0] pin */
mbed_official 403:91a4bea587f4 5365 #define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /*!< PB[0] pin */
mbed_official 403:91a4bea587f4 5366 #define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /*!< PC[0] pin */
mbed_official 403:91a4bea587f4 5367 #define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /*!< PD[0] pin */
mbed_official 403:91a4bea587f4 5368 #define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) /*!< PE[0] pin */
mbed_official 403:91a4bea587f4 5369 #define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) /*!< PF[0] pin */
mbed_official 403:91a4bea587f4 5370
mbed_official 403:91a4bea587f4 5371 /*!<*
mbed_official 403:91a4bea587f4 5372 * @brief EXTI1 configuration
mbed_official 403:91a4bea587f4 5373 */
mbed_official 403:91a4bea587f4 5374 #define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!< PA[1] pin */
mbed_official 403:91a4bea587f4 5375 #define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /*!< PB[1] pin */
mbed_official 403:91a4bea587f4 5376 #define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /*!< PC[1] pin */
mbed_official 403:91a4bea587f4 5377 #define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /*!< PD[1] pin */
mbed_official 403:91a4bea587f4 5378 #define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) /*!< PE[1] pin */
mbed_official 403:91a4bea587f4 5379 #define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) /*!< PF[1] pin */
mbed_official 403:91a4bea587f4 5380
mbed_official 403:91a4bea587f4 5381 /*!<*
mbed_official 403:91a4bea587f4 5382 * @brief EXTI2 configuration
mbed_official 403:91a4bea587f4 5383 */
mbed_official 403:91a4bea587f4 5384 #define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!< PA[2] pin */
mbed_official 403:91a4bea587f4 5385 #define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /*!< PB[2] pin */
mbed_official 403:91a4bea587f4 5386 #define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /*!< PC[2] pin */
mbed_official 403:91a4bea587f4 5387 #define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /*!< PD[2] pin */
mbed_official 403:91a4bea587f4 5388 #define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) /*!< PE[2] pin */
mbed_official 403:91a4bea587f4 5389 #define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) /*!< PF[2] pin */
mbed_official 403:91a4bea587f4 5390
mbed_official 403:91a4bea587f4 5391 /*!<*
mbed_official 403:91a4bea587f4 5392 * @brief EXTI3 configuration
mbed_official 403:91a4bea587f4 5393 */
mbed_official 403:91a4bea587f4 5394 #define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!< PA[3] pin */
mbed_official 403:91a4bea587f4 5395 #define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /*!< PB[3] pin */
mbed_official 403:91a4bea587f4 5396 #define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /*!< PC[3] pin */
mbed_official 403:91a4bea587f4 5397 #define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /*!< PD[3] pin */
mbed_official 403:91a4bea587f4 5398 #define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) /*!< PE[3] pin */
mbed_official 403:91a4bea587f4 5399
mbed_official 403:91a4bea587f4 5400 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
mbed_official 403:91a4bea587f4 5401 #define SYSCFG_EXTICR2_EXTI4 ((uint32_t)0x0000000F) /*!< EXTI 4 configuration */
mbed_official 403:91a4bea587f4 5402 #define SYSCFG_EXTICR2_EXTI5 ((uint32_t)0x000000F0) /*!< EXTI 5 configuration */
mbed_official 403:91a4bea587f4 5403 #define SYSCFG_EXTICR2_EXTI6 ((uint32_t)0x00000F00) /*!< EXTI 6 configuration */
mbed_official 403:91a4bea587f4 5404 #define SYSCFG_EXTICR2_EXTI7 ((uint32_t)0x0000F000) /*!< EXTI 7 configuration */
mbed_official 403:91a4bea587f4 5405
mbed_official 403:91a4bea587f4 5406 /*!<*
mbed_official 403:91a4bea587f4 5407 * @brief EXTI4 configuration
mbed_official 403:91a4bea587f4 5408 */
mbed_official 403:91a4bea587f4 5409 #define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!< PA[4] pin */
mbed_official 403:91a4bea587f4 5410 #define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /*!< PB[4] pin */
mbed_official 403:91a4bea587f4 5411 #define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /*!< PC[4] pin */
mbed_official 403:91a4bea587f4 5412 #define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /*!< PD[4] pin */
mbed_official 403:91a4bea587f4 5413 #define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) /*!< PE[4] pin */
mbed_official 403:91a4bea587f4 5414 #define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) /*!< PF[4] pin */
mbed_official 403:91a4bea587f4 5415
mbed_official 403:91a4bea587f4 5416 /*!<*
mbed_official 403:91a4bea587f4 5417 * @brief EXTI5 configuration
mbed_official 403:91a4bea587f4 5418 */
mbed_official 403:91a4bea587f4 5419 #define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!< PA[5] pin */
mbed_official 403:91a4bea587f4 5420 #define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /*!< PB[5] pin */
mbed_official 403:91a4bea587f4 5421 #define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /*!< PC[5] pin */
mbed_official 403:91a4bea587f4 5422 #define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /*!< PD[5] pin */
mbed_official 403:91a4bea587f4 5423 #define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) /*!< PE[5] pin */
mbed_official 403:91a4bea587f4 5424 #define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) /*!< PF[5] pin */
mbed_official 403:91a4bea587f4 5425
mbed_official 403:91a4bea587f4 5426 /*!<*
mbed_official 403:91a4bea587f4 5427 * @brief EXTI6 configuration
mbed_official 403:91a4bea587f4 5428 */
mbed_official 403:91a4bea587f4 5429 #define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!< PA[6] pin */
mbed_official 403:91a4bea587f4 5430 #define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /*!< PB[6] pin */
mbed_official 403:91a4bea587f4 5431 #define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /*!< PC[6] pin */
mbed_official 403:91a4bea587f4 5432 #define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /*!< PD[6] pin */
mbed_official 403:91a4bea587f4 5433 #define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) /*!< PE[6] pin */
mbed_official 403:91a4bea587f4 5434 #define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) /*!< PF[6] pin */
mbed_official 403:91a4bea587f4 5435
mbed_official 403:91a4bea587f4 5436 /*!<*
mbed_official 403:91a4bea587f4 5437 * @brief EXTI7 configuration
mbed_official 403:91a4bea587f4 5438 */
mbed_official 403:91a4bea587f4 5439 #define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!< PA[7] pin */
mbed_official 403:91a4bea587f4 5440 #define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /*!< PB[7] pin */
mbed_official 403:91a4bea587f4 5441 #define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /*!< PC[7] pin */
mbed_official 403:91a4bea587f4 5442 #define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /*!< PD[7] pin */
mbed_official 403:91a4bea587f4 5443 #define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) /*!< PE[7] pin */
mbed_official 403:91a4bea587f4 5444
mbed_official 403:91a4bea587f4 5445 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
mbed_official 403:91a4bea587f4 5446 #define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x0000000F) /*!< EXTI 8 configuration */
mbed_official 403:91a4bea587f4 5447 #define SYSCFG_EXTICR3_EXTI9 ((uint32_t)0x000000F0) /*!< EXTI 9 configuration */
mbed_official 403:91a4bea587f4 5448 #define SYSCFG_EXTICR3_EXTI10 ((uint32_t)0x00000F00) /*!< EXTI 10 configuration */
mbed_official 403:91a4bea587f4 5449 #define SYSCFG_EXTICR3_EXTI11 ((uint32_t)0x0000F000) /*!< EXTI 11 configuration */
mbed_official 403:91a4bea587f4 5450
mbed_official 403:91a4bea587f4 5451 /*!<*
mbed_official 403:91a4bea587f4 5452 * @brief EXTI8 configuration
mbed_official 403:91a4bea587f4 5453 */
mbed_official 403:91a4bea587f4 5454 #define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!< PA[8] pin */
mbed_official 403:91a4bea587f4 5455 #define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /*!< PB[8] pin */
mbed_official 403:91a4bea587f4 5456 #define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /*!< PC[8] pin */
mbed_official 403:91a4bea587f4 5457 #define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /*!< PD[8] pin */
mbed_official 403:91a4bea587f4 5458 #define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) /*!< PE[8] pin */
mbed_official 403:91a4bea587f4 5459
mbed_official 403:91a4bea587f4 5460 /*!<*
mbed_official 403:91a4bea587f4 5461 * @brief EXTI9 configuration
mbed_official 403:91a4bea587f4 5462 */
mbed_official 403:91a4bea587f4 5463 #define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!< PA[9] pin */
mbed_official 403:91a4bea587f4 5464 #define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /*!< PB[9] pin */
mbed_official 403:91a4bea587f4 5465 #define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /*!< PC[9] pin */
mbed_official 403:91a4bea587f4 5466 #define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /*!< PD[9] pin */
mbed_official 403:91a4bea587f4 5467 #define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) /*!< PE[9] pin */
mbed_official 403:91a4bea587f4 5468 #define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) /*!< PF[9] pin */
mbed_official 403:91a4bea587f4 5469
mbed_official 403:91a4bea587f4 5470 /*!<*
mbed_official 403:91a4bea587f4 5471 * @brief EXTI10 configuration
mbed_official 403:91a4bea587f4 5472 */
mbed_official 403:91a4bea587f4 5473 #define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!< PA[10] pin */
mbed_official 403:91a4bea587f4 5474 #define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /*!< PB[10] pin */
mbed_official 403:91a4bea587f4 5475 #define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /*!< PC[10] pin */
mbed_official 403:91a4bea587f4 5476 #define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /*!< PD[10] pin */
mbed_official 403:91a4bea587f4 5477 #define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) /*!< PE[10] pin */
mbed_official 403:91a4bea587f4 5478 #define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) /*!< PF[10] pin */
mbed_official 403:91a4bea587f4 5479
mbed_official 403:91a4bea587f4 5480 /*!<*
mbed_official 403:91a4bea587f4 5481 * @brief EXTI11 configuration
mbed_official 403:91a4bea587f4 5482 */
mbed_official 403:91a4bea587f4 5483 #define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!< PA[11] pin */
mbed_official 403:91a4bea587f4 5484 #define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /*!< PB[11] pin */
mbed_official 403:91a4bea587f4 5485 #define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /*!< PC[11] pin */
mbed_official 403:91a4bea587f4 5486 #define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /*!< PD[11] pin */
mbed_official 403:91a4bea587f4 5487 #define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) /*!< PE[11] pin */
mbed_official 403:91a4bea587f4 5488
mbed_official 403:91a4bea587f4 5489 /***************** Bit definition for SYSCFG_EXTICR4 register *****************/
mbed_official 403:91a4bea587f4 5490 #define SYSCFG_EXTICR4_EXTI12 ((uint32_t)0x0000000F) /*!< EXTI 12 configuration */
mbed_official 403:91a4bea587f4 5491 #define SYSCFG_EXTICR4_EXTI13 ((uint32_t)0x000000F0) /*!< EXTI 13 configuration */
mbed_official 403:91a4bea587f4 5492 #define SYSCFG_EXTICR4_EXTI14 ((uint32_t)0x00000F00) /*!< EXTI 14 configuration */
mbed_official 403:91a4bea587f4 5493 #define SYSCFG_EXTICR4_EXTI15 ((uint32_t)0x0000F000) /*!< EXTI 15 configuration */
mbed_official 403:91a4bea587f4 5494
mbed_official 403:91a4bea587f4 5495 /*!<*
mbed_official 403:91a4bea587f4 5496 * @brief EXTI12 configuration
mbed_official 403:91a4bea587f4 5497 */
mbed_official 403:91a4bea587f4 5498 #define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!< PA[12] pin */
mbed_official 403:91a4bea587f4 5499 #define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /*!< PB[12] pin */
mbed_official 403:91a4bea587f4 5500 #define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /*!< PC[12] pin */
mbed_official 403:91a4bea587f4 5501 #define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /*!< PD[12] pin */
mbed_official 403:91a4bea587f4 5502 #define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) /*!< PE[12] pin */
mbed_official 403:91a4bea587f4 5503
mbed_official 403:91a4bea587f4 5504 /*!<*
mbed_official 403:91a4bea587f4 5505 * @brief EXTI13 configuration
mbed_official 403:91a4bea587f4 5506 */
mbed_official 403:91a4bea587f4 5507 #define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!< PA[13] pin */
mbed_official 403:91a4bea587f4 5508 #define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /*!< PB[13] pin */
mbed_official 403:91a4bea587f4 5509 #define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /*!< PC[13] pin */
mbed_official 403:91a4bea587f4 5510 #define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /*!< PD[13] pin */
mbed_official 403:91a4bea587f4 5511 #define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) /*!< PE[13] pin */
mbed_official 403:91a4bea587f4 5512
mbed_official 403:91a4bea587f4 5513 /*!<*
mbed_official 403:91a4bea587f4 5514 * @brief EXTI14 configuration
mbed_official 403:91a4bea587f4 5515 */
mbed_official 403:91a4bea587f4 5516 #define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!< PA[14] pin */
mbed_official 403:91a4bea587f4 5517 #define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /*!< PB[14] pin */
mbed_official 403:91a4bea587f4 5518 #define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /*!< PC[14] pin */
mbed_official 403:91a4bea587f4 5519 #define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /*!< PD[14] pin */
mbed_official 403:91a4bea587f4 5520 #define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) /*!< PE[14] pin */
mbed_official 403:91a4bea587f4 5521
mbed_official 403:91a4bea587f4 5522 /*!<*
mbed_official 403:91a4bea587f4 5523 * @brief EXTI15 configuration
mbed_official 403:91a4bea587f4 5524 */
mbed_official 403:91a4bea587f4 5525 #define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!< PA[15] pin */
mbed_official 403:91a4bea587f4 5526 #define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /*!< PB[15] pin */
mbed_official 403:91a4bea587f4 5527 #define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /*!< PC[15] pin */
mbed_official 403:91a4bea587f4 5528 #define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!< PD[15] pin */
mbed_official 403:91a4bea587f4 5529 #define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /*!< PE[15] pin */
mbed_official 403:91a4bea587f4 5530
mbed_official 403:91a4bea587f4 5531 /***************** Bit definition for SYSCFG_CFGR2 register *****************/
mbed_official 403:91a4bea587f4 5532 #define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM4 with Break Input of TIM1/8/15/16/17 */
mbed_official 403:91a4bea587f4 5533 #define SYSCFG_CFGR2_SRAM_PARITY_LOCK ((uint32_t)0x00000002) /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIM1/8/15/16/17 */
mbed_official 403:91a4bea587f4 5534 #define SYSCFG_CFGR2_PVD_LOCK ((uint32_t)0x00000004) /*!< Enables and locks the PVD connection with TIM1/8/15/16/17 Break Input, as well as the PVDE and PLS[2:0] in the PWR_CR register */
mbed_official 403:91a4bea587f4 5535 #define SYSCFG_CFGR2_BYP_ADDR_PAR ((uint32_t)0x00000010) /*!< Disables the adddress parity check on RAM */
mbed_official 403:91a4bea587f4 5536 #define SYSCFG_CFGR2_SRAM_PE ((uint32_t)0x00000100) /*!< SRAM Parity error flag */
mbed_official 403:91a4bea587f4 5537
mbed_official 403:91a4bea587f4 5538 /******************************************************************************/
mbed_official 403:91a4bea587f4 5539 /* */
mbed_official 403:91a4bea587f4 5540 /* TIM */
mbed_official 403:91a4bea587f4 5541 /* */
mbed_official 403:91a4bea587f4 5542 /******************************************************************************/
mbed_official 403:91a4bea587f4 5543 /******************* Bit definition for TIM_CR1 register ********************/
mbed_official 403:91a4bea587f4 5544 #define TIM_CR1_CEN ((uint32_t)0x00000001) /*!<Counter enable */
mbed_official 403:91a4bea587f4 5545 #define TIM_CR1_UDIS ((uint32_t)0x00000002) /*!<Update disable */
mbed_official 403:91a4bea587f4 5546 #define TIM_CR1_URS ((uint32_t)0x00000004) /*!<Update request source */
mbed_official 403:91a4bea587f4 5547 #define TIM_CR1_OPM ((uint32_t)0x00000008) /*!<One pulse mode */
mbed_official 403:91a4bea587f4 5548 #define TIM_CR1_DIR ((uint32_t)0x00000010) /*!<Direction */
mbed_official 403:91a4bea587f4 5549
mbed_official 403:91a4bea587f4 5550 #define TIM_CR1_CMS ((uint32_t)0x00000060) /*!<CMS[1:0] bits (Center-aligned mode selection) */
mbed_official 403:91a4bea587f4 5551 #define TIM_CR1_CMS_0 ((uint32_t)0x00000020) /*!<Bit 0 */
mbed_official 403:91a4bea587f4 5552 #define TIM_CR1_CMS_1 ((uint32_t)0x00000040) /*!<Bit 1 */
mbed_official 403:91a4bea587f4 5553
mbed_official 403:91a4bea587f4 5554 #define TIM_CR1_ARPE ((uint32_t)0x00000080) /*!<Auto-reload preload enable */
mbed_official 403:91a4bea587f4 5555
mbed_official 403:91a4bea587f4 5556 #define TIM_CR1_CKD ((uint32_t)0x00000300) /*!<CKD[1:0] bits (clock division) */
mbed_official 403:91a4bea587f4 5557 #define TIM_CR1_CKD_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 403:91a4bea587f4 5558 #define TIM_CR1_CKD_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 403:91a4bea587f4 5559
mbed_official 403:91a4bea587f4 5560 #define TIM_CR1_UIFREMAP ((uint32_t)0x00000800) /*!<Update interrupt flag remap */
mbed_official 403:91a4bea587f4 5561
mbed_official 403:91a4bea587f4 5562 /******************* Bit definition for TIM_CR2 register ********************/
mbed_official 403:91a4bea587f4 5563 #define TIM_CR2_CCPC ((uint32_t)0x00000001) /*!<Capture/Compare Preloaded Control */
mbed_official 403:91a4bea587f4 5564 #define TIM_CR2_CCUS ((uint32_t)0x00000004) /*!<Capture/Compare Control Update Selection */
mbed_official 403:91a4bea587f4 5565 #define TIM_CR2_CCDS ((uint32_t)0x00000008) /*!<Capture/Compare DMA Selection */
mbed_official 403:91a4bea587f4 5566
mbed_official 403:91a4bea587f4 5567 #define TIM_CR2_MMS ((uint32_t)0x00000070) /*!<MMS[2:0] bits (Master Mode Selection) */
mbed_official 403:91a4bea587f4 5568 #define TIM_CR2_MMS_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 403:91a4bea587f4 5569 #define TIM_CR2_MMS_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 403:91a4bea587f4 5570 #define TIM_CR2_MMS_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 403:91a4bea587f4 5571
mbed_official 403:91a4bea587f4 5572 #define TIM_CR2_TI1S ((uint32_t)0x00000080) /*!<TI1 Selection */
mbed_official 403:91a4bea587f4 5573 #define TIM_CR2_OIS1 ((uint32_t)0x00000100) /*!<Output Idle state 1 (OC1 output) */
mbed_official 403:91a4bea587f4 5574 #define TIM_CR2_OIS1N ((uint32_t)0x00000200) /*!<Output Idle state 1 (OC1N output) */
mbed_official 403:91a4bea587f4 5575 #define TIM_CR2_OIS2 ((uint32_t)0x00000400) /*!<Output Idle state 2 (OC2 output) */
mbed_official 403:91a4bea587f4 5576 #define TIM_CR2_OIS2N ((uint32_t)0x00000800) /*!<Output Idle state 2 (OC2N output) */
mbed_official 403:91a4bea587f4 5577 #define TIM_CR2_OIS3 ((uint32_t)0x00001000) /*!<Output Idle state 3 (OC3 output) */
mbed_official 403:91a4bea587f4 5578 #define TIM_CR2_OIS3N ((uint32_t)0x00002000) /*!<Output Idle state 3 (OC3N output) */
mbed_official 403:91a4bea587f4 5579 #define TIM_CR2_OIS4 ((uint32_t)0x00004000) /*!<Output Idle state 4 (OC4 output) */
mbed_official 403:91a4bea587f4 5580 #define TIM_CR2_OIS5 ((uint32_t)0x00010000) /*!<Output Idle state 4 (OC4 output) */
mbed_official 403:91a4bea587f4 5581 #define TIM_CR2_OIS6 ((uint32_t)0x00040000) /*!<Output Idle state 4 (OC4 output) */
mbed_official 403:91a4bea587f4 5582
mbed_official 403:91a4bea587f4 5583 #define TIM_CR2_MMS2 ((uint32_t)0x00F00000) /*!<MMS[2:0] bits (Master Mode Selection) */
mbed_official 403:91a4bea587f4 5584 #define TIM_CR2_MMS2_0 ((uint32_t)0x00100000) /*!<Bit 0 */
mbed_official 403:91a4bea587f4 5585 #define TIM_CR2_MMS2_1 ((uint32_t)0x00200000) /*!<Bit 1 */
mbed_official 403:91a4bea587f4 5586 #define TIM_CR2_MMS2_2 ((uint32_t)0x00400000) /*!<Bit 2 */
mbed_official 403:91a4bea587f4 5587 #define TIM_CR2_MMS2_3 ((uint32_t)0x00800000) /*!<Bit 2 */
mbed_official 403:91a4bea587f4 5588
mbed_official 403:91a4bea587f4 5589 /******************* Bit definition for TIM_SMCR register *******************/
mbed_official 403:91a4bea587f4 5590 #define TIM_SMCR_SMS ((uint32_t)0x00010007) /*!<SMS[2:0] bits (Slave mode selection) */
mbed_official 403:91a4bea587f4 5591 #define TIM_SMCR_SMS_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 403:91a4bea587f4 5592 #define TIM_SMCR_SMS_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 403:91a4bea587f4 5593 #define TIM_SMCR_SMS_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 403:91a4bea587f4 5594 #define TIM_SMCR_SMS_3 ((uint32_t)0x00010000) /*!<Bit 3 */
mbed_official 403:91a4bea587f4 5595
mbed_official 403:91a4bea587f4 5596 #define TIM_SMCR_OCCS ((uint32_t)0x00000008) /*!< OCREF clear selection */
mbed_official 403:91a4bea587f4 5597
mbed_official 403:91a4bea587f4 5598 #define TIM_SMCR_TS ((uint32_t)0x00000070) /*!<TS[2:0] bits (Trigger selection) */
mbed_official 403:91a4bea587f4 5599 #define TIM_SMCR_TS_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 403:91a4bea587f4 5600 #define TIM_SMCR_TS_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 403:91a4bea587f4 5601 #define TIM_SMCR_TS_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 403:91a4bea587f4 5602
mbed_official 403:91a4bea587f4 5603 #define TIM_SMCR_MSM ((uint32_t)0x00000080) /*!<Master/slave mode */
mbed_official 403:91a4bea587f4 5604
mbed_official 403:91a4bea587f4 5605 #define TIM_SMCR_ETF ((uint32_t)0x00000F00) /*!<ETF[3:0] bits (External trigger filter) */
mbed_official 403:91a4bea587f4 5606 #define TIM_SMCR_ETF_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 403:91a4bea587f4 5607 #define TIM_SMCR_ETF_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 403:91a4bea587f4 5608 #define TIM_SMCR_ETF_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 403:91a4bea587f4 5609 #define TIM_SMCR_ETF_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 403:91a4bea587f4 5610
mbed_official 403:91a4bea587f4 5611 #define TIM_SMCR_ETPS ((uint32_t)0x00003000) /*!<ETPS[1:0] bits (External trigger prescaler) */
mbed_official 403:91a4bea587f4 5612 #define TIM_SMCR_ETPS_0 ((uint32_t)0x00001000) /*!<Bit 0 */
mbed_official 403:91a4bea587f4 5613 #define TIM_SMCR_ETPS_1 ((uint32_t)0x00002000) /*!<Bit 1 */
mbed_official 403:91a4bea587f4 5614
mbed_official 403:91a4bea587f4 5615 #define TIM_SMCR_ECE ((uint32_t)0x00004000) /*!<External clock enable */
mbed_official 403:91a4bea587f4 5616 #define TIM_SMCR_ETP ((uint32_t)0x00008000) /*!<External trigger polarity */
mbed_official 403:91a4bea587f4 5617
mbed_official 403:91a4bea587f4 5618 /******************* Bit definition for TIM_DIER register *******************/
mbed_official 403:91a4bea587f4 5619 #define TIM_DIER_UIE ((uint32_t)0x00000001) /*!<Update interrupt enable */
mbed_official 403:91a4bea587f4 5620 #define TIM_DIER_CC1IE ((uint32_t)0x00000002) /*!<Capture/Compare 1 interrupt enable */
mbed_official 403:91a4bea587f4 5621 #define TIM_DIER_CC2IE ((uint32_t)0x00000004) /*!<Capture/Compare 2 interrupt enable */
mbed_official 403:91a4bea587f4 5622 #define TIM_DIER_CC3IE ((uint32_t)0x00000008) /*!<Capture/Compare 3 interrupt enable */
mbed_official 403:91a4bea587f4 5623 #define TIM_DIER_CC4IE ((uint32_t)0x00000010) /*!<Capture/Compare 4 interrupt enable */
mbed_official 403:91a4bea587f4 5624 #define TIM_DIER_COMIE ((uint32_t)0x00000020) /*!<COM interrupt enable */
mbed_official 403:91a4bea587f4 5625 #define TIM_DIER_TIE ((uint32_t)0x00000040) /*!<Trigger interrupt enable */
mbed_official 403:91a4bea587f4 5626 #define TIM_DIER_BIE ((uint32_t)0x00000080) /*!<Break interrupt enable */
mbed_official 403:91a4bea587f4 5627 #define TIM_DIER_UDE ((uint32_t)0x00000100) /*!<Update DMA request enable */
mbed_official 403:91a4bea587f4 5628 #define TIM_DIER_CC1DE ((uint32_t)0x00000200) /*!<Capture/Compare 1 DMA request enable */
mbed_official 403:91a4bea587f4 5629 #define TIM_DIER_CC2DE ((uint32_t)0x00000400) /*!<Capture/Compare 2 DMA request enable */
mbed_official 403:91a4bea587f4 5630 #define TIM_DIER_CC3DE ((uint32_t)0x00000800) /*!<Capture/Compare 3 DMA request enable */
mbed_official 403:91a4bea587f4 5631 #define TIM_DIER_CC4DE ((uint32_t)0x00001000) /*!<Capture/Compare 4 DMA request enable */
mbed_official 403:91a4bea587f4 5632 #define TIM_DIER_COMDE ((uint32_t)0x00002000) /*!<COM DMA request enable */
mbed_official 403:91a4bea587f4 5633 #define TIM_DIER_TDE ((uint32_t)0x00004000) /*!<Trigger DMA request enable */
mbed_official 403:91a4bea587f4 5634
mbed_official 403:91a4bea587f4 5635 /******************** Bit definition for TIM_SR register ********************/
mbed_official 403:91a4bea587f4 5636 #define TIM_SR_UIF ((uint32_t)0x00000001) /*!<Update interrupt Flag */
mbed_official 403:91a4bea587f4 5637 #define TIM_SR_CC1IF ((uint32_t)0x00000002) /*!<Capture/Compare 1 interrupt Flag */
mbed_official 403:91a4bea587f4 5638 #define TIM_SR_CC2IF ((uint32_t)0x00000004) /*!<Capture/Compare 2 interrupt Flag */
mbed_official 403:91a4bea587f4 5639 #define TIM_SR_CC3IF ((uint32_t)0x00000008) /*!<Capture/Compare 3 interrupt Flag */
mbed_official 403:91a4bea587f4 5640 #define TIM_SR_CC4IF ((uint32_t)0x00000010) /*!<Capture/Compare 4 interrupt Flag */
mbed_official 403:91a4bea587f4 5641 #define TIM_SR_COMIF ((uint32_t)0x00000020) /*!<COM interrupt Flag */
mbed_official 403:91a4bea587f4 5642 #define TIM_SR_TIF ((uint32_t)0x00000040) /*!<Trigger interrupt Flag */
mbed_official 403:91a4bea587f4 5643 #define TIM_SR_BIF ((uint32_t)0x00000080) /*!<Break interrupt Flag */
mbed_official 403:91a4bea587f4 5644 #define TIM_SR_B2IF ((uint32_t)0x00000100) /*!<Break2 interrupt Flag */
mbed_official 403:91a4bea587f4 5645 #define TIM_SR_CC1OF ((uint32_t)0x00000200) /*!<Capture/Compare 1 Overcapture Flag */
mbed_official 403:91a4bea587f4 5646 #define TIM_SR_CC2OF ((uint32_t)0x00000400) /*!<Capture/Compare 2 Overcapture Flag */
mbed_official 403:91a4bea587f4 5647 #define TIM_SR_CC3OF ((uint32_t)0x00000800) /*!<Capture/Compare 3 Overcapture Flag */
mbed_official 403:91a4bea587f4 5648 #define TIM_SR_CC4OF ((uint32_t)0x00001000) /*!<Capture/Compare 4 Overcapture Flag */
mbed_official 403:91a4bea587f4 5649 #define TIM_SR_CC5IF ((uint32_t)0x00010000) /*!<Capture/Compare 5 interrupt Flag */
mbed_official 403:91a4bea587f4 5650 #define TIM_SR_CC6IF ((uint32_t)0x00020000) /*!<Capture/Compare 6 interrupt Flag */
mbed_official 403:91a4bea587f4 5651
mbed_official 403:91a4bea587f4 5652 /******************* Bit definition for TIM_EGR register ********************/
mbed_official 403:91a4bea587f4 5653 #define TIM_EGR_UG ((uint32_t)0x00000001) /*!<Update Generation */
mbed_official 403:91a4bea587f4 5654 #define TIM_EGR_CC1G ((uint32_t)0x00000002) /*!<Capture/Compare 1 Generation */
mbed_official 403:91a4bea587f4 5655 #define TIM_EGR_CC2G ((uint32_t)0x00000004) /*!<Capture/Compare 2 Generation */
mbed_official 403:91a4bea587f4 5656 #define TIM_EGR_CC3G ((uint32_t)0x00000008) /*!<Capture/Compare 3 Generation */
mbed_official 403:91a4bea587f4 5657 #define TIM_EGR_CC4G ((uint32_t)0x00000010) /*!<Capture/Compare 4 Generation */
mbed_official 403:91a4bea587f4 5658 #define TIM_EGR_COMG ((uint32_t)0x00000020) /*!<Capture/Compare Control Update Generation */
mbed_official 403:91a4bea587f4 5659 #define TIM_EGR_TG ((uint32_t)0x00000040) /*!<Trigger Generation */
mbed_official 403:91a4bea587f4 5660 #define TIM_EGR_BG ((uint32_t)0x00000080) /*!<Break Generation */
mbed_official 403:91a4bea587f4 5661 #define TIM_EGR_B2G ((uint32_t)0x00000100) /*!<Break Generation */
mbed_official 403:91a4bea587f4 5662
mbed_official 403:91a4bea587f4 5663 /****************** Bit definition for TIM_CCMR1 register *******************/
mbed_official 403:91a4bea587f4 5664 #define TIM_CCMR1_CC1S ((uint32_t)0x00000003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
mbed_official 403:91a4bea587f4 5665 #define TIM_CCMR1_CC1S_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 403:91a4bea587f4 5666 #define TIM_CCMR1_CC1S_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 403:91a4bea587f4 5667
mbed_official 403:91a4bea587f4 5668 #define TIM_CCMR1_OC1FE ((uint32_t)0x00000004) /*!<Output Compare 1 Fast enable */
mbed_official 403:91a4bea587f4 5669 #define TIM_CCMR1_OC1PE ((uint32_t)0x00000008) /*!<Output Compare 1 Preload enable */
mbed_official 403:91a4bea587f4 5670
mbed_official 403:91a4bea587f4 5671 #define TIM_CCMR1_OC1M ((uint32_t)0x00010070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
mbed_official 403:91a4bea587f4 5672 #define TIM_CCMR1_OC1M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 403:91a4bea587f4 5673 #define TIM_CCMR1_OC1M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 403:91a4bea587f4 5674 #define TIM_CCMR1_OC1M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 403:91a4bea587f4 5675 #define TIM_CCMR1_OC1M_3 ((uint32_t)0x00010000) /*!<Bit 3 */
mbed_official 403:91a4bea587f4 5676
mbed_official 403:91a4bea587f4 5677 #define TIM_CCMR1_OC1CE ((uint32_t)0x00000080) /*!<Output Compare 1Clear Enable */
mbed_official 403:91a4bea587f4 5678
mbed_official 403:91a4bea587f4 5679 #define TIM_CCMR1_CC2S ((uint32_t)0x00000300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
mbed_official 403:91a4bea587f4 5680 #define TIM_CCMR1_CC2S_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 403:91a4bea587f4 5681 #define TIM_CCMR1_CC2S_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 403:91a4bea587f4 5682
mbed_official 403:91a4bea587f4 5683 #define TIM_CCMR1_OC2FE ((uint32_t)0x00000400) /*!<Output Compare 2 Fast enable */
mbed_official 403:91a4bea587f4 5684 #define TIM_CCMR1_OC2PE ((uint32_t)0x00000800) /*!<Output Compare 2 Preload enable */
mbed_official 403:91a4bea587f4 5685
mbed_official 403:91a4bea587f4 5686 #define TIM_CCMR1_OC2M ((uint32_t)0x01007000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
mbed_official 403:91a4bea587f4 5687 #define TIM_CCMR1_OC2M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
mbed_official 403:91a4bea587f4 5688 #define TIM_CCMR1_OC2M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
mbed_official 403:91a4bea587f4 5689 #define TIM_CCMR1_OC2M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
mbed_official 403:91a4bea587f4 5690 #define TIM_CCMR1_OC2M_3 ((uint32_t)0x01000000) /*!<Bit 3 */
mbed_official 403:91a4bea587f4 5691
mbed_official 403:91a4bea587f4 5692 #define TIM_CCMR1_OC2CE ((uint32_t)0x00008000) /*!<Output Compare 2 Clear Enable */
mbed_official 403:91a4bea587f4 5693
mbed_official 403:91a4bea587f4 5694 /*----------------------------------------------------------------------------*/
mbed_official 403:91a4bea587f4 5695
mbed_official 403:91a4bea587f4 5696 #define TIM_CCMR1_IC1PSC ((uint32_t)0x0000000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
mbed_official 403:91a4bea587f4 5697 #define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x00000004) /*!<Bit 0 */
mbed_official 403:91a4bea587f4 5698 #define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x00000008) /*!<Bit 1 */
mbed_official 403:91a4bea587f4 5699
mbed_official 403:91a4bea587f4 5700 #define TIM_CCMR1_IC1F ((uint32_t)0x000000F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
mbed_official 403:91a4bea587f4 5701 #define TIM_CCMR1_IC1F_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 403:91a4bea587f4 5702 #define TIM_CCMR1_IC1F_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 403:91a4bea587f4 5703 #define TIM_CCMR1_IC1F_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 403:91a4bea587f4 5704 #define TIM_CCMR1_IC1F_3 ((uint32_t)0x00000080) /*!<Bit 3 */
mbed_official 403:91a4bea587f4 5705
mbed_official 403:91a4bea587f4 5706 #define TIM_CCMR1_IC2PSC ((uint32_t)0x00000C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
mbed_official 403:91a4bea587f4 5707 #define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x00000400) /*!<Bit 0 */
mbed_official 403:91a4bea587f4 5708 #define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x00000800) /*!<Bit 1 */
mbed_official 403:91a4bea587f4 5709
mbed_official 403:91a4bea587f4 5710 #define TIM_CCMR1_IC2F ((uint32_t)0x0000F000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
mbed_official 403:91a4bea587f4 5711 #define TIM_CCMR1_IC2F_0 ((uint32_t)0x00001000) /*!<Bit 0 */
mbed_official 403:91a4bea587f4 5712 #define TIM_CCMR1_IC2F_1 ((uint32_t)0x00002000) /*!<Bit 1 */
mbed_official 403:91a4bea587f4 5713 #define TIM_CCMR1_IC2F_2 ((uint32_t)0x00004000) /*!<Bit 2 */
mbed_official 403:91a4bea587f4 5714 #define TIM_CCMR1_IC2F_3 ((uint32_t)0x00008000) /*!<Bit 3 */
mbed_official 403:91a4bea587f4 5715
mbed_official 403:91a4bea587f4 5716 /****************** Bit definition for TIM_CCMR2 register *******************/
mbed_official 403:91a4bea587f4 5717 #define TIM_CCMR2_CC3S ((uint32_t)0x00000003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
mbed_official 403:91a4bea587f4 5718 #define TIM_CCMR2_CC3S_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 403:91a4bea587f4 5719 #define TIM_CCMR2_CC3S_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 403:91a4bea587f4 5720
mbed_official 403:91a4bea587f4 5721 #define TIM_CCMR2_OC3FE ((uint32_t)0x00000004) /*!<Output Compare 3 Fast enable */
mbed_official 403:91a4bea587f4 5722 #define TIM_CCMR2_OC3PE ((uint32_t)0x00000008) /*!<Output Compare 3 Preload enable */
mbed_official 403:91a4bea587f4 5723
mbed_official 403:91a4bea587f4 5724 #define TIM_CCMR2_OC3M ((uint32_t)0x00010070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
mbed_official 403:91a4bea587f4 5725 #define TIM_CCMR2_OC3M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 403:91a4bea587f4 5726 #define TIM_CCMR2_OC3M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 403:91a4bea587f4 5727 #define TIM_CCMR2_OC3M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 403:91a4bea587f4 5728 #define TIM_CCMR2_OC3M_3 ((uint32_t)0x00010000) /*!<Bit 3 */
mbed_official 403:91a4bea587f4 5729
mbed_official 403:91a4bea587f4 5730 #define TIM_CCMR2_OC3CE ((uint32_t)0x00000080) /*!<Output Compare 3 Clear Enable */
mbed_official 403:91a4bea587f4 5731
mbed_official 403:91a4bea587f4 5732 #define TIM_CCMR2_CC4S ((uint32_t)0x00000300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
mbed_official 403:91a4bea587f4 5733 #define TIM_CCMR2_CC4S_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 403:91a4bea587f4 5734 #define TIM_CCMR2_CC4S_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 403:91a4bea587f4 5735
mbed_official 403:91a4bea587f4 5736 #define TIM_CCMR2_OC4FE ((uint32_t)0x00000400) /*!<Output Compare 4 Fast enable */
mbed_official 403:91a4bea587f4 5737 #define TIM_CCMR2_OC4PE ((uint32_t)0x00000800) /*!<Output Compare 4 Preload enable */
mbed_official 403:91a4bea587f4 5738
mbed_official 403:91a4bea587f4 5739 #define TIM_CCMR2_OC4M ((uint32_t)0x01007000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
mbed_official 403:91a4bea587f4 5740 #define TIM_CCMR2_OC4M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
mbed_official 403:91a4bea587f4 5741 #define TIM_CCMR2_OC4M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
mbed_official 403:91a4bea587f4 5742 #define TIM_CCMR2_OC4M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
mbed_official 403:91a4bea587f4 5743 #define TIM_CCMR2_OC4M_3 ((uint32_t)0x01000000) /*!<Bit 3 */
mbed_official 403:91a4bea587f4 5744
mbed_official 403:91a4bea587f4 5745 #define TIM_CCMR2_OC4CE ((uint32_t)0x00008000) /*!<Output Compare 4 Clear Enable */
mbed_official 403:91a4bea587f4 5746
mbed_official 403:91a4bea587f4 5747 /*----------------------------------------------------------------------------*/
mbed_official 403:91a4bea587f4 5748
mbed_official 403:91a4bea587f4 5749 #define TIM_CCMR2_IC3PSC ((uint32_t)0x00000000000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
mbed_official 403:91a4bea587f4 5750 #define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x000000000004) /*!<Bit 0 */
mbed_official 403:91a4bea587f4 5751 #define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x000000000008) /*!<Bit 1 */
mbed_official 403:91a4bea587f4 5752
mbed_official 403:91a4bea587f4 5753 #define TIM_CCMR2_IC3F ((uint32_t)0x0000000000F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
mbed_official 403:91a4bea587f4 5754 #define TIM_CCMR2_IC3F_0 ((uint32_t)0x000000000010) /*!<Bit 0 */
mbed_official 403:91a4bea587f4 5755 #define TIM_CCMR2_IC3F_1 ((uint32_t)0x000000000020) /*!<Bit 1 */
mbed_official 403:91a4bea587f4 5756 #define TIM_CCMR2_IC3F_2 ((uint32_t)0x000000000040) /*!<Bit 2 */
mbed_official 403:91a4bea587f4 5757 #define TIM_CCMR2_IC3F_3 ((uint32_t)0x000000000080) /*!<Bit 3 */
mbed_official 403:91a4bea587f4 5758
mbed_official 403:91a4bea587f4 5759 #define TIM_CCMR2_IC4PSC ((uint32_t)0x000000000C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
mbed_official 403:91a4bea587f4 5760 #define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x000000000400) /*!<Bit 0 */
mbed_official 403:91a4bea587f4 5761 #define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x000000000800) /*!<Bit 1 */
mbed_official 403:91a4bea587f4 5762
mbed_official 403:91a4bea587f4 5763 #define TIM_CCMR2_IC4F ((uint32_t)0x00000000F000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
mbed_official 403:91a4bea587f4 5764 #define TIM_CCMR2_IC4F_0 ((uint32_t)0x000000001000) /*!<Bit 0 */
mbed_official 403:91a4bea587f4 5765 #define TIM_CCMR2_IC4F_1 ((uint32_t)0x000000002000) /*!<Bit 1 */
mbed_official 403:91a4bea587f4 5766 #define TIM_CCMR2_IC4F_2 ((uint32_t)0x000000004000) /*!<Bit 2 */
mbed_official 403:91a4bea587f4 5767 #define TIM_CCMR2_IC4F_3 ((uint32_t)0x000000008000) /*!<Bit 3 */
mbed_official 403:91a4bea587f4 5768
mbed_official 403:91a4bea587f4 5769 /******************* Bit definition for TIM_CCER register *******************/
mbed_official 403:91a4bea587f4 5770 #define TIM_CCER_CC1E ((uint32_t)0x00000001) /*!<Capture/Compare 1 output enable */
mbed_official 403:91a4bea587f4 5771 #define TIM_CCER_CC1P ((uint32_t)0x00000002) /*!<Capture/Compare 1 output Polarity */
mbed_official 403:91a4bea587f4 5772 #define TIM_CCER_CC1NE ((uint32_t)0x00000004) /*!<Capture/Compare 1 Complementary output enable */
mbed_official 403:91a4bea587f4 5773 #define TIM_CCER_CC1NP ((uint32_t)0x00000008) /*!<Capture/Compare 1 Complementary output Polarity */
mbed_official 403:91a4bea587f4 5774 #define TIM_CCER_CC2E ((uint32_t)0x00000010) /*!<Capture/Compare 2 output enable */
mbed_official 403:91a4bea587f4 5775 #define TIM_CCER_CC2P ((uint32_t)0x00000020) /*!<Capture/Compare 2 output Polarity */
mbed_official 403:91a4bea587f4 5776 #define TIM_CCER_CC2NE ((uint32_t)0x00000040) /*!<Capture/Compare 2 Complementary output enable */
mbed_official 403:91a4bea587f4 5777 #define TIM_CCER_CC2NP ((uint32_t)0x00000080) /*!<Capture/Compare 2 Complementary output Polarity */
mbed_official 403:91a4bea587f4 5778 #define TIM_CCER_CC3E ((uint32_t)0x00000100) /*!<Capture/Compare 3 output enable */
mbed_official 403:91a4bea587f4 5779 #define TIM_CCER_CC3P ((uint32_t)0x00000200) /*!<Capture/Compare 3 output Polarity */
mbed_official 403:91a4bea587f4 5780 #define TIM_CCER_CC3NE ((uint32_t)0x00000400) /*!<Capture/Compare 3 Complementary output enable */
mbed_official 403:91a4bea587f4 5781 #define TIM_CCER_CC3NP ((uint32_t)0x00000800) /*!<Capture/Compare 3 Complementary output Polarity */
mbed_official 403:91a4bea587f4 5782 #define TIM_CCER_CC4E ((uint32_t)0x00001000) /*!<Capture/Compare 4 output enable */
mbed_official 403:91a4bea587f4 5783 #define TIM_CCER_CC4P ((uint32_t)0x00002000) /*!<Capture/Compare 4 output Polarity */
mbed_official 403:91a4bea587f4 5784 #define TIM_CCER_CC4NP ((uint32_t)0x00008000) /*!<Capture/Compare 4 Complementary output Polarity */
mbed_official 403:91a4bea587f4 5785 #define TIM_CCER_CC5E ((uint32_t)0x00010000) /*!<Capture/Compare 5 output enable */
mbed_official 403:91a4bea587f4 5786 #define TIM_CCER_CC5P ((uint32_t)0x00020000) /*!<Capture/Compare 5 output Polarity */
mbed_official 403:91a4bea587f4 5787 #define TIM_CCER_CC6E ((uint32_t)0x00100000) /*!<Capture/Compare 6 output enable */
mbed_official 403:91a4bea587f4 5788 #define TIM_CCER_CC6P ((uint32_t)0x00200000) /*!<Capture/Compare 6 output Polarity */
mbed_official 403:91a4bea587f4 5789
mbed_official 403:91a4bea587f4 5790 /******************* Bit definition for TIM_CNT register ********************/
mbed_official 403:91a4bea587f4 5791 #define TIM_CNT_CNT ((uint32_t)0xFFFFFFFF) /*!<Counter Value */
mbed_official 403:91a4bea587f4 5792 #define TIM_CNT_UIFCPY ((uint32_t)0x80000000) /*!<Update interrupt flag copy */
mbed_official 403:91a4bea587f4 5793
mbed_official 403:91a4bea587f4 5794 /******************* Bit definition for TIM_PSC register ********************/
mbed_official 403:91a4bea587f4 5795 #define TIM_PSC_PSC ((uint32_t)0x0000FFFF) /*!<Prescaler Value */
mbed_official 403:91a4bea587f4 5796
mbed_official 403:91a4bea587f4 5797 /******************* Bit definition for TIM_ARR register ********************/
mbed_official 403:91a4bea587f4 5798 #define TIM_ARR_ARR ((uint32_t)0xFFFFFFFF) /*!<actual auto-reload Value */
mbed_official 403:91a4bea587f4 5799
mbed_official 403:91a4bea587f4 5800 /******************* Bit definition for TIM_RCR register ********************/
mbed_official 403:91a4bea587f4 5801 #define TIM_RCR_REP ((uint32_t)0x000000FF) /*!<Repetition Counter Value */
mbed_official 403:91a4bea587f4 5802
mbed_official 403:91a4bea587f4 5803 /******************* Bit definition for TIM_CCR1 register *******************/
mbed_official 403:91a4bea587f4 5804 #define TIM_CCR1_CCR1 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 1 Value */
mbed_official 403:91a4bea587f4 5805
mbed_official 403:91a4bea587f4 5806 /******************* Bit definition for TIM_CCR2 register *******************/
mbed_official 403:91a4bea587f4 5807 #define TIM_CCR2_CCR2 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 2 Value */
mbed_official 403:91a4bea587f4 5808
mbed_official 403:91a4bea587f4 5809 /******************* Bit definition for TIM_CCR3 register *******************/
mbed_official 403:91a4bea587f4 5810 #define TIM_CCR3_CCR3 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 3 Value */
mbed_official 403:91a4bea587f4 5811
mbed_official 403:91a4bea587f4 5812 /******************* Bit definition for TIM_CCR4 register *******************/
mbed_official 403:91a4bea587f4 5813 #define TIM_CCR4_CCR4 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 4 Value */
mbed_official 403:91a4bea587f4 5814
mbed_official 403:91a4bea587f4 5815 /******************* Bit definition for TIM_CCR5 register *******************/
mbed_official 403:91a4bea587f4 5816 #define TIM_CCR5_CCR5 ((uint32_t)0xFFFFFFFF) /*!<Capture/Compare 5 Value */
mbed_official 403:91a4bea587f4 5817 #define TIM_CCR5_GC5C1 ((uint32_t)0x20000000) /*!<Group Channel 5 and Channel 1 */
mbed_official 403:91a4bea587f4 5818 #define TIM_CCR5_GC5C2 ((uint32_t)0x40000000) /*!<Group Channel 5 and Channel 2 */
mbed_official 403:91a4bea587f4 5819 #define TIM_CCR5_GC5C3 ((uint32_t)0x80000000) /*!<Group Channel 5 and Channel 3 */
mbed_official 403:91a4bea587f4 5820
mbed_official 403:91a4bea587f4 5821 /******************* Bit definition for TIM_CCR6 register *******************/
mbed_official 403:91a4bea587f4 5822 #define TIM_CCR6_CCR6 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 6 Value */
mbed_official 403:91a4bea587f4 5823
mbed_official 403:91a4bea587f4 5824 /******************* Bit definition for TIM_BDTR register *******************/
mbed_official 403:91a4bea587f4 5825 #define TIM_BDTR_DTG ((uint32_t)0x000000FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
mbed_official 403:91a4bea587f4 5826 #define TIM_BDTR_DTG_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 403:91a4bea587f4 5827 #define TIM_BDTR_DTG_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 403:91a4bea587f4 5828 #define TIM_BDTR_DTG_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 403:91a4bea587f4 5829 #define TIM_BDTR_DTG_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 403:91a4bea587f4 5830 #define TIM_BDTR_DTG_4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 403:91a4bea587f4 5831 #define TIM_BDTR_DTG_5 ((uint32_t)0x00000020) /*!<Bit 5 */
mbed_official 403:91a4bea587f4 5832 #define TIM_BDTR_DTG_6 ((uint32_t)0x00000040) /*!<Bit 6 */
mbed_official 403:91a4bea587f4 5833 #define TIM_BDTR_DTG_7 ((uint32_t)0x00000080) /*!<Bit 7 */
mbed_official 403:91a4bea587f4 5834
mbed_official 403:91a4bea587f4 5835 #define TIM_BDTR_LOCK ((uint32_t)0x00000300) /*!<LOCK[1:0] bits (Lock Configuration) */
mbed_official 403:91a4bea587f4 5836 #define TIM_BDTR_LOCK_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 403:91a4bea587f4 5837 #define TIM_BDTR_LOCK_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 403:91a4bea587f4 5838
mbed_official 403:91a4bea587f4 5839 #define TIM_BDTR_OSSI ((uint32_t)0x00000400) /*!<Off-State Selection for Idle mode */
mbed_official 403:91a4bea587f4 5840 #define TIM_BDTR_OSSR ((uint32_t)0x00000800) /*!<Off-State Selection for Run mode */
mbed_official 403:91a4bea587f4 5841 #define TIM_BDTR_BKE ((uint32_t)0x00001000) /*!<Break enable for Break1 */
mbed_official 403:91a4bea587f4 5842 #define TIM_BDTR_BKP ((uint32_t)0x00002000) /*!<Break Polarity for Break1 */
mbed_official 403:91a4bea587f4 5843 #define TIM_BDTR_AOE ((uint32_t)0x00004000) /*!<Automatic Output enable */
mbed_official 403:91a4bea587f4 5844 #define TIM_BDTR_MOE ((uint32_t)0x00008000) /*!<Main Output enable */
mbed_official 403:91a4bea587f4 5845
mbed_official 403:91a4bea587f4 5846 #define TIM_BDTR_BKF ((uint32_t)0x000F0000) /*!<Break Filter for Break1 */
mbed_official 403:91a4bea587f4 5847 #define TIM_BDTR_BK2F ((uint32_t)0x00F00000) /*!<Break Filter for Break2 */
mbed_official 403:91a4bea587f4 5848
mbed_official 403:91a4bea587f4 5849 #define TIM_BDTR_BK2E ((uint32_t)0x01000000) /*!<Break enable for Break2 */
mbed_official 403:91a4bea587f4 5850 #define TIM_BDTR_BK2P ((uint32_t)0x02000000) /*!<Break Polarity for Break2 */
mbed_official 403:91a4bea587f4 5851
mbed_official 403:91a4bea587f4 5852 /******************* Bit definition for TIM_DCR register ********************/
mbed_official 403:91a4bea587f4 5853 #define TIM_DCR_DBA ((uint32_t)0x0000001F) /*!<DBA[4:0] bits (DMA Base Address) */
mbed_official 403:91a4bea587f4 5854 #define TIM_DCR_DBA_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 403:91a4bea587f4 5855 #define TIM_DCR_DBA_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 403:91a4bea587f4 5856 #define TIM_DCR_DBA_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 403:91a4bea587f4 5857 #define TIM_DCR_DBA_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 403:91a4bea587f4 5858 #define TIM_DCR_DBA_4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 403:91a4bea587f4 5859
mbed_official 403:91a4bea587f4 5860 #define TIM_DCR_DBL ((uint32_t)0x00001F00) /*!<DBL[4:0] bits (DMA Burst Length) */
mbed_official 403:91a4bea587f4 5861 #define TIM_DCR_DBL_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 403:91a4bea587f4 5862 #define TIM_DCR_DBL_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 403:91a4bea587f4 5863 #define TIM_DCR_DBL_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 403:91a4bea587f4 5864 #define TIM_DCR_DBL_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 403:91a4bea587f4 5865 #define TIM_DCR_DBL_4 ((uint32_t)0x00001000) /*!<Bit 4 */
mbed_official 403:91a4bea587f4 5866
mbed_official 403:91a4bea587f4 5867 /******************* Bit definition for TIM_DMAR register *******************/
mbed_official 403:91a4bea587f4 5868 #define TIM_DMAR_DMAB ((uint32_t)0x0000FFFF) /*!<DMA register for burst accesses */
mbed_official 403:91a4bea587f4 5869
mbed_official 403:91a4bea587f4 5870 /******************* Bit definition for TIM16_OR register *********************/
mbed_official 403:91a4bea587f4 5871 #define TIM16_OR_TI1_RMP ((uint32_t)0x000000C0) /*!<TI1_RMP[1:0] bits (TIM16 Input 1 remap) */
mbed_official 403:91a4bea587f4 5872 #define TIM16_OR_TI1_RMP_0 ((uint32_t)0x00000040) /*!<Bit 0 */
mbed_official 403:91a4bea587f4 5873 #define TIM16_OR_TI1_RMP_1 ((uint32_t)0x00000080) /*!<Bit 1 */
mbed_official 403:91a4bea587f4 5874
mbed_official 403:91a4bea587f4 5875 /******************* Bit definition for TIM1_OR register *********************/
mbed_official 403:91a4bea587f4 5876 #define TIM1_OR_ETR_RMP ((uint32_t)0x0000000F) /*!<ETR_RMP[3:0] bits (TIM1 ETR remap) */
mbed_official 403:91a4bea587f4 5877 #define TIM1_OR_ETR_RMP_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 403:91a4bea587f4 5878 #define TIM1_OR_ETR_RMP_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 403:91a4bea587f4 5879 #define TIM1_OR_ETR_RMP_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 403:91a4bea587f4 5880 #define TIM1_OR_ETR_RMP_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 403:91a4bea587f4 5881
mbed_official 403:91a4bea587f4 5882 /******************* Bit definition for TIM8_OR register *********************/
mbed_official 403:91a4bea587f4 5883 #define TIM8_OR_ETR_RMP ((uint32_t)0x0000000F) /*!<ETR_RMP[3:0] bits (TIM8 ETR remap) */
mbed_official 403:91a4bea587f4 5884 #define TIM8_OR_ETR_RMP_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 403:91a4bea587f4 5885 #define TIM8_OR_ETR_RMP_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 403:91a4bea587f4 5886 #define TIM8_OR_ETR_RMP_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 403:91a4bea587f4 5887 #define TIM8_OR_ETR_RMP_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 403:91a4bea587f4 5888
mbed_official 403:91a4bea587f4 5889 /****************** Bit definition for TIM_CCMR3 register *******************/
mbed_official 403:91a4bea587f4 5890 #define TIM_CCMR3_OC5FE ((uint32_t)0x00000004) /*!<Output Compare 5 Fast enable */
mbed_official 403:91a4bea587f4 5891 #define TIM_CCMR3_OC5PE ((uint32_t)0x00000008) /*!<Output Compare 5 Preload enable */
mbed_official 403:91a4bea587f4 5892
mbed_official 403:91a4bea587f4 5893 #define TIM_CCMR3_OC5M ((uint32_t)0x00010070) /*!<OC5M[2:0] bits (Output Compare 5 Mode) */
mbed_official 403:91a4bea587f4 5894 #define TIM_CCMR3_OC5M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 403:91a4bea587f4 5895 #define TIM_CCMR3_OC5M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 403:91a4bea587f4 5896 #define TIM_CCMR3_OC5M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 403:91a4bea587f4 5897 #define TIM_CCMR3_OC5M_3 ((uint32_t)0x00010000) /*!<Bit 3 */
mbed_official 403:91a4bea587f4 5898
mbed_official 403:91a4bea587f4 5899 #define TIM_CCMR3_OC5CE ((uint32_t)0x00000080) /*!<Output Compare 5 Clear Enable */
mbed_official 403:91a4bea587f4 5900
mbed_official 403:91a4bea587f4 5901 #define TIM_CCMR3_OC6FE ((uint32_t)0x00000400) /*!<Output Compare 6 Fast enable */
mbed_official 403:91a4bea587f4 5902 #define TIM_CCMR3_OC6PE ((uint32_t)0x00000800) /*!<Output Compare 6 Preload enable */
mbed_official 403:91a4bea587f4 5903
mbed_official 403:91a4bea587f4 5904 #define TIM_CCMR3_OC6M ((uint32_t)0x01007000) /*!<OC6M[2:0] bits (Output Compare 6 Mode) */
mbed_official 403:91a4bea587f4 5905 #define TIM_CCMR3_OC6M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
mbed_official 403:91a4bea587f4 5906 #define TIM_CCMR3_OC6M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
mbed_official 403:91a4bea587f4 5907 #define TIM_CCMR3_OC6M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
mbed_official 403:91a4bea587f4 5908 #define TIM_CCMR3_OC6M_3 ((uint32_t)0x01000000) /*!<Bit 3 */
mbed_official 403:91a4bea587f4 5909
mbed_official 403:91a4bea587f4 5910 #define TIM_CCMR3_OC6CE ((uint32_t)0x00008000) /*!<Output Compare 6 Clear Enable */
mbed_official 403:91a4bea587f4 5911
mbed_official 403:91a4bea587f4 5912 /******************************************************************************/
mbed_official 403:91a4bea587f4 5913 /* */
mbed_official 403:91a4bea587f4 5914 /* Touch Sensing Controller (TSC) */
mbed_official 403:91a4bea587f4 5915 /* */
mbed_official 403:91a4bea587f4 5916 /******************************************************************************/
mbed_official 403:91a4bea587f4 5917 /******************* Bit definition for TSC_CR register *********************/
mbed_official 403:91a4bea587f4 5918 #define TSC_CR_TSCE ((uint32_t)0x00000001) /*!<Touch sensing controller enable */
mbed_official 403:91a4bea587f4 5919 #define TSC_CR_START ((uint32_t)0x00000002) /*!<Start acquisition */
mbed_official 403:91a4bea587f4 5920 #define TSC_CR_AM ((uint32_t)0x00000004) /*!<Acquisition mode */
mbed_official 403:91a4bea587f4 5921 #define TSC_CR_SYNCPOL ((uint32_t)0x00000008) /*!<Synchronization pin polarity */
mbed_official 403:91a4bea587f4 5922 #define TSC_CR_IODEF ((uint32_t)0x00000010) /*!<IO default mode */
mbed_official 403:91a4bea587f4 5923
mbed_official 403:91a4bea587f4 5924 #define TSC_CR_MCV ((uint32_t)0x000000E0) /*!<MCV[2:0] bits (Max Count Value) */
mbed_official 403:91a4bea587f4 5925 #define TSC_CR_MCV_0 ((uint32_t)0x00000020) /*!<Bit 0 */
mbed_official 403:91a4bea587f4 5926 #define TSC_CR_MCV_1 ((uint32_t)0x00000040) /*!<Bit 1 */
mbed_official 403:91a4bea587f4 5927 #define TSC_CR_MCV_2 ((uint32_t)0x00000080) /*!<Bit 2 */
mbed_official 403:91a4bea587f4 5928
mbed_official 403:91a4bea587f4 5929 #define TSC_CR_PGPSC ((uint32_t)0x00007000) /*!<PGPSC[2:0] bits (Pulse Generator Prescaler) */
mbed_official 403:91a4bea587f4 5930 #define TSC_CR_PGPSC_0 ((uint32_t)0x00001000) /*!<Bit 0 */
mbed_official 403:91a4bea587f4 5931 #define TSC_CR_PGPSC_1 ((uint32_t)0x00002000) /*!<Bit 1 */
mbed_official 403:91a4bea587f4 5932 #define TSC_CR_PGPSC_2 ((uint32_t)0x00004000) /*!<Bit 2 */
mbed_official 403:91a4bea587f4 5933
mbed_official 403:91a4bea587f4 5934 #define TSC_CR_SSPSC ((uint32_t)0x00008000) /*!<Spread Spectrum Prescaler */
mbed_official 403:91a4bea587f4 5935 #define TSC_CR_SSE ((uint32_t)0x00010000) /*!<Spread Spectrum Enable */
mbed_official 403:91a4bea587f4 5936
mbed_official 403:91a4bea587f4 5937 #define TSC_CR_SSD ((uint32_t)0x00FE0000) /*!<SSD[6:0] bits (Spread Spectrum Deviation) */
mbed_official 403:91a4bea587f4 5938 #define TSC_CR_SSD_0 ((uint32_t)0x00020000) /*!<Bit 0 */
mbed_official 403:91a4bea587f4 5939 #define TSC_CR_SSD_1 ((uint32_t)0x00040000) /*!<Bit 1 */
mbed_official 403:91a4bea587f4 5940 #define TSC_CR_SSD_2 ((uint32_t)0x00080000) /*!<Bit 2 */
mbed_official 403:91a4bea587f4 5941 #define TSC_CR_SSD_3 ((uint32_t)0x00100000) /*!<Bit 3 */
mbed_official 403:91a4bea587f4 5942 #define TSC_CR_SSD_4 ((uint32_t)0x00200000) /*!<Bit 4 */
mbed_official 403:91a4bea587f4 5943 #define TSC_CR_SSD_5 ((uint32_t)0x00400000) /*!<Bit 5 */
mbed_official 403:91a4bea587f4 5944 #define TSC_CR_SSD_6 ((uint32_t)0x00800000) /*!<Bit 6 */
mbed_official 403:91a4bea587f4 5945
mbed_official 403:91a4bea587f4 5946 #define TSC_CR_CTPL ((uint32_t)0x0F000000) /*!<CTPL[3:0] bits (Charge Transfer pulse low) */
mbed_official 403:91a4bea587f4 5947 #define TSC_CR_CTPL_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 403:91a4bea587f4 5948 #define TSC_CR_CTPL_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 403:91a4bea587f4 5949 #define TSC_CR_CTPL_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 403:91a4bea587f4 5950 #define TSC_CR_CTPL_3 ((uint32_t)0x08000000) /*!<Bit 3 */
mbed_official 403:91a4bea587f4 5951
mbed_official 403:91a4bea587f4 5952 #define TSC_CR_CTPH ((uint32_t)0xF0000000) /*!<CTPH[3:0] bits (Charge Transfer pulse high) */
mbed_official 403:91a4bea587f4 5953 #define TSC_CR_CTPH_0 ((uint32_t)0x10000000) /*!<Bit 0 */
mbed_official 403:91a4bea587f4 5954 #define TSC_CR_CTPH_1 ((uint32_t)0x20000000) /*!<Bit 1 */
mbed_official 403:91a4bea587f4 5955 #define TSC_CR_CTPH_2 ((uint32_t)0x40000000) /*!<Bit 2 */
mbed_official 403:91a4bea587f4 5956 #define TSC_CR_CTPH_3 ((uint32_t)0x80000000) /*!<Bit 3 */
mbed_official 403:91a4bea587f4 5957
mbed_official 403:91a4bea587f4 5958 /******************* Bit definition for TSC_IER register ********************/
mbed_official 403:91a4bea587f4 5959 #define TSC_IER_EOAIE ((uint32_t)0x00000001) /*!<End of acquisition interrupt enable */
mbed_official 403:91a4bea587f4 5960 #define TSC_IER_MCEIE ((uint32_t)0x00000002) /*!<Max count error interrupt enable */
mbed_official 403:91a4bea587f4 5961
mbed_official 403:91a4bea587f4 5962 /******************* Bit definition for TSC_ICR register ********************/
mbed_official 403:91a4bea587f4 5963 #define TSC_ICR_EOAIC ((uint32_t)0x00000001) /*!<End of acquisition interrupt clear */
mbed_official 403:91a4bea587f4 5964 #define TSC_ICR_MCEIC ((uint32_t)0x00000002) /*!<Max count error interrupt clear */
mbed_official 403:91a4bea587f4 5965
mbed_official 403:91a4bea587f4 5966 /******************* Bit definition for TSC_ISR register ********************/
mbed_official 403:91a4bea587f4 5967 #define TSC_ISR_EOAF ((uint32_t)0x00000001) /*!<End of acquisition flag */
mbed_official 403:91a4bea587f4 5968 #define TSC_ISR_MCEF ((uint32_t)0x00000002) /*!<Max count error flag */
mbed_official 403:91a4bea587f4 5969
mbed_official 403:91a4bea587f4 5970 /******************* Bit definition for TSC_IOHCR register ******************/
mbed_official 403:91a4bea587f4 5971 #define TSC_IOHCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 schmitt trigger hysteresis mode */
mbed_official 403:91a4bea587f4 5972 #define TSC_IOHCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 schmitt trigger hysteresis mode */
mbed_official 403:91a4bea587f4 5973 #define TSC_IOHCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 schmitt trigger hysteresis mode */
mbed_official 403:91a4bea587f4 5974 #define TSC_IOHCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 schmitt trigger hysteresis mode */
mbed_official 403:91a4bea587f4 5975 #define TSC_IOHCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 schmitt trigger hysteresis mode */
mbed_official 403:91a4bea587f4 5976 #define TSC_IOHCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 schmitt trigger hysteresis mode */
mbed_official 403:91a4bea587f4 5977 #define TSC_IOHCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 schmitt trigger hysteresis mode */
mbed_official 403:91a4bea587f4 5978 #define TSC_IOHCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 schmitt trigger hysteresis mode */
mbed_official 403:91a4bea587f4 5979 #define TSC_IOHCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 schmitt trigger hysteresis mode */
mbed_official 403:91a4bea587f4 5980 #define TSC_IOHCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 schmitt trigger hysteresis mode */
mbed_official 403:91a4bea587f4 5981 #define TSC_IOHCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 schmitt trigger hysteresis mode */
mbed_official 403:91a4bea587f4 5982 #define TSC_IOHCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 schmitt trigger hysteresis mode */
mbed_official 403:91a4bea587f4 5983 #define TSC_IOHCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 schmitt trigger hysteresis mode */
mbed_official 403:91a4bea587f4 5984 #define TSC_IOHCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 schmitt trigger hysteresis mode */
mbed_official 403:91a4bea587f4 5985 #define TSC_IOHCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 schmitt trigger hysteresis mode */
mbed_official 403:91a4bea587f4 5986 #define TSC_IOHCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 schmitt trigger hysteresis mode */
mbed_official 403:91a4bea587f4 5987 #define TSC_IOHCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 schmitt trigger hysteresis mode */
mbed_official 403:91a4bea587f4 5988 #define TSC_IOHCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 schmitt trigger hysteresis mode */
mbed_official 403:91a4bea587f4 5989 #define TSC_IOHCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 schmitt trigger hysteresis mode */
mbed_official 403:91a4bea587f4 5990 #define TSC_IOHCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 schmitt trigger hysteresis mode */
mbed_official 403:91a4bea587f4 5991 #define TSC_IOHCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 schmitt trigger hysteresis mode */
mbed_official 403:91a4bea587f4 5992 #define TSC_IOHCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 schmitt trigger hysteresis mode */
mbed_official 403:91a4bea587f4 5993 #define TSC_IOHCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 schmitt trigger hysteresis mode */
mbed_official 403:91a4bea587f4 5994 #define TSC_IOHCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 schmitt trigger hysteresis mode */
mbed_official 403:91a4bea587f4 5995 #define TSC_IOHCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 schmitt trigger hysteresis mode */
mbed_official 403:91a4bea587f4 5996 #define TSC_IOHCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 schmitt trigger hysteresis mode */
mbed_official 403:91a4bea587f4 5997 #define TSC_IOHCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 schmitt trigger hysteresis mode */
mbed_official 403:91a4bea587f4 5998 #define TSC_IOHCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 schmitt trigger hysteresis mode */
mbed_official 403:91a4bea587f4 5999 #define TSC_IOHCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 schmitt trigger hysteresis mode */
mbed_official 403:91a4bea587f4 6000 #define TSC_IOHCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 schmitt trigger hysteresis mode */
mbed_official 403:91a4bea587f4 6001 #define TSC_IOHCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 schmitt trigger hysteresis mode */
mbed_official 403:91a4bea587f4 6002 #define TSC_IOHCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 schmitt trigger hysteresis mode */
mbed_official 403:91a4bea587f4 6003
mbed_official 403:91a4bea587f4 6004 /******************* Bit definition for TSC_IOASCR register *****************/
mbed_official 403:91a4bea587f4 6005 #define TSC_IOASCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 analog switch enable */
mbed_official 403:91a4bea587f4 6006 #define TSC_IOASCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 analog switch enable */
mbed_official 403:91a4bea587f4 6007 #define TSC_IOASCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 analog switch enable */
mbed_official 403:91a4bea587f4 6008 #define TSC_IOASCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 analog switch enable */
mbed_official 403:91a4bea587f4 6009 #define TSC_IOASCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 analog switch enable */
mbed_official 403:91a4bea587f4 6010 #define TSC_IOASCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 analog switch enable */
mbed_official 403:91a4bea587f4 6011 #define TSC_IOASCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 analog switch enable */
mbed_official 403:91a4bea587f4 6012 #define TSC_IOASCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 analog switch enable */
mbed_official 403:91a4bea587f4 6013 #define TSC_IOASCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 analog switch enable */
mbed_official 403:91a4bea587f4 6014 #define TSC_IOASCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 analog switch enable */
mbed_official 403:91a4bea587f4 6015 #define TSC_IOASCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 analog switch enable */
mbed_official 403:91a4bea587f4 6016 #define TSC_IOASCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 analog switch enable */
mbed_official 403:91a4bea587f4 6017 #define TSC_IOASCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 analog switch enable */
mbed_official 403:91a4bea587f4 6018 #define TSC_IOASCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 analog switch enable */
mbed_official 403:91a4bea587f4 6019 #define TSC_IOASCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 analog switch enable */
mbed_official 403:91a4bea587f4 6020 #define TSC_IOASCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 analog switch enable */
mbed_official 403:91a4bea587f4 6021 #define TSC_IOASCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 analog switch enable */
mbed_official 403:91a4bea587f4 6022 #define TSC_IOASCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 analog switch enable */
mbed_official 403:91a4bea587f4 6023 #define TSC_IOASCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 analog switch enable */
mbed_official 403:91a4bea587f4 6024 #define TSC_IOASCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 analog switch enable */
mbed_official 403:91a4bea587f4 6025 #define TSC_IOASCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 analog switch enable */
mbed_official 403:91a4bea587f4 6026 #define TSC_IOASCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 analog switch enable */
mbed_official 403:91a4bea587f4 6027 #define TSC_IOASCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 analog switch enable */
mbed_official 403:91a4bea587f4 6028 #define TSC_IOASCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 analog switch enable */
mbed_official 403:91a4bea587f4 6029 #define TSC_IOASCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 analog switch enable */
mbed_official 403:91a4bea587f4 6030 #define TSC_IOASCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 analog switch enable */
mbed_official 403:91a4bea587f4 6031 #define TSC_IOASCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 analog switch enable */
mbed_official 403:91a4bea587f4 6032 #define TSC_IOASCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 analog switch enable */
mbed_official 403:91a4bea587f4 6033 #define TSC_IOASCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 analog switch enable */
mbed_official 403:91a4bea587f4 6034 #define TSC_IOASCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 analog switch enable */
mbed_official 403:91a4bea587f4 6035 #define TSC_IOASCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 analog switch enable */
mbed_official 403:91a4bea587f4 6036 #define TSC_IOASCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 analog switch enable */
mbed_official 403:91a4bea587f4 6037
mbed_official 403:91a4bea587f4 6038 /******************* Bit definition for TSC_IOSCR register ******************/
mbed_official 403:91a4bea587f4 6039 #define TSC_IOSCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 sampling mode */
mbed_official 403:91a4bea587f4 6040 #define TSC_IOSCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 sampling mode */
mbed_official 403:91a4bea587f4 6041 #define TSC_IOSCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 sampling mode */
mbed_official 403:91a4bea587f4 6042 #define TSC_IOSCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 sampling mode */
mbed_official 403:91a4bea587f4 6043 #define TSC_IOSCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 sampling mode */
mbed_official 403:91a4bea587f4 6044 #define TSC_IOSCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 sampling mode */
mbed_official 403:91a4bea587f4 6045 #define TSC_IOSCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 sampling mode */
mbed_official 403:91a4bea587f4 6046 #define TSC_IOSCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 sampling mode */
mbed_official 403:91a4bea587f4 6047 #define TSC_IOSCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 sampling mode */
mbed_official 403:91a4bea587f4 6048 #define TSC_IOSCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 sampling mode */
mbed_official 403:91a4bea587f4 6049 #define TSC_IOSCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 sampling mode */
mbed_official 403:91a4bea587f4 6050 #define TSC_IOSCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 sampling mode */
mbed_official 403:91a4bea587f4 6051 #define TSC_IOSCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 sampling mode */
mbed_official 403:91a4bea587f4 6052 #define TSC_IOSCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 sampling mode */
mbed_official 403:91a4bea587f4 6053 #define TSC_IOSCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 sampling mode */
mbed_official 403:91a4bea587f4 6054 #define TSC_IOSCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 sampling mode */
mbed_official 403:91a4bea587f4 6055 #define TSC_IOSCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 sampling mode */
mbed_official 403:91a4bea587f4 6056 #define TSC_IOSCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 sampling mode */
mbed_official 403:91a4bea587f4 6057 #define TSC_IOSCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 sampling mode */
mbed_official 403:91a4bea587f4 6058 #define TSC_IOSCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 sampling mode */
mbed_official 403:91a4bea587f4 6059 #define TSC_IOSCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 sampling mode */
mbed_official 403:91a4bea587f4 6060 #define TSC_IOSCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 sampling mode */
mbed_official 403:91a4bea587f4 6061 #define TSC_IOSCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 sampling mode */
mbed_official 403:91a4bea587f4 6062 #define TSC_IOSCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 sampling mode */
mbed_official 403:91a4bea587f4 6063 #define TSC_IOSCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 sampling mode */
mbed_official 403:91a4bea587f4 6064 #define TSC_IOSCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 sampling mode */
mbed_official 403:91a4bea587f4 6065 #define TSC_IOSCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 sampling mode */
mbed_official 403:91a4bea587f4 6066 #define TSC_IOSCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 sampling mode */
mbed_official 403:91a4bea587f4 6067 #define TSC_IOSCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 sampling mode */
mbed_official 403:91a4bea587f4 6068 #define TSC_IOSCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 sampling mode */
mbed_official 403:91a4bea587f4 6069 #define TSC_IOSCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 sampling mode */
mbed_official 403:91a4bea587f4 6070 #define TSC_IOSCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 sampling mode */
mbed_official 403:91a4bea587f4 6071
mbed_official 403:91a4bea587f4 6072 /******************* Bit definition for TSC_IOCCR register ******************/
mbed_official 403:91a4bea587f4 6073 #define TSC_IOCCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 channel mode */
mbed_official 403:91a4bea587f4 6074 #define TSC_IOCCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 channel mode */
mbed_official 403:91a4bea587f4 6075 #define TSC_IOCCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 channel mode */
mbed_official 403:91a4bea587f4 6076 #define TSC_IOCCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 channel mode */
mbed_official 403:91a4bea587f4 6077 #define TSC_IOCCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 channel mode */
mbed_official 403:91a4bea587f4 6078 #define TSC_IOCCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 channel mode */
mbed_official 403:91a4bea587f4 6079 #define TSC_IOCCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 channel mode */
mbed_official 403:91a4bea587f4 6080 #define TSC_IOCCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 channel mode */
mbed_official 403:91a4bea587f4 6081 #define TSC_IOCCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 channel mode */
mbed_official 403:91a4bea587f4 6082 #define TSC_IOCCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 channel mode */
mbed_official 403:91a4bea587f4 6083 #define TSC_IOCCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 channel mode */
mbed_official 403:91a4bea587f4 6084 #define TSC_IOCCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 channel mode */
mbed_official 403:91a4bea587f4 6085 #define TSC_IOCCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 channel mode */
mbed_official 403:91a4bea587f4 6086 #define TSC_IOCCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 channel mode */
mbed_official 403:91a4bea587f4 6087 #define TSC_IOCCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 channel mode */
mbed_official 403:91a4bea587f4 6088 #define TSC_IOCCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 channel mode */
mbed_official 403:91a4bea587f4 6089 #define TSC_IOCCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 channel mode */
mbed_official 403:91a4bea587f4 6090 #define TSC_IOCCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 channel mode */
mbed_official 403:91a4bea587f4 6091 #define TSC_IOCCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 channel mode */
mbed_official 403:91a4bea587f4 6092 #define TSC_IOCCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 channel mode */
mbed_official 403:91a4bea587f4 6093 #define TSC_IOCCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 channel mode */
mbed_official 403:91a4bea587f4 6094 #define TSC_IOCCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 channel mode */
mbed_official 403:91a4bea587f4 6095 #define TSC_IOCCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 channel mode */
mbed_official 403:91a4bea587f4 6096 #define TSC_IOCCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 channel mode */
mbed_official 403:91a4bea587f4 6097 #define TSC_IOCCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 channel mode */
mbed_official 403:91a4bea587f4 6098 #define TSC_IOCCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 channel mode */
mbed_official 403:91a4bea587f4 6099 #define TSC_IOCCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 channel mode */
mbed_official 403:91a4bea587f4 6100 #define TSC_IOCCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 channel mode */
mbed_official 403:91a4bea587f4 6101 #define TSC_IOCCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 channel mode */
mbed_official 403:91a4bea587f4 6102 #define TSC_IOCCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 channel mode */
mbed_official 403:91a4bea587f4 6103 #define TSC_IOCCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 channel mode */
mbed_official 403:91a4bea587f4 6104 #define TSC_IOCCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 channel mode */
mbed_official 403:91a4bea587f4 6105
mbed_official 403:91a4bea587f4 6106 /******************* Bit definition for TSC_IOGCSR register *****************/
mbed_official 403:91a4bea587f4 6107 #define TSC_IOGCSR_G1E ((uint32_t)0x00000001) /*!<Analog IO GROUP1 enable */
mbed_official 403:91a4bea587f4 6108 #define TSC_IOGCSR_G2E ((uint32_t)0x00000002) /*!<Analog IO GROUP2 enable */
mbed_official 403:91a4bea587f4 6109 #define TSC_IOGCSR_G3E ((uint32_t)0x00000004) /*!<Analog IO GROUP3 enable */
mbed_official 403:91a4bea587f4 6110 #define TSC_IOGCSR_G4E ((uint32_t)0x00000008) /*!<Analog IO GROUP4 enable */
mbed_official 403:91a4bea587f4 6111 #define TSC_IOGCSR_G5E ((uint32_t)0x00000010) /*!<Analog IO GROUP5 enable */
mbed_official 403:91a4bea587f4 6112 #define TSC_IOGCSR_G6E ((uint32_t)0x00000020) /*!<Analog IO GROUP6 enable */
mbed_official 403:91a4bea587f4 6113 #define TSC_IOGCSR_G7E ((uint32_t)0x00000040) /*!<Analog IO GROUP7 enable */
mbed_official 403:91a4bea587f4 6114 #define TSC_IOGCSR_G8E ((uint32_t)0x00000080) /*!<Analog IO GROUP8 enable */
mbed_official 403:91a4bea587f4 6115 #define TSC_IOGCSR_G1S ((uint32_t)0x00010000) /*!<Analog IO GROUP1 status */
mbed_official 403:91a4bea587f4 6116 #define TSC_IOGCSR_G2S ((uint32_t)0x00020000) /*!<Analog IO GROUP2 status */
mbed_official 403:91a4bea587f4 6117 #define TSC_IOGCSR_G3S ((uint32_t)0x00040000) /*!<Analog IO GROUP3 status */
mbed_official 403:91a4bea587f4 6118 #define TSC_IOGCSR_G4S ((uint32_t)0x00080000) /*!<Analog IO GROUP4 status */
mbed_official 403:91a4bea587f4 6119 #define TSC_IOGCSR_G5S ((uint32_t)0x00100000) /*!<Analog IO GROUP5 status */
mbed_official 403:91a4bea587f4 6120 #define TSC_IOGCSR_G6S ((uint32_t)0x00200000) /*!<Analog IO GROUP6 status */
mbed_official 403:91a4bea587f4 6121 #define TSC_IOGCSR_G7S ((uint32_t)0x00400000) /*!<Analog IO GROUP7 status */
mbed_official 403:91a4bea587f4 6122 #define TSC_IOGCSR_G8S ((uint32_t)0x00800000) /*!<Analog IO GROUP8 status */
mbed_official 403:91a4bea587f4 6123
mbed_official 403:91a4bea587f4 6124 /******************* Bit definition for TSC_IOGXCR register *****************/
mbed_official 403:91a4bea587f4 6125 #define TSC_IOGXCR_CNT ((uint32_t)0x00003FFF) /*!<CNT[13:0] bits (Counter value) */
mbed_official 403:91a4bea587f4 6126
mbed_official 403:91a4bea587f4 6127 /******************************************************************************/
mbed_official 403:91a4bea587f4 6128 /* */
mbed_official 403:91a4bea587f4 6129 /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
mbed_official 403:91a4bea587f4 6130 /* */
mbed_official 403:91a4bea587f4 6131 /******************************************************************************/
mbed_official 403:91a4bea587f4 6132 /****************** Bit definition for USART_CR1 register *******************/
mbed_official 403:91a4bea587f4 6133 #define USART_CR1_UE ((uint32_t)0x00000001) /*!< USART Enable */
mbed_official 403:91a4bea587f4 6134 #define USART_CR1_UESM ((uint32_t)0x00000002) /*!< USART Enable in STOP Mode */
mbed_official 403:91a4bea587f4 6135 #define USART_CR1_RE ((uint32_t)0x00000004) /*!< Receiver Enable */
mbed_official 403:91a4bea587f4 6136 #define USART_CR1_TE ((uint32_t)0x00000008) /*!< Transmitter Enable */
mbed_official 403:91a4bea587f4 6137 #define USART_CR1_IDLEIE ((uint32_t)0x00000010) /*!< IDLE Interrupt Enable */
mbed_official 403:91a4bea587f4 6138 #define USART_CR1_RXNEIE ((uint32_t)0x00000020) /*!< RXNE Interrupt Enable */
mbed_official 403:91a4bea587f4 6139 #define USART_CR1_TCIE ((uint32_t)0x00000040) /*!< Transmission Complete Interrupt Enable */
mbed_official 403:91a4bea587f4 6140 #define USART_CR1_TXEIE ((uint32_t)0x00000080) /*!< TXE Interrupt Enable */
mbed_official 403:91a4bea587f4 6141 #define USART_CR1_PEIE ((uint32_t)0x00000100) /*!< PE Interrupt Enable */
mbed_official 403:91a4bea587f4 6142 #define USART_CR1_PS ((uint32_t)0x00000200) /*!< Parity Selection */
mbed_official 403:91a4bea587f4 6143 #define USART_CR1_PCE ((uint32_t)0x00000400) /*!< Parity Control Enable */
mbed_official 403:91a4bea587f4 6144 #define USART_CR1_WAKE ((uint32_t)0x00000800) /*!< Receiver Wakeup method */
mbed_official 403:91a4bea587f4 6145 #define USART_CR1_M ((uint32_t)0x00001000) /*!< Word length */
mbed_official 403:91a4bea587f4 6146 #define USART_CR1_M0 ((uint32_t)0x00001000) /*!< SmartCard Word length */
mbed_official 403:91a4bea587f4 6147 #define USART_CR1_MME ((uint32_t)0x00002000) /*!< Mute Mode Enable */
mbed_official 403:91a4bea587f4 6148 #define USART_CR1_CMIE ((uint32_t)0x00004000) /*!< Character match interrupt enable */
mbed_official 403:91a4bea587f4 6149 #define USART_CR1_OVER8 ((uint32_t)0x00008000) /*!< Oversampling by 8-bit or 16-bit mode */
mbed_official 403:91a4bea587f4 6150 #define USART_CR1_DEDT ((uint32_t)0x001F0000) /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
mbed_official 403:91a4bea587f4 6151 #define USART_CR1_DEDT_0 ((uint32_t)0x00010000) /*!< Bit 0 */
mbed_official 403:91a4bea587f4 6152 #define USART_CR1_DEDT_1 ((uint32_t)0x00020000) /*!< Bit 1 */
mbed_official 403:91a4bea587f4 6153 #define USART_CR1_DEDT_2 ((uint32_t)0x00040000) /*!< Bit 2 */
mbed_official 403:91a4bea587f4 6154 #define USART_CR1_DEDT_3 ((uint32_t)0x00080000) /*!< Bit 3 */
mbed_official 403:91a4bea587f4 6155 #define USART_CR1_DEDT_4 ((uint32_t)0x00100000) /*!< Bit 4 */
mbed_official 403:91a4bea587f4 6156 #define USART_CR1_DEAT ((uint32_t)0x03E00000) /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
mbed_official 403:91a4bea587f4 6157 #define USART_CR1_DEAT_0 ((uint32_t)0x00200000) /*!< Bit 0 */
mbed_official 403:91a4bea587f4 6158 #define USART_CR1_DEAT_1 ((uint32_t)0x00400000) /*!< Bit 1 */
mbed_official 403:91a4bea587f4 6159 #define USART_CR1_DEAT_2 ((uint32_t)0x00800000) /*!< Bit 2 */
mbed_official 403:91a4bea587f4 6160 #define USART_CR1_DEAT_3 ((uint32_t)0x01000000) /*!< Bit 3 */
mbed_official 403:91a4bea587f4 6161 #define USART_CR1_DEAT_4 ((uint32_t)0x02000000) /*!< Bit 4 */
mbed_official 403:91a4bea587f4 6162 #define USART_CR1_RTOIE ((uint32_t)0x04000000) /*!< Receive Time Out interrupt enable */
mbed_official 403:91a4bea587f4 6163 #define USART_CR1_EOBIE ((uint32_t)0x08000000) /*!< End of Block interrupt enable */
mbed_official 403:91a4bea587f4 6164
mbed_official 403:91a4bea587f4 6165 /****************** Bit definition for USART_CR2 register *******************/
mbed_official 403:91a4bea587f4 6166 #define USART_CR2_ADDM7 ((uint32_t)0x00000010) /*!< 7-bit or 4-bit Address Detection */
mbed_official 403:91a4bea587f4 6167 #define USART_CR2_LBDL ((uint32_t)0x00000020) /*!< LIN Break Detection Length */
mbed_official 403:91a4bea587f4 6168 #define USART_CR2_LBDIE ((uint32_t)0x00000040) /*!< LIN Break Detection Interrupt Enable */
mbed_official 403:91a4bea587f4 6169 #define USART_CR2_LBCL ((uint32_t)0x00000100) /*!< Last Bit Clock pulse */
mbed_official 403:91a4bea587f4 6170 #define USART_CR2_CPHA ((uint32_t)0x00000200) /*!< Clock Phase */
mbed_official 403:91a4bea587f4 6171 #define USART_CR2_CPOL ((uint32_t)0x00000400) /*!< Clock Polarity */
mbed_official 403:91a4bea587f4 6172 #define USART_CR2_CLKEN ((uint32_t)0x00000800) /*!< Clock Enable */
mbed_official 403:91a4bea587f4 6173 #define USART_CR2_STOP ((uint32_t)0x00003000) /*!< STOP[1:0] bits (STOP bits) */
mbed_official 403:91a4bea587f4 6174 #define USART_CR2_STOP_0 ((uint32_t)0x00001000) /*!< Bit 0 */
mbed_official 403:91a4bea587f4 6175 #define USART_CR2_STOP_1 ((uint32_t)0x00002000) /*!< Bit 1 */
mbed_official 403:91a4bea587f4 6176 #define USART_CR2_LINEN ((uint32_t)0x00004000) /*!< LIN mode enable */
mbed_official 403:91a4bea587f4 6177 #define USART_CR2_SWAP ((uint32_t)0x00008000) /*!< SWAP TX/RX pins */
mbed_official 403:91a4bea587f4 6178 #define USART_CR2_RXINV ((uint32_t)0x00010000) /*!< RX pin active level inversion */
mbed_official 403:91a4bea587f4 6179 #define USART_CR2_TXINV ((uint32_t)0x00020000) /*!< TX pin active level inversion */
mbed_official 403:91a4bea587f4 6180 #define USART_CR2_DATAINV ((uint32_t)0x00040000) /*!< Binary data inversion */
mbed_official 403:91a4bea587f4 6181 #define USART_CR2_MSBFIRST ((uint32_t)0x00080000) /*!< Most Significant Bit First */
mbed_official 403:91a4bea587f4 6182 #define USART_CR2_ABREN ((uint32_t)0x00100000) /*!< Auto Baud-Rate Enable*/
mbed_official 403:91a4bea587f4 6183 #define USART_CR2_ABRMODE ((uint32_t)0x00600000) /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
mbed_official 403:91a4bea587f4 6184 #define USART_CR2_ABRMODE_0 ((uint32_t)0x00200000) /*!< Bit 0 */
mbed_official 403:91a4bea587f4 6185 #define USART_CR2_ABRMODE_1 ((uint32_t)0x00400000) /*!< Bit 1 */
mbed_official 403:91a4bea587f4 6186 #define USART_CR2_RTOEN ((uint32_t)0x00800000) /*!< Receiver Time-Out enable */
mbed_official 403:91a4bea587f4 6187 #define USART_CR2_ADD ((uint32_t)0xFF000000) /*!< Address of the USART node */
mbed_official 403:91a4bea587f4 6188
mbed_official 403:91a4bea587f4 6189 /****************** Bit definition for USART_CR3 register *******************/
mbed_official 403:91a4bea587f4 6190 #define USART_CR3_EIE ((uint32_t)0x00000001) /*!< Error Interrupt Enable */
mbed_official 403:91a4bea587f4 6191 #define USART_CR3_IREN ((uint32_t)0x00000002) /*!< IrDA mode Enable */
mbed_official 403:91a4bea587f4 6192 #define USART_CR3_IRLP ((uint32_t)0x00000004) /*!< IrDA Low-Power */
mbed_official 403:91a4bea587f4 6193 #define USART_CR3_HDSEL ((uint32_t)0x00000008) /*!< Half-Duplex Selection */
mbed_official 403:91a4bea587f4 6194 #define USART_CR3_NACK ((uint32_t)0x00000010) /*!< SmartCard NACK enable */
mbed_official 403:91a4bea587f4 6195 #define USART_CR3_SCEN ((uint32_t)0x00000020) /*!< SmartCard mode enable */
mbed_official 403:91a4bea587f4 6196 #define USART_CR3_DMAR ((uint32_t)0x00000040) /*!< DMA Enable Receiver */
mbed_official 403:91a4bea587f4 6197 #define USART_CR3_DMAT ((uint32_t)0x00000080) /*!< DMA Enable Transmitter */
mbed_official 403:91a4bea587f4 6198 #define USART_CR3_RTSE ((uint32_t)0x00000100) /*!< RTS Enable */
mbed_official 403:91a4bea587f4 6199 #define USART_CR3_CTSE ((uint32_t)0x00000200) /*!< CTS Enable */
mbed_official 403:91a4bea587f4 6200 #define USART_CR3_CTSIE ((uint32_t)0x00000400) /*!< CTS Interrupt Enable */
mbed_official 403:91a4bea587f4 6201 #define USART_CR3_ONEBIT ((uint32_t)0x00000800) /*!< One sample bit method enable */
mbed_official 403:91a4bea587f4 6202 #define USART_CR3_OVRDIS ((uint32_t)0x00001000) /*!< Overrun Disable */
mbed_official 403:91a4bea587f4 6203 #define USART_CR3_DDRE ((uint32_t)0x00002000) /*!< DMA Disable on Reception Error */
mbed_official 403:91a4bea587f4 6204 #define USART_CR3_DEM ((uint32_t)0x00004000) /*!< Driver Enable Mode */
mbed_official 403:91a4bea587f4 6205 #define USART_CR3_DEP ((uint32_t)0x00008000) /*!< Driver Enable Polarity Selection */
mbed_official 403:91a4bea587f4 6206 #define USART_CR3_SCARCNT ((uint32_t)0x000E0000) /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
mbed_official 403:91a4bea587f4 6207 #define USART_CR3_SCARCNT_0 ((uint32_t)0x00020000) /*!< Bit 0 */
mbed_official 403:91a4bea587f4 6208 #define USART_CR3_SCARCNT_1 ((uint32_t)0x00040000) /*!< Bit 1 */
mbed_official 403:91a4bea587f4 6209 #define USART_CR3_SCARCNT_2 ((uint32_t)0x00080000) /*!< Bit 2 */
mbed_official 403:91a4bea587f4 6210 #define USART_CR3_WUS ((uint32_t)0x00300000) /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
mbed_official 403:91a4bea587f4 6211 #define USART_CR3_WUS_0 ((uint32_t)0x00100000) /*!< Bit 0 */
mbed_official 403:91a4bea587f4 6212 #define USART_CR3_WUS_1 ((uint32_t)0x00200000) /*!< Bit 1 */
mbed_official 403:91a4bea587f4 6213 #define USART_CR3_WUFIE ((uint32_t)0x00400000) /*!< Wake Up Interrupt Enable */
mbed_official 403:91a4bea587f4 6214
mbed_official 403:91a4bea587f4 6215 /****************** Bit definition for USART_BRR register *******************/
mbed_official 403:91a4bea587f4 6216 #define USART_BRR_DIV_FRACTION ((uint32_t)0x0000000F) /*!< Fraction of USARTDIV */
mbed_official 403:91a4bea587f4 6217 #define USART_BRR_DIV_MANTISSA ((uint32_t)0x0000FFF0) /*!< Mantissa of USARTDIV */
mbed_official 403:91a4bea587f4 6218
mbed_official 403:91a4bea587f4 6219 /****************** Bit definition for USART_GTPR register ******************/
mbed_official 403:91a4bea587f4 6220 #define USART_GTPR_PSC ((uint32_t)0x000000FF) /*!< PSC[7:0] bits (Prescaler value) */
mbed_official 403:91a4bea587f4 6221 #define USART_GTPR_GT ((uint32_t)0x0000FF00) /*!< GT[7:0] bits (Guard time value) */
mbed_official 403:91a4bea587f4 6222
mbed_official 403:91a4bea587f4 6223
mbed_official 403:91a4bea587f4 6224 /******************* Bit definition for USART_RTOR register *****************/
mbed_official 403:91a4bea587f4 6225 #define USART_RTOR_RTO ((uint32_t)0x00FFFFFF) /*!< Receiver Time Out Value */
mbed_official 403:91a4bea587f4 6226 #define USART_RTOR_BLEN ((uint32_t)0xFF000000) /*!< Block Length */
mbed_official 403:91a4bea587f4 6227
mbed_official 403:91a4bea587f4 6228 /******************* Bit definition for USART_RQR register ******************/
mbed_official 403:91a4bea587f4 6229 #define USART_RQR_ABRRQ ((uint32_t)0x00000001) /*!< Auto-Baud Rate Request */
mbed_official 403:91a4bea587f4 6230 #define USART_RQR_SBKRQ ((uint32_t)0x00000002) /*!< Send Break Request */
mbed_official 403:91a4bea587f4 6231 #define USART_RQR_MMRQ ((uint32_t)0x00000004) /*!< Mute Mode Request */
mbed_official 403:91a4bea587f4 6232 #define USART_RQR_RXFRQ ((uint32_t)0x00000008) /*!< Receive Data flush Request */
mbed_official 403:91a4bea587f4 6233 #define USART_RQR_TXFRQ ((uint32_t)0x00000010) /*!< Transmit data flush Request */
mbed_official 403:91a4bea587f4 6234
mbed_official 403:91a4bea587f4 6235 /******************* Bit definition for USART_ISR register ******************/
mbed_official 403:91a4bea587f4 6236 #define USART_ISR_PE ((uint32_t)0x00000001) /*!< Parity Error */
mbed_official 403:91a4bea587f4 6237 #define USART_ISR_FE ((uint32_t)0x00000002) /*!< Framing Error */
mbed_official 403:91a4bea587f4 6238 #define USART_ISR_NE ((uint32_t)0x00000004) /*!< Noise detected Flag */
mbed_official 403:91a4bea587f4 6239 #define USART_ISR_ORE ((uint32_t)0x00000008) /*!< OverRun Error */
mbed_official 403:91a4bea587f4 6240 #define USART_ISR_IDLE ((uint32_t)0x00000010) /*!< IDLE line detected */
mbed_official 403:91a4bea587f4 6241 #define USART_ISR_RXNE ((uint32_t)0x00000020) /*!< Read Data Register Not Empty */
mbed_official 403:91a4bea587f4 6242 #define USART_ISR_TC ((uint32_t)0x00000040) /*!< Transmission Complete */
mbed_official 403:91a4bea587f4 6243 #define USART_ISR_TXE ((uint32_t)0x00000080) /*!< Transmit Data Register Empty */
mbed_official 403:91a4bea587f4 6244 #define USART_ISR_LBDF ((uint32_t)0x00000100) /*!< LIN Break Detection Flag */
mbed_official 403:91a4bea587f4 6245 #define USART_ISR_CTSIF ((uint32_t)0x00000200) /*!< CTS interrupt flag */
mbed_official 403:91a4bea587f4 6246 #define USART_ISR_CTS ((uint32_t)0x00000400) /*!< CTS flag */
mbed_official 403:91a4bea587f4 6247 #define USART_ISR_RTOF ((uint32_t)0x00000800) /*!< Receiver Time Out */
mbed_official 403:91a4bea587f4 6248 #define USART_ISR_EOBF ((uint32_t)0x00001000) /*!< End Of Block Flag */
mbed_official 403:91a4bea587f4 6249 #define USART_ISR_ABRE ((uint32_t)0x00004000) /*!< Auto-Baud Rate Error */
mbed_official 403:91a4bea587f4 6250 #define USART_ISR_ABRF ((uint32_t)0x00008000) /*!< Auto-Baud Rate Flag */
mbed_official 403:91a4bea587f4 6251 #define USART_ISR_BUSY ((uint32_t)0x00010000) /*!< Busy Flag */
mbed_official 403:91a4bea587f4 6252 #define USART_ISR_CMF ((uint32_t)0x00020000) /*!< Character Match Flag */
mbed_official 403:91a4bea587f4 6253 #define USART_ISR_SBKF ((uint32_t)0x00040000) /*!< Send Break Flag */
mbed_official 403:91a4bea587f4 6254 #define USART_ISR_RWU ((uint32_t)0x00080000) /*!< Receive Wake Up from mute mode Flag */
mbed_official 403:91a4bea587f4 6255 #define USART_ISR_WUF ((uint32_t)0x00100000) /*!< Wake Up from stop mode Flag */
mbed_official 403:91a4bea587f4 6256 #define USART_ISR_TEACK ((uint32_t)0x00200000) /*!< Transmit Enable Acknowledge Flag */
mbed_official 403:91a4bea587f4 6257 #define USART_ISR_REACK ((uint32_t)0x00400000) /*!< Receive Enable Acknowledge Flag */
mbed_official 403:91a4bea587f4 6258
mbed_official 403:91a4bea587f4 6259 /******************* Bit definition for USART_ICR register ******************/
mbed_official 403:91a4bea587f4 6260 #define USART_ICR_PECF ((uint32_t)0x00000001) /*!< Parity Error Clear Flag */
mbed_official 403:91a4bea587f4 6261 #define USART_ICR_FECF ((uint32_t)0x00000002) /*!< Framing Error Clear Flag */
mbed_official 403:91a4bea587f4 6262 #define USART_ICR_NCF ((uint32_t)0x00000004) /*!< Noise detected Clear Flag */
mbed_official 403:91a4bea587f4 6263 #define USART_ICR_ORECF ((uint32_t)0x00000008) /*!< OverRun Error Clear Flag */
mbed_official 403:91a4bea587f4 6264 #define USART_ICR_IDLECF ((uint32_t)0x00000010) /*!< IDLE line detected Clear Flag */
mbed_official 403:91a4bea587f4 6265 #define USART_ICR_TCCF ((uint32_t)0x00000040) /*!< Transmission Complete Clear Flag */
mbed_official 403:91a4bea587f4 6266 #define USART_ICR_LBDCF ((uint32_t)0x00000100) /*!< LIN Break Detection Clear Flag */
mbed_official 403:91a4bea587f4 6267 #define USART_ICR_CTSCF ((uint32_t)0x00000200) /*!< CTS Interrupt Clear Flag */
mbed_official 403:91a4bea587f4 6268 #define USART_ICR_RTOCF ((uint32_t)0x00000800) /*!< Receiver Time Out Clear Flag */
mbed_official 403:91a4bea587f4 6269 #define USART_ICR_EOBCF ((uint32_t)0x00001000) /*!< End Of Block Clear Flag */
mbed_official 403:91a4bea587f4 6270 #define USART_ICR_CMCF ((uint32_t)0x00020000) /*!< Character Match Clear Flag */
mbed_official 403:91a4bea587f4 6271 #define USART_ICR_WUCF ((uint32_t)0x00100000) /*!< Wake Up from stop mode Clear Flag */
mbed_official 403:91a4bea587f4 6272
mbed_official 403:91a4bea587f4 6273 /******************* Bit definition for USART_RDR register ******************/
mbed_official 403:91a4bea587f4 6274 #define USART_RDR_RDR ((uint32_t)0x000001FF) /*!< RDR[8:0] bits (Receive Data value) */
mbed_official 403:91a4bea587f4 6275
mbed_official 403:91a4bea587f4 6276 /******************* Bit definition for USART_TDR register ******************/
mbed_official 403:91a4bea587f4 6277 #define USART_TDR_TDR ((uint32_t)0x000001FF) /*!< TDR[8:0] bits (Transmit Data value) */
mbed_official 403:91a4bea587f4 6278
mbed_official 403:91a4bea587f4 6279 /******************************************************************************/
mbed_official 403:91a4bea587f4 6280 /* */
mbed_official 403:91a4bea587f4 6281 /* USB Device General registers */
mbed_official 403:91a4bea587f4 6282 /* */
mbed_official 403:91a4bea587f4 6283 /******************************************************************************/
mbed_official 403:91a4bea587f4 6284 #define USB_CNTR (USB_BASE + 0x40) /*!< Control register */
mbed_official 403:91a4bea587f4 6285 #define USB_ISTR (USB_BASE + 0x44) /*!< Interrupt status register */
mbed_official 403:91a4bea587f4 6286 #define USB_FNR (USB_BASE + 0x48) /*!< Frame number register */
mbed_official 403:91a4bea587f4 6287 #define USB_DADDR (USB_BASE + 0x4C) /*!< Device address register */
mbed_official 403:91a4bea587f4 6288 #define USB_BTABLE (USB_BASE + 0x50) /*!< Buffer Table address register */
mbed_official 403:91a4bea587f4 6289
mbed_official 403:91a4bea587f4 6290 /**************************** ISTR interrupt events *************************/
mbed_official 403:91a4bea587f4 6291 #define USB_ISTR_CTR ((uint16_t)0x8000) /*!< Correct TRansfer (clear-only bit) */
mbed_official 403:91a4bea587f4 6292 #define USB_ISTR_PMAOVRM ((uint16_t)0x4000) /*!< DMA OVeR/underrun (clear-only bit) */
mbed_official 403:91a4bea587f4 6293 #define USB_ISTR_ERR ((uint16_t)0x2000) /*!< ERRor (clear-only bit) */
mbed_official 403:91a4bea587f4 6294 #define USB_ISTR_WKUP ((uint16_t)0x1000) /*!< WaKe UP (clear-only bit) */
mbed_official 403:91a4bea587f4 6295 #define USB_ISTR_SUSP ((uint16_t)0x0800) /*!< SUSPend (clear-only bit) */
mbed_official 403:91a4bea587f4 6296 #define USB_ISTR_RESET ((uint16_t)0x0400) /*!< RESET (clear-only bit) */
mbed_official 403:91a4bea587f4 6297 #define USB_ISTR_SOF ((uint16_t)0x0200) /*!< Start Of Frame (clear-only bit) */
mbed_official 403:91a4bea587f4 6298 #define USB_ISTR_ESOF ((uint16_t)0x0100) /*!< Expected Start Of Frame (clear-only bit) */
mbed_official 403:91a4bea587f4 6299 #define USB_ISTR_DIR ((uint16_t)0x0010) /*!< DIRection of transaction (read-only bit) */
mbed_official 403:91a4bea587f4 6300 #define USB_ISTR_EP_ID ((uint16_t)0x000F) /*!< EndPoint IDentifier (read-only bit) */
mbed_official 403:91a4bea587f4 6301
mbed_official 403:91a4bea587f4 6302 #define USB_CLR_CTR (~USB_ISTR_CTR) /*!< clear Correct TRansfer bit */
mbed_official 403:91a4bea587f4 6303 #define USB_CLR_PMAOVRM (~USB_ISTR_PMAOVR) /*!< clear DMA OVeR/underrun bit*/
mbed_official 403:91a4bea587f4 6304 #define USB_CLR_ERR (~USB_ISTR_ERR) /*!< clear ERRor bit */
mbed_official 403:91a4bea587f4 6305 #define USB_CLR_WKUP (~USB_ISTR_WKUP) /*!< clear WaKe UP bit */
mbed_official 403:91a4bea587f4 6306 #define USB_CLR_SUSP (~USB_ISTR_SUSP) /*!< clear SUSPend bit */
mbed_official 403:91a4bea587f4 6307 #define USB_CLR_RESET (~USB_ISTR_RESET) /*!< clear RESET bit */
mbed_official 403:91a4bea587f4 6308 #define USB_CLR_SOF (~USB_ISTR_SOF) /*!< clear Start Of Frame bit */
mbed_official 403:91a4bea587f4 6309 #define USB_CLR_ESOF (~USB_ISTR_ESOF) /*!< clear Expected Start Of Frame bit */
mbed_official 403:91a4bea587f4 6310
mbed_official 403:91a4bea587f4 6311 /************************* CNTR control register bits definitions ***********/
mbed_official 403:91a4bea587f4 6312 #define USB_CNTR_CTRM ((uint16_t)0x8000) /*!< Correct TRansfer Mask */
mbed_official 403:91a4bea587f4 6313 #define USB_CNTR_PMAOVRM ((uint16_t)0x4000) /*!< DMA OVeR/underrun Mask */
mbed_official 403:91a4bea587f4 6314 #define USB_CNTR_ERRM ((uint16_t)0x2000) /*!< ERRor Mask */
mbed_official 403:91a4bea587f4 6315 #define USB_CNTR_WKUPM ((uint16_t)0x1000) /*!< WaKe UP Mask */
mbed_official 403:91a4bea587f4 6316 #define USB_CNTR_SUSPM ((uint16_t)0x0800) /*!< SUSPend Mask */
mbed_official 403:91a4bea587f4 6317 #define USB_CNTR_RESETM ((uint16_t)0x0400) /*!< RESET Mask */
mbed_official 403:91a4bea587f4 6318 #define USB_CNTR_SOFM ((uint16_t)0x0200) /*!< Start Of Frame Mask */
mbed_official 403:91a4bea587f4 6319 #define USB_CNTR_ESOFM ((uint16_t)0x0100) /*!< Expected Start Of Frame Mask */
mbed_official 403:91a4bea587f4 6320 #define USB_CNTR_RESUME ((uint16_t)0x0010) /*!< RESUME request */
mbed_official 403:91a4bea587f4 6321 #define USB_CNTR_FSUSP ((uint16_t)0x0008) /*!< Force SUSPend */
mbed_official 403:91a4bea587f4 6322 #define USB_CNTR_LP_MODE ((uint16_t)0x0004) /*!< Low-power MODE */
mbed_official 403:91a4bea587f4 6323 #define USB_CNTR_PDWN ((uint16_t)0x0002) /*!< Power DoWN */
mbed_official 403:91a4bea587f4 6324 #define USB_CNTR_FRES ((uint16_t)0x0001) /*!< Force USB RESet */
mbed_official 403:91a4bea587f4 6325
mbed_official 403:91a4bea587f4 6326 /******************** FNR Frame Number Register bit definitions ************/
mbed_official 403:91a4bea587f4 6327 #define USB_FNR_RXDP ((uint16_t)0x8000) /*!< status of D+ data line */
mbed_official 403:91a4bea587f4 6328 #define USB_FNR_RXDM ((uint16_t)0x4000) /*!< status of D- data line */
mbed_official 403:91a4bea587f4 6329 #define USB_FNR_LCK ((uint16_t)0x2000) /*!< LoCKed */
mbed_official 403:91a4bea587f4 6330 #define USB_FNR_LSOF ((uint16_t)0x1800) /*!< Lost SOF */
mbed_official 403:91a4bea587f4 6331 #define USB_FNR_FN ((uint16_t)0x07FF) /*!< Frame Number */
mbed_official 403:91a4bea587f4 6332
mbed_official 403:91a4bea587f4 6333 /******************** DADDR Device ADDRess bit definitions ****************/
mbed_official 403:91a4bea587f4 6334 #define USB_DADDR_EF ((uint8_t)0x80) /*!< USB device address Enable Function */
mbed_official 403:91a4bea587f4 6335 #define USB_DADDR_ADD ((uint8_t)0x7F) /*!< USB device address */
mbed_official 403:91a4bea587f4 6336
mbed_official 403:91a4bea587f4 6337 /****************************** Endpoint register *************************/
mbed_official 403:91a4bea587f4 6338 #define USB_EP0R USB_BASE /*!< endpoint 0 register address */
mbed_official 403:91a4bea587f4 6339 #define USB_EP1R (USB_BASE + 0x04) /*!< endpoint 1 register address */
mbed_official 403:91a4bea587f4 6340 #define USB_EP2R (USB_BASE + 0x08) /*!< endpoint 2 register address */
mbed_official 403:91a4bea587f4 6341 #define USB_EP3R (USB_BASE + 0x0C) /*!< endpoint 3 register address */
mbed_official 403:91a4bea587f4 6342 #define USB_EP4R (USB_BASE + 0x10) /*!< endpoint 4 register address */
mbed_official 403:91a4bea587f4 6343 #define USB_EP5R (USB_BASE + 0x14) /*!< endpoint 5 register address */
mbed_official 403:91a4bea587f4 6344 #define USB_EP6R (USB_BASE + 0x18) /*!< endpoint 6 register address */
mbed_official 403:91a4bea587f4 6345 #define USB_EP7R (USB_BASE + 0x1C) /*!< endpoint 7 register address */
mbed_official 403:91a4bea587f4 6346 /* bit positions */
mbed_official 403:91a4bea587f4 6347 #define USB_EP_CTR_RX ((uint16_t)0x8000) /*!< EndPoint Correct TRansfer RX */
mbed_official 403:91a4bea587f4 6348 #define USB_EP_DTOG_RX ((uint16_t)0x4000) /*!< EndPoint Data TOGGLE RX */
mbed_official 403:91a4bea587f4 6349 #define USB_EPRX_STAT ((uint16_t)0x3000) /*!< EndPoint RX STATus bit field */
mbed_official 403:91a4bea587f4 6350 #define USB_EP_SETUP ((uint16_t)0x0800) /*!< EndPoint SETUP */
mbed_official 403:91a4bea587f4 6351 #define USB_EP_T_FIELD ((uint16_t)0x0600) /*!< EndPoint TYPE */
mbed_official 403:91a4bea587f4 6352 #define USB_EP_KIND ((uint16_t)0x0100) /*!< EndPoint KIND */
mbed_official 403:91a4bea587f4 6353 #define USB_EP_CTR_TX ((uint16_t)0x0080) /*!< EndPoint Correct TRansfer TX */
mbed_official 403:91a4bea587f4 6354 #define USB_EP_DTOG_TX ((uint16_t)0x0040) /*!< EndPoint Data TOGGLE TX */
mbed_official 403:91a4bea587f4 6355 #define USB_EPTX_STAT ((uint16_t)0x0030) /*!< EndPoint TX STATus bit field */
mbed_official 403:91a4bea587f4 6356 #define USB_EPADDR_FIELD ((uint16_t)0x000F) /*!< EndPoint ADDRess FIELD */
mbed_official 403:91a4bea587f4 6357
mbed_official 403:91a4bea587f4 6358 /* EndPoint REGister MASK (no toggle fields) */
mbed_official 403:91a4bea587f4 6359 #define USB_EPREG_MASK (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
mbed_official 403:91a4bea587f4 6360 /*!< EP_TYPE[1:0] EndPoint TYPE */
mbed_official 403:91a4bea587f4 6361 #define USB_EP_TYPE_MASK ((uint16_t)0x0600) /*!< EndPoint TYPE Mask */
mbed_official 403:91a4bea587f4 6362 #define USB_EP_BULK ((uint16_t)0x0000) /*!< EndPoint BULK */
mbed_official 403:91a4bea587f4 6363 #define USB_EP_CONTROL ((uint16_t)0x0200) /*!< EndPoint CONTROL */
mbed_official 403:91a4bea587f4 6364 #define USB_EP_ISOCHRONOUS ((uint16_t)0x0400) /*!< EndPoint ISOCHRONOUS */
mbed_official 403:91a4bea587f4 6365 #define USB_EP_INTERRUPT ((uint16_t)0x0600) /*!< EndPoint INTERRUPT */
mbed_official 403:91a4bea587f4 6366 #define USB_EP_T_MASK (~USB_EP_T_FIELD & USB_EPREG_MASK)
mbed_official 403:91a4bea587f4 6367
mbed_official 403:91a4bea587f4 6368 #define USB_EPKIND_MASK (~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
mbed_official 403:91a4bea587f4 6369 /*!< STAT_TX[1:0] STATus for TX transfer */
mbed_official 403:91a4bea587f4 6370 #define USB_EP_TX_DIS ((uint16_t)0x0000) /*!< EndPoint TX DISabled */
mbed_official 403:91a4bea587f4 6371 #define USB_EP_TX_STALL ((uint16_t)0x0010) /*!< EndPoint TX STALLed */
mbed_official 403:91a4bea587f4 6372 #define USB_EP_TX_NAK ((uint16_t)0x0020) /*!< EndPoint TX NAKed */
mbed_official 403:91a4bea587f4 6373 #define USB_EP_TX_VALID ((uint16_t)0x0030) /*!< EndPoint TX VALID */
mbed_official 403:91a4bea587f4 6374 #define USB_EPTX_DTOG1 ((uint16_t)0x0010) /*!< EndPoint TX Data TOGgle bit1 */
mbed_official 403:91a4bea587f4 6375 #define USB_EPTX_DTOG2 ((uint16_t)0x0020) /*!< EndPoint TX Data TOGgle bit2 */
mbed_official 403:91a4bea587f4 6376 #define USB_EPTX_DTOGMASK (USB_EPTX_STAT|USB_EPREG_MASK)
mbed_official 403:91a4bea587f4 6377 /*!< STAT_RX[1:0] STATus for RX transfer */
mbed_official 403:91a4bea587f4 6378 #define USB_EP_RX_DIS ((uint16_t)0x0000) /*!< EndPoint RX DISabled */
mbed_official 403:91a4bea587f4 6379 #define USB_EP_RX_STALL ((uint16_t)0x1000) /*!< EndPoint RX STALLed */
mbed_official 403:91a4bea587f4 6380 #define USB_EP_RX_NAK ((uint16_t)0x2000) /*!< EndPoint RX NAKed */
mbed_official 403:91a4bea587f4 6381 #define USB_EP_RX_VALID ((uint16_t)0x3000) /*!< EndPoint RX VALID */
mbed_official 403:91a4bea587f4 6382 #define USB_EPRX_DTOG1 ((uint16_t)0x1000) /*!< EndPoint RX Data TOGgle bit1 */
mbed_official 403:91a4bea587f4 6383 #define USB_EPRX_DTOG2 ((uint16_t)0x2000) /*!< EndPoint RX Data TOGgle bit1 */
mbed_official 403:91a4bea587f4 6384 #define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK)
mbed_official 403:91a4bea587f4 6385
mbed_official 403:91a4bea587f4 6386 /******************************************************************************/
mbed_official 403:91a4bea587f4 6387 /* */
mbed_official 403:91a4bea587f4 6388 /* Window WATCHDOG */
mbed_official 403:91a4bea587f4 6389 /* */
mbed_official 403:91a4bea587f4 6390 /******************************************************************************/
mbed_official 403:91a4bea587f4 6391 /******************* Bit definition for WWDG_CR register ********************/
mbed_official 403:91a4bea587f4 6392 #define WWDG_CR_T ((uint32_t)0x0000007F) /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
mbed_official 403:91a4bea587f4 6393 #define WWDG_CR_T0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 403:91a4bea587f4 6394 #define WWDG_CR_T1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 403:91a4bea587f4 6395 #define WWDG_CR_T2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 403:91a4bea587f4 6396 #define WWDG_CR_T3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 403:91a4bea587f4 6397 #define WWDG_CR_T4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 403:91a4bea587f4 6398 #define WWDG_CR_T5 ((uint32_t)0x00000020) /*!<Bit 5 */
mbed_official 403:91a4bea587f4 6399 #define WWDG_CR_T6 ((uint32_t)0x00000040) /*!<Bit 6 */
mbed_official 403:91a4bea587f4 6400
mbed_official 403:91a4bea587f4 6401 #define WWDG_CR_WDGA ((uint32_t)0x00000080) /*!<Activation bit */
mbed_official 403:91a4bea587f4 6402
mbed_official 403:91a4bea587f4 6403 /******************* Bit definition for WWDG_CFR register *******************/
mbed_official 403:91a4bea587f4 6404 #define WWDG_CFR_W ((uint32_t)0x0000007F) /*!<W[6:0] bits (7-bit window value) */
mbed_official 403:91a4bea587f4 6405 #define WWDG_CFR_W0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 403:91a4bea587f4 6406 #define WWDG_CFR_W1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 403:91a4bea587f4 6407 #define WWDG_CFR_W2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 403:91a4bea587f4 6408 #define WWDG_CFR_W3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 403:91a4bea587f4 6409 #define WWDG_CFR_W4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 403:91a4bea587f4 6410 #define WWDG_CFR_W5 ((uint32_t)0x00000020) /*!<Bit 5 */
mbed_official 403:91a4bea587f4 6411 #define WWDG_CFR_W6 ((uint32_t)0x00000040) /*!<Bit 6 */
mbed_official 403:91a4bea587f4 6412
mbed_official 403:91a4bea587f4 6413 #define WWDG_CFR_WDGTB ((uint32_t)0x00000180) /*!<WDGTB[1:0] bits (Timer Base) */
mbed_official 403:91a4bea587f4 6414 #define WWDG_CFR_WDGTB0 ((uint32_t)0x00000080) /*!<Bit 0 */
mbed_official 403:91a4bea587f4 6415 #define WWDG_CFR_WDGTB1 ((uint32_t)0x00000100) /*!<Bit 1 */
mbed_official 403:91a4bea587f4 6416
mbed_official 403:91a4bea587f4 6417 #define WWDG_CFR_EWI ((uint32_t)0x00000200) /*!<Early Wakeup Interrupt */
mbed_official 403:91a4bea587f4 6418
mbed_official 403:91a4bea587f4 6419 /******************* Bit definition for WWDG_SR register ********************/
mbed_official 403:91a4bea587f4 6420 #define WWDG_SR_EWIF ((uint32_t)0x00000001) /*!<Early Wakeup Interrupt Flag */
mbed_official 403:91a4bea587f4 6421
mbed_official 403:91a4bea587f4 6422 /**
mbed_official 403:91a4bea587f4 6423 * @}
mbed_official 403:91a4bea587f4 6424 */
mbed_official 403:91a4bea587f4 6425
mbed_official 403:91a4bea587f4 6426 /**
mbed_official 403:91a4bea587f4 6427 * @}
mbed_official 403:91a4bea587f4 6428 */
mbed_official 403:91a4bea587f4 6429
mbed_official 403:91a4bea587f4 6430 /** @addtogroup Exported_macros
mbed_official 403:91a4bea587f4 6431 * @{
mbed_official 403:91a4bea587f4 6432 */
mbed_official 403:91a4bea587f4 6433
mbed_official 403:91a4bea587f4 6434 /****************************** ADC Instances *********************************/
mbed_official 403:91a4bea587f4 6435 #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
mbed_official 403:91a4bea587f4 6436 ((INSTANCE) == ADC2) || \
mbed_official 403:91a4bea587f4 6437 ((INSTANCE) == ADC3) || \
mbed_official 403:91a4bea587f4 6438 ((INSTANCE) == ADC4))
mbed_official 403:91a4bea587f4 6439
mbed_official 403:91a4bea587f4 6440 #define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
mbed_official 403:91a4bea587f4 6441 ((INSTANCE) == ADC3))
mbed_official 403:91a4bea587f4 6442
mbed_official 403:91a4bea587f4 6443 #define IS_ADC_COMMON_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_2_COMMON) || \
mbed_official 403:91a4bea587f4 6444 ((INSTANCE) == ADC3_4_COMMON))
mbed_official 403:91a4bea587f4 6445
mbed_official 403:91a4bea587f4 6446 /****************************** CAN Instances *********************************/
mbed_official 403:91a4bea587f4 6447 #define IS_CAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CAN)
mbed_official 403:91a4bea587f4 6448
mbed_official 403:91a4bea587f4 6449 /****************************** COMP Instances ********************************/
mbed_official 403:91a4bea587f4 6450 #define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
mbed_official 403:91a4bea587f4 6451 ((INSTANCE) == COMP2) || \
mbed_official 403:91a4bea587f4 6452 ((INSTANCE) == COMP3) || \
mbed_official 403:91a4bea587f4 6453 ((INSTANCE) == COMP4) || \
mbed_official 403:91a4bea587f4 6454 ((INSTANCE) == COMP5) || \
mbed_official 403:91a4bea587f4 6455 ((INSTANCE) == COMP6) || \
mbed_official 403:91a4bea587f4 6456 ((INSTANCE) == COMP7))
mbed_official 403:91a4bea587f4 6457
mbed_official 403:91a4bea587f4 6458 /******************** COMP Instances with switch on DAC1 Channel1 output ******/
mbed_official 403:91a4bea587f4 6459 #define IS_COMP_DAC1SWITCH_INSTANCE(INSTANCE) ((INSTANCE) == COMP1)
mbed_official 403:91a4bea587f4 6460
mbed_official 403:91a4bea587f4 6461 /******************** COMP Instances with window mode capability **************/
mbed_official 403:91a4bea587f4 6462 #define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) (((INSTANCE) == COMP2) || \
mbed_official 403:91a4bea587f4 6463 ((INSTANCE) == COMP4) || \
mbed_official 403:91a4bea587f4 6464 ((INSTANCE) == COMP6))
mbed_official 403:91a4bea587f4 6465
mbed_official 403:91a4bea587f4 6466 /****************************** CRC Instances *********************************/
mbed_official 403:91a4bea587f4 6467 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
mbed_official 403:91a4bea587f4 6468
mbed_official 403:91a4bea587f4 6469 /****************************** DAC Instances *********************************/
mbed_official 403:91a4bea587f4 6470 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
mbed_official 403:91a4bea587f4 6471
mbed_official 403:91a4bea587f4 6472 #define IS_DAC_CHANNEL_INSTANCE(INSTANCE, CHANNEL) \
mbed_official 403:91a4bea587f4 6473 (((INSTANCE) == DAC1) && \
mbed_official 403:91a4bea587f4 6474 (((CHANNEL) == DAC_CHANNEL_1) || \
mbed_official 403:91a4bea587f4 6475 ((CHANNEL) == DAC_CHANNEL_2)))
mbed_official 403:91a4bea587f4 6476
mbed_official 403:91a4bea587f4 6477 /****************************** DMA Instances *********************************/
mbed_official 403:91a4bea587f4 6478 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
mbed_official 403:91a4bea587f4 6479 ((INSTANCE) == DMA1_Channel2) || \
mbed_official 403:91a4bea587f4 6480 ((INSTANCE) == DMA1_Channel3) || \
mbed_official 403:91a4bea587f4 6481 ((INSTANCE) == DMA1_Channel4) || \
mbed_official 403:91a4bea587f4 6482 ((INSTANCE) == DMA1_Channel5) || \
mbed_official 403:91a4bea587f4 6483 ((INSTANCE) == DMA1_Channel6) || \
mbed_official 403:91a4bea587f4 6484 ((INSTANCE) == DMA1_Channel7) || \
mbed_official 403:91a4bea587f4 6485 ((INSTANCE) == DMA2_Channel1) || \
mbed_official 403:91a4bea587f4 6486 ((INSTANCE) == DMA2_Channel2) || \
mbed_official 403:91a4bea587f4 6487 ((INSTANCE) == DMA2_Channel3) || \
mbed_official 403:91a4bea587f4 6488 ((INSTANCE) == DMA2_Channel4) || \
mbed_official 403:91a4bea587f4 6489 ((INSTANCE) == DMA2_Channel5))
mbed_official 403:91a4bea587f4 6490
mbed_official 403:91a4bea587f4 6491 /****************************** GPIO Instances ********************************/
mbed_official 403:91a4bea587f4 6492 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
mbed_official 403:91a4bea587f4 6493 ((INSTANCE) == GPIOB) || \
mbed_official 403:91a4bea587f4 6494 ((INSTANCE) == GPIOC) || \
mbed_official 403:91a4bea587f4 6495 ((INSTANCE) == GPIOD) || \
mbed_official 403:91a4bea587f4 6496 ((INSTANCE) == GPIOE) || \
mbed_official 403:91a4bea587f4 6497 ((INSTANCE) == GPIOF))
mbed_official 403:91a4bea587f4 6498
mbed_official 403:91a4bea587f4 6499 /****************************** I2C Instances *********************************/
mbed_official 403:91a4bea587f4 6500 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
mbed_official 403:91a4bea587f4 6501 ((INSTANCE) == I2C2))
mbed_official 403:91a4bea587f4 6502
mbed_official 403:91a4bea587f4 6503 /****************************** I2S Instances *********************************/
mbed_official 403:91a4bea587f4 6504 #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
mbed_official 403:91a4bea587f4 6505 ((INSTANCE) == SPI3))
mbed_official 403:91a4bea587f4 6506
mbed_official 403:91a4bea587f4 6507 /****************************** IWDG Instances ********************************/
mbed_official 403:91a4bea587f4 6508 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
mbed_official 403:91a4bea587f4 6509
mbed_official 403:91a4bea587f4 6510 /****************************** OPAMP Instances *******************************/
mbed_official 403:91a4bea587f4 6511 #define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \
mbed_official 403:91a4bea587f4 6512 ((INSTANCE) == OPAMP2) || \
mbed_official 403:91a4bea587f4 6513 ((INSTANCE) == OPAMP3) || \
mbed_official 403:91a4bea587f4 6514 ((INSTANCE) == OPAMP4))
mbed_official 403:91a4bea587f4 6515
mbed_official 403:91a4bea587f4 6516 /****************************** RTC Instances *********************************/
mbed_official 403:91a4bea587f4 6517 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
mbed_official 403:91a4bea587f4 6518
mbed_official 403:91a4bea587f4 6519 /****************************** SMBUS Instances *******************************/
mbed_official 403:91a4bea587f4 6520 #define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
mbed_official 403:91a4bea587f4 6521 ((INSTANCE) == I2C2))
mbed_official 403:91a4bea587f4 6522
mbed_official 403:91a4bea587f4 6523 /****************************** SPI Instances *********************************/
mbed_official 403:91a4bea587f4 6524 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
mbed_official 403:91a4bea587f4 6525 ((INSTANCE) == SPI2) || \
mbed_official 403:91a4bea587f4 6526 ((INSTANCE) == SPI3))
mbed_official 403:91a4bea587f4 6527
mbed_official 403:91a4bea587f4 6528 /******************* TIM Instances : All supported instances ******************/
mbed_official 403:91a4bea587f4 6529 #define IS_TIM_INSTANCE(INSTANCE)\
mbed_official 403:91a4bea587f4 6530 (((INSTANCE) == TIM1) || \
mbed_official 403:91a4bea587f4 6531 ((INSTANCE) == TIM2) || \
mbed_official 403:91a4bea587f4 6532 ((INSTANCE) == TIM3) || \
mbed_official 403:91a4bea587f4 6533 ((INSTANCE) == TIM4) || \
mbed_official 403:91a4bea587f4 6534 ((INSTANCE) == TIM6) || \
mbed_official 403:91a4bea587f4 6535 ((INSTANCE) == TIM7) || \
mbed_official 403:91a4bea587f4 6536 ((INSTANCE) == TIM8) || \
mbed_official 403:91a4bea587f4 6537 ((INSTANCE) == TIM15) || \
mbed_official 403:91a4bea587f4 6538 ((INSTANCE) == TIM16) || \
mbed_official 403:91a4bea587f4 6539 ((INSTANCE) == TIM17))
mbed_official 403:91a4bea587f4 6540
mbed_official 403:91a4bea587f4 6541 /******************* TIM Instances : at least 1 capture/compare channel *******/
mbed_official 403:91a4bea587f4 6542 #define IS_TIM_CC1_INSTANCE(INSTANCE)\
mbed_official 403:91a4bea587f4 6543 (((INSTANCE) == TIM1) || \
mbed_official 403:91a4bea587f4 6544 ((INSTANCE) == TIM2) || \
mbed_official 403:91a4bea587f4 6545 ((INSTANCE) == TIM3) || \
mbed_official 403:91a4bea587f4 6546 ((INSTANCE) == TIM4) || \
mbed_official 403:91a4bea587f4 6547 ((INSTANCE) == TIM8) || \
mbed_official 403:91a4bea587f4 6548 ((INSTANCE) == TIM15) || \
mbed_official 403:91a4bea587f4 6549 ((INSTANCE) == TIM16) || \
mbed_official 403:91a4bea587f4 6550 ((INSTANCE) == TIM17))
mbed_official 403:91a4bea587f4 6551
mbed_official 403:91a4bea587f4 6552 /****************** TIM Instances : at least 2 capture/compare channels *******/
mbed_official 403:91a4bea587f4 6553 #define IS_TIM_CC2_INSTANCE(INSTANCE)\
mbed_official 403:91a4bea587f4 6554 (((INSTANCE) == TIM1) || \
mbed_official 403:91a4bea587f4 6555 ((INSTANCE) == TIM2) || \
mbed_official 403:91a4bea587f4 6556 ((INSTANCE) == TIM3) || \
mbed_official 403:91a4bea587f4 6557 ((INSTANCE) == TIM4) || \
mbed_official 403:91a4bea587f4 6558 ((INSTANCE) == TIM8) || \
mbed_official 403:91a4bea587f4 6559 ((INSTANCE) == TIM15))
mbed_official 403:91a4bea587f4 6560
mbed_official 403:91a4bea587f4 6561 /****************** TIM Instances : at least 3 capture/compare channels *******/
mbed_official 403:91a4bea587f4 6562 #define IS_TIM_CC3_INSTANCE(INSTANCE)\
mbed_official 403:91a4bea587f4 6563 (((INSTANCE) == TIM1) || \
mbed_official 403:91a4bea587f4 6564 ((INSTANCE) == TIM2) || \
mbed_official 403:91a4bea587f4 6565 ((INSTANCE) == TIM3) || \
mbed_official 403:91a4bea587f4 6566 ((INSTANCE) == TIM4) || \
mbed_official 403:91a4bea587f4 6567 ((INSTANCE) == TIM8))
mbed_official 403:91a4bea587f4 6568
mbed_official 403:91a4bea587f4 6569 /****************** TIM Instances : at least 4 capture/compare channels *******/
mbed_official 403:91a4bea587f4 6570 #define IS_TIM_CC4_INSTANCE(INSTANCE)\
mbed_official 403:91a4bea587f4 6571 (((INSTANCE) == TIM1) || \
mbed_official 403:91a4bea587f4 6572 ((INSTANCE) == TIM2) || \
mbed_official 403:91a4bea587f4 6573 ((INSTANCE) == TIM3) || \
mbed_official 403:91a4bea587f4 6574 ((INSTANCE) == TIM4) || \
mbed_official 403:91a4bea587f4 6575 ((INSTANCE) == TIM8))
mbed_official 403:91a4bea587f4 6576
mbed_official 403:91a4bea587f4 6577 /****************** TIM Instances : at least 5 capture/compare channels *******/
mbed_official 403:91a4bea587f4 6578 #define IS_TIM_CC5_INSTANCE(INSTANCE)\
mbed_official 403:91a4bea587f4 6579 (((INSTANCE) == TIM1) || \
mbed_official 403:91a4bea587f4 6580 ((INSTANCE) == TIM8))
mbed_official 403:91a4bea587f4 6581
mbed_official 403:91a4bea587f4 6582 /****************** TIM Instances : at least 6 capture/compare channels *******/
mbed_official 403:91a4bea587f4 6583 #define IS_TIM_CC6_INSTANCE(INSTANCE)\
mbed_official 403:91a4bea587f4 6584 (((INSTANCE) == TIM1) || \
mbed_official 403:91a4bea587f4 6585 ((INSTANCE) == TIM8))
mbed_official 403:91a4bea587f4 6586
mbed_official 403:91a4bea587f4 6587 /************************** TIM Instances : Advanced-control timers ***********/
mbed_official 403:91a4bea587f4 6588
mbed_official 403:91a4bea587f4 6589 /****************** TIM Instances : supporting clock selection ****************/
mbed_official 403:91a4bea587f4 6590 #define IS_TIM_CLOCK_SELECT_INSTANCE(INSTANCE)\
mbed_official 403:91a4bea587f4 6591 (((INSTANCE) == TIM1) || \
mbed_official 403:91a4bea587f4 6592 ((INSTANCE) == TIM2) || \
mbed_official 403:91a4bea587f4 6593 ((INSTANCE) == TIM3) || \
mbed_official 403:91a4bea587f4 6594 ((INSTANCE) == TIM4) || \
mbed_official 403:91a4bea587f4 6595 ((INSTANCE) == TIM8) || \
mbed_official 403:91a4bea587f4 6596 ((INSTANCE) == TIM15))
mbed_official 403:91a4bea587f4 6597
mbed_official 403:91a4bea587f4 6598 /****************** TIM Instances : supporting external clock mode 1 for ETRF input */
mbed_official 403:91a4bea587f4 6599 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
mbed_official 403:91a4bea587f4 6600 (((INSTANCE) == TIM1) || \
mbed_official 403:91a4bea587f4 6601 ((INSTANCE) == TIM2) || \
mbed_official 403:91a4bea587f4 6602 ((INSTANCE) == TIM3) || \
mbed_official 403:91a4bea587f4 6603 ((INSTANCE) == TIM4) || \
mbed_official 403:91a4bea587f4 6604 ((INSTANCE) == TIM8))
mbed_official 403:91a4bea587f4 6605
mbed_official 403:91a4bea587f4 6606 /****************** TIM Instances : supporting external clock mode 2 **********/
mbed_official 403:91a4bea587f4 6607 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
mbed_official 403:91a4bea587f4 6608 (((INSTANCE) == TIM1) || \
mbed_official 403:91a4bea587f4 6609 ((INSTANCE) == TIM2) || \
mbed_official 403:91a4bea587f4 6610 ((INSTANCE) == TIM3) || \
mbed_official 403:91a4bea587f4 6611 ((INSTANCE) == TIM4) || \
mbed_official 403:91a4bea587f4 6612 ((INSTANCE) == TIM8))
mbed_official 403:91a4bea587f4 6613
mbed_official 403:91a4bea587f4 6614 /****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
mbed_official 403:91a4bea587f4 6615 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
mbed_official 403:91a4bea587f4 6616 (((INSTANCE) == TIM1) || \
mbed_official 403:91a4bea587f4 6617 ((INSTANCE) == TIM2) || \
mbed_official 403:91a4bea587f4 6618 ((INSTANCE) == TIM3) || \
mbed_official 403:91a4bea587f4 6619 ((INSTANCE) == TIM4) || \
mbed_official 403:91a4bea587f4 6620 ((INSTANCE) == TIM8) || \
mbed_official 403:91a4bea587f4 6621 ((INSTANCE) == TIM15))
mbed_official 403:91a4bea587f4 6622
mbed_official 403:91a4bea587f4 6623 /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
mbed_official 403:91a4bea587f4 6624 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
mbed_official 403:91a4bea587f4 6625 (((INSTANCE) == TIM1) || \
mbed_official 403:91a4bea587f4 6626 ((INSTANCE) == TIM2) || \
mbed_official 403:91a4bea587f4 6627 ((INSTANCE) == TIM3) || \
mbed_official 403:91a4bea587f4 6628 ((INSTANCE) == TIM4) || \
mbed_official 403:91a4bea587f4 6629 ((INSTANCE) == TIM8) || \
mbed_official 403:91a4bea587f4 6630 ((INSTANCE) == TIM15))
mbed_official 403:91a4bea587f4 6631
mbed_official 403:91a4bea587f4 6632 /****************** TIM Instances : supporting OCxREF clear *******************/
mbed_official 403:91a4bea587f4 6633 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
mbed_official 403:91a4bea587f4 6634 (((INSTANCE) == TIM1) || \
mbed_official 403:91a4bea587f4 6635 ((INSTANCE) == TIM2) || \
mbed_official 403:91a4bea587f4 6636 ((INSTANCE) == TIM3) || \
mbed_official 403:91a4bea587f4 6637 ((INSTANCE) == TIM4) || \
mbed_official 403:91a4bea587f4 6638 ((INSTANCE) == TIM8))
mbed_official 403:91a4bea587f4 6639
mbed_official 403:91a4bea587f4 6640 /****************** TIM Instances : supporting encoder interface **************/
mbed_official 403:91a4bea587f4 6641 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\
mbed_official 403:91a4bea587f4 6642 (((INSTANCE) == TIM1) || \
mbed_official 403:91a4bea587f4 6643 ((INSTANCE) == TIM2) || \
mbed_official 403:91a4bea587f4 6644 ((INSTANCE) == TIM3) || \
mbed_official 403:91a4bea587f4 6645 ((INSTANCE) == TIM4) || \
mbed_official 403:91a4bea587f4 6646 ((INSTANCE) == TIM8))
mbed_official 403:91a4bea587f4 6647
mbed_official 403:91a4bea587f4 6648 /****************** TIM Instances : supporting Hall interface *****************/
mbed_official 403:91a4bea587f4 6649 #define IS_TIM_HALL_INTERFACE_INSTANCE(INSTANCE)\
mbed_official 403:91a4bea587f4 6650 (((INSTANCE) == TIM1) || \
mbed_official 403:91a4bea587f4 6651 ((INSTANCE) == TIM8))
mbed_official 403:91a4bea587f4 6652
mbed_official 403:91a4bea587f4 6653 /****************** TIM Instances : supporting input XOR function *************/
mbed_official 403:91a4bea587f4 6654 #define IS_TIM_XOR_INSTANCE(INSTANCE)\
mbed_official 403:91a4bea587f4 6655 (((INSTANCE) == TIM1) || \
mbed_official 403:91a4bea587f4 6656 ((INSTANCE) == TIM2) || \
mbed_official 403:91a4bea587f4 6657 ((INSTANCE) == TIM3) || \
mbed_official 403:91a4bea587f4 6658 ((INSTANCE) == TIM4) || \
mbed_official 403:91a4bea587f4 6659 ((INSTANCE) == TIM8) || \
mbed_official 403:91a4bea587f4 6660 ((INSTANCE) == TIM15))
mbed_official 403:91a4bea587f4 6661
mbed_official 403:91a4bea587f4 6662 /****************** TIM Instances : supporting master mode ********************/
mbed_official 403:91a4bea587f4 6663 #define IS_TIM_MASTER_INSTANCE(INSTANCE)\
mbed_official 403:91a4bea587f4 6664 (((INSTANCE) == TIM1) || \
mbed_official 403:91a4bea587f4 6665 ((INSTANCE) == TIM2) || \
mbed_official 403:91a4bea587f4 6666 ((INSTANCE) == TIM3) || \
mbed_official 403:91a4bea587f4 6667 ((INSTANCE) == TIM4) || \
mbed_official 403:91a4bea587f4 6668 ((INSTANCE) == TIM6) || \
mbed_official 403:91a4bea587f4 6669 ((INSTANCE) == TIM7) || \
mbed_official 403:91a4bea587f4 6670 ((INSTANCE) == TIM8) || \
mbed_official 403:91a4bea587f4 6671 ((INSTANCE) == TIM15))
mbed_official 403:91a4bea587f4 6672
mbed_official 403:91a4bea587f4 6673 /****************** TIM Instances : supporting slave mode *********************/
mbed_official 403:91a4bea587f4 6674 #define IS_TIM_SLAVE_INSTANCE(INSTANCE)\
mbed_official 403:91a4bea587f4 6675 (((INSTANCE) == TIM1) || \
mbed_official 403:91a4bea587f4 6676 ((INSTANCE) == TIM2) || \
mbed_official 403:91a4bea587f4 6677 ((INSTANCE) == TIM3) || \
mbed_official 403:91a4bea587f4 6678 ((INSTANCE) == TIM4) || \
mbed_official 403:91a4bea587f4 6679 ((INSTANCE) == TIM8) || \
mbed_official 403:91a4bea587f4 6680 ((INSTANCE) == TIM15))
mbed_official 403:91a4bea587f4 6681
mbed_official 403:91a4bea587f4 6682 /****************** TIM Instances : supporting synchronization ****************/
mbed_official 403:91a4bea587f4 6683 #define IS_TIM_SYNCHRO_INSTANCE(INSTANCE)\
mbed_official 403:91a4bea587f4 6684 (((INSTANCE) == TIM1) || \
mbed_official 403:91a4bea587f4 6685 ((INSTANCE) == TIM2) || \
mbed_official 403:91a4bea587f4 6686 ((INSTANCE) == TIM3) || \
mbed_official 403:91a4bea587f4 6687 ((INSTANCE) == TIM4) || \
mbed_official 403:91a4bea587f4 6688 ((INSTANCE) == TIM6) || \
mbed_official 403:91a4bea587f4 6689 ((INSTANCE) == TIM7) || \
mbed_official 403:91a4bea587f4 6690 ((INSTANCE) == TIM8) || \
mbed_official 403:91a4bea587f4 6691 ((INSTANCE) == TIM15))
mbed_official 403:91a4bea587f4 6692
mbed_official 403:91a4bea587f4 6693 /****************** TIM Instances : supporting 32 bits counter ****************/
mbed_official 403:91a4bea587f4 6694 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)\
mbed_official 403:91a4bea587f4 6695 ((INSTANCE) == TIM2)
mbed_official 403:91a4bea587f4 6696
mbed_official 403:91a4bea587f4 6697 /****************** TIM Instances : supporting DMA burst **********************/
mbed_official 403:91a4bea587f4 6698 #define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
mbed_official 403:91a4bea587f4 6699 (((INSTANCE) == TIM1) || \
mbed_official 403:91a4bea587f4 6700 ((INSTANCE) == TIM2) || \
mbed_official 403:91a4bea587f4 6701 ((INSTANCE) == TIM3) || \
mbed_official 403:91a4bea587f4 6702 ((INSTANCE) == TIM4) || \
mbed_official 403:91a4bea587f4 6703 ((INSTANCE) == TIM8) || \
mbed_official 403:91a4bea587f4 6704 ((INSTANCE) == TIM15) || \
mbed_official 403:91a4bea587f4 6705 ((INSTANCE) == TIM16) || \
mbed_official 403:91a4bea587f4 6706 ((INSTANCE) == TIM17))
mbed_official 403:91a4bea587f4 6707
mbed_official 403:91a4bea587f4 6708 /****************** TIM Instances : supporting the break function *************/
mbed_official 403:91a4bea587f4 6709 #define IS_TIM_BREAK_INSTANCE(INSTANCE)\
mbed_official 403:91a4bea587f4 6710 (((INSTANCE) == TIM1) || \
mbed_official 403:91a4bea587f4 6711 ((INSTANCE) == TIM8) || \
mbed_official 403:91a4bea587f4 6712 ((INSTANCE) == TIM15) || \
mbed_official 403:91a4bea587f4 6713 ((INSTANCE) == TIM16) || \
mbed_official 403:91a4bea587f4 6714 ((INSTANCE) == TIM17))
mbed_official 403:91a4bea587f4 6715
mbed_official 403:91a4bea587f4 6716 /****************** TIM Instances : supporting input/output channel(s) ********/
mbed_official 403:91a4bea587f4 6717 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
mbed_official 403:91a4bea587f4 6718 ((((INSTANCE) == TIM1) && \
mbed_official 403:91a4bea587f4 6719 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 403:91a4bea587f4 6720 ((CHANNEL) == TIM_CHANNEL_2) || \
mbed_official 403:91a4bea587f4 6721 ((CHANNEL) == TIM_CHANNEL_3) || \
mbed_official 403:91a4bea587f4 6722 ((CHANNEL) == TIM_CHANNEL_4) || \
mbed_official 403:91a4bea587f4 6723 ((CHANNEL) == TIM_CHANNEL_5) || \
mbed_official 403:91a4bea587f4 6724 ((CHANNEL) == TIM_CHANNEL_6))) \
mbed_official 403:91a4bea587f4 6725 || \
mbed_official 403:91a4bea587f4 6726 (((INSTANCE) == TIM2) && \
mbed_official 403:91a4bea587f4 6727 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 403:91a4bea587f4 6728 ((CHANNEL) == TIM_CHANNEL_2) || \
mbed_official 403:91a4bea587f4 6729 ((CHANNEL) == TIM_CHANNEL_3) || \
mbed_official 403:91a4bea587f4 6730 ((CHANNEL) == TIM_CHANNEL_4))) \
mbed_official 403:91a4bea587f4 6731 || \
mbed_official 403:91a4bea587f4 6732 (((INSTANCE) == TIM3) && \
mbed_official 403:91a4bea587f4 6733 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 403:91a4bea587f4 6734 ((CHANNEL) == TIM_CHANNEL_2) || \
mbed_official 403:91a4bea587f4 6735 ((CHANNEL) == TIM_CHANNEL_3) || \
mbed_official 403:91a4bea587f4 6736 ((CHANNEL) == TIM_CHANNEL_4))) \
mbed_official 403:91a4bea587f4 6737 || \
mbed_official 403:91a4bea587f4 6738 (((INSTANCE) == TIM4) && \
mbed_official 403:91a4bea587f4 6739 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 403:91a4bea587f4 6740 ((CHANNEL) == TIM_CHANNEL_2) || \
mbed_official 403:91a4bea587f4 6741 ((CHANNEL) == TIM_CHANNEL_3) || \
mbed_official 403:91a4bea587f4 6742 ((CHANNEL) == TIM_CHANNEL_4))) \
mbed_official 403:91a4bea587f4 6743 || \
mbed_official 403:91a4bea587f4 6744 (((INSTANCE) == TIM8) && \
mbed_official 403:91a4bea587f4 6745 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 403:91a4bea587f4 6746 ((CHANNEL) == TIM_CHANNEL_2) || \
mbed_official 403:91a4bea587f4 6747 ((CHANNEL) == TIM_CHANNEL_3) || \
mbed_official 403:91a4bea587f4 6748 ((CHANNEL) == TIM_CHANNEL_4) || \
mbed_official 403:91a4bea587f4 6749 ((CHANNEL) == TIM_CHANNEL_5) || \
mbed_official 403:91a4bea587f4 6750 ((CHANNEL) == TIM_CHANNEL_6))) \
mbed_official 403:91a4bea587f4 6751 || \
mbed_official 403:91a4bea587f4 6752 (((INSTANCE) == TIM15) && \
mbed_official 403:91a4bea587f4 6753 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 403:91a4bea587f4 6754 ((CHANNEL) == TIM_CHANNEL_2))) \
mbed_official 403:91a4bea587f4 6755 || \
mbed_official 403:91a4bea587f4 6756 (((INSTANCE) == TIM16) && \
mbed_official 403:91a4bea587f4 6757 (((CHANNEL) == TIM_CHANNEL_1))) \
mbed_official 403:91a4bea587f4 6758 || \
mbed_official 403:91a4bea587f4 6759 (((INSTANCE) == TIM17) && \
mbed_official 403:91a4bea587f4 6760 (((CHANNEL) == TIM_CHANNEL_1))))
mbed_official 403:91a4bea587f4 6761
mbed_official 403:91a4bea587f4 6762 /****************** TIM Instances : supporting complementary output(s) ********/
mbed_official 403:91a4bea587f4 6763 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
mbed_official 403:91a4bea587f4 6764 ((((INSTANCE) == TIM1) && \
mbed_official 403:91a4bea587f4 6765 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 403:91a4bea587f4 6766 ((CHANNEL) == TIM_CHANNEL_2) || \
mbed_official 403:91a4bea587f4 6767 ((CHANNEL) == TIM_CHANNEL_3))) \
mbed_official 403:91a4bea587f4 6768 || \
mbed_official 403:91a4bea587f4 6769 (((INSTANCE) == TIM8) && \
mbed_official 403:91a4bea587f4 6770 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 403:91a4bea587f4 6771 ((CHANNEL) == TIM_CHANNEL_2) || \
mbed_official 403:91a4bea587f4 6772 ((CHANNEL) == TIM_CHANNEL_3))) \
mbed_official 403:91a4bea587f4 6773 || \
mbed_official 403:91a4bea587f4 6774 (((INSTANCE) == TIM15) && \
mbed_official 403:91a4bea587f4 6775 ((CHANNEL) == TIM_CHANNEL_1)) \
mbed_official 403:91a4bea587f4 6776 || \
mbed_official 403:91a4bea587f4 6777 (((INSTANCE) == TIM16) && \
mbed_official 403:91a4bea587f4 6778 ((CHANNEL) == TIM_CHANNEL_1)) \
mbed_official 403:91a4bea587f4 6779 || \
mbed_official 403:91a4bea587f4 6780 (((INSTANCE) == TIM17) && \
mbed_official 403:91a4bea587f4 6781 ((CHANNEL) == TIM_CHANNEL_1)))
mbed_official 403:91a4bea587f4 6782
mbed_official 403:91a4bea587f4 6783 /****************** TIM Instances : supporting counting mode selection ********/
mbed_official 403:91a4bea587f4 6784 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
mbed_official 403:91a4bea587f4 6785 (((INSTANCE) == TIM1) || \
mbed_official 403:91a4bea587f4 6786 ((INSTANCE) == TIM2) || \
mbed_official 403:91a4bea587f4 6787 ((INSTANCE) == TIM3) || \
mbed_official 403:91a4bea587f4 6788 ((INSTANCE) == TIM4) || \
mbed_official 403:91a4bea587f4 6789 ((INSTANCE) == TIM8))
mbed_official 403:91a4bea587f4 6790
mbed_official 403:91a4bea587f4 6791 /****************** TIM Instances : supporting repetition counter *************/
mbed_official 403:91a4bea587f4 6792 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
mbed_official 403:91a4bea587f4 6793 (((INSTANCE) == TIM1) || \
mbed_official 403:91a4bea587f4 6794 ((INSTANCE) == TIM8) || \
mbed_official 403:91a4bea587f4 6795 ((INSTANCE) == TIM15) || \
mbed_official 403:91a4bea587f4 6796 ((INSTANCE) == TIM16) || \
mbed_official 403:91a4bea587f4 6797 ((INSTANCE) == TIM17))
mbed_official 403:91a4bea587f4 6798
mbed_official 403:91a4bea587f4 6799 /****************** TIM Instances : supporting clock division *****************/
mbed_official 403:91a4bea587f4 6800 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
mbed_official 403:91a4bea587f4 6801 (((INSTANCE) == TIM1) || \
mbed_official 403:91a4bea587f4 6802 ((INSTANCE) == TIM2) || \
mbed_official 403:91a4bea587f4 6803 ((INSTANCE) == TIM3) || \
mbed_official 403:91a4bea587f4 6804 ((INSTANCE) == TIM4) || \
mbed_official 403:91a4bea587f4 6805 ((INSTANCE) == TIM8) || \
mbed_official 403:91a4bea587f4 6806 ((INSTANCE) == TIM15) || \
mbed_official 403:91a4bea587f4 6807 ((INSTANCE) == TIM16) || \
mbed_official 403:91a4bea587f4 6808 ((INSTANCE) == TIM17))
mbed_official 403:91a4bea587f4 6809
mbed_official 403:91a4bea587f4 6810 /****************** TIM Instances : supporting 2 break inputs *****************/
mbed_official 403:91a4bea587f4 6811 #define IS_TIM_BKIN2_INSTANCE(INSTANCE)\
mbed_official 403:91a4bea587f4 6812 (((INSTANCE) == TIM1) || \
mbed_official 403:91a4bea587f4 6813 ((INSTANCE) == TIM8))
mbed_official 403:91a4bea587f4 6814
mbed_official 403:91a4bea587f4 6815 /****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
mbed_official 403:91a4bea587f4 6816 #define IS_TIM_TRGO2_INSTANCE(INSTANCE)\
mbed_official 403:91a4bea587f4 6817 (((INSTANCE) == TIM1) || \
mbed_official 403:91a4bea587f4 6818 ((INSTANCE) == TIM8))
mbed_official 403:91a4bea587f4 6819
mbed_official 403:91a4bea587f4 6820 /****************** TIM Instances : supporting DMA generation on Update events*/
mbed_official 403:91a4bea587f4 6821 #define IS_TIM_DMA_INSTANCE(INSTANCE)\
mbed_official 403:91a4bea587f4 6822 (((INSTANCE) == TIM1) || \
mbed_official 403:91a4bea587f4 6823 ((INSTANCE) == TIM2) || \
mbed_official 403:91a4bea587f4 6824 ((INSTANCE) == TIM3) || \
mbed_official 403:91a4bea587f4 6825 ((INSTANCE) == TIM4) || \
mbed_official 403:91a4bea587f4 6826 ((INSTANCE) == TIM6) || \
mbed_official 403:91a4bea587f4 6827 ((INSTANCE) == TIM7) || \
mbed_official 403:91a4bea587f4 6828 ((INSTANCE) == TIM8) || \
mbed_official 403:91a4bea587f4 6829 ((INSTANCE) == TIM15) || \
mbed_official 403:91a4bea587f4 6830 ((INSTANCE) == TIM16) || \
mbed_official 403:91a4bea587f4 6831 ((INSTANCE) == TIM17))
mbed_official 403:91a4bea587f4 6832
mbed_official 403:91a4bea587f4 6833 /****************** TIM Instances : supporting DMA generation on Capture/Compare events */
mbed_official 403:91a4bea587f4 6834 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\
mbed_official 403:91a4bea587f4 6835 (((INSTANCE) == TIM1) || \
mbed_official 403:91a4bea587f4 6836 ((INSTANCE) == TIM2) || \
mbed_official 403:91a4bea587f4 6837 ((INSTANCE) == TIM3) || \
mbed_official 403:91a4bea587f4 6838 ((INSTANCE) == TIM4) || \
mbed_official 403:91a4bea587f4 6839 ((INSTANCE) == TIM8) || \
mbed_official 403:91a4bea587f4 6840 ((INSTANCE) == TIM15) || \
mbed_official 403:91a4bea587f4 6841 ((INSTANCE) == TIM16) || \
mbed_official 403:91a4bea587f4 6842 ((INSTANCE) == TIM17))
mbed_official 403:91a4bea587f4 6843
mbed_official 403:91a4bea587f4 6844 /****************** TIM Instances : supporting commutation event generation ***/
mbed_official 403:91a4bea587f4 6845 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\
mbed_official 403:91a4bea587f4 6846 (((INSTANCE) == TIM1) || \
mbed_official 403:91a4bea587f4 6847 ((INSTANCE) == TIM8) || \
mbed_official 403:91a4bea587f4 6848 ((INSTANCE) == TIM15) || \
mbed_official 403:91a4bea587f4 6849 ((INSTANCE) == TIM16) || \
mbed_official 403:91a4bea587f4 6850 ((INSTANCE) == TIM17))
mbed_official 403:91a4bea587f4 6851
mbed_official 403:91a4bea587f4 6852 /****************** TIM Instances : supporting remapping capability ***********/
mbed_official 403:91a4bea587f4 6853 #define IS_TIM_REMAP_INSTANCE(INSTANCE)\
mbed_official 403:91a4bea587f4 6854 (((INSTANCE) == TIM1) || \
mbed_official 403:91a4bea587f4 6855 ((INSTANCE) == TIM8) || \
mbed_official 403:91a4bea587f4 6856 ((INSTANCE) == TIM16))
mbed_official 403:91a4bea587f4 6857
mbed_official 403:91a4bea587f4 6858 /****************** TIM Instances : supporting combined 3-phase PWM mode ******/
mbed_official 403:91a4bea587f4 6859 #define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) \
mbed_official 403:91a4bea587f4 6860 (((INSTANCE) == TIM1) || \
mbed_official 403:91a4bea587f4 6861 ((INSTANCE) == TIM8))
mbed_official 403:91a4bea587f4 6862
mbed_official 403:91a4bea587f4 6863 /****************************** TSC Instances *********************************/
mbed_official 403:91a4bea587f4 6864 #define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC)
mbed_official 403:91a4bea587f4 6865
mbed_official 403:91a4bea587f4 6866 /******************** USART Instances : Synchronous mode **********************/
mbed_official 403:91a4bea587f4 6867 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 403:91a4bea587f4 6868 ((INSTANCE) == USART2) || \
mbed_official 403:91a4bea587f4 6869 ((INSTANCE) == USART3))
mbed_official 403:91a4bea587f4 6870
mbed_official 403:91a4bea587f4 6871 /****************** USART Instances : Auto Baud Rate detection ****************/
mbed_official 403:91a4bea587f4 6872 #define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 403:91a4bea587f4 6873 ((INSTANCE) == USART2) || \
mbed_official 403:91a4bea587f4 6874 ((INSTANCE) == USART3))
mbed_official 403:91a4bea587f4 6875
mbed_official 403:91a4bea587f4 6876 /******************** UART Instances : Asynchronous mode **********************/
mbed_official 403:91a4bea587f4 6877 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 403:91a4bea587f4 6878 ((INSTANCE) == USART2) || \
mbed_official 403:91a4bea587f4 6879 ((INSTANCE) == USART3) || \
mbed_official 403:91a4bea587f4 6880 ((INSTANCE) == UART4) || \
mbed_official 403:91a4bea587f4 6881 ((INSTANCE) == UART5))
mbed_official 403:91a4bea587f4 6882
mbed_official 403:91a4bea587f4 6883 /******************** UART Instances : Half-Duplex mode **********************/
mbed_official 403:91a4bea587f4 6884 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 403:91a4bea587f4 6885 ((INSTANCE) == USART2) || \
mbed_official 403:91a4bea587f4 6886 ((INSTANCE) == USART3) || \
mbed_official 403:91a4bea587f4 6887 ((INSTANCE) == UART4) || \
mbed_official 403:91a4bea587f4 6888 ((INSTANCE) == UART5))
mbed_official 403:91a4bea587f4 6889
mbed_official 403:91a4bea587f4 6890 /******************** UART Instances : LIN mode **********************/
mbed_official 403:91a4bea587f4 6891 #define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 403:91a4bea587f4 6892 ((INSTANCE) == USART2) || \
mbed_official 403:91a4bea587f4 6893 ((INSTANCE) == USART3) || \
mbed_official 403:91a4bea587f4 6894 ((INSTANCE) == UART4) || \
mbed_official 403:91a4bea587f4 6895 ((INSTANCE) == UART5))
mbed_official 403:91a4bea587f4 6896
mbed_official 403:91a4bea587f4 6897 /******************** UART Instances : Wake-up from Stop mode **********************/
mbed_official 403:91a4bea587f4 6898 #define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 403:91a4bea587f4 6899 ((INSTANCE) == USART2) || \
mbed_official 403:91a4bea587f4 6900 ((INSTANCE) == USART3) || \
mbed_official 403:91a4bea587f4 6901 ((INSTANCE) == UART4) || \
mbed_official 403:91a4bea587f4 6902 ((INSTANCE) == UART5))
mbed_official 403:91a4bea587f4 6903
mbed_official 403:91a4bea587f4 6904 /****************** UART Instances : Hardware Flow control ********************/
mbed_official 403:91a4bea587f4 6905 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 403:91a4bea587f4 6906 ((INSTANCE) == USART2) || \
mbed_official 403:91a4bea587f4 6907 ((INSTANCE) == USART3))
mbed_official 403:91a4bea587f4 6908
mbed_official 403:91a4bea587f4 6909 /****************** UART Instances : Auto Baud Rate detection *****************/
mbed_official 403:91a4bea587f4 6910 #define IS_UART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 403:91a4bea587f4 6911 ((INSTANCE) == USART2) || \
mbed_official 403:91a4bea587f4 6912 ((INSTANCE) == USART3))
mbed_official 403:91a4bea587f4 6913
mbed_official 403:91a4bea587f4 6914 /****************** UART Instances : Driver Enable ****************************/
mbed_official 403:91a4bea587f4 6915 #define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 403:91a4bea587f4 6916 ((INSTANCE) == USART2) || \
mbed_official 403:91a4bea587f4 6917 ((INSTANCE) == USART3))
mbed_official 403:91a4bea587f4 6918
mbed_official 403:91a4bea587f4 6919 /********************* UART Instances : Smard card mode ***********************/
mbed_official 403:91a4bea587f4 6920 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 403:91a4bea587f4 6921 ((INSTANCE) == USART2) || \
mbed_official 403:91a4bea587f4 6922 ((INSTANCE) == USART3))
mbed_official 403:91a4bea587f4 6923
mbed_official 403:91a4bea587f4 6924 /*********************** UART Instances : IRDA mode ***************************/
mbed_official 403:91a4bea587f4 6925 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 403:91a4bea587f4 6926 ((INSTANCE) == USART2) || \
mbed_official 403:91a4bea587f4 6927 ((INSTANCE) == USART3) || \
mbed_official 403:91a4bea587f4 6928 ((INSTANCE) == UART4) || \
mbed_official 403:91a4bea587f4 6929 ((INSTANCE) == UART5))
mbed_official 403:91a4bea587f4 6930
mbed_official 403:91a4bea587f4 6931 /****************************** USB Instances *********************************/
mbed_official 403:91a4bea587f4 6932 #define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
mbed_official 403:91a4bea587f4 6933
mbed_official 403:91a4bea587f4 6934 /****************************** WWDG Instances ********************************/
mbed_official 403:91a4bea587f4 6935 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
mbed_official 403:91a4bea587f4 6936
mbed_official 403:91a4bea587f4 6937 /**
mbed_official 403:91a4bea587f4 6938 * @}
mbed_official 403:91a4bea587f4 6939 */
mbed_official 403:91a4bea587f4 6940
mbed_official 403:91a4bea587f4 6941
mbed_official 403:91a4bea587f4 6942 /******************************************************************************/
mbed_official 403:91a4bea587f4 6943 /* For a painless codes migration between the STM32F3xx device product */
mbed_official 403:91a4bea587f4 6944 /* lines, the aliases defined below are put in place to overcome the */
mbed_official 403:91a4bea587f4 6945 /* differences in the interrupt handlers and IRQn definitions. */
mbed_official 403:91a4bea587f4 6946 /* No need to update developed interrupt code when moving across */
mbed_official 403:91a4bea587f4 6947 /* product lines within the same STM32F3 Family */
mbed_official 403:91a4bea587f4 6948 /******************************************************************************/
mbed_official 403:91a4bea587f4 6949
mbed_official 403:91a4bea587f4 6950 /* Aliases for __IRQn */
mbed_official 403:91a4bea587f4 6951
mbed_official 403:91a4bea587f4 6952 #define ADC1_IRQn ADC1_2_IRQn
mbed_official 403:91a4bea587f4 6953 #define CAN_TX_IRQn USB_HP_CAN_TX_IRQn
mbed_official 403:91a4bea587f4 6954 #define CAN_RX0_IRQn USB_LP_CAN_RX0_IRQn
mbed_official 403:91a4bea587f4 6955 #define TIM15_IRQn TIM1_BRK_TIM15_IRQn
mbed_official 403:91a4bea587f4 6956 #define TIM16_IRQn TIM1_UP_TIM16_IRQn
mbed_official 403:91a4bea587f4 6957 #define TIM17_IRQn TIM1_TRG_COM_TIM17_IRQn
mbed_official 403:91a4bea587f4 6958 #define COMP_IRQn COMP1_2_3_IRQn
mbed_official 403:91a4bea587f4 6959 #define COMP2_IRQn COMP1_2_3_IRQn
mbed_official 403:91a4bea587f4 6960 #define COMP1_2_IRQn COMP1_2_3_IRQn
mbed_official 403:91a4bea587f4 6961 #define COMP4_6_IRQn COMP4_5_6_IRQn
mbed_official 403:91a4bea587f4 6962 #define TIM6_DAC1_IRQn TIM6_DAC_IRQn
mbed_official 403:91a4bea587f4 6963
mbed_official 403:91a4bea587f4 6964 /* Aliases for __IRQHandler */
mbed_official 403:91a4bea587f4 6965 #define ADC1_IRQHandler ADC1_2_IRQHandler
mbed_official 403:91a4bea587f4 6966 #define CAN_TX_IRQHandler USB_HP_CAN_TX_IRQHandler
mbed_official 403:91a4bea587f4 6967 #define CAN_RX0_IRQHandler USB_LP_CAN_RX0_IRQHandler
mbed_official 403:91a4bea587f4 6968 #define TIM15_IRQHandler TIM1_BRK_TIM15_IRQHandler
mbed_official 403:91a4bea587f4 6969 #define TIM16_IRQHandler TIM1_UP_TIM16_IRQHandler
mbed_official 403:91a4bea587f4 6970 #define TIM17_IRQHandler TIM1_TRG_COM_TIM17_IRQHandler
mbed_official 403:91a4bea587f4 6971 #define COMP_IRQHandler COMP1_2_3_IRQHandler
mbed_official 403:91a4bea587f4 6972 #define COMP2_IRQHandler COMP1_2_3_IRQHandler
mbed_official 403:91a4bea587f4 6973 #define COMP1_2_IRQHandler COMP1_2_3_IRQHandler
mbed_official 403:91a4bea587f4 6974 #define COMP4_6_IRQHandler COMP4_5_6_IRQHandler
mbed_official 403:91a4bea587f4 6975 #define TIM6_DAC1_IRQHandler TIM6_DAC_IRQHandler
mbed_official 403:91a4bea587f4 6976
mbed_official 403:91a4bea587f4 6977 #ifdef __cplusplus
mbed_official 403:91a4bea587f4 6978 }
mbed_official 403:91a4bea587f4 6979 #endif /* __cplusplus */
mbed_official 403:91a4bea587f4 6980
mbed_official 403:91a4bea587f4 6981 #endif /* __STM32F303xC_H */
mbed_official 403:91a4bea587f4 6982
mbed_official 403:91a4bea587f4 6983 /**
mbed_official 403:91a4bea587f4 6984 * @}
mbed_official 403:91a4bea587f4 6985 */
mbed_official 403:91a4bea587f4 6986
mbed_official 403:91a4bea587f4 6987 /**
mbed_official 403:91a4bea587f4 6988 * @}
mbed_official 403:91a4bea587f4 6989 */
mbed_official 403:91a4bea587f4 6990
mbed_official 403:91a4bea587f4 6991 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/