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targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rcc_ex.h@579:53297373a894, 2015-07-01 (annotated)

Committer:: mbed_official
Date:: Wed Jul 01 09:45:11 2015 +0100
Revision:: 579:53297373a894
Parent:: 441:d2c15dda23c1
Child:: 630:825f75ca301e

Synchronized with git revision d5b4d2ab9c47edb4dc5776e7177b0c2263459081

Full URL: https://github.com/mbedmicro/mbed/commit/d5b4d2ab9c47edb4dc5776e7177b0c2263459081/

Initial version of drivers for SAMR21

Who changed what in which revision?

User	Revision	Line number	New contents of line
mbed_official	340:28d1f895c6fe	1	/**
mbed_official	340:28d1f895c6fe	2	******************************************************************************
mbed_official	340:28d1f895c6fe	3	* @file stm32f0xx_hal_rcc_ex.h
mbed_official	340:28d1f895c6fe	4	* @author MCD Application Team
mbed_official	441:d2c15dda23c1	5	* @version V1.2.0
mbed_official	441:d2c15dda23c1	6	* @date 11-December-2014
mbed_official	340:28d1f895c6fe	7	* @brief Header file of RCC HAL Extension module.
mbed_official	340:28d1f895c6fe	8	******************************************************************************
mbed_official	340:28d1f895c6fe	9	* @attention
mbed_official	340:28d1f895c6fe	10	*
mbed_official	340:28d1f895c6fe	11	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
mbed_official	340:28d1f895c6fe	12	*
mbed_official	340:28d1f895c6fe	13	* Redistribution and use in source and binary forms, with or without modification,
mbed_official	340:28d1f895c6fe	14	* are permitted provided that the following conditions are met:
mbed_official	340:28d1f895c6fe	15	* 1. Redistributions of source code must retain the above copyright notice,
mbed_official	340:28d1f895c6fe	16	* this list of conditions and the following disclaimer.
mbed_official	340:28d1f895c6fe	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official	340:28d1f895c6fe	18	* this list of conditions and the following disclaimer in the documentation
mbed_official	340:28d1f895c6fe	19	* and/or other materials provided with the distribution.
mbed_official	340:28d1f895c6fe	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official	340:28d1f895c6fe	21	* may be used to endorse or promote products derived from this software
mbed_official	340:28d1f895c6fe	22	* without specific prior written permission.
mbed_official	340:28d1f895c6fe	23	*
mbed_official	340:28d1f895c6fe	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official	340:28d1f895c6fe	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official	340:28d1f895c6fe	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official	340:28d1f895c6fe	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official	340:28d1f895c6fe	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official	340:28d1f895c6fe	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official	340:28d1f895c6fe	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official	340:28d1f895c6fe	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official	340:28d1f895c6fe	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official	340:28d1f895c6fe	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official	340:28d1f895c6fe	34	*
mbed_official	340:28d1f895c6fe	35	******************************************************************************
mbed_official	340:28d1f895c6fe	36	*/
mbed_official	340:28d1f895c6fe	37
mbed_official	340:28d1f895c6fe	38	/* Define to prevent recursive inclusion -------------------------------------*/
mbed_official	340:28d1f895c6fe	39	#ifndef __STM32F0xx_HAL_RCC_EX_H
mbed_official	340:28d1f895c6fe	40	#define __STM32F0xx_HAL_RCC_EX_H
mbed_official	340:28d1f895c6fe	41
mbed_official	340:28d1f895c6fe	42	#ifdef __cplusplus
mbed_official	340:28d1f895c6fe	43	extern "C" {
mbed_official	340:28d1f895c6fe	44	#endif
mbed_official	340:28d1f895c6fe	45
mbed_official	340:28d1f895c6fe	46	/* Includes ------------------------------------------------------------------*/
mbed_official	340:28d1f895c6fe	47	#include "stm32f0xx_hal_def.h"
mbed_official	340:28d1f895c6fe	48
mbed_official	340:28d1f895c6fe	49	/** @addtogroup STM32F0xx_HAL_Driver
mbed_official	340:28d1f895c6fe	50	* @{
mbed_official	340:28d1f895c6fe	51	*/
mbed_official	340:28d1f895c6fe	52
mbed_official	340:28d1f895c6fe	53	/** @addtogroup RCCEx
mbed_official	340:28d1f895c6fe	54	* @{
mbed_official	340:28d1f895c6fe	55	*/
mbed_official	340:28d1f895c6fe	56
mbed_official	340:28d1f895c6fe	57	/* Exported types ------------------------------------------------------------*/
mbed_official	340:28d1f895c6fe	58
mbed_official	340:28d1f895c6fe	59	/** @defgroup RCCEx_Exported_Types RCCEx Exported Types
mbed_official	340:28d1f895c6fe	60	* @{
mbed_official	340:28d1f895c6fe	61	*/
mbed_official	340:28d1f895c6fe	62
mbed_official	340:28d1f895c6fe	63	/**
mbed_official	340:28d1f895c6fe	64	* @brief RCC extended clocks structure definition
mbed_official	340:28d1f895c6fe	65	*/
mbed_official	441:d2c15dda23c1	66	#if defined(STM32F030x6) \|\| defined(STM32F030x8) \|\| defined(STM32F031x6) \|\| defined(STM32F038xx) \|\| \
mbed_official	441:d2c15dda23c1	67	defined(STM32F030xC)
mbed_official	340:28d1f895c6fe	68	typedef struct
mbed_official	340:28d1f895c6fe	69	{
mbed_official	340:28d1f895c6fe	70	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
mbed_official	340:28d1f895c6fe	71	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
mbed_official	340:28d1f895c6fe	72
mbed_official	340:28d1f895c6fe	73	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
mbed_official	340:28d1f895c6fe	74	This parameter can be a value of @ref RCC_RTC_Clock_Source */
mbed_official	340:28d1f895c6fe	75
mbed_official	340:28d1f895c6fe	76	uint32_t Usart1ClockSelection; /*!< USART1 clock source
mbed_official	340:28d1f895c6fe	77	This parameter can be a value of @ref RCC_USART1_Clock_Source */
mbed_official	340:28d1f895c6fe	78
mbed_official	340:28d1f895c6fe	79	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
mbed_official	340:28d1f895c6fe	80	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
mbed_official	340:28d1f895c6fe	81
mbed_official	340:28d1f895c6fe	82	}RCC_PeriphCLKInitTypeDef;
mbed_official	441:d2c15dda23c1	83	#endif /* STM32F030x6 \|\| STM32F030x8 \|\| STM32F031x6 \|\| STM32F038xx \|\|
mbed_official	441:d2c15dda23c1	84	STM32F030xC */
mbed_official	441:d2c15dda23c1	85
mbed_official	441:d2c15dda23c1	86	#if defined(STM32F070x6) \|\| defined(STM32F070xB)
mbed_official	441:d2c15dda23c1	87	typedef struct
mbed_official	441:d2c15dda23c1	88	{
mbed_official	441:d2c15dda23c1	89	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
mbed_official	441:d2c15dda23c1	90	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
mbed_official	441:d2c15dda23c1	91
mbed_official	441:d2c15dda23c1	92	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
mbed_official	441:d2c15dda23c1	93	This parameter can be a value of @ref RCC_RTC_Clock_Source */
mbed_official	441:d2c15dda23c1	94
mbed_official	441:d2c15dda23c1	95	uint32_t Usart1ClockSelection; /*!< USART1 clock source
mbed_official	441:d2c15dda23c1	96	This parameter can be a value of @ref RCC_USART1_Clock_Source */
mbed_official	441:d2c15dda23c1	97
mbed_official	441:d2c15dda23c1	98	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
mbed_official	441:d2c15dda23c1	99	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
mbed_official	441:d2c15dda23c1	100
mbed_official	441:d2c15dda23c1	101	uint32_t UsbClockSelection; /*!< USB clock source
mbed_official	441:d2c15dda23c1	102	This parameter can be a value of @ref RCCEx_USB_Clock_Source */
mbed_official	441:d2c15dda23c1	103
mbed_official	441:d2c15dda23c1	104	}RCC_PeriphCLKInitTypeDef;
mbed_official	441:d2c15dda23c1	105	#endif /* STM32F070x6 \|\| STM32F070xB */
mbed_official	340:28d1f895c6fe	106
mbed_official	340:28d1f895c6fe	107	#if defined(STM32F042x6) \|\| defined(STM32F048xx)
mbed_official	340:28d1f895c6fe	108	typedef struct
mbed_official	340:28d1f895c6fe	109	{
mbed_official	340:28d1f895c6fe	110	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
mbed_official	340:28d1f895c6fe	111	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
mbed_official	340:28d1f895c6fe	112
mbed_official	340:28d1f895c6fe	113	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
mbed_official	340:28d1f895c6fe	114	This parameter can be a value of @ref RCC_RTC_Clock_Source */
mbed_official	340:28d1f895c6fe	115
mbed_official	340:28d1f895c6fe	116	uint32_t Usart1ClockSelection; /*!< USART1 clock source
mbed_official	340:28d1f895c6fe	117	This parameter can be a value of @ref RCC_USART1_Clock_Source */
mbed_official	340:28d1f895c6fe	118
mbed_official	340:28d1f895c6fe	119	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
mbed_official	340:28d1f895c6fe	120	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
mbed_official	340:28d1f895c6fe	121
mbed_official	340:28d1f895c6fe	122	uint32_t CecClockSelection; /*!< HDMI CEC clock source
mbed_official	340:28d1f895c6fe	123	This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
mbed_official	340:28d1f895c6fe	124
mbed_official	340:28d1f895c6fe	125	uint32_t UsbClockSelection; /*!< USB clock source
mbed_official	340:28d1f895c6fe	126	This parameter can be a value of @ref RCCEx_USB_Clock_Source */
mbed_official	340:28d1f895c6fe	127
mbed_official	340:28d1f895c6fe	128	}RCC_PeriphCLKInitTypeDef;
mbed_official	340:28d1f895c6fe	129	#endif /* STM32F042x6 \|\| STM32F048xx */
mbed_official	340:28d1f895c6fe	130
mbed_official	340:28d1f895c6fe	131	#if defined(STM32F051x8) \|\| defined(STM32F058xx)
mbed_official	340:28d1f895c6fe	132	typedef struct
mbed_official	340:28d1f895c6fe	133	{
mbed_official	340:28d1f895c6fe	134	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
mbed_official	340:28d1f895c6fe	135	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
mbed_official	340:28d1f895c6fe	136
mbed_official	340:28d1f895c6fe	137	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
mbed_official	340:28d1f895c6fe	138	This parameter can be a value of @ref RCC_RTC_Clock_Source */
mbed_official	340:28d1f895c6fe	139
mbed_official	340:28d1f895c6fe	140	uint32_t Usart1ClockSelection; /*!< USART1 clock source
mbed_official	340:28d1f895c6fe	141	This parameter can be a value of @ref RCC_USART1_Clock_Source */
mbed_official	340:28d1f895c6fe	142
mbed_official	340:28d1f895c6fe	143	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
mbed_official	340:28d1f895c6fe	144	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
mbed_official	340:28d1f895c6fe	145
mbed_official	340:28d1f895c6fe	146	uint32_t CecClockSelection; /*!< HDMI CEC clock source
mbed_official	340:28d1f895c6fe	147	This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
mbed_official	340:28d1f895c6fe	148
mbed_official	340:28d1f895c6fe	149	}RCC_PeriphCLKInitTypeDef;
mbed_official	340:28d1f895c6fe	150	#endif /* STM32F051x8 \|\| STM32F058xx */
mbed_official	340:28d1f895c6fe	151
mbed_official	340:28d1f895c6fe	152	#if defined(STM32F071xB)
mbed_official	340:28d1f895c6fe	153	typedef struct
mbed_official	340:28d1f895c6fe	154	{
mbed_official	340:28d1f895c6fe	155	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
mbed_official	340:28d1f895c6fe	156	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
mbed_official	340:28d1f895c6fe	157
mbed_official	340:28d1f895c6fe	158	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
mbed_official	340:28d1f895c6fe	159	This parameter can be a value of @ref RCC_RTC_Clock_Source */
mbed_official	340:28d1f895c6fe	160
mbed_official	340:28d1f895c6fe	161	uint32_t Usart1ClockSelection; /*!< USART1 clock source
mbed_official	340:28d1f895c6fe	162	This parameter can be a value of @ref RCC_USART1_Clock_Source */
mbed_official	340:28d1f895c6fe	163
mbed_official	340:28d1f895c6fe	164	uint32_t Usart2ClockSelection; /*!< USART2 clock source
mbed_official	340:28d1f895c6fe	165	This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
mbed_official	340:28d1f895c6fe	166
mbed_official	340:28d1f895c6fe	167	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
mbed_official	340:28d1f895c6fe	168	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
mbed_official	340:28d1f895c6fe	169
mbed_official	340:28d1f895c6fe	170	uint32_t CecClockSelection; /*!< HDMI CEC clock source
mbed_official	340:28d1f895c6fe	171	This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
mbed_official	340:28d1f895c6fe	172
mbed_official	340:28d1f895c6fe	173	}RCC_PeriphCLKInitTypeDef;
mbed_official	340:28d1f895c6fe	174	#endif /* STM32F071xB */
mbed_official	340:28d1f895c6fe	175
mbed_official	340:28d1f895c6fe	176	#if defined(STM32F072xB) \|\| defined(STM32F078xx)
mbed_official	340:28d1f895c6fe	177	typedef struct
mbed_official	340:28d1f895c6fe	178	{
mbed_official	340:28d1f895c6fe	179	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
mbed_official	340:28d1f895c6fe	180	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
mbed_official	340:28d1f895c6fe	181
mbed_official	340:28d1f895c6fe	182	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
mbed_official	340:28d1f895c6fe	183	This parameter can be a value of @ref RCC_RTC_Clock_Source */
mbed_official	340:28d1f895c6fe	184
mbed_official	340:28d1f895c6fe	185	uint32_t Usart1ClockSelection; /*!< USART1 clock source
mbed_official	340:28d1f895c6fe	186	This parameter can be a value of @ref RCC_USART1_Clock_Source */
mbed_official	340:28d1f895c6fe	187
mbed_official	340:28d1f895c6fe	188	uint32_t Usart2ClockSelection; /*!< USART2 clock source
mbed_official	340:28d1f895c6fe	189	This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
mbed_official	340:28d1f895c6fe	190
mbed_official	340:28d1f895c6fe	191	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
mbed_official	340:28d1f895c6fe	192	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
mbed_official	340:28d1f895c6fe	193
mbed_official	340:28d1f895c6fe	194	uint32_t CecClockSelection; /*!< HDMI CEC clock source
mbed_official	340:28d1f895c6fe	195	This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
mbed_official	340:28d1f895c6fe	196
mbed_official	340:28d1f895c6fe	197	uint32_t UsbClockSelection; /*!< USB clock source
mbed_official	340:28d1f895c6fe	198	This parameter can be a value of @ref RCCEx_USB_Clock_Source */
mbed_official	340:28d1f895c6fe	199
mbed_official	340:28d1f895c6fe	200	}RCC_PeriphCLKInitTypeDef;
mbed_official	340:28d1f895c6fe	201	#endif /* STM32F072xB \|\| STM32F078xx */
mbed_official	340:28d1f895c6fe	202
mbed_official	340:28d1f895c6fe	203
mbed_official	340:28d1f895c6fe	204	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	340:28d1f895c6fe	205	typedef struct
mbed_official	340:28d1f895c6fe	206	{
mbed_official	340:28d1f895c6fe	207	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
mbed_official	340:28d1f895c6fe	208	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
mbed_official	340:28d1f895c6fe	209
mbed_official	340:28d1f895c6fe	210	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
mbed_official	340:28d1f895c6fe	211	This parameter can be a value of @ref RCC_RTC_Clock_Source */
mbed_official	340:28d1f895c6fe	212
mbed_official	340:28d1f895c6fe	213	uint32_t Usart1ClockSelection; /*!< USART1 clock source
mbed_official	340:28d1f895c6fe	214	This parameter can be a value of @ref RCC_USART1_Clock_Source */
mbed_official	340:28d1f895c6fe	215
mbed_official	340:28d1f895c6fe	216	uint32_t Usart2ClockSelection; /*!< USART2 clock source
mbed_official	340:28d1f895c6fe	217	This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
mbed_official	340:28d1f895c6fe	218
mbed_official	340:28d1f895c6fe	219	uint32_t Usart3ClockSelection; /*!< USART3 clock source
mbed_official	340:28d1f895c6fe	220	This parameter can be a value of @ref RCCEx_USART3_Clock_Source */
mbed_official	340:28d1f895c6fe	221
mbed_official	340:28d1f895c6fe	222	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
mbed_official	340:28d1f895c6fe	223	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
mbed_official	340:28d1f895c6fe	224
mbed_official	340:28d1f895c6fe	225	uint32_t CecClockSelection; /*!< HDMI CEC clock source
mbed_official	340:28d1f895c6fe	226	This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
mbed_official	340:28d1f895c6fe	227
mbed_official	340:28d1f895c6fe	228	}RCC_PeriphCLKInitTypeDef;
mbed_official	340:28d1f895c6fe	229	#endif /* STM32F091xC \|\| STM32F098xx */
mbed_official	340:28d1f895c6fe	230
mbed_official	340:28d1f895c6fe	231	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
mbed_official	340:28d1f895c6fe	232	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
mbed_official	340:28d1f895c6fe	233	defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	340:28d1f895c6fe	234
mbed_official	340:28d1f895c6fe	235	/**
mbed_official	340:28d1f895c6fe	236	* @brief RCC_CRS Init structure definition
mbed_official	340:28d1f895c6fe	237	*/
mbed_official	340:28d1f895c6fe	238	typedef struct
mbed_official	340:28d1f895c6fe	239	{
mbed_official	340:28d1f895c6fe	240	uint32_t Prescaler; /*!< Specifies the division factor of the SYNC signal.
mbed_official	340:28d1f895c6fe	241	This parameter can be a value of @ref RCCEx_CRS_SynchroDivider */
mbed_official	340:28d1f895c6fe	242
mbed_official	340:28d1f895c6fe	243	uint32_t Source; /*!< Specifies the SYNC signal source.
mbed_official	340:28d1f895c6fe	244	This parameter can be a value of @ref RCCEx_CRS_SynchroSource */
mbed_official	340:28d1f895c6fe	245
mbed_official	340:28d1f895c6fe	246	uint32_t Polarity; /*!< Specifies the input polarity for the SYNC signal source.
mbed_official	340:28d1f895c6fe	247	This parameter can be a value of @ref RCCEx_CRS_SynchroPolarity */
mbed_official	340:28d1f895c6fe	248
mbed_official	340:28d1f895c6fe	249	uint32_t ReloadValue; /*!< Specifies the value to be loaded in the frequency error counter with each SYNC event.
mbed_official	340:28d1f895c6fe	250	It can be calculated in using macro __HAL_RCC_CRS_CALCULATE_RELOADVALUE(_FTARGET_, _FSYNC_)
mbed_official	340:28d1f895c6fe	251	This parameter must be a number between 0 and 0xFFFF or a value of @ref RCCEx_CRS_ReloadValueDefault .*/
mbed_official	340:28d1f895c6fe	252
mbed_official	340:28d1f895c6fe	253	uint32_t ErrorLimitValue; /*!< Specifies the value to be used to evaluate the captured frequency error value.
mbed_official	340:28d1f895c6fe	254	This parameter must be a number between 0 and 0xFF or a value of @ref RCCEx_CRS_ErrorLimitDefault */
mbed_official	340:28d1f895c6fe	255
mbed_official	340:28d1f895c6fe	256	uint32_t HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value to the HSI48 oscillator.
mbed_official	340:28d1f895c6fe	257	This parameter must be a number between 0 and 0x3F or a value of @ref RCCEx_CRS_HSI48CalibrationDefault */
mbed_official	340:28d1f895c6fe	258
mbed_official	340:28d1f895c6fe	259	}RCC_CRSInitTypeDef;
mbed_official	340:28d1f895c6fe	260
mbed_official	340:28d1f895c6fe	261	/**
mbed_official	340:28d1f895c6fe	262	* @brief RCC_CRS Synchronization structure definition
mbed_official	340:28d1f895c6fe	263	*/
mbed_official	340:28d1f895c6fe	264	typedef struct
mbed_official	340:28d1f895c6fe	265	{
mbed_official	340:28d1f895c6fe	266	uint32_t ReloadValue; /*!< Specifies the value loaded in the Counter reload value.
mbed_official	340:28d1f895c6fe	267	This parameter must be a number between 0 and 0xFFFF*/
mbed_official	340:28d1f895c6fe	268
mbed_official	340:28d1f895c6fe	269	uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48 oscillator smooth trimming.
mbed_official	340:28d1f895c6fe	270	This parameter must be a number between 0 and 0x3F */
mbed_official	340:28d1f895c6fe	271
mbed_official	340:28d1f895c6fe	272	uint32_t FreqErrorCapture; /*!< Specifies the value loaded in the .FECAP, the frequency error counter
mbed_official	340:28d1f895c6fe	273	value latched in the time of the last SYNC event.
mbed_official	340:28d1f895c6fe	274	This parameter must be a number between 0 and 0xFFFF */
mbed_official	340:28d1f895c6fe	275
mbed_official	340:28d1f895c6fe	276	uint32_t FreqErrorDirection; /*!< Specifies the value loaded in the .FEDIR, the counting direction of the
mbed_official	340:28d1f895c6fe	277	frequency error counter latched in the time of the last SYNC event.
mbed_official	340:28d1f895c6fe	278	It shows whether the actual frequency is below or above the target.
mbed_official	340:28d1f895c6fe	279	This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/
mbed_official	340:28d1f895c6fe	280
mbed_official	340:28d1f895c6fe	281	}RCC_CRSSynchroInfoTypeDef;
mbed_official	340:28d1f895c6fe	282
mbed_official	441:d2c15dda23c1	283	#endif /* STM32F042x6 \|\| STM32F048xx */
mbed_official	340:28d1f895c6fe	284	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
mbed_official	340:28d1f895c6fe	285	/* STM32F091xC \|\| STM32F098xx */
mbed_official	340:28d1f895c6fe	286
mbed_official	340:28d1f895c6fe	287	/**
mbed_official	340:28d1f895c6fe	288	* @}
mbed_official	340:28d1f895c6fe	289	*/
mbed_official	340:28d1f895c6fe	290
mbed_official	340:28d1f895c6fe	291	/* Exported constants --------------------------------------------------------*/
mbed_official	340:28d1f895c6fe	292
mbed_official	340:28d1f895c6fe	293	/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
mbed_official	340:28d1f895c6fe	294	* @{
mbed_official	340:28d1f895c6fe	295	*/
mbed_official	340:28d1f895c6fe	296
mbed_official	441:d2c15dda23c1	297	/** @defgroup RCCEx_CRS_Status RCCEx CRS Status
mbed_official	441:d2c15dda23c1	298	* @{
mbed_official	441:d2c15dda23c1	299	*/
mbed_official	441:d2c15dda23c1	300	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
mbed_official	441:d2c15dda23c1	301	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
mbed_official	441:d2c15dda23c1	302	defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	441:d2c15dda23c1	303
mbed_official	441:d2c15dda23c1	304	#define RCC_CRS_NONE ((uint32_t)0x00000000)
mbed_official	441:d2c15dda23c1	305	#define RCC_CRS_TIMEOUT ((uint32_t)0x00000001)
mbed_official	441:d2c15dda23c1	306	#define RCC_CRS_SYNCOK ((uint32_t)0x00000002)
mbed_official	441:d2c15dda23c1	307	#define RCC_CRS_SYNCWARM ((uint32_t)0x00000004)
mbed_official	441:d2c15dda23c1	308	#define RCC_CRS_SYNCERR ((uint32_t)0x00000008)
mbed_official	441:d2c15dda23c1	309	#define RCC_CRS_SYNCMISS ((uint32_t)0x00000010)
mbed_official	441:d2c15dda23c1	310	#define RCC_CRS_TRIMOV ((uint32_t)0x00000020)
mbed_official	441:d2c15dda23c1	311
mbed_official	441:d2c15dda23c1	312	#endif /* STM32F042x6 \|\| STM32F048xx */
mbed_official	441:d2c15dda23c1	313	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
mbed_official	441:d2c15dda23c1	314	/* STM32F091xC \|\| STM32F098xx */
mbed_official	441:d2c15dda23c1	315	/**
mbed_official	441:d2c15dda23c1	316	* @}
mbed_official	441:d2c15dda23c1	317	*/
mbed_official	441:d2c15dda23c1	318
mbed_official	340:28d1f895c6fe	319	/** @defgroup RCCEx_Periph_Clock_Selection RCCEx Periph Clock Selection
mbed_official	340:28d1f895c6fe	320	* @{
mbed_official	340:28d1f895c6fe	321	*/
mbed_official	441:d2c15dda23c1	322	#if defined(STM32F030x6) \|\| defined(STM32F030x8) \|\| defined(STM32F031x6) \|\| defined(STM32F038xx) \|\| \
mbed_official	441:d2c15dda23c1	323	defined(STM32F030xC)
mbed_official	340:28d1f895c6fe	324	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
mbed_official	340:28d1f895c6fe	325	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
mbed_official	340:28d1f895c6fe	326	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
mbed_official	340:28d1f895c6fe	327
mbed_official	340:28d1f895c6fe	328	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_I2C1 \| \
mbed_official	340:28d1f895c6fe	329	RCC_PERIPHCLK_RTC))
mbed_official	441:d2c15dda23c1	330	#endif /* STM32F030x6 \|\| STM32F030x8 \|\| STM32F031x6 \|\| STM32F038xx \|\|
mbed_official	441:d2c15dda23c1	331	STM32F030xC */
mbed_official	441:d2c15dda23c1	332
mbed_official	441:d2c15dda23c1	333	#if defined(STM32F070x6) \|\| defined(STM32F070xB)
mbed_official	441:d2c15dda23c1	334	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
mbed_official	441:d2c15dda23c1	335	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
mbed_official	441:d2c15dda23c1	336	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
mbed_official	441:d2c15dda23c1	337	#define RCC_PERIPHCLK_USB ((uint32_t)0x00020000)
mbed_official	441:d2c15dda23c1	338
mbed_official	441:d2c15dda23c1	339	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_I2C1 \| \
mbed_official	441:d2c15dda23c1	340	RCC_PERIPHCLK_RTC \| RCC_PERIPHCLK_USB))
mbed_official	441:d2c15dda23c1	341	#endif /* STM32F070x6 \|\| STM32F070xB */
mbed_official	340:28d1f895c6fe	342
mbed_official	340:28d1f895c6fe	343	#if defined(STM32F042x6) \|\| defined(STM32F048xx)
mbed_official	340:28d1f895c6fe	344	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
mbed_official	340:28d1f895c6fe	345	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
mbed_official	340:28d1f895c6fe	346	#define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400)
mbed_official	340:28d1f895c6fe	347	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
mbed_official	340:28d1f895c6fe	348	#define RCC_PERIPHCLK_USB ((uint32_t)0x00020000)
mbed_official	340:28d1f895c6fe	349
mbed_official	340:28d1f895c6fe	350	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_I2C1 \| \
mbed_official	340:28d1f895c6fe	351	RCC_PERIPHCLK_CEC \| RCC_PERIPHCLK_RTC \| \
mbed_official	340:28d1f895c6fe	352	RCC_PERIPHCLK_USB))
mbed_official	340:28d1f895c6fe	353	#endif /* STM32F042x6 \|\| STM32F048xx */
mbed_official	340:28d1f895c6fe	354
mbed_official	340:28d1f895c6fe	355	#if defined(STM32F051x8) \|\| defined(STM32F058xx)
mbed_official	340:28d1f895c6fe	356	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
mbed_official	340:28d1f895c6fe	357	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
mbed_official	340:28d1f895c6fe	358	#define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400)
mbed_official	340:28d1f895c6fe	359	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
mbed_official	340:28d1f895c6fe	360
mbed_official	340:28d1f895c6fe	361	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_I2C1 \| \
mbed_official	340:28d1f895c6fe	362	RCC_PERIPHCLK_CEC \| RCC_PERIPHCLK_RTC))
mbed_official	340:28d1f895c6fe	363	#endif /* STM32F051x8 \|\| STM32F058xx */
mbed_official	340:28d1f895c6fe	364
mbed_official	340:28d1f895c6fe	365	#if defined(STM32F071xB)
mbed_official	340:28d1f895c6fe	366	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
mbed_official	340:28d1f895c6fe	367	#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
mbed_official	340:28d1f895c6fe	368	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
mbed_official	340:28d1f895c6fe	369	#define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400)
mbed_official	340:28d1f895c6fe	370	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
mbed_official	340:28d1f895c6fe	371
mbed_official	340:28d1f895c6fe	372	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| \
mbed_official	340:28d1f895c6fe	373	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_CEC \| \
mbed_official	340:28d1f895c6fe	374	RCC_PERIPHCLK_RTC))
mbed_official	340:28d1f895c6fe	375	#endif /* STM32F071xB */
mbed_official	340:28d1f895c6fe	376
mbed_official	340:28d1f895c6fe	377	#if defined(STM32F072xB) \|\| defined(STM32F078xx)
mbed_official	340:28d1f895c6fe	378	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
mbed_official	340:28d1f895c6fe	379	#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
mbed_official	340:28d1f895c6fe	380	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
mbed_official	340:28d1f895c6fe	381	#define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400)
mbed_official	340:28d1f895c6fe	382	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
mbed_official	340:28d1f895c6fe	383	#define RCC_PERIPHCLK_USB ((uint32_t)0x00020000)
mbed_official	340:28d1f895c6fe	384
mbed_official	340:28d1f895c6fe	385	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| \
mbed_official	340:28d1f895c6fe	386	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_CEC \| \
mbed_official	340:28d1f895c6fe	387	RCC_PERIPHCLK_RTC \| RCC_PERIPHCLK_USB))
mbed_official	340:28d1f895c6fe	388	#endif /* STM32F072xB \|\| STM32F078xx */
mbed_official	340:28d1f895c6fe	389
mbed_official	340:28d1f895c6fe	390	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	340:28d1f895c6fe	391	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
mbed_official	340:28d1f895c6fe	392	#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
mbed_official	340:28d1f895c6fe	393	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
mbed_official	340:28d1f895c6fe	394	#define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400)
mbed_official	340:28d1f895c6fe	395	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
mbed_official	340:28d1f895c6fe	396	#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00040000)
mbed_official	340:28d1f895c6fe	397
mbed_official	340:28d1f895c6fe	398	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| \
mbed_official	340:28d1f895c6fe	399	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_CEC \| \
mbed_official	340:28d1f895c6fe	400	RCC_PERIPHCLK_RTC \| RCC_PERIPHCLK_USART3 ))
mbed_official	340:28d1f895c6fe	401	#endif /* STM32F091xC \|\| STM32F098xx */
mbed_official	340:28d1f895c6fe	402
mbed_official	340:28d1f895c6fe	403	/**
mbed_official	340:28d1f895c6fe	404	* @}
mbed_official	340:28d1f895c6fe	405	*/
mbed_official	340:28d1f895c6fe	406
mbed_official	340:28d1f895c6fe	407	/** @defgroup RCCEx_MCO_Clock_Source RCCEx MCO Clock Source
mbed_official	340:28d1f895c6fe	408	* @{
mbed_official	340:28d1f895c6fe	409	*/
mbed_official	340:28d1f895c6fe	410
mbed_official	441:d2c15dda23c1	411	#if defined(STM32F030x6) \|\| defined(STM32F031x6) \|\| defined(STM32F038xx) \|\| defined(STM32F070x6) \|\| defined(STM32F070xB) \|\| defined(STM32F030xC)
mbed_official	340:28d1f895c6fe	412
mbed_official	340:28d1f895c6fe	413	#define RCC_MCOSOURCE_PLLCLK_NODIV (RCC_CFGR_MCO_PLL \| RCC_CFGR_PLLNODIV)
mbed_official	340:28d1f895c6fe	414
mbed_official	340:28d1f895c6fe	415	#define IS_RCC_MCOSOURCE(SOURCE) (((SOURCE) == RCC_MCOSOURCE_NONE) \|\| \
mbed_official	340:28d1f895c6fe	416	((SOURCE) == RCC_MCOSOURCE_LSI) \|\| \
mbed_official	340:28d1f895c6fe	417	((SOURCE) == RCC_MCOSOURCE_LSE) \|\| \
mbed_official	340:28d1f895c6fe	418	((SOURCE) == RCC_MCOSOURCE_SYSCLK) \|\| \
mbed_official	340:28d1f895c6fe	419	((SOURCE) == RCC_MCOSOURCE_HSI) \|\| \
mbed_official	340:28d1f895c6fe	420	((SOURCE) == RCC_MCOSOURCE_HSE) \|\| \
mbed_official	340:28d1f895c6fe	421	((SOURCE) == RCC_MCOSOURCE_PLLCLK_NODIV) \|\| \
mbed_official	340:28d1f895c6fe	422	((SOURCE) == RCC_MCOSOURCE_PLLCLK_DIV2) \|\| \
mbed_official	340:28d1f895c6fe	423	((SOURCE) == RCC_MCOSOURCE_HSI14))
mbed_official	340:28d1f895c6fe	424
mbed_official	441:d2c15dda23c1	425	#endif /* STM32F030x6 \|\| STM32F031x6 \|\| STM32F038xx \|\| STM32F070x6 \|\| STM32F070xB \|\| STM32F030xC */
mbed_official	340:28d1f895c6fe	426
mbed_official	340:28d1f895c6fe	427	#if defined(STM32F030x8) \|\| defined(STM32F051x8) \|\| defined(STM32F058xx)
mbed_official	340:28d1f895c6fe	428
mbed_official	340:28d1f895c6fe	429	#define IS_RCC_MCOSOURCE(SOURCE) (((SOURCE) == RCC_MCOSOURCE_NONE) \|\| \
mbed_official	340:28d1f895c6fe	430	((SOURCE) == RCC_MCOSOURCE_LSI) \|\| \
mbed_official	340:28d1f895c6fe	431	((SOURCE) == RCC_MCOSOURCE_LSE) \|\| \
mbed_official	340:28d1f895c6fe	432	((SOURCE) == RCC_MCOSOURCE_SYSCLK) \|\| \
mbed_official	340:28d1f895c6fe	433	((SOURCE) == RCC_MCOSOURCE_HSI) \|\| \
mbed_official	340:28d1f895c6fe	434	((SOURCE) == RCC_MCOSOURCE_HSE) \|\| \
mbed_official	340:28d1f895c6fe	435	((SOURCE) == RCC_MCOSOURCE_PLLCLK_DIV2) \|\| \
mbed_official	340:28d1f895c6fe	436	((SOURCE) == RCC_MCOSOURCE_HSI14))
mbed_official	340:28d1f895c6fe	437
mbed_official	340:28d1f895c6fe	438	#endif /* STM32F030x8 \|\| STM32F051x8 \|\| STM32F058xx */
mbed_official	340:28d1f895c6fe	439
mbed_official	340:28d1f895c6fe	440	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
mbed_official	340:28d1f895c6fe	441	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
mbed_official	340:28d1f895c6fe	442	defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	340:28d1f895c6fe	443
mbed_official	340:28d1f895c6fe	444	#define RCC_MCOSOURCE_HSI48 RCC_CFGR_MCO_HSI48
mbed_official	340:28d1f895c6fe	445	#define RCC_MCOSOURCE_PLLCLK_NODIV (RCC_CFGR_MCO_PLL \| RCC_CFGR_PLLNODIV)
mbed_official	340:28d1f895c6fe	446
mbed_official	340:28d1f895c6fe	447	#define IS_RCC_MCOSOURCE(SOURCE) (((SOURCE) == RCC_MCOSOURCE_NONE) \|\| \
mbed_official	340:28d1f895c6fe	448	((SOURCE) == RCC_MCOSOURCE_LSI) \|\| \
mbed_official	340:28d1f895c6fe	449	((SOURCE) == RCC_MCOSOURCE_LSE) \|\| \
mbed_official	340:28d1f895c6fe	450	((SOURCE) == RCC_MCOSOURCE_SYSCLK) \|\| \
mbed_official	340:28d1f895c6fe	451	((SOURCE) == RCC_MCOSOURCE_HSI) \|\| \
mbed_official	340:28d1f895c6fe	452	((SOURCE) == RCC_MCOSOURCE_HSE) \|\| \
mbed_official	340:28d1f895c6fe	453	((SOURCE) == RCC_MCOSOURCE_PLLCLK_NODIV) \|\| \
mbed_official	340:28d1f895c6fe	454	((SOURCE) == RCC_MCOSOURCE_PLLCLK_DIV2) \|\| \
mbed_official	340:28d1f895c6fe	455	((SOURCE) == RCC_MCOSOURCE_HSI14) \|\| \
mbed_official	340:28d1f895c6fe	456	((SOURCE) == RCC_MCOSOURCE_HSI48))
mbed_official	340:28d1f895c6fe	457
mbed_official	340:28d1f895c6fe	458	#define RCC_IT_HSI48 ((uint8_t)0x40)
mbed_official	340:28d1f895c6fe	459
mbed_official	340:28d1f895c6fe	460	/* Flags in the CR2 register */
mbed_official	340:28d1f895c6fe	461	#define RCC_CR2_HSI48RDY_BitNumber 16
mbed_official	340:28d1f895c6fe	462
mbed_official	340:28d1f895c6fe	463	#define RCC_FLAG_HSI48RDY ((uint8_t)((CR2_REG_INDEX << 5) \| RCC_CR2_HSI48RDY_BitNumber))
mbed_official	340:28d1f895c6fe	464
mbed_official	340:28d1f895c6fe	465	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
mbed_official	340:28d1f895c6fe	466	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
mbed_official	340:28d1f895c6fe	467	/* STM32F091xC \|\| STM32F098xx */
mbed_official	340:28d1f895c6fe	468	/**
mbed_official	340:28d1f895c6fe	469	* @}
mbed_official	340:28d1f895c6fe	470	*/
mbed_official	340:28d1f895c6fe	471
mbed_official	340:28d1f895c6fe	472	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)
mbed_official	340:28d1f895c6fe	473
mbed_official	340:28d1f895c6fe	474	/** @defgroup RCCEx_USB_Clock_Source RCCEx USB Clock Source
mbed_official	340:28d1f895c6fe	475	* @{
mbed_official	340:28d1f895c6fe	476	*/
mbed_official	340:28d1f895c6fe	477	#define RCC_USBCLKSOURCE_HSI48 RCC_CFGR3_USBSW_HSI48
mbed_official	340:28d1f895c6fe	478	#define RCC_USBCLKSOURCE_PLLCLK RCC_CFGR3_USBSW_PLLCLK
mbed_official	340:28d1f895c6fe	479
mbed_official	340:28d1f895c6fe	480	#define IS_RCC_USBCLKSOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSOURCE_HSI48) \|\| \
mbed_official	340:28d1f895c6fe	481	((SOURCE) == RCC_USBCLKSOURCE_PLLCLK))
mbed_official	340:28d1f895c6fe	482	/**
mbed_official	340:28d1f895c6fe	483	* @}
mbed_official	340:28d1f895c6fe	484	*/
mbed_official	340:28d1f895c6fe	485
mbed_official	340:28d1f895c6fe	486	#endif /* STM32F042x6 \|\| STM32F048xx \|\| STM32F072xB \|\| STM32F078xx */
mbed_official	340:28d1f895c6fe	487
mbed_official	441:d2c15dda23c1	488	#if defined(STM32F070x6) \|\| defined(STM32F070xB)
mbed_official	441:d2c15dda23c1	489
mbed_official	441:d2c15dda23c1	490	/** @defgroup RCCEx_USB_Clock_Source RCCEx USB Clock Source
mbed_official	441:d2c15dda23c1	491	* @{
mbed_official	441:d2c15dda23c1	492	*/
mbed_official	441:d2c15dda23c1	493	#define RCC_USBCLKSOURCE_PLLCLK RCC_CFGR3_USBSW_PLLCLK
mbed_official	441:d2c15dda23c1	494
mbed_official	441:d2c15dda23c1	495	#define IS_RCC_USBCLKSOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSOURCE_PLLCLK))
mbed_official	441:d2c15dda23c1	496	/**
mbed_official	441:d2c15dda23c1	497	* @}
mbed_official	441:d2c15dda23c1	498	*/
mbed_official	441:d2c15dda23c1	499
mbed_official	441:d2c15dda23c1	500	#endif /* STM32F070x6 \|\| STM32F070xB */
mbed_official	441:d2c15dda23c1	501
mbed_official	340:28d1f895c6fe	502	#if defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
mbed_official	340:28d1f895c6fe	503	defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	340:28d1f895c6fe	504
mbed_official	340:28d1f895c6fe	505	/** @defgroup RCCEx_USART2_Clock_Source RCCEx USART2 Clock Source
mbed_official	340:28d1f895c6fe	506	* @{
mbed_official	340:28d1f895c6fe	507	*/
mbed_official	340:28d1f895c6fe	508	#define RCC_USART2CLKSOURCE_PCLK1 RCC_CFGR3_USART2SW_PCLK
mbed_official	340:28d1f895c6fe	509	#define RCC_USART2CLKSOURCE_SYSCLK RCC_CFGR3_USART2SW_SYSCLK
mbed_official	340:28d1f895c6fe	510	#define RCC_USART2CLKSOURCE_LSE RCC_CFGR3_USART2SW_LSE
mbed_official	340:28d1f895c6fe	511	#define RCC_USART2CLKSOURCE_HSI RCC_CFGR3_USART2SW_HSI
mbed_official	340:28d1f895c6fe	512
mbed_official	340:28d1f895c6fe	513	#define IS_RCC_USART2CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART2CLKSOURCE_PCLK1) \|\| \
mbed_official	340:28d1f895c6fe	514	((SOURCE) == RCC_USART2CLKSOURCE_SYSCLK) \|\| \
mbed_official	340:28d1f895c6fe	515	((SOURCE) == RCC_USART2CLKSOURCE_LSE) \|\| \
mbed_official	340:28d1f895c6fe	516	((SOURCE) == RCC_USART2CLKSOURCE_HSI))
mbed_official	340:28d1f895c6fe	517	/**
mbed_official	340:28d1f895c6fe	518	* @}
mbed_official	340:28d1f895c6fe	519	*/
mbed_official	340:28d1f895c6fe	520
mbed_official	340:28d1f895c6fe	521	#endif /* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
mbed_official	340:28d1f895c6fe	522	/* STM32F091xC \|\| STM32F098xx */
mbed_official	340:28d1f895c6fe	523
mbed_official	340:28d1f895c6fe	524	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	340:28d1f895c6fe	525
mbed_official	340:28d1f895c6fe	526	/** @defgroup RCCEx_USART3_Clock_Source RCCEx USART3 Clock Source
mbed_official	340:28d1f895c6fe	527	* @{
mbed_official	340:28d1f895c6fe	528	*/
mbed_official	340:28d1f895c6fe	529	#define RCC_USART3CLKSOURCE_PCLK1 RCC_CFGR3_USART3SW_PCLK
mbed_official	340:28d1f895c6fe	530	#define RCC_USART3CLKSOURCE_SYSCLK RCC_CFGR3_USART3SW_SYSCLK
mbed_official	340:28d1f895c6fe	531	#define RCC_USART3CLKSOURCE_LSE RCC_CFGR3_USART3SW_LSE
mbed_official	340:28d1f895c6fe	532	#define RCC_USART3CLKSOURCE_HSI RCC_CFGR3_USART3SW_HSI
mbed_official	340:28d1f895c6fe	533
mbed_official	340:28d1f895c6fe	534	#define IS_RCC_USART3CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART3CLKSOURCE_PCLK1) \|\| \
mbed_official	340:28d1f895c6fe	535	((SOURCE) == RCC_USART3CLKSOURCE_SYSCLK) \|\| \
mbed_official	340:28d1f895c6fe	536	((SOURCE) == RCC_USART3CLKSOURCE_LSE) \|\| \
mbed_official	340:28d1f895c6fe	537	((SOURCE) == RCC_USART3CLKSOURCE_HSI))
mbed_official	340:28d1f895c6fe	538	/**
mbed_official	340:28d1f895c6fe	539	* @}
mbed_official	340:28d1f895c6fe	540	*/
mbed_official	340:28d1f895c6fe	541
mbed_official	340:28d1f895c6fe	542	#endif /* STM32F091xC \|\| STM32F098xx */
mbed_official	340:28d1f895c6fe	543
mbed_official	340:28d1f895c6fe	544
mbed_official	340:28d1f895c6fe	545	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
mbed_official	340:28d1f895c6fe	546	defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
mbed_official	340:28d1f895c6fe	547	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
mbed_official	340:28d1f895c6fe	548	defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	340:28d1f895c6fe	549
mbed_official	340:28d1f895c6fe	550	/** @defgroup RCCEx_CEC_Clock_Source RCCEx CEC Clock Source
mbed_official	340:28d1f895c6fe	551	* @{
mbed_official	340:28d1f895c6fe	552	*/
mbed_official	340:28d1f895c6fe	553	#define RCC_CECCLKSOURCE_HSI RCC_CFGR3_CECSW_HSI_DIV244
mbed_official	340:28d1f895c6fe	554	#define RCC_CECCLKSOURCE_LSE RCC_CFGR3_CECSW_LSE
mbed_official	340:28d1f895c6fe	555
mbed_official	340:28d1f895c6fe	556	#define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_HSI) \|\| \
mbed_official	340:28d1f895c6fe	557	((SOURCE) == RCC_CECCLKSOURCE_LSE))
mbed_official	340:28d1f895c6fe	558	/**
mbed_official	340:28d1f895c6fe	559	* @}
mbed_official	340:28d1f895c6fe	560	*/
mbed_official	340:28d1f895c6fe	561
mbed_official	340:28d1f895c6fe	562	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
mbed_official	340:28d1f895c6fe	563	/* STM32F051x8 \|\| STM32F058xx \|\| */
mbed_official	340:28d1f895c6fe	564	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
mbed_official	340:28d1f895c6fe	565	/* STM32F091xC \|\| STM32F098xx */
mbed_official	340:28d1f895c6fe	566
mbed_official	340:28d1f895c6fe	567	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
mbed_official	340:28d1f895c6fe	568	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
mbed_official	340:28d1f895c6fe	569	defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	340:28d1f895c6fe	570
mbed_official	340:28d1f895c6fe	571	/** @defgroup RCCEx_PLL_Clock_Source RCCEx PLL Clock Source
mbed_official	340:28d1f895c6fe	572	* @{
mbed_official	340:28d1f895c6fe	573	*/
mbed_official	340:28d1f895c6fe	574	#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_PREDIV
mbed_official	340:28d1f895c6fe	575	#define RCC_PLLSOURCE_HSI48 RCC_CFGR_PLLSRC_HSI48_PREDIV
mbed_official	340:28d1f895c6fe	576
mbed_official	340:28d1f895c6fe	577	#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) \|\| \
mbed_official	340:28d1f895c6fe	578	((SOURCE) == RCC_PLLSOURCE_HSI48) \|\| \
mbed_official	340:28d1f895c6fe	579	((SOURCE) == RCC_PLLSOURCE_HSE))
mbed_official	340:28d1f895c6fe	580	/**
mbed_official	340:28d1f895c6fe	581	* @}
mbed_official	340:28d1f895c6fe	582	*/
mbed_official	340:28d1f895c6fe	583
mbed_official	340:28d1f895c6fe	584	/** @defgroup RCCEx_System_Clock_Source RCCEx System Clock Source
mbed_official	340:28d1f895c6fe	585	* @{
mbed_official	340:28d1f895c6fe	586	*/
mbed_official	340:28d1f895c6fe	587	#define RCC_SYSCLKSOURCE_HSI48 RCC_CFGR_SW_HSI48
mbed_official	340:28d1f895c6fe	588
mbed_official	340:28d1f895c6fe	589	#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) \|\| \
mbed_official	340:28d1f895c6fe	590	((SOURCE) == RCC_SYSCLKSOURCE_HSE) \|\| \
mbed_official	340:28d1f895c6fe	591	((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK) \|\| \
mbed_official	340:28d1f895c6fe	592	((SOURCE) == RCC_SYSCLKSOURCE_HSI48))
mbed_official	340:28d1f895c6fe	593
mbed_official	340:28d1f895c6fe	594	#define RCC_SYSCLKSOURCE_STATUS_HSI48 RCC_CFGR_SWS_HSI48
mbed_official	340:28d1f895c6fe	595
mbed_official	340:28d1f895c6fe	596	#define IS_RCC_SYSCLKSOURCE_STATUS(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI) \|\| \
mbed_official	340:28d1f895c6fe	597	((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSE) \|\| \
mbed_official	340:28d1f895c6fe	598	((SOURCE) == RCC_SYSCLKSOURCE_STATUS_PLLCLK) \|\| \
mbed_official	340:28d1f895c6fe	599	((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI48))
mbed_official	340:28d1f895c6fe	600	/**
mbed_official	340:28d1f895c6fe	601	* @}
mbed_official	340:28d1f895c6fe	602	*/
mbed_official	340:28d1f895c6fe	603
mbed_official	340:28d1f895c6fe	604	/** @defgroup RCCEx_HSI48_Config RCCEx HSI48 Config
mbed_official	340:28d1f895c6fe	605	* @{
mbed_official	340:28d1f895c6fe	606	*/
mbed_official	340:28d1f895c6fe	607	#define RCC_HSI48_OFF ((uint8_t)0x00)
mbed_official	340:28d1f895c6fe	608	#define RCC_HSI48_ON ((uint8_t)0x01)
mbed_official	340:28d1f895c6fe	609
mbed_official	340:28d1f895c6fe	610	#define IS_RCC_HSI48(HSI48) (((HSI48) == RCC_HSI48_OFF) \|\| ((HSI48) == RCC_HSI48_ON))
mbed_official	340:28d1f895c6fe	611	/**
mbed_official	340:28d1f895c6fe	612	* @}
mbed_official	340:28d1f895c6fe	613	*/
mbed_official	340:28d1f895c6fe	614	#else
mbed_official	340:28d1f895c6fe	615	/** @defgroup RCCEx_PLL_Clock_Source RCCEx PLL Clock Source
mbed_official	340:28d1f895c6fe	616	* @{
mbed_official	340:28d1f895c6fe	617	*/
mbed_official	441:d2c15dda23c1	618
mbed_official	441:d2c15dda23c1	619	#if defined(STM32F070xB) \|\| defined(STM32F070x6) \|\| defined(STM32F030xC)
mbed_official	441:d2c15dda23c1	620	#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_PREDIV
mbed_official	441:d2c15dda23c1	621	#else
mbed_official	340:28d1f895c6fe	622	#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_DIV2
mbed_official	441:d2c15dda23c1	623	#endif
mbed_official	340:28d1f895c6fe	624
mbed_official	340:28d1f895c6fe	625	#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) \|\| \
mbed_official	340:28d1f895c6fe	626	((SOURCE) == RCC_PLLSOURCE_HSE))
mbed_official	340:28d1f895c6fe	627	/**
mbed_official	340:28d1f895c6fe	628	* @}
mbed_official	340:28d1f895c6fe	629	*/
mbed_official	340:28d1f895c6fe	630
mbed_official	340:28d1f895c6fe	631	/** @defgroup RCCEx_System_Clock_Source RCCEx System Clock Source
mbed_official	340:28d1f895c6fe	632	* @{
mbed_official	340:28d1f895c6fe	633	*/
mbed_official	340:28d1f895c6fe	634	#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) \|\| \
mbed_official	340:28d1f895c6fe	635	((SOURCE) == RCC_SYSCLKSOURCE_HSE) \|\| \
mbed_official	340:28d1f895c6fe	636	((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK))
mbed_official	340:28d1f895c6fe	637
mbed_official	340:28d1f895c6fe	638	#define IS_RCC_SYSCLKSOURCE_STATUS(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI) \|\| \
mbed_official	340:28d1f895c6fe	639	((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSE) \|\| \
mbed_official	340:28d1f895c6fe	640	((SOURCE) == RCC_SYSCLKSOURCE_STATUS_PLLCLK))
mbed_official	340:28d1f895c6fe	641	/**
mbed_official	340:28d1f895c6fe	642	* @}
mbed_official	340:28d1f895c6fe	643	*/
mbed_official	340:28d1f895c6fe	644
mbed_official	340:28d1f895c6fe	645	/** @defgroup RCCEx_HSI48_Config RCCEx HSI48 Config
mbed_official	340:28d1f895c6fe	646	* @{
mbed_official	340:28d1f895c6fe	647	*/
mbed_official	340:28d1f895c6fe	648	#define RCC_HSI48_OFF ((uint8_t)0x00)
mbed_official	340:28d1f895c6fe	649
mbed_official	340:28d1f895c6fe	650	#define IS_RCC_HSI48(HSI48) (((HSI48) == RCC_HSI48_OFF))
mbed_official	340:28d1f895c6fe	651	/**
mbed_official	340:28d1f895c6fe	652	* @}
mbed_official	340:28d1f895c6fe	653	*/
mbed_official	340:28d1f895c6fe	654
mbed_official	340:28d1f895c6fe	655	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
mbed_official	340:28d1f895c6fe	656	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
mbed_official	340:28d1f895c6fe	657	/* STM32F091xC \|\| STM32F098xx */
mbed_official	340:28d1f895c6fe	658
mbed_official	340:28d1f895c6fe	659
mbed_official	340:28d1f895c6fe	660	/** @defgroup RCCEx_MCOx_Clock_Prescaler RCCEx MCOx Clock Prescaler
mbed_official	340:28d1f895c6fe	661	* @{
mbed_official	340:28d1f895c6fe	662	*/
mbed_official	340:28d1f895c6fe	663
mbed_official	340:28d1f895c6fe	664	#if defined(STM32F030x8) \|\| defined(STM32F051x8) \|\| defined(STM32F058xx)
mbed_official	340:28d1f895c6fe	665
mbed_official	340:28d1f895c6fe	666	#define RCC_MCO_NODIV ((uint32_t)0x00000000)
mbed_official	340:28d1f895c6fe	667
mbed_official	340:28d1f895c6fe	668	#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCO_NODIV))
mbed_official	340:28d1f895c6fe	669
mbed_official	340:28d1f895c6fe	670	#endif /* STM32F030x8 \|\| STM32F051x8 \|\| STM32F058xx */
mbed_official	340:28d1f895c6fe	671
mbed_official	441:d2c15dda23c1	672	#if defined(STM32F030x6) \|\| defined(STM32F031x6) \|\| defined(STM32F038xx) \|\| defined(STM32F070x6) \|\| \
mbed_official	441:d2c15dda23c1	673	defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F071xB) \|\| defined(STM32F070xB) \|\| \
mbed_official	340:28d1f895c6fe	674	defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
mbed_official	441:d2c15dda23c1	675	defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
mbed_official	340:28d1f895c6fe	676
mbed_official	340:28d1f895c6fe	677	#define RCC_MCO_DIV1 ((uint32_t)0x00000000)
mbed_official	340:28d1f895c6fe	678	#define RCC_MCO_DIV2 ((uint32_t)0x10000000)
mbed_official	340:28d1f895c6fe	679	#define RCC_MCO_DIV4 ((uint32_t)0x20000000)
mbed_official	340:28d1f895c6fe	680	#define RCC_MCO_DIV8 ((uint32_t)0x30000000)
mbed_official	340:28d1f895c6fe	681	#define RCC_MCO_DIV16 ((uint32_t)0x40000000)
mbed_official	340:28d1f895c6fe	682	#define RCC_MCO_DIV32 ((uint32_t)0x50000000)
mbed_official	340:28d1f895c6fe	683	#define RCC_MCO_DIV64 ((uint32_t)0x60000000)
mbed_official	340:28d1f895c6fe	684	#define RCC_MCO_DIV128 ((uint32_t)0x70000000)
mbed_official	340:28d1f895c6fe	685
mbed_official	340:28d1f895c6fe	686	#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCO_DIV1) \|\| ((DIV) == RCC_MCO_DIV2) \|\| \
mbed_official	340:28d1f895c6fe	687	((DIV) == RCC_MCO_DIV4) \|\| ((DIV) == RCC_MCO_DIV8) \|\| \
mbed_official	340:28d1f895c6fe	688	((DIV) == RCC_MCO_DIV16) \|\| ((DIV) == RCC_MCO_DIV32) \|\| \
mbed_official	340:28d1f895c6fe	689	((DIV) == RCC_MCO_DIV64) \|\| ((DIV) == RCC_MCO_DIV128))
mbed_official	340:28d1f895c6fe	690
mbed_official	340:28d1f895c6fe	691	#endif /* STM32F030x6 \|\| STM32F031x6 \|\| STM32F038xx \|\| STM32F042x6 \|\| STM32F048xx \|\| */
mbed_official	441:d2c15dda23c1	692	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070x6 \|\| STM32F070xB */
mbed_official	441:d2c15dda23c1	693	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
mbed_official	340:28d1f895c6fe	694
mbed_official	340:28d1f895c6fe	695	/**
mbed_official	340:28d1f895c6fe	696	* @}
mbed_official	340:28d1f895c6fe	697	*/
mbed_official	340:28d1f895c6fe	698
mbed_official	340:28d1f895c6fe	699	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
mbed_official	340:28d1f895c6fe	700	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
mbed_official	340:28d1f895c6fe	701	defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	340:28d1f895c6fe	702
mbed_official	340:28d1f895c6fe	703	/** @defgroup RCCEx_CRS_SynchroSource RCCEx CRS SynchroSource
mbed_official	340:28d1f895c6fe	704	* @{
mbed_official	340:28d1f895c6fe	705	*/
mbed_official	340:28d1f895c6fe	706	#define RCC_CRS_SYNC_SOURCE_GPIO ((uint32_t)0x00) /!< Synchro Signal soucre GPIO /
mbed_official	340:28d1f895c6fe	707	#define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /!< Synchro Signal source LSE /
mbed_official	340:28d1f895c6fe	708	#define RCC_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /!< Synchro Signal source USB SOF (default)/
mbed_official	340:28d1f895c6fe	709
mbed_official	340:28d1f895c6fe	710	#define IS_RCC_CRS_SYNC_SOURCE(_SOURCE_) (((_SOURCE_) == RCC_CRS_SYNC_SOURCE_GPIO) \|\| \
mbed_official	340:28d1f895c6fe	711	((_SOURCE_) == RCC_CRS_SYNC_SOURCE_LSE) \|\| \
mbed_official	340:28d1f895c6fe	712	((_SOURCE_) == RCC_CRS_SYNC_SOURCE_USB))
mbed_official	340:28d1f895c6fe	713	/**
mbed_official	340:28d1f895c6fe	714	* @}
mbed_official	340:28d1f895c6fe	715	*/
mbed_official	340:28d1f895c6fe	716
mbed_official	340:28d1f895c6fe	717	/** @defgroup RCCEx_CRS_SynchroDivider RCCEx CRS SynchroDivider
mbed_official	340:28d1f895c6fe	718	* @{
mbed_official	340:28d1f895c6fe	719	*/
mbed_official	340:28d1f895c6fe	720	#define RCC_CRS_SYNC_DIV1 ((uint32_t)0x00) /!< Synchro Signal not divided (default) /
mbed_official	340:28d1f895c6fe	721	#define RCC_CRS_SYNC_DIV2 CRS_CFGR_SYNCDIV_0 /!< Synchro Signal divided by 2 /
mbed_official	340:28d1f895c6fe	722	#define RCC_CRS_SYNC_DIV4 CRS_CFGR_SYNCDIV_1 /!< Synchro Signal divided by 4 /
mbed_official	340:28d1f895c6fe	723	#define RCC_CRS_SYNC_DIV8 (CRS_CFGR_SYNCDIV_1 \| CRS_CFGR_SYNCDIV_0) /!< Synchro Signal divided by 8 /
mbed_official	340:28d1f895c6fe	724	#define RCC_CRS_SYNC_DIV16 CRS_CFGR_SYNCDIV_2 /!< Synchro Signal divided by 16 /
mbed_official	340:28d1f895c6fe	725	#define RCC_CRS_SYNC_DIV32 (CRS_CFGR_SYNCDIV_2 \| CRS_CFGR_SYNCDIV_0) /!< Synchro Signal divided by 32 /
mbed_official	340:28d1f895c6fe	726	#define RCC_CRS_SYNC_DIV64 (CRS_CFGR_SYNCDIV_2 \| CRS_CFGR_SYNCDIV_1) /!< Synchro Signal divided by 64 /
mbed_official	340:28d1f895c6fe	727	#define RCC_CRS_SYNC_DIV128 CRS_CFGR_SYNCDIV /!< Synchro Signal divided by 128 /
mbed_official	340:28d1f895c6fe	728
mbed_official	340:28d1f895c6fe	729	#define IS_RCC_CRS_SYNC_DIV(_DIV_) (((_DIV_) == RCC_CRS_SYNC_DIV1) \|\| ((_DIV_) == RCC_CRS_SYNC_DIV2) \|\| \
mbed_official	340:28d1f895c6fe	730	((_DIV_) == RCC_CRS_SYNC_DIV4) \|\| ((_DIV_) == RCC_CRS_SYNC_DIV8) \|\| \
mbed_official	340:28d1f895c6fe	731	((_DIV_) == RCC_CRS_SYNC_DIV16) \|\| ((_DIV_) == RCC_CRS_SYNC_DIV32) \|\| \
mbed_official	340:28d1f895c6fe	732	((_DIV_) == RCC_CRS_SYNC_DIV64) \|\| ((_DIV_) == RCC_CRS_SYNC_DIV128))
mbed_official	340:28d1f895c6fe	733	/**
mbed_official	340:28d1f895c6fe	734	* @}
mbed_official	340:28d1f895c6fe	735	*/
mbed_official	340:28d1f895c6fe	736
mbed_official	340:28d1f895c6fe	737	/** @defgroup RCCEx_CRS_SynchroPolarity RCCEx CRS SynchroPolarity
mbed_official	340:28d1f895c6fe	738	* @{
mbed_official	340:28d1f895c6fe	739	*/
mbed_official	340:28d1f895c6fe	740	#define RCC_CRS_SYNC_POLARITY_RISING ((uint32_t)0x00) /!< Synchro Active on rising edge (default) /
mbed_official	340:28d1f895c6fe	741	#define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /!< Synchro Active on falling edge /
mbed_official	340:28d1f895c6fe	742
mbed_official	340:28d1f895c6fe	743	#define IS_RCC_CRS_SYNC_POLARITY(_POLARITY_) (((_POLARITY_) == RCC_CRS_SYNC_POLARITY_RISING) \|\| \
mbed_official	340:28d1f895c6fe	744	((_POLARITY_) == RCC_CRS_SYNC_POLARITY_FALLING))
mbed_official	340:28d1f895c6fe	745	/**
mbed_official	340:28d1f895c6fe	746	* @}
mbed_official	340:28d1f895c6fe	747	*/
mbed_official	340:28d1f895c6fe	748
mbed_official	340:28d1f895c6fe	749	/** @defgroup RCCEx_CRS_ReloadValueDefault RCCEx CRS ReloadValueDefault
mbed_official	340:28d1f895c6fe	750	* @{
mbed_official	340:28d1f895c6fe	751	*/
mbed_official	340:28d1f895c6fe	752	#define RCC_CRS_RELOADVALUE_DEFAULT ((uint32_t)0xBB7F) /*!< The reset value of the RELOAD field corresponds
mbed_official	340:28d1f895c6fe	753	to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */
mbed_official	340:28d1f895c6fe	754
mbed_official	340:28d1f895c6fe	755	#define IS_RCC_CRS_RELOADVALUE(_VALUE_) (((_VALUE_) <= 0xFFFF))
mbed_official	340:28d1f895c6fe	756	/**
mbed_official	340:28d1f895c6fe	757	* @}
mbed_official	340:28d1f895c6fe	758	*/
mbed_official	340:28d1f895c6fe	759
mbed_official	340:28d1f895c6fe	760	/** @defgroup RCCEx_CRS_ErrorLimitDefault RCCEx CRS ErrorLimitDefault
mbed_official	340:28d1f895c6fe	761	* @{
mbed_official	340:28d1f895c6fe	762	*/
mbed_official	340:28d1f895c6fe	763	#define RCC_CRS_ERRORLIMIT_DEFAULT ((uint32_t)0x22) /!< Default Frequency error limit /
mbed_official	340:28d1f895c6fe	764
mbed_official	340:28d1f895c6fe	765	#define IS_RCC_CRS_ERRORLIMIT(_VALUE_) (((_VALUE_) <= 0xFF))
mbed_official	340:28d1f895c6fe	766	/**
mbed_official	340:28d1f895c6fe	767	* @}
mbed_official	340:28d1f895c6fe	768	*/
mbed_official	340:28d1f895c6fe	769
mbed_official	340:28d1f895c6fe	770	/** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCCEx CRS HSI48CalibrationDefault
mbed_official	340:28d1f895c6fe	771	* @{
mbed_official	340:28d1f895c6fe	772	*/
mbed_official	340:28d1f895c6fe	773	#define RCC_CRS_HSI48CALIBRATION_DEFAULT ((uint32_t)0x20) /*!< The default value is 32, which corresponds to the middle of the trimming interval.
mbed_official	340:28d1f895c6fe	774	The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value
mbed_official	340:28d1f895c6fe	775	corresponds to a higher output frequency */
mbed_official	340:28d1f895c6fe	776
mbed_official	340:28d1f895c6fe	777	#define IS_RCC_CRS_HSI48CALIBRATION(_VALUE_) (((_VALUE_) <= 0x3F))
mbed_official	340:28d1f895c6fe	778	/**
mbed_official	340:28d1f895c6fe	779	* @}
mbed_official	340:28d1f895c6fe	780	*/
mbed_official	340:28d1f895c6fe	781
mbed_official	340:28d1f895c6fe	782	/** @defgroup RCCEx_CRS_FreqErrorDirection RCCEx CRS FreqErrorDirection
mbed_official	340:28d1f895c6fe	783	* @{
mbed_official	340:28d1f895c6fe	784	*/
mbed_official	340:28d1f895c6fe	785	#define RCC_CRS_FREQERRORDIR_UP ((uint32_t)0x00) /!< Upcounting direction, the actual frequency is above the target /
mbed_official	340:28d1f895c6fe	786	#define RCC_CRS_FREQERRORDIR_DOWN ((uint32_t)CRS_ISR_FEDIR) /!< Downcounting direction, the actual frequency is below the target /
mbed_official	340:28d1f895c6fe	787
mbed_official	340:28d1f895c6fe	788	#define IS_RCC_CRS_FREQERRORDIR(_DIR_) (((_DIR_) == RCC_CRS_FREQERRORDIR_UP) \|\| \
mbed_official	340:28d1f895c6fe	789	((_DIR_) == RCC_CRS_FREQERRORDIR_DOWN))
mbed_official	340:28d1f895c6fe	790	/**
mbed_official	340:28d1f895c6fe	791	* @}
mbed_official	340:28d1f895c6fe	792	*/
mbed_official	340:28d1f895c6fe	793
mbed_official	340:28d1f895c6fe	794	/** @defgroup RCCEx_CRS_Interrupt_Sources RCCEx CRS Interrupt Sources
mbed_official	340:28d1f895c6fe	795	* @{
mbed_official	340:28d1f895c6fe	796	*/
mbed_official	340:28d1f895c6fe	797	#define RCC_CRS_IT_SYNCOK CRS_ISR_SYNCOKF /!< SYNC event OK /
mbed_official	340:28d1f895c6fe	798	#define RCC_CRS_IT_SYNCWARN CRS_ISR_SYNCWARNF /!< SYNC warning /
mbed_official	340:28d1f895c6fe	799	#define RCC_CRS_IT_ERR CRS_ISR_ERRF /!< error /
mbed_official	340:28d1f895c6fe	800	#define RCC_CRS_IT_ESYNC CRS_ISR_ESYNCF /!< Expected SYNC /
mbed_official	340:28d1f895c6fe	801	#define RCC_CRS_IT_TRIMOVF CRS_ISR_TRIMOVF /!< Trimming overflow or underflow /
mbed_official	340:28d1f895c6fe	802	#define RCC_CRS_IT_SYNCERR CRS_ISR_SYNCERR /!< SYNC error /
mbed_official	340:28d1f895c6fe	803	#define RCC_CRS_IT_SYNCMISS CRS_ISR_SYNCMISS /!< SYNC missed/
mbed_official	340:28d1f895c6fe	804
mbed_official	340:28d1f895c6fe	805	/**
mbed_official	340:28d1f895c6fe	806	* @}
mbed_official	340:28d1f895c6fe	807	*/
mbed_official	340:28d1f895c6fe	808
mbed_official	340:28d1f895c6fe	809	/** @defgroup RCCEx_CRS_Flags RCCEx CRS Flags
mbed_official	340:28d1f895c6fe	810	* @{
mbed_official	340:28d1f895c6fe	811	*/
mbed_official	340:28d1f895c6fe	812	#define RCC_CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF /* SYNC event OK flag */
mbed_official	340:28d1f895c6fe	813	#define RCC_CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF /* SYNC warning flag */
mbed_official	340:28d1f895c6fe	814	#define RCC_CRS_FLAG_ERR CRS_ISR_ERRF /* Error flag */
mbed_official	340:28d1f895c6fe	815	#define RCC_CRS_FLAG_ESYNC CRS_ISR_ESYNCF /* Expected SYNC flag */
mbed_official	340:28d1f895c6fe	816	#define RCC_CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF /!< Trimming overflow or underflow /
mbed_official	340:28d1f895c6fe	817	#define RCC_CRS_FLAG_SYNCERR CRS_ISR_SYNCERR /!< SYNC error /
mbed_official	340:28d1f895c6fe	818	#define RCC_CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS /!< SYNC missed/
mbed_official	340:28d1f895c6fe	819
mbed_official	340:28d1f895c6fe	820	/**
mbed_official	340:28d1f895c6fe	821	* @}
mbed_official	340:28d1f895c6fe	822	*/
mbed_official	340:28d1f895c6fe	823
mbed_official	441:d2c15dda23c1	824	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
mbed_official	441:d2c15dda23c1	825	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
mbed_official	441:d2c15dda23c1	826	/* STM32F091xC \|\| STM32F098xx */
mbed_official	441:d2c15dda23c1	827
mbed_official	340:28d1f895c6fe	828	/**
mbed_official	340:28d1f895c6fe	829	* @}
mbed_official	340:28d1f895c6fe	830	*/
mbed_official	340:28d1f895c6fe	831
mbed_official	340:28d1f895c6fe	832	/* Exported macros ------------------------------------------------------------*/
mbed_official	340:28d1f895c6fe	833	/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
mbed_official	340:28d1f895c6fe	834	* @{
mbed_official	340:28d1f895c6fe	835	*/
mbed_official	340:28d1f895c6fe	836
mbed_official	340:28d1f895c6fe	837	/** @defgroup RCCEx_Peripheral_Clock_Enable_Disable RCCEx_Peripheral_Clock_Enable_Disable
mbed_official	340:28d1f895c6fe	838	* @brief Enables or disables the AHB1 peripheral clock.
mbed_official	340:28d1f895c6fe	839	* @note After reset, the peripheral clock (used for registers read/write access)
mbed_official	340:28d1f895c6fe	840	* is disabled and the application software has to enable this clock before
mbed_official	340:28d1f895c6fe	841	* using it.
mbed_official	340:28d1f895c6fe	842	* @{
mbed_official	340:28d1f895c6fe	843	*/
mbed_official	441:d2c15dda23c1	844	#if defined(STM32F030x6) \|\| defined(STM32F030x8) \|\| \
mbed_official	441:d2c15dda23c1	845	defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| defined(STM32F070xB) \|\| \
mbed_official	340:28d1f895c6fe	846	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
mbed_official	441:d2c15dda23c1	847	defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
mbed_official	340:28d1f895c6fe	848
mbed_official	340:28d1f895c6fe	849	#define __GPIOD_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_GPIODEN))
mbed_official	340:28d1f895c6fe	850
mbed_official	340:28d1f895c6fe	851	#define __GPIOD_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIODEN))
mbed_official	340:28d1f895c6fe	852
mbed_official	441:d2c15dda23c1	853	#endif /* STM32F030x6 \|\| STM32F030x8 \|\| */
mbed_official	441:d2c15dda23c1	854	/* STM32F051x8 \|\| STM32F058xx \|\| STM32F070xB \|\| */
mbed_official	441:d2c15dda23c1	855	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
mbed_official	441:d2c15dda23c1	856	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
mbed_official	340:28d1f895c6fe	857
mbed_official	441:d2c15dda23c1	858	#if defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB) \|\| \
mbed_official	441:d2c15dda23c1	859	defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
mbed_official	340:28d1f895c6fe	860
mbed_official	340:28d1f895c6fe	861	#define __GPIOE_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_GPIOEEN))
mbed_official	340:28d1f895c6fe	862
mbed_official	340:28d1f895c6fe	863	#define __GPIOE_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOEEN))
mbed_official	340:28d1f895c6fe	864
mbed_official	441:d2c15dda23c1	865	#endif /* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
mbed_official	441:d2c15dda23c1	866	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
mbed_official	340:28d1f895c6fe	867
mbed_official	340:28d1f895c6fe	868	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
mbed_official	340:28d1f895c6fe	869	defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
mbed_official	340:28d1f895c6fe	870	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
mbed_official	340:28d1f895c6fe	871	defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	340:28d1f895c6fe	872
mbed_official	340:28d1f895c6fe	873	#define __TSC_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_TSCEN))
mbed_official	340:28d1f895c6fe	874
mbed_official	340:28d1f895c6fe	875	#define __TSC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_TSCEN))
mbed_official	340:28d1f895c6fe	876
mbed_official	340:28d1f895c6fe	877	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
mbed_official	340:28d1f895c6fe	878	/* STM32F051x8 \|\| STM32F058xx \|\| */
mbed_official	340:28d1f895c6fe	879	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
mbed_official	340:28d1f895c6fe	880	/* STM32F091xC \|\| STM32F098xx */
mbed_official	340:28d1f895c6fe	881
mbed_official	340:28d1f895c6fe	882	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	340:28d1f895c6fe	883
mbed_official	340:28d1f895c6fe	884	#define __DMA2_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_DMA2EN))
mbed_official	340:28d1f895c6fe	885
mbed_official	340:28d1f895c6fe	886	#define __DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN))
mbed_official	340:28d1f895c6fe	887
mbed_official	340:28d1f895c6fe	888	#endif /* STM32F091xC \|\| STM32F098xx */
mbed_official	340:28d1f895c6fe	889
mbed_official	340:28d1f895c6fe	890	/** @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
mbed_official	340:28d1f895c6fe	891	* @note After reset, the peripheral clock (used for registers read/write access)
mbed_official	340:28d1f895c6fe	892	* is disabled and the application software has to enable this clock before
mbed_official	340:28d1f895c6fe	893	* using it.
mbed_official	340:28d1f895c6fe	894	*/
mbed_official	340:28d1f895c6fe	895	#if defined(STM32F030x8) \|\| \
mbed_official	340:28d1f895c6fe	896	defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
mbed_official	340:28d1f895c6fe	897	defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
mbed_official	441:d2c15dda23c1	898	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB) \|\| \
mbed_official	441:d2c15dda23c1	899	defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
mbed_official	340:28d1f895c6fe	900
mbed_official	340:28d1f895c6fe	901	#define __USART2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_USART2EN))
mbed_official	340:28d1f895c6fe	902	#define __SPI2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_SPI2EN))
mbed_official	340:28d1f895c6fe	903
mbed_official	340:28d1f895c6fe	904	#define __USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
mbed_official	340:28d1f895c6fe	905	#define __SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
mbed_official	340:28d1f895c6fe	906
mbed_official	340:28d1f895c6fe	907	#endif /* STM32F030x8 \|\| STM32F042x6 \|\| STM32F048xx \|\| */
mbed_official	340:28d1f895c6fe	908	/* STM32F051x8 \|\| STM32F058xx \|\| */
mbed_official	441:d2c15dda23c1	909	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
mbed_official	441:d2c15dda23c1	910	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
mbed_official	340:28d1f895c6fe	911
mbed_official	340:28d1f895c6fe	912	#if defined(STM32F031x6) \|\| defined(STM32F038xx) \|\| \
mbed_official	340:28d1f895c6fe	913	defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
mbed_official	340:28d1f895c6fe	914	defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
mbed_official	340:28d1f895c6fe	915	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
mbed_official	340:28d1f895c6fe	916	defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	340:28d1f895c6fe	917
mbed_official	340:28d1f895c6fe	918	#define __TIM2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM2EN))
mbed_official	340:28d1f895c6fe	919
mbed_official	340:28d1f895c6fe	920	#define __TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
mbed_official	340:28d1f895c6fe	921
mbed_official	340:28d1f895c6fe	922	#endif /* STM32F031x6 \|\| STM32F038xx \|\| */
mbed_official	340:28d1f895c6fe	923	/* STM32F042x6 \|\| STM32F048xx \|\| */
mbed_official	340:28d1f895c6fe	924	/* STM32F051x8 \|\| STM32F058xx \|\| */
mbed_official	340:28d1f895c6fe	925	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
mbed_official	340:28d1f895c6fe	926	/* STM32F091xC \|\| STM32F098xx */
mbed_official	340:28d1f895c6fe	927
mbed_official	340:28d1f895c6fe	928	#if defined(STM32F030x8) \|\| \
mbed_official	340:28d1f895c6fe	929	defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
mbed_official	441:d2c15dda23c1	930	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB) \|\| \
mbed_official	441:d2c15dda23c1	931	defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
mbed_official	340:28d1f895c6fe	932
mbed_official	340:28d1f895c6fe	933	#define __TIM6_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM6EN))
mbed_official	340:28d1f895c6fe	934	#define __I2C2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_I2C2EN))
mbed_official	340:28d1f895c6fe	935
mbed_official	340:28d1f895c6fe	936	#define __TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
mbed_official	340:28d1f895c6fe	937	#define __I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
mbed_official	340:28d1f895c6fe	938
mbed_official	340:28d1f895c6fe	939	#endif /* STM32F030x8 \|\| */
mbed_official	340:28d1f895c6fe	940	/* STM32F051x8 \|\| STM32F058xx \|\| */
mbed_official	441:d2c15dda23c1	941	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
mbed_official	441:d2c15dda23c1	942	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
mbed_official	340:28d1f895c6fe	943
mbed_official	340:28d1f895c6fe	944	#if defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
mbed_official	340:28d1f895c6fe	945	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
mbed_official	340:28d1f895c6fe	946	defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	340:28d1f895c6fe	947
mbed_official	340:28d1f895c6fe	948	#define __DAC1_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_DACEN))
mbed_official	340:28d1f895c6fe	949
mbed_official	340:28d1f895c6fe	950	#define __DAC1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
mbed_official	340:28d1f895c6fe	951
mbed_official	340:28d1f895c6fe	952	#endif /* STM32F051x8 \|\| STM32F058xx \|\| */
mbed_official	340:28d1f895c6fe	953	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
mbed_official	340:28d1f895c6fe	954	/* STM32F091xC \|\| STM32F098xx */
mbed_official	340:28d1f895c6fe	955
mbed_official	340:28d1f895c6fe	956	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
mbed_official	340:28d1f895c6fe	957	defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
mbed_official	340:28d1f895c6fe	958	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
mbed_official	340:28d1f895c6fe	959	defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	340:28d1f895c6fe	960
mbed_official	340:28d1f895c6fe	961	#define __CEC_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_CECEN))
mbed_official	340:28d1f895c6fe	962
mbed_official	340:28d1f895c6fe	963	#define __CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))
mbed_official	340:28d1f895c6fe	964
mbed_official	340:28d1f895c6fe	965	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
mbed_official	340:28d1f895c6fe	966	/* STM32F051x8 \|\| STM32F058xx \|\| */
mbed_official	340:28d1f895c6fe	967	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
mbed_official	340:28d1f895c6fe	968	/* STM32F091xC \|\| STM32F098xx */
mbed_official	340:28d1f895c6fe	969
mbed_official	441:d2c15dda23c1	970	#if defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB) \|\| \
mbed_official	441:d2c15dda23c1	971	defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
mbed_official	340:28d1f895c6fe	972
mbed_official	340:28d1f895c6fe	973	#define __TIM7_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM7EN))
mbed_official	340:28d1f895c6fe	974	#define __USART3_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_USART3EN))
mbed_official	340:28d1f895c6fe	975	#define __USART4_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_USART4EN))
mbed_official	340:28d1f895c6fe	976
mbed_official	340:28d1f895c6fe	977	#define __TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
mbed_official	340:28d1f895c6fe	978	#define __USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
mbed_official	340:28d1f895c6fe	979	#define __USART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART4EN))
mbed_official	340:28d1f895c6fe	980
mbed_official	441:d2c15dda23c1	981	#endif /* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
mbed_official	441:d2c15dda23c1	982	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
mbed_official	340:28d1f895c6fe	983
mbed_official	441:d2c15dda23c1	984	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F070x6) \|\| \
mbed_official	441:d2c15dda23c1	985	defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)
mbed_official	340:28d1f895c6fe	986
mbed_official	340:28d1f895c6fe	987	#define __USB_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_USBEN))
mbed_official	340:28d1f895c6fe	988
mbed_official	340:28d1f895c6fe	989	#define __USB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN))
mbed_official	340:28d1f895c6fe	990
mbed_official	441:d2c15dda23c1	991	#endif /* STM32F042x6 \|\| STM32F048xx \|\| STM32F070x6 \|\| */
mbed_official	441:d2c15dda23c1	992	/* STM32F072xB \|\| STM32F078xx \|\| STM32F070xB */
mbed_official	340:28d1f895c6fe	993
mbed_official	340:28d1f895c6fe	994	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F072xB) \|\| \
mbed_official	340:28d1f895c6fe	995	defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	340:28d1f895c6fe	996
mbed_official	340:28d1f895c6fe	997	#define __CAN_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_CANEN))
mbed_official	340:28d1f895c6fe	998	#define __CAN_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CANEN))
mbed_official	340:28d1f895c6fe	999
mbed_official	340:28d1f895c6fe	1000	#endif /* STM32F042x6 \|\| STM32F048xx \|\| STM32F072xB \|\| */
mbed_official	340:28d1f895c6fe	1001	/* STM32F091xC \|\| STM32F098xx */
mbed_official	340:28d1f895c6fe	1002
mbed_official	340:28d1f895c6fe	1003	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
mbed_official	340:28d1f895c6fe	1004	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
mbed_official	340:28d1f895c6fe	1005	defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	340:28d1f895c6fe	1006
mbed_official	340:28d1f895c6fe	1007	#define __CRS_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_CRSEN))
mbed_official	340:28d1f895c6fe	1008
mbed_official	340:28d1f895c6fe	1009	#define __CRS_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CRSEN))
mbed_official	340:28d1f895c6fe	1010
mbed_official	340:28d1f895c6fe	1011	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
mbed_official	340:28d1f895c6fe	1012	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
mbed_official	340:28d1f895c6fe	1013	/* STM32F091xC \|\| STM32F098xx */
mbed_official	340:28d1f895c6fe	1014
mbed_official	441:d2c15dda23c1	1015	#if defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
mbed_official	340:28d1f895c6fe	1016
mbed_official	340:28d1f895c6fe	1017	#define __USART5_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_USART5EN))
mbed_official	340:28d1f895c6fe	1018
mbed_official	340:28d1f895c6fe	1019	#define __USART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART5EN))
mbed_official	340:28d1f895c6fe	1020
mbed_official	441:d2c15dda23c1	1021	#endif /* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
mbed_official	340:28d1f895c6fe	1022
mbed_official	340:28d1f895c6fe	1023	/** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
mbed_official	340:28d1f895c6fe	1024	* @note After reset, the peripheral clock (used for registers read/write access)
mbed_official	340:28d1f895c6fe	1025	* is disabled and the application software has to enable this clock before
mbed_official	340:28d1f895c6fe	1026	* using it.
mbed_official	340:28d1f895c6fe	1027	*/
mbed_official	441:d2c15dda23c1	1028	#if defined(STM32F030x8) \|\| defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F070x6) \|\| \
mbed_official	340:28d1f895c6fe	1029	defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
mbed_official	441:d2c15dda23c1	1030	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB) \|\| \
mbed_official	441:d2c15dda23c1	1031	defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
mbed_official	340:28d1f895c6fe	1032
mbed_official	340:28d1f895c6fe	1033	#define __TIM15_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_TIM15EN))
mbed_official	340:28d1f895c6fe	1034
mbed_official	340:28d1f895c6fe	1035	#define __TIM15_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM15EN))
mbed_official	340:28d1f895c6fe	1036
mbed_official	441:d2c15dda23c1	1037	#endif /* STM32F030x8 \|\| STM32F042x6 \|\| STM32F048xx \|\| STM32F070x6 \|\| */
mbed_official	340:28d1f895c6fe	1038	/* STM32F051x8 \|\| STM32F058xx \|\| */
mbed_official	441:d2c15dda23c1	1039	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
mbed_official	441:d2c15dda23c1	1040	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
mbed_official	441:d2c15dda23c1	1041
mbed_official	441:d2c15dda23c1	1042	#if defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
mbed_official	441:d2c15dda23c1	1043
mbed_official	441:d2c15dda23c1	1044	#define __USART6_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_USART6EN))
mbed_official	441:d2c15dda23c1	1045
mbed_official	441:d2c15dda23c1	1046	#define __USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))
mbed_official	441:d2c15dda23c1	1047
mbed_official	441:d2c15dda23c1	1048	#endif /* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
mbed_official	340:28d1f895c6fe	1049
mbed_official	340:28d1f895c6fe	1050	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	340:28d1f895c6fe	1051
mbed_official	340:28d1f895c6fe	1052	#define __USART7_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_USART7EN))
mbed_official	340:28d1f895c6fe	1053	#define __USART8_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_USART8EN))
mbed_official	340:28d1f895c6fe	1054
mbed_official	340:28d1f895c6fe	1055	#define __USART7_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART7EN))
mbed_official	340:28d1f895c6fe	1056	#define __USART8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART8EN))
mbed_official	340:28d1f895c6fe	1057
mbed_official	340:28d1f895c6fe	1058	#endif /* STM32F091xC \|\| STM32F098xx */
mbed_official	340:28d1f895c6fe	1059
mbed_official	340:28d1f895c6fe	1060	/**
mbed_official	340:28d1f895c6fe	1061	* @}
mbed_official	340:28d1f895c6fe	1062	*/
mbed_official	340:28d1f895c6fe	1063
mbed_official	340:28d1f895c6fe	1064
mbed_official	340:28d1f895c6fe	1065	/** @defgroup RCCEx_Force_Release_Peripheral_Reset RCCEx Force Release Peripheral Reset
mbed_official	340:28d1f895c6fe	1066	* @brief Forces or releases peripheral reset.
mbed_official	340:28d1f895c6fe	1067	* @{
mbed_official	340:28d1f895c6fe	1068	*/
mbed_official	340:28d1f895c6fe	1069
mbed_official	340:28d1f895c6fe	1070	/** @brief Force or release AHB peripheral reset.
mbed_official	340:28d1f895c6fe	1071	*/
mbed_official	441:d2c15dda23c1	1072	#if defined(STM32F030x6) \|\| defined(STM32F030x8) \|\| \
mbed_official	441:d2c15dda23c1	1073	defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
mbed_official	441:d2c15dda23c1	1074	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB) \|\| \
mbed_official	441:d2c15dda23c1	1075	defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
mbed_official	340:28d1f895c6fe	1076
mbed_official	340:28d1f895c6fe	1077	#define __GPIOD_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIODRST))
mbed_official	340:28d1f895c6fe	1078
mbed_official	340:28d1f895c6fe	1079	#define __GPIOD_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIODRST))
mbed_official	340:28d1f895c6fe	1080
mbed_official	340:28d1f895c6fe	1081	#endif /* STM32F030x6 \|\| STM32F030x8 \|\| */
mbed_official	340:28d1f895c6fe	1082	/* STM32F051x8 \|\| STM32F058xx \|\| */
mbed_official	441:d2c15dda23c1	1083	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
mbed_official	441:d2c15dda23c1	1084	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
mbed_official	340:28d1f895c6fe	1085
mbed_official	441:d2c15dda23c1	1086	#if defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB) \|\| \
mbed_official	441:d2c15dda23c1	1087	defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
mbed_official	340:28d1f895c6fe	1088
mbed_official	340:28d1f895c6fe	1089	#define __GPIOE_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIOERST))
mbed_official	340:28d1f895c6fe	1090
mbed_official	340:28d1f895c6fe	1091	#define __GPIOE_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOERST))
mbed_official	340:28d1f895c6fe	1092
mbed_official	441:d2c15dda23c1	1093	#endif /* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
mbed_official	441:d2c15dda23c1	1094	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
mbed_official	340:28d1f895c6fe	1095
mbed_official	340:28d1f895c6fe	1096	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
mbed_official	340:28d1f895c6fe	1097	defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
mbed_official	340:28d1f895c6fe	1098	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
mbed_official	340:28d1f895c6fe	1099	defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	340:28d1f895c6fe	1100
mbed_official	340:28d1f895c6fe	1101	#define __TSC_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_TSCRST))
mbed_official	340:28d1f895c6fe	1102
mbed_official	340:28d1f895c6fe	1103	#define __TSC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_TSCRST))
mbed_official	340:28d1f895c6fe	1104
mbed_official	340:28d1f895c6fe	1105	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
mbed_official	340:28d1f895c6fe	1106	/* STM32F051x8 \|\| STM32F058xx \|\| */
mbed_official	340:28d1f895c6fe	1107	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
mbed_official	340:28d1f895c6fe	1108	/* STM32F091xC \|\| STM32F098xx */
mbed_official	340:28d1f895c6fe	1109
mbed_official	340:28d1f895c6fe	1110	/** @brief Force or release APB1 peripheral reset.
mbed_official	340:28d1f895c6fe	1111	*/
mbed_official	340:28d1f895c6fe	1112	#if defined(STM32F030x8) \|\| \
mbed_official	441:d2c15dda23c1	1113	defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F070x6) \|\| \
mbed_official	340:28d1f895c6fe	1114	defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
mbed_official	441:d2c15dda23c1	1115	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB) \|\| \
mbed_official	441:d2c15dda23c1	1116	defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
mbed_official	340:28d1f895c6fe	1117
mbed_official	340:28d1f895c6fe	1118	#define __USART2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART2RST))
mbed_official	340:28d1f895c6fe	1119	#define __SPI2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI2RST))
mbed_official	340:28d1f895c6fe	1120
mbed_official	340:28d1f895c6fe	1121	#define __USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
mbed_official	340:28d1f895c6fe	1122	#define __SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
mbed_official	340:28d1f895c6fe	1123
mbed_official	441:d2c15dda23c1	1124	#endif /* STM32F030x8 \|\| STM32F042x6 \|\| STM32F048xx \|\| STM32F070x6 \|\| */
mbed_official	340:28d1f895c6fe	1125	/* STM32F051x8 \|\| STM32F058xx \|\| */
mbed_official	441:d2c15dda23c1	1126	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
mbed_official	441:d2c15dda23c1	1127	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
mbed_official	340:28d1f895c6fe	1128
mbed_official	340:28d1f895c6fe	1129	#if defined(STM32F031x6) \|\| defined(STM32F038xx) \|\| \
mbed_official	340:28d1f895c6fe	1130	defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
mbed_official	340:28d1f895c6fe	1131	defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
mbed_official	340:28d1f895c6fe	1132	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
mbed_official	340:28d1f895c6fe	1133	defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	340:28d1f895c6fe	1134
mbed_official	340:28d1f895c6fe	1135	#define __TIM2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM2RST))
mbed_official	340:28d1f895c6fe	1136
mbed_official	340:28d1f895c6fe	1137	#define __TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
mbed_official	340:28d1f895c6fe	1138
mbed_official	340:28d1f895c6fe	1139	#endif /* STM32F031x6 \|\| STM32F038xx \|\| */
mbed_official	340:28d1f895c6fe	1140	/* STM32F042x6 \|\| STM32F048xx \|\| */
mbed_official	340:28d1f895c6fe	1141	/* STM32F051x8 \|\| STM32F058xx \|\| */
mbed_official	340:28d1f895c6fe	1142	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
mbed_official	340:28d1f895c6fe	1143	/* STM32F091xC \|\| STM32F098xx */
mbed_official	340:28d1f895c6fe	1144
mbed_official	340:28d1f895c6fe	1145	#if defined(STM32F030x8) \|\| \
mbed_official	340:28d1f895c6fe	1146	defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
mbed_official	441:d2c15dda23c1	1147	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB) \|\|\
mbed_official	441:d2c15dda23c1	1148	defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
mbed_official	340:28d1f895c6fe	1149
mbed_official	340:28d1f895c6fe	1150	#define __TIM6_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM6RST))
mbed_official	340:28d1f895c6fe	1151	#define __I2C2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C2RST))
mbed_official	340:28d1f895c6fe	1152
mbed_official	340:28d1f895c6fe	1153	#define __TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
mbed_official	340:28d1f895c6fe	1154	#define __I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
mbed_official	340:28d1f895c6fe	1155
mbed_official	340:28d1f895c6fe	1156	#endif /* STM32F030x8 \|\| */
mbed_official	340:28d1f895c6fe	1157	/* STM32F051x8 \|\| STM32F058xx \|\| */
mbed_official	441:d2c15dda23c1	1158	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
mbed_official	441:d2c15dda23c1	1159	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
mbed_official	340:28d1f895c6fe	1160
mbed_official	340:28d1f895c6fe	1161	#if defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
mbed_official	340:28d1f895c6fe	1162	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
mbed_official	340:28d1f895c6fe	1163	defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	340:28d1f895c6fe	1164
mbed_official	340:28d1f895c6fe	1165	#define __DAC1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_DACRST))
mbed_official	340:28d1f895c6fe	1166
mbed_official	340:28d1f895c6fe	1167	#define __DAC1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
mbed_official	340:28d1f895c6fe	1168
mbed_official	340:28d1f895c6fe	1169	#endif /* STM32F051x8 \|\| STM32F058xx \|\| */
mbed_official	340:28d1f895c6fe	1170	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
mbed_official	340:28d1f895c6fe	1171	/* STM32F091xC \|\| STM32F098xx */
mbed_official	340:28d1f895c6fe	1172
mbed_official	340:28d1f895c6fe	1173	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
mbed_official	340:28d1f895c6fe	1174	defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
mbed_official	340:28d1f895c6fe	1175	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
mbed_official	340:28d1f895c6fe	1176	defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	340:28d1f895c6fe	1177
mbed_official	340:28d1f895c6fe	1178	#define __CEC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CECRST))
mbed_official	340:28d1f895c6fe	1179
mbed_official	340:28d1f895c6fe	1180	#define __CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST))
mbed_official	340:28d1f895c6fe	1181
mbed_official	340:28d1f895c6fe	1182	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
mbed_official	340:28d1f895c6fe	1183	/* STM32F051x8 \|\| STM32F058xx \|\| */
mbed_official	340:28d1f895c6fe	1184	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
mbed_official	340:28d1f895c6fe	1185	/* STM32F091xC \|\| STM32F098xx */
mbed_official	340:28d1f895c6fe	1186
mbed_official	441:d2c15dda23c1	1187	#if defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB) \|\| \
mbed_official	441:d2c15dda23c1	1188	defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
mbed_official	340:28d1f895c6fe	1189
mbed_official	340:28d1f895c6fe	1190	#define __TIM7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM7RST))
mbed_official	340:28d1f895c6fe	1191	#define __USART3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART3RST))
mbed_official	340:28d1f895c6fe	1192	#define __USART4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART4RST))
mbed_official	340:28d1f895c6fe	1193
mbed_official	340:28d1f895c6fe	1194	#define __TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
mbed_official	340:28d1f895c6fe	1195	#define __USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
mbed_official	340:28d1f895c6fe	1196	#define __USART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART4RST))
mbed_official	340:28d1f895c6fe	1197
mbed_official	441:d2c15dda23c1	1198	#endif /* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
mbed_official	441:d2c15dda23c1	1199	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
mbed_official	340:28d1f895c6fe	1200
mbed_official	441:d2c15dda23c1	1201	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F070x6) \|\| \
mbed_official	441:d2c15dda23c1	1202	defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)
mbed_official	340:28d1f895c6fe	1203
mbed_official	340:28d1f895c6fe	1204	#define __USB_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USBRST))
mbed_official	340:28d1f895c6fe	1205
mbed_official	340:28d1f895c6fe	1206	#define __USB_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USBRST))
mbed_official	340:28d1f895c6fe	1207
mbed_official	441:d2c15dda23c1	1208	#endif /* STM32F042x6 \|\| STM32F048xx \|\| STM32F070x6 \|\| */
mbed_official	441:d2c15dda23c1	1209	/* STM32F072xB \|\| STM32F078xx \|\| STM32F070xB */
mbed_official	340:28d1f895c6fe	1210
mbed_official	340:28d1f895c6fe	1211	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F072xB) \|\| \
mbed_official	340:28d1f895c6fe	1212	defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	340:28d1f895c6fe	1213
mbed_official	340:28d1f895c6fe	1214	#define __CAN_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CANRST))
mbed_official	340:28d1f895c6fe	1215
mbed_official	340:28d1f895c6fe	1216	#define __CAN_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CANRST))
mbed_official	340:28d1f895c6fe	1217
mbed_official	340:28d1f895c6fe	1218	#endif /* STM32F042x6 \|\| STM32F048xx \|\| STM32F072xB \|\| */
mbed_official	340:28d1f895c6fe	1219	/* STM32F091xC \|\| STM32F098xx */
mbed_official	340:28d1f895c6fe	1220
mbed_official	340:28d1f895c6fe	1221	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
mbed_official	340:28d1f895c6fe	1222	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
mbed_official	340:28d1f895c6fe	1223	defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	340:28d1f895c6fe	1224
mbed_official	340:28d1f895c6fe	1225	#define __CRS_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CRSRST))
mbed_official	340:28d1f895c6fe	1226
mbed_official	340:28d1f895c6fe	1227	#define __CRS_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CRSRST))
mbed_official	340:28d1f895c6fe	1228
mbed_official	340:28d1f895c6fe	1229	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
mbed_official	340:28d1f895c6fe	1230	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
mbed_official	340:28d1f895c6fe	1231	/* STM32F091xC \|\| STM32F098xx */
mbed_official	340:28d1f895c6fe	1232
mbed_official	441:d2c15dda23c1	1233	#if defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
mbed_official	340:28d1f895c6fe	1234
mbed_official	340:28d1f895c6fe	1235	#define __USART5_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART5RST))
mbed_official	340:28d1f895c6fe	1236
mbed_official	340:28d1f895c6fe	1237	#define __USART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART5RST))
mbed_official	340:28d1f895c6fe	1238
mbed_official	441:d2c15dda23c1	1239	#endif /* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
mbed_official	340:28d1f895c6fe	1240
mbed_official	340:28d1f895c6fe	1241
mbed_official	340:28d1f895c6fe	1242	/** @brief Force or release APB2 peripheral reset.
mbed_official	340:28d1f895c6fe	1243	*/
mbed_official	441:d2c15dda23c1	1244	#if defined(STM32F030x8) \|\| defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F070x6) \|\| \
mbed_official	340:28d1f895c6fe	1245	defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
mbed_official	441:d2c15dda23c1	1246	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB) \|\| \
mbed_official	441:d2c15dda23c1	1247	defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
mbed_official	340:28d1f895c6fe	1248
mbed_official	340:28d1f895c6fe	1249	#define __TIM15_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM15RST))
mbed_official	340:28d1f895c6fe	1250
mbed_official	340:28d1f895c6fe	1251	#define __TIM15_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM15RST))
mbed_official	340:28d1f895c6fe	1252
mbed_official	441:d2c15dda23c1	1253	#endif /* STM32F030x8 \|\| STM32F042x6 \|\| STM32F048xx \|\| STM32F070x6 \|\| */
mbed_official	340:28d1f895c6fe	1254	/* STM32F051x8 \|\| STM32F058xx \|\| */
mbed_official	441:d2c15dda23c1	1255	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
mbed_official	441:d2c15dda23c1	1256	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
mbed_official	441:d2c15dda23c1	1257
mbed_official	441:d2c15dda23c1	1258	#if defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
mbed_official	441:d2c15dda23c1	1259
mbed_official	441:d2c15dda23c1	1260	#define __USART6_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_USART6RST))
mbed_official	441:d2c15dda23c1	1261
mbed_official	441:d2c15dda23c1	1262	#define __USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST))
mbed_official	441:d2c15dda23c1	1263
mbed_official	441:d2c15dda23c1	1264	#endif /* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
mbed_official	340:28d1f895c6fe	1265
mbed_official	340:28d1f895c6fe	1266	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	340:28d1f895c6fe	1267
mbed_official	340:28d1f895c6fe	1268	#define __USART7_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_USART7RST))
mbed_official	340:28d1f895c6fe	1269	#define __USART8_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_USART8RST))
mbed_official	340:28d1f895c6fe	1270
mbed_official	340:28d1f895c6fe	1271	#define __USART7_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART7RST))
mbed_official	340:28d1f895c6fe	1272	#define __USART8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART8RST))
mbed_official	340:28d1f895c6fe	1273
mbed_official	340:28d1f895c6fe	1274	#endif /* STM32F091xC \|\| STM32F098xx */
mbed_official	340:28d1f895c6fe	1275
mbed_official	340:28d1f895c6fe	1276	/**
mbed_official	340:28d1f895c6fe	1277	* @}
mbed_official	340:28d1f895c6fe	1278	*/
mbed_official	340:28d1f895c6fe	1279
mbed_official	340:28d1f895c6fe	1280	/** @defgroup RCCEx_HSI48_Enable_Disable RCCEx HSI48 Enable Disable
mbed_official	340:28d1f895c6fe	1281	* @brief Macros to enable or disable the Internal 48Mhz High Speed oscillator (HSI48).
mbed_official	340:28d1f895c6fe	1282	* @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes.
mbed_official	340:28d1f895c6fe	1283	* @note HSI48 can not be stopped if it is used as system clock source. In this case,
mbed_official	340:28d1f895c6fe	1284	* you have to select another source of the system clock then stop the HSI14.
mbed_official	340:28d1f895c6fe	1285	* @note After enabling the HSI48 with __HAL_RCC_HSI48_ENABLE(), the application software
mbed_official	340:28d1f895c6fe	1286	* should wait on HSI48RDY flag to be set indicating that HSI48 clock is stable and can be
mbed_official	340:28d1f895c6fe	1287	* used as system clock source. This is not necessary if HAL_RCC_OscConfig() is used.
mbed_official	340:28d1f895c6fe	1288	* @note When the HSI48 is stopped, HSI48RDY flag goes low after 6 HSI48 oscillator
mbed_official	340:28d1f895c6fe	1289	* clock cycles.
mbed_official	340:28d1f895c6fe	1290	* @{
mbed_official	340:28d1f895c6fe	1291	*/
mbed_official	340:28d1f895c6fe	1292	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
mbed_official	340:28d1f895c6fe	1293	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
mbed_official	340:28d1f895c6fe	1294	defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	340:28d1f895c6fe	1295
mbed_official	340:28d1f895c6fe	1296	#define __HAL_RCC_HSI48_ENABLE() SET_BIT(RCC->CR2, RCC_CR2_HSI48ON)
mbed_official	340:28d1f895c6fe	1297	#define __HAL_RCC_HSI48_DISABLE() CLEAR_BIT(RCC->CR2, RCC_CR2_HSI48ON)
mbed_official	340:28d1f895c6fe	1298
mbed_official	340:28d1f895c6fe	1299	/** @brief Macro to get the Internal 48Mhz High Speed oscillator (HSI48) state.
mbed_official	340:28d1f895c6fe	1300	* @retval The clock source can be one of the following values:
mbed_official	340:28d1f895c6fe	1301	* @arg RCC_HSI48_ON: HSI48 enabled
mbed_official	340:28d1f895c6fe	1302	* @arg RCC_HSI48_OFF: HSI48 disabled
mbed_official	340:28d1f895c6fe	1303	*/
mbed_official	340:28d1f895c6fe	1304	#define __HAL_RCC_GET_HSI48_STATE() \
mbed_official	340:28d1f895c6fe	1305	(((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CR2_HSI48ON)) != RESET) ? RCC_HSI48_ON : RCC_HSI48_OFF)
mbed_official	340:28d1f895c6fe	1306
mbed_official	340:28d1f895c6fe	1307	#else
mbed_official	340:28d1f895c6fe	1308
mbed_official	340:28d1f895c6fe	1309	/** @brief Macro to get the Internal 48Mhz High Speed oscillator (HSI48) state.
mbed_official	340:28d1f895c6fe	1310	* @retval The clock source can be one of the following values:
mbed_official	340:28d1f895c6fe	1311	* @arg RCC_HSI_OFF: HSI48 disabled
mbed_official	340:28d1f895c6fe	1312	*/
mbed_official	340:28d1f895c6fe	1313	#define __HAL_RCC_GET_HSI48_STATE() RCC_HSI_OFF
mbed_official	340:28d1f895c6fe	1314
mbed_official	340:28d1f895c6fe	1315	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
mbed_official	340:28d1f895c6fe	1316	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
mbed_official	340:28d1f895c6fe	1317	/* STM32F091xC \|\| STM32F098xx */
mbed_official	340:28d1f895c6fe	1318
mbed_official	340:28d1f895c6fe	1319	/**
mbed_official	340:28d1f895c6fe	1320	* @}
mbed_official	340:28d1f895c6fe	1321	*/
mbed_official	340:28d1f895c6fe	1322
mbed_official	340:28d1f895c6fe	1323	/** @defgroup RCCEx_Peripheral_Clock_Source_Config RCCEx Peripheral Clock Source Config
mbed_official	340:28d1f895c6fe	1324	* @{
mbed_official	340:28d1f895c6fe	1325	*/
mbed_official	441:d2c15dda23c1	1326	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
mbed_official	441:d2c15dda23c1	1327	defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
mbed_official	441:d2c15dda23c1	1328	defined(STM32F070x6) \|\| defined(STM32F070xB)
mbed_official	340:28d1f895c6fe	1329
mbed_official	340:28d1f895c6fe	1330	/** @brief Macro to configure the USB clock (USBCLK).
mbed_official	340:28d1f895c6fe	1331	* @param __USBCLKSource__: specifies the USB clock source.
mbed_official	340:28d1f895c6fe	1332	* This parameter can be one of the following values:
mbed_official	441:d2c15dda23c1	1333	* @arg RCC_USBCLKSOURCE_HSI48: HSI48 selected as USB clock (not available for STM32F070x6 & STM32F070xB)
mbed_official	340:28d1f895c6fe	1334	* @arg RCC_USBCLKSOURCE_PLLCLK: PLL Clock selected as USB clock
mbed_official	340:28d1f895c6fe	1335	*/
mbed_official	340:28d1f895c6fe	1336	#define __HAL_RCC_USB_CONFIG(__USBCLKSource__) \
mbed_official	340:28d1f895c6fe	1337	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USBSW, (uint32_t)(__USBCLKSource__))
mbed_official	340:28d1f895c6fe	1338
mbed_official	340:28d1f895c6fe	1339	/** @brief Macro to get the USB clock source.
mbed_official	340:28d1f895c6fe	1340	* @retval The clock source can be one of the following values:
mbed_official	441:d2c15dda23c1	1341	* @arg RCC_USBCLKSOURCE_HSI48: HSI48 selected as USB clock (not available for STM32F070x6 & STM32F070xB)
mbed_official	340:28d1f895c6fe	1342	* @arg RCC_USBCLKSOURCE_PLLCLK: PLL Clock selected as USB clock
mbed_official	340:28d1f895c6fe	1343	*/
mbed_official	340:28d1f895c6fe	1344	#define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USBSW)))
mbed_official	340:28d1f895c6fe	1345
mbed_official	340:28d1f895c6fe	1346	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
mbed_official	441:d2c15dda23c1	1347	/* STM32F072xB \|\| STM32F078xx \|\| */
mbed_official	441:d2c15dda23c1	1348	/* STM32F070x6 \|\| STM32F070xB */
mbed_official	340:28d1f895c6fe	1349
mbed_official	340:28d1f895c6fe	1350	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
mbed_official	340:28d1f895c6fe	1351	defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
mbed_official	340:28d1f895c6fe	1352	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
mbed_official	340:28d1f895c6fe	1353	defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	340:28d1f895c6fe	1354
mbed_official	340:28d1f895c6fe	1355	/** @brief Macro to configure the CEC clock.
mbed_official	340:28d1f895c6fe	1356	* @param __CECCLKSource__: specifies the CEC clock source.
mbed_official	340:28d1f895c6fe	1357	* This parameter can be one of the following values:
mbed_official	340:28d1f895c6fe	1358	* @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock
mbed_official	340:28d1f895c6fe	1359	* @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
mbed_official	340:28d1f895c6fe	1360	*/
mbed_official	340:28d1f895c6fe	1361	#define __HAL_RCC_CEC_CONFIG(__CECCLKSource__) \
mbed_official	340:28d1f895c6fe	1362	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_CECSW, (uint32_t)(__CECCLKSource__))
mbed_official	340:28d1f895c6fe	1363
mbed_official	340:28d1f895c6fe	1364	/** @brief Macro to get the HDMI CEC clock source.
mbed_official	340:28d1f895c6fe	1365	* @retval The clock source can be one of the following values:
mbed_official	340:28d1f895c6fe	1366	* @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock
mbed_official	340:28d1f895c6fe	1367	* @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
mbed_official	340:28d1f895c6fe	1368	*/
mbed_official	340:28d1f895c6fe	1369	#define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_CECSW)))
mbed_official	340:28d1f895c6fe	1370
mbed_official	340:28d1f895c6fe	1371	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
mbed_official	340:28d1f895c6fe	1372	/* STM32F051x8 \|\| STM32F058xx \|\| */
mbed_official	340:28d1f895c6fe	1373	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
mbed_official	340:28d1f895c6fe	1374	/* STM32F091xC \|\| defined(STM32F098xx) */
mbed_official	340:28d1f895c6fe	1375
mbed_official	340:28d1f895c6fe	1376	#if defined(STM32F030x6) \|\| defined(STM32F031x6) \|\| defined(STM32F038xx) \|\| \
mbed_official	441:d2c15dda23c1	1377	defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F070x6) \|\| \
mbed_official	441:d2c15dda23c1	1378	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB) \|\| \
mbed_official	441:d2c15dda23c1	1379	defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
mbed_official	340:28d1f895c6fe	1380
mbed_official	340:28d1f895c6fe	1381	/** @brief Macro to configure the MCO clock.
mbed_official	340:28d1f895c6fe	1382	* @param __MCOCLKSource__: specifies the MCO clock source.
mbed_official	340:28d1f895c6fe	1383	* This parameter can be one of the following values:
mbed_official	340:28d1f895c6fe	1384	* @arg RCC_MCOSOURCE_HSI: HSI selected as MCO clock
mbed_official	340:28d1f895c6fe	1385	* @arg RCC_MCOSOURCE_HSE: HSE selected as MCO clock
mbed_official	340:28d1f895c6fe	1386	* @arg RCC_MCOSOURCE_LSI: LSI selected as MCO clock
mbed_official	340:28d1f895c6fe	1387	* @arg RCC_MCOSOURCE_LSE: LSE selected as MCO clock
mbed_official	340:28d1f895c6fe	1388	* @arg RCC_MCOSOURCE_PLLCLK_NODIV: PLLCLK selected as MCO clock
mbed_official	340:28d1f895c6fe	1389	* @arg RCC_MCOSOURCE_PLLCLK_DIV2: PLLCLK Divided by 2 selected as MCO clock
mbed_official	340:28d1f895c6fe	1390	* @arg RCC_MCOSOURCE_SYSCLK: System Clock selected as MCO clock
mbed_official	340:28d1f895c6fe	1391	* @arg RCC_MCOSOURCE_HSI14: HSI14 selected as MCO clock
mbed_official	340:28d1f895c6fe	1392	* @arg RCC_MCOSOURCE_HSI48: HSI48 selected as MCO clock
mbed_official	340:28d1f895c6fe	1393	* @param __MCODiv__: specifies the MCO clock prescaler.
mbed_official	340:28d1f895c6fe	1394	* This parameter can be one of the following values:
mbed_official	340:28d1f895c6fe	1395	* @arg RCC_MCO_DIV1: MCO clock source is divided by 1
mbed_official	340:28d1f895c6fe	1396	* @arg RCC_MCO_DIV2: MCO clock source is divided by 2
mbed_official	340:28d1f895c6fe	1397	* @arg RCC_MCO_DIV4: MCO clock source is divided by 4
mbed_official	340:28d1f895c6fe	1398	* @arg RCC_MCO_DIV8: MCO clock source is divided by 8
mbed_official	340:28d1f895c6fe	1399	* @arg RCC_MCO_DIV16: MCO clock source is divided by 16
mbed_official	340:28d1f895c6fe	1400	* @arg RCC_MCO_DIV32: MCO clock source is divided by 32
mbed_official	340:28d1f895c6fe	1401	* @arg RCC_MCO_DIV64: MCO clock source is divided by 64
mbed_official	340:28d1f895c6fe	1402	* @arg RCC_MCO_DIV128: MCO clock source is divided by 128
mbed_official	340:28d1f895c6fe	1403	*/
mbed_official	340:28d1f895c6fe	1404	#define __HAL_RCC_MCO_CONFIG(__MCOCLKSource__, __MCODiv__) \
mbed_official	340:28d1f895c6fe	1405	MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO \| RCC_CFGR_MCOPRE), ((__MCOCLKSource__) \| (__MCODiv__)))
mbed_official	340:28d1f895c6fe	1406	#else
mbed_official	340:28d1f895c6fe	1407
mbed_official	340:28d1f895c6fe	1408	/** @brief Macro to configure the MCO clock.
mbed_official	340:28d1f895c6fe	1409	* @param __MCOCLKSource__: specifies the MCO clock source.
mbed_official	340:28d1f895c6fe	1410	* This parameter can be one of the following values:
mbed_official	340:28d1f895c6fe	1411	* @arg RCC_MCOSOURCE_HSI: HSI selected as MCO clock
mbed_official	340:28d1f895c6fe	1412	* @arg RCC_MCOSOURCE_HSE: HSE selected as MCO clock
mbed_official	340:28d1f895c6fe	1413	* @arg RCC_MCOSOURCE_LSI: LSI selected as MCO clock
mbed_official	340:28d1f895c6fe	1414	* @arg RCC_MCOSOURCE_LSE: LSE selected as MCO clock
mbed_official	340:28d1f895c6fe	1415	* @arg RCC_MCOSOURCE_PLLCLK_DIV2: PLLCLK Divided by 2 selected as MCO clock
mbed_official	340:28d1f895c6fe	1416	* @arg RCC_MCOSOURCE_SYSCLK: System Clock selected as MCO clock
mbed_official	340:28d1f895c6fe	1417	* @arg RCC_MCOSOURCE_HSI14: HSI14 selected as MCO clock
mbed_official	340:28d1f895c6fe	1418	* @arg RCC_MCOSOURCE_HSI48: HSI48 selected as MCO clock
mbed_official	340:28d1f895c6fe	1419	* @param __MCODiv__: specifies the MCO clock prescaler.
mbed_official	340:28d1f895c6fe	1420	* This parameter can be one of the following values:
mbed_official	340:28d1f895c6fe	1421	* @arg RCC_MCO_NODIV: No division applied on MCO clock source
mbed_official	340:28d1f895c6fe	1422	*/
mbed_official	340:28d1f895c6fe	1423	#define __HAL_RCC_MCO_CONFIG(__MCOCLKSource__, __MCODiv__) \
mbed_official	340:28d1f895c6fe	1424	MODIFY_REG(RCC->CFGR, RCC_CFGR_MCO, __MCOCLKSource__)
mbed_official	340:28d1f895c6fe	1425
mbed_official	441:d2c15dda23c1	1426	#endif /* STM32F030x6 \|\| STM32F031x6 \|\| STM32F038xx \|\| STM32F070x6 \|\| */
mbed_official	441:d2c15dda23c1	1427	/* STM32F042x6 \|\| STM32F048xx \|\| */
mbed_official	441:d2c15dda23c1	1428	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
mbed_official	441:d2c15dda23c1	1429	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
mbed_official	441:d2c15dda23c1	1430
mbed_official	441:d2c15dda23c1	1431	#if defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
mbed_official	441:d2c15dda23c1	1432	defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	441:d2c15dda23c1	1433	/** @brief Macro to configure the USART2 clock (USART2CLK).
mbed_official	441:d2c15dda23c1	1434	* @param __USART2CLKSource__: specifies the USART2 clock source.
mbed_official	441:d2c15dda23c1	1435	* This parameter can be one of the following values:
mbed_official	441:d2c15dda23c1	1436	* @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock
mbed_official	441:d2c15dda23c1	1437	* @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
mbed_official	441:d2c15dda23c1	1438	* @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock
mbed_official	441:d2c15dda23c1	1439	* @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock
mbed_official	441:d2c15dda23c1	1440	*/
mbed_official	441:d2c15dda23c1	1441	#define __HAL_RCC_USART2_CONFIG(__USART2CLKSource__) \
mbed_official	441:d2c15dda23c1	1442	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART2SW, (uint32_t)(__USART2CLKSource__))
mbed_official	441:d2c15dda23c1	1443
mbed_official	441:d2c15dda23c1	1444	/** @brief Macro to get the USART2 clock source.
mbed_official	441:d2c15dda23c1	1445	* @retval The clock source can be one of the following values:
mbed_official	441:d2c15dda23c1	1446	* @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock
mbed_official	441:d2c15dda23c1	1447	* @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
mbed_official	441:d2c15dda23c1	1448	* @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock
mbed_official	441:d2c15dda23c1	1449	* @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock
mbed_official	441:d2c15dda23c1	1450	*/
mbed_official	441:d2c15dda23c1	1451	#define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART2SW)))
mbed_official	441:d2c15dda23c1	1452	#endif /* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F091xC \|\| STM32F098xx*/
mbed_official	340:28d1f895c6fe	1453
mbed_official	340:28d1f895c6fe	1454	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	340:28d1f895c6fe	1455	/** @brief Macro to configure the USART3 clock (USART3CLK).
mbed_official	340:28d1f895c6fe	1456	* @param __USART3CLKSource__: specifies the USART3 clock source.
mbed_official	340:28d1f895c6fe	1457	* This parameter can be one of the following values:
mbed_official	340:28d1f895c6fe	1458	* @arg RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock
mbed_official	340:28d1f895c6fe	1459	* @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock
mbed_official	340:28d1f895c6fe	1460	* @arg RCC_USART3CLKSOURCE_SYSCLK: System Clock selected as USART3 clock
mbed_official	340:28d1f895c6fe	1461	* @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock
mbed_official	340:28d1f895c6fe	1462	*/
mbed_official	340:28d1f895c6fe	1463	#define __HAL_RCC_USART3_CONFIG(__USART3CLKSource__) \
mbed_official	340:28d1f895c6fe	1464	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART3SW, (uint32_t)(__USART3CLKSource__))
mbed_official	340:28d1f895c6fe	1465
mbed_official	340:28d1f895c6fe	1466	/** @brief Macro to get the USART3 clock source.
mbed_official	340:28d1f895c6fe	1467	* @retval The clock source can be one of the following values:
mbed_official	340:28d1f895c6fe	1468	* @arg RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock
mbed_official	340:28d1f895c6fe	1469	* @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock
mbed_official	340:28d1f895c6fe	1470	* @arg RCC_USART3CLKSOURCE_SYSCLK: System Clock selected as USART3 clock
mbed_official	340:28d1f895c6fe	1471	* @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock
mbed_official	340:28d1f895c6fe	1472	*/
mbed_official	340:28d1f895c6fe	1473	#define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART3SW)))
mbed_official	340:28d1f895c6fe	1474
mbed_official	441:d2c15dda23c1	1475	#endif /* STM32F091xC \|\| STM32F098xx */
mbed_official	340:28d1f895c6fe	1476	/**
mbed_official	340:28d1f895c6fe	1477	* @}
mbed_official	340:28d1f895c6fe	1478	*/
mbed_official	340:28d1f895c6fe	1479
mbed_official	340:28d1f895c6fe	1480	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
mbed_official	340:28d1f895c6fe	1481	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
mbed_official	340:28d1f895c6fe	1482	defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	340:28d1f895c6fe	1483
mbed_official	340:28d1f895c6fe	1484	/** @defgroup RCCEx_IT_And_Flag RCCEx IT and Flag
mbed_official	340:28d1f895c6fe	1485	* @{
mbed_official	340:28d1f895c6fe	1486	*/
mbed_official	340:28d1f895c6fe	1487	/* Interrupt & Flag management */
mbed_official	340:28d1f895c6fe	1488
mbed_official	340:28d1f895c6fe	1489	/**
mbed_official	340:28d1f895c6fe	1490	* @brief Enables the specified CRS interrupts.
mbed_official	340:28d1f895c6fe	1491	* @param __INTERRUPT__: specifies the CRS interrupt sources to be enabled.
mbed_official	340:28d1f895c6fe	1492	* This parameter can be any combination of the following values:
mbed_official	340:28d1f895c6fe	1493	* @arg RCC_CRS_IT_SYNCOK
mbed_official	340:28d1f895c6fe	1494	* @arg RCC_CRS_IT_SYNCWARN
mbed_official	340:28d1f895c6fe	1495	* @arg RCC_CRS_IT_ERR
mbed_official	340:28d1f895c6fe	1496	* @arg RCC_CRS_IT_ESYNC
mbed_official	340:28d1f895c6fe	1497	* @retval None
mbed_official	340:28d1f895c6fe	1498	*/
mbed_official	340:28d1f895c6fe	1499	#define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) (CRS->CR \|= (__INTERRUPT__))
mbed_official	340:28d1f895c6fe	1500
mbed_official	340:28d1f895c6fe	1501	/**
mbed_official	340:28d1f895c6fe	1502	* @brief Disables the specified CRS interrupts.
mbed_official	340:28d1f895c6fe	1503	* @param __INTERRUPT__: specifies the CRS interrupt sources to be disabled.
mbed_official	340:28d1f895c6fe	1504	* This parameter can be any combination of the following values:
mbed_official	340:28d1f895c6fe	1505	* @arg RCC_CRS_IT_SYNCOK
mbed_official	340:28d1f895c6fe	1506	* @arg RCC_CRS_IT_SYNCWARN
mbed_official	340:28d1f895c6fe	1507	* @arg RCC_CRS_IT_ERR
mbed_official	340:28d1f895c6fe	1508	* @arg RCC_CRS_IT_ESYNC
mbed_official	340:28d1f895c6fe	1509	* @retval None
mbed_official	340:28d1f895c6fe	1510	*/
mbed_official	340:28d1f895c6fe	1511	#define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) (CRS->CR &= ~(__INTERRUPT__))
mbed_official	340:28d1f895c6fe	1512
mbed_official	340:28d1f895c6fe	1513	/** @brief Check the CRS's interrupt has occurred or not.
mbed_official	340:28d1f895c6fe	1514	* @param __INTERRUPT__: specifies the CRS interrupt source to check.
mbed_official	340:28d1f895c6fe	1515	* This parameter can be one of the following values:
mbed_official	340:28d1f895c6fe	1516	* @arg RCC_CRS_IT_SYNCOK
mbed_official	340:28d1f895c6fe	1517	* @arg RCC_CRS_IT_SYNCWARN
mbed_official	340:28d1f895c6fe	1518	* @arg RCC_CRS_IT_ERR
mbed_official	340:28d1f895c6fe	1519	* @arg RCC_CRS_IT_ESYNC
mbed_official	340:28d1f895c6fe	1520	* @retval The new state of __INTERRUPT__ (SET or RESET).
mbed_official	340:28d1f895c6fe	1521	*/
mbed_official	340:28d1f895c6fe	1522	#define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((CRS->CR & (__INTERRUPT__))? SET : RESET)
mbed_official	340:28d1f895c6fe	1523
mbed_official	340:28d1f895c6fe	1524	/** @brief Clear the CRS's interrupt pending bits
mbed_official	340:28d1f895c6fe	1525	* bits to clear the selected interrupt pending bits.
mbed_official	340:28d1f895c6fe	1526	* @param __INTERRUPT__: specifies the interrupt pending bit to clear.
mbed_official	340:28d1f895c6fe	1527	* This parameter can be any combination of the following values:
mbed_official	340:28d1f895c6fe	1528	* @arg RCC_CRS_IT_SYNCOK
mbed_official	340:28d1f895c6fe	1529	* @arg RCC_CRS_IT_SYNCWARN
mbed_official	340:28d1f895c6fe	1530	* @arg RCC_CRS_IT_ERR
mbed_official	340:28d1f895c6fe	1531	* @arg RCC_CRS_IT_ESYNC
mbed_official	340:28d1f895c6fe	1532	* @arg RCC_CRS_IT_TRIMOVF
mbed_official	340:28d1f895c6fe	1533	* @arg RCC_CRS_IT_SYNCERR
mbed_official	340:28d1f895c6fe	1534	* @arg RCC_CRS_IT_SYNCMISS
mbed_official	340:28d1f895c6fe	1535	*/
mbed_official	340:28d1f895c6fe	1536	/* CRS IT Error Mask */
mbed_official	340:28d1f895c6fe	1537	#define RCC_CRS_IT_ERROR_MASK ((uint32_t)(RCC_CRS_IT_TRIMOVF \| RCC_CRS_IT_SYNCERR \| RCC_CRS_IT_SYNCMISS))
mbed_official	340:28d1f895c6fe	1538
mbed_official	340:28d1f895c6fe	1539	#define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) ((((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK)!= 0) ? (CRS->ICR \|= CRS_ICR_ERRC) : \
mbed_official	340:28d1f895c6fe	1540	(CRS->ICR \|= (__INTERRUPT__)))
mbed_official	340:28d1f895c6fe	1541
mbed_official	340:28d1f895c6fe	1542	/**
mbed_official	340:28d1f895c6fe	1543	* @brief Checks whether the specified CRS flag is set or not.
mbed_official	340:28d1f895c6fe	1544	* @param _FLAG_: specifies the flag to check.
mbed_official	340:28d1f895c6fe	1545	* This parameter can be one of the following values:
mbed_official	340:28d1f895c6fe	1546	* @arg RCC_CRS_FLAG_SYNCOK
mbed_official	340:28d1f895c6fe	1547	* @arg RCC_CRS_FLAG_SYNCWARN
mbed_official	340:28d1f895c6fe	1548	* @arg RCC_CRS_FLAG_ERR
mbed_official	340:28d1f895c6fe	1549	* @arg RCC_CRS_FLAG_ESYNC
mbed_official	340:28d1f895c6fe	1550	* @arg RCC_CRS_FLAG_TRIMOVF
mbed_official	340:28d1f895c6fe	1551	* @arg RCC_CRS_FLAG_SYNCERR
mbed_official	340:28d1f895c6fe	1552	* @arg RCC_CRS_FLAG_SYNCMISS
mbed_official	340:28d1f895c6fe	1553	* @retval The new state of _FLAG_ (TRUE or FALSE).
mbed_official	340:28d1f895c6fe	1554	*/
mbed_official	340:28d1f895c6fe	1555	#define __HAL_RCC_CRS_GET_FLAG(_FLAG_) ((CRS->ISR & (_FLAG_)) == (_FLAG_))
mbed_official	340:28d1f895c6fe	1556
mbed_official	340:28d1f895c6fe	1557	/**
mbed_official	340:28d1f895c6fe	1558	* @brief Clears the CRS specified FLAG.
mbed_official	340:28d1f895c6fe	1559	* @param _FLAG_: specifies the flag to clear.
mbed_official	340:28d1f895c6fe	1560	* This parameter can be one of the following values:
mbed_official	340:28d1f895c6fe	1561	* @arg RCC_CRS_FLAG_SYNCOK
mbed_official	340:28d1f895c6fe	1562	* @arg RCC_CRS_FLAG_SYNCWARN
mbed_official	340:28d1f895c6fe	1563	* @arg RCC_CRS_FLAG_ERR
mbed_official	340:28d1f895c6fe	1564	* @arg RCC_CRS_FLAG_ESYNC
mbed_official	340:28d1f895c6fe	1565	* @arg RCC_CRS_FLAG_TRIMOVF
mbed_official	340:28d1f895c6fe	1566	* @arg RCC_CRS_FLAG_SYNCERR
mbed_official	340:28d1f895c6fe	1567	* @arg RCC_CRS_FLAG_SYNCMISS
mbed_official	340:28d1f895c6fe	1568	* @retval None
mbed_official	340:28d1f895c6fe	1569	*/
mbed_official	340:28d1f895c6fe	1570
mbed_official	340:28d1f895c6fe	1571	/* CRS Flag Error Mask */
mbed_official	340:28d1f895c6fe	1572	#define RCC_CRS_FLAG_ERROR_MASK ((uint32_t)(RCC_CRS_FLAG_TRIMOVF \| RCC_CRS_FLAG_SYNCERR \| RCC_CRS_FLAG_SYNCMISS))
mbed_official	340:28d1f895c6fe	1573
mbed_official	340:28d1f895c6fe	1574	#define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) ((((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK)!= 0) ? (CRS->ICR \|= CRS_ICR_ERRC) : \
mbed_official	340:28d1f895c6fe	1575	(CRS->ICR \|= (__FLAG__)))
mbed_official	340:28d1f895c6fe	1576
mbed_official	340:28d1f895c6fe	1577	/**
mbed_official	340:28d1f895c6fe	1578	* @}
mbed_official	340:28d1f895c6fe	1579	*/
mbed_official	340:28d1f895c6fe	1580
mbed_official	340:28d1f895c6fe	1581	/** @defgroup RCCEx_CRS_Extended_Features RCCEx CRS Extended Features
mbed_official	340:28d1f895c6fe	1582	* @{
mbed_official	340:28d1f895c6fe	1583	*/
mbed_official	340:28d1f895c6fe	1584	/**
mbed_official	340:28d1f895c6fe	1585	* @brief Enables the oscillator clock for frequency error counter.
mbed_official	340:28d1f895c6fe	1586	* @note when the CEN bit is set the CRS_CFGR register becomes write-protected.
mbed_official	340:28d1f895c6fe	1587	* @retval None
mbed_official	340:28d1f895c6fe	1588	*/
mbed_official	340:28d1f895c6fe	1589	#define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER() (CRS->CR \|= CRS_CR_CEN)
mbed_official	340:28d1f895c6fe	1590
mbed_official	340:28d1f895c6fe	1591	/**
mbed_official	340:28d1f895c6fe	1592	* @brief Disables the oscillator clock for frequency error counter.
mbed_official	340:28d1f895c6fe	1593	* @retval None
mbed_official	340:28d1f895c6fe	1594	*/
mbed_official	340:28d1f895c6fe	1595	#define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER() (CRS->CR &= ~CRS_CR_CEN)
mbed_official	340:28d1f895c6fe	1596
mbed_official	340:28d1f895c6fe	1597	/**
mbed_official	340:28d1f895c6fe	1598	* @brief Enables the automatic hardware adjustement of TRIM bits.
mbed_official	340:28d1f895c6fe	1599	* @note When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected.
mbed_official	340:28d1f895c6fe	1600	* @retval None
mbed_official	340:28d1f895c6fe	1601	*/
mbed_official	340:28d1f895c6fe	1602	#define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB() (CRS->CR \|= CRS_CR_AUTOTRIMEN)
mbed_official	340:28d1f895c6fe	1603
mbed_official	340:28d1f895c6fe	1604	/**
mbed_official	340:28d1f895c6fe	1605	* @brief Enables or disables the automatic hardware adjustement of TRIM bits.
mbed_official	340:28d1f895c6fe	1606	* @retval None
mbed_official	340:28d1f895c6fe	1607	*/
mbed_official	340:28d1f895c6fe	1608	#define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB() (CRS->CR &= ~CRS_CR_AUTOTRIMEN)
mbed_official	340:28d1f895c6fe	1609
mbed_official	340:28d1f895c6fe	1610	/**
mbed_official	340:28d1f895c6fe	1611	* @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies
mbed_official	340:28d1f895c6fe	1612	* @note The RELOAD value should be selected according to the ratio between the target frequency and the frequency
mbed_official	340:28d1f895c6fe	1613	* of the synchronization source after prescaling. It is then decreased by one in order to
mbed_official	340:28d1f895c6fe	1614	* reach the expected synchronization on the zero value. The formula is the following:
mbed_official	340:28d1f895c6fe	1615	* RELOAD = (fTARGET / fSYNC) -1
mbed_official	340:28d1f895c6fe	1616	* @param _FTARGET_ Target frequency (value in Hz)
mbed_official	340:28d1f895c6fe	1617	* @param _FSYNC_ Synchronization signal frequency (value in Hz)
mbed_official	340:28d1f895c6fe	1618	* @retval None
mbed_official	340:28d1f895c6fe	1619	*/
mbed_official	340:28d1f895c6fe	1620	#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE(_FTARGET_, _FSYNC_) (((_FTARGET_) / (_FSYNC_)) - 1)
mbed_official	340:28d1f895c6fe	1621
mbed_official	340:28d1f895c6fe	1622	/**
mbed_official	340:28d1f895c6fe	1623	* @}
mbed_official	340:28d1f895c6fe	1624	*/
mbed_official	340:28d1f895c6fe	1625
mbed_official	340:28d1f895c6fe	1626	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
mbed_official	340:28d1f895c6fe	1627	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
mbed_official	340:28d1f895c6fe	1628	/* STM32F091xC \|\| STM32F098xx */
mbed_official	340:28d1f895c6fe	1629
mbed_official	340:28d1f895c6fe	1630	/**
mbed_official	340:28d1f895c6fe	1631	* @}
mbed_official	340:28d1f895c6fe	1632	*/
mbed_official	340:28d1f895c6fe	1633
mbed_official	340:28d1f895c6fe	1634	/* Exported functions --------------------------------------------------------*/
mbed_official	340:28d1f895c6fe	1635	/** @addtogroup RCCEx_Exported_Functions
mbed_official	340:28d1f895c6fe	1636	* @{
mbed_official	340:28d1f895c6fe	1637	*/
mbed_official	340:28d1f895c6fe	1638
mbed_official	340:28d1f895c6fe	1639	/** @addtogroup RCCEx_Exported_Functions_Group1
mbed_official	340:28d1f895c6fe	1640	* @{
mbed_official	340:28d1f895c6fe	1641	*/
mbed_official	340:28d1f895c6fe	1642
mbed_official	340:28d1f895c6fe	1643	HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
mbed_official	340:28d1f895c6fe	1644	void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
mbed_official	340:28d1f895c6fe	1645
mbed_official	340:28d1f895c6fe	1646	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
mbed_official	340:28d1f895c6fe	1647	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
mbed_official	340:28d1f895c6fe	1648	defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	340:28d1f895c6fe	1649	void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit);
mbed_official	340:28d1f895c6fe	1650	void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void);
mbed_official	340:28d1f895c6fe	1651	void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo);
mbed_official	441:d2c15dda23c1	1652	uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout);
mbed_official	340:28d1f895c6fe	1653	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
mbed_official	340:28d1f895c6fe	1654	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
mbed_official	340:28d1f895c6fe	1655	/* STM32F091xC \|\| STM32F098xx */
mbed_official	340:28d1f895c6fe	1656
mbed_official	340:28d1f895c6fe	1657
mbed_official	340:28d1f895c6fe	1658	/**
mbed_official	340:28d1f895c6fe	1659	* @}
mbed_official	340:28d1f895c6fe	1660	*/
mbed_official	340:28d1f895c6fe	1661
mbed_official	340:28d1f895c6fe	1662	/**
mbed_official	340:28d1f895c6fe	1663	* @}
mbed_official	340:28d1f895c6fe	1664	*/
mbed_official	340:28d1f895c6fe	1665
mbed_official	340:28d1f895c6fe	1666	/**
mbed_official	340:28d1f895c6fe	1667	* @}
mbed_official	340:28d1f895c6fe	1668	*/
mbed_official	340:28d1f895c6fe	1669
mbed_official	340:28d1f895c6fe	1670	/**
mbed_official	340:28d1f895c6fe	1671	* @}
mbed_official	340:28d1f895c6fe	1672	*/
mbed_official	340:28d1f895c6fe	1673
mbed_official	340:28d1f895c6fe	1674	#ifdef __cplusplus
mbed_official	340:28d1f895c6fe	1675	}
mbed_official	340:28d1f895c6fe	1676	#endif
mbed_official	340:28d1f895c6fe	1677
mbed_official	340:28d1f895c6fe	1678	#endif /* __STM32F0xx_HAL_RCC_EX_H */
mbed_official	340:28d1f895c6fe	1679
mbed_official	340:28d1f895c6fe	1680	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/