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targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_rcc.h@579:53297373a894, 2015-07-01 (annotated)

Committer:: mbed_official
Date:: Wed Jul 01 09:45:11 2015 +0100
Revision:: 579:53297373a894
Parent:: 441:d2c15dda23c1
Child:: 630:825f75ca301e

Synchronized with git revision d5b4d2ab9c47edb4dc5776e7177b0c2263459081

Full URL: https://github.com/mbedmicro/mbed/commit/d5b4d2ab9c47edb4dc5776e7177b0c2263459081/

Initial version of drivers for SAMR21

Who changed what in which revision?

User	Revision	Line number	New contents of line
mbed_official	340:28d1f895c6fe	1	/**
mbed_official	340:28d1f895c6fe	2	******************************************************************************
mbed_official	340:28d1f895c6fe	3	* @file stm32f0xx_hal_rcc.h
mbed_official	340:28d1f895c6fe	4	* @author MCD Application Team
mbed_official	441:d2c15dda23c1	5	* @version V1.2.0
mbed_official	441:d2c15dda23c1	6	* @date 11-December-2014
mbed_official	340:28d1f895c6fe	7	* @brief Header file of RCC HAL module.
mbed_official	340:28d1f895c6fe	8	******************************************************************************
mbed_official	340:28d1f895c6fe	9	* @attention
mbed_official	340:28d1f895c6fe	10	*
mbed_official	340:28d1f895c6fe	11	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
mbed_official	340:28d1f895c6fe	12	*
mbed_official	340:28d1f895c6fe	13	* Redistribution and use in source and binary forms, with or without modification,
mbed_official	340:28d1f895c6fe	14	* are permitted provided that the following conditions are met:
mbed_official	340:28d1f895c6fe	15	* 1. Redistributions of source code must retain the above copyright notice,
mbed_official	340:28d1f895c6fe	16	* this list of conditions and the following disclaimer.
mbed_official	340:28d1f895c6fe	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official	340:28d1f895c6fe	18	* this list of conditions and the following disclaimer in the documentation
mbed_official	340:28d1f895c6fe	19	* and/or other materials provided with the distribution.
mbed_official	340:28d1f895c6fe	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official	340:28d1f895c6fe	21	* may be used to endorse or promote products derived from this software
mbed_official	340:28d1f895c6fe	22	* without specific prior written permission.
mbed_official	340:28d1f895c6fe	23	*
mbed_official	340:28d1f895c6fe	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official	340:28d1f895c6fe	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official	340:28d1f895c6fe	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official	340:28d1f895c6fe	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official	340:28d1f895c6fe	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official	340:28d1f895c6fe	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official	340:28d1f895c6fe	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official	340:28d1f895c6fe	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official	340:28d1f895c6fe	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official	340:28d1f895c6fe	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official	340:28d1f895c6fe	34	*
mbed_official	340:28d1f895c6fe	35	******************************************************************************
mbed_official	340:28d1f895c6fe	36	*/
mbed_official	340:28d1f895c6fe	37
mbed_official	340:28d1f895c6fe	38	/* Define to prevent recursive inclusion -------------------------------------*/
mbed_official	340:28d1f895c6fe	39	#ifndef __STM32F0xx_HAL_RCC_H
mbed_official	340:28d1f895c6fe	40	#define __STM32F0xx_HAL_RCC_H
mbed_official	340:28d1f895c6fe	41
mbed_official	340:28d1f895c6fe	42	#ifdef __cplusplus
mbed_official	340:28d1f895c6fe	43	extern "C" {
mbed_official	340:28d1f895c6fe	44	#endif
mbed_official	340:28d1f895c6fe	45
mbed_official	340:28d1f895c6fe	46	/* Includes ------------------------------------------------------------------*/
mbed_official	340:28d1f895c6fe	47	#include "stm32f0xx_hal_def.h"
mbed_official	340:28d1f895c6fe	48
mbed_official	340:28d1f895c6fe	49	/** @addtogroup STM32F0xx_HAL_Driver
mbed_official	340:28d1f895c6fe	50	* @{
mbed_official	340:28d1f895c6fe	51	*/
mbed_official	340:28d1f895c6fe	52
mbed_official	340:28d1f895c6fe	53	/** @addtogroup RCC
mbed_official	340:28d1f895c6fe	54	* @{
mbed_official	340:28d1f895c6fe	55	*/
mbed_official	340:28d1f895c6fe	56
mbed_official	340:28d1f895c6fe	57	/* Exported types ------------------------------------------------------------*/
mbed_official	340:28d1f895c6fe	58
mbed_official	340:28d1f895c6fe	59	/** @defgroup RCC_Exported_Types RCC Exported Types
mbed_official	340:28d1f895c6fe	60	* @{
mbed_official	340:28d1f895c6fe	61	*/
mbed_official	340:28d1f895c6fe	62
mbed_official	340:28d1f895c6fe	63	/**
mbed_official	340:28d1f895c6fe	64	* @brief RCC PLL configuration structure definition
mbed_official	340:28d1f895c6fe	65	*/
mbed_official	340:28d1f895c6fe	66	typedef struct
mbed_official	340:28d1f895c6fe	67	{
mbed_official	340:28d1f895c6fe	68	uint32_t PLLState; /*!< PLLState: The new state of the PLL.
mbed_official	340:28d1f895c6fe	69	This parameter can be a value of @ref RCC_PLL_Config */
mbed_official	340:28d1f895c6fe	70
mbed_official	340:28d1f895c6fe	71	uint32_t PLLSource; /*!< PLLSource: PLL entry clock source.
mbed_official	340:28d1f895c6fe	72	This parameter must be a value of @ref RCC_PLL_Clock_Source */
mbed_official	340:28d1f895c6fe	73
mbed_official	340:28d1f895c6fe	74	uint32_t PREDIV; /*!< PREDIV: Predivision factor for PLL VCO input clock
mbed_official	340:28d1f895c6fe	75	This parameter must be a value of @ref RCC_PLL_Prediv_Factor */
mbed_official	340:28d1f895c6fe	76
mbed_official	340:28d1f895c6fe	77	uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO input clock
mbed_official	340:28d1f895c6fe	78	This parameter must be a value of @ref RCC_PLL_Multiplication_Factor */
mbed_official	340:28d1f895c6fe	79
mbed_official	340:28d1f895c6fe	80	}RCC_PLLInitTypeDef;
mbed_official	340:28d1f895c6fe	81
mbed_official	340:28d1f895c6fe	82	/**
mbed_official	340:28d1f895c6fe	83	* @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
mbed_official	340:28d1f895c6fe	84	*/
mbed_official	340:28d1f895c6fe	85	typedef struct
mbed_official	340:28d1f895c6fe	86	{
mbed_official	340:28d1f895c6fe	87	uint32_t OscillatorType; /*!< The Oscillators to be configured.
mbed_official	340:28d1f895c6fe	88	This parameter can be a value of @ref RCC_Oscillator_Type */
mbed_official	340:28d1f895c6fe	89
mbed_official	340:28d1f895c6fe	90	uint32_t HSEState; /*!< The new state of the HSE.
mbed_official	340:28d1f895c6fe	91	This parameter can be a value of @ref RCC_HSE_Config */
mbed_official	340:28d1f895c6fe	92
mbed_official	340:28d1f895c6fe	93	uint32_t LSEState; /*!< The new state of the LSE.
mbed_official	340:28d1f895c6fe	94	This parameter can be a value of @ref RCC_LSE_Config */
mbed_official	340:28d1f895c6fe	95
mbed_official	340:28d1f895c6fe	96	uint32_t HSIState; /*!< The new state of the HSI.
mbed_official	340:28d1f895c6fe	97	This parameter can be a value of @ref RCC_HSI_Config */
mbed_official	340:28d1f895c6fe	98
mbed_official	340:28d1f895c6fe	99	uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
mbed_official	340:28d1f895c6fe	100	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
mbed_official	340:28d1f895c6fe	101
mbed_official	340:28d1f895c6fe	102	uint32_t HSI14State; /*!< The new state of the HSI14.
mbed_official	340:28d1f895c6fe	103	This parameter can be a value of @ref RCC_HSI14_Config */
mbed_official	340:28d1f895c6fe	104
mbed_official	340:28d1f895c6fe	105	uint32_t HSI14CalibrationValue; /*!< The HSI14 calibration trimming value (default is RCC_HSI14CALIBRATION_DEFAULT).
mbed_official	340:28d1f895c6fe	106	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
mbed_official	340:28d1f895c6fe	107
mbed_official	441:d2c15dda23c1	108	uint32_t HSI48State; /*!< The new state of the HSI48 (only applicable to STM32F07x, STM32F0x2 and STM32F09x devices).
mbed_official	340:28d1f895c6fe	109	This parameter can be a value of @ref RCCEx_HSI48_Config */
mbed_official	340:28d1f895c6fe	110
mbed_official	340:28d1f895c6fe	111	uint32_t LSIState; /*!< The new state of the LSI.
mbed_official	340:28d1f895c6fe	112	This parameter can be a value of @ref RCC_LSI_Config */
mbed_official	340:28d1f895c6fe	113
mbed_official	340:28d1f895c6fe	114	RCC_PLLInitTypeDef PLL; /!< PLL structure parameters /
mbed_official	340:28d1f895c6fe	115
mbed_official	340:28d1f895c6fe	116	}RCC_OscInitTypeDef;
mbed_official	340:28d1f895c6fe	117
mbed_official	340:28d1f895c6fe	118	/**
mbed_official	340:28d1f895c6fe	119	* @brief RCC System, AHB and APB busses clock configuration structure definition
mbed_official	340:28d1f895c6fe	120	*/
mbed_official	340:28d1f895c6fe	121	typedef struct
mbed_official	340:28d1f895c6fe	122	{
mbed_official	340:28d1f895c6fe	123	uint32_t ClockType; /*!< The clock to be configured.
mbed_official	340:28d1f895c6fe	124	This parameter can be a value of @ref RCC_System_Clock_Type */
mbed_official	340:28d1f895c6fe	125
mbed_official	340:28d1f895c6fe	126	uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.
mbed_official	340:28d1f895c6fe	127	This parameter can be a value of @ref RCC_System_Clock_Source */
mbed_official	340:28d1f895c6fe	128
mbed_official	340:28d1f895c6fe	129	uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
mbed_official	340:28d1f895c6fe	130	This parameter can be a value of @ref RCC_AHB_Clock_Source */
mbed_official	340:28d1f895c6fe	131
mbed_official	340:28d1f895c6fe	132	uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
mbed_official	340:28d1f895c6fe	133	This parameter can be a value of @ref RCC_APB1_Clock_Source */
mbed_official	340:28d1f895c6fe	134
mbed_official	340:28d1f895c6fe	135	}RCC_ClkInitTypeDef;
mbed_official	340:28d1f895c6fe	136
mbed_official	340:28d1f895c6fe	137	/**
mbed_official	340:28d1f895c6fe	138	* @}
mbed_official	340:28d1f895c6fe	139	*/
mbed_official	340:28d1f895c6fe	140
mbed_official	340:28d1f895c6fe	141	/* Exported constants --------------------------------------------------------*/
mbed_official	340:28d1f895c6fe	142	/** @defgroup RCC_Exported_Constants RCC Exported Constants
mbed_official	340:28d1f895c6fe	143	* @{
mbed_official	340:28d1f895c6fe	144	*/
mbed_official	340:28d1f895c6fe	145
mbed_official	340:28d1f895c6fe	146	/** @defgroup RCC_BitAddress_AliasRegion RCC BitAddress AliasRegion
mbed_official	340:28d1f895c6fe	147	* @brief RCC registers bit address in the alias region
mbed_official	340:28d1f895c6fe	148	* @{
mbed_official	340:28d1f895c6fe	149	*/
mbed_official	340:28d1f895c6fe	150	#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
mbed_official	340:28d1f895c6fe	151	/* --- CR Register ---*/
mbed_official	340:28d1f895c6fe	152	#define RCC_CR_OFFSET (RCC_OFFSET + 0x00)
mbed_official	340:28d1f895c6fe	153	/* --- CFGR Register ---*/
mbed_official	340:28d1f895c6fe	154	#define RCC_CFGR_OFFSET (RCC_OFFSET + 0x04)
mbed_official	340:28d1f895c6fe	155	/* --- CIR Register ---*/
mbed_official	340:28d1f895c6fe	156	#define RCC_CIR_OFFSET (RCC_OFFSET + 0x08)
mbed_official	340:28d1f895c6fe	157	/* --- BDCR Register ---*/
mbed_official	340:28d1f895c6fe	158	#define RCC_BDCR_OFFSET (RCC_OFFSET + 0x20)
mbed_official	340:28d1f895c6fe	159	/* --- CSR Register ---*/
mbed_official	340:28d1f895c6fe	160	#define RCC_CSR_OFFSET (RCC_OFFSET + 0x24)
mbed_official	340:28d1f895c6fe	161	/* --- CR2 Register ---*/
mbed_official	340:28d1f895c6fe	162	#define RCC_CR2_OFFSET (RCC_OFFSET + 0x34)
mbed_official	340:28d1f895c6fe	163
mbed_official	340:28d1f895c6fe	164	/* CR register byte 2 (Bits[23:16]) base address */
mbed_official	340:28d1f895c6fe	165	#define RCC_CR_BYTE2_ADDRESS (PERIPH_BASE + RCC_CR_OFFSET + 0x02)
mbed_official	340:28d1f895c6fe	166
mbed_official	340:28d1f895c6fe	167	/* CIR register byte 1 (Bits[15:8]) base address */
mbed_official	340:28d1f895c6fe	168	#define RCC_CIR_BYTE1_ADDRESS (PERIPH_BASE + RCC_CIR_OFFSET + 0x01)
mbed_official	340:28d1f895c6fe	169
mbed_official	340:28d1f895c6fe	170	/* CIR register byte 2 (Bits[23:16]) base address */
mbed_official	340:28d1f895c6fe	171	#define RCC_CIR_BYTE2_ADDRESS (PERIPH_BASE + RCC_CIR_OFFSET + 0x02)
mbed_official	340:28d1f895c6fe	172
mbed_official	340:28d1f895c6fe	173	/* CSR register byte 1 (Bits[15:8]) base address */
mbed_official	340:28d1f895c6fe	174	#define RCC_CSR_BYTE1_ADDRESS (PERIPH_BASE + RCC_CSR_OFFSET + 0x01)
mbed_official	340:28d1f895c6fe	175
mbed_official	340:28d1f895c6fe	176	/* BDCR register byte 0 (Bits[7:0] base address */
mbed_official	340:28d1f895c6fe	177	#define RCC_BDCR_BYTE0_ADDRESS (PERIPH_BASE + RCC_BDCR_OFFSET)
mbed_official	340:28d1f895c6fe	178
mbed_official	340:28d1f895c6fe	179	#define RCC_CFGR_PLLMUL_BITNUMBER 18
mbed_official	340:28d1f895c6fe	180	#define RCC_CFGR2_PREDIV_BITNUMBER 0
mbed_official	340:28d1f895c6fe	181
mbed_official	340:28d1f895c6fe	182	/**
mbed_official	340:28d1f895c6fe	183	* @}
mbed_official	340:28d1f895c6fe	184	*/
mbed_official	340:28d1f895c6fe	185
mbed_official	340:28d1f895c6fe	186	/** @defgroup RCC_Timeout RCC Timeout
mbed_official	340:28d1f895c6fe	187	* @{
mbed_official	340:28d1f895c6fe	188	*/
mbed_official	340:28d1f895c6fe	189	/* LSE state change timeout */
mbed_official	340:28d1f895c6fe	190	#define LSE_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */
mbed_official	340:28d1f895c6fe	191
mbed_official	340:28d1f895c6fe	192	/* Disable Backup domain write protection state change timeout */
mbed_official	340:28d1f895c6fe	193	#define DBP_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
mbed_official	340:28d1f895c6fe	194	/**
mbed_official	340:28d1f895c6fe	195	* @}
mbed_official	340:28d1f895c6fe	196	*/
mbed_official	340:28d1f895c6fe	197
mbed_official	340:28d1f895c6fe	198	/** @defgroup RCC_Oscillator_Type RCC Oscillator Type
mbed_official	340:28d1f895c6fe	199	* @{
mbed_official	340:28d1f895c6fe	200	*/
mbed_official	340:28d1f895c6fe	201	#define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000)
mbed_official	340:28d1f895c6fe	202	#define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001)
mbed_official	340:28d1f895c6fe	203	#define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002)
mbed_official	340:28d1f895c6fe	204	#define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004)
mbed_official	340:28d1f895c6fe	205	#define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008)
mbed_official	340:28d1f895c6fe	206	#define RCC_OSCILLATORTYPE_HSI14 ((uint32_t)0x00000010)
mbed_official	340:28d1f895c6fe	207	#define RCC_OSCILLATORTYPE_HSI48 ((uint32_t)0x00000020)
mbed_official	340:28d1f895c6fe	208
mbed_official	340:28d1f895c6fe	209	#define IS_RCC_OSCILLATORTYPE(OSCILLATOR) (((OSCILLATOR) == RCC_OSCILLATORTYPE_NONE) \|\| \
mbed_official	340:28d1f895c6fe	210	(((OSCILLATOR) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) \|\| \
mbed_official	340:28d1f895c6fe	211	(((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) \|\| \
mbed_official	340:28d1f895c6fe	212	(((OSCILLATOR) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) \|\| \
mbed_official	340:28d1f895c6fe	213	(((OSCILLATOR) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) \|\| \
mbed_official	340:28d1f895c6fe	214	(((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI14) == RCC_OSCILLATORTYPE_HSI14) \|\| \
mbed_official	340:28d1f895c6fe	215	(((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48))
mbed_official	340:28d1f895c6fe	216	/**
mbed_official	340:28d1f895c6fe	217	* @}
mbed_official	340:28d1f895c6fe	218	*/
mbed_official	340:28d1f895c6fe	219
mbed_official	340:28d1f895c6fe	220	/** @defgroup RCC_HSE_Config RCC HSE Config
mbed_official	340:28d1f895c6fe	221	* @{
mbed_official	340:28d1f895c6fe	222	*/
mbed_official	340:28d1f895c6fe	223	#define RCC_HSE_OFF ((uint8_t)0x00)
mbed_official	340:28d1f895c6fe	224	#define RCC_HSE_ON ((uint8_t)0x01)
mbed_official	340:28d1f895c6fe	225	#define RCC_HSE_BYPASS ((uint8_t)0x05)
mbed_official	340:28d1f895c6fe	226
mbed_official	340:28d1f895c6fe	227	#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) \|\| ((HSE) == RCC_HSE_ON) \|\| \
mbed_official	340:28d1f895c6fe	228	((HSE) == RCC_HSE_BYPASS))
mbed_official	340:28d1f895c6fe	229	/**
mbed_official	340:28d1f895c6fe	230	* @}
mbed_official	340:28d1f895c6fe	231	*/
mbed_official	340:28d1f895c6fe	232
mbed_official	340:28d1f895c6fe	233	/** @defgroup RCC_LSE_Config RCC_LSE_Config
mbed_official	340:28d1f895c6fe	234	* @{
mbed_official	340:28d1f895c6fe	235	*/
mbed_official	340:28d1f895c6fe	236	#define RCC_LSE_OFF ((uint8_t)0x00)
mbed_official	340:28d1f895c6fe	237	#define RCC_LSE_ON ((uint8_t)0x01)
mbed_official	340:28d1f895c6fe	238	#define RCC_LSE_BYPASS ((uint8_t)0x05)
mbed_official	340:28d1f895c6fe	239
mbed_official	340:28d1f895c6fe	240	#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) \|\| ((LSE) == RCC_LSE_ON) \|\| \
mbed_official	340:28d1f895c6fe	241	((LSE) == RCC_LSE_BYPASS))
mbed_official	340:28d1f895c6fe	242	/**
mbed_official	340:28d1f895c6fe	243	* @}
mbed_official	340:28d1f895c6fe	244	*/
mbed_official	340:28d1f895c6fe	245
mbed_official	340:28d1f895c6fe	246	/** @defgroup RCC_HSI_Config RCC HSI Config
mbed_official	340:28d1f895c6fe	247	* @{
mbed_official	340:28d1f895c6fe	248	*/
mbed_official	340:28d1f895c6fe	249	#define RCC_HSI_OFF ((uint8_t)0x00)
mbed_official	340:28d1f895c6fe	250	#define RCC_HSI_ON ((uint8_t)0x01)
mbed_official	340:28d1f895c6fe	251
mbed_official	340:28d1f895c6fe	252	#define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) \|\| ((HSI) == RCC_HSI_ON))
mbed_official	340:28d1f895c6fe	253
mbed_official	340:28d1f895c6fe	254	#define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x10) /* Default HSI calibration trimming value */
mbed_official	340:28d1f895c6fe	255	/**
mbed_official	340:28d1f895c6fe	256	* @}
mbed_official	340:28d1f895c6fe	257	*/
mbed_official	340:28d1f895c6fe	258
mbed_official	340:28d1f895c6fe	259	/** @defgroup RCC_HSI14_Config RCC HSI14 Config
mbed_official	340:28d1f895c6fe	260	* @{
mbed_official	340:28d1f895c6fe	261	*/
mbed_official	340:28d1f895c6fe	262	#define RCC_HSI14_OFF ((uint32_t)0x00)
mbed_official	340:28d1f895c6fe	263	#define RCC_HSI14_ON RCC_CR2_HSI14ON
mbed_official	340:28d1f895c6fe	264	#define RCC_HSI14_ADC_CONTROL (~RCC_CR2_HSI14DIS)
mbed_official	340:28d1f895c6fe	265
mbed_official	340:28d1f895c6fe	266	#define IS_RCC_HSI14(HSI14) (((HSI14) == RCC_HSI14_OFF) \|\| ((HSI14) == RCC_HSI14_ON) \|\| ((HSI14) == RCC_HSI14_ADC_CONTROL))
mbed_official	340:28d1f895c6fe	267
mbed_official	340:28d1f895c6fe	268	#define RCC_HSI14CALIBRATION_DEFAULT ((uint32_t)0x10) /* Default HSI14 calibration trimming value */
mbed_official	340:28d1f895c6fe	269	/**
mbed_official	340:28d1f895c6fe	270	* @}
mbed_official	340:28d1f895c6fe	271	*/
mbed_official	340:28d1f895c6fe	272
mbed_official	340:28d1f895c6fe	273	/** @defgroup RCC_LSI_Config RCC LSI Config
mbed_official	340:28d1f895c6fe	274	* @{
mbed_official	340:28d1f895c6fe	275	*/
mbed_official	340:28d1f895c6fe	276	#define RCC_LSI_OFF ((uint8_t)0x00)
mbed_official	340:28d1f895c6fe	277	#define RCC_LSI_ON ((uint8_t)0x01)
mbed_official	340:28d1f895c6fe	278
mbed_official	340:28d1f895c6fe	279	#define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) \|\| ((LSI) == RCC_LSI_ON))
mbed_official	340:28d1f895c6fe	280	/**
mbed_official	340:28d1f895c6fe	281	* @}
mbed_official	340:28d1f895c6fe	282	*/
mbed_official	340:28d1f895c6fe	283
mbed_official	340:28d1f895c6fe	284	/** @defgroup RCC_PLL_Config RCC PLL Config
mbed_official	340:28d1f895c6fe	285	* @{
mbed_official	340:28d1f895c6fe	286	*/
mbed_official	340:28d1f895c6fe	287	#define RCC_PLL_NONE ((uint8_t)0x00)
mbed_official	340:28d1f895c6fe	288	#define RCC_PLL_OFF ((uint8_t)0x01)
mbed_official	340:28d1f895c6fe	289	#define RCC_PLL_ON ((uint8_t)0x02)
mbed_official	340:28d1f895c6fe	290
mbed_official	340:28d1f895c6fe	291	#define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) \|\|((PLL) == RCC_PLL_OFF) \|\| ((PLL) == RCC_PLL_ON))
mbed_official	340:28d1f895c6fe	292	/**
mbed_official	340:28d1f895c6fe	293	* @}
mbed_official	340:28d1f895c6fe	294	*/
mbed_official	340:28d1f895c6fe	295
mbed_official	340:28d1f895c6fe	296	/** @defgroup RCC_PLL_Prediv_Factor RCC PLL Prediv Factor
mbed_official	340:28d1f895c6fe	297	* @{
mbed_official	340:28d1f895c6fe	298	*/
mbed_official	340:28d1f895c6fe	299	#define RCC_PREDIV_DIV1 RCC_CFGR2_PREDIV_DIV1
mbed_official	340:28d1f895c6fe	300	#define RCC_PREDIV_DIV2 RCC_CFGR2_PREDIV_DIV2
mbed_official	340:28d1f895c6fe	301	#define RCC_PREDIV_DIV3 RCC_CFGR2_PREDIV_DIV3
mbed_official	340:28d1f895c6fe	302	#define RCC_PREDIV_DIV4 RCC_CFGR2_PREDIV_DIV4
mbed_official	340:28d1f895c6fe	303	#define RCC_PREDIV_DIV5 RCC_CFGR2_PREDIV_DIV5
mbed_official	340:28d1f895c6fe	304	#define RCC_PREDIV_DIV6 RCC_CFGR2_PREDIV_DIV6
mbed_official	340:28d1f895c6fe	305	#define RCC_PREDIV_DIV7 RCC_CFGR2_PREDIV_DIV7
mbed_official	340:28d1f895c6fe	306	#define RCC_PREDIV_DIV8 RCC_CFGR2_PREDIV_DIV8
mbed_official	340:28d1f895c6fe	307	#define RCC_PREDIV_DIV9 RCC_CFGR2_PREDIV_DIV9
mbed_official	340:28d1f895c6fe	308	#define RCC_PREDIV_DIV10 RCC_CFGR2_PREDIV_DIV10
mbed_official	340:28d1f895c6fe	309	#define RCC_PREDIV_DIV11 RCC_CFGR2_PREDIV_DIV11
mbed_official	340:28d1f895c6fe	310	#define RCC_PREDIV_DIV12 RCC_CFGR2_PREDIV_DIV12
mbed_official	340:28d1f895c6fe	311	#define RCC_PREDIV_DIV13 RCC_CFGR2_PREDIV_DIV13
mbed_official	340:28d1f895c6fe	312	#define RCC_PREDIV_DIV14 RCC_CFGR2_PREDIV_DIV14
mbed_official	340:28d1f895c6fe	313	#define RCC_PREDIV_DIV15 RCC_CFGR2_PREDIV_DIV15
mbed_official	340:28d1f895c6fe	314	#define RCC_PREDIV_DIV16 RCC_CFGR2_PREDIV_DIV16
mbed_official	340:28d1f895c6fe	315
mbed_official	340:28d1f895c6fe	316	#define IS_RCC_PREDIV(PREDIV) (((PREDIV) == RCC_PREDIV_DIV1) \|\| ((PREDIV) == RCC_PREDIV_DIV2) \|\| \
mbed_official	340:28d1f895c6fe	317	((PREDIV) == RCC_PREDIV_DIV3) \|\| ((PREDIV) == RCC_PREDIV_DIV4) \|\| \
mbed_official	340:28d1f895c6fe	318	((PREDIV) == RCC_PREDIV_DIV5) \|\| ((PREDIV) == RCC_PREDIV_DIV6) \|\| \
mbed_official	340:28d1f895c6fe	319	((PREDIV) == RCC_PREDIV_DIV7) \|\| ((PREDIV) == RCC_PREDIV_DIV8) \|\| \
mbed_official	340:28d1f895c6fe	320	((PREDIV) == RCC_PREDIV_DIV9) \|\| ((PREDIV) == RCC_PREDIV_DIV10) \|\| \
mbed_official	340:28d1f895c6fe	321	((PREDIV) == RCC_PREDIV_DIV11) \|\| ((PREDIV) == RCC_PREDIV_DIV12) \|\| \
mbed_official	340:28d1f895c6fe	322	((PREDIV) == RCC_PREDIV_DIV13) \|\| ((PREDIV) == RCC_PREDIV_DIV14) \|\| \
mbed_official	340:28d1f895c6fe	323	((PREDIV) == RCC_PREDIV_DIV15) \|\| ((PREDIV) == RCC_PREDIV_DIV16))
mbed_official	340:28d1f895c6fe	324	/**
mbed_official	340:28d1f895c6fe	325	* @}
mbed_official	340:28d1f895c6fe	326	*/
mbed_official	340:28d1f895c6fe	327
mbed_official	340:28d1f895c6fe	328	/** @defgroup RCC_PLL_Multiplication_Factor RCC PLL Multiplication Factor
mbed_official	340:28d1f895c6fe	329	* @{
mbed_official	340:28d1f895c6fe	330	*/
mbed_official	340:28d1f895c6fe	331	#define RCC_PLL_MUL2 RCC_CFGR_PLLMUL2
mbed_official	340:28d1f895c6fe	332	#define RCC_PLL_MUL3 RCC_CFGR_PLLMUL3
mbed_official	340:28d1f895c6fe	333	#define RCC_PLL_MUL4 RCC_CFGR_PLLMUL4
mbed_official	340:28d1f895c6fe	334	#define RCC_PLL_MUL5 RCC_CFGR_PLLMUL5
mbed_official	340:28d1f895c6fe	335	#define RCC_PLL_MUL6 RCC_CFGR_PLLMUL6
mbed_official	340:28d1f895c6fe	336	#define RCC_PLL_MUL7 RCC_CFGR_PLLMUL7
mbed_official	340:28d1f895c6fe	337	#define RCC_PLL_MUL8 RCC_CFGR_PLLMUL8
mbed_official	340:28d1f895c6fe	338	#define RCC_PLL_MUL9 RCC_CFGR_PLLMUL9
mbed_official	340:28d1f895c6fe	339	#define RCC_PLL_MUL10 RCC_CFGR_PLLMUL10
mbed_official	340:28d1f895c6fe	340	#define RCC_PLL_MUL11 RCC_CFGR_PLLMUL11
mbed_official	340:28d1f895c6fe	341	#define RCC_PLL_MUL12 RCC_CFGR_PLLMUL12
mbed_official	340:28d1f895c6fe	342	#define RCC_PLL_MUL13 RCC_CFGR_PLLMUL13
mbed_official	340:28d1f895c6fe	343	#define RCC_PLL_MUL14 RCC_CFGR_PLLMUL14
mbed_official	340:28d1f895c6fe	344	#define RCC_PLL_MUL15 RCC_CFGR_PLLMUL15
mbed_official	340:28d1f895c6fe	345	#define RCC_PLL_MUL16 RCC_CFGR_PLLMUL16
mbed_official	340:28d1f895c6fe	346
mbed_official	340:28d1f895c6fe	347	#define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLL_MUL2) \|\| ((MUL) == RCC_PLL_MUL3) \|\| \
mbed_official	340:28d1f895c6fe	348	((MUL) == RCC_PLL_MUL4) \|\| ((MUL) == RCC_PLL_MUL5) \|\| \
mbed_official	340:28d1f895c6fe	349	((MUL) == RCC_PLL_MUL6) \|\| ((MUL) == RCC_PLL_MUL7) \|\| \
mbed_official	340:28d1f895c6fe	350	((MUL) == RCC_PLL_MUL8) \|\| ((MUL) == RCC_PLL_MUL9) \|\| \
mbed_official	340:28d1f895c6fe	351	((MUL) == RCC_PLL_MUL10) \|\| ((MUL) == RCC_PLL_MUL11) \|\| \
mbed_official	340:28d1f895c6fe	352	((MUL) == RCC_PLL_MUL12) \|\| ((MUL) == RCC_PLL_MUL13) \|\| \
mbed_official	340:28d1f895c6fe	353	((MUL) == RCC_PLL_MUL14) \|\| ((MUL) == RCC_PLL_MUL15) \|\| \
mbed_official	340:28d1f895c6fe	354	((MUL) == RCC_PLL_MUL16))
mbed_official	340:28d1f895c6fe	355	/**
mbed_official	340:28d1f895c6fe	356	* @}
mbed_official	340:28d1f895c6fe	357	*/
mbed_official	340:28d1f895c6fe	358
mbed_official	340:28d1f895c6fe	359	/** @defgroup RCC_PLL_Clock_Source RCC PLL Clock Source
mbed_official	340:28d1f895c6fe	360	* @{
mbed_official	340:28d1f895c6fe	361	*/
mbed_official	340:28d1f895c6fe	362	#define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE_PREDIV
mbed_official	340:28d1f895c6fe	363	/**
mbed_official	340:28d1f895c6fe	364	* @}
mbed_official	340:28d1f895c6fe	365	*/
mbed_official	340:28d1f895c6fe	366
mbed_official	340:28d1f895c6fe	367	/** @defgroup RCC_System_Clock_Type RCC System Clock Type
mbed_official	340:28d1f895c6fe	368	* @{
mbed_official	340:28d1f895c6fe	369	*/
mbed_official	340:28d1f895c6fe	370	#define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001)
mbed_official	340:28d1f895c6fe	371	#define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002)
mbed_official	340:28d1f895c6fe	372	#define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004)
mbed_official	340:28d1f895c6fe	373
mbed_official	340:28d1f895c6fe	374	#define IS_RCC_CLOCKTYPE(CLK) ((((CLK) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) \|\| \
mbed_official	340:28d1f895c6fe	375	(((CLK) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) \|\| \
mbed_official	340:28d1f895c6fe	376	(((CLK) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1))
mbed_official	340:28d1f895c6fe	377	/**
mbed_official	340:28d1f895c6fe	378	* @}
mbed_official	340:28d1f895c6fe	379	*/
mbed_official	340:28d1f895c6fe	380
mbed_official	340:28d1f895c6fe	381	/** @defgroup RCC_System_Clock_Source RCC System Clock Source
mbed_official	340:28d1f895c6fe	382	* @{
mbed_official	340:28d1f895c6fe	383	*/
mbed_official	340:28d1f895c6fe	384	#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI
mbed_official	340:28d1f895c6fe	385	#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE
mbed_official	340:28d1f895c6fe	386	#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL
mbed_official	340:28d1f895c6fe	387	/**
mbed_official	340:28d1f895c6fe	388	* @}
mbed_official	340:28d1f895c6fe	389	*/
mbed_official	340:28d1f895c6fe	390
mbed_official	340:28d1f895c6fe	391	/** @defgroup RCC_System_Clock_Source_Status RCC System Clock Source Status
mbed_official	340:28d1f895c6fe	392	* @{
mbed_official	340:28d1f895c6fe	393	*/
mbed_official	340:28d1f895c6fe	394	#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI
mbed_official	340:28d1f895c6fe	395	#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE
mbed_official	340:28d1f895c6fe	396	#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL
mbed_official	340:28d1f895c6fe	397	/**
mbed_official	340:28d1f895c6fe	398	* @}
mbed_official	340:28d1f895c6fe	399	*/
mbed_official	340:28d1f895c6fe	400
mbed_official	340:28d1f895c6fe	401	/** @defgroup RCC_AHB_Clock_Source RCC AHB Clock Source
mbed_official	340:28d1f895c6fe	402	* @{
mbed_official	340:28d1f895c6fe	403	*/
mbed_official	340:28d1f895c6fe	404	#define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1
mbed_official	340:28d1f895c6fe	405	#define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2
mbed_official	340:28d1f895c6fe	406	#define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4
mbed_official	340:28d1f895c6fe	407	#define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8
mbed_official	340:28d1f895c6fe	408	#define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16
mbed_official	340:28d1f895c6fe	409	#define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64
mbed_official	340:28d1f895c6fe	410	#define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128
mbed_official	340:28d1f895c6fe	411	#define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256
mbed_official	340:28d1f895c6fe	412	#define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512
mbed_official	340:28d1f895c6fe	413
mbed_official	340:28d1f895c6fe	414	#define IS_RCC_SYSCLK_DIV(DIV) (((DIV) == RCC_SYSCLK_DIV1) \|\| ((DIV) == RCC_SYSCLK_DIV2) \|\| \
mbed_official	340:28d1f895c6fe	415	((DIV) == RCC_SYSCLK_DIV4) \|\| ((DIV) == RCC_SYSCLK_DIV8) \|\| \
mbed_official	340:28d1f895c6fe	416	((DIV) == RCC_SYSCLK_DIV16) \|\| ((DIV) == RCC_SYSCLK_DIV64) \|\| \
mbed_official	340:28d1f895c6fe	417	((DIV) == RCC_SYSCLK_DIV128) \|\| ((DIV) == RCC_SYSCLK_DIV256) \|\| \
mbed_official	340:28d1f895c6fe	418	((DIV) == RCC_SYSCLK_DIV512))
mbed_official	340:28d1f895c6fe	419	/**
mbed_official	340:28d1f895c6fe	420	* @}
mbed_official	340:28d1f895c6fe	421	*/
mbed_official	340:28d1f895c6fe	422
mbed_official	340:28d1f895c6fe	423	/** @defgroup RCC_APB1_Clock_Source RCC APB1 Clock Source
mbed_official	340:28d1f895c6fe	424	* @{
mbed_official	340:28d1f895c6fe	425	*/
mbed_official	340:28d1f895c6fe	426	#define RCC_HCLK_DIV1 RCC_CFGR_PPRE_DIV1
mbed_official	340:28d1f895c6fe	427	#define RCC_HCLK_DIV2 RCC_CFGR_PPRE_DIV2
mbed_official	340:28d1f895c6fe	428	#define RCC_HCLK_DIV4 RCC_CFGR_PPRE_DIV4
mbed_official	340:28d1f895c6fe	429	#define RCC_HCLK_DIV8 RCC_CFGR_PPRE_DIV8
mbed_official	340:28d1f895c6fe	430	#define RCC_HCLK_DIV16 RCC_CFGR_PPRE_DIV16
mbed_official	340:28d1f895c6fe	431
mbed_official	340:28d1f895c6fe	432	#define IS_RCC_HCLK_DIV(DIV) (((DIV) == RCC_HCLK_DIV1) \|\| ((DIV) == RCC_HCLK_DIV2) \|\| \
mbed_official	340:28d1f895c6fe	433	((DIV) == RCC_HCLK_DIV4) \|\| ((DIV) == RCC_HCLK_DIV8) \|\| \
mbed_official	340:28d1f895c6fe	434	((DIV) == RCC_HCLK_DIV16))
mbed_official	340:28d1f895c6fe	435	/**
mbed_official	340:28d1f895c6fe	436	* @}
mbed_official	340:28d1f895c6fe	437	*/
mbed_official	340:28d1f895c6fe	438
mbed_official	340:28d1f895c6fe	439	/** @defgroup RCC_RTC_Clock_Source RCC RTC Clock Source
mbed_official	340:28d1f895c6fe	440	* @{
mbed_official	340:28d1f895c6fe	441	*/
mbed_official	340:28d1f895c6fe	442	#define RCC_RTCCLKSOURCE_NONE RCC_BDCR_RTCSEL_NOCLOCK
mbed_official	340:28d1f895c6fe	443	#define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_LSE
mbed_official	340:28d1f895c6fe	444	#define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_LSI
mbed_official	340:28d1f895c6fe	445	#define RCC_RTCCLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL_HSE
mbed_official	340:28d1f895c6fe	446
mbed_official	340:28d1f895c6fe	447	#define IS_RCC_RTCCLKSOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSOURCE_NONE) \|\| \
mbed_official	340:28d1f895c6fe	448	((SOURCE) == RCC_RTCCLKSOURCE_LSE) \|\| \
mbed_official	340:28d1f895c6fe	449	((SOURCE) == RCC_RTCCLKSOURCE_LSI) \|\| \
mbed_official	340:28d1f895c6fe	450	((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV32))
mbed_official	340:28d1f895c6fe	451	/**
mbed_official	340:28d1f895c6fe	452	* @}
mbed_official	340:28d1f895c6fe	453	*/
mbed_official	340:28d1f895c6fe	454
mbed_official	340:28d1f895c6fe	455	/** @defgroup RCC_USART1_Clock_Source RCC USART1 Clock Source
mbed_official	340:28d1f895c6fe	456	* @{
mbed_official	340:28d1f895c6fe	457	*/
mbed_official	340:28d1f895c6fe	458	#define RCC_USART1CLKSOURCE_PCLK1 RCC_CFGR3_USART1SW_PCLK
mbed_official	340:28d1f895c6fe	459	#define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK
mbed_official	340:28d1f895c6fe	460	#define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE
mbed_official	340:28d1f895c6fe	461	#define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI
mbed_official	340:28d1f895c6fe	462
mbed_official	340:28d1f895c6fe	463	#define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_PCLK1) \|\| \
mbed_official	340:28d1f895c6fe	464	((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) \|\| \
mbed_official	340:28d1f895c6fe	465	((SOURCE) == RCC_USART1CLKSOURCE_LSE) \|\| \
mbed_official	340:28d1f895c6fe	466	((SOURCE) == RCC_USART1CLKSOURCE_HSI))
mbed_official	340:28d1f895c6fe	467	/**
mbed_official	340:28d1f895c6fe	468	* @}
mbed_official	340:28d1f895c6fe	469	*/
mbed_official	340:28d1f895c6fe	470
mbed_official	340:28d1f895c6fe	471	/** @defgroup RCC_I2C1_Clock_Source RCC I2C1 Clock Source
mbed_official	340:28d1f895c6fe	472	* @{
mbed_official	340:28d1f895c6fe	473	*/
mbed_official	340:28d1f895c6fe	474	#define RCC_I2C1CLKSOURCE_HSI RCC_CFGR3_I2C1SW_HSI
mbed_official	340:28d1f895c6fe	475	#define RCC_I2C1CLKSOURCE_SYSCLK RCC_CFGR3_I2C1SW_SYSCLK
mbed_official	340:28d1f895c6fe	476
mbed_official	340:28d1f895c6fe	477	#define IS_RCC_I2C1CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C1CLKSOURCE_HSI) \|\| \
mbed_official	340:28d1f895c6fe	478	((SOURCE) == RCC_I2C1CLKSOURCE_SYSCLK))
mbed_official	340:28d1f895c6fe	479	/**
mbed_official	340:28d1f895c6fe	480	* @}
mbed_official	340:28d1f895c6fe	481	*/
mbed_official	340:28d1f895c6fe	482
mbed_official	340:28d1f895c6fe	483	/** @defgroup RCC_MCOx_Index RCC MCOx Index
mbed_official	340:28d1f895c6fe	484	* @{
mbed_official	340:28d1f895c6fe	485	*/
mbed_official	340:28d1f895c6fe	486	#define RCC_MCO ((uint32_t)0x00000000)
mbed_official	340:28d1f895c6fe	487
mbed_official	340:28d1f895c6fe	488	#define IS_RCC_MCO(MCOx) ((MCOx) == RCC_MCO)
mbed_official	340:28d1f895c6fe	489	/**
mbed_official	340:28d1f895c6fe	490	* @}
mbed_official	340:28d1f895c6fe	491	*/
mbed_official	340:28d1f895c6fe	492
mbed_official	340:28d1f895c6fe	493	/** @defgroup RCC_MCO_Clock_Source RCC MCO Clock Source
mbed_official	340:28d1f895c6fe	494	* @{
mbed_official	340:28d1f895c6fe	495	*/
mbed_official	340:28d1f895c6fe	496	#define RCC_MCOSOURCE_NONE RCC_CFGR_MCO_NOCLOCK
mbed_official	340:28d1f895c6fe	497	#define RCC_MCOSOURCE_LSI RCC_CFGR_MCO_LSI
mbed_official	340:28d1f895c6fe	498	#define RCC_MCOSOURCE_LSE RCC_CFGR_MCO_LSE
mbed_official	340:28d1f895c6fe	499	#define RCC_MCOSOURCE_SYSCLK RCC_CFGR_MCO_SYSCLK
mbed_official	340:28d1f895c6fe	500	#define RCC_MCOSOURCE_HSI RCC_CFGR_MCO_HSI
mbed_official	340:28d1f895c6fe	501	#define RCC_MCOSOURCE_HSE RCC_CFGR_MCO_HSE
mbed_official	340:28d1f895c6fe	502	#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_CFGR_MCO_PLL
mbed_official	340:28d1f895c6fe	503	#define RCC_MCOSOURCE_HSI14 RCC_CFGR_MCO_HSI14
mbed_official	340:28d1f895c6fe	504	/**
mbed_official	340:28d1f895c6fe	505	* @}
mbed_official	340:28d1f895c6fe	506	*/
mbed_official	340:28d1f895c6fe	507
mbed_official	340:28d1f895c6fe	508	/** @defgroup RCC_Interrupt RCC Interrupt
mbed_official	340:28d1f895c6fe	509	* @{
mbed_official	340:28d1f895c6fe	510	*/
mbed_official	340:28d1f895c6fe	511	#define RCC_IT_LSIRDY ((uint8_t)0x01)
mbed_official	340:28d1f895c6fe	512	#define RCC_IT_LSERDY ((uint8_t)0x02)
mbed_official	340:28d1f895c6fe	513	#define RCC_IT_HSIRDY ((uint8_t)0x04)
mbed_official	340:28d1f895c6fe	514	#define RCC_IT_HSERDY ((uint8_t)0x08)
mbed_official	340:28d1f895c6fe	515	#define RCC_IT_PLLRDY ((uint8_t)0x10)
mbed_official	340:28d1f895c6fe	516	#define RCC_IT_HSI14 ((uint8_t)0x20)
mbed_official	340:28d1f895c6fe	517	#define RCC_IT_CSS ((uint8_t)0x80)
mbed_official	340:28d1f895c6fe	518	/**
mbed_official	340:28d1f895c6fe	519	* @}
mbed_official	340:28d1f895c6fe	520	*/
mbed_official	340:28d1f895c6fe	521
mbed_official	340:28d1f895c6fe	522	/** @defgroup RCC_Flag RCC Flag
mbed_official	340:28d1f895c6fe	523	* Elements values convention: 0XXYYYYYb
mbed_official	340:28d1f895c6fe	524	* - YYYYY : Flag position in the register
mbed_official	340:28d1f895c6fe	525	* - XX : Register index
mbed_official	340:28d1f895c6fe	526	* - 00: CR register
mbed_official	340:28d1f895c6fe	527	* - 01: CR2 register
mbed_official	340:28d1f895c6fe	528	* - 10: BDCR register
mbed_official	340:28d1f895c6fe	529	* - 11: CSR register
mbed_official	340:28d1f895c6fe	530	* @{
mbed_official	340:28d1f895c6fe	531	*/
mbed_official	340:28d1f895c6fe	532	#define CR_REG_INDEX 0
mbed_official	340:28d1f895c6fe	533	#define CR2_REG_INDEX 1
mbed_official	340:28d1f895c6fe	534	#define BDCR_REG_INDEX 2
mbed_official	340:28d1f895c6fe	535	#define CSR_REG_INDEX 3
mbed_official	340:28d1f895c6fe	536
mbed_official	340:28d1f895c6fe	537	/* Flags in the CR register */
mbed_official	340:28d1f895c6fe	538	#define RCC_CR_HSIRDY_BitNumber 1
mbed_official	340:28d1f895c6fe	539	#define RCC_CR_HSERDY_BitNumber 17
mbed_official	340:28d1f895c6fe	540	#define RCC_CR_PLLRDY_BitNumber 25
mbed_official	340:28d1f895c6fe	541
mbed_official	340:28d1f895c6fe	542	#define RCC_FLAG_HSIRDY ((uint8_t)((CR_REG_INDEX << 5) \| RCC_CR_HSIRDY_BitNumber))
mbed_official	340:28d1f895c6fe	543	#define RCC_FLAG_HSERDY ((uint8_t)((CR_REG_INDEX << 5) \| RCC_CR_HSERDY_BitNumber))
mbed_official	340:28d1f895c6fe	544	#define RCC_FLAG_PLLRDY ((uint8_t)((CR_REG_INDEX << 5) \| RCC_CR_PLLRDY_BitNumber))
mbed_official	340:28d1f895c6fe	545
mbed_official	340:28d1f895c6fe	546	/* Flags in the CR2 register */
mbed_official	340:28d1f895c6fe	547	#define RCC_CR2_HSI14RDY_BitNumber 1
mbed_official	340:28d1f895c6fe	548
mbed_official	340:28d1f895c6fe	549	#define RCC_FLAG_HSI14RDY ((uint8_t)((CR2_REG_INDEX << 5) \| RCC_CR2_HSI14RDY_BitNumber))
mbed_official	340:28d1f895c6fe	550
mbed_official	340:28d1f895c6fe	551	/* Flags in the BDCR register */
mbed_official	340:28d1f895c6fe	552	#define RCC_BDCR_LSERDY_BitNumber 1
mbed_official	340:28d1f895c6fe	553
mbed_official	340:28d1f895c6fe	554	#define RCC_FLAG_LSERDY ((uint8_t)((BDCR_REG_INDEX << 5) \| RCC_BDCR_LSERDY_BitNumber))
mbed_official	340:28d1f895c6fe	555
mbed_official	340:28d1f895c6fe	556	/* Flags in the CSR register */
mbed_official	340:28d1f895c6fe	557	#define RCC_CSR_LSIRDY_BitNumber 1
mbed_official	340:28d1f895c6fe	558	#define RCC_CSR_V18PWRRSTF_BitNumber 23
mbed_official	340:28d1f895c6fe	559	#define RCC_CSR_RMVF_BitNumber 24
mbed_official	340:28d1f895c6fe	560	#define RCC_CSR_OBLRSTF_BitNumber 25
mbed_official	340:28d1f895c6fe	561	#define RCC_CSR_PINRSTF_BitNumber 26
mbed_official	340:28d1f895c6fe	562	#define RCC_CSR_PORRSTF_BitNumber 27
mbed_official	340:28d1f895c6fe	563	#define RCC_CSR_SFTRSTF_BitNumber 28
mbed_official	340:28d1f895c6fe	564	#define RCC_CSR_IWDGRSTF_BitNumber 29
mbed_official	340:28d1f895c6fe	565	#define RCC_CSR_WWDGRSTF_BitNumber 30
mbed_official	340:28d1f895c6fe	566	#define RCC_CSR_LPWRRSTF_BitNumber 31
mbed_official	340:28d1f895c6fe	567
mbed_official	340:28d1f895c6fe	568	#define RCC_FLAG_LSIRDY ((uint8_t)((CSR_REG_INDEX << 5) \| RCC_CSR_LSIRDY_BitNumber))
mbed_official	340:28d1f895c6fe	569	#define RCC_FLAG_V18PWRRST ((uint8_t)((CSR_REG_INDEX << 5) \| RCC_CSR_LSIRDY_BitNumber))
mbed_official	340:28d1f895c6fe	570	#define RCC_FLAG_RMV ((uint8_t)((CSR_REG_INDEX << 5) \| RCC_CSR_RMVF_BitNumber))
mbed_official	340:28d1f895c6fe	571	#define RCC_FLAG_OBLRST ((uint8_t)((CSR_REG_INDEX << 5) \| RCC_CSR_OBLRSTF_BitNumber))
mbed_official	340:28d1f895c6fe	572	#define RCC_FLAG_PINRST ((uint8_t)((CSR_REG_INDEX << 5) \| RCC_CSR_PINRSTF_BitNumber))
mbed_official	340:28d1f895c6fe	573	#define RCC_FLAG_PORRST ((uint8_t)((CSR_REG_INDEX << 5) \| RCC_CSR_PORRSTF_BitNumber))
mbed_official	340:28d1f895c6fe	574	#define RCC_FLAG_SFTRST ((uint8_t)((CSR_REG_INDEX << 5) \| RCC_CSR_SFTRSTF_BitNumber))
mbed_official	340:28d1f895c6fe	575	#define RCC_FLAG_IWDGRST ((uint8_t)((CSR_REG_INDEX << 5) \| RCC_CSR_IWDGRSTF_BitNumber))
mbed_official	340:28d1f895c6fe	576	#define RCC_FLAG_WWDGRST ((uint8_t)((CSR_REG_INDEX << 5) \| RCC_CSR_WWDGRSTF_BitNumber))
mbed_official	340:28d1f895c6fe	577	#define RCC_FLAG_LPWRRST ((uint8_t)((CSR_REG_INDEX << 5) \| RCC_CSR_LPWRRSTF_BitNumber))
mbed_official	340:28d1f895c6fe	578	/**
mbed_official	340:28d1f895c6fe	579	* @}
mbed_official	340:28d1f895c6fe	580	*/
mbed_official	340:28d1f895c6fe	581
mbed_official	340:28d1f895c6fe	582	/** @defgroup RCC_Calibration_values RCC Calibration values
mbed_official	340:28d1f895c6fe	583	* @{
mbed_official	340:28d1f895c6fe	584	*/
mbed_official	340:28d1f895c6fe	585	#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
mbed_official	340:28d1f895c6fe	586
mbed_official	340:28d1f895c6fe	587	/**
mbed_official	340:28d1f895c6fe	588	* @}
mbed_official	340:28d1f895c6fe	589	*/
mbed_official	340:28d1f895c6fe	590
mbed_official	340:28d1f895c6fe	591	/** @addtogroup RCC_Timeout
mbed_official	340:28d1f895c6fe	592	* @{
mbed_official	340:28d1f895c6fe	593	*/
mbed_official	340:28d1f895c6fe	594
mbed_official	340:28d1f895c6fe	595	#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
mbed_official	340:28d1f895c6fe	596	#define HSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
mbed_official	340:28d1f895c6fe	597	#define LSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
mbed_official	340:28d1f895c6fe	598	#define LSE_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */
mbed_official	340:28d1f895c6fe	599	#define HSI14_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
mbed_official	340:28d1f895c6fe	600	#define HSI48_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
mbed_official	340:28d1f895c6fe	601	#define PLL_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
mbed_official	340:28d1f895c6fe	602	#define CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */
mbed_official	340:28d1f895c6fe	603
mbed_official	340:28d1f895c6fe	604	/**
mbed_official	340:28d1f895c6fe	605	* @}
mbed_official	340:28d1f895c6fe	606	*/
mbed_official	340:28d1f895c6fe	607
mbed_official	340:28d1f895c6fe	608	/**
mbed_official	340:28d1f895c6fe	609	* @}
mbed_official	340:28d1f895c6fe	610	*/
mbed_official	340:28d1f895c6fe	611
mbed_official	340:28d1f895c6fe	612	/* Exported macro ------------------------------------------------------------*/
mbed_official	340:28d1f895c6fe	613
mbed_official	340:28d1f895c6fe	614	/** @defgroup RCC_Exported_Macros RCC Exported Macros
mbed_official	340:28d1f895c6fe	615	* @{
mbed_official	340:28d1f895c6fe	616	*/
mbed_official	340:28d1f895c6fe	617
mbed_official	340:28d1f895c6fe	618	/** @defgroup RCC_AHB_Clock_Enable_Disable RCC AHB Clock Enable Disable
mbed_official	340:28d1f895c6fe	619	* @brief Enable or disable the AHB peripheral clock.
mbed_official	340:28d1f895c6fe	620	* @note After reset, the peripheral clock (used for registers read/write access)
mbed_official	340:28d1f895c6fe	621	* is disabled and the application software has to enable this clock before
mbed_official	340:28d1f895c6fe	622	* using it.
mbed_official	340:28d1f895c6fe	623	* @{
mbed_official	340:28d1f895c6fe	624	*/
mbed_official	340:28d1f895c6fe	625	#define __GPIOA_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_GPIOAEN))
mbed_official	340:28d1f895c6fe	626	#define __GPIOB_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_GPIOBEN))
mbed_official	340:28d1f895c6fe	627	#define __GPIOC_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_GPIOCEN))
mbed_official	340:28d1f895c6fe	628	#define __GPIOF_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_GPIOFEN))
mbed_official	340:28d1f895c6fe	629	#define __CRC_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_CRCEN))
mbed_official	340:28d1f895c6fe	630	#define __DMA1_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_DMA1EN))
mbed_official	340:28d1f895c6fe	631	#define __SRAM_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_SRAMEN))
mbed_official	340:28d1f895c6fe	632	#define __FLITF_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_FLITFEN))
mbed_official	340:28d1f895c6fe	633
mbed_official	340:28d1f895c6fe	634	#define __GPIOA_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOAEN))
mbed_official	340:28d1f895c6fe	635	#define __GPIOB_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOBEN))
mbed_official	340:28d1f895c6fe	636	#define __GPIOC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOCEN))
mbed_official	340:28d1f895c6fe	637	#define __GPIOF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOFEN))
mbed_official	340:28d1f895c6fe	638	#define __CRC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_CRCEN))
mbed_official	340:28d1f895c6fe	639	#define __DMA1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN))
mbed_official	340:28d1f895c6fe	640	#define __SRAM_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SRAMEN))
mbed_official	340:28d1f895c6fe	641	#define __FLITF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FLITFEN))
mbed_official	340:28d1f895c6fe	642	/**
mbed_official	340:28d1f895c6fe	643	* @}
mbed_official	340:28d1f895c6fe	644	*/
mbed_official	340:28d1f895c6fe	645
mbed_official	340:28d1f895c6fe	646	/** @defgroup RCC_APB1_Clock_Enable_Disable RCC APB1 Clock Enable Disable
mbed_official	340:28d1f895c6fe	647	* @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
mbed_official	340:28d1f895c6fe	648	* @note After reset, the peripheral clock (used for registers read/write access)
mbed_official	340:28d1f895c6fe	649	* is disabled and the application software has to enable this clock before
mbed_official	340:28d1f895c6fe	650	* using it.
mbed_official	340:28d1f895c6fe	651	* @{
mbed_official	340:28d1f895c6fe	652	*/
mbed_official	340:28d1f895c6fe	653	#define __TIM3_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM3EN))
mbed_official	340:28d1f895c6fe	654	#define __TIM14_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM14EN))
mbed_official	340:28d1f895c6fe	655	#define __WWDG_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_WWDGEN))
mbed_official	340:28d1f895c6fe	656	#define __I2C1_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_I2C1EN))
mbed_official	340:28d1f895c6fe	657	#define __PWR_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_PWREN))
mbed_official	340:28d1f895c6fe	658
mbed_official	340:28d1f895c6fe	659	#define __TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
mbed_official	340:28d1f895c6fe	660	#define __TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
mbed_official	340:28d1f895c6fe	661	#define __WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
mbed_official	340:28d1f895c6fe	662	#define __I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
mbed_official	340:28d1f895c6fe	663	#define __PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
mbed_official	340:28d1f895c6fe	664	/**
mbed_official	340:28d1f895c6fe	665	* @}
mbed_official	340:28d1f895c6fe	666	*/
mbed_official	340:28d1f895c6fe	667
mbed_official	340:28d1f895c6fe	668	/** @defgroup RCC_APB2_Clock_Enable_Disable RCC APB2 Clock Enable Disable
mbed_official	340:28d1f895c6fe	669	* @brief Enable or disable the High Speed APB (APB2) peripheral clock.
mbed_official	340:28d1f895c6fe	670	* @note After reset, the peripheral clock (used for registers read/write access)
mbed_official	340:28d1f895c6fe	671	* is disabled and the application software has to enable this clock before
mbed_official	340:28d1f895c6fe	672	* using it.
mbed_official	340:28d1f895c6fe	673	* @{
mbed_official	340:28d1f895c6fe	674	*/
mbed_official	340:28d1f895c6fe	675	#define __SYSCFG_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_SYSCFGEN))
mbed_official	340:28d1f895c6fe	676	#define __ADC1_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_ADC1EN))
mbed_official	340:28d1f895c6fe	677	#define __TIM1_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_TIM1EN))
mbed_official	340:28d1f895c6fe	678	#define __SPI1_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_SPI1EN))
mbed_official	340:28d1f895c6fe	679	#define __TIM16_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_TIM16EN))
mbed_official	340:28d1f895c6fe	680	#define __TIM17_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_TIM17EN))
mbed_official	340:28d1f895c6fe	681	#define __USART1_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_USART1EN))
mbed_official	340:28d1f895c6fe	682	#define __DBGMCU_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_DBGMCUEN))
mbed_official	340:28d1f895c6fe	683
mbed_official	340:28d1f895c6fe	684	#define __SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
mbed_official	340:28d1f895c6fe	685	#define __ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
mbed_official	340:28d1f895c6fe	686	#define __TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
mbed_official	340:28d1f895c6fe	687	#define __SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
mbed_official	340:28d1f895c6fe	688	#define __TIM16_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM16EN))
mbed_official	340:28d1f895c6fe	689	#define __TIM17_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM17EN))
mbed_official	340:28d1f895c6fe	690	#define __USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
mbed_official	340:28d1f895c6fe	691	#define __DBGMCU_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DBGMCUEN))
mbed_official	340:28d1f895c6fe	692	/**
mbed_official	340:28d1f895c6fe	693	* @}
mbed_official	340:28d1f895c6fe	694	*/
mbed_official	340:28d1f895c6fe	695
mbed_official	340:28d1f895c6fe	696	/** @defgroup RCC_AHB_Force_Release_Reset RCC AHB Force Release Reset
mbed_official	340:28d1f895c6fe	697	* @brief Force or release AHB peripheral reset.
mbed_official	340:28d1f895c6fe	698	* @{
mbed_official	340:28d1f895c6fe	699	*/
mbed_official	340:28d1f895c6fe	700	#define __AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFF)
mbed_official	340:28d1f895c6fe	701	#define __GPIOA_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIOARST))
mbed_official	340:28d1f895c6fe	702	#define __GPIOB_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIOBRST))
mbed_official	340:28d1f895c6fe	703	#define __GPIOC_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIOCRST))
mbed_official	340:28d1f895c6fe	704	#define __GPIOF_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIOFRST))
mbed_official	340:28d1f895c6fe	705
mbed_official	340:28d1f895c6fe	706	#define __AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00)
mbed_official	340:28d1f895c6fe	707	#define __GPIOA_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOARST))
mbed_official	340:28d1f895c6fe	708	#define __GPIOB_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOBRST))
mbed_official	340:28d1f895c6fe	709	#define __GPIOC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOCRST))
mbed_official	340:28d1f895c6fe	710	#define __GPIOF_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOFRST))
mbed_official	340:28d1f895c6fe	711	/**
mbed_official	340:28d1f895c6fe	712	* @}
mbed_official	340:28d1f895c6fe	713	*/
mbed_official	340:28d1f895c6fe	714
mbed_official	340:28d1f895c6fe	715	/** @defgroup RCC_APB1_Force_Release_Reset RCC APB1 Force Release Reset
mbed_official	340:28d1f895c6fe	716	* @brief Force or release APB1 peripheral reset.
mbed_official	340:28d1f895c6fe	717	* @{
mbed_official	340:28d1f895c6fe	718	*/
mbed_official	340:28d1f895c6fe	719	#define __APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFF)
mbed_official	340:28d1f895c6fe	720	#define __TIM3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM3RST))
mbed_official	340:28d1f895c6fe	721	#define __TIM14_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM14RST))
mbed_official	340:28d1f895c6fe	722	#define __WWDG_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_WWDGRST))
mbed_official	340:28d1f895c6fe	723	#define __I2C1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C1RST))
mbed_official	340:28d1f895c6fe	724	#define __PWR_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_PWRRST))
mbed_official	340:28d1f895c6fe	725
mbed_official	340:28d1f895c6fe	726	#define __APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00)
mbed_official	340:28d1f895c6fe	727	#define __TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
mbed_official	340:28d1f895c6fe	728	#define __TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
mbed_official	340:28d1f895c6fe	729	#define __WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
mbed_official	340:28d1f895c6fe	730	#define __I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
mbed_official	340:28d1f895c6fe	731	#define __PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
mbed_official	340:28d1f895c6fe	732	/**
mbed_official	340:28d1f895c6fe	733	* @}
mbed_official	340:28d1f895c6fe	734	*/
mbed_official	340:28d1f895c6fe	735
mbed_official	340:28d1f895c6fe	736	/** @defgroup RCC_APB2_Force_Release_Reset RCC APB2 Force Release Reset
mbed_official	340:28d1f895c6fe	737	* @brief Force or release APB2 peripheral reset.
mbed_official	340:28d1f895c6fe	738	* @{
mbed_official	340:28d1f895c6fe	739	*/
mbed_official	340:28d1f895c6fe	740	#define __APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFF)
mbed_official	340:28d1f895c6fe	741	#define __SYSCFG_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SYSCFGRST))
mbed_official	340:28d1f895c6fe	742	#define __ADC1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_ADC1RST))
mbed_official	340:28d1f895c6fe	743	#define __TIM1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM1RST))
mbed_official	340:28d1f895c6fe	744	#define __SPI1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI1RST))
mbed_official	340:28d1f895c6fe	745	#define __USART1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_USART1RST))
mbed_official	340:28d1f895c6fe	746	#define __TIM16_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM16RST))
mbed_official	340:28d1f895c6fe	747	#define __TIM17_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM17RST))
mbed_official	340:28d1f895c6fe	748	#define __DBGMCU_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_DBGMCURST))
mbed_official	340:28d1f895c6fe	749
mbed_official	340:28d1f895c6fe	750	#define __APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00)
mbed_official	340:28d1f895c6fe	751	#define __SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))
mbed_official	340:28d1f895c6fe	752	#define __ADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC1RST))
mbed_official	340:28d1f895c6fe	753	#define __TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
mbed_official	340:28d1f895c6fe	754	#define __SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
mbed_official	340:28d1f895c6fe	755	#define __USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
mbed_official	340:28d1f895c6fe	756	#define __TIM16_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM16RST))
mbed_official	340:28d1f895c6fe	757	#define __TIM17_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM17RST))
mbed_official	340:28d1f895c6fe	758	#define __DBGMCU_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DBGMCURST))
mbed_official	340:28d1f895c6fe	759	/**
mbed_official	340:28d1f895c6fe	760	* @}
mbed_official	340:28d1f895c6fe	761	*/
mbed_official	340:28d1f895c6fe	762
mbed_official	340:28d1f895c6fe	763	/** @defgroup RCC_HSI_Configuration RCC HSI Configuration
mbed_official	340:28d1f895c6fe	764	* @{
mbed_official	340:28d1f895c6fe	765	*/
mbed_official	340:28d1f895c6fe	766
mbed_official	340:28d1f895c6fe	767	/** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
mbed_official	340:28d1f895c6fe	768	* @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
mbed_official	340:28d1f895c6fe	769	* It is used (enabled by hardware) as system clock source after startup
mbed_official	340:28d1f895c6fe	770	* from Reset, wakeup from STOP and STANDBY mode, or in case of failure
mbed_official	340:28d1f895c6fe	771	* of the HSE used directly or indirectly as system clock (if the Clock
mbed_official	340:28d1f895c6fe	772	* Security System CSS is enabled).
mbed_official	340:28d1f895c6fe	773	* @note HSI can not be stopped if it is used as system clock source. In this case,
mbed_official	340:28d1f895c6fe	774	* you have to select another source of the system clock then stop the HSI.
mbed_official	340:28d1f895c6fe	775	* @note After enabling the HSI, the application software should wait on HSIRDY
mbed_official	340:28d1f895c6fe	776	* flag to be set indicating that HSI clock is stable and can be used as
mbed_official	340:28d1f895c6fe	777	* system clock source.
mbed_official	340:28d1f895c6fe	778	* @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
mbed_official	340:28d1f895c6fe	779	* clock cycles.
mbed_official	340:28d1f895c6fe	780	*/
mbed_official	340:28d1f895c6fe	781	#define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION)
mbed_official	340:28d1f895c6fe	782	#define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION)
mbed_official	340:28d1f895c6fe	783
mbed_official	340:28d1f895c6fe	784	/** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
mbed_official	340:28d1f895c6fe	785	* @note The calibration is used to compensate for the variations in voltage
mbed_official	340:28d1f895c6fe	786	* and temperature that influence the frequency of the internal HSI RC.
mbed_official	340:28d1f895c6fe	787	* @param __HSICalibrationValue__: specifies the calibration trimming value
mbed_official	340:28d1f895c6fe	788	* (default is RCC_HSICALIBRATION_DEFAULT).
mbed_official	340:28d1f895c6fe	789	* This parameter must be a number between 0 and 0x1F.
mbed_official	340:28d1f895c6fe	790	*/
mbed_official	340:28d1f895c6fe	791	#define RCC_CR_HSITRIM_BitNumber 3
mbed_official	340:28d1f895c6fe	792	#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) \
mbed_official	340:28d1f895c6fe	793	MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << RCC_CR_HSITRIM_BitNumber)
mbed_official	340:28d1f895c6fe	794	/**
mbed_official	340:28d1f895c6fe	795	* @}
mbed_official	340:28d1f895c6fe	796	*/
mbed_official	340:28d1f895c6fe	797
mbed_official	340:28d1f895c6fe	798	/** @defgroup RCC_LSI_Configuration RCC LSI Configuration
mbed_official	340:28d1f895c6fe	799	* @{
mbed_official	340:28d1f895c6fe	800	*/
mbed_official	340:28d1f895c6fe	801
mbed_official	340:28d1f895c6fe	802	/** @brief Macro to enable or disable the Internal Low Speed oscillator (LSI).
mbed_official	340:28d1f895c6fe	803	* @note After enabling the LSI, the application software should wait on
mbed_official	340:28d1f895c6fe	804	* LSIRDY flag to be set indicating that LSI clock is stable and can
mbed_official	340:28d1f895c6fe	805	* be used to clock the IWDG and/or the RTC.
mbed_official	340:28d1f895c6fe	806	* @note LSI can not be disabled if the IWDG is running.
mbed_official	340:28d1f895c6fe	807	* @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
mbed_official	340:28d1f895c6fe	808	* clock cycles.
mbed_official	340:28d1f895c6fe	809	*/
mbed_official	340:28d1f895c6fe	810	#define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION)
mbed_official	340:28d1f895c6fe	811	#define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_LSION)
mbed_official	340:28d1f895c6fe	812	/**
mbed_official	340:28d1f895c6fe	813	* @}
mbed_official	340:28d1f895c6fe	814	*/
mbed_official	340:28d1f895c6fe	815
mbed_official	340:28d1f895c6fe	816	/** @defgroup RCC_HSE_Configuration RCC HSE Configuration
mbed_official	340:28d1f895c6fe	817	* @{
mbed_official	340:28d1f895c6fe	818	*/
mbed_official	340:28d1f895c6fe	819
mbed_official	340:28d1f895c6fe	820	/**
mbed_official	340:28d1f895c6fe	821	* @brief Macro to configure the External High Speed oscillator (HSE).
mbed_official	340:28d1f895c6fe	822	* @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
mbed_official	340:28d1f895c6fe	823	* software should wait on HSERDY flag to be set indicating that HSE clock
mbed_official	340:28d1f895c6fe	824	* is stable and can be used to clock the PLL and/or system clock.
mbed_official	340:28d1f895c6fe	825	* @note HSE state can not be changed if it is used directly or through the
mbed_official	340:28d1f895c6fe	826	* PLL as system clock. In this case, you have to select another source
mbed_official	340:28d1f895c6fe	827	* of the system clock then change the HSE state (ex. disable it).
mbed_official	340:28d1f895c6fe	828	* @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
mbed_official	340:28d1f895c6fe	829	* @note This function reset the CSSON bit, so if the Clock security system(CSS)
mbed_official	340:28d1f895c6fe	830	* was previously enabled you have to enable it again after calling this
mbed_official	340:28d1f895c6fe	831	* function.
mbed_official	340:28d1f895c6fe	832	* @param __STATE__: specifies the new state of the HSE.
mbed_official	340:28d1f895c6fe	833	* This parameter can be one of the following values:
mbed_official	340:28d1f895c6fe	834	* @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
mbed_official	340:28d1f895c6fe	835	* 6 HSE oscillator clock cycles.
mbed_official	340:28d1f895c6fe	836	* @arg RCC_HSE_ON: turn ON the HSE oscillator
mbed_official	340:28d1f895c6fe	837	* @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock
mbed_official	340:28d1f895c6fe	838	*/
mbed_official	340:28d1f895c6fe	839	#define __HAL_RCC_HSE_CONFIG(__STATE__) ((__IO uint8_t )RCC_CR_BYTE2_ADDRESS = (__STATE__))
mbed_official	340:28d1f895c6fe	840
mbed_official	340:28d1f895c6fe	841	/**
mbed_official	340:28d1f895c6fe	842	* @brief Macro to configure the External High Speed oscillator (HSE) Predivision factor for PLL.
mbed_official	340:28d1f895c6fe	843	* @note Predivision factor can not be changed if PLL is used as system clock
mbed_official	340:28d1f895c6fe	844	* In this case, you have to select another source of the system clock, disable the PLL and
mbed_official	340:28d1f895c6fe	845	* then change the HSE predivision factor.
mbed_official	340:28d1f895c6fe	846	* @param __HSEPredivValue__: specifies the division value applied to HSE.
mbed_official	340:28d1f895c6fe	847	* This parameter must be a number between RCC_HSE_PREDIV_DIV1 and RCC_HSE_PREDIV_DIV16.
mbed_official	340:28d1f895c6fe	848	*/
mbed_official	340:28d1f895c6fe	849	#define __HAL_RCC_HSE_PREDIV_CONFIG(__HSEPredivValue__) \
mbed_official	340:28d1f895c6fe	850	MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (uint32_t)(__HSEPredivValue__))
mbed_official	340:28d1f895c6fe	851	/**
mbed_official	340:28d1f895c6fe	852	* @}
mbed_official	340:28d1f895c6fe	853	*/
mbed_official	340:28d1f895c6fe	854
mbed_official	340:28d1f895c6fe	855	/** @defgroup RCC_LSE_Configuration RCC LSE Configuration
mbed_official	340:28d1f895c6fe	856	* @{
mbed_official	340:28d1f895c6fe	857	*/
mbed_official	340:28d1f895c6fe	858	/**
mbed_official	340:28d1f895c6fe	859	* @brief Macro to configure the External Low Speed oscillator (LSE).
mbed_official	340:28d1f895c6fe	860	* @note As the LSE is in the Backup domain and write access is denied to
mbed_official	340:28d1f895c6fe	861	* this domain after reset, you have to enable write access using
mbed_official	340:28d1f895c6fe	862	* HAL_PWR_EnableBkUpAccess() function before to configure the LSE
mbed_official	340:28d1f895c6fe	863	* (to be done once after reset).
mbed_official	340:28d1f895c6fe	864	* @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
mbed_official	340:28d1f895c6fe	865	* software should wait on LSERDY flag to be set indicating that LSE clock
mbed_official	340:28d1f895c6fe	866	* is stable and can be used to clock the RTC.
mbed_official	340:28d1f895c6fe	867	* @param __STATE__: specifies the new state of the LSE.
mbed_official	340:28d1f895c6fe	868	* This parameter can be one of the following values:
mbed_official	340:28d1f895c6fe	869	* @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
mbed_official	340:28d1f895c6fe	870	* 6 LSE oscillator clock cycles.
mbed_official	340:28d1f895c6fe	871	* @arg RCC_LSE_ON: turn ON the LSE oscillator
mbed_official	340:28d1f895c6fe	872	* @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock
mbed_official	340:28d1f895c6fe	873	*/
mbed_official	340:28d1f895c6fe	874	#define __HAL_RCC_LSE_CONFIG(__STATE__) \
mbed_official	340:28d1f895c6fe	875	MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEON\|RCC_BDCR_LSEBYP, (uint32_t)(__STATE__))
mbed_official	340:28d1f895c6fe	876	/**
mbed_official	340:28d1f895c6fe	877	* @}
mbed_official	340:28d1f895c6fe	878	*/
mbed_official	340:28d1f895c6fe	879
mbed_official	340:28d1f895c6fe	880	/** @defgroup RCC_HSI14_Configuration RCC_HSI14_Configuration
mbed_official	340:28d1f895c6fe	881	* @{
mbed_official	340:28d1f895c6fe	882	*/
mbed_official	340:28d1f895c6fe	883
mbed_official	340:28d1f895c6fe	884	/** @brief Macros to enable or disable the Internal 14Mhz High Speed oscillator (HSI14).
mbed_official	340:28d1f895c6fe	885	* @note The HSI14 is stopped by hardware when entering STOP and STANDBY modes.
mbed_official	340:28d1f895c6fe	886	* @note HSI14 can not be stopped if it is used as system clock source. In this case,
mbed_official	340:28d1f895c6fe	887	* you have to select another source of the system clock then stop the HSI14.
mbed_official	340:28d1f895c6fe	888	* @note After enabling the HSI14 with __HAL_RCC_HSI14_ENABLE(), the application software
mbed_official	340:28d1f895c6fe	889	* should wait on HSI14RDY flag to be set indicating that HSI clock is stable and can be
mbed_official	340:28d1f895c6fe	890	* used as system clock source. This is not necessary if HAL_RCC_OscConfig() is used.
mbed_official	340:28d1f895c6fe	891	* @note When the HSI14 is stopped, HSI14RDY flag goes low after 6 HSI14 oscillator
mbed_official	340:28d1f895c6fe	892	* clock cycles.
mbed_official	340:28d1f895c6fe	893	*/
mbed_official	340:28d1f895c6fe	894	#define __HAL_RCC_HSI14_ENABLE() SET_BIT(RCC->CR2, RCC_CR2_HSI14ON)
mbed_official	340:28d1f895c6fe	895	#define __HAL_RCC_HSI14_DISABLE() CLEAR_BIT(RCC->CR2, RCC_CR2_HSI14ON)
mbed_official	340:28d1f895c6fe	896
mbed_official	340:28d1f895c6fe	897	/** @brief macros to Enable or Disable the Internal 14Mhz High Speed oscillator (HSI14) usage by ADC.
mbed_official	340:28d1f895c6fe	898	*/
mbed_official	340:28d1f895c6fe	899	#define __HAL_RCC_HSI14ADC_ENABLE() CLEAR_BIT(RCC->CR2, RCC_CR2_HSI14DIS)
mbed_official	340:28d1f895c6fe	900	#define __HAL_RCC_HSI14ADC_DISABLE() SET_BIT(RCC->CR2, RCC_CR2_HSI14DIS)
mbed_official	340:28d1f895c6fe	901
mbed_official	340:28d1f895c6fe	902	/** @brief Macro to adjust the Internal 14Mhz High Speed oscillator (HSI) calibration value.
mbed_official	340:28d1f895c6fe	903	* @note The calibration is used to compensate for the variations in voltage
mbed_official	340:28d1f895c6fe	904	* and temperature that influence the frequency of the internal HSI14 RC.
mbed_official	340:28d1f895c6fe	905	* @param __HSI14CalibrationValue__: specifies the calibration trimming value
mbed_official	340:28d1f895c6fe	906	* (default is RCC_HSI14CALIBRATION_DEFAULT).
mbed_official	340:28d1f895c6fe	907	* This parameter must be a number between 0 and 0x1F.
mbed_official	340:28d1f895c6fe	908	*/
mbed_official	340:28d1f895c6fe	909	#define RCC_CR2_HSI14TRIM_BitNumber 3
mbed_official	340:28d1f895c6fe	910	#define __HAL_RCC_HSI14_CALIBRATIONVALUE_ADJUST(__HSI14CalibrationValue__) \
mbed_official	340:28d1f895c6fe	911	MODIFY_REG(RCC->CR2, RCC_CR2_HSI14TRIM, (uint32_t)(__HSI14CalibrationValue__) << RCC_CR2_HSI14TRIM_BitNumber)
mbed_official	340:28d1f895c6fe	912	/**
mbed_official	340:28d1f895c6fe	913	* @}
mbed_official	340:28d1f895c6fe	914	*/
mbed_official	340:28d1f895c6fe	915
mbed_official	340:28d1f895c6fe	916	/** @defgroup RCC_USARTx_Clock_Config RCC USARTx Clock Config
mbed_official	340:28d1f895c6fe	917	* @{
mbed_official	340:28d1f895c6fe	918	*/
mbed_official	340:28d1f895c6fe	919
mbed_official	340:28d1f895c6fe	920	/** @brief Macro to configure the USART1 clock (USART1CLK).
mbed_official	340:28d1f895c6fe	921	* @param __USART1CLKSource__: specifies the USART1 clock source.
mbed_official	340:28d1f895c6fe	922	* This parameter can be one of the following values:
mbed_official	340:28d1f895c6fe	923	* @arg RCC_USART1CLKSOURCE_PCLK1: PCLK1 selected as USART1 clock
mbed_official	340:28d1f895c6fe	924	* @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
mbed_official	340:28d1f895c6fe	925	* @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock
mbed_official	340:28d1f895c6fe	926	* @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock
mbed_official	340:28d1f895c6fe	927	*/
mbed_official	340:28d1f895c6fe	928	#define __HAL_RCC_USART1_CONFIG(__USART1CLKSource__) \
mbed_official	340:28d1f895c6fe	929	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART1SW, (uint32_t)(__USART1CLKSource__))
mbed_official	340:28d1f895c6fe	930
mbed_official	340:28d1f895c6fe	931	/** @brief Macro to get the USART1 clock source.
mbed_official	340:28d1f895c6fe	932	* @retval The clock source can be one of the following values:
mbed_official	340:28d1f895c6fe	933	* @arg RCC_USART1CLKSOURCE_PCLK1: PCLK1 selected as USART1 clock
mbed_official	340:28d1f895c6fe	934	* @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
mbed_official	340:28d1f895c6fe	935	* @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock
mbed_official	340:28d1f895c6fe	936	* @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock
mbed_official	340:28d1f895c6fe	937	*/
mbed_official	340:28d1f895c6fe	938	#define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART1SW)))
mbed_official	340:28d1f895c6fe	939	/**
mbed_official	340:28d1f895c6fe	940	* @}
mbed_official	340:28d1f895c6fe	941	*/
mbed_official	340:28d1f895c6fe	942
mbed_official	340:28d1f895c6fe	943	/** @defgroup RCC_I2Cx_Clock_Config RCC I2Cx Clock Config
mbed_official	340:28d1f895c6fe	944	* @{
mbed_official	340:28d1f895c6fe	945	*/
mbed_official	340:28d1f895c6fe	946
mbed_official	340:28d1f895c6fe	947	/** @brief Macro to configure the I2C1 clock (I2C1CLK).
mbed_official	340:28d1f895c6fe	948	* @param __I2C1CLKSource__: specifies the I2C1 clock source.
mbed_official	340:28d1f895c6fe	949	* This parameter can be one of the following values:
mbed_official	340:28d1f895c6fe	950	* @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
mbed_official	340:28d1f895c6fe	951	* @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock
mbed_official	340:28d1f895c6fe	952	*/
mbed_official	340:28d1f895c6fe	953	#define __HAL_RCC_I2C1_CONFIG(__I2C1CLKSource__) \
mbed_official	340:28d1f895c6fe	954	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C1SW, (uint32_t)(__I2C1CLKSource__))
mbed_official	340:28d1f895c6fe	955
mbed_official	340:28d1f895c6fe	956	/** @brief Macro to get the I2C1 clock source.
mbed_official	340:28d1f895c6fe	957	* @retval The clock source can be one of the following values:
mbed_official	340:28d1f895c6fe	958	* @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
mbed_official	340:28d1f895c6fe	959	* @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock
mbed_official	340:28d1f895c6fe	960	*/
mbed_official	340:28d1f895c6fe	961	#define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C1SW)))
mbed_official	340:28d1f895c6fe	962	/**
mbed_official	340:28d1f895c6fe	963	* @}
mbed_official	340:28d1f895c6fe	964	*/
mbed_official	340:28d1f895c6fe	965
mbed_official	340:28d1f895c6fe	966	/** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration
mbed_official	340:28d1f895c6fe	967	* @{
mbed_official	340:28d1f895c6fe	968	*/
mbed_official	340:28d1f895c6fe	969	/** @brief Macros to enable or disable the the RTC clock.
mbed_official	340:28d1f895c6fe	970	* @note These macros must be used only after the RTC clock source was selected.
mbed_official	340:28d1f895c6fe	971	*/
mbed_official	340:28d1f895c6fe	972	#define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
mbed_official	340:28d1f895c6fe	973	#define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
mbed_official	340:28d1f895c6fe	974
mbed_official	340:28d1f895c6fe	975	/** @brief Macro to configure the RTC clock (RTCCLK).
mbed_official	340:28d1f895c6fe	976	* @note As the RTC clock configuration bits are in the Backup domain and write
mbed_official	340:28d1f895c6fe	977	* access is denied to this domain after reset, you have to enable write
mbed_official	340:28d1f895c6fe	978	* access using the Power Backup Access macro before to configure
mbed_official	340:28d1f895c6fe	979	* the RTC clock source (to be done once after reset).
mbed_official	340:28d1f895c6fe	980	* @note Once the RTC clock is configured it can't be changed unless the
mbed_official	340:28d1f895c6fe	981	* Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by
mbed_official	340:28d1f895c6fe	982	* a Power On Reset (POR).
mbed_official	340:28d1f895c6fe	983	* @param __RTCCLKSource__: specifies the RTC clock source.
mbed_official	340:28d1f895c6fe	984	* This parameter can be one of the following values:
mbed_official	340:28d1f895c6fe	985	* @arg RCC_RTCCLKSOURCE_NONE: No clock selected as RTC clock
mbed_official	340:28d1f895c6fe	986	* @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock
mbed_official	340:28d1f895c6fe	987	* @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock
mbed_official	340:28d1f895c6fe	988	* @arg RCC_RTCCLKSOURCE_HSE_DIV32: HSE clock divided by 32
mbed_official	340:28d1f895c6fe	989	*
mbed_official	340:28d1f895c6fe	990	* @note If the LSE is used as RTC clock source, the RTC continues to
mbed_official	340:28d1f895c6fe	991	* work in STOP and STANDBY modes, and can be used as wakeup source.
mbed_official	340:28d1f895c6fe	992	* However, when the LSI clock and HSE clock divided by 32 is used as RTC clock source,
mbed_official	340:28d1f895c6fe	993	* the RTC cannot be used in STOP and STANDBY modes.
mbed_official	340:28d1f895c6fe	994	* @note The system must always be configured so as to get a PCLK frequency greater than or
mbed_official	340:28d1f895c6fe	995	* equal to the RTCCLK frequency for a proper operation of the RTC.
mbed_official	340:28d1f895c6fe	996	*/
mbed_official	340:28d1f895c6fe	997	#define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) \
mbed_official	340:28d1f895c6fe	998	MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, (uint32_t)(__RTCCLKSource__))
mbed_official	340:28d1f895c6fe	999
mbed_official	340:28d1f895c6fe	1000	/** @brief Macro to get the RTC clock source.
mbed_official	340:28d1f895c6fe	1001	* @retval The clock source can be one of the following values:
mbed_official	340:28d1f895c6fe	1002	* @arg RCC_RTCCLKSOURCE_NONE: No clock selected as RTC clock
mbed_official	340:28d1f895c6fe	1003	* @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock
mbed_official	340:28d1f895c6fe	1004	* @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock
mbed_official	340:28d1f895c6fe	1005	* @arg RCC_RTCCLKSOURCE_HSE_DIV32: HSE clock divided by 32 selected as RTC clock
mbed_official	340:28d1f895c6fe	1006	*/
mbed_official	340:28d1f895c6fe	1007	#define __HAL_RCC_GET_RTC_SOURCE() ((uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)))
mbed_official	340:28d1f895c6fe	1008	/**
mbed_official	340:28d1f895c6fe	1009	* @}
mbed_official	340:28d1f895c6fe	1010	*/
mbed_official	340:28d1f895c6fe	1011
mbed_official	340:28d1f895c6fe	1012	/** @defgroup RCC_Force_Release_Backup RCC Force Release Backup
mbed_official	340:28d1f895c6fe	1013	* @{
mbed_official	340:28d1f895c6fe	1014	*/
mbed_official	340:28d1f895c6fe	1015
mbed_official	340:28d1f895c6fe	1016	/** @brief Macro to force or release the Backup domain reset.
mbed_official	340:28d1f895c6fe	1017	* @note These macros reset the RTC peripheral (including the backup registers)
mbed_official	340:28d1f895c6fe	1018	* and the RTC clock source selection in RCC_CSR register.
mbed_official	340:28d1f895c6fe	1019	* @note The BKPSRAM is not affected by this reset.
mbed_official	340:28d1f895c6fe	1020	*/
mbed_official	340:28d1f895c6fe	1021	#define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->BDCR, RCC_BDCR_BDRST)
mbed_official	340:28d1f895c6fe	1022	#define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST)
mbed_official	340:28d1f895c6fe	1023	/**
mbed_official	340:28d1f895c6fe	1024	* @}
mbed_official	340:28d1f895c6fe	1025	*/
mbed_official	340:28d1f895c6fe	1026
mbed_official	340:28d1f895c6fe	1027	/** @defgroup RCC_PLL_Configuration RCC PLL Configuration
mbed_official	340:28d1f895c6fe	1028	* @{
mbed_official	340:28d1f895c6fe	1029	*/
mbed_official	340:28d1f895c6fe	1030
mbed_official	340:28d1f895c6fe	1031	/** @brief Macro to enable or disable the PLL.
mbed_official	340:28d1f895c6fe	1032	* @note After enabling the PLL, the application software should wait on
mbed_official	340:28d1f895c6fe	1033	* PLLRDY flag to be set indicating that PLL clock is stable and can
mbed_official	340:28d1f895c6fe	1034	* be used as system clock source.
mbed_official	340:28d1f895c6fe	1035	* @note The PLL can not be disabled if it is used as system clock source
mbed_official	340:28d1f895c6fe	1036	* @note The PLL is disabled by hardware when entering STOP and STANDBY modes.
mbed_official	340:28d1f895c6fe	1037	*/
mbed_official	340:28d1f895c6fe	1038	#define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON)
mbed_official	340:28d1f895c6fe	1039	#define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON)
mbed_official	340:28d1f895c6fe	1040
mbed_official	340:28d1f895c6fe	1041	/** @brief Macro to configure the PLL clock source, multiplication and division factors.
mbed_official	340:28d1f895c6fe	1042	* @note This macro must be used only when the PLL is disabled.
mbed_official	340:28d1f895c6fe	1043	*
mbed_official	340:28d1f895c6fe	1044	* @param __RCC_PLLSource__: specifies the PLL entry clock source.
mbed_official	340:28d1f895c6fe	1045	* This parameter can be one of the following values:
mbed_official	340:28d1f895c6fe	1046	* @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
mbed_official	340:28d1f895c6fe	1047	* @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
mbed_official	340:28d1f895c6fe	1048	* @param __PREDIV__: specifies the predivider factor for PLL VCO input clock
mbed_official	340:28d1f895c6fe	1049	* This parameter must be a number between RCC_PREDIV_DIV1 and RCC_PREDIV_DIV16.
mbed_official	340:28d1f895c6fe	1050	* @param __PLLMUL__: specifies the multiplication factor for PLL VCO input clock
mbed_official	340:28d1f895c6fe	1051	* This parameter must be a number between RCC_PLL_MUL2 and RCC_PLL_MUL16.
mbed_official	340:28d1f895c6fe	1052	*
mbed_official	340:28d1f895c6fe	1053	*/
mbed_official	340:28d1f895c6fe	1054	#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__ , __PREDIV__, __PLLMUL__) \
mbed_official	340:28d1f895c6fe	1055	do { \
mbed_official	340:28d1f895c6fe	1056	MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (__PREDIV__)); \
mbed_official	340:28d1f895c6fe	1057	MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLMUL \| RCC_CFGR_PLLSRC, (uint32_t)((__PLLMUL__)\|(__RCC_PLLSource__))); \
mbed_official	340:28d1f895c6fe	1058	} while(0)
mbed_official	340:28d1f895c6fe	1059	/**
mbed_official	340:28d1f895c6fe	1060	* @}
mbed_official	340:28d1f895c6fe	1061	*/
mbed_official	340:28d1f895c6fe	1062
mbed_official	340:28d1f895c6fe	1063	/** @defgroup RCC_Get_Clock_source RCC Get Clock source
mbed_official	340:28d1f895c6fe	1064	* @{
mbed_official	340:28d1f895c6fe	1065	*/
mbed_official	340:28d1f895c6fe	1066
mbed_official	340:28d1f895c6fe	1067	/** @brief Macro to get the clock source used as system clock.
mbed_official	340:28d1f895c6fe	1068	* @retval The clock source used as system clock.
mbed_official	340:28d1f895c6fe	1069	* The returned value can be one of the following value:
mbed_official	340:28d1f895c6fe	1070	* @arg RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock
mbed_official	340:28d1f895c6fe	1071	* @arg RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock
mbed_official	340:28d1f895c6fe	1072	* @arg RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock
mbed_official	340:28d1f895c6fe	1073	*/
mbed_official	340:28d1f895c6fe	1074	#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS)))
mbed_official	340:28d1f895c6fe	1075
mbed_official	340:28d1f895c6fe	1076	/** @brief Macro to get the oscillator used as PLL clock source.
mbed_official	340:28d1f895c6fe	1077	* @retval The oscillator used as PLL clock source. The returned value can be one
mbed_official	340:28d1f895c6fe	1078	* of the following:
mbed_official	340:28d1f895c6fe	1079	* - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
mbed_official	340:28d1f895c6fe	1080	* - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.
mbed_official	340:28d1f895c6fe	1081	*/
mbed_official	340:28d1f895c6fe	1082	#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC)))
mbed_official	340:28d1f895c6fe	1083	/**
mbed_official	340:28d1f895c6fe	1084	* @}
mbed_official	340:28d1f895c6fe	1085	*/
mbed_official	340:28d1f895c6fe	1086
mbed_official	340:28d1f895c6fe	1087	/** @defgroup RCC_Flags_Interrupts_Management RCC Flags Interrupts Management
mbed_official	340:28d1f895c6fe	1088	* @brief macros to manage the specified RCC Flags and interrupts.
mbed_official	340:28d1f895c6fe	1089	* @{
mbed_official	340:28d1f895c6fe	1090	*/
mbed_official	340:28d1f895c6fe	1091
mbed_official	340:28d1f895c6fe	1092	/** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[12:8] bits to enable
mbed_official	340:28d1f895c6fe	1093	* the selected interrupts.).
mbed_official	340:28d1f895c6fe	1094	* @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled.
mbed_official	340:28d1f895c6fe	1095	* This parameter can be any combination of the following values:
mbed_official	340:28d1f895c6fe	1096	* @arg RCC_IT_LSIRDY: LSI ready interrupt enable
mbed_official	340:28d1f895c6fe	1097	* @arg RCC_IT_LSERDY: LSE ready interrupt enable
mbed_official	340:28d1f895c6fe	1098	* @arg RCC_IT_HSIRDY: HSI ready interrupt enable
mbed_official	340:28d1f895c6fe	1099	* @arg RCC_IT_HSERDY: HSE ready interrupt enable
mbed_official	340:28d1f895c6fe	1100	* @arg RCC_IT_PLLRDY: PLL ready interrupt enable
mbed_official	340:28d1f895c6fe	1101	* @arg RCC_IT_HSI14RDY: HSI14 ready interrupt enable
mbed_official	340:28d1f895c6fe	1102	* @arg RCC_IT_HSI48RDY: HSI48 ready interrupt enable (only applicable to STM32F0X2 USB devices)
mbed_official	340:28d1f895c6fe	1103	*/
mbed_official	340:28d1f895c6fe	1104	#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) ((__IO uint8_t )RCC_CIR_BYTE1_ADDRESS \|= (__INTERRUPT__))
mbed_official	340:28d1f895c6fe	1105
mbed_official	340:28d1f895c6fe	1106	/** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[12:8] bits to disable
mbed_official	340:28d1f895c6fe	1107	* the selected interrupts.).
mbed_official	340:28d1f895c6fe	1108	* @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled.
mbed_official	340:28d1f895c6fe	1109	* This parameter can be any combination of the following values:
mbed_official	340:28d1f895c6fe	1110	* @arg RCC_IT_LSIRDY: LSI ready interrupt enable
mbed_official	340:28d1f895c6fe	1111	* @arg RCC_IT_LSERDY: LSE ready interrupt enable
mbed_official	340:28d1f895c6fe	1112	* @arg RCC_IT_HSIRDY: HSI ready interrupt enable
mbed_official	340:28d1f895c6fe	1113	* @arg RCC_IT_HSERDY: HSE ready interrupt enable
mbed_official	340:28d1f895c6fe	1114	* @arg RCC_IT_PLLRDY: PLL ready interrupt enable
mbed_official	340:28d1f895c6fe	1115	* @arg RCC_IT_HSI14RDY: HSI14 ready interrupt enable
mbed_official	340:28d1f895c6fe	1116	* @arg RCC_IT_HSI48RDY: HSI48 ready interrupt enable (only applicable to STM32F0X2 USB devices)
mbed_official	340:28d1f895c6fe	1117	*/
mbed_official	340:28d1f895c6fe	1118	#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) ((__IO uint8_t )RCC_CIR_BYTE1_ADDRESS &= ~(__INTERRUPT__))
mbed_official	340:28d1f895c6fe	1119
mbed_official	340:28d1f895c6fe	1120	/** @brief Clear the RCC's interrupt pending bits ( Perform Byte access to RCC_CIR[23:16]
mbed_official	340:28d1f895c6fe	1121	* bits to clear the selected interrupt pending bits.
mbed_official	340:28d1f895c6fe	1122	* @param __IT__: specifies the interrupt pending bit to clear.
mbed_official	340:28d1f895c6fe	1123	* This parameter can be any combination of the following values:
mbed_official	340:28d1f895c6fe	1124	* @arg RCC_IT_LSIRDY: LSI ready interrupt clear
mbed_official	340:28d1f895c6fe	1125	* @arg RCC_IT_LSERDY: LSE ready interrupt clear
mbed_official	340:28d1f895c6fe	1126	* @arg RCC_IT_HSIRDY: HSI ready interrupt clear
mbed_official	340:28d1f895c6fe	1127	* @arg RCC_IT_HSERDY: HSE ready interrupt clear
mbed_official	340:28d1f895c6fe	1128	* @arg RCC_IT_PLLRDY: PLL ready interrupt clear
mbed_official	340:28d1f895c6fe	1129	* @arg RCC_IT_HSI14RDY: HSI14 ready interrupt clear
mbed_official	340:28d1f895c6fe	1130	* @arg RCC_IT_HSI48RDY: HSI48 ready interrupt clear (only applicable to STM32F0X2 USB devices)
mbed_official	340:28d1f895c6fe	1131	* @arg RCC_IT_CSS: Clock Security System interrupt clear
mbed_official	340:28d1f895c6fe	1132	*/
mbed_official	340:28d1f895c6fe	1133	#define __HAL_RCC_CLEAR_IT(__IT__) ((__IO uint8_t )RCC_CIR_BYTE2_ADDRESS = (__IT__))
mbed_official	340:28d1f895c6fe	1134
mbed_official	340:28d1f895c6fe	1135	/** @brief Check the RCC's interrupt has occurred or not.
mbed_official	340:28d1f895c6fe	1136	* @param __IT__: specifies the RCC interrupt source to check.
mbed_official	340:28d1f895c6fe	1137	* This parameter can be one of the following values:
mbed_official	340:28d1f895c6fe	1138	* @arg RCC_IT_LSIRDY: LSI ready interrupt flag
mbed_official	340:28d1f895c6fe	1139	* @arg RCC_IT_LSERDY: LSE ready interrupt flag
mbed_official	340:28d1f895c6fe	1140	* @arg RCC_IT_HSIRDY: HSI ready interrupt flag
mbed_official	340:28d1f895c6fe	1141	* @arg RCC_IT_HSERDY: HSE ready interrupt flag
mbed_official	340:28d1f895c6fe	1142	* @arg RCC_IT_PLLRDY: PLL ready interrupt flag
mbed_official	340:28d1f895c6fe	1143	* @arg RCC_IT_HSI14RDY: HSI14 ready interrupt flag
mbed_official	340:28d1f895c6fe	1144	* @arg RCC_IT_HSI48RDY: HSI48 ready interrupt flag (only applicable to STM32F0X2 USB devices)
mbed_official	340:28d1f895c6fe	1145	* @arg RCC_IT_CSS: Clock Security System interrupt flag
mbed_official	340:28d1f895c6fe	1146	* @retval The new state of __IT__ (TRUE or FALSE).
mbed_official	340:28d1f895c6fe	1147	*/
mbed_official	340:28d1f895c6fe	1148	#define __HAL_RCC_GET_IT(__IT__) ((RCC->CIR & (__IT__)) == (__IT__))
mbed_official	340:28d1f895c6fe	1149
mbed_official	340:28d1f895c6fe	1150	/** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST,
mbed_official	340:28d1f895c6fe	1151	* RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST
mbed_official	340:28d1f895c6fe	1152	*/
mbed_official	340:28d1f895c6fe	1153	#define __HAL_RCC_CLEAR_RESET_FLAGS() SET_BIT(RCC->CSR, RCC_CSR_RMVF)
mbed_official	340:28d1f895c6fe	1154
mbed_official	340:28d1f895c6fe	1155	/** @brief Check RCC flag is set or not.
mbed_official	340:28d1f895c6fe	1156	* @param __FLAG__: specifies the flag to check.
mbed_official	340:28d1f895c6fe	1157	* This parameter can be one of the following values:
mbed_official	340:28d1f895c6fe	1158	* @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready
mbed_official	340:28d1f895c6fe	1159	* @arg RCC_FLAG_HSERDY: HSE oscillator clock ready
mbed_official	340:28d1f895c6fe	1160	* @arg RCC_FLAG_PLLRDY: PLL clock ready
mbed_official	340:28d1f895c6fe	1161	* @arg RCC_FLAG_HSI14RDY: HSI14 oscillator clock ready
mbed_official	340:28d1f895c6fe	1162	* @arg RCC_FLAG_HSI48RDY: HSI48 oscillator clock ready (only applicable to STM32F0X2 USB devices)
mbed_official	340:28d1f895c6fe	1163	* @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
mbed_official	340:28d1f895c6fe	1164	* @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
mbed_official	340:28d1f895c6fe	1165	* @arg RCC_FLAG_OBLRST: Option Byte Load reset
mbed_official	340:28d1f895c6fe	1166	* @arg RCC_FLAG_PINRST: Pin reset
mbed_official	340:28d1f895c6fe	1167	* @arg RCC_FLAG_PORRST: POR/PDR reset
mbed_official	340:28d1f895c6fe	1168	* @arg RCC_FLAG_SFTRST: Software reset
mbed_official	340:28d1f895c6fe	1169	* @arg RCC_FLAG_IWDGRST: Independent Watchdog reset
mbed_official	340:28d1f895c6fe	1170	* @arg RCC_FLAG_WWDGRST: Window Watchdog reset
mbed_official	340:28d1f895c6fe	1171	* @arg RCC_FLAG_LPWRRST: Low Power reset
mbed_official	340:28d1f895c6fe	1172	* @retval The new state of __FLAG__ (TRUE or FALSE).
mbed_official	340:28d1f895c6fe	1173	*/
mbed_official	340:28d1f895c6fe	1174	#define RCC_FLAG_MASK ((uint8_t)0x1F)
mbed_official	340:28d1f895c6fe	1175	#define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5) == CR_REG_INDEX)? RCC->CR : \
mbed_official	340:28d1f895c6fe	1176	(((__FLAG__) >> 5) == CR2_REG_INDEX)? RCC->CR2 : \
mbed_official	340:28d1f895c6fe	1177	(((__FLAG__) >> 5) == BDCR_REG_INDEX) ? RCC->BDCR : \
mbed_official	340:28d1f895c6fe	1178	RCC->CSR) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK)))
mbed_official	340:28d1f895c6fe	1179
mbed_official	340:28d1f895c6fe	1180
mbed_official	340:28d1f895c6fe	1181
mbed_official	340:28d1f895c6fe	1182	/**
mbed_official	340:28d1f895c6fe	1183	* @}
mbed_official	340:28d1f895c6fe	1184	*/
mbed_official	340:28d1f895c6fe	1185
mbed_official	340:28d1f895c6fe	1186	/**
mbed_official	340:28d1f895c6fe	1187	* @}
mbed_official	340:28d1f895c6fe	1188	*/
mbed_official	340:28d1f895c6fe	1189
mbed_official	340:28d1f895c6fe	1190	/* Include RCC HAL Extension module */
mbed_official	340:28d1f895c6fe	1191	#include "stm32f0xx_hal_rcc_ex.h"
mbed_official	340:28d1f895c6fe	1192
mbed_official	340:28d1f895c6fe	1193	/* Exported functions --------------------------------------------------------*/
mbed_official	340:28d1f895c6fe	1194
mbed_official	340:28d1f895c6fe	1195	/** @addtogroup RCC_Exported_Functions
mbed_official	340:28d1f895c6fe	1196	* @{
mbed_official	340:28d1f895c6fe	1197	*/
mbed_official	340:28d1f895c6fe	1198
mbed_official	340:28d1f895c6fe	1199	/** @addtogroup RCC_Exported_Functions_Group1
mbed_official	340:28d1f895c6fe	1200	* @{
mbed_official	340:28d1f895c6fe	1201	*/
mbed_official	340:28d1f895c6fe	1202
mbed_official	340:28d1f895c6fe	1203	/* Initialization and de-initialization functions ***************************/
mbed_official	340:28d1f895c6fe	1204	void HAL_RCC_DeInit(void);
mbed_official	340:28d1f895c6fe	1205	HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
mbed_official	340:28d1f895c6fe	1206	HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
mbed_official	340:28d1f895c6fe	1207
mbed_official	340:28d1f895c6fe	1208	/**
mbed_official	340:28d1f895c6fe	1209	* @}
mbed_official	340:28d1f895c6fe	1210	*/
mbed_official	340:28d1f895c6fe	1211
mbed_official	340:28d1f895c6fe	1212	/** @addtogroup RCC_Exported_Functions_Group2
mbed_official	340:28d1f895c6fe	1213	* @{
mbed_official	340:28d1f895c6fe	1214	*/
mbed_official	340:28d1f895c6fe	1215
mbed_official	340:28d1f895c6fe	1216	/* Peripheral Control functions *********************************************/
mbed_official	340:28d1f895c6fe	1217	void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
mbed_official	340:28d1f895c6fe	1218	void HAL_RCC_EnableCSS(void);
mbed_official	340:28d1f895c6fe	1219	void HAL_RCC_DisableCSS(void);
mbed_official	340:28d1f895c6fe	1220	uint32_t HAL_RCC_GetSysClockFreq(void);
mbed_official	340:28d1f895c6fe	1221	uint32_t HAL_RCC_GetHCLKFreq(void);
mbed_official	340:28d1f895c6fe	1222	uint32_t HAL_RCC_GetPCLK1Freq(void);
mbed_official	340:28d1f895c6fe	1223	void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
mbed_official	340:28d1f895c6fe	1224	void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef RCC_ClkInitStruct, uint32_t pFLatency);
mbed_official	340:28d1f895c6fe	1225
mbed_official	340:28d1f895c6fe	1226	/* CSS NMI IRQ handler */
mbed_official	340:28d1f895c6fe	1227	void HAL_RCC_NMI_IRQHandler(void);
mbed_official	340:28d1f895c6fe	1228
mbed_official	340:28d1f895c6fe	1229	/* User Callbacks in non blocking mode (IT mode) */
mbed_official	340:28d1f895c6fe	1230	void HAL_RCC_CCSCallback(void);
mbed_official	340:28d1f895c6fe	1231
mbed_official	340:28d1f895c6fe	1232	/**
mbed_official	340:28d1f895c6fe	1233	* @}
mbed_official	340:28d1f895c6fe	1234	*/
mbed_official	340:28d1f895c6fe	1235
mbed_official	340:28d1f895c6fe	1236	/**
mbed_official	340:28d1f895c6fe	1237	* @}
mbed_official	340:28d1f895c6fe	1238	*/
mbed_official	340:28d1f895c6fe	1239
mbed_official	340:28d1f895c6fe	1240	/**
mbed_official	340:28d1f895c6fe	1241	* @}
mbed_official	340:28d1f895c6fe	1242	*/
mbed_official	340:28d1f895c6fe	1243
mbed_official	340:28d1f895c6fe	1244	/**
mbed_official	340:28d1f895c6fe	1245	* @}
mbed_official	340:28d1f895c6fe	1246	*/
mbed_official	340:28d1f895c6fe	1247
mbed_official	340:28d1f895c6fe	1248	#ifdef __cplusplus
mbed_official	340:28d1f895c6fe	1249	}
mbed_official	340:28d1f895c6fe	1250	#endif
mbed_official	340:28d1f895c6fe	1251
mbed_official	340:28d1f895c6fe	1252	#endif /* __STM32F0xx_HAL_RCC_H */
mbed_official	340:28d1f895c6fe	1253
mbed_official	340:28d1f895c6fe	1254	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/
mbed_official	340:28d1f895c6fe	1255