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targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_dma_ex.h@579:53297373a894, 2015-07-01 (annotated)

Committer:: mbed_official
Date:: Wed Jul 01 09:45:11 2015 +0100
Revision:: 579:53297373a894
Parent:: 441:d2c15dda23c1
Child:: 630:825f75ca301e

Synchronized with git revision d5b4d2ab9c47edb4dc5776e7177b0c2263459081

Full URL: https://github.com/mbedmicro/mbed/commit/d5b4d2ab9c47edb4dc5776e7177b0c2263459081/

Initial version of drivers for SAMR21

Who changed what in which revision?

User	Revision	Line number	New contents of line
mbed_official	340:28d1f895c6fe	1	/**
mbed_official	340:28d1f895c6fe	2	******************************************************************************
mbed_official	340:28d1f895c6fe	3	* @file stm32f0xx_hal_dma_ex.h
mbed_official	340:28d1f895c6fe	4	* @author MCD Application Team
mbed_official	441:d2c15dda23c1	5	* @version V1.2.0
mbed_official	441:d2c15dda23c1	6	* @date 11-December-2014
mbed_official	340:28d1f895c6fe	7	* @brief Header file of DMA HAL Extension module.
mbed_official	340:28d1f895c6fe	8	******************************************************************************
mbed_official	340:28d1f895c6fe	9	* @attention
mbed_official	340:28d1f895c6fe	10	*
mbed_official	340:28d1f895c6fe	11	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
mbed_official	340:28d1f895c6fe	12	*
mbed_official	340:28d1f895c6fe	13	* Redistribution and use in source and binary forms, with or without modification,
mbed_official	340:28d1f895c6fe	14	* are permitted provided that the following conditions are met:
mbed_official	340:28d1f895c6fe	15	* 1. Redistributions of source code must retain the above copyright notice,
mbed_official	340:28d1f895c6fe	16	* this list of conditions and the following disclaimer.
mbed_official	340:28d1f895c6fe	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official	340:28d1f895c6fe	18	* this list of conditions and the following disclaimer in the documentation
mbed_official	340:28d1f895c6fe	19	* and/or other materials provided with the distribution.
mbed_official	340:28d1f895c6fe	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official	340:28d1f895c6fe	21	* may be used to endorse or promote products derived from this software
mbed_official	340:28d1f895c6fe	22	* without specific prior written permission.
mbed_official	340:28d1f895c6fe	23	*
mbed_official	340:28d1f895c6fe	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official	340:28d1f895c6fe	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official	340:28d1f895c6fe	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official	340:28d1f895c6fe	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official	340:28d1f895c6fe	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official	340:28d1f895c6fe	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official	340:28d1f895c6fe	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official	340:28d1f895c6fe	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official	340:28d1f895c6fe	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official	340:28d1f895c6fe	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official	340:28d1f895c6fe	34	*
mbed_official	340:28d1f895c6fe	35	******************************************************************************
mbed_official	340:28d1f895c6fe	36	*/
mbed_official	340:28d1f895c6fe	37
mbed_official	340:28d1f895c6fe	38	/* Define to prevent recursive inclusion -------------------------------------*/
mbed_official	340:28d1f895c6fe	39	#ifndef __STM32F0xx_HAL_DMA_EX_H
mbed_official	340:28d1f895c6fe	40	#define __STM32F0xx_HAL_DMA_EX_H
mbed_official	340:28d1f895c6fe	41
mbed_official	340:28d1f895c6fe	42	#ifdef __cplusplus
mbed_official	340:28d1f895c6fe	43	extern "C" {
mbed_official	340:28d1f895c6fe	44	#endif
mbed_official	340:28d1f895c6fe	45
mbed_official	340:28d1f895c6fe	46	/* Includes ------------------------------------------------------------------*/
mbed_official	340:28d1f895c6fe	47	#include "stm32f0xx_hal_def.h"
mbed_official	340:28d1f895c6fe	48
mbed_official	340:28d1f895c6fe	49	/** @addtogroup STM32F0xx_HAL_Driver
mbed_official	340:28d1f895c6fe	50	* @{
mbed_official	340:28d1f895c6fe	51	*/
mbed_official	340:28d1f895c6fe	52
mbed_official	340:28d1f895c6fe	53	/** @addtogroup DMAEx
mbed_official	340:28d1f895c6fe	54	* @{
mbed_official	340:28d1f895c6fe	55	*/
mbed_official	340:28d1f895c6fe	56
mbed_official	340:28d1f895c6fe	57	/* Exported types ------------------------------------------------------------*/
mbed_official	340:28d1f895c6fe	58	/* Exported constants --------------------------------------------------------*/
mbed_official	441:d2c15dda23c1	59	#if defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
mbed_official	340:28d1f895c6fe	60	/** @defgroup DMAEx_Exported_Constants DMAEx Exported Constants
mbed_official	340:28d1f895c6fe	61	* @{
mbed_official	340:28d1f895c6fe	62	*/
mbed_official	441:d2c15dda23c1	63	#define DMA1_CHANNEL1_RMP 0x00000000 /!< Internal define for remaping on STM32F09x/30xC /
mbed_official	441:d2c15dda23c1	64	#define DMA1_CHANNEL2_RMP 0x10000000 /!< Internal define for remaping on STM32F09x/30xC /
mbed_official	441:d2c15dda23c1	65	#define DMA1_CHANNEL3_RMP 0x20000000 /!< Internal define for remaping on STM32F09x/30xC /
mbed_official	441:d2c15dda23c1	66	#define DMA1_CHANNEL4_RMP 0x30000000 /!< Internal define for remaping on STM32F09x/30xC /
mbed_official	441:d2c15dda23c1	67	#define DMA1_CHANNEL5_RMP 0x40000000 /!< Internal define for remaping on STM32F09x/30xC /
mbed_official	441:d2c15dda23c1	68	#if !defined(STM32F030xC)
mbed_official	441:d2c15dda23c1	69	#define DMA1_CHANNEL6_RMP 0x50000000 /!< Internal define for remaping on STM32F09x/30xC /
mbed_official	441:d2c15dda23c1	70	#define DMA1_CHANNEL7_RMP 0x60000000 /!< Internal define for remaping on STM32F09x/30xC /
mbed_official	441:d2c15dda23c1	71	#define DMA2_CHANNEL1_RMP 0x00000000 /!< Internal define for remaping on STM32F09x/30xC /
mbed_official	441:d2c15dda23c1	72	#define DMA2_CHANNEL2_RMP 0x10000000 /!< Internal define for remaping on STM32F09x/30xC /
mbed_official	441:d2c15dda23c1	73	#define DMA2_CHANNEL3_RMP 0x20000000 /!< Internal define for remaping on STM32F09x/30xC /
mbed_official	441:d2c15dda23c1	74	#define DMA2_CHANNEL4_RMP 0x30000000 /!< Internal define for remaping on STM32F09x/30xC /
mbed_official	441:d2c15dda23c1	75	#define DMA2_CHANNEL5_RMP 0x40000000 /!< Internal define for remaping on STM32F09x/30xC /
mbed_official	441:d2c15dda23c1	76	#endif /* !defined(STM32F030xC) */
mbed_official	340:28d1f895c6fe	77
mbed_official	340:28d1f895c6fe	78	/**************** DMA1 remap bit field definition******************/
mbed_official	340:28d1f895c6fe	79	/* DMA1 - Channel 1 */
mbed_official	441:d2c15dda23c1	80	#define HAL_DMA1_CH1_DEFAULT (uint32_t) (DMA1_CHANNEL1_RMP \| DMA1_CSELR_DEFAULT) /!< Default remap position for DMA1 /
mbed_official	441:d2c15dda23c1	81	#define HAL_DMA1_CH1_ADC (uint32_t) (DMA1_CHANNEL1_RMP \| DMA1_CSELR_CH1_ADC) /!< Remap ADC on DMA1 Channel 1/
mbed_official	441:d2c15dda23c1	82	#define HAL_DMA1_CH1_TIM17_CH1 (uint32_t) (DMA1_CHANNEL1_RMP \| DMA1_CSELR_CH1_TIM17_CH1) /!< Remap TIM17 channel 1 on DMA1 channel 1 /
mbed_official	441:d2c15dda23c1	83	#define HAL_DMA1_CH1_TIM17_UP (uint32_t) (DMA1_CHANNEL1_RMP \| DMA1_CSELR_CH1_TIM17_UP) /!< Remap TIM17 up on DMA1 channel 1 /
mbed_official	441:d2c15dda23c1	84	#define HAL_DMA1_CH1_USART1_RX (uint32_t) (DMA1_CHANNEL1_RMP \| DMA1_CSELR_CH1_USART1_RX) /!< Remap USART1 Rx on DMA1 channel 1 /
mbed_official	441:d2c15dda23c1	85	#define HAL_DMA1_CH1_USART2_RX (uint32_t) (DMA1_CHANNEL1_RMP \| DMA1_CSELR_CH1_USART2_RX) /!< Remap USART2 Rx on DMA1 channel 1 /
mbed_official	441:d2c15dda23c1	86	#define HAL_DMA1_CH1_USART3_RX (uint32_t) (DMA1_CHANNEL1_RMP \| DMA1_CSELR_CH1_USART3_RX) /!< Remap USART3 Rx on DMA1 channel 1 /
mbed_official	441:d2c15dda23c1	87	#define HAL_DMA1_CH1_USART4_RX (uint32_t) (DMA1_CHANNEL1_RMP \| DMA1_CSELR_CH1_USART4_RX) /!< Remap USART4 Rx on DMA1 channel 1 /
mbed_official	441:d2c15dda23c1	88	#define HAL_DMA1_CH1_USART5_RX (uint32_t) (DMA1_CHANNEL1_RMP \| DMA1_CSELR_CH1_USART5_RX) /!< Remap USART5 Rx on DMA1 channel 1 /
mbed_official	441:d2c15dda23c1	89	#define HAL_DMA1_CH1_USART6_RX (uint32_t) (DMA1_CHANNEL1_RMP \| DMA1_CSELR_CH1_USART6_RX) /!< Remap USART6 Rx on DMA1 channel 1 /
mbed_official	441:d2c15dda23c1	90	#if !defined(STM32F030xC)
mbed_official	441:d2c15dda23c1	91	#define HAL_DMA1_CH1_USART7_RX (uint32_t) (DMA1_CHANNEL1_RMP \| DMA1_CSELR_CH1_USART7_RX) /!< Remap USART7 Rx on DMA1 channel 1 /
mbed_official	441:d2c15dda23c1	92	#define HAL_DMA1_CH1_USART8_RX (uint32_t) (DMA1_CHANNEL1_RMP \| DMA1_CSELR_CH1_USART8_RX) /!< Remap USART8 Rx on DMA1 channel 1 /
mbed_official	441:d2c15dda23c1	93	#endif /* !defined(STM32F030xC) */
mbed_official	441:d2c15dda23c1	94
mbed_official	340:28d1f895c6fe	95	/* DMA1 - Channel 2 */
mbed_official	441:d2c15dda23c1	96	#define HAL_DMA1_CH2_DEFAULT (uint32_t) (DMA1_CHANNEL2_RMP \| DMA1_CSELR_DEFAULT) /!< Default remap position for DMA1 /
mbed_official	441:d2c15dda23c1	97	#define HAL_DMA1_CH2_ADC (uint32_t) (DMA1_CHANNEL2_RMP \| DMA1_CSELR_CH2_ADC) /!< Remap ADC on DMA1 channel 2 /
mbed_official	441:d2c15dda23c1	98	#define HAL_DMA1_CH2_I2C1_TX (uint32_t) (DMA1_CHANNEL2_RMP \| DMA1_CSELR_CH2_I2C1_TX) /!< Remap I2C1 Tx on DMA1 channel 2 /
mbed_official	441:d2c15dda23c1	99	#define HAL_DMA1_CH2_SPI1_RX (uint32_t) (DMA1_CHANNEL2_RMP \| DMA1_CSELR_CH2_SPI1_RX) /!< Remap SPI1 Rx on DMA1 channel 2 /
mbed_official	441:d2c15dda23c1	100	#define HAL_DMA1_CH2_TIM1_CH1 (uint32_t) (DMA1_CHANNEL2_RMP \| DMA1_CSELR_CH2_TIM1_CH1) /!< Remap TIM1 channel 1 on DMA1 channel 2 /
mbed_official	441:d2c15dda23c1	101	#define HAL_DMA1_CH2_TIM17_CH1 (uint32_t) (DMA1_CHANNEL2_RMP \| DMA1_CSELR_CH2_TIM17_CH1) /!< Remap TIM17 channel 1 on DMA1 channel 2 /
mbed_official	441:d2c15dda23c1	102	#define HAL_DMA1_CH2_TIM17_UP (uint32_t) (DMA1_CHANNEL2_RMP \| DMA1_CSELR_CH2_TIM17_UP) /!< Remap TIM17 up on DMA1 channel 2 /
mbed_official	441:d2c15dda23c1	103	#define HAL_DMA1_CH2_USART1_TX (uint32_t) (DMA1_CHANNEL2_RMP \| DMA1_CSELR_CH2_USART1_TX) /!< Remap USART1 Tx on DMA1 channel 2 /
mbed_official	441:d2c15dda23c1	104	#define HAL_DMA1_CH2_USART2_TX (uint32_t) (DMA1_CHANNEL2_RMP \| DMA1_CSELR_CH2_USART2_TX) /!< Remap USART2 Tx on DMA1 channel 2 /
mbed_official	441:d2c15dda23c1	105	#define HAL_DMA1_CH2_USART3_TX (uint32_t) (DMA1_CHANNEL2_RMP \| DMA1_CSELR_CH2_USART3_TX) /!< Remap USART3 Tx on DMA1 channel 2 /
mbed_official	441:d2c15dda23c1	106	#define HAL_DMA1_CH2_USART4_TX (uint32_t) (DMA1_CHANNEL2_RMP \| DMA1_CSELR_CH2_USART4_TX) /!< Remap USART4 Tx on DMA1 channel 2 /
mbed_official	441:d2c15dda23c1	107	#define HAL_DMA1_CH2_USART5_TX (uint32_t) (DMA1_CHANNEL2_RMP \| DMA1_CSELR_CH2_USART5_TX) /!< Remap USART5 Tx on DMA1 channel 2 /
mbed_official	441:d2c15dda23c1	108	#define HAL_DMA1_CH2_USART6_TX (uint32_t) (DMA1_CHANNEL2_RMP \| DMA1_CSELR_CH2_USART6_TX) /!< Remap USART6 Tx on DMA1 channel 2 /
mbed_official	441:d2c15dda23c1	109	#if !defined(STM32F030xC)
mbed_official	441:d2c15dda23c1	110	#define HAL_DMA1_CH2_USART7_TX (uint32_t) (DMA1_CHANNEL2_RMP \| DMA1_CSELR_CH2_USART7_TX) /!< Remap USART7 Tx on DMA1 channel 2 /
mbed_official	441:d2c15dda23c1	111	#define HAL_DMA1_CH2_USART8_TX (uint32_t) (DMA1_CHANNEL2_RMP \| DMA1_CSELR_CH2_USART8_TX) /!< Remap USART8 Tx on DMA1 channel 2 /
mbed_official	441:d2c15dda23c1	112	#endif /* !defined(STM32F030xC) */
mbed_official	441:d2c15dda23c1	113
mbed_official	340:28d1f895c6fe	114	/* DMA1 - Channel 3 */
mbed_official	441:d2c15dda23c1	115	#define HAL_DMA1_CH3_DEFAULT (uint32_t) (DMA1_CHANNEL3_RMP \| DMA1_CSELR_DEFAULT) /!< Default remap position for DMA1 /
mbed_official	441:d2c15dda23c1	116	#define HAL_DMA1_CH3_TIM6_UP (uint32_t) (DMA1_CHANNEL3_RMP \| DMA1_CSELR_CH3_TIM6_UP) /!< Remap TIM6 up on DMA1 channel 3 /
mbed_official	441:d2c15dda23c1	117	#if !defined(STM32F030xC)
mbed_official	441:d2c15dda23c1	118	#define HAL_DMA1_CH3_DAC_CH1 (uint32_t) (DMA1_CHANNEL3_RMP \| DMA1_CSELR_CH3_DAC_CH1) /!< Remap DAC Channel 1on DMA1 channel 3 /
mbed_official	441:d2c15dda23c1	119	#endif /* !defined(STM32F030xC) */
mbed_official	441:d2c15dda23c1	120	#define HAL_DMA1_CH3_I2C1_RX (uint32_t) (DMA1_CHANNEL3_RMP \| DMA1_CSELR_CH3_I2C1_RX) /!< Remap I2C1 Rx on DMA1 channel 3 /
mbed_official	441:d2c15dda23c1	121	#define HAL_DMA1_CH3_SPI1_TX (uint32_t) (DMA1_CHANNEL3_RMP \| DMA1_CSELR_CH3_SPI1_TX) /!< Remap SPI1 Tx on DMA1 channel 3 /
mbed_official	441:d2c15dda23c1	122	#define HAL_DMA1_CH3_TIM1_CH2 (uint32_t) (DMA1_CHANNEL3_RMP \| DMA1_CSELR_CH3_TIM1_CH2) /!< Remap TIM1 channel 2 on DMA1 channel 3 /
mbed_official	441:d2c15dda23c1	123	#if !defined(STM32F030xC)
mbed_official	441:d2c15dda23c1	124	#define HAL_DMA1_CH3_TIM2_CH2 (uint32_t) (DMA1_CHANNEL3_RMP \| DMA1_CSELR_CH3_TIM2_CH2) /!< Remap TIM2 channel 2 on DMA1 channel 3 /
mbed_official	441:d2c15dda23c1	125	#endif /* !defined(STM32F030xC) */
mbed_official	441:d2c15dda23c1	126	#define HAL_DMA1_CH3_TIM16_CH1 (uint32_t) (DMA1_CHANNEL3_RMP \| DMA1_CSELR_CH3_TIM16_CH1) /!< Remap TIM16 channel 1 on DMA1 channel 3 /
mbed_official	441:d2c15dda23c1	127	#define HAL_DMA1_CH3_TIM16_UP (uint32_t) (DMA1_CHANNEL3_RMP \| DMA1_CSELR_CH3_TIM16_UP) /!< Remap TIM16 up on DMA1 channel 3 /
mbed_official	441:d2c15dda23c1	128	#define HAL_DMA1_CH3_USART1_RX (uint32_t) (DMA1_CHANNEL3_RMP \| DMA1_CSELR_CH3_USART1_RX) /!< Remap USART1 Rx on DMA1 channel 3 /
mbed_official	441:d2c15dda23c1	129	#define HAL_DMA1_CH3_USART2_RX (uint32_t) (DMA1_CHANNEL3_RMP \| DMA1_CSELR_CH3_USART2_RX) /!< Remap USART2 Rx on DMA1 channel 3 /
mbed_official	441:d2c15dda23c1	130	#define HAL_DMA1_CH3_USART3_RX (uint32_t) (DMA1_CHANNEL3_RMP \| DMA1_CSELR_CH3_USART3_RX) /!< Remap USART3 Rx on DMA1 channel 3 /
mbed_official	441:d2c15dda23c1	131	#define HAL_DMA1_CH3_USART4_RX (uint32_t) (DMA1_CHANNEL3_RMP \| DMA1_CSELR_CH3_USART4_RX) /!< Remap USART4 Rx on DMA1 channel 3 /
mbed_official	441:d2c15dda23c1	132	#define HAL_DMA1_CH3_USART5_RX (uint32_t) (DMA1_CHANNEL3_RMP \| DMA1_CSELR_CH3_USART5_RX) /!< Remap USART5 Rx on DMA1 channel 3 /
mbed_official	441:d2c15dda23c1	133	#define HAL_DMA1_CH3_USART6_RX (uint32_t) (DMA1_CHANNEL3_RMP \| DMA1_CSELR_CH3_USART6_RX) /!< Remap USART6 Rx on DMA1 channel 3 /
mbed_official	441:d2c15dda23c1	134	#if !defined(STM32F030xC)
mbed_official	441:d2c15dda23c1	135	#define HAL_DMA1_CH3_USART7_RX (uint32_t) (DMA1_CHANNEL3_RMP \| DMA1_CSELR_CH3_USART7_RX) /!< Remap USART7 Rx on DMA1 channel 3 /
mbed_official	441:d2c15dda23c1	136	#define HAL_DMA1_CH3_USART8_RX (uint32_t) (DMA1_CHANNEL3_RMP \| DMA1_CSELR_CH3_USART8_RX) /!< Remap USART8 Rx on DMA1 channel 3 /
mbed_official	441:d2c15dda23c1	137	#endif /* !defined(STM32F030xC) */
mbed_official	441:d2c15dda23c1	138
mbed_official	340:28d1f895c6fe	139	/* DMA1 - Channel 4 */
mbed_official	441:d2c15dda23c1	140	#define HAL_DMA1_CH4_DEFAULT (uint32_t) (DMA1_CHANNEL4_RMP \| DMA1_CSELR_DEFAULT) /!< Default remap position for DMA1 /
mbed_official	441:d2c15dda23c1	141	#define HAL_DMA1_CH4_TIM7_UP (uint32_t) (DMA1_CHANNEL4_RMP \| DMA1_CSELR_CH4_TIM7_UP) /!< Remap TIM7 up on DMA1 channel 4 /
mbed_official	441:d2c15dda23c1	142	#if !defined(STM32F030xC)
mbed_official	441:d2c15dda23c1	143	#define HAL_DMA1_CH4_DAC_CH2 (uint32_t) (DMA1_CHANNEL4_RMP \| DMA1_CSELR_CH4_DAC_CH2) /!< Remap DAC Channel 2 on DMA1 channel 4 /
mbed_official	441:d2c15dda23c1	144	#endif /* !defined(STM32F030xC) */
mbed_official	441:d2c15dda23c1	145	#define HAL_DMA1_CH4_I2C2_TX (uint32_t) (DMA1_CHANNEL4_RMP \| DMA1_CSELR_CH4_I2C2_TX) /!< Remap I2C2 Tx on DMA1 channel 4 /
mbed_official	441:d2c15dda23c1	146	#define HAL_DMA1_CH4_SPI2_RX (uint32_t) (DMA1_CHANNEL4_RMP \| DMA1_CSELR_CH4_SPI2_RX) /!< Remap SPI2 Rx on DMA1 channel 4 /
mbed_official	441:d2c15dda23c1	147	#if !defined(STM32F030xC)
mbed_official	441:d2c15dda23c1	148	#define HAL_DMA1_CH4_TIM2_CH4 (uint32_t) (DMA1_CHANNEL4_RMP \| DMA1_CSELR_CH4_TIM2_CH4) /!< Remap TIM2 channel 4 on DMA1 channel 4 /
mbed_official	441:d2c15dda23c1	149	#endif /* !defined(STM32F030xC) */
mbed_official	441:d2c15dda23c1	150	#define HAL_DMA1_CH4_TIM3_CH1 (uint32_t) (DMA1_CHANNEL4_RMP \| DMA1_CSELR_CH4_TIM3_CH1) /!< Remap TIM3 channel 1 on DMA1 channel 4 /
mbed_official	441:d2c15dda23c1	151	#define HAL_DMA1_CH4_TIM3_TRIG (uint32_t) (DMA1_CHANNEL4_RMP \| DMA1_CSELR_CH4_TIM3_TRIG) /!< Remap TIM3 Trig on DMA1 channel 4 /
mbed_official	441:d2c15dda23c1	152	#define HAL_DMA1_CH4_TIM16_CH1 (uint32_t) (DMA1_CHANNEL4_RMP \| DMA1_CSELR_CH4_TIM16_CH1) /!< Remap TIM16 channel 1 on DMA1 channel 4 /
mbed_official	441:d2c15dda23c1	153	#define HAL_DMA1_CH4_TIM16_UP (uint32_t) (DMA1_CHANNEL4_RMP \| DMA1_CSELR_CH4_TIM16_UP) /!< Remap TIM16 up on DMA1 channel 4 /
mbed_official	441:d2c15dda23c1	154	#define HAL_DMA1_CH4_USART1_TX (uint32_t) (DMA1_CHANNEL4_RMP \| DMA1_CSELR_CH4_USART1_TX) /!< Remap USART1 Tx on DMA1 channel 4 /
mbed_official	441:d2c15dda23c1	155	#define HAL_DMA1_CH4_USART2_TX (uint32_t) (DMA1_CHANNEL4_RMP \| DMA1_CSELR_CH4_USART2_TX) /!< Remap USART2 Tx on DMA1 channel 4 /
mbed_official	441:d2c15dda23c1	156	#define HAL_DMA1_CH4_USART3_TX (uint32_t) (DMA1_CHANNEL4_RMP \| DMA1_CSELR_CH4_USART3_TX) /!< Remap USART3 Tx on DMA1 channel 4 /
mbed_official	441:d2c15dda23c1	157	#define HAL_DMA1_CH4_USART4_TX (uint32_t) (DMA1_CHANNEL4_RMP \| DMA1_CSELR_CH4_USART4_TX) /!< Remap USART4 Tx on DMA1 channel 4 /
mbed_official	441:d2c15dda23c1	158	#define HAL_DMA1_CH4_USART5_TX (uint32_t) (DMA1_CHANNEL4_RMP \| DMA1_CSELR_CH4_USART5_TX) /!< Remap USART5 Tx on DMA1 channel 4 /
mbed_official	441:d2c15dda23c1	159	#define HAL_DMA1_CH4_USART6_TX (uint32_t) (DMA1_CHANNEL4_RMP \| DMA1_CSELR_CH4_USART6_TX) /!< Remap USART6 Tx on DMA1 channel 4 /
mbed_official	441:d2c15dda23c1	160	#if !defined(STM32F030xC)
mbed_official	441:d2c15dda23c1	161	#define HAL_DMA1_CH4_USART7_TX (uint32_t) (DMA1_CHANNEL4_RMP \| DMA1_CSELR_CH4_USART7_TX) /!< Remap USART7 Tx on DMA1 channel 4 /
mbed_official	441:d2c15dda23c1	162	#define HAL_DMA1_CH4_USART8_TX (uint32_t) (DMA1_CHANNEL4_RMP \| DMA1_CSELR_CH4_USART8_TX) /!< Remap USART8 Tx on DMA1 channel 4 /
mbed_official	441:d2c15dda23c1	163	#endif /* !defined(STM32F030xC) */
mbed_official	441:d2c15dda23c1	164
mbed_official	340:28d1f895c6fe	165	/* DMA1 - Channel 5 */
mbed_official	441:d2c15dda23c1	166	#define HAL_DMA1_CH5_DEFAULT (uint32_t) (DMA1_CHANNEL5_RMP \| DMA1_CSELR_DEFAULT) /!< Default remap position for DMA1 /
mbed_official	441:d2c15dda23c1	167	#define HAL_DMA1_CH5_I2C2_RX (uint32_t) (DMA1_CHANNEL5_RMP \| DMA1_CSELR_CH5_I2C2_RX) /!< Remap I2C2 Rx on DMA1 channel 5 /
mbed_official	441:d2c15dda23c1	168	#define HAL_DMA1_CH5_SPI2_TX (uint32_t) (DMA1_CHANNEL5_RMP \| DMA1_CSELR_CH5_SPI2_TX) /!< Remap SPI1 Tx on DMA1 channel 5 /
mbed_official	441:d2c15dda23c1	169	#define HAL_DMA1_CH5_TIM1_CH3 (uint32_t) (DMA1_CHANNEL5_RMP \| DMA1_CSELR_CH5_TIM1_CH3) /!< Remap TIM1 channel 3 on DMA1 channel 5 /
mbed_official	441:d2c15dda23c1	170	#define HAL_DMA1_CH5_USART1_RX (uint32_t) (DMA1_CHANNEL5_RMP \| DMA1_CSELR_CH5_USART1_RX) /!< Remap USART1 Rx on DMA1 channel 5 /
mbed_official	441:d2c15dda23c1	171	#define HAL_DMA1_CH5_USART2_RX (uint32_t) (DMA1_CHANNEL5_RMP \| DMA1_CSELR_CH5_USART2_RX) /!< Remap USART2 Rx on DMA1 channel 5 /
mbed_official	441:d2c15dda23c1	172	#define HAL_DMA1_CH5_USART3_RX (uint32_t) (DMA1_CHANNEL5_RMP \| DMA1_CSELR_CH5_USART3_RX) /!< Remap USART3 Rx on DMA1 channel 5 /
mbed_official	441:d2c15dda23c1	173	#define HAL_DMA1_CH5_USART4_RX (uint32_t) (DMA1_CHANNEL5_RMP \| DMA1_CSELR_CH5_USART4_RX) /!< Remap USART4 Rx on DMA1 channel 5 /
mbed_official	441:d2c15dda23c1	174	#define HAL_DMA1_CH5_USART5_RX (uint32_t) (DMA1_CHANNEL5_RMP \| DMA1_CSELR_CH5_USART5_RX) /!< Remap USART5 Rx on DMA1 channel 5 /
mbed_official	441:d2c15dda23c1	175	#define HAL_DMA1_CH5_USART6_RX (uint32_t) (DMA1_CHANNEL5_RMP \| DMA1_CSELR_CH5_USART6_RX) /!< Remap USART6 Rx on DMA1 channel 5 /
mbed_official	441:d2c15dda23c1	176	#if !defined(STM32F030xC)
mbed_official	441:d2c15dda23c1	177	#define HAL_DMA1_CH5_USART7_RX (uint32_t) (DMA1_CHANNEL5_RMP \| DMA1_CSELR_CH5_USART7_RX) /!< Remap USART7 Rx on DMA1 channel 5 /
mbed_official	441:d2c15dda23c1	178	#define HAL_DMA1_CH5_USART8_RX (uint32_t) (DMA1_CHANNEL5_RMP \| DMA1_CSELR_CH5_USART8_RX) /!< Remap USART8 Rx on DMA1 channel 5 /
mbed_official	441:d2c15dda23c1	179	#endif /* !defined(STM32F030xC) */
mbed_official	441:d2c15dda23c1	180
mbed_official	441:d2c15dda23c1	181	#if !defined(STM32F030xC)
mbed_official	340:28d1f895c6fe	182	/* DMA1 - Channel 6 */
mbed_official	441:d2c15dda23c1	183	#define HAL_DMA1_CH6_DEFAULT (uint32_t) (DMA1_CHANNEL6_RMP \| DMA1_CSELR_DEFAULT) /!< Default remap position for DMA1 /
mbed_official	441:d2c15dda23c1	184	#define HAL_DMA1_CH6_I2C1_TX (uint32_t) (DMA1_CHANNEL6_RMP \| DMA1_CSELR_CH6_I2C1_TX) /!< Remap I2C1 Tx on DMA1 channel 6 /
mbed_official	441:d2c15dda23c1	185	#define HAL_DMA1_CH6_SPI2_RX (uint32_t) (DMA1_CHANNEL6_RMP \| DMA1_CSELR_CH6_SPI2_RX) /!< Remap SPI2 Rx on DMA1 channel 6 /
mbed_official	441:d2c15dda23c1	186	#define HAL_DMA1_CH6_TIM1_CH1 (uint32_t) (DMA1_CHANNEL6_RMP \| DMA1_CSELR_CH6_TIM1_CH1) /!< Remap TIM1 channel 1 on DMA1 channel 6 /
mbed_official	441:d2c15dda23c1	187	#define HAL_DMA1_CH6_TIM1_CH2 (uint32_t) (DMA1_CHANNEL6_RMP \| DMA1_CSELR_CH6_TIM1_CH2) /!< Remap TIM1 channel 2 on DMA1 channel 6 /
mbed_official	441:d2c15dda23c1	188	#define HAL_DMA1_CH6_TIM1_CH3 (uint32_t) (DMA1_CHANNEL6_RMP \| DMA1_CSELR_CH6_TIM1_CH3) /!< Remap TIM1 channel 3 on DMA1 channel 6 /
mbed_official	441:d2c15dda23c1	189	#define HAL_DMA1_CH6_TIM3_CH1 (uint32_t) (DMA1_CHANNEL6_RMP \| DMA1_CSELR_CH6_TIM3_CH1) /!< Remap TIM3 channel 1 on DMA1 channel 6 /
mbed_official	441:d2c15dda23c1	190	#define HAL_DMA1_CH6_TIM3_TRIG (uint32_t) (DMA1_CHANNEL6_RMP \| DMA1_CSELR_CH6_TIM3_TRIG) /!< Remap TIM3 Trig on DMA1 channel 6 /
mbed_official	441:d2c15dda23c1	191	#define HAL_DMA1_CH6_TIM16_CH1 (uint32_t) (DMA1_CHANNEL6_RMP \| DMA1_CSELR_CH6_TIM16_CH1) /!< Remap TIM16 channel 1 on DMA1 channel 6 /
mbed_official	441:d2c15dda23c1	192	#define HAL_DMA1_CH6_TIM16_UP (uint32_t) (DMA1_CHANNEL6_RMP \| DMA1_CSELR_CH6_TIM16_UP) /!< Remap TIM16 up on DMA1 channel 6 /
mbed_official	441:d2c15dda23c1	193	#define HAL_DMA1_CH6_USART1_RX (uint32_t) (DMA1_CHANNEL6_RMP \| DMA1_CSELR_CH6_USART1_RX) /!< Remap USART1 Rx on DMA1 channel 6 /
mbed_official	441:d2c15dda23c1	194	#define HAL_DMA1_CH6_USART2_RX (uint32_t) (DMA1_CHANNEL6_RMP \| DMA1_CSELR_CH6_USART2_RX) /!< Remap USART2 Rx on DMA1 channel 6 /
mbed_official	441:d2c15dda23c1	195	#define HAL_DMA1_CH6_USART3_RX (uint32_t) (DMA1_CHANNEL6_RMP \| DMA1_CSELR_CH6_USART3_RX) /!< Remap USART3 Rx on DMA1 channel 6 /
mbed_official	441:d2c15dda23c1	196	#define HAL_DMA1_CH6_USART4_RX (uint32_t) (DMA1_CHANNEL6_RMP \| DMA1_CSELR_CH6_USART4_RX) /!< Remap USART4 Rx on DMA1 channel 6 /
mbed_official	441:d2c15dda23c1	197	#define HAL_DMA1_CH6_USART5_RX (uint32_t) (DMA1_CHANNEL6_RMP \| DMA1_CSELR_CH6_USART5_RX) /!< Remap USART5 Rx on DMA1 channel 6 /
mbed_official	441:d2c15dda23c1	198	#define HAL_DMA1_CH6_USART6_RX (uint32_t) (DMA1_CHANNEL6_RMP \| DMA1_CSELR_CH6_USART6_RX) /!< Remap USART6 Rx on DMA1 channel 6 /
mbed_official	441:d2c15dda23c1	199	#define HAL_DMA1_CH6_USART7_RX (uint32_t) (DMA1_CHANNEL6_RMP \| DMA1_CSELR_CH6_USART7_RX) /!< Remap USART7 Rx on DMA1 channel 6 /
mbed_official	441:d2c15dda23c1	200	#define HAL_DMA1_CH6_USART8_RX (uint32_t) (DMA1_CHANNEL6_RMP \| DMA1_CSELR_CH6_USART8_RX) /!< Remap USART8 Rx on DMA1 channel 6 /
mbed_official	340:28d1f895c6fe	201	/* DMA1 - Channel 7 */
mbed_official	441:d2c15dda23c1	202	#define HAL_DMA1_CH7_DEFAULT (uint32_t) (DMA1_CHANNEL7_RMP \| DMA1_CSELR_DEFAULT) /!< Default remap position for DMA1 /
mbed_official	441:d2c15dda23c1	203	#define HAL_DMA1_CH7_I2C1_RX (uint32_t) (DMA1_CHANNEL7_RMP \| DMA1_CSELR_CH7_I2C1_RX) /!< Remap I2C1 Rx on DMA1 channel 7 /
mbed_official	441:d2c15dda23c1	204	#define HAL_DMA1_CH7_SPI2_TX (uint32_t) (DMA1_CHANNEL7_RMP \| DMA1_CSELR_CH7_SPI2_TX) /!< Remap SPI2 Tx on DMA1 channel 7 /
mbed_official	441:d2c15dda23c1	205	#define HAL_DMA1_CH7_TIM2_CH2 (uint32_t) (DMA1_CHANNEL7_RMP \| DMA1_CSELR_CH7_TIM2_CH2) /!< Remap TIM2 channel 2 on DMA1 channel 7 /
mbed_official	441:d2c15dda23c1	206	#define HAL_DMA1_CH7_TIM2_CH4 (uint32_t) (DMA1_CHANNEL7_RMP \| DMA1_CSELR_CH7_TIM2_CH4) /!< Remap TIM2 channel 4 on DMA1 channel 7 /
mbed_official	441:d2c15dda23c1	207	#define HAL_DMA1_CH7_TIM17_CH1 (uint32_t) (DMA1_CHANNEL7_RMP \| DMA1_CSELR_CH7_TIM17_CH1) /!< Remap TIM17 channel 1 on DMA1 channel 7 /
mbed_official	441:d2c15dda23c1	208	#define HAL_DMA1_CH7_TIM17_UP (uint32_t) (DMA1_CHANNEL7_RMP \| DMA1_CSELR_CH7_TIM17_UP) /!< Remap TIM17 up on DMA1 channel 7 /
mbed_official	441:d2c15dda23c1	209	#define HAL_DMA1_CH7_USART1_TX (uint32_t) (DMA1_CHANNEL7_RMP \| DMA1_CSELR_CH7_USART1_TX) /!< Remap USART1 Tx on DMA1 channel 7 /
mbed_official	441:d2c15dda23c1	210	#define HAL_DMA1_CH7_USART2_TX (uint32_t) (DMA1_CHANNEL7_RMP \| DMA1_CSELR_CH7_USART2_TX) /!< Remap USART2 Tx on DMA1 channel 7 /
mbed_official	441:d2c15dda23c1	211	#define HAL_DMA1_CH7_USART3_TX (uint32_t) (DMA1_CHANNEL7_RMP \| DMA1_CSELR_CH7_USART3_TX) /!< Remap USART3 Tx on DMA1 channel 7 /
mbed_official	441:d2c15dda23c1	212	#define HAL_DMA1_CH7_USART4_TX (uint32_t) (DMA1_CHANNEL7_RMP \| DMA1_CSELR_CH7_USART4_TX) /!< Remap USART4 Tx on DMA1 channel 7 /
mbed_official	441:d2c15dda23c1	213	#define HAL_DMA1_CH7_USART5_TX (uint32_t) (DMA1_CHANNEL7_RMP \| DMA1_CSELR_CH7_USART5_TX) /!< Remap USART5 Tx on DMA1 channel 7 /
mbed_official	441:d2c15dda23c1	214	#define HAL_DMA1_CH7_USART6_TX (uint32_t) (DMA1_CHANNEL7_RMP \| DMA1_CSELR_CH7_USART6_TX) /!< Remap USART6 Tx on DMA1 channel 7 /
mbed_official	441:d2c15dda23c1	215	#define HAL_DMA1_CH7_USART7_TX (uint32_t) (DMA1_CHANNEL7_RMP \| DMA1_CSELR_CH7_USART7_TX) /!< Remap USART7 Tx on DMA1 channel 7 /
mbed_official	441:d2c15dda23c1	216	#define HAL_DMA1_CH7_USART8_TX (uint32_t) (DMA1_CHANNEL7_RMP \| DMA1_CSELR_CH7_USART8_TX) /!< Remap USART8 Tx on DMA1 channel 7 /
mbed_official	340:28d1f895c6fe	217
mbed_official	340:28d1f895c6fe	218	/**************** DMA2 remap bit field definition******************/
mbed_official	340:28d1f895c6fe	219	/* DMA2 - Channel 1 */
mbed_official	441:d2c15dda23c1	220	#define HAL_DMA2_CH1_DEFAULT (uint32_t) (DMA2_CHANNEL1_RMP \| DMA2_CSELR_DEFAULT) /!< Default remap position for DMA2 /
mbed_official	441:d2c15dda23c1	221	#define HAL_DMA2_CH1_I2C2_TX (uint32_t) (DMA2_CHANNEL1_RMP \| DMA2_CSELR_CH1_I2C2_TX) /!< Remap I2C2 TX on DMA2 channel 1 /
mbed_official	441:d2c15dda23c1	222	#define HAL_DMA2_CH1_USART1_TX (uint32_t) (DMA2_CHANNEL1_RMP \| DMA2_CSELR_CH1_USART1_TX) /!< Remap USART1 Tx on DMA2 channel 1 /
mbed_official	441:d2c15dda23c1	223	#define HAL_DMA2_CH1_USART2_TX (uint32_t) (DMA2_CHANNEL1_RMP \| DMA2_CSELR_CH1_USART2_TX) /!< Remap USART2 Tx on DMA2 channel 1 /
mbed_official	441:d2c15dda23c1	224	#define HAL_DMA2_CH1_USART3_TX (uint32_t) (DMA2_CHANNEL1_RMP \| DMA2_CSELR_CH1_USART3_TX) /!< Remap USART3 Tx on DMA2 channel 1 /
mbed_official	441:d2c15dda23c1	225	#define HAL_DMA2_CH1_USART4_TX (uint32_t) (DMA2_CHANNEL1_RMP \| DMA2_CSELR_CH1_USART4_TX) /!< Remap USART4 Tx on DMA2 channel 1 /
mbed_official	441:d2c15dda23c1	226	#define HAL_DMA2_CH1_USART5_TX (uint32_t) (DMA2_CHANNEL1_RMP \| DMA2_CSELR_CH1_USART5_TX) /!< Remap USART5 Tx on DMA2 channel 1 /
mbed_official	441:d2c15dda23c1	227	#define HAL_DMA2_CH1_USART6_TX (uint32_t) (DMA2_CHANNEL1_RMP \| DMA2_CSELR_CH1_USART6_TX) /!< Remap USART6 Tx on DMA2 channel 1 /
mbed_official	441:d2c15dda23c1	228	#define HAL_DMA2_CH1_USART7_TX (uint32_t) (DMA2_CHANNEL1_RMP \| DMA2_CSELR_CH1_USART7_TX) /!< Remap USART7 Tx on DMA2 channel 1 /
mbed_official	441:d2c15dda23c1	229	#define HAL_DMA2_CH1_USART8_TX (uint32_t) (DMA2_CHANNEL1_RMP \| DMA2_CSELR_CH1_USART8_TX) /!< Remap USART8 Tx on DMA2 channel 1 /
mbed_official	340:28d1f895c6fe	230	/* DMA2 - Channel 2 */
mbed_official	441:d2c15dda23c1	231	#define HAL_DMA2_CH2_DEFAULT (uint32_t) (DMA2_CHANNEL2_RMP \| DMA2_CSELR_DEFAULT) /!< Default remap position for DMA2 /
mbed_official	441:d2c15dda23c1	232	#define HAL_DMA2_CH2_I2C2_RX (uint32_t) (DMA2_CHANNEL2_RMP \| DMA2_CSELR_CH2_I2C2_RX) /!< Remap I2C2 Rx on DMA2 channel 2 /
mbed_official	441:d2c15dda23c1	233	#define HAL_DMA2_CH2_USART1_RX (uint32_t) (DMA2_CHANNEL2_RMP \| DMA2_CSELR_CH2_USART1_RX) /!< Remap USART1 Rx on DMA2 channel 2 /
mbed_official	441:d2c15dda23c1	234	#define HAL_DMA2_CH2_USART2_RX (uint32_t) (DMA2_CHANNEL2_RMP \| DMA2_CSELR_CH2_USART2_RX) /!< Remap USART2 Rx on DMA2 channel 2 /
mbed_official	441:d2c15dda23c1	235	#define HAL_DMA2_CH2_USART3_RX (uint32_t) (DMA2_CHANNEL2_RMP \| DMA2_CSELR_CH2_USART3_RX) /!< Remap USART3 Rx on DMA2 channel 2 /
mbed_official	441:d2c15dda23c1	236	#define HAL_DMA2_CH2_USART4_RX (uint32_t) (DMA2_CHANNEL2_RMP \| DMA2_CSELR_CH2_USART4_RX) /!< Remap USART4 Rx on DMA2 channel 2 /
mbed_official	441:d2c15dda23c1	237	#define HAL_DMA2_CH2_USART5_RX (uint32_t) (DMA2_CHANNEL2_RMP \| DMA2_CSELR_CH2_USART5_RX) /!< Remap USART5 Rx on DMA2 channel 2 /
mbed_official	441:d2c15dda23c1	238	#define HAL_DMA2_CH2_USART6_RX (uint32_t) (DMA2_CHANNEL2_RMP \| DMA2_CSELR_CH2_USART6_RX) /!< Remap USART6 Rx on DMA2 channel 2 /
mbed_official	441:d2c15dda23c1	239	#define HAL_DMA2_CH2_USART7_RX (uint32_t) (DMA2_CHANNEL2_RMP \| DMA2_CSELR_CH2_USART7_RX) /!< Remap USART7 Rx on DMA2 channel 2 /
mbed_official	441:d2c15dda23c1	240	#define HAL_DMA2_CH2_USART8_RX (uint32_t) (DMA2_CHANNEL2_RMP \| DMA2_CSELR_CH2_USART8_RX) /!< Remap USART8 Rx on DMA2 channel 2 /
mbed_official	340:28d1f895c6fe	241	/* DMA2 - Channel 3 */
mbed_official	441:d2c15dda23c1	242	#define HAL_DMA2_CH3_DEFAULT (uint32_t) (DMA2_CHANNEL3_RMP \| DMA2_CSELR_DEFAULT) /!< Default remap position for DMA2 /
mbed_official	441:d2c15dda23c1	243	#define HAL_DMA2_CH3_TIM6_UP (uint32_t) (DMA2_CHANNEL3_RMP \| DMA2_CSELR_CH3_TIM6_UP) /!< Remap TIM6 up on DMA2 channel 3 /
mbed_official	441:d2c15dda23c1	244	#define HAL_DMA2_CH3_DAC_CH1 (uint32_t) (DMA2_CHANNEL3_RMP \| DMA2_CSELR_CH3_DAC_CH1) /!< Remap DAC channel 1 on DMA2 channel 3 /
mbed_official	441:d2c15dda23c1	245	#define HAL_DMA2_CH3_SPI1_RX (uint32_t) (DMA2_CHANNEL3_RMP \| DMA2_CSELR_CH3_SPI1_RX) /!< Remap SPI1 Rx on DMA2 channel 3 /
mbed_official	441:d2c15dda23c1	246	#define HAL_DMA2_CH3_USART1_RX (uint32_t) (DMA2_CHANNEL3_RMP \| DMA2_CSELR_CH3_USART1_RX) /!< Remap USART1 Rx on DMA2 channel 3 /
mbed_official	441:d2c15dda23c1	247	#define HAL_DMA2_CH3_USART2_RX (uint32_t) (DMA2_CHANNEL3_RMP \| DMA2_CSELR_CH3_USART2_RX) /!< Remap USART2 Rx on DMA2 channel 3 /
mbed_official	441:d2c15dda23c1	248	#define HAL_DMA2_CH3_USART3_RX (uint32_t) (DMA2_CHANNEL3_RMP \| DMA2_CSELR_CH3_USART3_RX) /!< Remap USART3 Rx on DMA2 channel 3 /
mbed_official	441:d2c15dda23c1	249	#define HAL_DMA2_CH3_USART4_RX (uint32_t) (DMA2_CHANNEL3_RMP \| DMA2_CSELR_CH3_USART4_RX) /!< Remap USART4 Rx on DMA2 channel 3 /
mbed_official	441:d2c15dda23c1	250	#define HAL_DMA2_CH3_USART5_RX (uint32_t) (DMA2_CHANNEL3_RMP \| DMA2_CSELR_CH3_USART5_RX) /!< Remap USART5 Rx on DMA2 channel 3 /
mbed_official	441:d2c15dda23c1	251	#define HAL_DMA2_CH3_USART6_RX (uint32_t) (DMA2_CHANNEL3_RMP \| DMA2_CSELR_CH3_USART6_RX) /!< Remap USART6 Rx on DMA2 channel 3 /
mbed_official	441:d2c15dda23c1	252	#define HAL_DMA2_CH3_USART7_RX (uint32_t) (DMA2_CHANNEL3_RMP \| DMA2_CSELR_CH3_USART7_RX) /!< Remap USART7 Rx on DMA2 channel 3 /
mbed_official	441:d2c15dda23c1	253	#define HAL_DMA2_CH3_USART8_RX (uint32_t) (DMA2_CHANNEL3_RMP \| DMA2_CSELR_CH3_USART8_RX) /!< Remap USART8 Rx on DMA2 channel 3 /
mbed_official	340:28d1f895c6fe	254	/* DMA2 - Channel 4 */
mbed_official	441:d2c15dda23c1	255	#define HAL_DMA2_CH4_DEFAULT (uint32_t) (DMA2_CHANNEL4_RMP \| DMA2_CSELR_DEFAULT) /!< Default remap position for DMA2 /
mbed_official	441:d2c15dda23c1	256	#define HAL_DMA2_CH4_TIM7_UP (uint32_t) (DMA2_CHANNEL4_RMP \| DMA2_CSELR_CH4_TIM7_UP) /!< Remap TIM7 up on DMA2 channel 4 /
mbed_official	441:d2c15dda23c1	257	#define HAL_DMA2_CH4_DAC_CH2 (uint32_t) (DMA2_CHANNEL4_RMP \| DMA2_CSELR_CH4_DAC_CH2) /!< Remap DAC channel 2 on DMA2 channel 4 /
mbed_official	441:d2c15dda23c1	258	#define HAL_DMA2_CH4_SPI1_TX (uint32_t) (DMA2_CHANNEL4_RMP \| DMA2_CSELR_CH4_SPI1_TX) /!< Remap SPI1 Tx on DMA2 channel 4 /
mbed_official	441:d2c15dda23c1	259	#define HAL_DMA2_CH4_USART1_TX (uint32_t) (DMA2_CHANNEL4_RMP \| DMA2_CSELR_CH4_USART1_TX) /!< Remap USART1 Tx on DMA2 channel 4 /
mbed_official	441:d2c15dda23c1	260	#define HAL_DMA2_CH4_USART2_TX (uint32_t) (DMA2_CHANNEL4_RMP \| DMA2_CSELR_CH4_USART2_TX) /!< Remap USART2 Tx on DMA2 channel 4 /
mbed_official	441:d2c15dda23c1	261	#define HAL_DMA2_CH4_USART3_TX (uint32_t) (DMA2_CHANNEL4_RMP \| DMA2_CSELR_CH4_USART3_TX) /!< Remap USART3 Tx on DMA2 channel 4 /
mbed_official	441:d2c15dda23c1	262	#define HAL_DMA2_CH4_USART4_TX (uint32_t) (DMA2_CHANNEL4_RMP \| DMA2_CSELR_CH4_USART4_TX) /!< Remap USART4 Tx on DMA2 channel 4 /
mbed_official	441:d2c15dda23c1	263	#define HAL_DMA2_CH4_USART5_TX (uint32_t) (DMA2_CHANNEL4_RMP \| DMA2_CSELR_CH4_USART5_TX) /!< Remap USART5 Tx on DMA2 channel 4 /
mbed_official	441:d2c15dda23c1	264	#define HAL_DMA2_CH4_USART6_TX (uint32_t) (DMA2_CHANNEL4_RMP \| DMA2_CSELR_CH4_USART6_TX) /!< Remap USART6 Tx on DMA2 channel 4 /
mbed_official	441:d2c15dda23c1	265	#define HAL_DMA2_CH4_USART7_TX (uint32_t) (DMA2_CHANNEL4_RMP \| DMA2_CSELR_CH4_USART7_TX) /!< Remap USART7 Tx on DMA2 channel 4 /
mbed_official	441:d2c15dda23c1	266	#define HAL_DMA2_CH4_USART8_TX (uint32_t) (DMA2_CHANNEL4_RMP \| DMA2_CSELR_CH4_USART8_TX) /!< Remap USART8 Tx on DMA2 channel 4 /
mbed_official	340:28d1f895c6fe	267	/* DMA2 - Channel 5 */
mbed_official	441:d2c15dda23c1	268	#define HAL_DMA2_CH5_DEFAULT (uint32_t) (DMA2_CHANNEL5_RMP \| DMA2_CSELR_DEFAULT) /!< Default remap position for DMA2 /
mbed_official	441:d2c15dda23c1	269	#define HAL_DMA2_CH5_ADC (uint32_t) (DMA2_CHANNEL5_RMP \| DMA2_CSELR_CH5_ADC) /!< Remap ADC on DMA2 channel 5 /
mbed_official	441:d2c15dda23c1	270	#define HAL_DMA2_CH5_USART1_TX (uint32_t) (DMA2_CHANNEL5_RMP \| DMA2_CSELR_CH5_USART1_TX) /!< Remap USART1 Tx on DMA2 channel 5 /
mbed_official	441:d2c15dda23c1	271	#define HAL_DMA2_CH5_USART2_TX (uint32_t) (DMA2_CHANNEL5_RMP \| DMA2_CSELR_CH5_USART2_TX) /!< Remap USART2 Tx on DMA2 channel 5 /
mbed_official	441:d2c15dda23c1	272	#define HAL_DMA2_CH5_USART3_TX (uint32_t) (DMA2_CHANNEL5_RMP \| DMA2_CSELR_CH5_USART3_TX) /!< Remap USART3 Tx on DMA2 channel 5 /
mbed_official	441:d2c15dda23c1	273	#define HAL_DMA2_CH5_USART4_TX (uint32_t) (DMA2_CHANNEL5_RMP \| DMA2_CSELR_CH5_USART4_TX) /!< Remap USART4 Tx on DMA2 channel 5 /
mbed_official	441:d2c15dda23c1	274	#define HAL_DMA2_CH5_USART5_TX (uint32_t) (DMA2_CHANNEL5_RMP \| DMA2_CSELR_CH5_USART5_TX) /!< Remap USART5 Tx on DMA2 channel 5 /
mbed_official	441:d2c15dda23c1	275	#define HAL_DMA2_CH5_USART6_TX (uint32_t) (DMA2_CHANNEL5_RMP \| DMA2_CSELR_CH5_USART6_TX) /!< Remap USART6 Tx on DMA2 channel 5 /
mbed_official	441:d2c15dda23c1	276	#define HAL_DMA2_CH5_USART7_TX (uint32_t) (DMA2_CHANNEL5_RMP \| DMA2_CSELR_CH5_USART7_TX) /!< Remap USART7 Tx on DMA2 channel 5 /
mbed_official	441:d2c15dda23c1	277	#define HAL_DMA2_CH5_USART8_TX (uint32_t) (DMA2_CHANNEL5_RMP \| DMA2_CSELR_CH5_USART8_TX) /!< Remap USART8 Tx on DMA2 channel 5 /
mbed_official	441:d2c15dda23c1	278	#endif /* !defined(STM32F030xC) */
mbed_official	340:28d1f895c6fe	279
mbed_official	441:d2c15dda23c1	280	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	441:d2c15dda23c1	281	#define IS_HAL_DMA1_REMAP(REQUEST) (((REQUEST) == HAL_DMA1_CH1_DEFAULT) \|\|\
mbed_official	340:28d1f895c6fe	282	((REQUEST) == HAL_DMA1_CH1_ADC) \|\|\
mbed_official	340:28d1f895c6fe	283	((REQUEST) == HAL_DMA1_CH1_TIM17_CH1) \|\|\
mbed_official	340:28d1f895c6fe	284	((REQUEST) == HAL_DMA1_CH1_TIM17_UP) \|\|\
mbed_official	340:28d1f895c6fe	285	((REQUEST) == HAL_DMA1_CH1_USART1_RX) \|\|\
mbed_official	340:28d1f895c6fe	286	((REQUEST) == HAL_DMA1_CH1_USART2_RX) \|\|\
mbed_official	340:28d1f895c6fe	287	((REQUEST) == HAL_DMA1_CH1_USART3_RX) \|\|\
mbed_official	340:28d1f895c6fe	288	((REQUEST) == HAL_DMA1_CH1_USART4_RX) \|\|\
mbed_official	340:28d1f895c6fe	289	((REQUEST) == HAL_DMA1_CH1_USART5_RX) \|\|\
mbed_official	340:28d1f895c6fe	290	((REQUEST) == HAL_DMA1_CH1_USART6_RX) \|\|\
mbed_official	340:28d1f895c6fe	291	((REQUEST) == HAL_DMA1_CH1_USART7_RX) \|\|\
mbed_official	340:28d1f895c6fe	292	((REQUEST) == HAL_DMA1_CH1_USART8_RX) \|\|\
mbed_official	340:28d1f895c6fe	293	((REQUEST) == HAL_DMA1_CH2_DEFAULT) \|\|\
mbed_official	340:28d1f895c6fe	294	((REQUEST) == HAL_DMA1_CH2_ADC) \|\|\
mbed_official	340:28d1f895c6fe	295	((REQUEST) == HAL_DMA1_CH2_I2C1_TX) \|\|\
mbed_official	340:28d1f895c6fe	296	((REQUEST) == HAL_DMA1_CH2_SPI1_RX) \|\|\
mbed_official	340:28d1f895c6fe	297	((REQUEST) == HAL_DMA1_CH2_TIM1_CH1) \|\|\
mbed_official	340:28d1f895c6fe	298	((REQUEST) == HAL_DMA1_CH2_I2C1_TX) \|\|\
mbed_official	340:28d1f895c6fe	299	((REQUEST) == HAL_DMA1_CH2_TIM17_CH1) \|\|\
mbed_official	340:28d1f895c6fe	300	((REQUEST) == HAL_DMA1_CH2_TIM17_UP) \|\|\
mbed_official	340:28d1f895c6fe	301	((REQUEST) == HAL_DMA1_CH2_USART1_TX) \|\|\
mbed_official	340:28d1f895c6fe	302	((REQUEST) == HAL_DMA1_CH2_USART2_TX) \|\|\
mbed_official	340:28d1f895c6fe	303	((REQUEST) == HAL_DMA1_CH2_USART3_TX) \|\|\
mbed_official	340:28d1f895c6fe	304	((REQUEST) == HAL_DMA1_CH2_USART4_TX) \|\|\
mbed_official	340:28d1f895c6fe	305	((REQUEST) == HAL_DMA1_CH2_USART5_TX) \|\|\
mbed_official	340:28d1f895c6fe	306	((REQUEST) == HAL_DMA1_CH2_USART6_TX) \|\|\
mbed_official	340:28d1f895c6fe	307	((REQUEST) == HAL_DMA1_CH2_USART7_TX) \|\|\
mbed_official	340:28d1f895c6fe	308	((REQUEST) == HAL_DMA1_CH2_USART8_TX) \|\|\
mbed_official	340:28d1f895c6fe	309	((REQUEST) == HAL_DMA1_CH3_DEFAULT) \|\|\
mbed_official	340:28d1f895c6fe	310	((REQUEST) == HAL_DMA1_CH3_TIM6_UP) \|\|\
mbed_official	340:28d1f895c6fe	311	((REQUEST) == HAL_DMA1_CH3_DAC_CH1) \|\|\
mbed_official	340:28d1f895c6fe	312	((REQUEST) == HAL_DMA1_CH3_I2C1_RX) \|\|\
mbed_official	340:28d1f895c6fe	313	((REQUEST) == HAL_DMA1_CH3_SPI1_TX) \|\|\
mbed_official	340:28d1f895c6fe	314	((REQUEST) == HAL_DMA1_CH3_TIM1_CH2) \|\|\
mbed_official	340:28d1f895c6fe	315	((REQUEST) == HAL_DMA1_CH3_TIM2_CH2) \|\|\
mbed_official	340:28d1f895c6fe	316	((REQUEST) == HAL_DMA1_CH3_TIM16_CH1) \|\|\
mbed_official	340:28d1f895c6fe	317	((REQUEST) == HAL_DMA1_CH3_TIM16_UP) \|\|\
mbed_official	340:28d1f895c6fe	318	((REQUEST) == HAL_DMA1_CH3_USART1_RX) \|\|\
mbed_official	340:28d1f895c6fe	319	((REQUEST) == HAL_DMA1_CH3_USART2_RX) \|\|\
mbed_official	340:28d1f895c6fe	320	((REQUEST) == HAL_DMA1_CH3_USART3_RX) \|\|\
mbed_official	340:28d1f895c6fe	321	((REQUEST) == HAL_DMA1_CH3_USART4_RX) \|\|\
mbed_official	340:28d1f895c6fe	322	((REQUEST) == HAL_DMA1_CH3_USART5_RX) \|\|\
mbed_official	340:28d1f895c6fe	323	((REQUEST) == HAL_DMA1_CH3_USART6_RX) \|\|\
mbed_official	340:28d1f895c6fe	324	((REQUEST) == HAL_DMA1_CH3_USART7_RX) \|\|\
mbed_official	340:28d1f895c6fe	325	((REQUEST) == HAL_DMA1_CH3_USART8_RX) \|\|\
mbed_official	340:28d1f895c6fe	326	((REQUEST) == HAL_DMA1_CH4_DEFAULT) \|\|\
mbed_official	340:28d1f895c6fe	327	((REQUEST) == HAL_DMA1_CH4_TIM7_UP) \|\|\
mbed_official	340:28d1f895c6fe	328	((REQUEST) == HAL_DMA1_CH4_DAC_CH2) \|\|\
mbed_official	340:28d1f895c6fe	329	((REQUEST) == HAL_DMA1_CH4_I2C2_TX) \|\|\
mbed_official	340:28d1f895c6fe	330	((REQUEST) == HAL_DMA1_CH4_SPI2_RX) \|\|\
mbed_official	340:28d1f895c6fe	331	((REQUEST) == HAL_DMA1_CH4_TIM2_CH4) \|\|\
mbed_official	340:28d1f895c6fe	332	((REQUEST) == HAL_DMA1_CH4_TIM3_CH1) \|\|\
mbed_official	340:28d1f895c6fe	333	((REQUEST) == HAL_DMA1_CH4_TIM3_TRIG) \|\|\
mbed_official	340:28d1f895c6fe	334	((REQUEST) == HAL_DMA1_CH4_TIM16_CH1) \|\|\
mbed_official	340:28d1f895c6fe	335	((REQUEST) == HAL_DMA1_CH4_TIM16_UP) \|\|\
mbed_official	340:28d1f895c6fe	336	((REQUEST) == HAL_DMA1_CH4_USART1_TX) \|\|\
mbed_official	340:28d1f895c6fe	337	((REQUEST) == HAL_DMA1_CH4_USART2_TX) \|\|\
mbed_official	340:28d1f895c6fe	338	((REQUEST) == HAL_DMA1_CH4_USART3_TX) \|\|\
mbed_official	340:28d1f895c6fe	339	((REQUEST) == HAL_DMA1_CH4_USART4_TX) \|\|\
mbed_official	340:28d1f895c6fe	340	((REQUEST) == HAL_DMA1_CH4_USART5_TX) \|\|\
mbed_official	340:28d1f895c6fe	341	((REQUEST) == HAL_DMA1_CH4_USART6_TX) \|\|\
mbed_official	340:28d1f895c6fe	342	((REQUEST) == HAL_DMA1_CH4_USART7_TX) \|\|\
mbed_official	340:28d1f895c6fe	343	((REQUEST) == HAL_DMA1_CH4_USART8_TX) \|\|\
mbed_official	340:28d1f895c6fe	344	((REQUEST) == HAL_DMA1_CH5_DEFAULT) \|\|\
mbed_official	340:28d1f895c6fe	345	((REQUEST) == HAL_DMA1_CH5_I2C2_RX) \|\|\
mbed_official	340:28d1f895c6fe	346	((REQUEST) == HAL_DMA1_CH5_SPI2_TX) \|\|\
mbed_official	340:28d1f895c6fe	347	((REQUEST) == HAL_DMA1_CH5_TIM1_CH3) \|\|\
mbed_official	340:28d1f895c6fe	348	((REQUEST) == HAL_DMA1_CH5_USART1_RX) \|\|\
mbed_official	340:28d1f895c6fe	349	((REQUEST) == HAL_DMA1_CH5_USART2_RX) \|\|\
mbed_official	340:28d1f895c6fe	350	((REQUEST) == HAL_DMA1_CH5_USART3_RX) \|\|\
mbed_official	340:28d1f895c6fe	351	((REQUEST) == HAL_DMA1_CH5_USART4_RX) \|\|\
mbed_official	340:28d1f895c6fe	352	((REQUEST) == HAL_DMA1_CH5_USART5_RX) \|\|\
mbed_official	340:28d1f895c6fe	353	((REQUEST) == HAL_DMA1_CH5_USART6_RX) \|\|\
mbed_official	340:28d1f895c6fe	354	((REQUEST) == HAL_DMA1_CH5_USART7_RX) \|\|\
mbed_official	340:28d1f895c6fe	355	((REQUEST) == HAL_DMA1_CH5_USART8_RX) \|\|\
mbed_official	340:28d1f895c6fe	356	((REQUEST) == HAL_DMA1_CH6_DEFAULT) \|\|\
mbed_official	340:28d1f895c6fe	357	((REQUEST) == HAL_DMA1_CH6_I2C1_TX) \|\|\
mbed_official	340:28d1f895c6fe	358	((REQUEST) == HAL_DMA1_CH6_SPI2_RX) \|\|\
mbed_official	340:28d1f895c6fe	359	((REQUEST) == HAL_DMA1_CH6_TIM1_CH1) \|\|\
mbed_official	340:28d1f895c6fe	360	((REQUEST) == HAL_DMA1_CH6_TIM1_CH2) \|\|\
mbed_official	340:28d1f895c6fe	361	((REQUEST) == HAL_DMA1_CH6_TIM1_CH3) \|\|\
mbed_official	340:28d1f895c6fe	362	((REQUEST) == HAL_DMA1_CH6_TIM3_CH1) \|\|\
mbed_official	340:28d1f895c6fe	363	((REQUEST) == HAL_DMA1_CH6_TIM3_TRIG) \|\|\
mbed_official	340:28d1f895c6fe	364	((REQUEST) == HAL_DMA1_CH6_TIM16_CH1) \|\|\
mbed_official	340:28d1f895c6fe	365	((REQUEST) == HAL_DMA1_CH6_TIM16_UP) \|\|\
mbed_official	340:28d1f895c6fe	366	((REQUEST) == HAL_DMA1_CH6_USART1_RX) \|\|\
mbed_official	340:28d1f895c6fe	367	((REQUEST) == HAL_DMA1_CH6_USART2_RX) \|\|\
mbed_official	340:28d1f895c6fe	368	((REQUEST) == HAL_DMA1_CH6_USART3_RX) \|\|\
mbed_official	340:28d1f895c6fe	369	((REQUEST) == HAL_DMA1_CH6_USART4_RX) \|\|\
mbed_official	340:28d1f895c6fe	370	((REQUEST) == HAL_DMA1_CH6_USART5_RX) \|\|\
mbed_official	340:28d1f895c6fe	371	((REQUEST) == HAL_DMA1_CH6_USART6_RX) \|\|\
mbed_official	340:28d1f895c6fe	372	((REQUEST) == HAL_DMA1_CH6_USART7_RX) \|\|\
mbed_official	340:28d1f895c6fe	373	((REQUEST) == HAL_DMA1_CH6_USART8_RX) \|\|\
mbed_official	340:28d1f895c6fe	374	((REQUEST) == HAL_DMA1_CH7_DEFAULT) \|\|\
mbed_official	340:28d1f895c6fe	375	((REQUEST) == HAL_DMA1_CH7_I2C1_RX) \|\|\
mbed_official	340:28d1f895c6fe	376	((REQUEST) == HAL_DMA1_CH7_SPI2_TX) \|\|\
mbed_official	340:28d1f895c6fe	377	((REQUEST) == HAL_DMA1_CH7_TIM2_CH2) \|\|\
mbed_official	340:28d1f895c6fe	378	((REQUEST) == HAL_DMA1_CH7_TIM2_CH4) \|\|\
mbed_official	340:28d1f895c6fe	379	((REQUEST) == HAL_DMA1_CH7_TIM17_CH1) \|\|\
mbed_official	340:28d1f895c6fe	380	((REQUEST) == HAL_DMA1_CH7_TIM17_UP) \|\|\
mbed_official	340:28d1f895c6fe	381	((REQUEST) == HAL_DMA1_CH7_USART1_TX) \|\|\
mbed_official	340:28d1f895c6fe	382	((REQUEST) == HAL_DMA1_CH7_USART2_TX) \|\|\
mbed_official	340:28d1f895c6fe	383	((REQUEST) == HAL_DMA1_CH7_USART3_TX) \|\|\
mbed_official	340:28d1f895c6fe	384	((REQUEST) == HAL_DMA1_CH7_USART4_TX) \|\|\
mbed_official	340:28d1f895c6fe	385	((REQUEST) == HAL_DMA1_CH7_USART5_TX) \|\|\
mbed_official	340:28d1f895c6fe	386	((REQUEST) == HAL_DMA1_CH7_USART6_TX) \|\|\
mbed_official	340:28d1f895c6fe	387	((REQUEST) == HAL_DMA1_CH7_USART7_TX) \|\|\
mbed_official	340:28d1f895c6fe	388	((REQUEST) == HAL_DMA1_CH7_USART8_TX))
mbed_official	340:28d1f895c6fe	389
mbed_official	340:28d1f895c6fe	390	#define IS_HAL_DMA2_REMAP(REQUEST) (((REQUEST) == HAL_DMA2_CH1_DEFAULT) \|\|\
mbed_official	340:28d1f895c6fe	391	((REQUEST) == HAL_DMA2_CH1_I2C2_TX) \|\|\
mbed_official	340:28d1f895c6fe	392	((REQUEST) == HAL_DMA2_CH1_USART1_TX) \|\|\
mbed_official	340:28d1f895c6fe	393	((REQUEST) == HAL_DMA2_CH1_USART2_TX) \|\|\
mbed_official	340:28d1f895c6fe	394	((REQUEST) == HAL_DMA2_CH1_USART3_TX) \|\|\
mbed_official	340:28d1f895c6fe	395	((REQUEST) == HAL_DMA2_CH1_USART4_TX) \|\|\
mbed_official	340:28d1f895c6fe	396	((REQUEST) == HAL_DMA2_CH1_USART5_TX) \|\|\
mbed_official	340:28d1f895c6fe	397	((REQUEST) == HAL_DMA2_CH1_USART6_TX) \|\|\
mbed_official	340:28d1f895c6fe	398	((REQUEST) == HAL_DMA2_CH1_USART7_TX) \|\|\
mbed_official	340:28d1f895c6fe	399	((REQUEST) == HAL_DMA2_CH1_USART8_TX) \|\|\
mbed_official	340:28d1f895c6fe	400	((REQUEST) == HAL_DMA2_CH2_DEFAULT) \|\|\
mbed_official	340:28d1f895c6fe	401	((REQUEST) == HAL_DMA2_CH2_I2C2_RX) \|\|\
mbed_official	340:28d1f895c6fe	402	((REQUEST) == HAL_DMA2_CH2_USART1_RX) \|\|\
mbed_official	340:28d1f895c6fe	403	((REQUEST) == HAL_DMA2_CH2_USART2_RX) \|\|\
mbed_official	340:28d1f895c6fe	404	((REQUEST) == HAL_DMA2_CH2_USART3_RX) \|\|\
mbed_official	340:28d1f895c6fe	405	((REQUEST) == HAL_DMA2_CH2_USART4_RX) \|\|\
mbed_official	340:28d1f895c6fe	406	((REQUEST) == HAL_DMA2_CH2_USART5_RX) \|\|\
mbed_official	340:28d1f895c6fe	407	((REQUEST) == HAL_DMA2_CH2_USART6_RX) \|\|\
mbed_official	340:28d1f895c6fe	408	((REQUEST) == HAL_DMA2_CH2_USART7_RX) \|\|\
mbed_official	340:28d1f895c6fe	409	((REQUEST) == HAL_DMA2_CH2_USART8_RX) \|\|\
mbed_official	340:28d1f895c6fe	410	((REQUEST) == HAL_DMA2_CH3_DEFAULT) \|\|\
mbed_official	340:28d1f895c6fe	411	((REQUEST) == HAL_DMA2_CH3_TIM6_UP) \|\|\
mbed_official	340:28d1f895c6fe	412	((REQUEST) == HAL_DMA2_CH3_DAC_CH1) \|\|\
mbed_official	340:28d1f895c6fe	413	((REQUEST) == HAL_DMA2_CH3_SPI1_RX) \|\|\
mbed_official	340:28d1f895c6fe	414	((REQUEST) == HAL_DMA2_CH3_USART1_RX) \|\|\
mbed_official	340:28d1f895c6fe	415	((REQUEST) == HAL_DMA2_CH3_USART2_RX) \|\|\
mbed_official	340:28d1f895c6fe	416	((REQUEST) == HAL_DMA2_CH3_USART3_RX) \|\|\
mbed_official	340:28d1f895c6fe	417	((REQUEST) == HAL_DMA2_CH3_USART4_RX) \|\|\
mbed_official	340:28d1f895c6fe	418	((REQUEST) == HAL_DMA2_CH3_USART5_RX) \|\|\
mbed_official	340:28d1f895c6fe	419	((REQUEST) == HAL_DMA2_CH3_USART6_RX) \|\|\
mbed_official	340:28d1f895c6fe	420	((REQUEST) == HAL_DMA2_CH3_USART7_RX) \|\|\
mbed_official	340:28d1f895c6fe	421	((REQUEST) == HAL_DMA2_CH3_USART8_RX) \|\|\
mbed_official	340:28d1f895c6fe	422	((REQUEST) == HAL_DMA2_CH4_DEFAULT) \|\|\
mbed_official	340:28d1f895c6fe	423	((REQUEST) == HAL_DMA2_CH4_TIM7_UP) \|\|\
mbed_official	340:28d1f895c6fe	424	((REQUEST) == HAL_DMA2_CH4_DAC_CH2) \|\|\
mbed_official	340:28d1f895c6fe	425	((REQUEST) == HAL_DMA2_CH4_SPI1_TX) \|\|\
mbed_official	340:28d1f895c6fe	426	((REQUEST) == HAL_DMA2_CH4_USART1_TX) \|\|\
mbed_official	340:28d1f895c6fe	427	((REQUEST) == HAL_DMA2_CH4_USART2_TX) \|\|\
mbed_official	340:28d1f895c6fe	428	((REQUEST) == HAL_DMA2_CH4_USART3_TX) \|\|\
mbed_official	340:28d1f895c6fe	429	((REQUEST) == HAL_DMA2_CH4_USART4_TX) \|\|\
mbed_official	340:28d1f895c6fe	430	((REQUEST) == HAL_DMA2_CH4_USART5_TX) \|\|\
mbed_official	340:28d1f895c6fe	431	((REQUEST) == HAL_DMA2_CH4_USART6_TX) \|\|\
mbed_official	340:28d1f895c6fe	432	((REQUEST) == HAL_DMA2_CH4_USART7_TX) \|\|\
mbed_official	340:28d1f895c6fe	433	((REQUEST) == HAL_DMA2_CH4_USART8_TX) \|\|\
mbed_official	340:28d1f895c6fe	434	((REQUEST) == HAL_DMA2_CH5_DEFAULT) \|\|\
mbed_official	340:28d1f895c6fe	435	((REQUEST) == HAL_DMA2_CH5_ADC) \|\|\
mbed_official	340:28d1f895c6fe	436	((REQUEST) == HAL_DMA2_CH5_USART1_TX) \|\|\
mbed_official	340:28d1f895c6fe	437	((REQUEST) == HAL_DMA2_CH5_USART2_TX) \|\|\
mbed_official	340:28d1f895c6fe	438	((REQUEST) == HAL_DMA2_CH5_USART3_TX) \|\|\
mbed_official	340:28d1f895c6fe	439	((REQUEST) == HAL_DMA2_CH5_USART4_TX) \|\|\
mbed_official	340:28d1f895c6fe	440	((REQUEST) == HAL_DMA2_CH5_USART5_TX) \|\|\
mbed_official	340:28d1f895c6fe	441	((REQUEST) == HAL_DMA2_CH5_USART6_TX) \|\|\
mbed_official	340:28d1f895c6fe	442	((REQUEST) == HAL_DMA2_CH5_USART7_TX) \|\|\
mbed_official	340:28d1f895c6fe	443	((REQUEST) == HAL_DMA2_CH5_USART8_TX ))
mbed_official	441:d2c15dda23c1	444	#endif /* STM32F091xC \|\| STM32F098xx */
mbed_official	441:d2c15dda23c1	445
mbed_official	441:d2c15dda23c1	446	#if defined(STM32F030xC)
mbed_official	441:d2c15dda23c1	447	#define IS_HAL_DMA1_REMAP(REQUEST) (((REQUEST) == HAL_DMA1_CH1_DEFAULT) \|\|\
mbed_official	441:d2c15dda23c1	448	((REQUEST) == HAL_DMA1_CH1_ADC) \|\|\
mbed_official	441:d2c15dda23c1	449	((REQUEST) == HAL_DMA1_CH1_TIM17_CH1) \|\|\
mbed_official	441:d2c15dda23c1	450	((REQUEST) == HAL_DMA1_CH1_TIM17_UP) \|\|\
mbed_official	441:d2c15dda23c1	451	((REQUEST) == HAL_DMA1_CH1_USART1_RX) \|\|\
mbed_official	441:d2c15dda23c1	452	((REQUEST) == HAL_DMA1_CH1_USART2_RX) \|\|\
mbed_official	441:d2c15dda23c1	453	((REQUEST) == HAL_DMA1_CH1_USART3_RX) \|\|\
mbed_official	441:d2c15dda23c1	454	((REQUEST) == HAL_DMA1_CH1_USART4_RX) \|\|\
mbed_official	441:d2c15dda23c1	455	((REQUEST) == HAL_DMA1_CH1_USART5_RX) \|\|\
mbed_official	441:d2c15dda23c1	456	((REQUEST) == HAL_DMA1_CH1_USART6_RX) \|\|\
mbed_official	441:d2c15dda23c1	457	((REQUEST) == HAL_DMA1_CH2_DEFAULT) \|\|\
mbed_official	441:d2c15dda23c1	458	((REQUEST) == HAL_DMA1_CH2_ADC) \|\|\
mbed_official	441:d2c15dda23c1	459	((REQUEST) == HAL_DMA1_CH2_I2C1_TX) \|\|\
mbed_official	441:d2c15dda23c1	460	((REQUEST) == HAL_DMA1_CH2_SPI1_RX) \|\|\
mbed_official	441:d2c15dda23c1	461	((REQUEST) == HAL_DMA1_CH2_TIM1_CH1) \|\|\
mbed_official	441:d2c15dda23c1	462	((REQUEST) == HAL_DMA1_CH2_I2C1_TX) \|\|\
mbed_official	441:d2c15dda23c1	463	((REQUEST) == HAL_DMA1_CH2_TIM17_CH1) \|\|\
mbed_official	441:d2c15dda23c1	464	((REQUEST) == HAL_DMA1_CH2_TIM17_UP) \|\|\
mbed_official	441:d2c15dda23c1	465	((REQUEST) == HAL_DMA1_CH2_USART1_TX) \|\|\
mbed_official	441:d2c15dda23c1	466	((REQUEST) == HAL_DMA1_CH2_USART2_TX) \|\|\
mbed_official	441:d2c15dda23c1	467	((REQUEST) == HAL_DMA1_CH2_USART3_TX) \|\|\
mbed_official	441:d2c15dda23c1	468	((REQUEST) == HAL_DMA1_CH2_USART4_TX) \|\|\
mbed_official	441:d2c15dda23c1	469	((REQUEST) == HAL_DMA1_CH2_USART5_TX) \|\|\
mbed_official	441:d2c15dda23c1	470	((REQUEST) == HAL_DMA1_CH2_USART6_TX) \|\|\
mbed_official	441:d2c15dda23c1	471	((REQUEST) == HAL_DMA1_CH3_DEFAULT) \|\|\
mbed_official	441:d2c15dda23c1	472	((REQUEST) == HAL_DMA1_CH3_TIM6_UP) \|\|\
mbed_official	441:d2c15dda23c1	473	((REQUEST) == HAL_DMA1_CH3_I2C1_RX) \|\|\
mbed_official	441:d2c15dda23c1	474	((REQUEST) == HAL_DMA1_CH3_SPI1_TX) \|\|\
mbed_official	441:d2c15dda23c1	475	((REQUEST) == HAL_DMA1_CH3_TIM1_CH2) \|\|\
mbed_official	441:d2c15dda23c1	476	((REQUEST) == HAL_DMA1_CH3_TIM16_CH1) \|\|\
mbed_official	441:d2c15dda23c1	477	((REQUEST) == HAL_DMA1_CH3_TIM16_UP) \|\|\
mbed_official	441:d2c15dda23c1	478	((REQUEST) == HAL_DMA1_CH3_USART1_RX) \|\|\
mbed_official	441:d2c15dda23c1	479	((REQUEST) == HAL_DMA1_CH3_USART2_RX) \|\|\
mbed_official	441:d2c15dda23c1	480	((REQUEST) == HAL_DMA1_CH3_USART3_RX) \|\|\
mbed_official	441:d2c15dda23c1	481	((REQUEST) == HAL_DMA1_CH3_USART4_RX) \|\|\
mbed_official	441:d2c15dda23c1	482	((REQUEST) == HAL_DMA1_CH3_USART5_RX) \|\|\
mbed_official	441:d2c15dda23c1	483	((REQUEST) == HAL_DMA1_CH3_USART6_RX) \|\|\
mbed_official	441:d2c15dda23c1	484	((REQUEST) == HAL_DMA1_CH4_DEFAULT) \|\|\
mbed_official	441:d2c15dda23c1	485	((REQUEST) == HAL_DMA1_CH4_TIM7_UP) \|\|\
mbed_official	441:d2c15dda23c1	486	((REQUEST) == HAL_DMA1_CH4_I2C2_TX) \|\|\
mbed_official	441:d2c15dda23c1	487	((REQUEST) == HAL_DMA1_CH4_SPI2_RX) \|\|\
mbed_official	441:d2c15dda23c1	488	((REQUEST) == HAL_DMA1_CH4_TIM3_CH1) \|\|\
mbed_official	441:d2c15dda23c1	489	((REQUEST) == HAL_DMA1_CH4_TIM3_TRIG) \|\|\
mbed_official	441:d2c15dda23c1	490	((REQUEST) == HAL_DMA1_CH4_TIM16_CH1) \|\|\
mbed_official	441:d2c15dda23c1	491	((REQUEST) == HAL_DMA1_CH4_TIM16_UP) \|\|\
mbed_official	441:d2c15dda23c1	492	((REQUEST) == HAL_DMA1_CH4_USART1_TX) \|\|\
mbed_official	441:d2c15dda23c1	493	((REQUEST) == HAL_DMA1_CH4_USART2_TX) \|\|\
mbed_official	441:d2c15dda23c1	494	((REQUEST) == HAL_DMA1_CH4_USART3_TX) \|\|\
mbed_official	441:d2c15dda23c1	495	((REQUEST) == HAL_DMA1_CH4_USART4_TX) \|\|\
mbed_official	441:d2c15dda23c1	496	((REQUEST) == HAL_DMA1_CH4_USART5_TX) \|\|\
mbed_official	441:d2c15dda23c1	497	((REQUEST) == HAL_DMA1_CH4_USART6_TX) \|\|\
mbed_official	441:d2c15dda23c1	498	((REQUEST) == HAL_DMA1_CH5_DEFAULT) \|\|\
mbed_official	441:d2c15dda23c1	499	((REQUEST) == HAL_DMA1_CH5_I2C2_RX) \|\|\
mbed_official	441:d2c15dda23c1	500	((REQUEST) == HAL_DMA1_CH5_SPI2_TX) \|\|\
mbed_official	441:d2c15dda23c1	501	((REQUEST) == HAL_DMA1_CH5_TIM1_CH3) \|\|\
mbed_official	441:d2c15dda23c1	502	((REQUEST) == HAL_DMA1_CH5_USART1_RX) \|\|\
mbed_official	441:d2c15dda23c1	503	((REQUEST) == HAL_DMA1_CH5_USART2_RX) \|\|\
mbed_official	441:d2c15dda23c1	504	((REQUEST) == HAL_DMA1_CH5_USART3_RX) \|\|\
mbed_official	441:d2c15dda23c1	505	((REQUEST) == HAL_DMA1_CH5_USART4_RX) \|\|\
mbed_official	441:d2c15dda23c1	506	((REQUEST) == HAL_DMA1_CH5_USART5_RX) \|\|\
mbed_official	441:d2c15dda23c1	507	((REQUEST) == HAL_DMA1_CH5_USART6_RX))
mbed_official	441:d2c15dda23c1	508	#endif /* STM32F030xC */
mbed_official	441:d2c15dda23c1	509
mbed_official	340:28d1f895c6fe	510	/**
mbed_official	340:28d1f895c6fe	511	* @}
mbed_official	340:28d1f895c6fe	512	*/
mbed_official	441:d2c15dda23c1	513	#endif /* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
mbed_official	340:28d1f895c6fe	514
mbed_official	340:28d1f895c6fe	515	/* Exported macros -----------------------------------------------------------*/
mbed_official	340:28d1f895c6fe	516
mbed_official	340:28d1f895c6fe	517	/** @defgroup DMAEx_Exported_Macros DMAEx Exported Macros
mbed_official	340:28d1f895c6fe	518	* @{
mbed_official	340:28d1f895c6fe	519	*/
mbed_official	340:28d1f895c6fe	520	/* Interrupt & Flag management */
mbed_official	340:28d1f895c6fe	521
mbed_official	340:28d1f895c6fe	522	#if defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)
mbed_official	340:28d1f895c6fe	523	/**
mbed_official	340:28d1f895c6fe	524	* @brief Returns the current DMA Channel transfer complete flag.
mbed_official	340:28d1f895c6fe	525	* @param __HANDLE__: DMA handle
mbed_official	340:28d1f895c6fe	526	* @retval The specified transfer complete flag index.
mbed_official	340:28d1f895c6fe	527	*/
mbed_official	340:28d1f895c6fe	528	#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
mbed_official	340:28d1f895c6fe	529	(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
mbed_official	340:28d1f895c6fe	530	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
mbed_official	340:28d1f895c6fe	531	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
mbed_official	340:28d1f895c6fe	532	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
mbed_official	340:28d1f895c6fe	533	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
mbed_official	340:28d1f895c6fe	534	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
mbed_official	340:28d1f895c6fe	535	DMA_FLAG_TC7)
mbed_official	340:28d1f895c6fe	536
mbed_official	340:28d1f895c6fe	537	/**
mbed_official	340:28d1f895c6fe	538	* @brief Returns the current DMA Channel half transfer complete flag.
mbed_official	340:28d1f895c6fe	539	* @param __HANDLE__: DMA handle
mbed_official	340:28d1f895c6fe	540	* @retval The specified half transfer complete flag index.
mbed_official	340:28d1f895c6fe	541	*/
mbed_official	340:28d1f895c6fe	542	#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
mbed_official	340:28d1f895c6fe	543	(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
mbed_official	340:28d1f895c6fe	544	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
mbed_official	340:28d1f895c6fe	545	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
mbed_official	340:28d1f895c6fe	546	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
mbed_official	340:28d1f895c6fe	547	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
mbed_official	340:28d1f895c6fe	548	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
mbed_official	340:28d1f895c6fe	549	DMA_FLAG_HT7)
mbed_official	340:28d1f895c6fe	550
mbed_official	340:28d1f895c6fe	551	/**
mbed_official	340:28d1f895c6fe	552	* @brief Returns the current DMA Channel transfer error flag.
mbed_official	340:28d1f895c6fe	553	* @param __HANDLE__: DMA handle
mbed_official	340:28d1f895c6fe	554	* @retval The specified transfer error flag index.
mbed_official	340:28d1f895c6fe	555	*/
mbed_official	340:28d1f895c6fe	556	#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
mbed_official	340:28d1f895c6fe	557	(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
mbed_official	340:28d1f895c6fe	558	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
mbed_official	340:28d1f895c6fe	559	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
mbed_official	340:28d1f895c6fe	560	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
mbed_official	340:28d1f895c6fe	561	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
mbed_official	340:28d1f895c6fe	562	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
mbed_official	340:28d1f895c6fe	563	DMA_FLAG_TE7)
mbed_official	340:28d1f895c6fe	564
mbed_official	340:28d1f895c6fe	565	/**
mbed_official	340:28d1f895c6fe	566	* @brief Get the DMA Channel pending flags.
mbed_official	340:28d1f895c6fe	567	* @param __HANDLE__: DMA handle
mbed_official	340:28d1f895c6fe	568	* @param __FLAG__: Get the specified flag.
mbed_official	340:28d1f895c6fe	569	* This parameter can be any combination of the following values:
mbed_official	441:d2c15dda23c1	570	* @arg DMA_FLAG_TCx: Transfer complete flag
mbed_official	441:d2c15dda23c1	571	* @arg DMA_FLAG_HTx: Half transfer complete flag
mbed_official	441:d2c15dda23c1	572	* @arg DMA_FLAG_TEx: Transfer error flag
mbed_official	340:28d1f895c6fe	573	* Where x can be 1_7 to select the DMA Channel flag.
mbed_official	340:28d1f895c6fe	574	* @retval The state of FLAG (SET or RESET).
mbed_official	340:28d1f895c6fe	575	*/
mbed_official	340:28d1f895c6fe	576
mbed_official	340:28d1f895c6fe	577	#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__))
mbed_official	340:28d1f895c6fe	578
mbed_official	340:28d1f895c6fe	579	/**
mbed_official	340:28d1f895c6fe	580	* @brief Clears the DMA Channel pending flags.
mbed_official	340:28d1f895c6fe	581	* @param __HANDLE__: DMA handle
mbed_official	340:28d1f895c6fe	582	* @param __FLAG__: specifies the flag to clear.
mbed_official	340:28d1f895c6fe	583	* This parameter can be any combination of the following values:
mbed_official	441:d2c15dda23c1	584	* @arg DMA_FLAG_TCx: Transfer complete flag
mbed_official	441:d2c15dda23c1	585	* @arg DMA_FLAG_HTx: Half transfer complete flag
mbed_official	441:d2c15dda23c1	586	* @arg DMA_FLAG_TEx: Transfer error flag
mbed_official	340:28d1f895c6fe	587	* Where x can be 1_7 to select the DMA Channel flag.
mbed_official	340:28d1f895c6fe	588	* @retval None
mbed_official	340:28d1f895c6fe	589	*/
mbed_official	340:28d1f895c6fe	590	#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__))
mbed_official	340:28d1f895c6fe	591
mbed_official	340:28d1f895c6fe	592	#elif defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	340:28d1f895c6fe	593	/**
mbed_official	340:28d1f895c6fe	594	* @brief Returns the current DMA Channel transfer complete flag.
mbed_official	340:28d1f895c6fe	595	* @param __HANDLE__: DMA handle
mbed_official	340:28d1f895c6fe	596	* @retval The specified transfer complete flag index.
mbed_official	340:28d1f895c6fe	597	*/
mbed_official	340:28d1f895c6fe	598	#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
mbed_official	340:28d1f895c6fe	599	(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
mbed_official	340:28d1f895c6fe	600	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
mbed_official	340:28d1f895c6fe	601	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
mbed_official	340:28d1f895c6fe	602	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
mbed_official	340:28d1f895c6fe	603	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
mbed_official	340:28d1f895c6fe	604	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
mbed_official	340:28d1f895c6fe	605	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TC7 :\
mbed_official	340:28d1f895c6fe	606	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\
mbed_official	340:28d1f895c6fe	607	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\
mbed_official	340:28d1f895c6fe	608	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\
mbed_official	340:28d1f895c6fe	609	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\
mbed_official	340:28d1f895c6fe	610	DMA_FLAG_TC5)
mbed_official	340:28d1f895c6fe	611
mbed_official	340:28d1f895c6fe	612	/**
mbed_official	340:28d1f895c6fe	613	* @brief Returns the current DMA Channel half transfer complete flag.
mbed_official	340:28d1f895c6fe	614	* @param __HANDLE__: DMA handle
mbed_official	340:28d1f895c6fe	615	* @retval The specified half transfer complete flag index.
mbed_official	340:28d1f895c6fe	616	*/
mbed_official	340:28d1f895c6fe	617	#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
mbed_official	340:28d1f895c6fe	618	(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
mbed_official	340:28d1f895c6fe	619	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
mbed_official	340:28d1f895c6fe	620	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
mbed_official	340:28d1f895c6fe	621	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
mbed_official	340:28d1f895c6fe	622	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
mbed_official	340:28d1f895c6fe	623	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
mbed_official	340:28d1f895c6fe	624	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_HT7 :\
mbed_official	340:28d1f895c6fe	625	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\
mbed_official	340:28d1f895c6fe	626	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\
mbed_official	340:28d1f895c6fe	627	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\
mbed_official	340:28d1f895c6fe	628	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\
mbed_official	340:28d1f895c6fe	629	DMA_FLAG_HT5)
mbed_official	340:28d1f895c6fe	630
mbed_official	340:28d1f895c6fe	631	/**
mbed_official	340:28d1f895c6fe	632	* @brief Returns the current DMA Channel transfer error flag.
mbed_official	340:28d1f895c6fe	633	* @param __HANDLE__: DMA handle
mbed_official	340:28d1f895c6fe	634	* @retval The specified transfer error flag index.
mbed_official	340:28d1f895c6fe	635	*/
mbed_official	340:28d1f895c6fe	636	#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
mbed_official	340:28d1f895c6fe	637	(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
mbed_official	340:28d1f895c6fe	638	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
mbed_official	340:28d1f895c6fe	639	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
mbed_official	340:28d1f895c6fe	640	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
mbed_official	340:28d1f895c6fe	641	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
mbed_official	340:28d1f895c6fe	642	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
mbed_official	340:28d1f895c6fe	643	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TE7 :\
mbed_official	340:28d1f895c6fe	644	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\
mbed_official	340:28d1f895c6fe	645	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\
mbed_official	340:28d1f895c6fe	646	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\
mbed_official	340:28d1f895c6fe	647	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\
mbed_official	340:28d1f895c6fe	648	DMA_FLAG_TE5)
mbed_official	340:28d1f895c6fe	649
mbed_official	340:28d1f895c6fe	650	/**
mbed_official	340:28d1f895c6fe	651	* @brief Get the DMA Channel pending flags.
mbed_official	340:28d1f895c6fe	652	* @param __HANDLE__: DMA handle
mbed_official	340:28d1f895c6fe	653	* @param __FLAG__: Get the specified flag.
mbed_official	340:28d1f895c6fe	654	* This parameter can be any combination of the following values:
mbed_official	441:d2c15dda23c1	655	* @arg DMA_FLAG_TCx: Transfer complete flag
mbed_official	441:d2c15dda23c1	656	* @arg DMA_FLAG_HTx: Half transfer complete flag
mbed_official	441:d2c15dda23c1	657	* @arg DMA_FLAG_TEx: Transfer error flag
mbed_official	340:28d1f895c6fe	658	* Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Channel flag.
mbed_official	340:28d1f895c6fe	659	* @retval The state of FLAG (SET or RESET).
mbed_official	340:28d1f895c6fe	660	*/
mbed_official	340:28d1f895c6fe	661
mbed_official	340:28d1f895c6fe	662	#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\
mbed_official	340:28d1f895c6fe	663	(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->ISR & (__FLAG__)) :\
mbed_official	340:28d1f895c6fe	664	(DMA1->ISR & (__FLAG__)))
mbed_official	340:28d1f895c6fe	665
mbed_official	340:28d1f895c6fe	666	/**
mbed_official	340:28d1f895c6fe	667	* @brief Clears the DMA Channel pending flags.
mbed_official	340:28d1f895c6fe	668	* @param __HANDLE__: DMA handle
mbed_official	340:28d1f895c6fe	669	* @param __FLAG__: specifies the flag to clear.
mbed_official	340:28d1f895c6fe	670	* This parameter can be any combination of the following values:
mbed_official	441:d2c15dda23c1	671	* @arg DMA_FLAG_TCx: Transfer complete flag
mbed_official	441:d2c15dda23c1	672	* @arg DMA_FLAG_HTx: Half transfer complete flag
mbed_official	441:d2c15dda23c1	673	* @arg DMA_FLAG_TEx: Transfer error flag
mbed_official	340:28d1f895c6fe	674	* Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Channel flag.
mbed_official	340:28d1f895c6fe	675	* @retval None
mbed_official	340:28d1f895c6fe	676	*/
mbed_official	340:28d1f895c6fe	677	#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
mbed_official	340:28d1f895c6fe	678	(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->IFCR = (__FLAG__)) :\
mbed_official	340:28d1f895c6fe	679	(DMA1->IFCR = (__FLAG__)))
mbed_official	340:28d1f895c6fe	680
mbed_official	441:d2c15dda23c1	681	#else /* STM32F030x8_STM32F030xC_STM32F031x6_STM32F038xx_STM32F051x8_STM32F058xx_STM32F070x6_STM32F070xB Product devices */
mbed_official	340:28d1f895c6fe	682	/**
mbed_official	340:28d1f895c6fe	683	* @brief Returns the current DMA Channel transfer complete flag.
mbed_official	340:28d1f895c6fe	684	* @param __HANDLE__: DMA handle
mbed_official	340:28d1f895c6fe	685	* @retval The specified transfer complete flag index.
mbed_official	340:28d1f895c6fe	686	*/
mbed_official	340:28d1f895c6fe	687	#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
mbed_official	340:28d1f895c6fe	688	(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
mbed_official	340:28d1f895c6fe	689	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
mbed_official	340:28d1f895c6fe	690	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
mbed_official	340:28d1f895c6fe	691	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
mbed_official	340:28d1f895c6fe	692	DMA_FLAG_TC5)
mbed_official	340:28d1f895c6fe	693
mbed_official	340:28d1f895c6fe	694	/**
mbed_official	340:28d1f895c6fe	695	* @brief Returns the current DMA Channel half transfer complete flag.
mbed_official	340:28d1f895c6fe	696	* @param __HANDLE__: DMA handle
mbed_official	340:28d1f895c6fe	697	* @retval The specified half transfer complete flag index.
mbed_official	340:28d1f895c6fe	698	*/
mbed_official	340:28d1f895c6fe	699	#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
mbed_official	340:28d1f895c6fe	700	(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
mbed_official	340:28d1f895c6fe	701	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
mbed_official	340:28d1f895c6fe	702	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
mbed_official	340:28d1f895c6fe	703	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
mbed_official	340:28d1f895c6fe	704	DMA_FLAG_HT5)
mbed_official	340:28d1f895c6fe	705
mbed_official	340:28d1f895c6fe	706	/**
mbed_official	340:28d1f895c6fe	707	* @brief Returns the current DMA Channel transfer error flag.
mbed_official	340:28d1f895c6fe	708	* @param __HANDLE__: DMA handle
mbed_official	340:28d1f895c6fe	709	* @retval The specified transfer error flag index.
mbed_official	340:28d1f895c6fe	710	*/
mbed_official	340:28d1f895c6fe	711	#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
mbed_official	340:28d1f895c6fe	712	(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
mbed_official	340:28d1f895c6fe	713	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
mbed_official	340:28d1f895c6fe	714	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
mbed_official	340:28d1f895c6fe	715	((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
mbed_official	340:28d1f895c6fe	716	DMA_FLAG_TE5)
mbed_official	340:28d1f895c6fe	717
mbed_official	340:28d1f895c6fe	718	/**
mbed_official	340:28d1f895c6fe	719	* @brief Get the DMA Channel pending flags.
mbed_official	340:28d1f895c6fe	720	* @param __HANDLE__: DMA handle
mbed_official	340:28d1f895c6fe	721	* @param __FLAG__: Get the specified flag.
mbed_official	340:28d1f895c6fe	722	* This parameter can be any combination of the following values:
mbed_official	441:d2c15dda23c1	723	* @arg DMA_FLAG_TCx: Transfer complete flag
mbed_official	441:d2c15dda23c1	724	* @arg DMA_FLAG_HTx: Half transfer complete flag
mbed_official	441:d2c15dda23c1	725	* @arg DMA_FLAG_TEx: Transfer error flag
mbed_official	340:28d1f895c6fe	726	* Where x can be 1_5 to select the DMA Channel flag.
mbed_official	340:28d1f895c6fe	727	* @retval The state of FLAG (SET or RESET).
mbed_official	340:28d1f895c6fe	728	*/
mbed_official	340:28d1f895c6fe	729
mbed_official	340:28d1f895c6fe	730	#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__))
mbed_official	340:28d1f895c6fe	731
mbed_official	340:28d1f895c6fe	732	/**
mbed_official	340:28d1f895c6fe	733	* @brief Clears the DMA Channel pending flags.
mbed_official	340:28d1f895c6fe	734	* @param __HANDLE__: DMA handle
mbed_official	340:28d1f895c6fe	735	* @param __FLAG__: specifies the flag to clear.
mbed_official	340:28d1f895c6fe	736	* This parameter can be any combination of the following values:
mbed_official	441:d2c15dda23c1	737	* @arg DMA_FLAG_TCx: Transfer complete flag
mbed_official	441:d2c15dda23c1	738	* @arg DMA_FLAG_HTx: Half transfer complete flag
mbed_official	441:d2c15dda23c1	739	* @arg DMA_FLAG_TEx: Transfer error flag
mbed_official	340:28d1f895c6fe	740	* Where x can be 1_5 to select the DMA Channel flag.
mbed_official	340:28d1f895c6fe	741	* @retval None
mbed_official	340:28d1f895c6fe	742	*/
mbed_official	340:28d1f895c6fe	743	#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__))
mbed_official	340:28d1f895c6fe	744
mbed_official	340:28d1f895c6fe	745	#endif
mbed_official	340:28d1f895c6fe	746
mbed_official	340:28d1f895c6fe	747
mbed_official	441:d2c15dda23c1	748	#if defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
mbed_official	340:28d1f895c6fe	749	#define __HAL_DMA1_REMAP(__REQUEST__) \
mbed_official	340:28d1f895c6fe	750	do { assert_param(IS_HAL_DMA1_REMAP(__REQUEST__)); \
mbed_official	441:d2c15dda23c1	751	DMA1->CSELR &= ~((uint32_t)0x0F << (uint32_t)(((__REQUEST__) >> 28) * 4)); \
mbed_official	441:d2c15dda23c1	752	DMA1->CSELR \|= (uint32_t)((__REQUEST__) & 0x0FFFFFFF); \
mbed_official	340:28d1f895c6fe	753	}while(0)
mbed_official	340:28d1f895c6fe	754
mbed_official	441:d2c15dda23c1	755	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	340:28d1f895c6fe	756	#define __HAL_DMA2_REMAP(__REQUEST__) \
mbed_official	340:28d1f895c6fe	757	do { assert_param(IS_HAL_DMA2_REMAP(__REQUEST__)); \
mbed_official	441:d2c15dda23c1	758	DMA2->CSELR &= ~((uint32_t)0x0F << (uint32_t)(((__REQUEST__) >> 28) * 4)); \
mbed_official	441:d2c15dda23c1	759	DMA2->CSELR \|= (uint32_t)((__REQUEST__) & 0x0FFFFFFF); \
mbed_official	340:28d1f895c6fe	760	}while(0)
mbed_official	441:d2c15dda23c1	761	#endif /* STM32F091xC \|\| STM32F098xx */
mbed_official	340:28d1f895c6fe	762
mbed_official	441:d2c15dda23c1	763	#endif /* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
mbed_official	340:28d1f895c6fe	764
mbed_official	340:28d1f895c6fe	765	/**
mbed_official	340:28d1f895c6fe	766	* @}
mbed_official	340:28d1f895c6fe	767	*/
mbed_official	340:28d1f895c6fe	768
mbed_official	340:28d1f895c6fe	769	/**
mbed_official	340:28d1f895c6fe	770	* @}
mbed_official	340:28d1f895c6fe	771	*/
mbed_official	340:28d1f895c6fe	772
mbed_official	340:28d1f895c6fe	773	/**
mbed_official	340:28d1f895c6fe	774	* @}
mbed_official	340:28d1f895c6fe	775	*/
mbed_official	340:28d1f895c6fe	776
mbed_official	340:28d1f895c6fe	777	#ifdef __cplusplus
mbed_official	340:28d1f895c6fe	778	}
mbed_official	340:28d1f895c6fe	779	#endif
mbed_official	340:28d1f895c6fe	780
mbed_official	340:28d1f895c6fe	781	#endif /* __STM32F0xx_HAL_DMA_EX_H */
mbed_official	340:28d1f895c6fe	782
mbed_official	340:28d1f895c6fe	783	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/