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Last commit 20 Feb 2019 by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/stm32f091xc.h@579:53297373a894, 2015-07-01 (annotated)

Committer:
mbed_official
Date:
Wed Jul 01 09:45:11 2015 +0100
Revision:
579:53297373a894
Parent:
441:d2c15dda23c1
Child:
630:825f75ca301e
Synchronized with git revision d5b4d2ab9c47edb4dc5776e7177b0c2263459081



Full URL: https://github.com/mbedmicro/mbed/commit/d5b4d2ab9c47edb4dc5776e7177b0c2263459081/



Initial version of drivers for SAMR21

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 340:28d1f895c6fe 1 /**
mbed_official 340:28d1f895c6fe 2 ******************************************************************************
mbed_official 340:28d1f895c6fe 3 * @file stm32f091xc.h
mbed_official 340:28d1f895c6fe 4 * @author MCD Application Team
mbed_official 441:d2c15dda23c1 5 * @version V2.2.0
mbed_official 441:d2c15dda23c1 6 * @date 05-December-2014
mbed_official 340:28d1f895c6fe 7 * @brief CMSIS STM32F091xC devices Peripheral Access Layer Header File.
mbed_official 340:28d1f895c6fe 8 *
mbed_official 340:28d1f895c6fe 9 * This file contains:
mbed_official 340:28d1f895c6fe 10 * - Data structures and the address mapping for all peripherals
mbed_official 340:28d1f895c6fe 11 * - Peripheral's registers declarations and bits definition
mbed_official 340:28d1f895c6fe 12 * - Macros to access peripheral’s registers hardware
mbed_official 340:28d1f895c6fe 13 *
mbed_official 340:28d1f895c6fe 14 ******************************************************************************
mbed_official 340:28d1f895c6fe 15 * @attention
mbed_official 340:28d1f895c6fe 16 *
mbed_official 340:28d1f895c6fe 17 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
mbed_official 340:28d1f895c6fe 18 *
mbed_official 340:28d1f895c6fe 19 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 340:28d1f895c6fe 20 * are permitted provided that the following conditions are met:
mbed_official 340:28d1f895c6fe 21 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 340:28d1f895c6fe 22 * this list of conditions and the following disclaimer.
mbed_official 340:28d1f895c6fe 23 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 340:28d1f895c6fe 24 * this list of conditions and the following disclaimer in the documentation
mbed_official 340:28d1f895c6fe 25 * and/or other materials provided with the distribution.
mbed_official 340:28d1f895c6fe 26 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 340:28d1f895c6fe 27 * may be used to endorse or promote products derived from this software
mbed_official 340:28d1f895c6fe 28 * without specific prior written permission.
mbed_official 340:28d1f895c6fe 29 *
mbed_official 340:28d1f895c6fe 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 340:28d1f895c6fe 31 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 340:28d1f895c6fe 32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 340:28d1f895c6fe 33 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 340:28d1f895c6fe 34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 340:28d1f895c6fe 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 340:28d1f895c6fe 36 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 340:28d1f895c6fe 37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 340:28d1f895c6fe 38 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 340:28d1f895c6fe 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 340:28d1f895c6fe 40 *
mbed_official 340:28d1f895c6fe 41 ******************************************************************************
mbed_official 340:28d1f895c6fe 42 */
mbed_official 340:28d1f895c6fe 43
mbed_official 340:28d1f895c6fe 44 /** @addtogroup CMSIS_Device
mbed_official 340:28d1f895c6fe 45 * @{
mbed_official 340:28d1f895c6fe 46 */
mbed_official 340:28d1f895c6fe 47
mbed_official 340:28d1f895c6fe 48 /** @addtogroup stm32f091xc
mbed_official 340:28d1f895c6fe 49 * @{
mbed_official 340:28d1f895c6fe 50 */
mbed_official 340:28d1f895c6fe 51
mbed_official 340:28d1f895c6fe 52 #ifndef __STM32F091xC_H
mbed_official 340:28d1f895c6fe 53 #define __STM32F091xC_H
mbed_official 340:28d1f895c6fe 54
mbed_official 340:28d1f895c6fe 55 #ifdef __cplusplus
mbed_official 340:28d1f895c6fe 56 extern "C" {
mbed_official 340:28d1f895c6fe 57 #endif /* __cplusplus */
mbed_official 340:28d1f895c6fe 58
mbed_official 340:28d1f895c6fe 59 /** @addtogroup Configuration_section_for_CMSIS
mbed_official 340:28d1f895c6fe 60 * @{
mbed_official 340:28d1f895c6fe 61 */
mbed_official 340:28d1f895c6fe 62
mbed_official 340:28d1f895c6fe 63 /**
mbed_official 340:28d1f895c6fe 64 * @brief Configuration of the Cortex-M0 Processor and Core Peripherals
mbed_official 340:28d1f895c6fe 65 */
mbed_official 340:28d1f895c6fe 66 #define __CM0_REV 0 /*!< Core Revision r0p0 */
mbed_official 340:28d1f895c6fe 67 #define __MPU_PRESENT 0 /*!< STM32F0xx do not provide MPU */
mbed_official 340:28d1f895c6fe 68 #define __NVIC_PRIO_BITS 2 /*!< STM32F0xx uses 2 Bits for the Priority Levels */
mbed_official 340:28d1f895c6fe 69 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
mbed_official 340:28d1f895c6fe 70
mbed_official 340:28d1f895c6fe 71 /**
mbed_official 340:28d1f895c6fe 72 * @}
mbed_official 340:28d1f895c6fe 73 */
mbed_official 340:28d1f895c6fe 74
mbed_official 340:28d1f895c6fe 75 /** @addtogroup Peripheral_interrupt_number_definition
mbed_official 340:28d1f895c6fe 76 * @{
mbed_official 340:28d1f895c6fe 77 */
mbed_official 340:28d1f895c6fe 78
mbed_official 340:28d1f895c6fe 79 /**
mbed_official 340:28d1f895c6fe 80 * @brief STM32F091xC device Interrupt Number Definition
mbed_official 340:28d1f895c6fe 81 */
mbed_official 340:28d1f895c6fe 82 typedef enum
mbed_official 340:28d1f895c6fe 83 {
mbed_official 340:28d1f895c6fe 84 /****** Cortex-M0 Processor Exceptions Numbers **************************************************************/
mbed_official 340:28d1f895c6fe 85 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
mbed_official 340:28d1f895c6fe 86 HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */
mbed_official 340:28d1f895c6fe 87 SVC_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */
mbed_official 340:28d1f895c6fe 88 PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */
mbed_official 340:28d1f895c6fe 89 SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */
mbed_official 340:28d1f895c6fe 90
mbed_official 340:28d1f895c6fe 91 /****** STM32F091xC specific Interrupt Numbers **************************************************/
mbed_official 340:28d1f895c6fe 92 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
mbed_official 340:28d1f895c6fe 93 PVD_VDDIO2_IRQn = 1, /*!< PVD & VDDIO2 Interrupts through EXTI Lines 16 and 31 */
mbed_official 340:28d1f895c6fe 94 RTC_IRQn = 2, /*!< RTC Interrupt through EXTI Lines 17, 19 and 20 */
mbed_official 340:28d1f895c6fe 95 FLASH_IRQn = 3, /*!< FLASH global Interrupt */
mbed_official 340:28d1f895c6fe 96 RCC_CRS_IRQn = 4, /*!< RCC & CRS global Interrupts */
mbed_official 340:28d1f895c6fe 97 EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */
mbed_official 340:28d1f895c6fe 98 EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */
mbed_official 340:28d1f895c6fe 99 EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */
mbed_official 340:28d1f895c6fe 100 TSC_IRQn = 8, /*!< Touch Sensing Controller Interrupts */
mbed_official 340:28d1f895c6fe 101 DMA1_Ch1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */
mbed_official 340:28d1f895c6fe 102 DMA1_Ch2_3_DMA2_Ch1_2_IRQn = 10, /*!< DMA1 Channel 2 and 3 & DMA2 Channel 1 and 2 Interrupts */
mbed_official 340:28d1f895c6fe 103 DMA1_Ch4_7_DMA2_Ch3_5_IRQn = 11, /*!< DMA1 Channel 4 to 7 & DMA2 Channel 3 to 5 Interrupts */
mbed_official 340:28d1f895c6fe 104 ADC1_COMP_IRQn = 12, /*!< ADC, COMP1 and COMP2 Interrupts (EXTI Lines 21 and 22) */
mbed_official 340:28d1f895c6fe 105 TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupts */
mbed_official 340:28d1f895c6fe 106 TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */
mbed_official 340:28d1f895c6fe 107 TIM2_IRQn = 15, /*!< TIM2 global Interrupt */
mbed_official 340:28d1f895c6fe 108 TIM3_IRQn = 16, /*!< TIM3 global Interrupt */
mbed_official 340:28d1f895c6fe 109 TIM6_DAC_IRQn = 17, /*!< TIM6 global and DAC channel underrun error Interrupts */
mbed_official 340:28d1f895c6fe 110 TIM7_IRQn = 18, /*!< TIM7 global Interrupt */
mbed_official 340:28d1f895c6fe 111 TIM14_IRQn = 19, /*!< TIM14 global Interrupt */
mbed_official 340:28d1f895c6fe 112 TIM15_IRQn = 20, /*!< TIM15 global Interrupt */
mbed_official 340:28d1f895c6fe 113 TIM16_IRQn = 21, /*!< TIM16 global Interrupt */
mbed_official 340:28d1f895c6fe 114 TIM17_IRQn = 22, /*!< TIM17 global Interrupt */
mbed_official 340:28d1f895c6fe 115 I2C1_IRQn = 23, /*!< I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup) */
mbed_official 340:28d1f895c6fe 116 I2C2_IRQn = 24, /*!< I2C2 Event Interrupt */
mbed_official 340:28d1f895c6fe 117 SPI1_IRQn = 25, /*!< SPI1 global Interrupt */
mbed_official 340:28d1f895c6fe 118 SPI2_IRQn = 26, /*!< SPI2 global Interrupt */
mbed_official 340:28d1f895c6fe 119 USART1_IRQn = 27, /*!< USART1 global Interrupt & EXTI Line25 Interrupt (USART1 wakeup) */
mbed_official 340:28d1f895c6fe 120 USART2_IRQn = 28, /*!< USART2 global Interrupt & EXTI Line26 Interrupt (USART2 wakeup) */
mbed_official 340:28d1f895c6fe 121 USART3_8_IRQn = 29, /*!< USART3 to USART8 global Interrupts */
mbed_official 340:28d1f895c6fe 122 CEC_CAN_IRQn = 30 /*!< CEC and CAN global Interrupts & EXTI Line27 Interrupt */
mbed_official 340:28d1f895c6fe 123 } IRQn_Type;
mbed_official 340:28d1f895c6fe 124
mbed_official 340:28d1f895c6fe 125 /**
mbed_official 340:28d1f895c6fe 126 * @}
mbed_official 340:28d1f895c6fe 127 */
mbed_official 340:28d1f895c6fe 128
mbed_official 340:28d1f895c6fe 129 #include "core_cm0.h" /* Cortex-M0 processor and core peripherals */
mbed_official 340:28d1f895c6fe 130 #include "system_stm32f0xx.h" /* STM32F0xx System Header */
mbed_official 340:28d1f895c6fe 131 #include <stdint.h>
mbed_official 340:28d1f895c6fe 132
mbed_official 340:28d1f895c6fe 133 /** @addtogroup Peripheral_registers_structures
mbed_official 340:28d1f895c6fe 134 * @{
mbed_official 340:28d1f895c6fe 135 */
mbed_official 340:28d1f895c6fe 136
mbed_official 340:28d1f895c6fe 137 /**
mbed_official 340:28d1f895c6fe 138 * @brief Analog to Digital Converter
mbed_official 340:28d1f895c6fe 139 */
mbed_official 340:28d1f895c6fe 140
mbed_official 340:28d1f895c6fe 141 typedef struct
mbed_official 340:28d1f895c6fe 142 {
mbed_official 340:28d1f895c6fe 143 __IO uint32_t ISR; /*!< ADC Interrupt and Status register, Address offset:0x00 */
mbed_official 340:28d1f895c6fe 144 __IO uint32_t IER; /*!< ADC Interrupt Enable register, Address offset:0x04 */
mbed_official 340:28d1f895c6fe 145 __IO uint32_t CR; /*!< ADC Control register, Address offset:0x08 */
mbed_official 340:28d1f895c6fe 146 __IO uint32_t CFGR1; /*!< ADC Configuration register 1, Address offset:0x0C */
mbed_official 340:28d1f895c6fe 147 __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset:0x10 */
mbed_official 340:28d1f895c6fe 148 __IO uint32_t SMPR; /*!< ADC Sampling time register, Address offset:0x14 */
mbed_official 340:28d1f895c6fe 149 uint32_t RESERVED1; /*!< Reserved, 0x18 */
mbed_official 340:28d1f895c6fe 150 uint32_t RESERVED2; /*!< Reserved, 0x1C */
mbed_official 340:28d1f895c6fe 151 __IO uint32_t TR; /*!< ADC watchdog threshold register, Address offset:0x20 */
mbed_official 340:28d1f895c6fe 152 uint32_t RESERVED3; /*!< Reserved, 0x24 */
mbed_official 340:28d1f895c6fe 153 __IO uint32_t CHSELR; /*!< ADC channel selection register, Address offset:0x28 */
mbed_official 340:28d1f895c6fe 154 uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */
mbed_official 340:28d1f895c6fe 155 __IO uint32_t DR; /*!< ADC data register, Address offset:0x40 */
mbed_official 340:28d1f895c6fe 156 }ADC_TypeDef;
mbed_official 340:28d1f895c6fe 157
mbed_official 340:28d1f895c6fe 158 typedef struct
mbed_official 340:28d1f895c6fe 159 {
mbed_official 340:28d1f895c6fe 160 __IO uint32_t CCR;
mbed_official 340:28d1f895c6fe 161 }ADC_Common_TypeDef;
mbed_official 340:28d1f895c6fe 162
mbed_official 340:28d1f895c6fe 163 /**
mbed_official 340:28d1f895c6fe 164 * @brief Controller Area Network TxMailBox
mbed_official 340:28d1f895c6fe 165 */
mbed_official 340:28d1f895c6fe 166 typedef struct
mbed_official 340:28d1f895c6fe 167 {
mbed_official 340:28d1f895c6fe 168 __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
mbed_official 340:28d1f895c6fe 169 __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
mbed_official 340:28d1f895c6fe 170 __IO uint32_t TDLR; /*!< CAN mailbox data low register */
mbed_official 340:28d1f895c6fe 171 __IO uint32_t TDHR; /*!< CAN mailbox data high register */
mbed_official 340:28d1f895c6fe 172 }CAN_TxMailBox_TypeDef;
mbed_official 340:28d1f895c6fe 173
mbed_official 340:28d1f895c6fe 174 /**
mbed_official 340:28d1f895c6fe 175 * @brief Controller Area Network FIFOMailBox
mbed_official 340:28d1f895c6fe 176 */
mbed_official 340:28d1f895c6fe 177 typedef struct
mbed_official 340:28d1f895c6fe 178 {
mbed_official 340:28d1f895c6fe 179 __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
mbed_official 340:28d1f895c6fe 180 __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
mbed_official 340:28d1f895c6fe 181 __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
mbed_official 340:28d1f895c6fe 182 __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
mbed_official 340:28d1f895c6fe 183 }CAN_FIFOMailBox_TypeDef;
mbed_official 340:28d1f895c6fe 184
mbed_official 340:28d1f895c6fe 185 /**
mbed_official 340:28d1f895c6fe 186 * @brief Controller Area Network FilterRegister
mbed_official 340:28d1f895c6fe 187 */
mbed_official 340:28d1f895c6fe 188 typedef struct
mbed_official 340:28d1f895c6fe 189 {
mbed_official 340:28d1f895c6fe 190 __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
mbed_official 340:28d1f895c6fe 191 __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
mbed_official 340:28d1f895c6fe 192 }CAN_FilterRegister_TypeDef;
mbed_official 340:28d1f895c6fe 193
mbed_official 340:28d1f895c6fe 194 /**
mbed_official 340:28d1f895c6fe 195 * @brief Controller Area Network
mbed_official 340:28d1f895c6fe 196 */
mbed_official 340:28d1f895c6fe 197 typedef struct
mbed_official 340:28d1f895c6fe 198 {
mbed_official 340:28d1f895c6fe 199 __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
mbed_official 340:28d1f895c6fe 200 __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
mbed_official 340:28d1f895c6fe 201 __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
mbed_official 340:28d1f895c6fe 202 __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
mbed_official 340:28d1f895c6fe 203 __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
mbed_official 340:28d1f895c6fe 204 __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
mbed_official 340:28d1f895c6fe 205 __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
mbed_official 340:28d1f895c6fe 206 __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
mbed_official 340:28d1f895c6fe 207 uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
mbed_official 340:28d1f895c6fe 208 CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
mbed_official 340:28d1f895c6fe 209 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
mbed_official 340:28d1f895c6fe 210 uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
mbed_official 340:28d1f895c6fe 211 __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
mbed_official 340:28d1f895c6fe 212 __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
mbed_official 340:28d1f895c6fe 213 uint32_t RESERVED2; /*!< Reserved, 0x208 */
mbed_official 340:28d1f895c6fe 214 __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
mbed_official 340:28d1f895c6fe 215 uint32_t RESERVED3; /*!< Reserved, 0x210 */
mbed_official 340:28d1f895c6fe 216 __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
mbed_official 340:28d1f895c6fe 217 uint32_t RESERVED4; /*!< Reserved, 0x218 */
mbed_official 340:28d1f895c6fe 218 __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
mbed_official 340:28d1f895c6fe 219 uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
mbed_official 340:28d1f895c6fe 220 CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
mbed_official 340:28d1f895c6fe 221 }CAN_TypeDef;
mbed_official 340:28d1f895c6fe 222
mbed_official 340:28d1f895c6fe 223 /**
mbed_official 340:28d1f895c6fe 224 * @brief HDMI-CEC
mbed_official 340:28d1f895c6fe 225 */
mbed_official 340:28d1f895c6fe 226
mbed_official 340:28d1f895c6fe 227 typedef struct
mbed_official 340:28d1f895c6fe 228 {
mbed_official 340:28d1f895c6fe 229 __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */
mbed_official 340:28d1f895c6fe 230 __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */
mbed_official 340:28d1f895c6fe 231 __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */
mbed_official 340:28d1f895c6fe 232 __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */
mbed_official 340:28d1f895c6fe 233 __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */
mbed_official 340:28d1f895c6fe 234 __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */
mbed_official 340:28d1f895c6fe 235 }CEC_TypeDef;
mbed_official 340:28d1f895c6fe 236
mbed_official 340:28d1f895c6fe 237 /**
mbed_official 340:28d1f895c6fe 238 * @brief Comparator
mbed_official 340:28d1f895c6fe 239 */
mbed_official 340:28d1f895c6fe 240
mbed_official 340:28d1f895c6fe 241 typedef struct
mbed_official 340:28d1f895c6fe 242 {
mbed_official 340:28d1f895c6fe 243 __IO uint32_t CSR; /*!< Comparator 1 & 2 control Status register, Address offset: 0x00 */
mbed_official 340:28d1f895c6fe 244 }COMP1_2_TypeDef;
mbed_official 340:28d1f895c6fe 245
mbed_official 340:28d1f895c6fe 246 typedef struct
mbed_official 340:28d1f895c6fe 247 {
mbed_official 340:28d1f895c6fe 248 __IO uint16_t CSR; /*!< Comparator control Status register, Address offset: 0x00 */
mbed_official 340:28d1f895c6fe 249 }COMP_TypeDef;
mbed_official 340:28d1f895c6fe 250
mbed_official 340:28d1f895c6fe 251 /**
mbed_official 340:28d1f895c6fe 252 * @brief CRC calculation unit
mbed_official 340:28d1f895c6fe 253 */
mbed_official 340:28d1f895c6fe 254
mbed_official 340:28d1f895c6fe 255 typedef struct
mbed_official 340:28d1f895c6fe 256 {
mbed_official 340:28d1f895c6fe 257 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
mbed_official 340:28d1f895c6fe 258 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
mbed_official 340:28d1f895c6fe 259 uint8_t RESERVED0; /*!< Reserved, 0x05 */
mbed_official 340:28d1f895c6fe 260 uint16_t RESERVED1; /*!< Reserved, 0x06 */
mbed_official 340:28d1f895c6fe 261 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
mbed_official 340:28d1f895c6fe 262 uint32_t RESERVED2; /*!< Reserved, 0x0C */
mbed_official 340:28d1f895c6fe 263 __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
mbed_official 340:28d1f895c6fe 264 __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
mbed_official 340:28d1f895c6fe 265 }CRC_TypeDef;
mbed_official 340:28d1f895c6fe 266
mbed_official 340:28d1f895c6fe 267 /**
mbed_official 340:28d1f895c6fe 268 * @brief Clock Recovery System
mbed_official 340:28d1f895c6fe 269 */
mbed_official 340:28d1f895c6fe 270 typedef struct
mbed_official 340:28d1f895c6fe 271 {
mbed_official 340:28d1f895c6fe 272 __IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */
mbed_official 340:28d1f895c6fe 273 __IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */
mbed_official 340:28d1f895c6fe 274 __IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */
mbed_official 340:28d1f895c6fe 275 __IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */
mbed_official 340:28d1f895c6fe 276 }CRS_TypeDef;
mbed_official 340:28d1f895c6fe 277
mbed_official 340:28d1f895c6fe 278 /**
mbed_official 340:28d1f895c6fe 279 * @brief Digital to Analog Converter
mbed_official 340:28d1f895c6fe 280 */
mbed_official 340:28d1f895c6fe 281
mbed_official 340:28d1f895c6fe 282 typedef struct
mbed_official 340:28d1f895c6fe 283 {
mbed_official 340:28d1f895c6fe 284 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
mbed_official 340:28d1f895c6fe 285 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
mbed_official 340:28d1f895c6fe 286 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
mbed_official 340:28d1f895c6fe 287 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
mbed_official 340:28d1f895c6fe 288 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
mbed_official 340:28d1f895c6fe 289 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
mbed_official 340:28d1f895c6fe 290 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
mbed_official 340:28d1f895c6fe 291 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
mbed_official 340:28d1f895c6fe 292 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
mbed_official 340:28d1f895c6fe 293 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
mbed_official 340:28d1f895c6fe 294 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
mbed_official 340:28d1f895c6fe 295 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
mbed_official 340:28d1f895c6fe 296 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
mbed_official 340:28d1f895c6fe 297 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
mbed_official 340:28d1f895c6fe 298 }DAC_TypeDef;
mbed_official 340:28d1f895c6fe 299
mbed_official 340:28d1f895c6fe 300 /**
mbed_official 340:28d1f895c6fe 301 * @brief Debug MCU
mbed_official 340:28d1f895c6fe 302 */
mbed_official 340:28d1f895c6fe 303
mbed_official 340:28d1f895c6fe 304 typedef struct
mbed_official 340:28d1f895c6fe 305 {
mbed_official 340:28d1f895c6fe 306 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
mbed_official 340:28d1f895c6fe 307 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
mbed_official 340:28d1f895c6fe 308 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
mbed_official 340:28d1f895c6fe 309 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
mbed_official 340:28d1f895c6fe 310 }DBGMCU_TypeDef;
mbed_official 340:28d1f895c6fe 311
mbed_official 340:28d1f895c6fe 312 /**
mbed_official 340:28d1f895c6fe 313 * @brief DMA Controller
mbed_official 340:28d1f895c6fe 314 */
mbed_official 340:28d1f895c6fe 315
mbed_official 340:28d1f895c6fe 316 typedef struct
mbed_official 340:28d1f895c6fe 317 {
mbed_official 340:28d1f895c6fe 318 __IO uint32_t CCR; /*!< DMA channel x configuration register */
mbed_official 340:28d1f895c6fe 319 __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
mbed_official 340:28d1f895c6fe 320 __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
mbed_official 340:28d1f895c6fe 321 __IO uint32_t CMAR; /*!< DMA channel x memory address register */
mbed_official 340:28d1f895c6fe 322 }DMA_Channel_TypeDef;
mbed_official 340:28d1f895c6fe 323
mbed_official 340:28d1f895c6fe 324 typedef struct
mbed_official 340:28d1f895c6fe 325 {
mbed_official 340:28d1f895c6fe 326 __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
mbed_official 340:28d1f895c6fe 327 __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
mbed_official 441:d2c15dda23c1 328 uint32_t RESERVED0[40];/*!< Reserved as declared by channel typedef 0x08 - 0xA4 */
mbed_official 441:d2c15dda23c1 329 __IO uint32_t CSELR; /*!< Channel selection register, Address offset: 0xA8 */
mbed_official 340:28d1f895c6fe 330 }DMA_TypeDef;
mbed_official 340:28d1f895c6fe 331
mbed_official 340:28d1f895c6fe 332 /**
mbed_official 340:28d1f895c6fe 333 * @brief External Interrupt/Event Controller
mbed_official 340:28d1f895c6fe 334 */
mbed_official 340:28d1f895c6fe 335
mbed_official 340:28d1f895c6fe 336 typedef struct
mbed_official 340:28d1f895c6fe 337 {
mbed_official 340:28d1f895c6fe 338 __IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */
mbed_official 340:28d1f895c6fe 339 __IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */
mbed_official 340:28d1f895c6fe 340 __IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */
mbed_official 340:28d1f895c6fe 341 __IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */
mbed_official 340:28d1f895c6fe 342 __IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */
mbed_official 340:28d1f895c6fe 343 __IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */
mbed_official 340:28d1f895c6fe 344 }EXTI_TypeDef;
mbed_official 340:28d1f895c6fe 345
mbed_official 340:28d1f895c6fe 346 /**
mbed_official 340:28d1f895c6fe 347 * @brief FLASH Registers
mbed_official 340:28d1f895c6fe 348 */
mbed_official 340:28d1f895c6fe 349 typedef struct
mbed_official 340:28d1f895c6fe 350 {
mbed_official 340:28d1f895c6fe 351 __IO uint32_t ACR; /*!<FLASH access control register, Address offset: 0x00 */
mbed_official 340:28d1f895c6fe 352 __IO uint32_t KEYR; /*!<FLASH key register, Address offset: 0x04 */
mbed_official 340:28d1f895c6fe 353 __IO uint32_t OPTKEYR; /*!<FLASH OPT key register, Address offset: 0x08 */
mbed_official 340:28d1f895c6fe 354 __IO uint32_t SR; /*!<FLASH status register, Address offset: 0x0C */
mbed_official 340:28d1f895c6fe 355 __IO uint32_t CR; /*!<FLASH control register, Address offset: 0x10 */
mbed_official 340:28d1f895c6fe 356 __IO uint32_t AR; /*!<FLASH address register, Address offset: 0x14 */
mbed_official 340:28d1f895c6fe 357 __IO uint32_t RESERVED; /*!< Reserved, 0x18 */
mbed_official 340:28d1f895c6fe 358 __IO uint32_t OBR; /*!<FLASH option bytes register, Address offset: 0x1C */
mbed_official 340:28d1f895c6fe 359 __IO uint32_t WRPR; /*!<FLASH option bytes register, Address offset: 0x20 */
mbed_official 340:28d1f895c6fe 360 }FLASH_TypeDef;
mbed_official 340:28d1f895c6fe 361
mbed_official 340:28d1f895c6fe 362
mbed_official 340:28d1f895c6fe 363 /**
mbed_official 340:28d1f895c6fe 364 * @brief Option Bytes Registers
mbed_official 340:28d1f895c6fe 365 */
mbed_official 340:28d1f895c6fe 366 typedef struct
mbed_official 340:28d1f895c6fe 367 {
mbed_official 340:28d1f895c6fe 368 __IO uint16_t RDP; /*!< FLASH option byte Read protection, Address offset: 0x00 */
mbed_official 340:28d1f895c6fe 369 __IO uint16_t USER; /*!< FLASH option byte user options, Address offset: 0x02 */
mbed_official 340:28d1f895c6fe 370 __IO uint16_t DATA0; /*!< User data byte 0 (stored in FLASH_OBR[23:16]), Address offset: 0x04 */
mbed_official 340:28d1f895c6fe 371 __IO uint16_t DATA1; /*!< User data byte 1 (stored in FLASH_OBR[31:24]), Address offset: 0x06 */
mbed_official 340:28d1f895c6fe 372 __IO uint16_t WRP0; /*!< FLASH option byte write protection 0, Address offset: 0x08 */
mbed_official 340:28d1f895c6fe 373 __IO uint16_t WRP1; /*!< FLASH option byte write protection 1, Address offset: 0x0A */
mbed_official 340:28d1f895c6fe 374 __IO uint16_t WRP2; /*!< FLASH option byte write protection 2, Address offset: 0x0C */
mbed_official 340:28d1f895c6fe 375 __IO uint16_t WRP3; /*!< FLASH option byte write protection 3, Address offset: 0x0E */
mbed_official 340:28d1f895c6fe 376 }OB_TypeDef;
mbed_official 340:28d1f895c6fe 377
mbed_official 340:28d1f895c6fe 378 /**
mbed_official 340:28d1f895c6fe 379 * @brief General Purpose I/O
mbed_official 340:28d1f895c6fe 380 */
mbed_official 340:28d1f895c6fe 381
mbed_official 340:28d1f895c6fe 382 typedef struct
mbed_official 340:28d1f895c6fe 383 {
mbed_official 340:28d1f895c6fe 384 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
mbed_official 340:28d1f895c6fe 385 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
mbed_official 340:28d1f895c6fe 386 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
mbed_official 340:28d1f895c6fe 387 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
mbed_official 340:28d1f895c6fe 388 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
mbed_official 340:28d1f895c6fe 389 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
mbed_official 340:28d1f895c6fe 390 __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x1A */
mbed_official 340:28d1f895c6fe 391 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
mbed_official 340:28d1f895c6fe 392 __IO uint32_t AFR[2]; /*!< GPIO alternate function low register, Address offset: 0x20-0x24 */
mbed_official 340:28d1f895c6fe 393 __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
mbed_official 340:28d1f895c6fe 394 }GPIO_TypeDef;
mbed_official 340:28d1f895c6fe 395
mbed_official 340:28d1f895c6fe 396 /**
mbed_official 340:28d1f895c6fe 397 * @brief SysTem Configuration
mbed_official 340:28d1f895c6fe 398 */
mbed_official 340:28d1f895c6fe 399
mbed_official 340:28d1f895c6fe 400 typedef struct
mbed_official 340:28d1f895c6fe 401 {
mbed_official 340:28d1f895c6fe 402 __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
mbed_official 340:28d1f895c6fe 403 uint32_t RESERVED; /*!< Reserved, 0x04 */
mbed_official 340:28d1f895c6fe 404 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration register, Address offset: 0x14-0x08 */
mbed_official 340:28d1f895c6fe 405 __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */
mbed_official 340:28d1f895c6fe 406 uint32_t RESERVED1[25]; /*!< Reserved + COMP, 0x1C */
mbed_official 340:28d1f895c6fe 407 __IO uint32_t IT_LINE_SR[32]; /*!< SYSCFG configuration IT_LINE register, Address offset: 0x80 */
mbed_official 340:28d1f895c6fe 408
mbed_official 340:28d1f895c6fe 409 }SYSCFG_TypeDef;
mbed_official 340:28d1f895c6fe 410
mbed_official 340:28d1f895c6fe 411 /**
mbed_official 340:28d1f895c6fe 412 * @brief Inter-integrated Circuit Interface
mbed_official 340:28d1f895c6fe 413 */
mbed_official 340:28d1f895c6fe 414
mbed_official 340:28d1f895c6fe 415 typedef struct
mbed_official 340:28d1f895c6fe 416 {
mbed_official 340:28d1f895c6fe 417 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
mbed_official 340:28d1f895c6fe 418 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
mbed_official 340:28d1f895c6fe 419 __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
mbed_official 340:28d1f895c6fe 420 __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
mbed_official 340:28d1f895c6fe 421 __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
mbed_official 340:28d1f895c6fe 422 __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
mbed_official 340:28d1f895c6fe 423 __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
mbed_official 340:28d1f895c6fe 424 __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
mbed_official 340:28d1f895c6fe 425 __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
mbed_official 340:28d1f895c6fe 426 __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
mbed_official 340:28d1f895c6fe 427 __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
mbed_official 340:28d1f895c6fe 428 }I2C_TypeDef;
mbed_official 340:28d1f895c6fe 429
mbed_official 340:28d1f895c6fe 430 /**
mbed_official 340:28d1f895c6fe 431 * @brief Independent WATCHDOG
mbed_official 340:28d1f895c6fe 432 */
mbed_official 340:28d1f895c6fe 433
mbed_official 340:28d1f895c6fe 434 typedef struct
mbed_official 340:28d1f895c6fe 435 {
mbed_official 340:28d1f895c6fe 436 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
mbed_official 340:28d1f895c6fe 437 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
mbed_official 340:28d1f895c6fe 438 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
mbed_official 340:28d1f895c6fe 439 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
mbed_official 340:28d1f895c6fe 440 __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
mbed_official 340:28d1f895c6fe 441 }IWDG_TypeDef;
mbed_official 340:28d1f895c6fe 442
mbed_official 340:28d1f895c6fe 443 /**
mbed_official 340:28d1f895c6fe 444 * @brief Power Control
mbed_official 340:28d1f895c6fe 445 */
mbed_official 340:28d1f895c6fe 446
mbed_official 340:28d1f895c6fe 447 typedef struct
mbed_official 340:28d1f895c6fe 448 {
mbed_official 340:28d1f895c6fe 449 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
mbed_official 340:28d1f895c6fe 450 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
mbed_official 340:28d1f895c6fe 451 }PWR_TypeDef;
mbed_official 340:28d1f895c6fe 452
mbed_official 340:28d1f895c6fe 453 /**
mbed_official 340:28d1f895c6fe 454 * @brief Reset and Clock Control
mbed_official 340:28d1f895c6fe 455 */
mbed_official 340:28d1f895c6fe 456 typedef struct
mbed_official 340:28d1f895c6fe 457 {
mbed_official 340:28d1f895c6fe 458 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
mbed_official 340:28d1f895c6fe 459 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x04 */
mbed_official 340:28d1f895c6fe 460 __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x08 */
mbed_official 340:28d1f895c6fe 461 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x0C */
mbed_official 340:28d1f895c6fe 462 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x10 */
mbed_official 340:28d1f895c6fe 463 __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock register, Address offset: 0x14 */
mbed_official 340:28d1f895c6fe 464 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x18 */
mbed_official 340:28d1f895c6fe 465 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x1C */
mbed_official 340:28d1f895c6fe 466 __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x20 */
mbed_official 340:28d1f895c6fe 467 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x24 */
mbed_official 340:28d1f895c6fe 468 __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x28 */
mbed_official 340:28d1f895c6fe 469 __IO uint32_t CFGR2; /*!< RCC clock configuration register 2, Address offset: 0x2C */
mbed_official 340:28d1f895c6fe 470 __IO uint32_t CFGR3; /*!< RCC clock configuration register 3, Address offset: 0x30 */
mbed_official 340:28d1f895c6fe 471 __IO uint32_t CR2; /*!< RCC clock control register 2, Address offset: 0x34 */
mbed_official 340:28d1f895c6fe 472 }RCC_TypeDef;
mbed_official 340:28d1f895c6fe 473
mbed_official 340:28d1f895c6fe 474 /**
mbed_official 340:28d1f895c6fe 475 * @brief Real-Time Clock
mbed_official 340:28d1f895c6fe 476 */
mbed_official 340:28d1f895c6fe 477
mbed_official 340:28d1f895c6fe 478 typedef struct
mbed_official 340:28d1f895c6fe 479 {
mbed_official 340:28d1f895c6fe 480 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
mbed_official 340:28d1f895c6fe 481 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
mbed_official 340:28d1f895c6fe 482 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
mbed_official 340:28d1f895c6fe 483 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
mbed_official 340:28d1f895c6fe 484 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
mbed_official 340:28d1f895c6fe 485 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
mbed_official 340:28d1f895c6fe 486 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x18 */
mbed_official 340:28d1f895c6fe 487 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
mbed_official 340:28d1f895c6fe 488 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x20 */
mbed_official 340:28d1f895c6fe 489 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
mbed_official 340:28d1f895c6fe 490 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
mbed_official 340:28d1f895c6fe 491 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
mbed_official 340:28d1f895c6fe 492 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
mbed_official 340:28d1f895c6fe 493 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
mbed_official 340:28d1f895c6fe 494 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
mbed_official 340:28d1f895c6fe 495 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
mbed_official 340:28d1f895c6fe 496 __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
mbed_official 340:28d1f895c6fe 497 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
mbed_official 340:28d1f895c6fe 498 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x48 */
mbed_official 340:28d1f895c6fe 499 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x4C */
mbed_official 340:28d1f895c6fe 500 __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
mbed_official 340:28d1f895c6fe 501 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
mbed_official 340:28d1f895c6fe 502 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
mbed_official 340:28d1f895c6fe 503 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
mbed_official 340:28d1f895c6fe 504 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
mbed_official 340:28d1f895c6fe 505 }RTC_TypeDef;
mbed_official 340:28d1f895c6fe 506
mbed_official 340:28d1f895c6fe 507 /**
mbed_official 340:28d1f895c6fe 508 * @brief Serial Peripheral Interface
mbed_official 340:28d1f895c6fe 509 */
mbed_official 340:28d1f895c6fe 510
mbed_official 340:28d1f895c6fe 511 typedef struct
mbed_official 340:28d1f895c6fe 512 {
mbed_official 441:d2c15dda23c1 513 __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */
mbed_official 441:d2c15dda23c1 514 __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
mbed_official 441:d2c15dda23c1 515 __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
mbed_official 441:d2c15dda23c1 516 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
mbed_official 441:d2c15dda23c1 517 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
mbed_official 441:d2c15dda23c1 518 __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */
mbed_official 441:d2c15dda23c1 519 __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */
mbed_official 441:d2c15dda23c1 520 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
mbed_official 441:d2c15dda23c1 521 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
mbed_official 340:28d1f895c6fe 522 }SPI_TypeDef;
mbed_official 340:28d1f895c6fe 523
mbed_official 340:28d1f895c6fe 524 /**
mbed_official 340:28d1f895c6fe 525 * @brief TIM
mbed_official 340:28d1f895c6fe 526 */
mbed_official 340:28d1f895c6fe 527 typedef struct
mbed_official 340:28d1f895c6fe 528 {
mbed_official 340:28d1f895c6fe 529 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
mbed_official 340:28d1f895c6fe 530 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
mbed_official 340:28d1f895c6fe 531 __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */
mbed_official 340:28d1f895c6fe 532 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
mbed_official 340:28d1f895c6fe 533 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
mbed_official 340:28d1f895c6fe 534 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
mbed_official 340:28d1f895c6fe 535 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
mbed_official 340:28d1f895c6fe 536 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
mbed_official 340:28d1f895c6fe 537 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
mbed_official 340:28d1f895c6fe 538 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
mbed_official 340:28d1f895c6fe 539 __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
mbed_official 340:28d1f895c6fe 540 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
mbed_official 340:28d1f895c6fe 541 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
mbed_official 340:28d1f895c6fe 542 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
mbed_official 340:28d1f895c6fe 543 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
mbed_official 340:28d1f895c6fe 544 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
mbed_official 340:28d1f895c6fe 545 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
mbed_official 340:28d1f895c6fe 546 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
mbed_official 340:28d1f895c6fe 547 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
mbed_official 340:28d1f895c6fe 548 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */
mbed_official 340:28d1f895c6fe 549 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
mbed_official 340:28d1f895c6fe 550 }TIM_TypeDef;
mbed_official 340:28d1f895c6fe 551
mbed_official 340:28d1f895c6fe 552 /**
mbed_official 340:28d1f895c6fe 553 * @brief Touch Sensing Controller (TSC)
mbed_official 340:28d1f895c6fe 554 */
mbed_official 340:28d1f895c6fe 555 typedef struct
mbed_official 340:28d1f895c6fe 556 {
mbed_official 340:28d1f895c6fe 557 __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */
mbed_official 340:28d1f895c6fe 558 __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */
mbed_official 340:28d1f895c6fe 559 __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */
mbed_official 340:28d1f895c6fe 560 __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */
mbed_official 340:28d1f895c6fe 561 __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */
mbed_official 340:28d1f895c6fe 562 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
mbed_official 340:28d1f895c6fe 563 __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */
mbed_official 340:28d1f895c6fe 564 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */
mbed_official 340:28d1f895c6fe 565 __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */
mbed_official 340:28d1f895c6fe 566 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */
mbed_official 340:28d1f895c6fe 567 __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */
mbed_official 340:28d1f895c6fe 568 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */
mbed_official 340:28d1f895c6fe 569 __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */
mbed_official 340:28d1f895c6fe 570 __IO uint32_t IOGXCR[8]; /*!< TSC I/O group x counter register, Address offset: 0x34-50 */
mbed_official 340:28d1f895c6fe 571 }TSC_TypeDef;
mbed_official 340:28d1f895c6fe 572
mbed_official 340:28d1f895c6fe 573 /**
mbed_official 340:28d1f895c6fe 574 * @brief Universal Synchronous Asynchronous Receiver Transmitter
mbed_official 340:28d1f895c6fe 575 */
mbed_official 340:28d1f895c6fe 576
mbed_official 340:28d1f895c6fe 577 typedef struct
mbed_official 340:28d1f895c6fe 578 {
mbed_official 340:28d1f895c6fe 579 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
mbed_official 340:28d1f895c6fe 580 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
mbed_official 340:28d1f895c6fe 581 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
mbed_official 340:28d1f895c6fe 582 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
mbed_official 340:28d1f895c6fe 583 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
mbed_official 340:28d1f895c6fe 584 __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
mbed_official 340:28d1f895c6fe 585 __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
mbed_official 340:28d1f895c6fe 586 __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
mbed_official 340:28d1f895c6fe 587 __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
mbed_official 340:28d1f895c6fe 588 __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
mbed_official 340:28d1f895c6fe 589 uint16_t RESERVED1; /*!< Reserved, 0x26 */
mbed_official 340:28d1f895c6fe 590 __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
mbed_official 340:28d1f895c6fe 591 uint16_t RESERVED2; /*!< Reserved, 0x2A */
mbed_official 340:28d1f895c6fe 592 }USART_TypeDef;
mbed_official 340:28d1f895c6fe 593
mbed_official 340:28d1f895c6fe 594 /**
mbed_official 340:28d1f895c6fe 595 * @brief Window WATCHDOG
mbed_official 340:28d1f895c6fe 596 */
mbed_official 340:28d1f895c6fe 597 typedef struct
mbed_official 340:28d1f895c6fe 598 {
mbed_official 340:28d1f895c6fe 599 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
mbed_official 340:28d1f895c6fe 600 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
mbed_official 340:28d1f895c6fe 601 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
mbed_official 340:28d1f895c6fe 602 }WWDG_TypeDef;
mbed_official 340:28d1f895c6fe 603
mbed_official 340:28d1f895c6fe 604 /**
mbed_official 340:28d1f895c6fe 605 * @}
mbed_official 340:28d1f895c6fe 606 */
mbed_official 340:28d1f895c6fe 607
mbed_official 340:28d1f895c6fe 608 /** @addtogroup Peripheral_memory_map
mbed_official 340:28d1f895c6fe 609 * @{
mbed_official 340:28d1f895c6fe 610 */
mbed_official 340:28d1f895c6fe 611
mbed_official 340:28d1f895c6fe 612 #define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
mbed_official 340:28d1f895c6fe 613 #define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
mbed_official 340:28d1f895c6fe 614 #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
mbed_official 340:28d1f895c6fe 615
mbed_official 340:28d1f895c6fe 616 /*!< Peripheral memory map */
mbed_official 340:28d1f895c6fe 617 #define APBPERIPH_BASE PERIPH_BASE
mbed_official 340:28d1f895c6fe 618 #define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000)
mbed_official 340:28d1f895c6fe 619 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000)
mbed_official 340:28d1f895c6fe 620
mbed_official 340:28d1f895c6fe 621 #define TIM2_BASE (APBPERIPH_BASE + 0x00000000)
mbed_official 340:28d1f895c6fe 622 #define TIM3_BASE (APBPERIPH_BASE + 0x00000400)
mbed_official 340:28d1f895c6fe 623 #define TIM6_BASE (APBPERIPH_BASE + 0x00001000)
mbed_official 340:28d1f895c6fe 624 #define TIM7_BASE (APBPERIPH_BASE + 0x00001400)
mbed_official 340:28d1f895c6fe 625 #define TIM14_BASE (APBPERIPH_BASE + 0x00002000)
mbed_official 340:28d1f895c6fe 626 #define RTC_BASE (APBPERIPH_BASE + 0x00002800)
mbed_official 340:28d1f895c6fe 627 #define WWDG_BASE (APBPERIPH_BASE + 0x00002C00)
mbed_official 340:28d1f895c6fe 628 #define IWDG_BASE (APBPERIPH_BASE + 0x00003000)
mbed_official 340:28d1f895c6fe 629 #define SPI2_BASE (APBPERIPH_BASE + 0x00003800)
mbed_official 340:28d1f895c6fe 630 #define USART2_BASE (APBPERIPH_BASE + 0x00004400)
mbed_official 340:28d1f895c6fe 631 #define USART3_BASE (APBPERIPH_BASE + 0x00004800)
mbed_official 340:28d1f895c6fe 632 #define USART4_BASE (APBPERIPH_BASE + 0x00004C00)
mbed_official 340:28d1f895c6fe 633 #define USART5_BASE (APBPERIPH_BASE + 0x00005000)
mbed_official 340:28d1f895c6fe 634 #define I2C1_BASE (APBPERIPH_BASE + 0x00005400)
mbed_official 340:28d1f895c6fe 635 #define I2C2_BASE (APBPERIPH_BASE + 0x00005800)
mbed_official 340:28d1f895c6fe 636 #define CAN_BASE (APBPERIPH_BASE + 0x00006400)
mbed_official 340:28d1f895c6fe 637 #define CRS_BASE (APBPERIPH_BASE + 0x00006C00)
mbed_official 340:28d1f895c6fe 638 #define PWR_BASE (APBPERIPH_BASE + 0x00007000)
mbed_official 340:28d1f895c6fe 639 #define DAC_BASE (APBPERIPH_BASE + 0x00007400)
mbed_official 340:28d1f895c6fe 640 #define CEC_BASE (APBPERIPH_BASE + 0x00007800)
mbed_official 340:28d1f895c6fe 641
mbed_official 340:28d1f895c6fe 642 #define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000)
mbed_official 340:28d1f895c6fe 643 #define COMP_BASE (APBPERIPH_BASE + 0x0001001C)
mbed_official 340:28d1f895c6fe 644 #define EXTI_BASE (APBPERIPH_BASE + 0x00010400)
mbed_official 340:28d1f895c6fe 645 #define USART6_BASE (APBPERIPH_BASE + 0x00011400)
mbed_official 340:28d1f895c6fe 646 #define USART7_BASE (APBPERIPH_BASE + 0x00011800)
mbed_official 340:28d1f895c6fe 647 #define USART8_BASE (APBPERIPH_BASE + 0x00011C00)
mbed_official 340:28d1f895c6fe 648 #define ADC1_BASE (APBPERIPH_BASE + 0x00012400)
mbed_official 340:28d1f895c6fe 649 #define ADC_BASE (APBPERIPH_BASE + 0x00012708)
mbed_official 340:28d1f895c6fe 650 #define TIM1_BASE (APBPERIPH_BASE + 0x00012C00)
mbed_official 340:28d1f895c6fe 651 #define SPI1_BASE (APBPERIPH_BASE + 0x00013000)
mbed_official 340:28d1f895c6fe 652 #define USART1_BASE (APBPERIPH_BASE + 0x00013800)
mbed_official 340:28d1f895c6fe 653 #define TIM15_BASE (APBPERIPH_BASE + 0x00014000)
mbed_official 340:28d1f895c6fe 654 #define TIM16_BASE (APBPERIPH_BASE + 0x00014400)
mbed_official 340:28d1f895c6fe 655 #define TIM17_BASE (APBPERIPH_BASE + 0x00014800)
mbed_official 340:28d1f895c6fe 656 #define DBGMCU_BASE (APBPERIPH_BASE + 0x00015800)
mbed_official 340:28d1f895c6fe 657
mbed_official 340:28d1f895c6fe 658 /*!< AHB1 peripherals */
mbed_official 340:28d1f895c6fe 659 #define DMA1_BASE (AHBPERIPH_BASE + 0x00000000)
mbed_official 340:28d1f895c6fe 660 #define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008)
mbed_official 340:28d1f895c6fe 661 #define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001C)
mbed_official 340:28d1f895c6fe 662 #define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030)
mbed_official 340:28d1f895c6fe 663 #define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044)
mbed_official 340:28d1f895c6fe 664 #define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058)
mbed_official 340:28d1f895c6fe 665 #define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006C)
mbed_official 340:28d1f895c6fe 666 #define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080)
mbed_official 340:28d1f895c6fe 667 #define DMA2_BASE (AHBPERIPH_BASE + 0x00000400)
mbed_official 340:28d1f895c6fe 668 #define DMA2_Channel1_BASE (DMA2_BASE + 0x00000008)
mbed_official 340:28d1f895c6fe 669 #define DMA2_Channel2_BASE (DMA2_BASE + 0x0000001C)
mbed_official 340:28d1f895c6fe 670 #define DMA2_Channel3_BASE (DMA2_BASE + 0x00000030)
mbed_official 340:28d1f895c6fe 671 #define DMA2_Channel4_BASE (DMA2_BASE + 0x00000044)
mbed_official 340:28d1f895c6fe 672 #define DMA2_Channel5_BASE (DMA2_BASE + 0x00000058)
mbed_official 340:28d1f895c6fe 673
mbed_official 340:28d1f895c6fe 674 #define RCC_BASE (AHBPERIPH_BASE + 0x00001000)
mbed_official 340:28d1f895c6fe 675 #define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000) /*!< FLASH registers base address */
mbed_official 340:28d1f895c6fe 676 #define OB_BASE ((uint32_t)0x1FFFF800) /*!< FLASH Option Bytes base address */
mbed_official 340:28d1f895c6fe 677 #define CRC_BASE (AHBPERIPH_BASE + 0x00003000)
mbed_official 340:28d1f895c6fe 678 #define TSC_BASE (AHBPERIPH_BASE + 0x00004000)
mbed_official 340:28d1f895c6fe 679
mbed_official 340:28d1f895c6fe 680 #define GPIOA_BASE (AHB2PERIPH_BASE + 0x00000000)
mbed_official 340:28d1f895c6fe 681 #define GPIOB_BASE (AHB2PERIPH_BASE + 0x00000400)
mbed_official 340:28d1f895c6fe 682 #define GPIOC_BASE (AHB2PERIPH_BASE + 0x00000800)
mbed_official 340:28d1f895c6fe 683 #define GPIOD_BASE (AHB2PERIPH_BASE + 0x00000C00)
mbed_official 340:28d1f895c6fe 684 #define GPIOE_BASE (AHB2PERIPH_BASE + 0x00001000)
mbed_official 340:28d1f895c6fe 685 #define GPIOF_BASE (AHB2PERIPH_BASE + 0x00001400)
mbed_official 340:28d1f895c6fe 686
mbed_official 340:28d1f895c6fe 687 /**
mbed_official 340:28d1f895c6fe 688 * @}
mbed_official 340:28d1f895c6fe 689 */
mbed_official 340:28d1f895c6fe 690
mbed_official 340:28d1f895c6fe 691 /** @addtogroup Peripheral_declaration
mbed_official 340:28d1f895c6fe 692 * @{
mbed_official 340:28d1f895c6fe 693 */
mbed_official 340:28d1f895c6fe 694
mbed_official 340:28d1f895c6fe 695 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
mbed_official 340:28d1f895c6fe 696 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
mbed_official 340:28d1f895c6fe 697 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
mbed_official 340:28d1f895c6fe 698 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
mbed_official 340:28d1f895c6fe 699 #define TIM14 ((TIM_TypeDef *) TIM14_BASE)
mbed_official 340:28d1f895c6fe 700 #define RTC ((RTC_TypeDef *) RTC_BASE)
mbed_official 340:28d1f895c6fe 701 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
mbed_official 340:28d1f895c6fe 702 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
mbed_official 340:28d1f895c6fe 703 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
mbed_official 340:28d1f895c6fe 704 #define USART2 ((USART_TypeDef *) USART2_BASE)
mbed_official 340:28d1f895c6fe 705 #define USART3 ((USART_TypeDef *) USART3_BASE)
mbed_official 340:28d1f895c6fe 706 #define USART4 ((USART_TypeDef *) USART4_BASE)
mbed_official 340:28d1f895c6fe 707 #define USART5 ((USART_TypeDef *) USART5_BASE)
mbed_official 340:28d1f895c6fe 708 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
mbed_official 340:28d1f895c6fe 709 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
mbed_official 340:28d1f895c6fe 710 #define CAN ((CAN_TypeDef *) CAN_BASE)
mbed_official 340:28d1f895c6fe 711 #define CRS ((CRS_TypeDef *) CRS_BASE)
mbed_official 340:28d1f895c6fe 712 #define PWR ((PWR_TypeDef *) PWR_BASE)
mbed_official 340:28d1f895c6fe 713 #define DAC ((DAC_TypeDef *) DAC_BASE)
mbed_official 340:28d1f895c6fe 714 #define CEC ((CEC_TypeDef *) CEC_BASE)
mbed_official 340:28d1f895c6fe 715 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
mbed_official 340:28d1f895c6fe 716 #define COMP ((COMP1_2_TypeDef *) COMP_BASE)
mbed_official 340:28d1f895c6fe 717 #define COMP1 ((COMP_TypeDef *) COMP_BASE)
mbed_official 340:28d1f895c6fe 718 #define COMP2 ((COMP_TypeDef *) (COMP_BASE + 0x00000002))
mbed_official 340:28d1f895c6fe 719 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
mbed_official 340:28d1f895c6fe 720 #define USART6 ((USART_TypeDef *) USART6_BASE)
mbed_official 340:28d1f895c6fe 721 #define USART7 ((USART_TypeDef *) USART7_BASE)
mbed_official 340:28d1f895c6fe 722 #define USART8 ((USART_TypeDef *) USART8_BASE)
mbed_official 340:28d1f895c6fe 723 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
mbed_official 340:28d1f895c6fe 724 #define ADC ((ADC_Common_TypeDef *) ADC_BASE)
mbed_official 340:28d1f895c6fe 725 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
mbed_official 340:28d1f895c6fe 726 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
mbed_official 340:28d1f895c6fe 727 #define USART1 ((USART_TypeDef *) USART1_BASE)
mbed_official 340:28d1f895c6fe 728 #define TIM15 ((TIM_TypeDef *) TIM15_BASE)
mbed_official 340:28d1f895c6fe 729 #define TIM16 ((TIM_TypeDef *) TIM16_BASE)
mbed_official 340:28d1f895c6fe 730 #define TIM17 ((TIM_TypeDef *) TIM17_BASE)
mbed_official 340:28d1f895c6fe 731 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
mbed_official 340:28d1f895c6fe 732 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
mbed_official 340:28d1f895c6fe 733 #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
mbed_official 340:28d1f895c6fe 734 #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
mbed_official 340:28d1f895c6fe 735 #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
mbed_official 340:28d1f895c6fe 736 #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
mbed_official 340:28d1f895c6fe 737 #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
mbed_official 340:28d1f895c6fe 738 #define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
mbed_official 340:28d1f895c6fe 739 #define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
mbed_official 340:28d1f895c6fe 740 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
mbed_official 340:28d1f895c6fe 741 #define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
mbed_official 340:28d1f895c6fe 742 #define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
mbed_official 340:28d1f895c6fe 743 #define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
mbed_official 340:28d1f895c6fe 744 #define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
mbed_official 340:28d1f895c6fe 745 #define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
mbed_official 340:28d1f895c6fe 746 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
mbed_official 340:28d1f895c6fe 747 #define OB ((OB_TypeDef *) OB_BASE)
mbed_official 340:28d1f895c6fe 748 #define RCC ((RCC_TypeDef *) RCC_BASE)
mbed_official 340:28d1f895c6fe 749 #define CRC ((CRC_TypeDef *) CRC_BASE)
mbed_official 340:28d1f895c6fe 750 #define TSC ((TSC_TypeDef *) TSC_BASE)
mbed_official 340:28d1f895c6fe 751 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
mbed_official 340:28d1f895c6fe 752 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
mbed_official 340:28d1f895c6fe 753 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
mbed_official 340:28d1f895c6fe 754 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
mbed_official 340:28d1f895c6fe 755 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
mbed_official 340:28d1f895c6fe 756 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
mbed_official 340:28d1f895c6fe 757
mbed_official 340:28d1f895c6fe 758 /**
mbed_official 340:28d1f895c6fe 759 * @}
mbed_official 340:28d1f895c6fe 760 */
mbed_official 340:28d1f895c6fe 761
mbed_official 340:28d1f895c6fe 762 /** @addtogroup Exported_constants
mbed_official 340:28d1f895c6fe 763 * @{
mbed_official 340:28d1f895c6fe 764 */
mbed_official 340:28d1f895c6fe 765
mbed_official 340:28d1f895c6fe 766 /** @addtogroup Peripheral_Registers_Bits_Definition
mbed_official 340:28d1f895c6fe 767 * @{
mbed_official 340:28d1f895c6fe 768 */
mbed_official 340:28d1f895c6fe 769
mbed_official 340:28d1f895c6fe 770 /******************************************************************************/
mbed_official 340:28d1f895c6fe 771 /* Peripheral Registers Bits Definition */
mbed_official 340:28d1f895c6fe 772 /******************************************************************************/
mbed_official 340:28d1f895c6fe 773 /******************************************************************************/
mbed_official 340:28d1f895c6fe 774 /* */
mbed_official 340:28d1f895c6fe 775 /* Analog to Digital Converter (ADC) */
mbed_official 340:28d1f895c6fe 776 /* */
mbed_official 340:28d1f895c6fe 777 /******************************************************************************/
mbed_official 340:28d1f895c6fe 778 /******************** Bits definition for ADC_ISR register ******************/
mbed_official 340:28d1f895c6fe 779 #define ADC_ISR_AWD ((uint32_t)0x00000080) /*!< Analog watchdog flag */
mbed_official 340:28d1f895c6fe 780 #define ADC_ISR_OVR ((uint32_t)0x00000010) /*!< Overrun flag */
mbed_official 340:28d1f895c6fe 781 #define ADC_ISR_EOSEQ ((uint32_t)0x00000008) /*!< End of Sequence flag */
mbed_official 340:28d1f895c6fe 782 #define ADC_ISR_EOC ((uint32_t)0x00000004) /*!< End of Conversion */
mbed_official 340:28d1f895c6fe 783 #define ADC_ISR_EOSMP ((uint32_t)0x00000002) /*!< End of sampling flag */
mbed_official 340:28d1f895c6fe 784 #define ADC_ISR_ADRDY ((uint32_t)0x00000001) /*!< ADC Ready */
mbed_official 340:28d1f895c6fe 785
mbed_official 340:28d1f895c6fe 786 /* Old EOSEQ bit definition, maintained for legacy purpose */
mbed_official 340:28d1f895c6fe 787 #define ADC_ISR_EOS ADC_ISR_EOSEQ
mbed_official 340:28d1f895c6fe 788
mbed_official 340:28d1f895c6fe 789 /******************** Bits definition for ADC_IER register ******************/
mbed_official 340:28d1f895c6fe 790 #define ADC_IER_AWDIE ((uint32_t)0x00000080) /*!< Analog Watchdog interrupt enable */
mbed_official 340:28d1f895c6fe 791 #define ADC_IER_OVRIE ((uint32_t)0x00000010) /*!< Overrun interrupt enable */
mbed_official 340:28d1f895c6fe 792 #define ADC_IER_EOSEQIE ((uint32_t)0x00000008) /*!< End of Sequence of conversion interrupt enable */
mbed_official 340:28d1f895c6fe 793 #define ADC_IER_EOCIE ((uint32_t)0x00000004) /*!< End of Conversion interrupt enable */
mbed_official 340:28d1f895c6fe 794 #define ADC_IER_EOSMPIE ((uint32_t)0x00000002) /*!< End of sampling interrupt enable */
mbed_official 340:28d1f895c6fe 795 #define ADC_IER_ADRDYIE ((uint32_t)0x00000001) /*!< ADC Ready interrupt enable */
mbed_official 340:28d1f895c6fe 796
mbed_official 340:28d1f895c6fe 797 /* Old EOSEQIE bit definition, maintained for legacy purpose */
mbed_official 340:28d1f895c6fe 798 #define ADC_IER_EOSIE ADC_IER_EOSEQIE
mbed_official 340:28d1f895c6fe 799
mbed_official 340:28d1f895c6fe 800 /******************** Bits definition for ADC_CR register *******************/
mbed_official 340:28d1f895c6fe 801 #define ADC_CR_ADCAL ((uint32_t)0x80000000) /*!< ADC calibration */
mbed_official 340:28d1f895c6fe 802 #define ADC_CR_ADSTP ((uint32_t)0x00000010) /*!< ADC stop of conversion command */
mbed_official 340:28d1f895c6fe 803 #define ADC_CR_ADSTART ((uint32_t)0x00000004) /*!< ADC start of conversion */
mbed_official 340:28d1f895c6fe 804 #define ADC_CR_ADDIS ((uint32_t)0x00000002) /*!< ADC disable command */
mbed_official 340:28d1f895c6fe 805 #define ADC_CR_ADEN ((uint32_t)0x00000001) /*!< ADC enable control */
mbed_official 340:28d1f895c6fe 806
mbed_official 340:28d1f895c6fe 807 /******************* Bits definition for ADC_CFGR1 register *****************/
mbed_official 340:28d1f895c6fe 808 #define ADC_CFGR1_AWDCH ((uint32_t)0x7C000000) /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
mbed_official 340:28d1f895c6fe 809 #define ADC_CFGR1_AWDCH_0 ((uint32_t)0x04000000) /*!< Bit 0 */
mbed_official 340:28d1f895c6fe 810 #define ADC_CFGR1_AWDCH_1 ((uint32_t)0x08000000) /*!< Bit 1 */
mbed_official 340:28d1f895c6fe 811 #define ADC_CFGR1_AWDCH_2 ((uint32_t)0x10000000) /*!< Bit 2 */
mbed_official 340:28d1f895c6fe 812 #define ADC_CFGR1_AWDCH_3 ((uint32_t)0x20000000) /*!< Bit 3 */
mbed_official 340:28d1f895c6fe 813 #define ADC_CFGR1_AWDCH_4 ((uint32_t)0x40000000) /*!< Bit 4 */
mbed_official 340:28d1f895c6fe 814 #define ADC_CFGR1_AWDEN ((uint32_t)0x00800000) /*!< Analog watchdog enable on regular channels */
mbed_official 340:28d1f895c6fe 815 #define ADC_CFGR1_AWDSGL ((uint32_t)0x00400000) /*!< Enable the watchdog on a single channel or on all channels */
mbed_official 340:28d1f895c6fe 816 #define ADC_CFGR1_DISCEN ((uint32_t)0x00010000) /*!< Discontinuous mode on regular channels */
mbed_official 340:28d1f895c6fe 817 #define ADC_CFGR1_AUTOFF ((uint32_t)0x00008000) /*!< ADC auto power off */
mbed_official 340:28d1f895c6fe 818 #define ADC_CFGR1_WAIT ((uint32_t)0x00004000) /*!< ADC wait conversion mode */
mbed_official 340:28d1f895c6fe 819 #define ADC_CFGR1_CONT ((uint32_t)0x00002000) /*!< Continuous Conversion */
mbed_official 340:28d1f895c6fe 820 #define ADC_CFGR1_OVRMOD ((uint32_t)0x00001000) /*!< Overrun mode */
mbed_official 340:28d1f895c6fe 821 #define ADC_CFGR1_EXTEN ((uint32_t)0x00000C00) /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */
mbed_official 340:28d1f895c6fe 822 #define ADC_CFGR1_EXTEN_0 ((uint32_t)0x00000400) /*!< Bit 0 */
mbed_official 340:28d1f895c6fe 823 #define ADC_CFGR1_EXTEN_1 ((uint32_t)0x00000800) /*!< Bit 1 */
mbed_official 340:28d1f895c6fe 824 #define ADC_CFGR1_EXTSEL ((uint32_t)0x000001C0) /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
mbed_official 340:28d1f895c6fe 825 #define ADC_CFGR1_EXTSEL_0 ((uint32_t)0x00000040) /*!< Bit 0 */
mbed_official 340:28d1f895c6fe 826 #define ADC_CFGR1_EXTSEL_1 ((uint32_t)0x00000080) /*!< Bit 1 */
mbed_official 340:28d1f895c6fe 827 #define ADC_CFGR1_EXTSEL_2 ((uint32_t)0x00000100) /*!< Bit 2 */
mbed_official 340:28d1f895c6fe 828 #define ADC_CFGR1_ALIGN ((uint32_t)0x00000020) /*!< Data Alignment */
mbed_official 340:28d1f895c6fe 829 #define ADC_CFGR1_RES ((uint32_t)0x00000018) /*!< RES[1:0] bits (Resolution) */
mbed_official 340:28d1f895c6fe 830 #define ADC_CFGR1_RES_0 ((uint32_t)0x00000008) /*!< Bit 0 */
mbed_official 340:28d1f895c6fe 831 #define ADC_CFGR1_RES_1 ((uint32_t)0x00000010) /*!< Bit 1 */
mbed_official 340:28d1f895c6fe 832 #define ADC_CFGR1_SCANDIR ((uint32_t)0x00000004) /*!< Sequence scan direction */
mbed_official 340:28d1f895c6fe 833 #define ADC_CFGR1_DMACFG ((uint32_t)0x00000002) /*!< Direct memory access configuration */
mbed_official 340:28d1f895c6fe 834 #define ADC_CFGR1_DMAEN ((uint32_t)0x00000001) /*!< Direct memory access enable */
mbed_official 340:28d1f895c6fe 835
mbed_official 340:28d1f895c6fe 836 /* Old WAIT bit definition, maintained for legacy purpose */
mbed_official 340:28d1f895c6fe 837 #define ADC_CFGR1_AUTDLY ADC_CFGR1_WAIT
mbed_official 340:28d1f895c6fe 838
mbed_official 340:28d1f895c6fe 839 /******************* Bits definition for ADC_CFGR2 register *****************/
mbed_official 340:28d1f895c6fe 840 #define ADC_CFGR2_CKMODE ((uint32_t)0xC0000000) /*!< ADC clock mode */
mbed_official 340:28d1f895c6fe 841 #define ADC_CFGR2_CKMODE_1 ((uint32_t)0x80000000) /*!< ADC clocked by PCLK div4 */
mbed_official 340:28d1f895c6fe 842 #define ADC_CFGR2_CKMODE_0 ((uint32_t)0x40000000) /*!< ADC clocked by PCLK div2 */
mbed_official 340:28d1f895c6fe 843
mbed_official 340:28d1f895c6fe 844 /* Old bit definition, maintained for legacy purpose */
mbed_official 340:28d1f895c6fe 845 #define ADC_CFGR2_JITOFFDIV4 ADC_CFGR2_CKMODE_1 /*!< ADC clocked by PCLK div4 */
mbed_official 340:28d1f895c6fe 846 #define ADC_CFGR2_JITOFFDIV2 ADC_CFGR2_CKMODE_0 /*!< ADC clocked by PCLK div2 */
mbed_official 340:28d1f895c6fe 847
mbed_official 340:28d1f895c6fe 848 /****************** Bit definition for ADC_SMPR register ********************/
mbed_official 340:28d1f895c6fe 849 #define ADC_SMPR_SMP ((uint32_t)0x00000007) /*!< SMP[2:0] bits (Sampling time selection) */
mbed_official 340:28d1f895c6fe 850 #define ADC_SMPR_SMP_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 340:28d1f895c6fe 851 #define ADC_SMPR_SMP_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 340:28d1f895c6fe 852 #define ADC_SMPR_SMP_2 ((uint32_t)0x00000004) /*!< Bit 2 */
mbed_official 340:28d1f895c6fe 853
mbed_official 340:28d1f895c6fe 854 /* Old bit definition, maintained for legacy purpose */
mbed_official 340:28d1f895c6fe 855 #define ADC_SMPR1_SMPR ADC_SMPR_SMP /*!< SMP[2:0] bits (Sampling time selection) */
mbed_official 340:28d1f895c6fe 856 #define ADC_SMPR1_SMPR_0 ADC_SMPR_SMP_0 /*!< Bit 0 */
mbed_official 340:28d1f895c6fe 857 #define ADC_SMPR1_SMPR_1 ADC_SMPR_SMP_1 /*!< Bit 1 */
mbed_official 340:28d1f895c6fe 858 #define ADC_SMPR1_SMPR_2 ADC_SMPR_SMP_2 /*!< Bit 2 */
mbed_official 340:28d1f895c6fe 859
mbed_official 340:28d1f895c6fe 860 /******************* Bit definition for ADC_TR register ********************/
mbed_official 340:28d1f895c6fe 861 #define ADC_TR_HT ((uint32_t)0x0FFF0000) /*!< Analog watchdog high threshold */
mbed_official 340:28d1f895c6fe 862 #define ADC_TR_LT ((uint32_t)0x00000FFF) /*!< Analog watchdog low threshold */
mbed_official 340:28d1f895c6fe 863
mbed_official 340:28d1f895c6fe 864 /* Old bit definition, maintained for legacy purpose */
mbed_official 340:28d1f895c6fe 865 #define ADC_HTR_HT ADC_TR_HT /*!< Analog watchdog high threshold */
mbed_official 340:28d1f895c6fe 866 #define ADC_LTR_LT ADC_TR_LT /*!< Analog watchdog low threshold */
mbed_official 340:28d1f895c6fe 867
mbed_official 340:28d1f895c6fe 868 /****************** Bit definition for ADC_CHSELR register ******************/
mbed_official 340:28d1f895c6fe 869 #define ADC_CHSELR_CHSEL18 ((uint32_t)0x00040000) /*!< Channel 18 selection */
mbed_official 340:28d1f895c6fe 870 #define ADC_CHSELR_CHSEL17 ((uint32_t)0x00020000) /*!< Channel 17 selection */
mbed_official 340:28d1f895c6fe 871 #define ADC_CHSELR_CHSEL16 ((uint32_t)0x00010000) /*!< Channel 16 selection */
mbed_official 340:28d1f895c6fe 872 #define ADC_CHSELR_CHSEL15 ((uint32_t)0x00008000) /*!< Channel 15 selection */
mbed_official 340:28d1f895c6fe 873 #define ADC_CHSELR_CHSEL14 ((uint32_t)0x00004000) /*!< Channel 14 selection */
mbed_official 340:28d1f895c6fe 874 #define ADC_CHSELR_CHSEL13 ((uint32_t)0x00002000) /*!< Channel 13 selection */
mbed_official 340:28d1f895c6fe 875 #define ADC_CHSELR_CHSEL12 ((uint32_t)0x00001000) /*!< Channel 12 selection */
mbed_official 340:28d1f895c6fe 876 #define ADC_CHSELR_CHSEL11 ((uint32_t)0x00000800) /*!< Channel 11 selection */
mbed_official 340:28d1f895c6fe 877 #define ADC_CHSELR_CHSEL10 ((uint32_t)0x00000400) /*!< Channel 10 selection */
mbed_official 340:28d1f895c6fe 878 #define ADC_CHSELR_CHSEL9 ((uint32_t)0x00000200) /*!< Channel 9 selection */
mbed_official 340:28d1f895c6fe 879 #define ADC_CHSELR_CHSEL8 ((uint32_t)0x00000100) /*!< Channel 8 selection */
mbed_official 340:28d1f895c6fe 880 #define ADC_CHSELR_CHSEL7 ((uint32_t)0x00000080) /*!< Channel 7 selection */
mbed_official 340:28d1f895c6fe 881 #define ADC_CHSELR_CHSEL6 ((uint32_t)0x00000040) /*!< Channel 6 selection */
mbed_official 340:28d1f895c6fe 882 #define ADC_CHSELR_CHSEL5 ((uint32_t)0x00000020) /*!< Channel 5 selection */
mbed_official 340:28d1f895c6fe 883 #define ADC_CHSELR_CHSEL4 ((uint32_t)0x00000010) /*!< Channel 4 selection */
mbed_official 340:28d1f895c6fe 884 #define ADC_CHSELR_CHSEL3 ((uint32_t)0x00000008) /*!< Channel 3 selection */
mbed_official 340:28d1f895c6fe 885 #define ADC_CHSELR_CHSEL2 ((uint32_t)0x00000004) /*!< Channel 2 selection */
mbed_official 340:28d1f895c6fe 886 #define ADC_CHSELR_CHSEL1 ((uint32_t)0x00000002) /*!< Channel 1 selection */
mbed_official 340:28d1f895c6fe 887 #define ADC_CHSELR_CHSEL0 ((uint32_t)0x00000001) /*!< Channel 0 selection */
mbed_official 340:28d1f895c6fe 888
mbed_official 340:28d1f895c6fe 889 /******************** Bit definition for ADC_DR register ********************/
mbed_official 340:28d1f895c6fe 890 #define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!< Regular data */
mbed_official 340:28d1f895c6fe 891
mbed_official 340:28d1f895c6fe 892 /******************* Bit definition for ADC_CCR register ********************/
mbed_official 340:28d1f895c6fe 893 #define ADC_CCR_VBATEN ((uint32_t)0x01000000) /*!< Voltage battery enable */
mbed_official 340:28d1f895c6fe 894 #define ADC_CCR_TSEN ((uint32_t)0x00800000) /*!< Tempurature sensore enable */
mbed_official 340:28d1f895c6fe 895 #define ADC_CCR_VREFEN ((uint32_t)0x00400000) /*!< Vrefint enable */
mbed_official 340:28d1f895c6fe 896
mbed_official 340:28d1f895c6fe 897 /******************************************************************************/
mbed_official 340:28d1f895c6fe 898 /* */
mbed_official 340:28d1f895c6fe 899 /* Controller Area Network (CAN ) */
mbed_official 340:28d1f895c6fe 900 /* */
mbed_official 340:28d1f895c6fe 901 /******************************************************************************/
mbed_official 340:28d1f895c6fe 902 /*!<CAN control and status registers */
mbed_official 340:28d1f895c6fe 903 /******************* Bit definition for CAN_MCR register ********************/
mbed_official 340:28d1f895c6fe 904 #define CAN_MCR_INRQ ((uint32_t)0x00000001) /*!<Initialization Request */
mbed_official 340:28d1f895c6fe 905 #define CAN_MCR_SLEEP ((uint32_t)0x00000002) /*!<Sleep Mode Request */
mbed_official 340:28d1f895c6fe 906 #define CAN_MCR_TXFP ((uint32_t)0x00000004) /*!<Transmit FIFO Priority */
mbed_official 340:28d1f895c6fe 907 #define CAN_MCR_RFLM ((uint32_t)0x00000008) /*!<Receive FIFO Locked Mode */
mbed_official 340:28d1f895c6fe 908 #define CAN_MCR_NART ((uint32_t)0x00000010) /*!<No Automatic Retransmission */
mbed_official 340:28d1f895c6fe 909 #define CAN_MCR_AWUM ((uint32_t)0x00000020) /*!<Automatic Wakeup Mode */
mbed_official 340:28d1f895c6fe 910 #define CAN_MCR_ABOM ((uint32_t)0x00000040) /*!<Automatic Bus-Off Management */
mbed_official 340:28d1f895c6fe 911 #define CAN_MCR_TTCM ((uint32_t)0x00000080) /*!<Time Triggered Communication Mode */
mbed_official 340:28d1f895c6fe 912 #define CAN_MCR_RESET ((uint32_t)0x00008000) /*!<bxCAN software master reset */
mbed_official 340:28d1f895c6fe 913
mbed_official 340:28d1f895c6fe 914 /******************* Bit definition for CAN_MSR register ********************/
mbed_official 340:28d1f895c6fe 915 #define CAN_MSR_INAK ((uint32_t)0x00000001) /*!<Initialization Acknowledge */
mbed_official 340:28d1f895c6fe 916 #define CAN_MSR_SLAK ((uint32_t)0x00000002) /*!<Sleep Acknowledge */
mbed_official 340:28d1f895c6fe 917 #define CAN_MSR_ERRI ((uint32_t)0x00000004) /*!<Error Interrupt */
mbed_official 340:28d1f895c6fe 918 #define CAN_MSR_WKUI ((uint32_t)0x00000008) /*!<Wakeup Interrupt */
mbed_official 340:28d1f895c6fe 919 #define CAN_MSR_SLAKI ((uint32_t)0x00000010) /*!<Sleep Acknowledge Interrupt */
mbed_official 340:28d1f895c6fe 920 #define CAN_MSR_TXM ((uint32_t)0x00000100) /*!<Transmit Mode */
mbed_official 340:28d1f895c6fe 921 #define CAN_MSR_RXM ((uint32_t)0x00000200) /*!<Receive Mode */
mbed_official 340:28d1f895c6fe 922 #define CAN_MSR_SAMP ((uint32_t)0x00000400) /*!<Last Sample Point */
mbed_official 340:28d1f895c6fe 923 #define CAN_MSR_RX ((uint32_t)0x00000800) /*!<CAN Rx Signal */
mbed_official 340:28d1f895c6fe 924
mbed_official 340:28d1f895c6fe 925 /******************* Bit definition for CAN_TSR register ********************/
mbed_official 340:28d1f895c6fe 926 #define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /*!<Request Completed Mailbox0 */
mbed_official 340:28d1f895c6fe 927 #define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /*!<Transmission OK of Mailbox0 */
mbed_official 340:28d1f895c6fe 928 #define CAN_TSR_ALST0 ((uint32_t)0x00000004) /*!<Arbitration Lost for Mailbox0 */
mbed_official 340:28d1f895c6fe 929 #define CAN_TSR_TERR0 ((uint32_t)0x00000008) /*!<Transmission Error of Mailbox0 */
mbed_official 340:28d1f895c6fe 930 #define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /*!<Abort Request for Mailbox0 */
mbed_official 340:28d1f895c6fe 931 #define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /*!<Request Completed Mailbox1 */
mbed_official 340:28d1f895c6fe 932 #define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /*!<Transmission OK of Mailbox1 */
mbed_official 340:28d1f895c6fe 933 #define CAN_TSR_ALST1 ((uint32_t)0x00000400) /*!<Arbitration Lost for Mailbox1 */
mbed_official 340:28d1f895c6fe 934 #define CAN_TSR_TERR1 ((uint32_t)0x00000800) /*!<Transmission Error of Mailbox1 */
mbed_official 340:28d1f895c6fe 935 #define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /*!<Abort Request for Mailbox 1 */
mbed_official 340:28d1f895c6fe 936 #define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /*!<Request Completed Mailbox2 */
mbed_official 340:28d1f895c6fe 937 #define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /*!<Transmission OK of Mailbox 2 */
mbed_official 340:28d1f895c6fe 938 #define CAN_TSR_ALST2 ((uint32_t)0x00040000) /*!<Arbitration Lost for mailbox 2 */
mbed_official 340:28d1f895c6fe 939 #define CAN_TSR_TERR2 ((uint32_t)0x00080000) /*!<Transmission Error of Mailbox 2 */
mbed_official 340:28d1f895c6fe 940 #define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /*!<Abort Request for Mailbox 2 */
mbed_official 340:28d1f895c6fe 941 #define CAN_TSR_CODE ((uint32_t)0x03000000) /*!<Mailbox Code */
mbed_official 340:28d1f895c6fe 942
mbed_official 340:28d1f895c6fe 943 #define CAN_TSR_TME ((uint32_t)0x1C000000) /*!<TME[2:0] bits */
mbed_official 340:28d1f895c6fe 944 #define CAN_TSR_TME0 ((uint32_t)0x04000000) /*!<Transmit Mailbox 0 Empty */
mbed_official 340:28d1f895c6fe 945 #define CAN_TSR_TME1 ((uint32_t)0x08000000) /*!<Transmit Mailbox 1 Empty */
mbed_official 340:28d1f895c6fe 946 #define CAN_TSR_TME2 ((uint32_t)0x10000000) /*!<Transmit Mailbox 2 Empty */
mbed_official 340:28d1f895c6fe 947
mbed_official 340:28d1f895c6fe 948 #define CAN_TSR_LOW ((uint32_t)0xE0000000) /*!<LOW[2:0] bits */
mbed_official 340:28d1f895c6fe 949 #define CAN_TSR_LOW0 ((uint32_t)0x20000000) /*!<Lowest Priority Flag for Mailbox 0 */
mbed_official 340:28d1f895c6fe 950 #define CAN_TSR_LOW1 ((uint32_t)0x40000000) /*!<Lowest Priority Flag for Mailbox 1 */
mbed_official 340:28d1f895c6fe 951 #define CAN_TSR_LOW2 ((uint32_t)0x80000000) /*!<Lowest Priority Flag for Mailbox 2 */
mbed_official 340:28d1f895c6fe 952
mbed_official 340:28d1f895c6fe 953 /******************* Bit definition for CAN_RF0R register *******************/
mbed_official 340:28d1f895c6fe 954 #define CAN_RF0R_FMP0 ((uint32_t)0x00000003) /*!<FIFO 0 Message Pending */
mbed_official 340:28d1f895c6fe 955 #define CAN_RF0R_FULL0 ((uint32_t)0x00000008) /*!<FIFO 0 Full */
mbed_official 340:28d1f895c6fe 956 #define CAN_RF0R_FOVR0 ((uint32_t)0x00000010) /*!<FIFO 0 Overrun */
mbed_official 340:28d1f895c6fe 957 #define CAN_RF0R_RFOM0 ((uint32_t)0x00000020) /*!<Release FIFO 0 Output Mailbox */
mbed_official 340:28d1f895c6fe 958
mbed_official 340:28d1f895c6fe 959 /******************* Bit definition for CAN_RF1R register *******************/
mbed_official 340:28d1f895c6fe 960 #define CAN_RF1R_FMP1 ((uint32_t)0x00000003) /*!<FIFO 1 Message Pending */
mbed_official 340:28d1f895c6fe 961 #define CAN_RF1R_FULL1 ((uint32_t)0x00000008) /*!<FIFO 1 Full */
mbed_official 340:28d1f895c6fe 962 #define CAN_RF1R_FOVR1 ((uint32_t)0x00000010) /*!<FIFO 1 Overrun */
mbed_official 340:28d1f895c6fe 963 #define CAN_RF1R_RFOM1 ((uint32_t)0x00000020) /*!<Release FIFO 1 Output Mailbox */
mbed_official 340:28d1f895c6fe 964
mbed_official 340:28d1f895c6fe 965 /******************** Bit definition for CAN_IER register *******************/
mbed_official 340:28d1f895c6fe 966 #define CAN_IER_TMEIE ((uint32_t)0x00000001) /*!<Transmit Mailbox Empty Interrupt Enable */
mbed_official 340:28d1f895c6fe 967 #define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /*!<FIFO Message Pending Interrupt Enable */
mbed_official 340:28d1f895c6fe 968 #define CAN_IER_FFIE0 ((uint32_t)0x00000004) /*!<FIFO Full Interrupt Enable */
mbed_official 340:28d1f895c6fe 969 #define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /*!<FIFO Overrun Interrupt Enable */
mbed_official 340:28d1f895c6fe 970 #define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /*!<FIFO Message Pending Interrupt Enable */
mbed_official 340:28d1f895c6fe 971 #define CAN_IER_FFIE1 ((uint32_t)0x00000020) /*!<FIFO Full Interrupt Enable */
mbed_official 340:28d1f895c6fe 972 #define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /*!<FIFO Overrun Interrupt Enable */
mbed_official 340:28d1f895c6fe 973 #define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!<Error Warning Interrupt Enable */
mbed_official 340:28d1f895c6fe 974 #define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!<Error Passive Interrupt Enable */
mbed_official 340:28d1f895c6fe 975 #define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!<Bus-Off Interrupt Enable */
mbed_official 340:28d1f895c6fe 976 #define CAN_IER_LECIE ((uint32_t)0x00000800) /*!<Last Error Code Interrupt Enable */
mbed_official 340:28d1f895c6fe 977 #define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!<Error Interrupt Enable */
mbed_official 340:28d1f895c6fe 978 #define CAN_IER_WKUIE ((uint32_t)0x00010000) /*!<Wakeup Interrupt Enable */
mbed_official 340:28d1f895c6fe 979 #define CAN_IER_SLKIE ((uint32_t)0x00020000) /*!<Sleep Interrupt Enable */
mbed_official 340:28d1f895c6fe 980
mbed_official 340:28d1f895c6fe 981 /******************** Bit definition for CAN_ESR register *******************/
mbed_official 340:28d1f895c6fe 982 #define CAN_ESR_EWGF ((uint32_t)0x00000001) /*!<Error Warning Flag */
mbed_official 340:28d1f895c6fe 983 #define CAN_ESR_EPVF ((uint32_t)0x00000002) /*!<Error Passive Flag */
mbed_official 340:28d1f895c6fe 984 #define CAN_ESR_BOFF ((uint32_t)0x00000004) /*!<Bus-Off Flag */
mbed_official 340:28d1f895c6fe 985
mbed_official 340:28d1f895c6fe 986 #define CAN_ESR_LEC ((uint32_t)0x00000070) /*!<LEC[2:0] bits (Last Error Code) */
mbed_official 340:28d1f895c6fe 987 #define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 340:28d1f895c6fe 988 #define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 340:28d1f895c6fe 989 #define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 340:28d1f895c6fe 990
mbed_official 340:28d1f895c6fe 991 #define CAN_ESR_TEC ((uint32_t)0x00FF0000) /*!<Least significant byte of the 9-bit Transmit Error Counter */
mbed_official 340:28d1f895c6fe 992 #define CAN_ESR_REC ((uint32_t)0xFF000000) /*!<Receive Error Counter */
mbed_official 340:28d1f895c6fe 993
mbed_official 340:28d1f895c6fe 994 /******************* Bit definition for CAN_BTR register ********************/
mbed_official 340:28d1f895c6fe 995 #define CAN_BTR_BRP ((uint32_t)0x000003FF) /*!<Baud Rate Prescaler */
mbed_official 340:28d1f895c6fe 996 #define CAN_BTR_TS1 ((uint32_t)0x000F0000) /*!<Time Segment 1 */
mbed_official 340:28d1f895c6fe 997 #define CAN_BTR_TS1_0 ((uint32_t)0x00010000) /*!<Time Segment 1 (Bit 0) */
mbed_official 340:28d1f895c6fe 998 #define CAN_BTR_TS1_1 ((uint32_t)0x00020000) /*!<Time Segment 1 (Bit 1) */
mbed_official 340:28d1f895c6fe 999 #define CAN_BTR_TS1_2 ((uint32_t)0x00040000) /*!<Time Segment 1 (Bit 2) */
mbed_official 340:28d1f895c6fe 1000 #define CAN_BTR_TS1_3 ((uint32_t)0x00080000) /*!<Time Segment 1 (Bit 3) */
mbed_official 340:28d1f895c6fe 1001 #define CAN_BTR_TS2 ((uint32_t)0x00700000) /*!<Time Segment 2 */
mbed_official 340:28d1f895c6fe 1002 #define CAN_BTR_TS2_0 ((uint32_t)0x00100000) /*!<Time Segment 2 (Bit 0) */
mbed_official 340:28d1f895c6fe 1003 #define CAN_BTR_TS2_1 ((uint32_t)0x00200000) /*!<Time Segment 2 (Bit 1) */
mbed_official 340:28d1f895c6fe 1004 #define CAN_BTR_TS2_2 ((uint32_t)0x00400000) /*!<Time Segment 2 (Bit 2) */
mbed_official 340:28d1f895c6fe 1005 #define CAN_BTR_SJW ((uint32_t)0x03000000) /*!<Resynchronization Jump Width */
mbed_official 340:28d1f895c6fe 1006 #define CAN_BTR_SJW_0 ((uint32_t)0x01000000) /*!<Resynchronization Jump Width (Bit 0) */
mbed_official 340:28d1f895c6fe 1007 #define CAN_BTR_SJW_1 ((uint32_t)0x02000000) /*!<Resynchronization Jump Width (Bit 1) */
mbed_official 340:28d1f895c6fe 1008 #define CAN_BTR_LBKM ((uint32_t)0x40000000) /*!<Loop Back Mode (Debug) */
mbed_official 340:28d1f895c6fe 1009 #define CAN_BTR_SILM ((uint32_t)0x80000000) /*!<Silent Mode */
mbed_official 340:28d1f895c6fe 1010
mbed_official 340:28d1f895c6fe 1011 /*!<Mailbox registers */
mbed_official 340:28d1f895c6fe 1012 /****************** Bit definition for CAN_TI0R register ********************/
mbed_official 340:28d1f895c6fe 1013 #define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
mbed_official 340:28d1f895c6fe 1014 #define CAN_TI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
mbed_official 340:28d1f895c6fe 1015 #define CAN_TI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
mbed_official 340:28d1f895c6fe 1016 #define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
mbed_official 340:28d1f895c6fe 1017 #define CAN_TI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
mbed_official 340:28d1f895c6fe 1018
mbed_official 340:28d1f895c6fe 1019 /****************** Bit definition for CAN_TDT0R register *******************/
mbed_official 340:28d1f895c6fe 1020 #define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
mbed_official 340:28d1f895c6fe 1021 #define CAN_TDT0R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
mbed_official 340:28d1f895c6fe 1022 #define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
mbed_official 340:28d1f895c6fe 1023
mbed_official 340:28d1f895c6fe 1024 /****************** Bit definition for CAN_TDL0R register *******************/
mbed_official 340:28d1f895c6fe 1025 #define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
mbed_official 340:28d1f895c6fe 1026 #define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
mbed_official 340:28d1f895c6fe 1027 #define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
mbed_official 340:28d1f895c6fe 1028 #define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
mbed_official 340:28d1f895c6fe 1029
mbed_official 340:28d1f895c6fe 1030 /****************** Bit definition for CAN_TDH0R register *******************/
mbed_official 340:28d1f895c6fe 1031 #define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
mbed_official 340:28d1f895c6fe 1032 #define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
mbed_official 340:28d1f895c6fe 1033 #define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
mbed_official 340:28d1f895c6fe 1034 #define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
mbed_official 340:28d1f895c6fe 1035
mbed_official 340:28d1f895c6fe 1036 /******************* Bit definition for CAN_TI1R register *******************/
mbed_official 340:28d1f895c6fe 1037 #define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
mbed_official 340:28d1f895c6fe 1038 #define CAN_TI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
mbed_official 340:28d1f895c6fe 1039 #define CAN_TI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
mbed_official 340:28d1f895c6fe 1040 #define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
mbed_official 340:28d1f895c6fe 1041 #define CAN_TI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
mbed_official 340:28d1f895c6fe 1042
mbed_official 340:28d1f895c6fe 1043 /******************* Bit definition for CAN_TDT1R register ******************/
mbed_official 340:28d1f895c6fe 1044 #define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
mbed_official 340:28d1f895c6fe 1045 #define CAN_TDT1R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
mbed_official 340:28d1f895c6fe 1046 #define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
mbed_official 340:28d1f895c6fe 1047
mbed_official 340:28d1f895c6fe 1048 /******************* Bit definition for CAN_TDL1R register ******************/
mbed_official 340:28d1f895c6fe 1049 #define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
mbed_official 340:28d1f895c6fe 1050 #define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
mbed_official 340:28d1f895c6fe 1051 #define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
mbed_official 340:28d1f895c6fe 1052 #define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
mbed_official 340:28d1f895c6fe 1053
mbed_official 340:28d1f895c6fe 1054 /******************* Bit definition for CAN_TDH1R register ******************/
mbed_official 340:28d1f895c6fe 1055 #define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
mbed_official 340:28d1f895c6fe 1056 #define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
mbed_official 340:28d1f895c6fe 1057 #define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
mbed_official 340:28d1f895c6fe 1058 #define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
mbed_official 340:28d1f895c6fe 1059
mbed_official 340:28d1f895c6fe 1060 /******************* Bit definition for CAN_TI2R register *******************/
mbed_official 340:28d1f895c6fe 1061 #define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
mbed_official 340:28d1f895c6fe 1062 #define CAN_TI2R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
mbed_official 340:28d1f895c6fe 1063 #define CAN_TI2R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
mbed_official 340:28d1f895c6fe 1064 #define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
mbed_official 340:28d1f895c6fe 1065 #define CAN_TI2R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
mbed_official 340:28d1f895c6fe 1066
mbed_official 340:28d1f895c6fe 1067 /******************* Bit definition for CAN_TDT2R register ******************/
mbed_official 340:28d1f895c6fe 1068 #define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
mbed_official 340:28d1f895c6fe 1069 #define CAN_TDT2R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
mbed_official 340:28d1f895c6fe 1070 #define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
mbed_official 340:28d1f895c6fe 1071
mbed_official 340:28d1f895c6fe 1072 /******************* Bit definition for CAN_TDL2R register ******************/
mbed_official 340:28d1f895c6fe 1073 #define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
mbed_official 340:28d1f895c6fe 1074 #define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
mbed_official 340:28d1f895c6fe 1075 #define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
mbed_official 340:28d1f895c6fe 1076 #define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
mbed_official 340:28d1f895c6fe 1077
mbed_official 340:28d1f895c6fe 1078 /******************* Bit definition for CAN_TDH2R register ******************/
mbed_official 340:28d1f895c6fe 1079 #define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
mbed_official 340:28d1f895c6fe 1080 #define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
mbed_official 340:28d1f895c6fe 1081 #define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
mbed_official 340:28d1f895c6fe 1082 #define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
mbed_official 340:28d1f895c6fe 1083
mbed_official 340:28d1f895c6fe 1084 /******************* Bit definition for CAN_RI0R register *******************/
mbed_official 340:28d1f895c6fe 1085 #define CAN_RI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
mbed_official 340:28d1f895c6fe 1086 #define CAN_RI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
mbed_official 340:28d1f895c6fe 1087 #define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
mbed_official 340:28d1f895c6fe 1088 #define CAN_RI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
mbed_official 340:28d1f895c6fe 1089
mbed_official 340:28d1f895c6fe 1090 /******************* Bit definition for CAN_RDT0R register ******************/
mbed_official 340:28d1f895c6fe 1091 #define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
mbed_official 340:28d1f895c6fe 1092 #define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
mbed_official 340:28d1f895c6fe 1093 #define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
mbed_official 340:28d1f895c6fe 1094
mbed_official 340:28d1f895c6fe 1095 /******************* Bit definition for CAN_RDL0R register ******************/
mbed_official 340:28d1f895c6fe 1096 #define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
mbed_official 340:28d1f895c6fe 1097 #define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
mbed_official 340:28d1f895c6fe 1098 #define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
mbed_official 340:28d1f895c6fe 1099 #define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
mbed_official 340:28d1f895c6fe 1100
mbed_official 340:28d1f895c6fe 1101 /******************* Bit definition for CAN_RDH0R register ******************/
mbed_official 340:28d1f895c6fe 1102 #define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
mbed_official 340:28d1f895c6fe 1103 #define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
mbed_official 340:28d1f895c6fe 1104 #define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
mbed_official 340:28d1f895c6fe 1105 #define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
mbed_official 340:28d1f895c6fe 1106
mbed_official 340:28d1f895c6fe 1107 /******************* Bit definition for CAN_RI1R register *******************/
mbed_official 340:28d1f895c6fe 1108 #define CAN_RI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
mbed_official 340:28d1f895c6fe 1109 #define CAN_RI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
mbed_official 340:28d1f895c6fe 1110 #define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
mbed_official 340:28d1f895c6fe 1111 #define CAN_RI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
mbed_official 340:28d1f895c6fe 1112
mbed_official 340:28d1f895c6fe 1113 /******************* Bit definition for CAN_RDT1R register ******************/
mbed_official 340:28d1f895c6fe 1114 #define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
mbed_official 340:28d1f895c6fe 1115 #define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
mbed_official 340:28d1f895c6fe 1116 #define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
mbed_official 340:28d1f895c6fe 1117
mbed_official 340:28d1f895c6fe 1118 /******************* Bit definition for CAN_RDL1R register ******************/
mbed_official 340:28d1f895c6fe 1119 #define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
mbed_official 340:28d1f895c6fe 1120 #define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
mbed_official 340:28d1f895c6fe 1121 #define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
mbed_official 340:28d1f895c6fe 1122 #define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
mbed_official 340:28d1f895c6fe 1123
mbed_official 340:28d1f895c6fe 1124 /******************* Bit definition for CAN_RDH1R register ******************/
mbed_official 340:28d1f895c6fe 1125 #define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
mbed_official 340:28d1f895c6fe 1126 #define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
mbed_official 340:28d1f895c6fe 1127 #define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
mbed_official 340:28d1f895c6fe 1128 #define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
mbed_official 340:28d1f895c6fe 1129
mbed_official 340:28d1f895c6fe 1130 /*!<CAN filter registers */
mbed_official 340:28d1f895c6fe 1131 /******************* Bit definition for CAN_FMR register ********************/
mbed_official 340:28d1f895c6fe 1132 #define CAN_FMR_FINIT ((uint32_t)0x00000001) /*!<Filter Init Mode */
mbed_official 340:28d1f895c6fe 1133
mbed_official 340:28d1f895c6fe 1134 /******************* Bit definition for CAN_FM1R register *******************/
mbed_official 340:28d1f895c6fe 1135 #define CAN_FM1R_FBM ((uint32_t)0x00003FFF) /*!<Filter Mode */
mbed_official 340:28d1f895c6fe 1136 #define CAN_FM1R_FBM0 ((uint32_t)0x00000001) /*!<Filter Init Mode bit 0 */
mbed_official 340:28d1f895c6fe 1137 #define CAN_FM1R_FBM1 ((uint32_t)0x00000002) /*!<Filter Init Mode bit 1 */
mbed_official 340:28d1f895c6fe 1138 #define CAN_FM1R_FBM2 ((uint32_t)0x00000004) /*!<Filter Init Mode bit 2 */
mbed_official 340:28d1f895c6fe 1139 #define CAN_FM1R_FBM3 ((uint32_t)0x00000008) /*!<Filter Init Mode bit 3 */
mbed_official 340:28d1f895c6fe 1140 #define CAN_FM1R_FBM4 ((uint32_t)0x00000010) /*!<Filter Init Mode bit 4 */
mbed_official 340:28d1f895c6fe 1141 #define CAN_FM1R_FBM5 ((uint32_t)0x00000020) /*!<Filter Init Mode bit 5 */
mbed_official 340:28d1f895c6fe 1142 #define CAN_FM1R_FBM6 ((uint32_t)0x00000040) /*!<Filter Init Mode bit 6 */
mbed_official 340:28d1f895c6fe 1143 #define CAN_FM1R_FBM7 ((uint32_t)0x00000080) /*!<Filter Init Mode bit 7 */
mbed_official 340:28d1f895c6fe 1144 #define CAN_FM1R_FBM8 ((uint32_t)0x00000100) /*!<Filter Init Mode bit 8 */
mbed_official 340:28d1f895c6fe 1145 #define CAN_FM1R_FBM9 ((uint32_t)0x00000200) /*!<Filter Init Mode bit 9 */
mbed_official 340:28d1f895c6fe 1146 #define CAN_FM1R_FBM10 ((uint32_t)0x00000400) /*!<Filter Init Mode bit 10 */
mbed_official 340:28d1f895c6fe 1147 #define CAN_FM1R_FBM11 ((uint32_t)0x00000800) /*!<Filter Init Mode bit 11 */
mbed_official 340:28d1f895c6fe 1148 #define CAN_FM1R_FBM12 ((uint32_t)0x00001000) /*!<Filter Init Mode bit 12 */
mbed_official 340:28d1f895c6fe 1149 #define CAN_FM1R_FBM13 ((uint32_t)0x00002000) /*!<Filter Init Mode bit 13 */
mbed_official 340:28d1f895c6fe 1150
mbed_official 340:28d1f895c6fe 1151 /******************* Bit definition for CAN_FS1R register *******************/
mbed_official 340:28d1f895c6fe 1152 #define CAN_FS1R_FSC ((uint32_t)0x00003FFF) /*!<Filter Scale Configuration */
mbed_official 340:28d1f895c6fe 1153 #define CAN_FS1R_FSC0 ((uint32_t)0x00000001) /*!<Filter Scale Configuration bit 0 */
mbed_official 340:28d1f895c6fe 1154 #define CAN_FS1R_FSC1 ((uint32_t)0x00000002) /*!<Filter Scale Configuration bit 1 */
mbed_official 340:28d1f895c6fe 1155 #define CAN_FS1R_FSC2 ((uint32_t)0x00000004) /*!<Filter Scale Configuration bit 2 */
mbed_official 340:28d1f895c6fe 1156 #define CAN_FS1R_FSC3 ((uint32_t)0x00000008) /*!<Filter Scale Configuration bit 3 */
mbed_official 340:28d1f895c6fe 1157 #define CAN_FS1R_FSC4 ((uint32_t)0x00000010) /*!<Filter Scale Configuration bit 4 */
mbed_official 340:28d1f895c6fe 1158 #define CAN_FS1R_FSC5 ((uint32_t)0x00000020) /*!<Filter Scale Configuration bit 5 */
mbed_official 340:28d1f895c6fe 1159 #define CAN_FS1R_FSC6 ((uint32_t)0x00000040) /*!<Filter Scale Configuration bit 6 */
mbed_official 340:28d1f895c6fe 1160 #define CAN_FS1R_FSC7 ((uint32_t)0x00000080) /*!<Filter Scale Configuration bit 7 */
mbed_official 340:28d1f895c6fe 1161 #define CAN_FS1R_FSC8 ((uint32_t)0x00000100) /*!<Filter Scale Configuration bit 8 */
mbed_official 340:28d1f895c6fe 1162 #define CAN_FS1R_FSC9 ((uint32_t)0x00000200) /*!<Filter Scale Configuration bit 9 */
mbed_official 340:28d1f895c6fe 1163 #define CAN_FS1R_FSC10 ((uint32_t)0x00000400) /*!<Filter Scale Configuration bit 10 */
mbed_official 340:28d1f895c6fe 1164 #define CAN_FS1R_FSC11 ((uint32_t)0x00000800) /*!<Filter Scale Configuration bit 11 */
mbed_official 340:28d1f895c6fe 1165 #define CAN_FS1R_FSC12 ((uint32_t)0x00001000) /*!<Filter Scale Configuration bit 12 */
mbed_official 340:28d1f895c6fe 1166 #define CAN_FS1R_FSC13 ((uint32_t)0x00002000) /*!<Filter Scale Configuration bit 13 */
mbed_official 340:28d1f895c6fe 1167
mbed_official 340:28d1f895c6fe 1168 /****************** Bit definition for CAN_FFA1R register *******************/
mbed_official 340:28d1f895c6fe 1169 #define CAN_FFA1R_FFA ((uint32_t)0x00003FFF) /*!<Filter FIFO Assignment */
mbed_official 340:28d1f895c6fe 1170 #define CAN_FFA1R_FFA0 ((uint32_t)0x00000001) /*!<Filter FIFO Assignment for Filter 0 */
mbed_official 340:28d1f895c6fe 1171 #define CAN_FFA1R_FFA1 ((uint32_t)0x00000002) /*!<Filter FIFO Assignment for Filter 1 */
mbed_official 340:28d1f895c6fe 1172 #define CAN_FFA1R_FFA2 ((uint32_t)0x00000004) /*!<Filter FIFO Assignment for Filter 2 */
mbed_official 340:28d1f895c6fe 1173 #define CAN_FFA1R_FFA3 ((uint32_t)0x00000008) /*!<Filter FIFO Assignment for Filter 3 */
mbed_official 340:28d1f895c6fe 1174 #define CAN_FFA1R_FFA4 ((uint32_t)0x00000010) /*!<Filter FIFO Assignment for Filter 4 */
mbed_official 340:28d1f895c6fe 1175 #define CAN_FFA1R_FFA5 ((uint32_t)0x00000020) /*!<Filter FIFO Assignment for Filter 5 */
mbed_official 340:28d1f895c6fe 1176 #define CAN_FFA1R_FFA6 ((uint32_t)0x00000040) /*!<Filter FIFO Assignment for Filter 6 */
mbed_official 340:28d1f895c6fe 1177 #define CAN_FFA1R_FFA7 ((uint32_t)0x00000080) /*!<Filter FIFO Assignment for Filter 7 */
mbed_official 340:28d1f895c6fe 1178 #define CAN_FFA1R_FFA8 ((uint32_t)0x00000100) /*!<Filter FIFO Assignment for Filter 8 */
mbed_official 340:28d1f895c6fe 1179 #define CAN_FFA1R_FFA9 ((uint32_t)0x00000200) /*!<Filter FIFO Assignment for Filter 9 */
mbed_official 340:28d1f895c6fe 1180 #define CAN_FFA1R_FFA10 ((uint32_t)0x00000400) /*!<Filter FIFO Assignment for Filter 10 */
mbed_official 340:28d1f895c6fe 1181 #define CAN_FFA1R_FFA11 ((uint32_t)0x00000800) /*!<Filter FIFO Assignment for Filter 11 */
mbed_official 340:28d1f895c6fe 1182 #define CAN_FFA1R_FFA12 ((uint32_t)0x00001000) /*!<Filter FIFO Assignment for Filter 12 */
mbed_official 340:28d1f895c6fe 1183 #define CAN_FFA1R_FFA13 ((uint32_t)0x00002000) /*!<Filter FIFO Assignment for Filter 13 */
mbed_official 340:28d1f895c6fe 1184
mbed_official 340:28d1f895c6fe 1185 /******************* Bit definition for CAN_FA1R register *******************/
mbed_official 340:28d1f895c6fe 1186 #define CAN_FA1R_FACT ((uint32_t)0x00003FFF) /*!<Filter Active */
mbed_official 340:28d1f895c6fe 1187 #define CAN_FA1R_FACT0 ((uint32_t)0x00000001) /*!<Filter 0 Active */
mbed_official 340:28d1f895c6fe 1188 #define CAN_FA1R_FACT1 ((uint32_t)0x00000002) /*!<Filter 1 Active */
mbed_official 340:28d1f895c6fe 1189 #define CAN_FA1R_FACT2 ((uint32_t)0x00000004) /*!<Filter 2 Active */
mbed_official 340:28d1f895c6fe 1190 #define CAN_FA1R_FACT3 ((uint32_t)0x00000008) /*!<Filter 3 Active */
mbed_official 340:28d1f895c6fe 1191 #define CAN_FA1R_FACT4 ((uint32_t)0x00000010) /*!<Filter 4 Active */
mbed_official 340:28d1f895c6fe 1192 #define CAN_FA1R_FACT5 ((uint32_t)0x00000020) /*!<Filter 5 Active */
mbed_official 340:28d1f895c6fe 1193 #define CAN_FA1R_FACT6 ((uint32_t)0x00000040) /*!<Filter 6 Active */
mbed_official 340:28d1f895c6fe 1194 #define CAN_FA1R_FACT7 ((uint32_t)0x00000080) /*!<Filter 7 Active */
mbed_official 340:28d1f895c6fe 1195 #define CAN_FA1R_FACT8 ((uint32_t)0x00000100) /*!<Filter 8 Active */
mbed_official 340:28d1f895c6fe 1196 #define CAN_FA1R_FACT9 ((uint32_t)0x00000200) /*!<Filter 9 Active */
mbed_official 340:28d1f895c6fe 1197 #define CAN_FA1R_FACT10 ((uint32_t)0x00000400) /*!<Filter 10 Active */
mbed_official 340:28d1f895c6fe 1198 #define CAN_FA1R_FACT11 ((uint32_t)0x00000800) /*!<Filter 11 Active */
mbed_official 340:28d1f895c6fe 1199 #define CAN_FA1R_FACT12 ((uint32_t)0x00001000) /*!<Filter 12 Active */
mbed_official 340:28d1f895c6fe 1200 #define CAN_FA1R_FACT13 ((uint32_t)0x00002000) /*!<Filter 13 Active */
mbed_official 340:28d1f895c6fe 1201
mbed_official 340:28d1f895c6fe 1202 /******************* Bit definition for CAN_F0R1 register *******************/
mbed_official 340:28d1f895c6fe 1203 #define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 340:28d1f895c6fe 1204 #define CAN_F0R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 340:28d1f895c6fe 1205 #define CAN_F0R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 340:28d1f895c6fe 1206 #define CAN_F0R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 340:28d1f895c6fe 1207 #define CAN_F0R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 340:28d1f895c6fe 1208 #define CAN_F0R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 340:28d1f895c6fe 1209 #define CAN_F0R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 340:28d1f895c6fe 1210 #define CAN_F0R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 340:28d1f895c6fe 1211 #define CAN_F0R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 340:28d1f895c6fe 1212 #define CAN_F0R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 340:28d1f895c6fe 1213 #define CAN_F0R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 340:28d1f895c6fe 1214 #define CAN_F0R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 340:28d1f895c6fe 1215 #define CAN_F0R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 340:28d1f895c6fe 1216 #define CAN_F0R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 340:28d1f895c6fe 1217 #define CAN_F0R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 340:28d1f895c6fe 1218 #define CAN_F0R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 340:28d1f895c6fe 1219 #define CAN_F0R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 340:28d1f895c6fe 1220 #define CAN_F0R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 340:28d1f895c6fe 1221 #define CAN_F0R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 340:28d1f895c6fe 1222 #define CAN_F0R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 340:28d1f895c6fe 1223 #define CAN_F0R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 340:28d1f895c6fe 1224 #define CAN_F0R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 340:28d1f895c6fe 1225 #define CAN_F0R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 340:28d1f895c6fe 1226 #define CAN_F0R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 340:28d1f895c6fe 1227 #define CAN_F0R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 340:28d1f895c6fe 1228 #define CAN_F0R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 340:28d1f895c6fe 1229 #define CAN_F0R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 340:28d1f895c6fe 1230 #define CAN_F0R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 340:28d1f895c6fe 1231 #define CAN_F0R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 340:28d1f895c6fe 1232 #define CAN_F0R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 340:28d1f895c6fe 1233 #define CAN_F0R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 340:28d1f895c6fe 1234 #define CAN_F0R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 340:28d1f895c6fe 1235
mbed_official 340:28d1f895c6fe 1236 /******************* Bit definition for CAN_F1R1 register *******************/
mbed_official 340:28d1f895c6fe 1237 #define CAN_F1R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 340:28d1f895c6fe 1238 #define CAN_F1R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 340:28d1f895c6fe 1239 #define CAN_F1R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 340:28d1f895c6fe 1240 #define CAN_F1R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 340:28d1f895c6fe 1241 #define CAN_F1R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 340:28d1f895c6fe 1242 #define CAN_F1R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 340:28d1f895c6fe 1243 #define CAN_F1R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 340:28d1f895c6fe 1244 #define CAN_F1R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 340:28d1f895c6fe 1245 #define CAN_F1R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 340:28d1f895c6fe 1246 #define CAN_F1R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 340:28d1f895c6fe 1247 #define CAN_F1R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 340:28d1f895c6fe 1248 #define CAN_F1R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 340:28d1f895c6fe 1249 #define CAN_F1R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 340:28d1f895c6fe 1250 #define CAN_F1R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 340:28d1f895c6fe 1251 #define CAN_F1R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 340:28d1f895c6fe 1252 #define CAN_F1R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 340:28d1f895c6fe 1253 #define CAN_F1R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 340:28d1f895c6fe 1254 #define CAN_F1R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 340:28d1f895c6fe 1255 #define CAN_F1R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 340:28d1f895c6fe 1256 #define CAN_F1R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 340:28d1f895c6fe 1257 #define CAN_F1R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 340:28d1f895c6fe 1258 #define CAN_F1R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 340:28d1f895c6fe 1259 #define CAN_F1R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 340:28d1f895c6fe 1260 #define CAN_F1R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 340:28d1f895c6fe 1261 #define CAN_F1R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 340:28d1f895c6fe 1262 #define CAN_F1R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 340:28d1f895c6fe 1263 #define CAN_F1R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 340:28d1f895c6fe 1264 #define CAN_F1R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 340:28d1f895c6fe 1265 #define CAN_F1R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 340:28d1f895c6fe 1266 #define CAN_F1R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 340:28d1f895c6fe 1267 #define CAN_F1R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 340:28d1f895c6fe 1268 #define CAN_F1R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 340:28d1f895c6fe 1269
mbed_official 340:28d1f895c6fe 1270 /******************* Bit definition for CAN_F2R1 register *******************/
mbed_official 340:28d1f895c6fe 1271 #define CAN_F2R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 340:28d1f895c6fe 1272 #define CAN_F2R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 340:28d1f895c6fe 1273 #define CAN_F2R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 340:28d1f895c6fe 1274 #define CAN_F2R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 340:28d1f895c6fe 1275 #define CAN_F2R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 340:28d1f895c6fe 1276 #define CAN_F2R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 340:28d1f895c6fe 1277 #define CAN_F2R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 340:28d1f895c6fe 1278 #define CAN_F2R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 340:28d1f895c6fe 1279 #define CAN_F2R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 340:28d1f895c6fe 1280 #define CAN_F2R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 340:28d1f895c6fe 1281 #define CAN_F2R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 340:28d1f895c6fe 1282 #define CAN_F2R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 340:28d1f895c6fe 1283 #define CAN_F2R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 340:28d1f895c6fe 1284 #define CAN_F2R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 340:28d1f895c6fe 1285 #define CAN_F2R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 340:28d1f895c6fe 1286 #define CAN_F2R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 340:28d1f895c6fe 1287 #define CAN_F2R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 340:28d1f895c6fe 1288 #define CAN_F2R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 340:28d1f895c6fe 1289 #define CAN_F2R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 340:28d1f895c6fe 1290 #define CAN_F2R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 340:28d1f895c6fe 1291 #define CAN_F2R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 340:28d1f895c6fe 1292 #define CAN_F2R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 340:28d1f895c6fe 1293 #define CAN_F2R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 340:28d1f895c6fe 1294 #define CAN_F2R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 340:28d1f895c6fe 1295 #define CAN_F2R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 340:28d1f895c6fe 1296 #define CAN_F2R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 340:28d1f895c6fe 1297 #define CAN_F2R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 340:28d1f895c6fe 1298 #define CAN_F2R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 340:28d1f895c6fe 1299 #define CAN_F2R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 340:28d1f895c6fe 1300 #define CAN_F2R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 340:28d1f895c6fe 1301 #define CAN_F2R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 340:28d1f895c6fe 1302 #define CAN_F2R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 340:28d1f895c6fe 1303
mbed_official 340:28d1f895c6fe 1304 /******************* Bit definition for CAN_F3R1 register *******************/
mbed_official 340:28d1f895c6fe 1305 #define CAN_F3R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 340:28d1f895c6fe 1306 #define CAN_F3R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 340:28d1f895c6fe 1307 #define CAN_F3R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 340:28d1f895c6fe 1308 #define CAN_F3R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 340:28d1f895c6fe 1309 #define CAN_F3R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 340:28d1f895c6fe 1310 #define CAN_F3R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 340:28d1f895c6fe 1311 #define CAN_F3R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 340:28d1f895c6fe 1312 #define CAN_F3R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 340:28d1f895c6fe 1313 #define CAN_F3R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 340:28d1f895c6fe 1314 #define CAN_F3R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 340:28d1f895c6fe 1315 #define CAN_F3R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 340:28d1f895c6fe 1316 #define CAN_F3R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 340:28d1f895c6fe 1317 #define CAN_F3R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 340:28d1f895c6fe 1318 #define CAN_F3R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 340:28d1f895c6fe 1319 #define CAN_F3R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 340:28d1f895c6fe 1320 #define CAN_F3R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 340:28d1f895c6fe 1321 #define CAN_F3R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 340:28d1f895c6fe 1322 #define CAN_F3R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 340:28d1f895c6fe 1323 #define CAN_F3R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 340:28d1f895c6fe 1324 #define CAN_F3R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 340:28d1f895c6fe 1325 #define CAN_F3R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 340:28d1f895c6fe 1326 #define CAN_F3R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 340:28d1f895c6fe 1327 #define CAN_F3R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 340:28d1f895c6fe 1328 #define CAN_F3R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 340:28d1f895c6fe 1329 #define CAN_F3R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 340:28d1f895c6fe 1330 #define CAN_F3R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 340:28d1f895c6fe 1331 #define CAN_F3R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 340:28d1f895c6fe 1332 #define CAN_F3R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 340:28d1f895c6fe 1333 #define CAN_F3R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 340:28d1f895c6fe 1334 #define CAN_F3R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 340:28d1f895c6fe 1335 #define CAN_F3R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 340:28d1f895c6fe 1336 #define CAN_F3R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 340:28d1f895c6fe 1337
mbed_official 340:28d1f895c6fe 1338 /******************* Bit definition for CAN_F4R1 register *******************/
mbed_official 340:28d1f895c6fe 1339 #define CAN_F4R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 340:28d1f895c6fe 1340 #define CAN_F4R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 340:28d1f895c6fe 1341 #define CAN_F4R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 340:28d1f895c6fe 1342 #define CAN_F4R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 340:28d1f895c6fe 1343 #define CAN_F4R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 340:28d1f895c6fe 1344 #define CAN_F4R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 340:28d1f895c6fe 1345 #define CAN_F4R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 340:28d1f895c6fe 1346 #define CAN_F4R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 340:28d1f895c6fe 1347 #define CAN_F4R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 340:28d1f895c6fe 1348 #define CAN_F4R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 340:28d1f895c6fe 1349 #define CAN_F4R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 340:28d1f895c6fe 1350 #define CAN_F4R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 340:28d1f895c6fe 1351 #define CAN_F4R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 340:28d1f895c6fe 1352 #define CAN_F4R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 340:28d1f895c6fe 1353 #define CAN_F4R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 340:28d1f895c6fe 1354 #define CAN_F4R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 340:28d1f895c6fe 1355 #define CAN_F4R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 340:28d1f895c6fe 1356 #define CAN_F4R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 340:28d1f895c6fe 1357 #define CAN_F4R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 340:28d1f895c6fe 1358 #define CAN_F4R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 340:28d1f895c6fe 1359 #define CAN_F4R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 340:28d1f895c6fe 1360 #define CAN_F4R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 340:28d1f895c6fe 1361 #define CAN_F4R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 340:28d1f895c6fe 1362 #define CAN_F4R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 340:28d1f895c6fe 1363 #define CAN_F4R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 340:28d1f895c6fe 1364 #define CAN_F4R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 340:28d1f895c6fe 1365 #define CAN_F4R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 340:28d1f895c6fe 1366 #define CAN_F4R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 340:28d1f895c6fe 1367 #define CAN_F4R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 340:28d1f895c6fe 1368 #define CAN_F4R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 340:28d1f895c6fe 1369 #define CAN_F4R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 340:28d1f895c6fe 1370 #define CAN_F4R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 340:28d1f895c6fe 1371
mbed_official 340:28d1f895c6fe 1372 /******************* Bit definition for CAN_F5R1 register *******************/
mbed_official 340:28d1f895c6fe 1373 #define CAN_F5R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 340:28d1f895c6fe 1374 #define CAN_F5R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 340:28d1f895c6fe 1375 #define CAN_F5R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 340:28d1f895c6fe 1376 #define CAN_F5R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 340:28d1f895c6fe 1377 #define CAN_F5R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 340:28d1f895c6fe 1378 #define CAN_F5R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 340:28d1f895c6fe 1379 #define CAN_F5R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 340:28d1f895c6fe 1380 #define CAN_F5R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 340:28d1f895c6fe 1381 #define CAN_F5R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 340:28d1f895c6fe 1382 #define CAN_F5R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 340:28d1f895c6fe 1383 #define CAN_F5R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 340:28d1f895c6fe 1384 #define CAN_F5R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 340:28d1f895c6fe 1385 #define CAN_F5R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 340:28d1f895c6fe 1386 #define CAN_F5R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 340:28d1f895c6fe 1387 #define CAN_F5R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 340:28d1f895c6fe 1388 #define CAN_F5R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 340:28d1f895c6fe 1389 #define CAN_F5R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 340:28d1f895c6fe 1390 #define CAN_F5R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 340:28d1f895c6fe 1391 #define CAN_F5R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 340:28d1f895c6fe 1392 #define CAN_F5R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 340:28d1f895c6fe 1393 #define CAN_F5R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 340:28d1f895c6fe 1394 #define CAN_F5R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 340:28d1f895c6fe 1395 #define CAN_F5R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 340:28d1f895c6fe 1396 #define CAN_F5R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 340:28d1f895c6fe 1397 #define CAN_F5R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 340:28d1f895c6fe 1398 #define CAN_F5R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 340:28d1f895c6fe 1399 #define CAN_F5R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 340:28d1f895c6fe 1400 #define CAN_F5R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 340:28d1f895c6fe 1401 #define CAN_F5R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 340:28d1f895c6fe 1402 #define CAN_F5R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 340:28d1f895c6fe 1403 #define CAN_F5R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 340:28d1f895c6fe 1404 #define CAN_F5R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 340:28d1f895c6fe 1405
mbed_official 340:28d1f895c6fe 1406 /******************* Bit definition for CAN_F6R1 register *******************/
mbed_official 340:28d1f895c6fe 1407 #define CAN_F6R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 340:28d1f895c6fe 1408 #define CAN_F6R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 340:28d1f895c6fe 1409 #define CAN_F6R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 340:28d1f895c6fe 1410 #define CAN_F6R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 340:28d1f895c6fe 1411 #define CAN_F6R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 340:28d1f895c6fe 1412 #define CAN_F6R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 340:28d1f895c6fe 1413 #define CAN_F6R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 340:28d1f895c6fe 1414 #define CAN_F6R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 340:28d1f895c6fe 1415 #define CAN_F6R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 340:28d1f895c6fe 1416 #define CAN_F6R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 340:28d1f895c6fe 1417 #define CAN_F6R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 340:28d1f895c6fe 1418 #define CAN_F6R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 340:28d1f895c6fe 1419 #define CAN_F6R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 340:28d1f895c6fe 1420 #define CAN_F6R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 340:28d1f895c6fe 1421 #define CAN_F6R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 340:28d1f895c6fe 1422 #define CAN_F6R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 340:28d1f895c6fe 1423 #define CAN_F6R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 340:28d1f895c6fe 1424 #define CAN_F6R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 340:28d1f895c6fe 1425 #define CAN_F6R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 340:28d1f895c6fe 1426 #define CAN_F6R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 340:28d1f895c6fe 1427 #define CAN_F6R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 340:28d1f895c6fe 1428 #define CAN_F6R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 340:28d1f895c6fe 1429 #define CAN_F6R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 340:28d1f895c6fe 1430 #define CAN_F6R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 340:28d1f895c6fe 1431 #define CAN_F6R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 340:28d1f895c6fe 1432 #define CAN_F6R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 340:28d1f895c6fe 1433 #define CAN_F6R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 340:28d1f895c6fe 1434 #define CAN_F6R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 340:28d1f895c6fe 1435 #define CAN_F6R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 340:28d1f895c6fe 1436 #define CAN_F6R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 340:28d1f895c6fe 1437 #define CAN_F6R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 340:28d1f895c6fe 1438 #define CAN_F6R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 340:28d1f895c6fe 1439
mbed_official 340:28d1f895c6fe 1440 /******************* Bit definition for CAN_F7R1 register *******************/
mbed_official 340:28d1f895c6fe 1441 #define CAN_F7R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 340:28d1f895c6fe 1442 #define CAN_F7R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 340:28d1f895c6fe 1443 #define CAN_F7R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 340:28d1f895c6fe 1444 #define CAN_F7R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 340:28d1f895c6fe 1445 #define CAN_F7R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 340:28d1f895c6fe 1446 #define CAN_F7R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 340:28d1f895c6fe 1447 #define CAN_F7R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 340:28d1f895c6fe 1448 #define CAN_F7R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 340:28d1f895c6fe 1449 #define CAN_F7R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 340:28d1f895c6fe 1450 #define CAN_F7R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 340:28d1f895c6fe 1451 #define CAN_F7R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 340:28d1f895c6fe 1452 #define CAN_F7R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 340:28d1f895c6fe 1453 #define CAN_F7R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 340:28d1f895c6fe 1454 #define CAN_F7R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 340:28d1f895c6fe 1455 #define CAN_F7R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 340:28d1f895c6fe 1456 #define CAN_F7R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 340:28d1f895c6fe 1457 #define CAN_F7R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 340:28d1f895c6fe 1458 #define CAN_F7R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 340:28d1f895c6fe 1459 #define CAN_F7R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 340:28d1f895c6fe 1460 #define CAN_F7R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 340:28d1f895c6fe 1461 #define CAN_F7R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 340:28d1f895c6fe 1462 #define CAN_F7R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 340:28d1f895c6fe 1463 #define CAN_F7R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 340:28d1f895c6fe 1464 #define CAN_F7R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 340:28d1f895c6fe 1465 #define CAN_F7R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 340:28d1f895c6fe 1466 #define CAN_F7R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 340:28d1f895c6fe 1467 #define CAN_F7R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 340:28d1f895c6fe 1468 #define CAN_F7R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 340:28d1f895c6fe 1469 #define CAN_F7R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 340:28d1f895c6fe 1470 #define CAN_F7R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 340:28d1f895c6fe 1471 #define CAN_F7R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 340:28d1f895c6fe 1472 #define CAN_F7R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 340:28d1f895c6fe 1473
mbed_official 340:28d1f895c6fe 1474 /******************* Bit definition for CAN_F8R1 register *******************/
mbed_official 340:28d1f895c6fe 1475 #define CAN_F8R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 340:28d1f895c6fe 1476 #define CAN_F8R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 340:28d1f895c6fe 1477 #define CAN_F8R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 340:28d1f895c6fe 1478 #define CAN_F8R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 340:28d1f895c6fe 1479 #define CAN_F8R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 340:28d1f895c6fe 1480 #define CAN_F8R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 340:28d1f895c6fe 1481 #define CAN_F8R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 340:28d1f895c6fe 1482 #define CAN_F8R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 340:28d1f895c6fe 1483 #define CAN_F8R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 340:28d1f895c6fe 1484 #define CAN_F8R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 340:28d1f895c6fe 1485 #define CAN_F8R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 340:28d1f895c6fe 1486 #define CAN_F8R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 340:28d1f895c6fe 1487 #define CAN_F8R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 340:28d1f895c6fe 1488 #define CAN_F8R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 340:28d1f895c6fe 1489 #define CAN_F8R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 340:28d1f895c6fe 1490 #define CAN_F8R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 340:28d1f895c6fe 1491 #define CAN_F8R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 340:28d1f895c6fe 1492 #define CAN_F8R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 340:28d1f895c6fe 1493 #define CAN_F8R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 340:28d1f895c6fe 1494 #define CAN_F8R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 340:28d1f895c6fe 1495 #define CAN_F8R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 340:28d1f895c6fe 1496 #define CAN_F8R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 340:28d1f895c6fe 1497 #define CAN_F8R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 340:28d1f895c6fe 1498 #define CAN_F8R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 340:28d1f895c6fe 1499 #define CAN_F8R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 340:28d1f895c6fe 1500 #define CAN_F8R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 340:28d1f895c6fe 1501 #define CAN_F8R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 340:28d1f895c6fe 1502 #define CAN_F8R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 340:28d1f895c6fe 1503 #define CAN_F8R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 340:28d1f895c6fe 1504 #define CAN_F8R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 340:28d1f895c6fe 1505 #define CAN_F8R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 340:28d1f895c6fe 1506 #define CAN_F8R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 340:28d1f895c6fe 1507
mbed_official 340:28d1f895c6fe 1508 /******************* Bit definition for CAN_F9R1 register *******************/
mbed_official 340:28d1f895c6fe 1509 #define CAN_F9R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 340:28d1f895c6fe 1510 #define CAN_F9R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 340:28d1f895c6fe 1511 #define CAN_F9R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 340:28d1f895c6fe 1512 #define CAN_F9R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 340:28d1f895c6fe 1513 #define CAN_F9R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 340:28d1f895c6fe 1514 #define CAN_F9R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 340:28d1f895c6fe 1515 #define CAN_F9R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 340:28d1f895c6fe 1516 #define CAN_F9R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 340:28d1f895c6fe 1517 #define CAN_F9R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 340:28d1f895c6fe 1518 #define CAN_F9R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 340:28d1f895c6fe 1519 #define CAN_F9R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 340:28d1f895c6fe 1520 #define CAN_F9R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 340:28d1f895c6fe 1521 #define CAN_F9R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 340:28d1f895c6fe 1522 #define CAN_F9R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 340:28d1f895c6fe 1523 #define CAN_F9R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 340:28d1f895c6fe 1524 #define CAN_F9R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 340:28d1f895c6fe 1525 #define CAN_F9R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 340:28d1f895c6fe 1526 #define CAN_F9R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 340:28d1f895c6fe 1527 #define CAN_F9R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 340:28d1f895c6fe 1528 #define CAN_F9R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 340:28d1f895c6fe 1529 #define CAN_F9R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 340:28d1f895c6fe 1530 #define CAN_F9R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 340:28d1f895c6fe 1531 #define CAN_F9R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 340:28d1f895c6fe 1532 #define CAN_F9R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 340:28d1f895c6fe 1533 #define CAN_F9R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 340:28d1f895c6fe 1534 #define CAN_F9R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 340:28d1f895c6fe 1535 #define CAN_F9R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 340:28d1f895c6fe 1536 #define CAN_F9R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 340:28d1f895c6fe 1537 #define CAN_F9R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 340:28d1f895c6fe 1538 #define CAN_F9R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 340:28d1f895c6fe 1539 #define CAN_F9R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 340:28d1f895c6fe 1540 #define CAN_F9R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 340:28d1f895c6fe 1541
mbed_official 340:28d1f895c6fe 1542 /******************* Bit definition for CAN_F10R1 register ******************/
mbed_official 340:28d1f895c6fe 1543 #define CAN_F10R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 340:28d1f895c6fe 1544 #define CAN_F10R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 340:28d1f895c6fe 1545 #define CAN_F10R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 340:28d1f895c6fe 1546 #define CAN_F10R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 340:28d1f895c6fe 1547 #define CAN_F10R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 340:28d1f895c6fe 1548 #define CAN_F10R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 340:28d1f895c6fe 1549 #define CAN_F10R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 340:28d1f895c6fe 1550 #define CAN_F10R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 340:28d1f895c6fe 1551 #define CAN_F10R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 340:28d1f895c6fe 1552 #define CAN_F10R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 340:28d1f895c6fe 1553 #define CAN_F10R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 340:28d1f895c6fe 1554 #define CAN_F10R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 340:28d1f895c6fe 1555 #define CAN_F10R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 340:28d1f895c6fe 1556 #define CAN_F10R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 340:28d1f895c6fe 1557 #define CAN_F10R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 340:28d1f895c6fe 1558 #define CAN_F10R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 340:28d1f895c6fe 1559 #define CAN_F10R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 340:28d1f895c6fe 1560 #define CAN_F10R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 340:28d1f895c6fe 1561 #define CAN_F10R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 340:28d1f895c6fe 1562 #define CAN_F10R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 340:28d1f895c6fe 1563 #define CAN_F10R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 340:28d1f895c6fe 1564 #define CAN_F10R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 340:28d1f895c6fe 1565 #define CAN_F10R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 340:28d1f895c6fe 1566 #define CAN_F10R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 340:28d1f895c6fe 1567 #define CAN_F10R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 340:28d1f895c6fe 1568 #define CAN_F10R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 340:28d1f895c6fe 1569 #define CAN_F10R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 340:28d1f895c6fe 1570 #define CAN_F10R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 340:28d1f895c6fe 1571 #define CAN_F10R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 340:28d1f895c6fe 1572 #define CAN_F10R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 340:28d1f895c6fe 1573 #define CAN_F10R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 340:28d1f895c6fe 1574 #define CAN_F10R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 340:28d1f895c6fe 1575
mbed_official 340:28d1f895c6fe 1576 /******************* Bit definition for CAN_F11R1 register ******************/
mbed_official 340:28d1f895c6fe 1577 #define CAN_F11R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 340:28d1f895c6fe 1578 #define CAN_F11R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 340:28d1f895c6fe 1579 #define CAN_F11R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 340:28d1f895c6fe 1580 #define CAN_F11R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 340:28d1f895c6fe 1581 #define CAN_F11R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 340:28d1f895c6fe 1582 #define CAN_F11R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 340:28d1f895c6fe 1583 #define CAN_F11R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 340:28d1f895c6fe 1584 #define CAN_F11R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 340:28d1f895c6fe 1585 #define CAN_F11R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 340:28d1f895c6fe 1586 #define CAN_F11R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 340:28d1f895c6fe 1587 #define CAN_F11R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 340:28d1f895c6fe 1588 #define CAN_F11R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 340:28d1f895c6fe 1589 #define CAN_F11R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 340:28d1f895c6fe 1590 #define CAN_F11R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 340:28d1f895c6fe 1591 #define CAN_F11R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 340:28d1f895c6fe 1592 #define CAN_F11R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 340:28d1f895c6fe 1593 #define CAN_F11R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 340:28d1f895c6fe 1594 #define CAN_F11R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 340:28d1f895c6fe 1595 #define CAN_F11R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 340:28d1f895c6fe 1596 #define CAN_F11R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 340:28d1f895c6fe 1597 #define CAN_F11R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 340:28d1f895c6fe 1598 #define CAN_F11R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 340:28d1f895c6fe 1599 #define CAN_F11R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 340:28d1f895c6fe 1600 #define CAN_F11R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 340:28d1f895c6fe 1601 #define CAN_F11R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 340:28d1f895c6fe 1602 #define CAN_F11R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 340:28d1f895c6fe 1603 #define CAN_F11R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 340:28d1f895c6fe 1604 #define CAN_F11R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 340:28d1f895c6fe 1605 #define CAN_F11R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 340:28d1f895c6fe 1606 #define CAN_F11R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 340:28d1f895c6fe 1607 #define CAN_F11R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 340:28d1f895c6fe 1608 #define CAN_F11R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 340:28d1f895c6fe 1609
mbed_official 340:28d1f895c6fe 1610 /******************* Bit definition for CAN_F12R1 register ******************/
mbed_official 340:28d1f895c6fe 1611 #define CAN_F12R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 340:28d1f895c6fe 1612 #define CAN_F12R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 340:28d1f895c6fe 1613 #define CAN_F12R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 340:28d1f895c6fe 1614 #define CAN_F12R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 340:28d1f895c6fe 1615 #define CAN_F12R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 340:28d1f895c6fe 1616 #define CAN_F12R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 340:28d1f895c6fe 1617 #define CAN_F12R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 340:28d1f895c6fe 1618 #define CAN_F12R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 340:28d1f895c6fe 1619 #define CAN_F12R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 340:28d1f895c6fe 1620 #define CAN_F12R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 340:28d1f895c6fe 1621 #define CAN_F12R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 340:28d1f895c6fe 1622 #define CAN_F12R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 340:28d1f895c6fe 1623 #define CAN_F12R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 340:28d1f895c6fe 1624 #define CAN_F12R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 340:28d1f895c6fe 1625 #define CAN_F12R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 340:28d1f895c6fe 1626 #define CAN_F12R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 340:28d1f895c6fe 1627 #define CAN_F12R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 340:28d1f895c6fe 1628 #define CAN_F12R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 340:28d1f895c6fe 1629 #define CAN_F12R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 340:28d1f895c6fe 1630 #define CAN_F12R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 340:28d1f895c6fe 1631 #define CAN_F12R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 340:28d1f895c6fe 1632 #define CAN_F12R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 340:28d1f895c6fe 1633 #define CAN_F12R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 340:28d1f895c6fe 1634 #define CAN_F12R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 340:28d1f895c6fe 1635 #define CAN_F12R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 340:28d1f895c6fe 1636 #define CAN_F12R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 340:28d1f895c6fe 1637 #define CAN_F12R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 340:28d1f895c6fe 1638 #define CAN_F12R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 340:28d1f895c6fe 1639 #define CAN_F12R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 340:28d1f895c6fe 1640 #define CAN_F12R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 340:28d1f895c6fe 1641 #define CAN_F12R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 340:28d1f895c6fe 1642 #define CAN_F12R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 340:28d1f895c6fe 1643
mbed_official 340:28d1f895c6fe 1644 /******************* Bit definition for CAN_F13R1 register ******************/
mbed_official 340:28d1f895c6fe 1645 #define CAN_F13R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 340:28d1f895c6fe 1646 #define CAN_F13R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 340:28d1f895c6fe 1647 #define CAN_F13R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 340:28d1f895c6fe 1648 #define CAN_F13R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 340:28d1f895c6fe 1649 #define CAN_F13R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 340:28d1f895c6fe 1650 #define CAN_F13R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 340:28d1f895c6fe 1651 #define CAN_F13R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 340:28d1f895c6fe 1652 #define CAN_F13R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 340:28d1f895c6fe 1653 #define CAN_F13R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 340:28d1f895c6fe 1654 #define CAN_F13R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 340:28d1f895c6fe 1655 #define CAN_F13R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 340:28d1f895c6fe 1656 #define CAN_F13R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 340:28d1f895c6fe 1657 #define CAN_F13R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 340:28d1f895c6fe 1658 #define CAN_F13R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 340:28d1f895c6fe 1659 #define CAN_F13R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 340:28d1f895c6fe 1660 #define CAN_F13R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 340:28d1f895c6fe 1661 #define CAN_F13R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 340:28d1f895c6fe 1662 #define CAN_F13R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 340:28d1f895c6fe 1663 #define CAN_F13R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 340:28d1f895c6fe 1664 #define CAN_F13R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 340:28d1f895c6fe 1665 #define CAN_F13R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 340:28d1f895c6fe 1666 #define CAN_F13R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 340:28d1f895c6fe 1667 #define CAN_F13R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 340:28d1f895c6fe 1668 #define CAN_F13R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 340:28d1f895c6fe 1669 #define CAN_F13R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 340:28d1f895c6fe 1670 #define CAN_F13R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 340:28d1f895c6fe 1671 #define CAN_F13R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 340:28d1f895c6fe 1672 #define CAN_F13R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 340:28d1f895c6fe 1673 #define CAN_F13R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 340:28d1f895c6fe 1674 #define CAN_F13R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 340:28d1f895c6fe 1675 #define CAN_F13R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 340:28d1f895c6fe 1676 #define CAN_F13R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 340:28d1f895c6fe 1677
mbed_official 340:28d1f895c6fe 1678 /******************* Bit definition for CAN_F0R2 register *******************/
mbed_official 340:28d1f895c6fe 1679 #define CAN_F0R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 340:28d1f895c6fe 1680 #define CAN_F0R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 340:28d1f895c6fe 1681 #define CAN_F0R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 340:28d1f895c6fe 1682 #define CAN_F0R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 340:28d1f895c6fe 1683 #define CAN_F0R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 340:28d1f895c6fe 1684 #define CAN_F0R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 340:28d1f895c6fe 1685 #define CAN_F0R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 340:28d1f895c6fe 1686 #define CAN_F0R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 340:28d1f895c6fe 1687 #define CAN_F0R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 340:28d1f895c6fe 1688 #define CAN_F0R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 340:28d1f895c6fe 1689 #define CAN_F0R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 340:28d1f895c6fe 1690 #define CAN_F0R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 340:28d1f895c6fe 1691 #define CAN_F0R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 340:28d1f895c6fe 1692 #define CAN_F0R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 340:28d1f895c6fe 1693 #define CAN_F0R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 340:28d1f895c6fe 1694 #define CAN_F0R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 340:28d1f895c6fe 1695 #define CAN_F0R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 340:28d1f895c6fe 1696 #define CAN_F0R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 340:28d1f895c6fe 1697 #define CAN_F0R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 340:28d1f895c6fe 1698 #define CAN_F0R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 340:28d1f895c6fe 1699 #define CAN_F0R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 340:28d1f895c6fe 1700 #define CAN_F0R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 340:28d1f895c6fe 1701 #define CAN_F0R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 340:28d1f895c6fe 1702 #define CAN_F0R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 340:28d1f895c6fe 1703 #define CAN_F0R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 340:28d1f895c6fe 1704 #define CAN_F0R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 340:28d1f895c6fe 1705 #define CAN_F0R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 340:28d1f895c6fe 1706 #define CAN_F0R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 340:28d1f895c6fe 1707 #define CAN_F0R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 340:28d1f895c6fe 1708 #define CAN_F0R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 340:28d1f895c6fe 1709 #define CAN_F0R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 340:28d1f895c6fe 1710 #define CAN_F0R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 340:28d1f895c6fe 1711
mbed_official 340:28d1f895c6fe 1712 /******************* Bit definition for CAN_F1R2 register *******************/
mbed_official 340:28d1f895c6fe 1713 #define CAN_F1R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 340:28d1f895c6fe 1714 #define CAN_F1R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 340:28d1f895c6fe 1715 #define CAN_F1R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 340:28d1f895c6fe 1716 #define CAN_F1R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 340:28d1f895c6fe 1717 #define CAN_F1R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 340:28d1f895c6fe 1718 #define CAN_F1R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 340:28d1f895c6fe 1719 #define CAN_F1R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 340:28d1f895c6fe 1720 #define CAN_F1R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 340:28d1f895c6fe 1721 #define CAN_F1R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 340:28d1f895c6fe 1722 #define CAN_F1R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 340:28d1f895c6fe 1723 #define CAN_F1R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 340:28d1f895c6fe 1724 #define CAN_F1R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 340:28d1f895c6fe 1725 #define CAN_F1R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 340:28d1f895c6fe 1726 #define CAN_F1R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 340:28d1f895c6fe 1727 #define CAN_F1R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 340:28d1f895c6fe 1728 #define CAN_F1R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 340:28d1f895c6fe 1729 #define CAN_F1R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 340:28d1f895c6fe 1730 #define CAN_F1R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 340:28d1f895c6fe 1731 #define CAN_F1R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 340:28d1f895c6fe 1732 #define CAN_F1R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 340:28d1f895c6fe 1733 #define CAN_F1R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 340:28d1f895c6fe 1734 #define CAN_F1R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 340:28d1f895c6fe 1735 #define CAN_F1R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 340:28d1f895c6fe 1736 #define CAN_F1R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 340:28d1f895c6fe 1737 #define CAN_F1R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 340:28d1f895c6fe 1738 #define CAN_F1R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 340:28d1f895c6fe 1739 #define CAN_F1R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 340:28d1f895c6fe 1740 #define CAN_F1R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 340:28d1f895c6fe 1741 #define CAN_F1R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 340:28d1f895c6fe 1742 #define CAN_F1R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 340:28d1f895c6fe 1743 #define CAN_F1R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 340:28d1f895c6fe 1744 #define CAN_F1R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 340:28d1f895c6fe 1745
mbed_official 340:28d1f895c6fe 1746 /******************* Bit definition for CAN_F2R2 register *******************/
mbed_official 340:28d1f895c6fe 1747 #define CAN_F2R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 340:28d1f895c6fe 1748 #define CAN_F2R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 340:28d1f895c6fe 1749 #define CAN_F2R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 340:28d1f895c6fe 1750 #define CAN_F2R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 340:28d1f895c6fe 1751 #define CAN_F2R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 340:28d1f895c6fe 1752 #define CAN_F2R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 340:28d1f895c6fe 1753 #define CAN_F2R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 340:28d1f895c6fe 1754 #define CAN_F2R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 340:28d1f895c6fe 1755 #define CAN_F2R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 340:28d1f895c6fe 1756 #define CAN_F2R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 340:28d1f895c6fe 1757 #define CAN_F2R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 340:28d1f895c6fe 1758 #define CAN_F2R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 340:28d1f895c6fe 1759 #define CAN_F2R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 340:28d1f895c6fe 1760 #define CAN_F2R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 340:28d1f895c6fe 1761 #define CAN_F2R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 340:28d1f895c6fe 1762 #define CAN_F2R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 340:28d1f895c6fe 1763 #define CAN_F2R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 340:28d1f895c6fe 1764 #define CAN_F2R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 340:28d1f895c6fe 1765 #define CAN_F2R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 340:28d1f895c6fe 1766 #define CAN_F2R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 340:28d1f895c6fe 1767 #define CAN_F2R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 340:28d1f895c6fe 1768 #define CAN_F2R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 340:28d1f895c6fe 1769 #define CAN_F2R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 340:28d1f895c6fe 1770 #define CAN_F2R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 340:28d1f895c6fe 1771 #define CAN_F2R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 340:28d1f895c6fe 1772 #define CAN_F2R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 340:28d1f895c6fe 1773 #define CAN_F2R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 340:28d1f895c6fe 1774 #define CAN_F2R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 340:28d1f895c6fe 1775 #define CAN_F2R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 340:28d1f895c6fe 1776 #define CAN_F2R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 340:28d1f895c6fe 1777 #define CAN_F2R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 340:28d1f895c6fe 1778 #define CAN_F2R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 340:28d1f895c6fe 1779
mbed_official 340:28d1f895c6fe 1780 /******************* Bit definition for CAN_F3R2 register *******************/
mbed_official 340:28d1f895c6fe 1781 #define CAN_F3R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 340:28d1f895c6fe 1782 #define CAN_F3R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 340:28d1f895c6fe 1783 #define CAN_F3R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 340:28d1f895c6fe 1784 #define CAN_F3R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 340:28d1f895c6fe 1785 #define CAN_F3R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 340:28d1f895c6fe 1786 #define CAN_F3R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 340:28d1f895c6fe 1787 #define CAN_F3R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 340:28d1f895c6fe 1788 #define CAN_F3R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 340:28d1f895c6fe 1789 #define CAN_F3R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 340:28d1f895c6fe 1790 #define CAN_F3R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 340:28d1f895c6fe 1791 #define CAN_F3R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 340:28d1f895c6fe 1792 #define CAN_F3R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 340:28d1f895c6fe 1793 #define CAN_F3R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 340:28d1f895c6fe 1794 #define CAN_F3R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 340:28d1f895c6fe 1795 #define CAN_F3R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 340:28d1f895c6fe 1796 #define CAN_F3R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 340:28d1f895c6fe 1797 #define CAN_F3R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 340:28d1f895c6fe 1798 #define CAN_F3R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 340:28d1f895c6fe 1799 #define CAN_F3R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 340:28d1f895c6fe 1800 #define CAN_F3R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 340:28d1f895c6fe 1801 #define CAN_F3R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 340:28d1f895c6fe 1802 #define CAN_F3R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 340:28d1f895c6fe 1803 #define CAN_F3R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 340:28d1f895c6fe 1804 #define CAN_F3R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 340:28d1f895c6fe 1805 #define CAN_F3R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 340:28d1f895c6fe 1806 #define CAN_F3R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 340:28d1f895c6fe 1807 #define CAN_F3R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 340:28d1f895c6fe 1808 #define CAN_F3R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 340:28d1f895c6fe 1809 #define CAN_F3R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 340:28d1f895c6fe 1810 #define CAN_F3R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 340:28d1f895c6fe 1811 #define CAN_F3R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 340:28d1f895c6fe 1812 #define CAN_F3R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 340:28d1f895c6fe 1813
mbed_official 340:28d1f895c6fe 1814 /******************* Bit definition for CAN_F4R2 register *******************/
mbed_official 340:28d1f895c6fe 1815 #define CAN_F4R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 340:28d1f895c6fe 1816 #define CAN_F4R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 340:28d1f895c6fe 1817 #define CAN_F4R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 340:28d1f895c6fe 1818 #define CAN_F4R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 340:28d1f895c6fe 1819 #define CAN_F4R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 340:28d1f895c6fe 1820 #define CAN_F4R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 340:28d1f895c6fe 1821 #define CAN_F4R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 340:28d1f895c6fe 1822 #define CAN_F4R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 340:28d1f895c6fe 1823 #define CAN_F4R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 340:28d1f895c6fe 1824 #define CAN_F4R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 340:28d1f895c6fe 1825 #define CAN_F4R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 340:28d1f895c6fe 1826 #define CAN_F4R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 340:28d1f895c6fe 1827 #define CAN_F4R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 340:28d1f895c6fe 1828 #define CAN_F4R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 340:28d1f895c6fe 1829 #define CAN_F4R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 340:28d1f895c6fe 1830 #define CAN_F4R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 340:28d1f895c6fe 1831 #define CAN_F4R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 340:28d1f895c6fe 1832 #define CAN_F4R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 340:28d1f895c6fe 1833 #define CAN_F4R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 340:28d1f895c6fe 1834 #define CAN_F4R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 340:28d1f895c6fe 1835 #define CAN_F4R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 340:28d1f895c6fe 1836 #define CAN_F4R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 340:28d1f895c6fe 1837 #define CAN_F4R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 340:28d1f895c6fe 1838 #define CAN_F4R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 340:28d1f895c6fe 1839 #define CAN_F4R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 340:28d1f895c6fe 1840 #define CAN_F4R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 340:28d1f895c6fe 1841 #define CAN_F4R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 340:28d1f895c6fe 1842 #define CAN_F4R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 340:28d1f895c6fe 1843 #define CAN_F4R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 340:28d1f895c6fe 1844 #define CAN_F4R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 340:28d1f895c6fe 1845 #define CAN_F4R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 340:28d1f895c6fe 1846 #define CAN_F4R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 340:28d1f895c6fe 1847
mbed_official 340:28d1f895c6fe 1848 /******************* Bit definition for CAN_F5R2 register *******************/
mbed_official 340:28d1f895c6fe 1849 #define CAN_F5R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 340:28d1f895c6fe 1850 #define CAN_F5R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 340:28d1f895c6fe 1851 #define CAN_F5R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 340:28d1f895c6fe 1852 #define CAN_F5R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 340:28d1f895c6fe 1853 #define CAN_F5R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 340:28d1f895c6fe 1854 #define CAN_F5R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 340:28d1f895c6fe 1855 #define CAN_F5R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 340:28d1f895c6fe 1856 #define CAN_F5R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 340:28d1f895c6fe 1857 #define CAN_F5R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 340:28d1f895c6fe 1858 #define CAN_F5R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 340:28d1f895c6fe 1859 #define CAN_F5R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 340:28d1f895c6fe 1860 #define CAN_F5R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 340:28d1f895c6fe 1861 #define CAN_F5R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 340:28d1f895c6fe 1862 #define CAN_F5R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 340:28d1f895c6fe 1863 #define CAN_F5R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 340:28d1f895c6fe 1864 #define CAN_F5R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 340:28d1f895c6fe 1865 #define CAN_F5R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 340:28d1f895c6fe 1866 #define CAN_F5R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 340:28d1f895c6fe 1867 #define CAN_F5R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 340:28d1f895c6fe 1868 #define CAN_F5R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 340:28d1f895c6fe 1869 #define CAN_F5R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 340:28d1f895c6fe 1870 #define CAN_F5R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 340:28d1f895c6fe 1871 #define CAN_F5R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 340:28d1f895c6fe 1872 #define CAN_F5R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 340:28d1f895c6fe 1873 #define CAN_F5R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 340:28d1f895c6fe 1874 #define CAN_F5R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 340:28d1f895c6fe 1875 #define CAN_F5R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 340:28d1f895c6fe 1876 #define CAN_F5R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 340:28d1f895c6fe 1877 #define CAN_F5R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 340:28d1f895c6fe 1878 #define CAN_F5R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 340:28d1f895c6fe 1879 #define CAN_F5R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 340:28d1f895c6fe 1880 #define CAN_F5R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 340:28d1f895c6fe 1881
mbed_official 340:28d1f895c6fe 1882 /******************* Bit definition for CAN_F6R2 register *******************/
mbed_official 340:28d1f895c6fe 1883 #define CAN_F6R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 340:28d1f895c6fe 1884 #define CAN_F6R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 340:28d1f895c6fe 1885 #define CAN_F6R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 340:28d1f895c6fe 1886 #define CAN_F6R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 340:28d1f895c6fe 1887 #define CAN_F6R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 340:28d1f895c6fe 1888 #define CAN_F6R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 340:28d1f895c6fe 1889 #define CAN_F6R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 340:28d1f895c6fe 1890 #define CAN_F6R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 340:28d1f895c6fe 1891 #define CAN_F6R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 340:28d1f895c6fe 1892 #define CAN_F6R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 340:28d1f895c6fe 1893 #define CAN_F6R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 340:28d1f895c6fe 1894 #define CAN_F6R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 340:28d1f895c6fe 1895 #define CAN_F6R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 340:28d1f895c6fe 1896 #define CAN_F6R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 340:28d1f895c6fe 1897 #define CAN_F6R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 340:28d1f895c6fe 1898 #define CAN_F6R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 340:28d1f895c6fe 1899 #define CAN_F6R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 340:28d1f895c6fe 1900 #define CAN_F6R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 340:28d1f895c6fe 1901 #define CAN_F6R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 340:28d1f895c6fe 1902 #define CAN_F6R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 340:28d1f895c6fe 1903 #define CAN_F6R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 340:28d1f895c6fe 1904 #define CAN_F6R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 340:28d1f895c6fe 1905 #define CAN_F6R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 340:28d1f895c6fe 1906 #define CAN_F6R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 340:28d1f895c6fe 1907 #define CAN_F6R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 340:28d1f895c6fe 1908 #define CAN_F6R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 340:28d1f895c6fe 1909 #define CAN_F6R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 340:28d1f895c6fe 1910 #define CAN_F6R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 340:28d1f895c6fe 1911 #define CAN_F6R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 340:28d1f895c6fe 1912 #define CAN_F6R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 340:28d1f895c6fe 1913 #define CAN_F6R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 340:28d1f895c6fe 1914 #define CAN_F6R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 340:28d1f895c6fe 1915
mbed_official 340:28d1f895c6fe 1916 /******************* Bit definition for CAN_F7R2 register *******************/
mbed_official 340:28d1f895c6fe 1917 #define CAN_F7R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 340:28d1f895c6fe 1918 #define CAN_F7R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 340:28d1f895c6fe 1919 #define CAN_F7R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 340:28d1f895c6fe 1920 #define CAN_F7R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 340:28d1f895c6fe 1921 #define CAN_F7R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 340:28d1f895c6fe 1922 #define CAN_F7R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 340:28d1f895c6fe 1923 #define CAN_F7R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 340:28d1f895c6fe 1924 #define CAN_F7R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 340:28d1f895c6fe 1925 #define CAN_F7R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 340:28d1f895c6fe 1926 #define CAN_F7R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 340:28d1f895c6fe 1927 #define CAN_F7R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 340:28d1f895c6fe 1928 #define CAN_F7R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 340:28d1f895c6fe 1929 #define CAN_F7R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 340:28d1f895c6fe 1930 #define CAN_F7R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 340:28d1f895c6fe 1931 #define CAN_F7R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 340:28d1f895c6fe 1932 #define CAN_F7R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 340:28d1f895c6fe 1933 #define CAN_F7R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 340:28d1f895c6fe 1934 #define CAN_F7R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 340:28d1f895c6fe 1935 #define CAN_F7R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 340:28d1f895c6fe 1936 #define CAN_F7R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 340:28d1f895c6fe 1937 #define CAN_F7R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 340:28d1f895c6fe 1938 #define CAN_F7R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 340:28d1f895c6fe 1939 #define CAN_F7R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 340:28d1f895c6fe 1940 #define CAN_F7R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 340:28d1f895c6fe 1941 #define CAN_F7R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 340:28d1f895c6fe 1942 #define CAN_F7R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 340:28d1f895c6fe 1943 #define CAN_F7R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 340:28d1f895c6fe 1944 #define CAN_F7R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 340:28d1f895c6fe 1945 #define CAN_F7R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 340:28d1f895c6fe 1946 #define CAN_F7R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 340:28d1f895c6fe 1947 #define CAN_F7R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 340:28d1f895c6fe 1948 #define CAN_F7R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 340:28d1f895c6fe 1949
mbed_official 340:28d1f895c6fe 1950 /******************* Bit definition for CAN_F8R2 register *******************/
mbed_official 340:28d1f895c6fe 1951 #define CAN_F8R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 340:28d1f895c6fe 1952 #define CAN_F8R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 340:28d1f895c6fe 1953 #define CAN_F8R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 340:28d1f895c6fe 1954 #define CAN_F8R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 340:28d1f895c6fe 1955 #define CAN_F8R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 340:28d1f895c6fe 1956 #define CAN_F8R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 340:28d1f895c6fe 1957 #define CAN_F8R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 340:28d1f895c6fe 1958 #define CAN_F8R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 340:28d1f895c6fe 1959 #define CAN_F8R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 340:28d1f895c6fe 1960 #define CAN_F8R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 340:28d1f895c6fe 1961 #define CAN_F8R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 340:28d1f895c6fe 1962 #define CAN_F8R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 340:28d1f895c6fe 1963 #define CAN_F8R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 340:28d1f895c6fe 1964 #define CAN_F8R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 340:28d1f895c6fe 1965 #define CAN_F8R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 340:28d1f895c6fe 1966 #define CAN_F8R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 340:28d1f895c6fe 1967 #define CAN_F8R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 340:28d1f895c6fe 1968 #define CAN_F8R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 340:28d1f895c6fe 1969 #define CAN_F8R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 340:28d1f895c6fe 1970 #define CAN_F8R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 340:28d1f895c6fe 1971 #define CAN_F8R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 340:28d1f895c6fe 1972 #define CAN_F8R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 340:28d1f895c6fe 1973 #define CAN_F8R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 340:28d1f895c6fe 1974 #define CAN_F8R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 340:28d1f895c6fe 1975 #define CAN_F8R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 340:28d1f895c6fe 1976 #define CAN_F8R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 340:28d1f895c6fe 1977 #define CAN_F8R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 340:28d1f895c6fe 1978 #define CAN_F8R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 340:28d1f895c6fe 1979 #define CAN_F8R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 340:28d1f895c6fe 1980 #define CAN_F8R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 340:28d1f895c6fe 1981 #define CAN_F8R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 340:28d1f895c6fe 1982 #define CAN_F8R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 340:28d1f895c6fe 1983
mbed_official 340:28d1f895c6fe 1984 /******************* Bit definition for CAN_F9R2 register *******************/
mbed_official 340:28d1f895c6fe 1985 #define CAN_F9R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 340:28d1f895c6fe 1986 #define CAN_F9R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 340:28d1f895c6fe 1987 #define CAN_F9R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 340:28d1f895c6fe 1988 #define CAN_F9R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 340:28d1f895c6fe 1989 #define CAN_F9R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 340:28d1f895c6fe 1990 #define CAN_F9R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 340:28d1f895c6fe 1991 #define CAN_F9R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 340:28d1f895c6fe 1992 #define CAN_F9R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 340:28d1f895c6fe 1993 #define CAN_F9R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 340:28d1f895c6fe 1994 #define CAN_F9R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 340:28d1f895c6fe 1995 #define CAN_F9R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 340:28d1f895c6fe 1996 #define CAN_F9R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 340:28d1f895c6fe 1997 #define CAN_F9R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 340:28d1f895c6fe 1998 #define CAN_F9R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 340:28d1f895c6fe 1999 #define CAN_F9R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 340:28d1f895c6fe 2000 #define CAN_F9R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 340:28d1f895c6fe 2001 #define CAN_F9R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 340:28d1f895c6fe 2002 #define CAN_F9R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 340:28d1f895c6fe 2003 #define CAN_F9R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 340:28d1f895c6fe 2004 #define CAN_F9R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 340:28d1f895c6fe 2005 #define CAN_F9R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 340:28d1f895c6fe 2006 #define CAN_F9R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 340:28d1f895c6fe 2007 #define CAN_F9R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 340:28d1f895c6fe 2008 #define CAN_F9R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 340:28d1f895c6fe 2009 #define CAN_F9R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 340:28d1f895c6fe 2010 #define CAN_F9R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 340:28d1f895c6fe 2011 #define CAN_F9R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 340:28d1f895c6fe 2012 #define CAN_F9R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 340:28d1f895c6fe 2013 #define CAN_F9R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 340:28d1f895c6fe 2014 #define CAN_F9R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 340:28d1f895c6fe 2015 #define CAN_F9R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 340:28d1f895c6fe 2016 #define CAN_F9R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 340:28d1f895c6fe 2017
mbed_official 340:28d1f895c6fe 2018 /******************* Bit definition for CAN_F10R2 register ******************/
mbed_official 340:28d1f895c6fe 2019 #define CAN_F10R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 340:28d1f895c6fe 2020 #define CAN_F10R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 340:28d1f895c6fe 2021 #define CAN_F10R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 340:28d1f895c6fe 2022 #define CAN_F10R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 340:28d1f895c6fe 2023 #define CAN_F10R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 340:28d1f895c6fe 2024 #define CAN_F10R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 340:28d1f895c6fe 2025 #define CAN_F10R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 340:28d1f895c6fe 2026 #define CAN_F10R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 340:28d1f895c6fe 2027 #define CAN_F10R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 340:28d1f895c6fe 2028 #define CAN_F10R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 340:28d1f895c6fe 2029 #define CAN_F10R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 340:28d1f895c6fe 2030 #define CAN_F10R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 340:28d1f895c6fe 2031 #define CAN_F10R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 340:28d1f895c6fe 2032 #define CAN_F10R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 340:28d1f895c6fe 2033 #define CAN_F10R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 340:28d1f895c6fe 2034 #define CAN_F10R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 340:28d1f895c6fe 2035 #define CAN_F10R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 340:28d1f895c6fe 2036 #define CAN_F10R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 340:28d1f895c6fe 2037 #define CAN_F10R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 340:28d1f895c6fe 2038 #define CAN_F10R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 340:28d1f895c6fe 2039 #define CAN_F10R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 340:28d1f895c6fe 2040 #define CAN_F10R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 340:28d1f895c6fe 2041 #define CAN_F10R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 340:28d1f895c6fe 2042 #define CAN_F10R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 340:28d1f895c6fe 2043 #define CAN_F10R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 340:28d1f895c6fe 2044 #define CAN_F10R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 340:28d1f895c6fe 2045 #define CAN_F10R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 340:28d1f895c6fe 2046 #define CAN_F10R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 340:28d1f895c6fe 2047 #define CAN_F10R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 340:28d1f895c6fe 2048 #define CAN_F10R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 340:28d1f895c6fe 2049 #define CAN_F10R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 340:28d1f895c6fe 2050 #define CAN_F10R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 340:28d1f895c6fe 2051
mbed_official 340:28d1f895c6fe 2052 /******************* Bit definition for CAN_F11R2 register ******************/
mbed_official 340:28d1f895c6fe 2053 #define CAN_F11R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 340:28d1f895c6fe 2054 #define CAN_F11R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 340:28d1f895c6fe 2055 #define CAN_F11R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 340:28d1f895c6fe 2056 #define CAN_F11R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 340:28d1f895c6fe 2057 #define CAN_F11R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 340:28d1f895c6fe 2058 #define CAN_F11R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 340:28d1f895c6fe 2059 #define CAN_F11R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 340:28d1f895c6fe 2060 #define CAN_F11R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 340:28d1f895c6fe 2061 #define CAN_F11R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 340:28d1f895c6fe 2062 #define CAN_F11R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 340:28d1f895c6fe 2063 #define CAN_F11R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 340:28d1f895c6fe 2064 #define CAN_F11R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 340:28d1f895c6fe 2065 #define CAN_F11R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 340:28d1f895c6fe 2066 #define CAN_F11R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 340:28d1f895c6fe 2067 #define CAN_F11R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 340:28d1f895c6fe 2068 #define CAN_F11R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 340:28d1f895c6fe 2069 #define CAN_F11R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 340:28d1f895c6fe 2070 #define CAN_F11R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 340:28d1f895c6fe 2071 #define CAN_F11R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 340:28d1f895c6fe 2072 #define CAN_F11R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 340:28d1f895c6fe 2073 #define CAN_F11R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 340:28d1f895c6fe 2074 #define CAN_F11R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 340:28d1f895c6fe 2075 #define CAN_F11R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 340:28d1f895c6fe 2076 #define CAN_F11R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 340:28d1f895c6fe 2077 #define CAN_F11R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 340:28d1f895c6fe 2078 #define CAN_F11R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 340:28d1f895c6fe 2079 #define CAN_F11R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 340:28d1f895c6fe 2080 #define CAN_F11R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 340:28d1f895c6fe 2081 #define CAN_F11R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 340:28d1f895c6fe 2082 #define CAN_F11R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 340:28d1f895c6fe 2083 #define CAN_F11R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 340:28d1f895c6fe 2084 #define CAN_F11R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 340:28d1f895c6fe 2085
mbed_official 340:28d1f895c6fe 2086 /******************* Bit definition for CAN_F12R2 register ******************/
mbed_official 340:28d1f895c6fe 2087 #define CAN_F12R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 340:28d1f895c6fe 2088 #define CAN_F12R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 340:28d1f895c6fe 2089 #define CAN_F12R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 340:28d1f895c6fe 2090 #define CAN_F12R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 340:28d1f895c6fe 2091 #define CAN_F12R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 340:28d1f895c6fe 2092 #define CAN_F12R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 340:28d1f895c6fe 2093 #define CAN_F12R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 340:28d1f895c6fe 2094 #define CAN_F12R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 340:28d1f895c6fe 2095 #define CAN_F12R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 340:28d1f895c6fe 2096 #define CAN_F12R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 340:28d1f895c6fe 2097 #define CAN_F12R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 340:28d1f895c6fe 2098 #define CAN_F12R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 340:28d1f895c6fe 2099 #define CAN_F12R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 340:28d1f895c6fe 2100 #define CAN_F12R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 340:28d1f895c6fe 2101 #define CAN_F12R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 340:28d1f895c6fe 2102 #define CAN_F12R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 340:28d1f895c6fe 2103 #define CAN_F12R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 340:28d1f895c6fe 2104 #define CAN_F12R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 340:28d1f895c6fe 2105 #define CAN_F12R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 340:28d1f895c6fe 2106 #define CAN_F12R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 340:28d1f895c6fe 2107 #define CAN_F12R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 340:28d1f895c6fe 2108 #define CAN_F12R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 340:28d1f895c6fe 2109 #define CAN_F12R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 340:28d1f895c6fe 2110 #define CAN_F12R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 340:28d1f895c6fe 2111 #define CAN_F12R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 340:28d1f895c6fe 2112 #define CAN_F12R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 340:28d1f895c6fe 2113 #define CAN_F12R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 340:28d1f895c6fe 2114 #define CAN_F12R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 340:28d1f895c6fe 2115 #define CAN_F12R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 340:28d1f895c6fe 2116 #define CAN_F12R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 340:28d1f895c6fe 2117 #define CAN_F12R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 340:28d1f895c6fe 2118 #define CAN_F12R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 340:28d1f895c6fe 2119
mbed_official 340:28d1f895c6fe 2120 /******************* Bit definition for CAN_F13R2 register ******************/
mbed_official 340:28d1f895c6fe 2121 #define CAN_F13R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 340:28d1f895c6fe 2122 #define CAN_F13R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 340:28d1f895c6fe 2123 #define CAN_F13R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 340:28d1f895c6fe 2124 #define CAN_F13R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 340:28d1f895c6fe 2125 #define CAN_F13R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 340:28d1f895c6fe 2126 #define CAN_F13R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 340:28d1f895c6fe 2127 #define CAN_F13R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 340:28d1f895c6fe 2128 #define CAN_F13R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 340:28d1f895c6fe 2129 #define CAN_F13R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 340:28d1f895c6fe 2130 #define CAN_F13R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 340:28d1f895c6fe 2131 #define CAN_F13R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 340:28d1f895c6fe 2132 #define CAN_F13R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 340:28d1f895c6fe 2133 #define CAN_F13R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 340:28d1f895c6fe 2134 #define CAN_F13R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 340:28d1f895c6fe 2135 #define CAN_F13R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 340:28d1f895c6fe 2136 #define CAN_F13R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 340:28d1f895c6fe 2137 #define CAN_F13R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 340:28d1f895c6fe 2138 #define CAN_F13R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 340:28d1f895c6fe 2139 #define CAN_F13R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 340:28d1f895c6fe 2140 #define CAN_F13R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 340:28d1f895c6fe 2141 #define CAN_F13R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 340:28d1f895c6fe 2142 #define CAN_F13R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 340:28d1f895c6fe 2143 #define CAN_F13R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 340:28d1f895c6fe 2144 #define CAN_F13R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 340:28d1f895c6fe 2145 #define CAN_F13R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 340:28d1f895c6fe 2146 #define CAN_F13R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 340:28d1f895c6fe 2147 #define CAN_F13R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 340:28d1f895c6fe 2148 #define CAN_F13R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 340:28d1f895c6fe 2149 #define CAN_F13R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 340:28d1f895c6fe 2150 #define CAN_F13R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 340:28d1f895c6fe 2151 #define CAN_F13R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 340:28d1f895c6fe 2152 #define CAN_F13R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 340:28d1f895c6fe 2153
mbed_official 340:28d1f895c6fe 2154 /******************************************************************************/
mbed_official 340:28d1f895c6fe 2155 /* */
mbed_official 340:28d1f895c6fe 2156 /* HDMI-CEC (CEC) */
mbed_official 340:28d1f895c6fe 2157 /* */
mbed_official 340:28d1f895c6fe 2158 /******************************************************************************/
mbed_official 340:28d1f895c6fe 2159
mbed_official 340:28d1f895c6fe 2160 /******************* Bit definition for CEC_CR register *********************/
mbed_official 340:28d1f895c6fe 2161 #define CEC_CR_CECEN ((uint32_t)0x00000001) /*!< CEC Enable */
mbed_official 340:28d1f895c6fe 2162 #define CEC_CR_TXSOM ((uint32_t)0x00000002) /*!< CEC Tx Start Of Message */
mbed_official 340:28d1f895c6fe 2163 #define CEC_CR_TXEOM ((uint32_t)0x00000004) /*!< CEC Tx End Of Message */
mbed_official 340:28d1f895c6fe 2164
mbed_official 340:28d1f895c6fe 2165 /******************* Bit definition for CEC_CFGR register *******************/
mbed_official 340:28d1f895c6fe 2166 #define CEC_CFGR_SFT ((uint32_t)0x00000007) /*!< CEC Signal Free Time */
mbed_official 340:28d1f895c6fe 2167 #define CEC_CFGR_RXTOL ((uint32_t)0x00000008) /*!< CEC Tolerance */
mbed_official 340:28d1f895c6fe 2168 #define CEC_CFGR_BRESTP ((uint32_t)0x00000010) /*!< CEC Rx Stop */
mbed_official 340:28d1f895c6fe 2169 #define CEC_CFGR_BREGEN ((uint32_t)0x00000020) /*!< CEC Bit Rising Error generation */
mbed_official 340:28d1f895c6fe 2170 #define CEC_CFGR_LBPEGEN ((uint32_t)0x00000040) /*!< CEC Long Bit Period Error gener. */
mbed_official 340:28d1f895c6fe 2171 #define CEC_CFGR_BRDNOGEN ((uint32_t)0x00000080) /*!< CEC Broadcast No Error generation */
mbed_official 340:28d1f895c6fe 2172 #define CEC_CFGR_SFTOPT ((uint32_t)0x00000100) /*!< CEC Signal Free Time optional */
mbed_official 340:28d1f895c6fe 2173 #define CEC_CFGR_OAR ((uint32_t)0x7FFF0000) /*!< CEC Own Address */
mbed_official 340:28d1f895c6fe 2174 #define CEC_CFGR_LSTN ((uint32_t)0x80000000) /*!< CEC Listen mode */
mbed_official 340:28d1f895c6fe 2175
mbed_official 340:28d1f895c6fe 2176 /******************* Bit definition for CEC_TXDR register *******************/
mbed_official 340:28d1f895c6fe 2177 #define CEC_TXDR_TXD ((uint32_t)0x000000FF) /*!< CEC Tx Data */
mbed_official 340:28d1f895c6fe 2178
mbed_official 340:28d1f895c6fe 2179 /******************* Bit definition for CEC_RXDR register *******************/
mbed_official 340:28d1f895c6fe 2180 #define CEC_TXDR_RXD ((uint32_t)0x000000FF) /*!< CEC Rx Data */
mbed_official 340:28d1f895c6fe 2181
mbed_official 340:28d1f895c6fe 2182 /******************* Bit definition for CEC_ISR register ********************/
mbed_official 340:28d1f895c6fe 2183 #define CEC_ISR_RXBR ((uint32_t)0x00000001) /*!< CEC Rx-Byte Received */
mbed_official 340:28d1f895c6fe 2184 #define CEC_ISR_RXEND ((uint32_t)0x00000002) /*!< CEC End Of Reception */
mbed_official 340:28d1f895c6fe 2185 #define CEC_ISR_RXOVR ((uint32_t)0x00000004) /*!< CEC Rx-Overrun */
mbed_official 340:28d1f895c6fe 2186 #define CEC_ISR_BRE ((uint32_t)0x00000008) /*!< CEC Rx Bit Rising Error */
mbed_official 340:28d1f895c6fe 2187 #define CEC_ISR_SBPE ((uint32_t)0x00000010) /*!< CEC Rx Short Bit period Error */
mbed_official 340:28d1f895c6fe 2188 #define CEC_ISR_LBPE ((uint32_t)0x00000020) /*!< CEC Rx Long Bit period Error */
mbed_official 340:28d1f895c6fe 2189 #define CEC_ISR_RXACKE ((uint32_t)0x00000040) /*!< CEC Rx Missing Acknowledge */
mbed_official 340:28d1f895c6fe 2190 #define CEC_ISR_ARBLST ((uint32_t)0x00000080) /*!< CEC Arbitration Lost */
mbed_official 340:28d1f895c6fe 2191 #define CEC_ISR_TXBR ((uint32_t)0x00000100) /*!< CEC Tx Byte Request */
mbed_official 340:28d1f895c6fe 2192 #define CEC_ISR_TXEND ((uint32_t)0x00000200) /*!< CEC End of Transmission */
mbed_official 340:28d1f895c6fe 2193 #define CEC_ISR_TXUDR ((uint32_t)0x00000400) /*!< CEC Tx-Buffer Underrun */
mbed_official 340:28d1f895c6fe 2194 #define CEC_ISR_TXERR ((uint32_t)0x00000800) /*!< CEC Tx-Error */
mbed_official 340:28d1f895c6fe 2195 #define CEC_ISR_TXACKE ((uint32_t)0x00001000) /*!< CEC Tx Missing Acknowledge */
mbed_official 340:28d1f895c6fe 2196
mbed_official 340:28d1f895c6fe 2197 /******************* Bit definition for CEC_IER register ********************/
mbed_official 340:28d1f895c6fe 2198 #define CEC_IER_RXBRIE ((uint32_t)0x00000001) /*!< CEC Rx-Byte Received IT Enable */
mbed_official 340:28d1f895c6fe 2199 #define CEC_IER_RXENDIE ((uint32_t)0x00000002) /*!< CEC End Of Reception IT Enable */
mbed_official 340:28d1f895c6fe 2200 #define CEC_IER_RXOVRIE ((uint32_t)0x00000004) /*!< CEC Rx-Overrun IT Enable */
mbed_official 340:28d1f895c6fe 2201 #define CEC_IER_BREIE ((uint32_t)0x00000008) /*!< CEC Rx Bit Rising Error IT Enable */
mbed_official 340:28d1f895c6fe 2202 #define CEC_IER_SBPEIE ((uint32_t)0x00000010) /*!< CEC Rx Short Bit period Error IT Enable*/
mbed_official 340:28d1f895c6fe 2203 #define CEC_IER_LBPEIE ((uint32_t)0x00000020) /*!< CEC Rx Long Bit period Error IT Enable */
mbed_official 340:28d1f895c6fe 2204 #define CEC_IER_RXACKEIE ((uint32_t)0x00000040) /*!< CEC Rx Missing Acknowledge IT Enable */
mbed_official 340:28d1f895c6fe 2205 #define CEC_IER_ARBLSTIE ((uint32_t)0x00000080) /*!< CEC Arbitration Lost IT Enable */
mbed_official 340:28d1f895c6fe 2206 #define CEC_IER_TXBRIE ((uint32_t)0x00000100) /*!< CEC Tx Byte Request IT Enable */
mbed_official 340:28d1f895c6fe 2207 #define CEC_IER_TXENDIE ((uint32_t)0x00000200) /*!< CEC End of Transmission IT Enable */
mbed_official 340:28d1f895c6fe 2208 #define CEC_IER_TXUDRIE ((uint32_t)0x00000400) /*!< CEC Tx-Buffer Underrun IT Enable */
mbed_official 340:28d1f895c6fe 2209 #define CEC_IER_TXERRIE ((uint32_t)0x00000800) /*!< CEC Tx-Error IT Enable */
mbed_official 340:28d1f895c6fe 2210 #define CEC_IER_TXACKEIE ((uint32_t)0x00001000) /*!< CEC Tx Missing Acknowledge IT Enable */
mbed_official 340:28d1f895c6fe 2211
mbed_official 340:28d1f895c6fe 2212
mbed_official 340:28d1f895c6fe 2213 /******************************************************************************/
mbed_official 340:28d1f895c6fe 2214 /* */
mbed_official 340:28d1f895c6fe 2215 /* Analog Comparators (COMP) */
mbed_official 340:28d1f895c6fe 2216 /* */
mbed_official 340:28d1f895c6fe 2217 /******************************************************************************/
mbed_official 340:28d1f895c6fe 2218 /*********************** Bit definition for COMP_CSR register ***************/
mbed_official 340:28d1f895c6fe 2219 /* COMP1 bits definition */
mbed_official 340:28d1f895c6fe 2220 #define COMP_CSR_COMP1EN ((uint32_t)0x00000001) /*!< COMP1 enable */
mbed_official 340:28d1f895c6fe 2221 #define COMP_CSR_COMP1SW1 ((uint32_t)0x00000002) /*!< SW1 switch control */
mbed_official 340:28d1f895c6fe 2222 #define COMP_CSR_COMP1MODE ((uint32_t)0x0000000C) /*!< COMP1 power mode */
mbed_official 340:28d1f895c6fe 2223 #define COMP_CSR_COMP1MODE_0 ((uint32_t)0x00000004) /*!< COMP1 power mode bit 0 */
mbed_official 340:28d1f895c6fe 2224 #define COMP_CSR_COMP1MODE_1 ((uint32_t)0x00000008) /*!< COMP1 power mode bit 1 */
mbed_official 340:28d1f895c6fe 2225 #define COMP_CSR_COMP1INSEL ((uint32_t)0x00000070) /*!< COMP1 inverting input select */
mbed_official 340:28d1f895c6fe 2226 #define COMP_CSR_COMP1INSEL_0 ((uint32_t)0x00000010) /*!< COMP1 inverting input select bit 0 */
mbed_official 340:28d1f895c6fe 2227 #define COMP_CSR_COMP1INSEL_1 ((uint32_t)0x00000020) /*!< COMP1 inverting input select bit 1 */
mbed_official 340:28d1f895c6fe 2228 #define COMP_CSR_COMP1INSEL_2 ((uint32_t)0x00000040) /*!< COMP1 inverting input select bit 2 */
mbed_official 340:28d1f895c6fe 2229 #define COMP_CSR_COMP1OUTSEL ((uint32_t)0x00000700) /*!< COMP1 output select */
mbed_official 340:28d1f895c6fe 2230 #define COMP_CSR_COMP1OUTSEL_0 ((uint32_t)0x00000100) /*!< COMP1 output select bit 0 */
mbed_official 340:28d1f895c6fe 2231 #define COMP_CSR_COMP1OUTSEL_1 ((uint32_t)0x00000200) /*!< COMP1 output select bit 1 */
mbed_official 340:28d1f895c6fe 2232 #define COMP_CSR_COMP1OUTSEL_2 ((uint32_t)0x00000400) /*!< COMP1 output select bit 2 */
mbed_official 340:28d1f895c6fe 2233 #define COMP_CSR_COMP1POL ((uint32_t)0x00000800) /*!< COMP1 output polarity */
mbed_official 340:28d1f895c6fe 2234 #define COMP_CSR_COMP1HYST ((uint32_t)0x00003000) /*!< COMP1 hysteresis */
mbed_official 340:28d1f895c6fe 2235 #define COMP_CSR_COMP1HYST_0 ((uint32_t)0x00001000) /*!< COMP1 hysteresis bit 0 */
mbed_official 340:28d1f895c6fe 2236 #define COMP_CSR_COMP1HYST_1 ((uint32_t)0x00002000) /*!< COMP1 hysteresis bit 1 */
mbed_official 340:28d1f895c6fe 2237 #define COMP_CSR_COMP1OUT ((uint32_t)0x00004000) /*!< COMP1 output level */
mbed_official 340:28d1f895c6fe 2238 #define COMP_CSR_COMP1LOCK ((uint32_t)0x00008000) /*!< COMP1 lock */
mbed_official 340:28d1f895c6fe 2239 /* COMP2 bits definition */
mbed_official 340:28d1f895c6fe 2240 #define COMP_CSR_COMP2EN ((uint32_t)0x00010000) /*!< COMP2 enable */
mbed_official 340:28d1f895c6fe 2241 #define COMP_CSR_COMP2MODE ((uint32_t)0x000C0000) /*!< COMP2 power mode */
mbed_official 340:28d1f895c6fe 2242 #define COMP_CSR_COMP2MODE_0 ((uint32_t)0x00040000) /*!< COMP2 power mode bit 0 */
mbed_official 340:28d1f895c6fe 2243 #define COMP_CSR_COMP2MODE_1 ((uint32_t)0x00080000) /*!< COMP2 power mode bit 1 */
mbed_official 340:28d1f895c6fe 2244 #define COMP_CSR_COMP2INSEL ((uint32_t)0x00700000) /*!< COMP2 inverting input select */
mbed_official 340:28d1f895c6fe 2245 #define COMP_CSR_COMP2INSEL_0 ((uint32_t)0x00100000) /*!< COMP2 inverting input select bit 0 */
mbed_official 340:28d1f895c6fe 2246 #define COMP_CSR_COMP2INSEL_1 ((uint32_t)0x00200000) /*!< COMP2 inverting input select bit 1 */
mbed_official 340:28d1f895c6fe 2247 #define COMP_CSR_COMP2INSEL_2 ((uint32_t)0x00400000) /*!< COMP2 inverting input select bit 2 */
mbed_official 340:28d1f895c6fe 2248 #define COMP_CSR_WNDWEN ((uint32_t)0x00800000) /*!< Comparators window mode enable */
mbed_official 340:28d1f895c6fe 2249 #define COMP_CSR_COMP2OUTSEL ((uint32_t)0x07000000) /*!< COMP2 output select */
mbed_official 340:28d1f895c6fe 2250 #define COMP_CSR_COMP2OUTSEL_0 ((uint32_t)0x01000000) /*!< COMP2 output select bit 0 */
mbed_official 340:28d1f895c6fe 2251 #define COMP_CSR_COMP2OUTSEL_1 ((uint32_t)0x02000000) /*!< COMP2 output select bit 1 */
mbed_official 340:28d1f895c6fe 2252 #define COMP_CSR_COMP2OUTSEL_2 ((uint32_t)0x04000000) /*!< COMP2 output select bit 2 */
mbed_official 340:28d1f895c6fe 2253 #define COMP_CSR_COMP2POL ((uint32_t)0x08000000) /*!< COMP2 output polarity */
mbed_official 340:28d1f895c6fe 2254 #define COMP_CSR_COMP2HYST ((uint32_t)0x30000000) /*!< COMP2 hysteresis */
mbed_official 340:28d1f895c6fe 2255 #define COMP_CSR_COMP2HYST_0 ((uint32_t)0x10000000) /*!< COMP2 hysteresis bit 0 */
mbed_official 340:28d1f895c6fe 2256 #define COMP_CSR_COMP2HYST_1 ((uint32_t)0x20000000) /*!< COMP2 hysteresis bit 1 */
mbed_official 340:28d1f895c6fe 2257 #define COMP_CSR_COMP2OUT ((uint32_t)0x40000000) /*!< COMP2 output level */
mbed_official 340:28d1f895c6fe 2258 #define COMP_CSR_COMP2LOCK ((uint32_t)0x80000000) /*!< COMP2 lock */
mbed_official 340:28d1f895c6fe 2259 /* COMPx bits definition */
mbed_official 340:28d1f895c6fe 2260 #define COMP_CSR_COMPxEN ((uint16_t)0x0001) /*!< COMPx enable */
mbed_official 340:28d1f895c6fe 2261 #define COMP_CSR_COMPxMODE ((uint16_t)0x000C) /*!< COMPx power mode */
mbed_official 340:28d1f895c6fe 2262 #define COMP_CSR_COMPxMODE_0 ((uint16_t)0x0004) /*!< COMPx power mode bit 0 */
mbed_official 340:28d1f895c6fe 2263 #define COMP_CSR_COMPxMODE_1 ((uint16_t)0x0008) /*!< COMPx power mode bit 1 */
mbed_official 340:28d1f895c6fe 2264 #define COMP_CSR_COMPxINSEL ((uint16_t)0x0070) /*!< COMPx inverting input select */
mbed_official 340:28d1f895c6fe 2265 #define COMP_CSR_COMPxINSEL_0 ((uint16_t)0x0010) /*!< COMPx inverting input select bit 0 */
mbed_official 340:28d1f895c6fe 2266 #define COMP_CSR_COMPxINSEL_1 ((uint16_t)0x0020) /*!< COMPx inverting input select bit 1 */
mbed_official 340:28d1f895c6fe 2267 #define COMP_CSR_COMPxINSEL_2 ((uint16_t)0x0040) /*!< COMPx inverting input select bit 2 */
mbed_official 340:28d1f895c6fe 2268 #define COMP_CSR_COMPxOUTSEL ((uint16_t)0x0700) /*!< COMPx output select */
mbed_official 340:28d1f895c6fe 2269 #define COMP_CSR_COMPxOUTSEL_0 ((uint16_t)0x0100) /*!< COMPx output select bit 0 */
mbed_official 340:28d1f895c6fe 2270 #define COMP_CSR_COMPxOUTSEL_1 ((uint16_t)0x0200) /*!< COMPx output select bit 1 */
mbed_official 340:28d1f895c6fe 2271 #define COMP_CSR_COMPxOUTSEL_2 ((uint16_t)0x0400) /*!< COMPx output select bit 2 */
mbed_official 340:28d1f895c6fe 2272 #define COMP_CSR_COMPxPOL ((uint16_t)0x0800) /*!< COMPx output polarity */
mbed_official 340:28d1f895c6fe 2273 #define COMP_CSR_COMPxHYST ((uint16_t)0x3000) /*!< COMPx hysteresis */
mbed_official 340:28d1f895c6fe 2274 #define COMP_CSR_COMPxHYST_0 ((uint16_t)0x1000) /*!< COMPx hysteresis bit 0 */
mbed_official 340:28d1f895c6fe 2275 #define COMP_CSR_COMPxHYST_1 ((uint16_t)0x2000) /*!< COMPx hysteresis bit 1 */
mbed_official 340:28d1f895c6fe 2276 #define COMP_CSR_COMPxOUT ((uint16_t)0x4000) /*!< COMPx output level */
mbed_official 340:28d1f895c6fe 2277 #define COMP_CSR_COMPxLOCK ((uint16_t)0x8000) /*!< COMPx lock */
mbed_official 340:28d1f895c6fe 2278
mbed_official 340:28d1f895c6fe 2279 /******************************************************************************/
mbed_official 340:28d1f895c6fe 2280 /* */
mbed_official 340:28d1f895c6fe 2281 /* CRC calculation unit (CRC) */
mbed_official 340:28d1f895c6fe 2282 /* */
mbed_official 340:28d1f895c6fe 2283 /******************************************************************************/
mbed_official 340:28d1f895c6fe 2284 /******************* Bit definition for CRC_DR register *********************/
mbed_official 340:28d1f895c6fe 2285 #define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
mbed_official 340:28d1f895c6fe 2286
mbed_official 340:28d1f895c6fe 2287 /******************* Bit definition for CRC_IDR register ********************/
mbed_official 340:28d1f895c6fe 2288 #define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */
mbed_official 340:28d1f895c6fe 2289
mbed_official 340:28d1f895c6fe 2290 /******************** Bit definition for CRC_CR register ********************/
mbed_official 340:28d1f895c6fe 2291 #define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET the CRC computation unit bit */
mbed_official 340:28d1f895c6fe 2292 #define CRC_CR_POLYSIZE ((uint32_t)0x00000018) /*!< Polynomial size bits */
mbed_official 340:28d1f895c6fe 2293 #define CRC_CR_POLYSIZE_0 ((uint32_t)0x00000008) /*!< Polynomial size bit 0 */
mbed_official 340:28d1f895c6fe 2294 #define CRC_CR_POLYSIZE_1 ((uint32_t)0x00000010) /*!< Polynomial size bit 1 */
mbed_official 340:28d1f895c6fe 2295 #define CRC_CR_REV_IN ((uint32_t)0x00000060) /*!< REV_IN Reverse Input Data bits */
mbed_official 340:28d1f895c6fe 2296 #define CRC_CR_REV_IN_0 ((uint32_t)0x00000020) /*!< REV_IN Bit 0 */
mbed_official 340:28d1f895c6fe 2297 #define CRC_CR_REV_IN_1 ((uint32_t)0x00000040) /*!< REV_IN Bit 1 */
mbed_official 340:28d1f895c6fe 2298 #define CRC_CR_REV_OUT ((uint32_t)0x00000080) /*!< REV_OUT Reverse Output Data bits */
mbed_official 340:28d1f895c6fe 2299
mbed_official 340:28d1f895c6fe 2300 /******************* Bit definition for CRC_INIT register *******************/
mbed_official 340:28d1f895c6fe 2301 #define CRC_INIT_INIT ((uint32_t)0xFFFFFFFF) /*!< Initial CRC value bits */
mbed_official 340:28d1f895c6fe 2302
mbed_official 340:28d1f895c6fe 2303 /******************* Bit definition for CRC_POL register ********************/
mbed_official 340:28d1f895c6fe 2304 #define CRC_POL_POL ((uint32_t)0xFFFFFFFF) /*!< Coefficients of the polynomial */
mbed_official 340:28d1f895c6fe 2305
mbed_official 340:28d1f895c6fe 2306 /******************************************************************************/
mbed_official 340:28d1f895c6fe 2307 /* */
mbed_official 340:28d1f895c6fe 2308 /* CRS Clock Recovery System */
mbed_official 340:28d1f895c6fe 2309 /******************************************************************************/
mbed_official 340:28d1f895c6fe 2310
mbed_official 340:28d1f895c6fe 2311 /******************* Bit definition for CRS_CR register *********************/
mbed_official 340:28d1f895c6fe 2312 #define CRS_CR_SYNCOKIE ((uint32_t)0x00000001) /* SYNC event OK interrupt enable */
mbed_official 340:28d1f895c6fe 2313 #define CRS_CR_SYNCWARNIE ((uint32_t)0x00000002) /* SYNC warning interrupt enable */
mbed_official 340:28d1f895c6fe 2314 #define CRS_CR_ERRIE ((uint32_t)0x00000004) /* SYNC error interrupt enable */
mbed_official 340:28d1f895c6fe 2315 #define CRS_CR_ESYNCIE ((uint32_t)0x00000008) /* Expected SYNC(ESYNCF) interrupt Enable*/
mbed_official 340:28d1f895c6fe 2316 #define CRS_CR_CEN ((uint32_t)0x00000020) /* Frequency error counter enable */
mbed_official 340:28d1f895c6fe 2317 #define CRS_CR_AUTOTRIMEN ((uint32_t)0x00000040) /* Automatic trimming enable */
mbed_official 340:28d1f895c6fe 2318 #define CRS_CR_SWSYNC ((uint32_t)0x00000080) /* A Software SYNC event is generated */
mbed_official 340:28d1f895c6fe 2319 #define CRS_CR_TRIM ((uint32_t)0x00003F00) /* HSI48 oscillator smooth trimming */
mbed_official 340:28d1f895c6fe 2320
mbed_official 340:28d1f895c6fe 2321 /******************* Bit definition for CRS_CFGR register *********************/
mbed_official 340:28d1f895c6fe 2322 #define CRS_CFGR_RELOAD ((uint32_t)0x0000FFFF) /* Counter reload value */
mbed_official 340:28d1f895c6fe 2323 #define CRS_CFGR_FELIM ((uint32_t)0x00FF0000) /* Frequency error limit */
mbed_official 340:28d1f895c6fe 2324
mbed_official 340:28d1f895c6fe 2325 #define CRS_CFGR_SYNCDIV ((uint32_t)0x07000000) /* SYNC divider */
mbed_official 340:28d1f895c6fe 2326 #define CRS_CFGR_SYNCDIV_0 ((uint32_t)0x01000000) /* Bit 0 */
mbed_official 340:28d1f895c6fe 2327 #define CRS_CFGR_SYNCDIV_1 ((uint32_t)0x02000000) /* Bit 1 */
mbed_official 340:28d1f895c6fe 2328 #define CRS_CFGR_SYNCDIV_2 ((uint32_t)0x04000000) /* Bit 2 */
mbed_official 340:28d1f895c6fe 2329
mbed_official 340:28d1f895c6fe 2330 #define CRS_CFGR_SYNCSRC ((uint32_t)0x30000000) /* SYNC signal source selection */
mbed_official 340:28d1f895c6fe 2331 #define CRS_CFGR_SYNCSRC_0 ((uint32_t)0x10000000) /* Bit 0 */
mbed_official 340:28d1f895c6fe 2332 #define CRS_CFGR_SYNCSRC_1 ((uint32_t)0x20000000) /* Bit 1 */
mbed_official 340:28d1f895c6fe 2333
mbed_official 340:28d1f895c6fe 2334 #define CRS_CFGR_SYNCPOL ((uint32_t)0x80000000) /* SYNC polarity selection */
mbed_official 340:28d1f895c6fe 2335
mbed_official 340:28d1f895c6fe 2336 /******************* Bit definition for CRS_ISR register *********************/
mbed_official 340:28d1f895c6fe 2337 #define CRS_ISR_SYNCOKF ((uint32_t)0x00000001) /* SYNC event OK flag */
mbed_official 340:28d1f895c6fe 2338 #define CRS_ISR_SYNCWARNF ((uint32_t)0x00000002) /* SYNC warning */
mbed_official 340:28d1f895c6fe 2339 #define CRS_ISR_ERRF ((uint32_t)0x00000004) /* SYNC error flag */
mbed_official 340:28d1f895c6fe 2340 #define CRS_ISR_ESYNCF ((uint32_t)0x00000008) /* Expected SYNC flag */
mbed_official 340:28d1f895c6fe 2341 #define CRS_ISR_SYNCERR ((uint32_t)0x00000100) /* SYNC error */
mbed_official 340:28d1f895c6fe 2342 #define CRS_ISR_SYNCMISS ((uint32_t)0x00000200) /* SYNC missed */
mbed_official 340:28d1f895c6fe 2343 #define CRS_ISR_TRIMOVF ((uint32_t)0x00000400) /* Trimming overflow or underflow */
mbed_official 340:28d1f895c6fe 2344 #define CRS_ISR_FEDIR ((uint32_t)0x00008000) /* Frequency error direction */
mbed_official 340:28d1f895c6fe 2345 #define CRS_ISR_FECAP ((uint32_t)0xFFFF0000) /* Frequency error capture */
mbed_official 340:28d1f895c6fe 2346
mbed_official 340:28d1f895c6fe 2347 /******************* Bit definition for CRS_ICR register *********************/
mbed_official 340:28d1f895c6fe 2348 #define CRS_ICR_SYNCOKC ((uint32_t)0x00000001) /* SYNC event OK clear flag */
mbed_official 340:28d1f895c6fe 2349 #define CRS_ICR_SYNCWARNC ((uint32_t)0x00000002) /* SYNC warning clear flag */
mbed_official 340:28d1f895c6fe 2350 #define CRS_ICR_ERRC ((uint32_t)0x00000004) /* Error clear flag */
mbed_official 340:28d1f895c6fe 2351 #define CRS_ICR_ESYNCC ((uint32_t)0x00000008) /* Expected SYNC clear flag */
mbed_official 340:28d1f895c6fe 2352
mbed_official 340:28d1f895c6fe 2353 /******************************************************************************/
mbed_official 340:28d1f895c6fe 2354 /* */
mbed_official 340:28d1f895c6fe 2355 /* Digital to Analog Converter (DAC) */
mbed_official 340:28d1f895c6fe 2356 /* */
mbed_official 340:28d1f895c6fe 2357 /******************************************************************************/
mbed_official 340:28d1f895c6fe 2358 /******************** Bit definition for DAC_CR register ********************/
mbed_official 340:28d1f895c6fe 2359 #define DAC_CR_EN1 ((uint32_t)0x00000001) /*!< DAC channel1 enable */
mbed_official 340:28d1f895c6fe 2360 #define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!< DAC channel1 output buffer disable */
mbed_official 340:28d1f895c6fe 2361 #define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!< DAC channel1 Trigger enable */
mbed_official 340:28d1f895c6fe 2362
mbed_official 340:28d1f895c6fe 2363 #define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */
mbed_official 340:28d1f895c6fe 2364 #define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!< Bit 0 */
mbed_official 340:28d1f895c6fe 2365 #define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!< Bit 1 */
mbed_official 340:28d1f895c6fe 2366 #define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!< Bit 2 */
mbed_official 340:28d1f895c6fe 2367
mbed_official 340:28d1f895c6fe 2368 #define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
mbed_official 340:28d1f895c6fe 2369 #define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!< Bit 0 */
mbed_official 340:28d1f895c6fe 2370 #define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!< Bit 1 */
mbed_official 340:28d1f895c6fe 2371
mbed_official 340:28d1f895c6fe 2372 #define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
mbed_official 340:28d1f895c6fe 2373 #define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!< Bit 0 */
mbed_official 340:28d1f895c6fe 2374 #define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!< Bit 1 */
mbed_official 340:28d1f895c6fe 2375 #define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!< Bit 2 */
mbed_official 340:28d1f895c6fe 2376 #define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!< Bit 3 */
mbed_official 340:28d1f895c6fe 2377
mbed_official 340:28d1f895c6fe 2378 #define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!< DAC channel1 DMA enable */
mbed_official 340:28d1f895c6fe 2379 #define DAC_CR_DMAUDRIE1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA Underrun Interrupt enable */
mbed_official 340:28d1f895c6fe 2380
mbed_official 340:28d1f895c6fe 2381 #define DAC_CR_EN2 ((uint32_t)0x00010000) /*!< DAC channel2 enable */
mbed_official 340:28d1f895c6fe 2382 #define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!< DAC channel2 output buffer disable */
mbed_official 340:28d1f895c6fe 2383 #define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!< DAC channel2 Trigger enable */
mbed_official 340:28d1f895c6fe 2384
mbed_official 340:28d1f895c6fe 2385 #define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */
mbed_official 340:28d1f895c6fe 2386 #define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!< Bit 0 */
mbed_official 340:28d1f895c6fe 2387 #define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!< Bit 1 */
mbed_official 340:28d1f895c6fe 2388 #define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!< Bit 2 */
mbed_official 340:28d1f895c6fe 2389
mbed_official 340:28d1f895c6fe 2390 #define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
mbed_official 340:28d1f895c6fe 2391 #define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!< Bit 0 */
mbed_official 340:28d1f895c6fe 2392 #define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!< Bit 1 */
mbed_official 340:28d1f895c6fe 2393
mbed_official 340:28d1f895c6fe 2394 #define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
mbed_official 340:28d1f895c6fe 2395 #define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!< Bit 0 */
mbed_official 340:28d1f895c6fe 2396 #define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!< Bit 1 */
mbed_official 340:28d1f895c6fe 2397 #define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!< Bit 2 */
mbed_official 340:28d1f895c6fe 2398 #define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!< Bit 3 */
mbed_official 340:28d1f895c6fe 2399
mbed_official 340:28d1f895c6fe 2400 #define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!< DAC channel2 DMA enabled */
mbed_official 340:28d1f895c6fe 2401 #define DAC_CR_DMAUDRIE2 ((uint32_t)0x20000000) /*!< DAC channel2 DMA Underrun Interrupt enable */
mbed_official 340:28d1f895c6fe 2402
mbed_official 340:28d1f895c6fe 2403 /***************** Bit definition for DAC_SWTRIGR register ******************/
mbed_official 340:28d1f895c6fe 2404 #define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x00000001) /*!< DAC channel1 software trigger */
mbed_official 340:28d1f895c6fe 2405 #define DAC_SWTRIGR_SWTRIG2 ((uint32_t)0x00000002) /*!< DAC channel2 software trigger */
mbed_official 340:28d1f895c6fe 2406
mbed_official 340:28d1f895c6fe 2407 /***************** Bit definition for DAC_DHR12R1 register ******************/
mbed_official 340:28d1f895c6fe 2408 #define DAC_DHR12R1_DACC1DHR ((uint32_t)0x00000FFF) /*!< DAC channel1 12-bit Right aligned data */
mbed_official 340:28d1f895c6fe 2409
mbed_official 340:28d1f895c6fe 2410 /***************** Bit definition for DAC_DHR12L1 register ******************/
mbed_official 340:28d1f895c6fe 2411 #define DAC_DHR12L1_DACC1DHR ((uint32_t)0x0000FFF0) /*!< DAC channel1 12-bit Left aligned data */
mbed_official 340:28d1f895c6fe 2412
mbed_official 340:28d1f895c6fe 2413 /****************** Bit definition for DAC_DHR8R1 register ******************/
mbed_official 340:28d1f895c6fe 2414 #define DAC_DHR8R1_DACC1DHR ((uint32_t)0x000000FF) /*!< DAC channel1 8-bit Right aligned data */
mbed_official 340:28d1f895c6fe 2415
mbed_official 340:28d1f895c6fe 2416 /***************** Bit definition for DAC_DHR12R2 register ******************/
mbed_official 340:28d1f895c6fe 2417 #define DAC_DHR12R2_DACC2DHR ((uint32_t)0x00000FFF) /*!< DAC channel2 12-bit Right aligned data */
mbed_official 340:28d1f895c6fe 2418
mbed_official 340:28d1f895c6fe 2419 /***************** Bit definition for DAC_DHR12L2 register ******************/
mbed_official 340:28d1f895c6fe 2420 #define DAC_DHR12L2_DACC2DHR ((uint32_t)0x0000FFF0) /*!< DAC channel2 12-bit Left aligned data */
mbed_official 340:28d1f895c6fe 2421
mbed_official 340:28d1f895c6fe 2422 /****************** Bit definition for DAC_DHR8R2 register ******************/
mbed_official 340:28d1f895c6fe 2423 #define DAC_DHR8R2_DACC2DHR ((uint32_t)0x000000FF) /*!< DAC channel2 8-bit Right aligned data */
mbed_official 340:28d1f895c6fe 2424
mbed_official 340:28d1f895c6fe 2425 /***************** Bit definition for DAC_DHR12RD register ******************/
mbed_official 340:28d1f895c6fe 2426 #define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!< DAC channel1 12-bit Right aligned data */
mbed_official 340:28d1f895c6fe 2427 #define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!< DAC channel2 12-bit Right aligned data */
mbed_official 340:28d1f895c6fe 2428
mbed_official 340:28d1f895c6fe 2429 /***************** Bit definition for DAC_DHR12LD register ******************/
mbed_official 340:28d1f895c6fe 2430 #define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!< DAC channel1 12-bit Left aligned data */
mbed_official 340:28d1f895c6fe 2431 #define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!< DAC channel2 12-bit Left aligned data */
mbed_official 340:28d1f895c6fe 2432
mbed_official 340:28d1f895c6fe 2433 /****************** Bit definition for DAC_DHR8RD register ******************/
mbed_official 340:28d1f895c6fe 2434 #define DAC_DHR8RD_DACC1DHR ((uint32_t)0x000000FF) /*!< DAC channel1 8-bit Right aligned data */
mbed_official 340:28d1f895c6fe 2435 #define DAC_DHR8RD_DACC2DHR ((uint32_t)0x0000FF00) /*!< DAC channel2 8-bit Right aligned data */
mbed_official 340:28d1f895c6fe 2436
mbed_official 340:28d1f895c6fe 2437 /******************* Bit definition for DAC_DOR1 register *******************/
mbed_official 340:28d1f895c6fe 2438 #define DAC_DOR1_DACC1DOR ((uint32_t)0x00000FFF) /*!< DAC channel1 data output */
mbed_official 340:28d1f895c6fe 2439
mbed_official 340:28d1f895c6fe 2440 /******************* Bit definition for DAC_DOR2 register *******************/
mbed_official 340:28d1f895c6fe 2441 #define DAC_DOR2_DACC2DOR ((uint32_t)0x00000FFF) /*!< DAC channel2 data output */
mbed_official 340:28d1f895c6fe 2442
mbed_official 340:28d1f895c6fe 2443 /******************** Bit definition for DAC_SR register ********************/
mbed_official 340:28d1f895c6fe 2444 #define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA underrun flag */
mbed_official 340:28d1f895c6fe 2445 #define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!< DAC channel2 DMA underrun flag */
mbed_official 340:28d1f895c6fe 2446
mbed_official 340:28d1f895c6fe 2447 /******************************************************************************/
mbed_official 340:28d1f895c6fe 2448 /* */
mbed_official 340:28d1f895c6fe 2449 /* Debug MCU (DBGMCU) */
mbed_official 340:28d1f895c6fe 2450 /* */
mbed_official 340:28d1f895c6fe 2451 /******************************************************************************/
mbed_official 340:28d1f895c6fe 2452
mbed_official 340:28d1f895c6fe 2453 /**************** Bit definition for DBGMCU_IDCODE register *****************/
mbed_official 340:28d1f895c6fe 2454 #define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) /*!< Device Identifier */
mbed_official 340:28d1f895c6fe 2455
mbed_official 340:28d1f895c6fe 2456 #define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) /*!< REV_ID[15:0] bits (Revision Identifier) */
mbed_official 340:28d1f895c6fe 2457 #define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) /*!< Bit 0 */
mbed_official 340:28d1f895c6fe 2458 #define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) /*!< Bit 1 */
mbed_official 340:28d1f895c6fe 2459 #define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) /*!< Bit 2 */
mbed_official 340:28d1f895c6fe 2460 #define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) /*!< Bit 3 */
mbed_official 340:28d1f895c6fe 2461 #define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) /*!< Bit 4 */
mbed_official 340:28d1f895c6fe 2462 #define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) /*!< Bit 5 */
mbed_official 340:28d1f895c6fe 2463 #define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) /*!< Bit 6 */
mbed_official 340:28d1f895c6fe 2464 #define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) /*!< Bit 7 */
mbed_official 340:28d1f895c6fe 2465 #define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) /*!< Bit 8 */
mbed_official 340:28d1f895c6fe 2466 #define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) /*!< Bit 9 */
mbed_official 340:28d1f895c6fe 2467 #define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) /*!< Bit 10 */
mbed_official 340:28d1f895c6fe 2468 #define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) /*!< Bit 11 */
mbed_official 340:28d1f895c6fe 2469 #define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) /*!< Bit 12 */
mbed_official 340:28d1f895c6fe 2470 #define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) /*!< Bit 13 */
mbed_official 340:28d1f895c6fe 2471 #define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) /*!< Bit 14 */
mbed_official 340:28d1f895c6fe 2472 #define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) /*!< Bit 15 */
mbed_official 340:28d1f895c6fe 2473
mbed_official 340:28d1f895c6fe 2474 /****************** Bit definition for DBGMCU_CR register *******************/
mbed_official 340:28d1f895c6fe 2475 #define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) /*!< Debug Stop Mode */
mbed_official 340:28d1f895c6fe 2476 #define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) /*!< Debug Standby mode */
mbed_official 340:28d1f895c6fe 2477
mbed_official 340:28d1f895c6fe 2478 /****************** Bit definition for DBGMCU_APB1_FZ register **************/
mbed_official 340:28d1f895c6fe 2479 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001) /*!< TIM2 counter stopped when core is halted */
mbed_official 340:28d1f895c6fe 2480 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002) /*!< TIM3 counter stopped when core is halted */
mbed_official 340:28d1f895c6fe 2481 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010) /*!< TIM6 counter stopped when core is halted */
mbed_official 340:28d1f895c6fe 2482 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020) /*!< TIM7 counter stopped when core is halted */
mbed_official 340:28d1f895c6fe 2483 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP ((uint32_t)0x00000100) /*!< TIM14 counter stopped when core is halted */
mbed_official 340:28d1f895c6fe 2484 #define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400) /*!< RTC Calendar frozen when core is halted */
mbed_official 340:28d1f895c6fe 2485 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800) /*!< Debug Window Watchdog stopped when Core is halted */
mbed_official 340:28d1f895c6fe 2486 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000) /*!< Debug Independent Watchdog stopped when Core is halted */
mbed_official 340:28d1f895c6fe 2487 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000) /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
mbed_official 340:28d1f895c6fe 2488 #define DBGMCU_APB1_FZ_DBG_CAN_STOP ((uint32_t)0x02000000) /*!< CAN debug stopped when Core is halted */
mbed_official 340:28d1f895c6fe 2489
mbed_official 340:28d1f895c6fe 2490 /****************** Bit definition for DBGMCU_APB2_FZ register **************/
mbed_official 340:28d1f895c6fe 2491 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP ((uint32_t)0x00000800) /*!< TIM1 counter stopped when core is halted */
mbed_official 340:28d1f895c6fe 2492 #define DBGMCU_APB2_FZ_DBG_TIM15_STOP ((uint32_t)0x00010000) /*!< TIM15 counter stopped when core is halted */
mbed_official 340:28d1f895c6fe 2493 #define DBGMCU_APB2_FZ_DBG_TIM16_STOP ((uint32_t)0x00020000) /*!< TIM16 counter stopped when core is halted */
mbed_official 340:28d1f895c6fe 2494 #define DBGMCU_APB2_FZ_DBG_TIM17_STOP ((uint32_t)0x00040000) /*!< TIM17 counter stopped when core is halted */
mbed_official 340:28d1f895c6fe 2495
mbed_official 340:28d1f895c6fe 2496 /******************************************************************************/
mbed_official 340:28d1f895c6fe 2497 /* */
mbed_official 340:28d1f895c6fe 2498 /* DMA Controller (DMA) */
mbed_official 340:28d1f895c6fe 2499 /* */
mbed_official 340:28d1f895c6fe 2500 /******************************************************************************/
mbed_official 340:28d1f895c6fe 2501 /******************* Bit definition for DMA_ISR register ********************/
mbed_official 340:28d1f895c6fe 2502 #define DMA_ISR_GIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */
mbed_official 340:28d1f895c6fe 2503 #define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */
mbed_official 340:28d1f895c6fe 2504 #define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */
mbed_official 340:28d1f895c6fe 2505 #define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */
mbed_official 340:28d1f895c6fe 2506 #define DMA_ISR_GIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */
mbed_official 340:28d1f895c6fe 2507 #define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */
mbed_official 340:28d1f895c6fe 2508 #define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */
mbed_official 340:28d1f895c6fe 2509 #define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */
mbed_official 340:28d1f895c6fe 2510 #define DMA_ISR_GIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */
mbed_official 340:28d1f895c6fe 2511 #define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */
mbed_official 340:28d1f895c6fe 2512 #define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */
mbed_official 340:28d1f895c6fe 2513 #define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */
mbed_official 340:28d1f895c6fe 2514 #define DMA_ISR_GIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */
mbed_official 340:28d1f895c6fe 2515 #define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */
mbed_official 340:28d1f895c6fe 2516 #define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */
mbed_official 340:28d1f895c6fe 2517 #define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */
mbed_official 340:28d1f895c6fe 2518 #define DMA_ISR_GIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */
mbed_official 340:28d1f895c6fe 2519 #define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */
mbed_official 340:28d1f895c6fe 2520 #define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */
mbed_official 340:28d1f895c6fe 2521 #define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */
mbed_official 340:28d1f895c6fe 2522 #define DMA_ISR_GIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt flag */
mbed_official 340:28d1f895c6fe 2523 #define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete flag */
mbed_official 340:28d1f895c6fe 2524 #define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer flag */
mbed_official 340:28d1f895c6fe 2525 #define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error flag */
mbed_official 340:28d1f895c6fe 2526 #define DMA_ISR_GIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt flag */
mbed_official 340:28d1f895c6fe 2527 #define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete flag */
mbed_official 340:28d1f895c6fe 2528 #define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer flag */
mbed_official 340:28d1f895c6fe 2529 #define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error flag */
mbed_official 340:28d1f895c6fe 2530
mbed_official 340:28d1f895c6fe 2531 /******************* Bit definition for DMA_IFCR register *******************/
mbed_official 340:28d1f895c6fe 2532 #define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clear */
mbed_official 340:28d1f895c6fe 2533 #define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */
mbed_official 340:28d1f895c6fe 2534 #define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */
mbed_official 340:28d1f895c6fe 2535 #define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */
mbed_official 340:28d1f895c6fe 2536 #define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */
mbed_official 340:28d1f895c6fe 2537 #define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */
mbed_official 340:28d1f895c6fe 2538 #define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */
mbed_official 340:28d1f895c6fe 2539 #define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */
mbed_official 340:28d1f895c6fe 2540 #define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */
mbed_official 340:28d1f895c6fe 2541 #define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */
mbed_official 340:28d1f895c6fe 2542 #define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */
mbed_official 340:28d1f895c6fe 2543 #define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */
mbed_official 340:28d1f895c6fe 2544 #define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */
mbed_official 340:28d1f895c6fe 2545 #define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */
mbed_official 340:28d1f895c6fe 2546 #define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */
mbed_official 340:28d1f895c6fe 2547 #define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */
mbed_official 340:28d1f895c6fe 2548 #define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */
mbed_official 340:28d1f895c6fe 2549 #define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */
mbed_official 340:28d1f895c6fe 2550 #define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */
mbed_official 340:28d1f895c6fe 2551 #define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */
mbed_official 340:28d1f895c6fe 2552 #define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt clear */
mbed_official 340:28d1f895c6fe 2553 #define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete clear */
mbed_official 340:28d1f895c6fe 2554 #define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer clear */
mbed_official 340:28d1f895c6fe 2555 #define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error clear */
mbed_official 340:28d1f895c6fe 2556 #define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt clear */
mbed_official 340:28d1f895c6fe 2557 #define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete clear */
mbed_official 340:28d1f895c6fe 2558 #define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer clear */
mbed_official 340:28d1f895c6fe 2559 #define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error clear */
mbed_official 340:28d1f895c6fe 2560
mbed_official 340:28d1f895c6fe 2561 /******************* Bit definition for DMA_CCR register ********************/
mbed_official 340:28d1f895c6fe 2562 #define DMA_CCR_EN ((uint32_t)0x00000001) /*!< Channel enable */
mbed_official 340:28d1f895c6fe 2563 #define DMA_CCR_TCIE ((uint32_t)0x00000002) /*!< Transfer complete interrupt enable */
mbed_official 340:28d1f895c6fe 2564 #define DMA_CCR_HTIE ((uint32_t)0x00000004) /*!< Half Transfer interrupt enable */
mbed_official 340:28d1f895c6fe 2565 #define DMA_CCR_TEIE ((uint32_t)0x00000008) /*!< Transfer error interrupt enable */
mbed_official 340:28d1f895c6fe 2566 #define DMA_CCR_DIR ((uint32_t)0x00000010) /*!< Data transfer direction */
mbed_official 340:28d1f895c6fe 2567 #define DMA_CCR_CIRC ((uint32_t)0x00000020) /*!< Circular mode */
mbed_official 340:28d1f895c6fe 2568 #define DMA_CCR_PINC ((uint32_t)0x00000040) /*!< Peripheral increment mode */
mbed_official 340:28d1f895c6fe 2569 #define DMA_CCR_MINC ((uint32_t)0x00000080) /*!< Memory increment mode */
mbed_official 340:28d1f895c6fe 2570
mbed_official 340:28d1f895c6fe 2571 #define DMA_CCR_PSIZE ((uint32_t)0x00000300) /*!< PSIZE[1:0] bits (Peripheral size) */
mbed_official 340:28d1f895c6fe 2572 #define DMA_CCR_PSIZE_0 ((uint32_t)0x00000100) /*!< Bit 0 */
mbed_official 340:28d1f895c6fe 2573 #define DMA_CCR_PSIZE_1 ((uint32_t)0x00000200) /*!< Bit 1 */
mbed_official 340:28d1f895c6fe 2574
mbed_official 340:28d1f895c6fe 2575 #define DMA_CCR_MSIZE ((uint32_t)0x00000C00) /*!< MSIZE[1:0] bits (Memory size) */
mbed_official 340:28d1f895c6fe 2576 #define DMA_CCR_MSIZE_0 ((uint32_t)0x00000400) /*!< Bit 0 */
mbed_official 340:28d1f895c6fe 2577 #define DMA_CCR_MSIZE_1 ((uint32_t)0x00000800) /*!< Bit 1 */
mbed_official 340:28d1f895c6fe 2578
mbed_official 340:28d1f895c6fe 2579 #define DMA_CCR_PL ((uint32_t)0x00003000) /*!< PL[1:0] bits(Channel Priority level)*/
mbed_official 340:28d1f895c6fe 2580 #define DMA_CCR_PL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
mbed_official 340:28d1f895c6fe 2581 #define DMA_CCR_PL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
mbed_official 340:28d1f895c6fe 2582
mbed_official 340:28d1f895c6fe 2583 #define DMA_CCR_MEM2MEM ((uint32_t)0x00004000) /*!< Memory to memory mode */
mbed_official 340:28d1f895c6fe 2584
mbed_official 340:28d1f895c6fe 2585 /****************** Bit definition for DMA_CNDTR register *******************/
mbed_official 340:28d1f895c6fe 2586 #define DMA_CNDTR_NDT ((uint32_t)0x0000FFFF) /*!< Number of data to Transfer */
mbed_official 340:28d1f895c6fe 2587
mbed_official 340:28d1f895c6fe 2588 /****************** Bit definition for DMA_CPAR register ********************/
mbed_official 340:28d1f895c6fe 2589 #define DMA_CPAR_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
mbed_official 340:28d1f895c6fe 2590
mbed_official 340:28d1f895c6fe 2591 /****************** Bit definition for DMA_CMAR register ********************/
mbed_official 340:28d1f895c6fe 2592 #define DMA_CMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
mbed_official 340:28d1f895c6fe 2593
mbed_official 441:d2c15dda23c1 2594 /****************** Bit definition for DMA1_CSELR register ********************/
mbed_official 441:d2c15dda23c1 2595 #define DMA1_CSELR_DEFAULT ((uint32_t)0x00000000) /*!< Default remap position for DMA1 */
mbed_official 441:d2c15dda23c1 2596 #define DMA1_CSELR_CH1_ADC ((uint32_t)0x00000001) /*!< Remap ADC on DMA1 Channel 1*/
mbed_official 441:d2c15dda23c1 2597 #define DMA1_CSELR_CH1_TIM17_CH1 ((uint32_t)0x00000007) /*!< Remap TIM17 channel 1 on DMA1 channel 1 */
mbed_official 441:d2c15dda23c1 2598 #define DMA1_CSELR_CH1_TIM17_UP ((uint32_t)0x00000007) /*!< Remap TIM17 up on DMA1 channel 1 */
mbed_official 441:d2c15dda23c1 2599 #define DMA1_CSELR_CH1_USART1_RX ((uint32_t)0x00000008) /*!< Remap USART1 Rx on DMA1 channel 1 */
mbed_official 441:d2c15dda23c1 2600 #define DMA1_CSELR_CH1_USART2_RX ((uint32_t)0x00000009) /*!< Remap USART2 Rx on DMA1 channel 1 */
mbed_official 441:d2c15dda23c1 2601 #define DMA1_CSELR_CH1_USART3_RX ((uint32_t)0x0000000A) /*!< Remap USART3 Rx on DMA1 channel 1 */
mbed_official 441:d2c15dda23c1 2602 #define DMA1_CSELR_CH1_USART4_RX ((uint32_t)0x0000000B) /*!< Remap USART4 Rx on DMA1 channel 1 */
mbed_official 441:d2c15dda23c1 2603 #define DMA1_CSELR_CH1_USART5_RX ((uint32_t)0x0000000C) /*!< Remap USART5 Rx on DMA1 channel 1 */
mbed_official 441:d2c15dda23c1 2604 #define DMA1_CSELR_CH1_USART6_RX ((uint32_t)0x0000000D) /*!< Remap USART6 Rx on DMA1 channel 1 */
mbed_official 441:d2c15dda23c1 2605 #define DMA1_CSELR_CH1_USART7_RX ((uint32_t)0x0000000E) /*!< Remap USART7 Rx on DMA1 channel 1 */
mbed_official 441:d2c15dda23c1 2606 #define DMA1_CSELR_CH1_USART8_RX ((uint32_t)0x0000000F) /*!< Remap USART8 Rx on DMA1 channel 1 */
mbed_official 441:d2c15dda23c1 2607 #define DMA1_CSELR_CH2_ADC ((uint32_t)0x00000010) /*!< Remap ADC on DMA1 channel 2 */
mbed_official 441:d2c15dda23c1 2608 #define DMA1_CSELR_CH2_I2C1_TX ((uint32_t)0x00000020) /*!< Remap I2C1 Tx on DMA1 channel 2 */
mbed_official 441:d2c15dda23c1 2609 #define DMA1_CSELR_CH2_SPI1_RX ((uint32_t)0x00000030) /*!< Remap SPI1 Rx on DMA1 channel 2 */
mbed_official 441:d2c15dda23c1 2610 #define DMA1_CSELR_CH2_TIM1_CH1 ((uint32_t)0x00000040) /*!< Remap TIM1 channel 1 on DMA1 channel 2 */
mbed_official 441:d2c15dda23c1 2611 #define DMA1_CSELR_CH2_TIM17_CH1 ((uint32_t)0x00000070) /*!< Remap TIM17 channel 1 on DMA1 channel 2 */
mbed_official 441:d2c15dda23c1 2612 #define DMA1_CSELR_CH2_TIM17_UP ((uint32_t)0x00000070) /*!< Remap TIM17 up on DMA1 channel 2 */
mbed_official 441:d2c15dda23c1 2613 #define DMA1_CSELR_CH2_USART1_TX ((uint32_t)0x00000080) /*!< Remap USART1 Tx on DMA1 channel 2 */
mbed_official 441:d2c15dda23c1 2614 #define DMA1_CSELR_CH2_USART2_TX ((uint32_t)0x00000090) /*!< Remap USART2 Tx on DMA1 channel 2 */
mbed_official 441:d2c15dda23c1 2615 #define DMA1_CSELR_CH2_USART3_TX ((uint32_t)0x000000A0) /*!< Remap USART3 Tx on DMA1 channel 2 */
mbed_official 441:d2c15dda23c1 2616 #define DMA1_CSELR_CH2_USART4_TX ((uint32_t)0x000000B0) /*!< Remap USART4 Tx on DMA1 channel 2 */
mbed_official 441:d2c15dda23c1 2617 #define DMA1_CSELR_CH2_USART5_TX ((uint32_t)0x000000C0) /*!< Remap USART5 Tx on DMA1 channel 2 */
mbed_official 441:d2c15dda23c1 2618 #define DMA1_CSELR_CH2_USART6_TX ((uint32_t)0x000000D0) /*!< Remap USART6 Tx on DMA1 channel 2 */
mbed_official 441:d2c15dda23c1 2619 #define DMA1_CSELR_CH2_USART7_TX ((uint32_t)0x000000E0) /*!< Remap USART7 Tx on DMA1 channel 2 */
mbed_official 441:d2c15dda23c1 2620 #define DMA1_CSELR_CH2_USART8_TX ((uint32_t)0x000000F0) /*!< Remap USART8 Tx on DMA1 channel 2 */
mbed_official 441:d2c15dda23c1 2621 #define DMA1_CSELR_CH3_TIM6_UP ((uint32_t)0x00000100) /*!< Remap TIM6 up on DMA1 channel 3 */
mbed_official 441:d2c15dda23c1 2622 #define DMA1_CSELR_CH3_DAC_CH1 ((uint32_t)0x00000100) /*!< Remap DAC Channel 1on DMA1 channel 3 */
mbed_official 441:d2c15dda23c1 2623 #define DMA1_CSELR_CH3_I2C1_RX ((uint32_t)0x00000200) /*!< Remap I2C1 Rx on DMA1 channel 3 */
mbed_official 441:d2c15dda23c1 2624 #define DMA1_CSELR_CH3_SPI1_TX ((uint32_t)0x00000300) /*!< Remap SPI1 Tx on DMA1 channel 3 */
mbed_official 441:d2c15dda23c1 2625 #define DMA1_CSELR_CH3_TIM1_CH2 ((uint32_t)0x00000400) /*!< Remap TIM1 channel 2 on DMA1 channel 3 */
mbed_official 441:d2c15dda23c1 2626 #define DMA1_CSELR_CH3_TIM2_CH2 ((uint32_t)0x00000500) /*!< Remap TIM2 channel 2 on DMA1 channel 3 */
mbed_official 441:d2c15dda23c1 2627 #define DMA1_CSELR_CH3_TIM16_CH1 ((uint32_t)0x00000700) /*!< Remap TIM16 channel 1 on DMA1 channel 3 */
mbed_official 441:d2c15dda23c1 2628 #define DMA1_CSELR_CH3_TIM16_UP ((uint32_t)0x00000700) /*!< Remap TIM16 up on DMA1 channel 3 */
mbed_official 441:d2c15dda23c1 2629 #define DMA1_CSELR_CH3_USART1_RX ((uint32_t)0x00000800) /*!< Remap USART1 Rx on DMA1 channel 3 */
mbed_official 441:d2c15dda23c1 2630 #define DMA1_CSELR_CH3_USART2_RX ((uint32_t)0x00000900) /*!< Remap USART2 Rx on DMA1 channel 3 */
mbed_official 441:d2c15dda23c1 2631 #define DMA1_CSELR_CH3_USART3_RX ((uint32_t)0x00000A00) /*!< Remap USART3 Rx on DMA1 channel 3 */
mbed_official 441:d2c15dda23c1 2632 #define DMA1_CSELR_CH3_USART4_RX ((uint32_t)0x00000B00) /*!< Remap USART4 Rx on DMA1 channel 3 */
mbed_official 441:d2c15dda23c1 2633 #define DMA1_CSELR_CH3_USART5_RX ((uint32_t)0x00000C00) /*!< Remap USART5 Rx on DMA1 channel 3 */
mbed_official 441:d2c15dda23c1 2634 #define DMA1_CSELR_CH3_USART6_RX ((uint32_t)0x00000D00) /*!< Remap USART6 Rx on DMA1 channel 3 */
mbed_official 441:d2c15dda23c1 2635 #define DMA1_CSELR_CH3_USART7_RX ((uint32_t)0x00000E00) /*!< Remap USART7 Rx on DMA1 channel 3 */
mbed_official 441:d2c15dda23c1 2636 #define DMA1_CSELR_CH3_USART8_RX ((uint32_t)0x00000F00) /*!< Remap USART8 Rx on DMA1 channel 3 */
mbed_official 441:d2c15dda23c1 2637 #define DMA1_CSELR_CH4_TIM7_UP ((uint32_t)0x00001000) /*!< Remap TIM7 up on DMA1 channel 4 */
mbed_official 441:d2c15dda23c1 2638 #define DMA1_CSELR_CH4_DAC_CH2 ((uint32_t)0x00001000) /*!< Remap DAC Channel 2 on DMA1 channel 4 */
mbed_official 441:d2c15dda23c1 2639 #define DMA1_CSELR_CH4_I2C2_TX ((uint32_t)0x00002000) /*!< Remap I2C2 Tx on DMA1 channel 4 */
mbed_official 441:d2c15dda23c1 2640 #define DMA1_CSELR_CH4_SPI2_RX ((uint32_t)0x00003000) /*!< Remap SPI2 Rx on DMA1 channel 4 */
mbed_official 441:d2c15dda23c1 2641 #define DMA1_CSELR_CH4_TIM2_CH4 ((uint32_t)0x00005000) /*!< Remap TIM2 channel 4 on DMA1 channel 4 */
mbed_official 441:d2c15dda23c1 2642 #define DMA1_CSELR_CH4_TIM3_CH1 ((uint32_t)0x00006000) /*!< Remap TIM3 channel 1 on DMA1 channel 4 */
mbed_official 441:d2c15dda23c1 2643 #define DMA1_CSELR_CH4_TIM3_TRIG ((uint32_t)0x00006000) /*!< Remap TIM3 Trig on DMA1 channel 4 */
mbed_official 441:d2c15dda23c1 2644 #define DMA1_CSELR_CH4_TIM16_CH1 ((uint32_t)0x00007000) /*!< Remap TIM16 channel 1 on DMA1 channel 4 */
mbed_official 441:d2c15dda23c1 2645 #define DMA1_CSELR_CH4_TIM16_UP ((uint32_t)0x00007000) /*!< Remap TIM16 up on DMA1 channel 4 */
mbed_official 441:d2c15dda23c1 2646 #define DMA1_CSELR_CH4_USART1_TX ((uint32_t)0x00008000) /*!< Remap USART1 Tx on DMA1 channel 4 */
mbed_official 441:d2c15dda23c1 2647 #define DMA1_CSELR_CH4_USART2_TX ((uint32_t)0x00009000) /*!< Remap USART2 Tx on DMA1 channel 4 */
mbed_official 441:d2c15dda23c1 2648 #define DMA1_CSELR_CH4_USART3_TX ((uint32_t)0x0000A000) /*!< Remap USART3 Tx on DMA1 channel 4 */
mbed_official 441:d2c15dda23c1 2649 #define DMA1_CSELR_CH4_USART4_TX ((uint32_t)0x0000B000) /*!< Remap USART4 Tx on DMA1 channel 4 */
mbed_official 441:d2c15dda23c1 2650 #define DMA1_CSELR_CH4_USART5_TX ((uint32_t)0x0000C000) /*!< Remap USART5 Tx on DMA1 channel 4 */
mbed_official 441:d2c15dda23c1 2651 #define DMA1_CSELR_CH4_USART6_TX ((uint32_t)0x0000D000) /*!< Remap USART6 Tx on DMA1 channel 4 */
mbed_official 441:d2c15dda23c1 2652 #define DMA1_CSELR_CH4_USART7_TX ((uint32_t)0x0000E000) /*!< Remap USART7 Tx on DMA1 channel 4 */
mbed_official 441:d2c15dda23c1 2653 #define DMA1_CSELR_CH4_USART8_TX ((uint32_t)0x0000F000) /*!< Remap USART8 Tx on DMA1 channel 4 */
mbed_official 441:d2c15dda23c1 2654 #define DMA1_CSELR_CH5_I2C2_RX ((uint32_t)0x00020000) /*!< Remap I2C2 Rx on DMA1 channel 5 */
mbed_official 441:d2c15dda23c1 2655 #define DMA1_CSELR_CH5_SPI2_TX ((uint32_t)0x00030000) /*!< Remap SPI1 Tx on DMA1 channel 5 */
mbed_official 441:d2c15dda23c1 2656 #define DMA1_CSELR_CH5_TIM1_CH3 ((uint32_t)0x00040000) /*!< Remap TIM1 channel 3 on DMA1 channel 5 */
mbed_official 441:d2c15dda23c1 2657 #define DMA1_CSELR_CH5_USART1_RX ((uint32_t)0x00080000) /*!< Remap USART1 Rx on DMA1 channel 5 */
mbed_official 441:d2c15dda23c1 2658 #define DMA1_CSELR_CH5_USART2_RX ((uint32_t)0x00090000) /*!< Remap USART2 Rx on DMA1 channel 5 */
mbed_official 441:d2c15dda23c1 2659 #define DMA1_CSELR_CH5_USART3_RX ((uint32_t)0x000A0000) /*!< Remap USART3 Rx on DMA1 channel 5 */
mbed_official 441:d2c15dda23c1 2660 #define DMA1_CSELR_CH5_USART4_RX ((uint32_t)0x000B0000) /*!< Remap USART4 Rx on DMA1 channel 5 */
mbed_official 441:d2c15dda23c1 2661 #define DMA1_CSELR_CH5_USART5_RX ((uint32_t)0x000C0000) /*!< Remap USART5 Rx on DMA1 channel 5 */
mbed_official 441:d2c15dda23c1 2662 #define DMA1_CSELR_CH5_USART6_RX ((uint32_t)0x000D0000) /*!< Remap USART6 Rx on DMA1 channel 5 */
mbed_official 441:d2c15dda23c1 2663 #define DMA1_CSELR_CH5_USART7_RX ((uint32_t)0x000E0000) /*!< Remap USART7 Rx on DMA1 channel 5 */
mbed_official 441:d2c15dda23c1 2664 #define DMA1_CSELR_CH5_USART8_RX ((uint32_t)0x000F0000) /*!< Remap USART8 Rx on DMA1 channel 5 */
mbed_official 441:d2c15dda23c1 2665 #define DMA1_CSELR_CH6_I2C1_TX ((uint32_t)0x00200000) /*!< Remap I2C1 Tx on DMA1 channel 6 */
mbed_official 441:d2c15dda23c1 2666 #define DMA1_CSELR_CH6_SPI2_RX ((uint32_t)0x00300000) /*!< Remap SPI2 Rx on DMA1 channel 6 */
mbed_official 441:d2c15dda23c1 2667 #define DMA1_CSELR_CH6_TIM1_CH1 ((uint32_t)0x00400000) /*!< Remap TIM1 channel 1 on DMA1 channel 6 */
mbed_official 441:d2c15dda23c1 2668 #define DMA1_CSELR_CH6_TIM1_CH2 ((uint32_t)0x00400000) /*!< Remap TIM1 channel 2 on DMA1 channel 6 */
mbed_official 441:d2c15dda23c1 2669 #define DMA1_CSELR_CH6_TIM1_CH3 ((uint32_t)0x00400000) /*!< Remap TIM1 channel 3 on DMA1 channel 6 */
mbed_official 441:d2c15dda23c1 2670 #define DMA1_CSELR_CH6_TIM3_CH1 ((uint32_t)0x00600000) /*!< Remap TIM3 channel 1 on DMA1 channel 6 */
mbed_official 441:d2c15dda23c1 2671 #define DMA1_CSELR_CH6_TIM3_TRIG ((uint32_t)0x00600000) /*!< Remap TIM3 Trig on DMA1 channel 6 */
mbed_official 441:d2c15dda23c1 2672 #define DMA1_CSELR_CH6_TIM16_CH1 ((uint32_t)0x00700000) /*!< Remap TIM16 channel 1 on DMA1 channel 6 */
mbed_official 441:d2c15dda23c1 2673 #define DMA1_CSELR_CH6_TIM16_UP ((uint32_t)0x00700000) /*!< Remap TIM16 up on DMA1 channel 6 */
mbed_official 441:d2c15dda23c1 2674 #define DMA1_CSELR_CH6_USART1_RX ((uint32_t)0x00800000) /*!< Remap USART1 Rx on DMA1 channel 6 */
mbed_official 441:d2c15dda23c1 2675 #define DMA1_CSELR_CH6_USART2_RX ((uint32_t)0x00900000) /*!< Remap USART2 Rx on DMA1 channel 6 */
mbed_official 441:d2c15dda23c1 2676 #define DMA1_CSELR_CH6_USART3_RX ((uint32_t)0x00A00000) /*!< Remap USART3 Rx on DMA1 channel 6 */
mbed_official 441:d2c15dda23c1 2677 #define DMA1_CSELR_CH6_USART4_RX ((uint32_t)0x00B00000) /*!< Remap USART4 Rx on DMA1 channel 6 */
mbed_official 441:d2c15dda23c1 2678 #define DMA1_CSELR_CH6_USART5_RX ((uint32_t)0x00C00000) /*!< Remap USART5 Rx on DMA1 channel 6 */
mbed_official 441:d2c15dda23c1 2679 #define DMA1_CSELR_CH6_USART6_RX ((uint32_t)0x00D00000) /*!< Remap USART6 Rx on DMA1 channel 6 */
mbed_official 441:d2c15dda23c1 2680 #define DMA1_CSELR_CH6_USART7_RX ((uint32_t)0x00E00000) /*!< Remap USART7 Rx on DMA1 channel 6 */
mbed_official 441:d2c15dda23c1 2681 #define DMA1_CSELR_CH6_USART8_RX ((uint32_t)0x00F00000) /*!< Remap USART8 Rx on DMA1 channel 6 */
mbed_official 441:d2c15dda23c1 2682 #define DMA1_CSELR_CH7_I2C1_RX ((uint32_t)0x02000000) /*!< Remap I2C1 Rx on DMA1 channel 7 */
mbed_official 441:d2c15dda23c1 2683 #define DMA1_CSELR_CH7_SPI2_TX ((uint32_t)0x03000000) /*!< Remap SPI2 Tx on DMA1 channel 7 */
mbed_official 441:d2c15dda23c1 2684 #define DMA1_CSELR_CH7_TIM2_CH2 ((uint32_t)0x05000000) /*!< Remap TIM2 channel 2 on DMA1 channel 7 */
mbed_official 441:d2c15dda23c1 2685 #define DMA1_CSELR_CH7_TIM2_CH4 ((uint32_t)0x05000000) /*!< Remap TIM2 channel 4 on DMA1 channel 7 */
mbed_official 441:d2c15dda23c1 2686 #define DMA1_CSELR_CH7_TIM17_CH1 ((uint32_t)0x07000000) /*!< Remap TIM17 channel 1 on DMA1 channel 7 */
mbed_official 441:d2c15dda23c1 2687 #define DMA1_CSELR_CH7_TIM17_UP ((uint32_t)0x07000000) /*!< Remap TIM17 up on DMA1 channel 7 */
mbed_official 441:d2c15dda23c1 2688 #define DMA1_CSELR_CH7_USART1_TX ((uint32_t)0x08000000) /*!< Remap USART1 Tx on DMA1 channel 7 */
mbed_official 441:d2c15dda23c1 2689 #define DMA1_CSELR_CH7_USART2_TX ((uint32_t)0x09000000) /*!< Remap USART2 Tx on DMA1 channel 7 */
mbed_official 441:d2c15dda23c1 2690 #define DMA1_CSELR_CH7_USART3_TX ((uint32_t)0x0A000000) /*!< Remap USART3 Tx on DMA1 channel 7 */
mbed_official 441:d2c15dda23c1 2691 #define DMA1_CSELR_CH7_USART4_TX ((uint32_t)0x0B000000) /*!< Remap USART4 Tx on DMA1 channel 7 */
mbed_official 441:d2c15dda23c1 2692 #define DMA1_CSELR_CH7_USART5_TX ((uint32_t)0x0C000000) /*!< Remap USART5 Tx on DMA1 channel 7 */
mbed_official 441:d2c15dda23c1 2693 #define DMA1_CSELR_CH7_USART6_TX ((uint32_t)0x0D000000) /*!< Remap USART6 Tx on DMA1 channel 7 */
mbed_official 441:d2c15dda23c1 2694 #define DMA1_CSELR_CH7_USART7_TX ((uint32_t)0x0E000000) /*!< Remap USART7 Tx on DMA1 channel 7 */
mbed_official 441:d2c15dda23c1 2695 #define DMA1_CSELR_CH7_USART8_TX ((uint32_t)0x0F000000) /*!< Remap USART8 Tx on DMA1 channel 7 */
mbed_official 441:d2c15dda23c1 2696
mbed_official 441:d2c15dda23c1 2697 /****************** Bit definition for DMA2_CSELR register ********************/
mbed_official 441:d2c15dda23c1 2698 #define DMA2_CSELR_DEFAULT ((uint32_t)0x00000000) /*!< Default remap position for DMA2 */
mbed_official 441:d2c15dda23c1 2699 #define DMA2_CSELR_CH1_I2C2_TX ((uint32_t)0x00000002) /*!< Remap I2C2 TX on DMA2 channel 1 */
mbed_official 441:d2c15dda23c1 2700 #define DMA2_CSELR_CH1_USART1_TX ((uint32_t)0x00000008) /*!< Remap USART1 Tx on DMA2 channel 1 */
mbed_official 441:d2c15dda23c1 2701 #define DMA2_CSELR_CH1_USART2_TX ((uint32_t)0x00000009) /*!< Remap USART2 Tx on DMA2 channel 1 */
mbed_official 441:d2c15dda23c1 2702 #define DMA2_CSELR_CH1_USART3_TX ((uint32_t)0x0000000A) /*!< Remap USART3 Tx on DMA2 channel 1 */
mbed_official 441:d2c15dda23c1 2703 #define DMA2_CSELR_CH1_USART4_TX ((uint32_t)0x0000000B) /*!< Remap USART4 Tx on DMA2 channel 1 */
mbed_official 441:d2c15dda23c1 2704 #define DMA2_CSELR_CH1_USART5_TX ((uint32_t)0x0000000C) /*!< Remap USART5 Tx on DMA2 channel 1 */
mbed_official 441:d2c15dda23c1 2705 #define DMA2_CSELR_CH1_USART6_TX ((uint32_t)0x0000000D) /*!< Remap USART6 Tx on DMA2 channel 1 */
mbed_official 441:d2c15dda23c1 2706 #define DMA2_CSELR_CH1_USART7_TX ((uint32_t)0x0000000E) /*!< Remap USART7 Tx on DMA2 channel 1 */
mbed_official 441:d2c15dda23c1 2707 #define DMA2_CSELR_CH1_USART8_TX ((uint32_t)0x0000000F) /*!< Remap USART8 Tx on DMA2 channel 1 */
mbed_official 441:d2c15dda23c1 2708 #define DMA2_CSELR_CH2_I2C2_RX ((uint32_t)0x00000020) /*!< Remap I2C2 Rx on DMA2 channel 2 */
mbed_official 441:d2c15dda23c1 2709 #define DMA2_CSELR_CH2_USART1_RX ((uint32_t)0x00000080) /*!< Remap USART1 Rx on DMA2 channel 2 */
mbed_official 441:d2c15dda23c1 2710 #define DMA2_CSELR_CH2_USART2_RX ((uint32_t)0x00000090) /*!< Remap USART2 Rx on DMA2 channel 2 */
mbed_official 441:d2c15dda23c1 2711 #define DMA2_CSELR_CH2_USART3_RX ((uint32_t)0x000000A0) /*!< Remap USART3 Rx on DMA2 channel 2 */
mbed_official 441:d2c15dda23c1 2712 #define DMA2_CSELR_CH2_USART4_RX ((uint32_t)0x000000B0) /*!< Remap USART4 Rx on DMA2 channel 2 */
mbed_official 441:d2c15dda23c1 2713 #define DMA2_CSELR_CH2_USART5_RX ((uint32_t)0x000000C0) /*!< Remap USART5 Rx on DMA2 channel 2 */
mbed_official 441:d2c15dda23c1 2714 #define DMA2_CSELR_CH2_USART6_RX ((uint32_t)0x000000D0) /*!< Remap USART6 Rx on DMA2 channel 2 */
mbed_official 441:d2c15dda23c1 2715 #define DMA2_CSELR_CH2_USART7_RX ((uint32_t)0x000000E0) /*!< Remap USART7 Rx on DMA2 channel 2 */
mbed_official 441:d2c15dda23c1 2716 #define DMA2_CSELR_CH2_USART8_RX ((uint32_t)0x000000F0) /*!< Remap USART8 Rx on DMA2 channel 2 */
mbed_official 441:d2c15dda23c1 2717 #define DMA2_CSELR_CH3_TIM6_UP ((uint32_t)0x00000100) /*!< Remap TIM6 up on DMA2 channel 3 */
mbed_official 441:d2c15dda23c1 2718 #define DMA2_CSELR_CH3_DAC_CH1 ((uint32_t)0x00000100) /*!< Remap DAC channel 1 on DMA2 channel 3 */
mbed_official 441:d2c15dda23c1 2719 #define DMA2_CSELR_CH3_SPI1_RX ((uint32_t)0x00000300) /*!< Remap SPI1 Rx on DMA2 channel 3 */
mbed_official 441:d2c15dda23c1 2720 #define DMA2_CSELR_CH3_USART1_RX ((uint32_t)0x00000800) /*!< Remap USART1 Rx on DMA2 channel 3 */
mbed_official 441:d2c15dda23c1 2721 #define DMA2_CSELR_CH3_USART2_RX ((uint32_t)0x00000900) /*!< Remap USART2 Rx on DMA2 channel 3 */
mbed_official 441:d2c15dda23c1 2722 #define DMA2_CSELR_CH3_USART3_RX ((uint32_t)0x00000A00) /*!< Remap USART3 Rx on DMA2 channel 3 */
mbed_official 441:d2c15dda23c1 2723 #define DMA2_CSELR_CH3_USART4_RX ((uint32_t)0x00000B00) /*!< Remap USART4 Rx on DMA2 channel 3 */
mbed_official 441:d2c15dda23c1 2724 #define DMA2_CSELR_CH3_USART5_RX ((uint32_t)0x00000C00) /*!< Remap USART5 Rx on DMA2 channel 3 */
mbed_official 441:d2c15dda23c1 2725 #define DMA2_CSELR_CH3_USART6_RX ((uint32_t)0x00000D00) /*!< Remap USART6 Rx on DMA2 channel 3 */
mbed_official 441:d2c15dda23c1 2726 #define DMA2_CSELR_CH3_USART7_RX ((uint32_t)0x00000E00) /*!< Remap USART7 Rx on DMA2 channel 3 */
mbed_official 441:d2c15dda23c1 2727 #define DMA2_CSELR_CH3_USART8_RX ((uint32_t)0x00000F00) /*!< Remap USART8 Rx on DMA2 channel 3 */
mbed_official 441:d2c15dda23c1 2728 #define DMA2_CSELR_CH4_TIM7_UP ((uint32_t)0x00001000) /*!< Remap TIM7 up on DMA2 channel 4 */
mbed_official 441:d2c15dda23c1 2729 #define DMA2_CSELR_CH4_DAC_CH2 ((uint32_t)0x00001000) /*!< Remap DAC channel 2 on DMA2 channel 4 */
mbed_official 441:d2c15dda23c1 2730 #define DMA2_CSELR_CH4_SPI1_TX ((uint32_t)0x00003000) /*!< Remap SPI1 Tx on DMA2 channel 4 */
mbed_official 441:d2c15dda23c1 2731 #define DMA2_CSELR_CH4_USART1_TX ((uint32_t)0x00008000) /*!< Remap USART1 Tx on DMA2 channel 4 */
mbed_official 441:d2c15dda23c1 2732 #define DMA2_CSELR_CH4_USART2_TX ((uint32_t)0x00009000) /*!< Remap USART2 Tx on DMA2 channel 4 */
mbed_official 441:d2c15dda23c1 2733 #define DMA2_CSELR_CH4_USART3_TX ((uint32_t)0x0000A000) /*!< Remap USART3 Tx on DMA2 channel 4 */
mbed_official 441:d2c15dda23c1 2734 #define DMA2_CSELR_CH4_USART4_TX ((uint32_t)0x0000B000) /*!< Remap USART4 Tx on DMA2 channel 4 */
mbed_official 441:d2c15dda23c1 2735 #define DMA2_CSELR_CH4_USART5_TX ((uint32_t)0x0000C000) /*!< Remap USART5 Tx on DMA2 channel 4 */
mbed_official 441:d2c15dda23c1 2736 #define DMA2_CSELR_CH4_USART6_TX ((uint32_t)0x0000D000) /*!< Remap USART6 Tx on DMA2 channel 4 */
mbed_official 441:d2c15dda23c1 2737 #define DMA2_CSELR_CH4_USART7_TX ((uint32_t)0x0000E000) /*!< Remap USART7 Tx on DMA2 channel 4 */
mbed_official 441:d2c15dda23c1 2738 #define DMA2_CSELR_CH4_USART8_TX ((uint32_t)0x0000F000) /*!< Remap USART8 Tx on DMA2 channel 4 */
mbed_official 441:d2c15dda23c1 2739 #define DMA2_CSELR_CH5_ADC ((uint32_t)0x00010000) /*!< Remap ADC on DMA2 channel 5 */
mbed_official 441:d2c15dda23c1 2740 #define DMA2_CSELR_CH5_USART1_TX ((uint32_t)0x00080000) /*!< Remap USART1 Tx on DMA2 channel 5 */
mbed_official 441:d2c15dda23c1 2741 #define DMA2_CSELR_CH5_USART2_TX ((uint32_t)0x00090000) /*!< Remap USART2 Tx on DMA2 channel 5 */
mbed_official 441:d2c15dda23c1 2742 #define DMA2_CSELR_CH5_USART3_TX ((uint32_t)0x000A0000) /*!< Remap USART3 Tx on DMA2 channel 5 */
mbed_official 441:d2c15dda23c1 2743 #define DMA2_CSELR_CH5_USART4_TX ((uint32_t)0x000B0000) /*!< Remap USART4 Tx on DMA2 channel 5 */
mbed_official 441:d2c15dda23c1 2744 #define DMA2_CSELR_CH5_USART5_TX ((uint32_t)0x000C0000) /*!< Remap USART5 Tx on DMA2 channel 5 */
mbed_official 441:d2c15dda23c1 2745 #define DMA2_CSELR_CH5_USART6_TX ((uint32_t)0x000D0000) /*!< Remap USART6 Tx on DMA2 channel 5 */
mbed_official 441:d2c15dda23c1 2746 #define DMA2_CSELR_CH5_USART7_TX ((uint32_t)0x000E0000) /*!< Remap USART7 Tx on DMA2 channel 5 */
mbed_official 441:d2c15dda23c1 2747 #define DMA2_CSELR_CH5_USART8_TX ((uint32_t)0x000F0000) /*!< Remap USART8 Tx on DMA2 channel 5 */
mbed_official 340:28d1f895c6fe 2748
mbed_official 340:28d1f895c6fe 2749 /******************************************************************************/
mbed_official 340:28d1f895c6fe 2750 /* */
mbed_official 340:28d1f895c6fe 2751 /* External Interrupt/Event Controller (EXTI) */
mbed_official 340:28d1f895c6fe 2752 /* */
mbed_official 340:28d1f895c6fe 2753 /******************************************************************************/
mbed_official 340:28d1f895c6fe 2754 /******************* Bit definition for EXTI_IMR register *******************/
mbed_official 340:28d1f895c6fe 2755 #define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
mbed_official 340:28d1f895c6fe 2756 #define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
mbed_official 340:28d1f895c6fe 2757 #define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
mbed_official 340:28d1f895c6fe 2758 #define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
mbed_official 340:28d1f895c6fe 2759 #define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
mbed_official 340:28d1f895c6fe 2760 #define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
mbed_official 340:28d1f895c6fe 2761 #define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
mbed_official 340:28d1f895c6fe 2762 #define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
mbed_official 340:28d1f895c6fe 2763 #define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
mbed_official 340:28d1f895c6fe 2764 #define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
mbed_official 340:28d1f895c6fe 2765 #define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
mbed_official 340:28d1f895c6fe 2766 #define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
mbed_official 340:28d1f895c6fe 2767 #define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
mbed_official 340:28d1f895c6fe 2768 #define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
mbed_official 340:28d1f895c6fe 2769 #define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
mbed_official 340:28d1f895c6fe 2770 #define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
mbed_official 340:28d1f895c6fe 2771 #define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
mbed_official 340:28d1f895c6fe 2772 #define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
mbed_official 340:28d1f895c6fe 2773 #define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
mbed_official 441:d2c15dda23c1 2774 #define EXTI_IMR_MR20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */
mbed_official 340:28d1f895c6fe 2775 #define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */
mbed_official 340:28d1f895c6fe 2776 #define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */
mbed_official 340:28d1f895c6fe 2777 #define EXTI_IMR_MR23 ((uint32_t)0x00800000) /*!< Interrupt Mask on line 23 */
mbed_official 340:28d1f895c6fe 2778 #define EXTI_IMR_MR25 ((uint32_t)0x02000000) /*!< Interrupt Mask on line 25 */
mbed_official 441:d2c15dda23c1 2779 #define EXTI_IMR_MR26 ((uint32_t)0x04000000) /*!< Interrupt Mask on line 26 */
mbed_official 340:28d1f895c6fe 2780 #define EXTI_IMR_MR27 ((uint32_t)0x08000000) /*!< Interrupt Mask on line 27 */
mbed_official 441:d2c15dda23c1 2781 #define EXTI_IMR_MR28 ((uint32_t)0x10000000) /*!< Interrupt Mask on line 28 */
mbed_official 441:d2c15dda23c1 2782 #define EXTI_IMR_MR31 ((uint32_t)0x80000000) /*!< Interrupt Mask on line 31 */
mbed_official 340:28d1f895c6fe 2783
mbed_official 340:28d1f895c6fe 2784 /****************** Bit definition for EXTI_EMR register ********************/
mbed_official 340:28d1f895c6fe 2785 #define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
mbed_official 340:28d1f895c6fe 2786 #define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
mbed_official 340:28d1f895c6fe 2787 #define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
mbed_official 340:28d1f895c6fe 2788 #define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
mbed_official 340:28d1f895c6fe 2789 #define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
mbed_official 340:28d1f895c6fe 2790 #define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
mbed_official 340:28d1f895c6fe 2791 #define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
mbed_official 340:28d1f895c6fe 2792 #define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
mbed_official 340:28d1f895c6fe 2793 #define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
mbed_official 340:28d1f895c6fe 2794 #define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
mbed_official 340:28d1f895c6fe 2795 #define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
mbed_official 340:28d1f895c6fe 2796 #define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
mbed_official 340:28d1f895c6fe 2797 #define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
mbed_official 340:28d1f895c6fe 2798 #define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
mbed_official 340:28d1f895c6fe 2799 #define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
mbed_official 340:28d1f895c6fe 2800 #define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
mbed_official 340:28d1f895c6fe 2801 #define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
mbed_official 340:28d1f895c6fe 2802 #define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
mbed_official 340:28d1f895c6fe 2803 #define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
mbed_official 441:d2c15dda23c1 2804 #define EXTI_EMR_MR20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */
mbed_official 340:28d1f895c6fe 2805 #define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */
mbed_official 340:28d1f895c6fe 2806 #define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */
mbed_official 340:28d1f895c6fe 2807 #define EXTI_EMR_MR23 ((uint32_t)0x00800000) /*!< Event Mask on line 23 */
mbed_official 340:28d1f895c6fe 2808 #define EXTI_EMR_MR25 ((uint32_t)0x02000000) /*!< Event Mask on line 25 */
mbed_official 441:d2c15dda23c1 2809 #define EXTI_EMR_MR26 ((uint32_t)0x04000000) /*!< Event Mask on line 26 */
mbed_official 340:28d1f895c6fe 2810 #define EXTI_EMR_MR27 ((uint32_t)0x08000000) /*!< Event Mask on line 27 */
mbed_official 441:d2c15dda23c1 2811 #define EXTI_EMR_MR28 ((uint32_t)0x10000000) /*!< Event Mask on line 28 */
mbed_official 441:d2c15dda23c1 2812 #define EXTI_EMR_MR31 ((uint32_t)0x80000000) /*!< Event Mask on line 31 */
mbed_official 340:28d1f895c6fe 2813
mbed_official 340:28d1f895c6fe 2814 /******************* Bit definition for EXTI_RTSR register ******************/
mbed_official 340:28d1f895c6fe 2815 #define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
mbed_official 340:28d1f895c6fe 2816 #define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
mbed_official 340:28d1f895c6fe 2817 #define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
mbed_official 340:28d1f895c6fe 2818 #define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
mbed_official 340:28d1f895c6fe 2819 #define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
mbed_official 340:28d1f895c6fe 2820 #define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
mbed_official 340:28d1f895c6fe 2821 #define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
mbed_official 340:28d1f895c6fe 2822 #define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
mbed_official 340:28d1f895c6fe 2823 #define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
mbed_official 340:28d1f895c6fe 2824 #define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
mbed_official 340:28d1f895c6fe 2825 #define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
mbed_official 340:28d1f895c6fe 2826 #define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
mbed_official 340:28d1f895c6fe 2827 #define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
mbed_official 340:28d1f895c6fe 2828 #define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
mbed_official 340:28d1f895c6fe 2829 #define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
mbed_official 340:28d1f895c6fe 2830 #define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
mbed_official 340:28d1f895c6fe 2831 #define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
mbed_official 340:28d1f895c6fe 2832 #define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
mbed_official 340:28d1f895c6fe 2833 #define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
mbed_official 441:d2c15dda23c1 2834 #define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
mbed_official 441:d2c15dda23c1 2835 #define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
mbed_official 441:d2c15dda23c1 2836 #define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
mbed_official 340:28d1f895c6fe 2837
mbed_official 340:28d1f895c6fe 2838 /******************* Bit definition for EXTI_FTSR register *******************/
mbed_official 340:28d1f895c6fe 2839 #define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
mbed_official 340:28d1f895c6fe 2840 #define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
mbed_official 340:28d1f895c6fe 2841 #define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
mbed_official 340:28d1f895c6fe 2842 #define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
mbed_official 340:28d1f895c6fe 2843 #define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
mbed_official 340:28d1f895c6fe 2844 #define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
mbed_official 340:28d1f895c6fe 2845 #define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
mbed_official 340:28d1f895c6fe 2846 #define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
mbed_official 340:28d1f895c6fe 2847 #define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
mbed_official 340:28d1f895c6fe 2848 #define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
mbed_official 340:28d1f895c6fe 2849 #define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
mbed_official 340:28d1f895c6fe 2850 #define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
mbed_official 340:28d1f895c6fe 2851 #define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
mbed_official 340:28d1f895c6fe 2852 #define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
mbed_official 340:28d1f895c6fe 2853 #define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
mbed_official 340:28d1f895c6fe 2854 #define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
mbed_official 340:28d1f895c6fe 2855 #define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
mbed_official 340:28d1f895c6fe 2856 #define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
mbed_official 340:28d1f895c6fe 2857 #define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
mbed_official 441:d2c15dda23c1 2858 #define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
mbed_official 441:d2c15dda23c1 2859 #define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
mbed_official 441:d2c15dda23c1 2860 #define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
mbed_official 340:28d1f895c6fe 2861
mbed_official 340:28d1f895c6fe 2862 /******************* Bit definition for EXTI_SWIER register *******************/
mbed_official 340:28d1f895c6fe 2863 #define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
mbed_official 340:28d1f895c6fe 2864 #define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
mbed_official 340:28d1f895c6fe 2865 #define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
mbed_official 340:28d1f895c6fe 2866 #define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
mbed_official 340:28d1f895c6fe 2867 #define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
mbed_official 340:28d1f895c6fe 2868 #define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
mbed_official 340:28d1f895c6fe 2869 #define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
mbed_official 340:28d1f895c6fe 2870 #define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
mbed_official 340:28d1f895c6fe 2871 #define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
mbed_official 340:28d1f895c6fe 2872 #define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
mbed_official 340:28d1f895c6fe 2873 #define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
mbed_official 340:28d1f895c6fe 2874 #define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
mbed_official 340:28d1f895c6fe 2875 #define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
mbed_official 340:28d1f895c6fe 2876 #define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
mbed_official 340:28d1f895c6fe 2877 #define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
mbed_official 340:28d1f895c6fe 2878 #define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
mbed_official 340:28d1f895c6fe 2879 #define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
mbed_official 340:28d1f895c6fe 2880 #define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
mbed_official 340:28d1f895c6fe 2881 #define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
mbed_official 441:d2c15dda23c1 2882 #define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
mbed_official 441:d2c15dda23c1 2883 #define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
mbed_official 441:d2c15dda23c1 2884 #define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
mbed_official 340:28d1f895c6fe 2885
mbed_official 340:28d1f895c6fe 2886 /****************** Bit definition for EXTI_PR register *********************/
mbed_official 340:28d1f895c6fe 2887 #define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit 0 */
mbed_official 340:28d1f895c6fe 2888 #define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit 1 */
mbed_official 340:28d1f895c6fe 2889 #define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit 2 */
mbed_official 340:28d1f895c6fe 2890 #define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit 3 */
mbed_official 340:28d1f895c6fe 2891 #define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit 4 */
mbed_official 340:28d1f895c6fe 2892 #define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit 5 */
mbed_official 340:28d1f895c6fe 2893 #define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit 6 */
mbed_official 340:28d1f895c6fe 2894 #define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit 7 */
mbed_official 340:28d1f895c6fe 2895 #define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit 8 */
mbed_official 340:28d1f895c6fe 2896 #define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit 9 */
mbed_official 340:28d1f895c6fe 2897 #define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit 10 */
mbed_official 340:28d1f895c6fe 2898 #define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit 11 */
mbed_official 340:28d1f895c6fe 2899 #define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit 12 */
mbed_official 340:28d1f895c6fe 2900 #define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit 13 */
mbed_official 340:28d1f895c6fe 2901 #define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit 14 */
mbed_official 340:28d1f895c6fe 2902 #define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit 15 */
mbed_official 340:28d1f895c6fe 2903 #define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit 16 */
mbed_official 340:28d1f895c6fe 2904 #define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit 17 */
mbed_official 340:28d1f895c6fe 2905 #define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit 19 */
mbed_official 441:d2c15dda23c1 2906 #define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit 20 */
mbed_official 441:d2c15dda23c1 2907 #define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit 21 */
mbed_official 441:d2c15dda23c1 2908 #define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit 22 */
mbed_official 340:28d1f895c6fe 2909
mbed_official 340:28d1f895c6fe 2910 /******************************************************************************/
mbed_official 340:28d1f895c6fe 2911 /* */
mbed_official 340:28d1f895c6fe 2912 /* FLASH and Option Bytes Registers */
mbed_official 340:28d1f895c6fe 2913 /* */
mbed_official 340:28d1f895c6fe 2914 /******************************************************************************/
mbed_official 340:28d1f895c6fe 2915
mbed_official 340:28d1f895c6fe 2916 /******************* Bit definition for FLASH_ACR register ******************/
mbed_official 340:28d1f895c6fe 2917 #define FLASH_ACR_LATENCY ((uint32_t)0x00000001) /*!< LATENCY bit (Latency) */
mbed_official 340:28d1f895c6fe 2918
mbed_official 340:28d1f895c6fe 2919 #define FLASH_ACR_PRFTBE ((uint32_t)0x00000010) /*!< Prefetch Buffer Enable */
mbed_official 340:28d1f895c6fe 2920 #define FLASH_ACR_PRFTBS ((uint32_t)0x00000020) /*!< Prefetch Buffer Status */
mbed_official 340:28d1f895c6fe 2921
mbed_official 340:28d1f895c6fe 2922 /****************** Bit definition for FLASH_KEYR register ******************/
mbed_official 340:28d1f895c6fe 2923 #define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /*!< FPEC Key */
mbed_official 340:28d1f895c6fe 2924
mbed_official 340:28d1f895c6fe 2925 /***************** Bit definition for FLASH_OPTKEYR register ****************/
mbed_official 340:28d1f895c6fe 2926 #define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!< Option Byte Key */
mbed_official 340:28d1f895c6fe 2927
mbed_official 340:28d1f895c6fe 2928 /****************** FLASH Keys **********************************************/
mbed_official 340:28d1f895c6fe 2929 #define FLASH_FKEY1 ((uint32_t)0x45670123) /*!< Flash program erase key1 */
mbed_official 340:28d1f895c6fe 2930 #define FLASH_FKEY2 ((uint32_t)0xCDEF89AB) /*!< Flash program erase key2: used with FLASH_PEKEY1
mbed_official 340:28d1f895c6fe 2931 to unlock the write access to the FPEC. */
mbed_official 340:28d1f895c6fe 2932
mbed_official 340:28d1f895c6fe 2933 #define FLASH_OPTKEY1 ((uint32_t)0x45670123) /*!< Flash option key1 */
mbed_official 340:28d1f895c6fe 2934 #define FLASH_OPTKEY2 ((uint32_t)0xCDEF89AB) /*!< Flash option key2: used with FLASH_OPTKEY1 to
mbed_official 340:28d1f895c6fe 2935 unlock the write access to the option byte block */
mbed_official 340:28d1f895c6fe 2936
mbed_official 340:28d1f895c6fe 2937 /****************** Bit definition for FLASH_SR register *******************/
mbed_official 340:28d1f895c6fe 2938 #define FLASH_SR_BSY ((uint32_t)0x00000001) /*!< Busy */
mbed_official 340:28d1f895c6fe 2939 #define FLASH_SR_PGERR ((uint32_t)0x00000004) /*!< Programming Error */
mbed_official 340:28d1f895c6fe 2940 #define FLASH_SR_WRPRTERR ((uint32_t)0x00000010) /*!< Write Protection Error */
mbed_official 340:28d1f895c6fe 2941 #define FLASH_SR_EOP ((uint32_t)0x00000020) /*!< End of operation */
mbed_official 340:28d1f895c6fe 2942 #define FLASH_SR_WRPERR FLASH_SR_WRPRTERR /*!< Legacy of Write Protection Error */
mbed_official 340:28d1f895c6fe 2943
mbed_official 340:28d1f895c6fe 2944 /******************* Bit definition for FLASH_CR register *******************/
mbed_official 340:28d1f895c6fe 2945 #define FLASH_CR_PG ((uint32_t)0x00000001) /*!< Programming */
mbed_official 340:28d1f895c6fe 2946 #define FLASH_CR_PER ((uint32_t)0x00000002) /*!< Page Erase */
mbed_official 340:28d1f895c6fe 2947 #define FLASH_CR_MER ((uint32_t)0x00000004) /*!< Mass Erase */
mbed_official 340:28d1f895c6fe 2948 #define FLASH_CR_OPTPG ((uint32_t)0x00000010) /*!< Option Byte Programming */
mbed_official 340:28d1f895c6fe 2949 #define FLASH_CR_OPTER ((uint32_t)0x00000020) /*!< Option Byte Erase */
mbed_official 340:28d1f895c6fe 2950 #define FLASH_CR_STRT ((uint32_t)0x00000040) /*!< Start */
mbed_official 340:28d1f895c6fe 2951 #define FLASH_CR_LOCK ((uint32_t)0x00000080) /*!< Lock */
mbed_official 340:28d1f895c6fe 2952 #define FLASH_CR_OPTWRE ((uint32_t)0x00000200) /*!< Option Bytes Write Enable */
mbed_official 340:28d1f895c6fe 2953 #define FLASH_CR_ERRIE ((uint32_t)0x00000400) /*!< Error Interrupt Enable */
mbed_official 340:28d1f895c6fe 2954 #define FLASH_CR_EOPIE ((uint32_t)0x00001000) /*!< End of operation interrupt enable */
mbed_official 340:28d1f895c6fe 2955 #define FLASH_CR_OBL_LAUNCH ((uint32_t)0x00002000) /*!< Option Bytes Loader Launch */
mbed_official 340:28d1f895c6fe 2956
mbed_official 340:28d1f895c6fe 2957 /******************* Bit definition for FLASH_AR register *******************/
mbed_official 340:28d1f895c6fe 2958 #define FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) /*!< Flash Address */
mbed_official 340:28d1f895c6fe 2959
mbed_official 340:28d1f895c6fe 2960 /****************** Bit definition for FLASH_OBR register *******************/
mbed_official 340:28d1f895c6fe 2961 #define FLASH_OBR_OPTERR ((uint32_t)0x00000001) /*!< Option Byte Error */
mbed_official 340:28d1f895c6fe 2962 #define FLASH_OBR_RDPRT1 ((uint32_t)0x00000002) /*!< Read protection Level 1 */
mbed_official 340:28d1f895c6fe 2963 #define FLASH_OBR_RDPRT2 ((uint32_t)0x00000004) /*!< Read protection Level 2 */
mbed_official 340:28d1f895c6fe 2964
mbed_official 340:28d1f895c6fe 2965 #define FLASH_OBR_USER ((uint32_t)0x00003700) /*!< User Option Bytes */
mbed_official 340:28d1f895c6fe 2966 #define FLASH_OBR_IWDG_SW ((uint32_t)0x00000100) /*!< IWDG SW */
mbed_official 340:28d1f895c6fe 2967 #define FLASH_OBR_nRST_STOP ((uint32_t)0x00000200) /*!< nRST_STOP */
mbed_official 340:28d1f895c6fe 2968 #define FLASH_OBR_nRST_STDBY ((uint32_t)0x00000400) /*!< nRST_STDBY */
mbed_official 340:28d1f895c6fe 2969 #define FLASH_OBR_nBOOT1 ((uint32_t)0x00001000) /*!< nBOOT1 */
mbed_official 340:28d1f895c6fe 2970 #define FLASH_OBR_VDDA_MONITOR ((uint32_t)0x00002000) /*!< VDDA power supply supervisor */
mbed_official 340:28d1f895c6fe 2971
mbed_official 340:28d1f895c6fe 2972 /* Old BOOT1 bit definition, maintained for legacy purpose */
mbed_official 340:28d1f895c6fe 2973 #define FLASH_OBR_BOOT1 FLASH_OBR_nBOOT1
mbed_official 340:28d1f895c6fe 2974
mbed_official 340:28d1f895c6fe 2975 /* Old OBR_VDDA bit definition, maintained for legacy purpose */
mbed_official 340:28d1f895c6fe 2976 #define FLASH_OBR_VDDA_ANALOG FLASH_OBR_VDDA_MONITOR
mbed_official 340:28d1f895c6fe 2977
mbed_official 340:28d1f895c6fe 2978 /****************** Bit definition for FLASH_WRPR register ******************/
mbed_official 340:28d1f895c6fe 2979 #define FLASH_WRPR_WRP ((uint32_t)0x0000FFFF) /*!< Write Protect */
mbed_official 340:28d1f895c6fe 2980
mbed_official 340:28d1f895c6fe 2981 /*----------------------------------------------------------------------------*/
mbed_official 340:28d1f895c6fe 2982
mbed_official 340:28d1f895c6fe 2983 /****************** Bit definition for OB_RDP register **********************/
mbed_official 340:28d1f895c6fe 2984 #define OB_RDP_RDP ((uint32_t)0x000000FF) /*!< Read protection option byte */
mbed_official 340:28d1f895c6fe 2985 #define OB_RDP_nRDP ((uint32_t)0x0000FF00) /*!< Read protection complemented option byte */
mbed_official 340:28d1f895c6fe 2986
mbed_official 340:28d1f895c6fe 2987 /****************** Bit definition for OB_USER register *********************/
mbed_official 340:28d1f895c6fe 2988 #define OB_USER_USER ((uint32_t)0x00FF0000) /*!< User option byte */
mbed_official 340:28d1f895c6fe 2989 #define OB_USER_nUSER ((uint32_t)0xFF000000) /*!< User complemented option byte */
mbed_official 340:28d1f895c6fe 2990
mbed_official 340:28d1f895c6fe 2991 /****************** Bit definition for OB_WRP0 register *********************/
mbed_official 340:28d1f895c6fe 2992 #define OB_WRP0_WRP0 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */
mbed_official 340:28d1f895c6fe 2993 #define OB_WRP0_nWRP0 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */
mbed_official 340:28d1f895c6fe 2994
mbed_official 340:28d1f895c6fe 2995 /****************** Bit definition for OB_WRP1 register *********************/
mbed_official 340:28d1f895c6fe 2996 #define OB_WRP1_WRP1 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */
mbed_official 340:28d1f895c6fe 2997 #define OB_WRP1_nWRP1 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */
mbed_official 340:28d1f895c6fe 2998
mbed_official 340:28d1f895c6fe 2999 /****************** Bit definition for OB_WRP2 register *********************/
mbed_official 340:28d1f895c6fe 3000 #define OB_WRP2_WRP2 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */
mbed_official 340:28d1f895c6fe 3001 #define OB_WRP2_nWRP2 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */
mbed_official 340:28d1f895c6fe 3002
mbed_official 340:28d1f895c6fe 3003 /****************** Bit definition for OB_WRP3 register *********************/
mbed_official 340:28d1f895c6fe 3004 #define OB_WRP3_WRP3 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */
mbed_official 340:28d1f895c6fe 3005 #define OB_WRP3_nWRP3 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */
mbed_official 340:28d1f895c6fe 3006
mbed_official 340:28d1f895c6fe 3007 /******************************************************************************/
mbed_official 340:28d1f895c6fe 3008 /* */
mbed_official 340:28d1f895c6fe 3009 /* General Purpose IOs (GPIO) */
mbed_official 340:28d1f895c6fe 3010 /* */
mbed_official 340:28d1f895c6fe 3011 /******************************************************************************/
mbed_official 340:28d1f895c6fe 3012 /******************* Bit definition for GPIO_MODER register *****************/
mbed_official 340:28d1f895c6fe 3013 #define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
mbed_official 340:28d1f895c6fe 3014 #define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
mbed_official 340:28d1f895c6fe 3015 #define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
mbed_official 340:28d1f895c6fe 3016 #define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
mbed_official 340:28d1f895c6fe 3017 #define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
mbed_official 340:28d1f895c6fe 3018 #define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
mbed_official 340:28d1f895c6fe 3019 #define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
mbed_official 340:28d1f895c6fe 3020 #define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
mbed_official 340:28d1f895c6fe 3021 #define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
mbed_official 340:28d1f895c6fe 3022 #define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
mbed_official 340:28d1f895c6fe 3023 #define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
mbed_official 340:28d1f895c6fe 3024 #define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
mbed_official 340:28d1f895c6fe 3025 #define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
mbed_official 340:28d1f895c6fe 3026 #define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
mbed_official 340:28d1f895c6fe 3027 #define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
mbed_official 340:28d1f895c6fe 3028 #define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
mbed_official 340:28d1f895c6fe 3029 #define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
mbed_official 340:28d1f895c6fe 3030 #define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
mbed_official 340:28d1f895c6fe 3031 #define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
mbed_official 340:28d1f895c6fe 3032 #define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
mbed_official 340:28d1f895c6fe 3033 #define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
mbed_official 340:28d1f895c6fe 3034 #define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
mbed_official 340:28d1f895c6fe 3035 #define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
mbed_official 340:28d1f895c6fe 3036 #define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
mbed_official 340:28d1f895c6fe 3037 #define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
mbed_official 340:28d1f895c6fe 3038 #define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
mbed_official 340:28d1f895c6fe 3039 #define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
mbed_official 340:28d1f895c6fe 3040 #define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
mbed_official 340:28d1f895c6fe 3041 #define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
mbed_official 340:28d1f895c6fe 3042 #define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
mbed_official 340:28d1f895c6fe 3043 #define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
mbed_official 340:28d1f895c6fe 3044 #define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
mbed_official 340:28d1f895c6fe 3045 #define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
mbed_official 340:28d1f895c6fe 3046 #define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
mbed_official 340:28d1f895c6fe 3047 #define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
mbed_official 340:28d1f895c6fe 3048 #define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
mbed_official 340:28d1f895c6fe 3049 #define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
mbed_official 340:28d1f895c6fe 3050 #define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
mbed_official 340:28d1f895c6fe 3051 #define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
mbed_official 340:28d1f895c6fe 3052 #define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
mbed_official 340:28d1f895c6fe 3053 #define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
mbed_official 340:28d1f895c6fe 3054 #define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
mbed_official 340:28d1f895c6fe 3055 #define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
mbed_official 340:28d1f895c6fe 3056 #define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
mbed_official 340:28d1f895c6fe 3057 #define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
mbed_official 340:28d1f895c6fe 3058 #define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
mbed_official 340:28d1f895c6fe 3059 #define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
mbed_official 340:28d1f895c6fe 3060 #define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
mbed_official 340:28d1f895c6fe 3061
mbed_official 340:28d1f895c6fe 3062 /****************** Bit definition for GPIO_OTYPER register *****************/
mbed_official 340:28d1f895c6fe 3063 #define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
mbed_official 340:28d1f895c6fe 3064 #define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
mbed_official 340:28d1f895c6fe 3065 #define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
mbed_official 340:28d1f895c6fe 3066 #define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
mbed_official 340:28d1f895c6fe 3067 #define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
mbed_official 340:28d1f895c6fe 3068 #define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
mbed_official 340:28d1f895c6fe 3069 #define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
mbed_official 340:28d1f895c6fe 3070 #define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
mbed_official 340:28d1f895c6fe 3071 #define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
mbed_official 340:28d1f895c6fe 3072 #define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
mbed_official 340:28d1f895c6fe 3073 #define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
mbed_official 340:28d1f895c6fe 3074 #define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
mbed_official 340:28d1f895c6fe 3075 #define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
mbed_official 340:28d1f895c6fe 3076 #define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
mbed_official 340:28d1f895c6fe 3077 #define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
mbed_official 340:28d1f895c6fe 3078 #define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
mbed_official 340:28d1f895c6fe 3079
mbed_official 340:28d1f895c6fe 3080 /**************** Bit definition for GPIO_OSPEEDR register ******************/
mbed_official 340:28d1f895c6fe 3081 #define GPIO_OSPEEDR_OSPEEDR0 ((uint32_t)0x00000003)
mbed_official 340:28d1f895c6fe 3082 #define GPIO_OSPEEDR_OSPEEDR0_0 ((uint32_t)0x00000001)
mbed_official 340:28d1f895c6fe 3083 #define GPIO_OSPEEDR_OSPEEDR0_1 ((uint32_t)0x00000002)
mbed_official 340:28d1f895c6fe 3084 #define GPIO_OSPEEDR_OSPEEDR1 ((uint32_t)0x0000000C)
mbed_official 340:28d1f895c6fe 3085 #define GPIO_OSPEEDR_OSPEEDR1_0 ((uint32_t)0x00000004)
mbed_official 340:28d1f895c6fe 3086 #define GPIO_OSPEEDR_OSPEEDR1_1 ((uint32_t)0x00000008)
mbed_official 340:28d1f895c6fe 3087 #define GPIO_OSPEEDR_OSPEEDR2 ((uint32_t)0x00000030)
mbed_official 340:28d1f895c6fe 3088 #define GPIO_OSPEEDR_OSPEEDR2_0 ((uint32_t)0x00000010)
mbed_official 340:28d1f895c6fe 3089 #define GPIO_OSPEEDR_OSPEEDR2_1 ((uint32_t)0x00000020)
mbed_official 340:28d1f895c6fe 3090 #define GPIO_OSPEEDR_OSPEEDR3 ((uint32_t)0x000000C0)
mbed_official 340:28d1f895c6fe 3091 #define GPIO_OSPEEDR_OSPEEDR3_0 ((uint32_t)0x00000040)
mbed_official 340:28d1f895c6fe 3092 #define GPIO_OSPEEDR_OSPEEDR3_1 ((uint32_t)0x00000080)
mbed_official 340:28d1f895c6fe 3093 #define GPIO_OSPEEDR_OSPEEDR4 ((uint32_t)0x00000300)
mbed_official 340:28d1f895c6fe 3094 #define GPIO_OSPEEDR_OSPEEDR4_0 ((uint32_t)0x00000100)
mbed_official 340:28d1f895c6fe 3095 #define GPIO_OSPEEDR_OSPEEDR4_1 ((uint32_t)0x00000200)
mbed_official 340:28d1f895c6fe 3096 #define GPIO_OSPEEDR_OSPEEDR5 ((uint32_t)0x00000C00)
mbed_official 340:28d1f895c6fe 3097 #define GPIO_OSPEEDR_OSPEEDR5_0 ((uint32_t)0x00000400)
mbed_official 340:28d1f895c6fe 3098 #define GPIO_OSPEEDR_OSPEEDR5_1 ((uint32_t)0x00000800)
mbed_official 340:28d1f895c6fe 3099 #define GPIO_OSPEEDR_OSPEEDR6 ((uint32_t)0x00003000)
mbed_official 340:28d1f895c6fe 3100 #define GPIO_OSPEEDR_OSPEEDR6_0 ((uint32_t)0x00001000)
mbed_official 340:28d1f895c6fe 3101 #define GPIO_OSPEEDR_OSPEEDR6_1 ((uint32_t)0x00002000)
mbed_official 340:28d1f895c6fe 3102 #define GPIO_OSPEEDR_OSPEEDR7 ((uint32_t)0x0000C000)
mbed_official 340:28d1f895c6fe 3103 #define GPIO_OSPEEDR_OSPEEDR7_0 ((uint32_t)0x00004000)
mbed_official 340:28d1f895c6fe 3104 #define GPIO_OSPEEDR_OSPEEDR7_1 ((uint32_t)0x00008000)
mbed_official 340:28d1f895c6fe 3105 #define GPIO_OSPEEDR_OSPEEDR8 ((uint32_t)0x00030000)
mbed_official 340:28d1f895c6fe 3106 #define GPIO_OSPEEDR_OSPEEDR8_0 ((uint32_t)0x00010000)
mbed_official 340:28d1f895c6fe 3107 #define GPIO_OSPEEDR_OSPEEDR8_1 ((uint32_t)0x00020000)
mbed_official 340:28d1f895c6fe 3108 #define GPIO_OSPEEDR_OSPEEDR9 ((uint32_t)0x000C0000)
mbed_official 340:28d1f895c6fe 3109 #define GPIO_OSPEEDR_OSPEEDR9_0 ((uint32_t)0x00040000)
mbed_official 340:28d1f895c6fe 3110 #define GPIO_OSPEEDR_OSPEEDR9_1 ((uint32_t)0x00080000)
mbed_official 340:28d1f895c6fe 3111 #define GPIO_OSPEEDR_OSPEEDR10 ((uint32_t)0x00300000)
mbed_official 340:28d1f895c6fe 3112 #define GPIO_OSPEEDR_OSPEEDR10_0 ((uint32_t)0x00100000)
mbed_official 340:28d1f895c6fe 3113 #define GPIO_OSPEEDR_OSPEEDR10_1 ((uint32_t)0x00200000)
mbed_official 340:28d1f895c6fe 3114 #define GPIO_OSPEEDR_OSPEEDR11 ((uint32_t)0x00C00000)
mbed_official 340:28d1f895c6fe 3115 #define GPIO_OSPEEDR_OSPEEDR11_0 ((uint32_t)0x00400000)
mbed_official 340:28d1f895c6fe 3116 #define GPIO_OSPEEDR_OSPEEDR11_1 ((uint32_t)0x00800000)
mbed_official 340:28d1f895c6fe 3117 #define GPIO_OSPEEDR_OSPEEDR12 ((uint32_t)0x03000000)
mbed_official 340:28d1f895c6fe 3118 #define GPIO_OSPEEDR_OSPEEDR12_0 ((uint32_t)0x01000000)
mbed_official 340:28d1f895c6fe 3119 #define GPIO_OSPEEDR_OSPEEDR12_1 ((uint32_t)0x02000000)
mbed_official 340:28d1f895c6fe 3120 #define GPIO_OSPEEDR_OSPEEDR13 ((uint32_t)0x0C000000)
mbed_official 340:28d1f895c6fe 3121 #define GPIO_OSPEEDR_OSPEEDR13_0 ((uint32_t)0x04000000)
mbed_official 340:28d1f895c6fe 3122 #define GPIO_OSPEEDR_OSPEEDR13_1 ((uint32_t)0x08000000)
mbed_official 340:28d1f895c6fe 3123 #define GPIO_OSPEEDR_OSPEEDR14 ((uint32_t)0x30000000)
mbed_official 340:28d1f895c6fe 3124 #define GPIO_OSPEEDR_OSPEEDR14_0 ((uint32_t)0x10000000)
mbed_official 340:28d1f895c6fe 3125 #define GPIO_OSPEEDR_OSPEEDR14_1 ((uint32_t)0x20000000)
mbed_official 340:28d1f895c6fe 3126 #define GPIO_OSPEEDR_OSPEEDR15 ((uint32_t)0xC0000000)
mbed_official 340:28d1f895c6fe 3127 #define GPIO_OSPEEDR_OSPEEDR15_0 ((uint32_t)0x40000000)
mbed_official 340:28d1f895c6fe 3128 #define GPIO_OSPEEDR_OSPEEDR15_1 ((uint32_t)0x80000000)
mbed_official 340:28d1f895c6fe 3129
mbed_official 340:28d1f895c6fe 3130 /* Old Bit definition for GPIO_OSPEEDR register maintained for legacy purpose */
mbed_official 340:28d1f895c6fe 3131 #define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEEDR0
mbed_official 340:28d1f895c6fe 3132 #define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEEDR0_0
mbed_official 340:28d1f895c6fe 3133 #define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEEDR0_1
mbed_official 340:28d1f895c6fe 3134 #define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEEDR1
mbed_official 340:28d1f895c6fe 3135 #define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEEDR1_0
mbed_official 340:28d1f895c6fe 3136 #define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEEDR1_1
mbed_official 340:28d1f895c6fe 3137 #define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEEDR2
mbed_official 340:28d1f895c6fe 3138 #define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEEDR2_0
mbed_official 340:28d1f895c6fe 3139 #define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEEDR2_1
mbed_official 340:28d1f895c6fe 3140 #define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEEDR3
mbed_official 340:28d1f895c6fe 3141 #define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEEDR3_0
mbed_official 340:28d1f895c6fe 3142 #define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEEDR3_1
mbed_official 340:28d1f895c6fe 3143 #define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEEDR4
mbed_official 340:28d1f895c6fe 3144 #define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEEDR4_0
mbed_official 340:28d1f895c6fe 3145 #define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEEDR4_1
mbed_official 340:28d1f895c6fe 3146 #define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEEDR5
mbed_official 340:28d1f895c6fe 3147 #define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEEDR5_0
mbed_official 340:28d1f895c6fe 3148 #define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEEDR5_1
mbed_official 340:28d1f895c6fe 3149 #define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEEDR6
mbed_official 340:28d1f895c6fe 3150 #define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEEDR6_0
mbed_official 340:28d1f895c6fe 3151 #define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEEDR6_1
mbed_official 340:28d1f895c6fe 3152 #define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEEDR7
mbed_official 340:28d1f895c6fe 3153 #define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEEDR7_0
mbed_official 340:28d1f895c6fe 3154 #define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEEDR7_1
mbed_official 340:28d1f895c6fe 3155 #define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEEDR8
mbed_official 340:28d1f895c6fe 3156 #define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEEDR8_0
mbed_official 340:28d1f895c6fe 3157 #define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEEDR8_1
mbed_official 340:28d1f895c6fe 3158 #define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEEDR9
mbed_official 340:28d1f895c6fe 3159 #define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEEDR9_0
mbed_official 340:28d1f895c6fe 3160 #define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEEDR9_1
mbed_official 340:28d1f895c6fe 3161 #define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEEDR10
mbed_official 340:28d1f895c6fe 3162 #define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEEDR10_0
mbed_official 340:28d1f895c6fe 3163 #define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEEDR10_1
mbed_official 340:28d1f895c6fe 3164 #define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEEDR11
mbed_official 340:28d1f895c6fe 3165 #define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEEDR11_0
mbed_official 340:28d1f895c6fe 3166 #define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEEDR11_1
mbed_official 340:28d1f895c6fe 3167 #define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEEDR12
mbed_official 340:28d1f895c6fe 3168 #define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEEDR12_0
mbed_official 340:28d1f895c6fe 3169 #define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEEDR12_1
mbed_official 340:28d1f895c6fe 3170 #define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEEDR13
mbed_official 340:28d1f895c6fe 3171 #define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEEDR13_0
mbed_official 340:28d1f895c6fe 3172 #define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEEDR13_1
mbed_official 340:28d1f895c6fe 3173 #define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEEDR14
mbed_official 340:28d1f895c6fe 3174 #define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEEDR14_0
mbed_official 340:28d1f895c6fe 3175 #define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEEDR14_1
mbed_official 340:28d1f895c6fe 3176 #define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEEDR15
mbed_official 340:28d1f895c6fe 3177 #define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEEDR15_0
mbed_official 340:28d1f895c6fe 3178 #define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEEDR15_1
mbed_official 340:28d1f895c6fe 3179
mbed_official 340:28d1f895c6fe 3180 /******************* Bit definition for GPIO_PUPDR register ******************/
mbed_official 340:28d1f895c6fe 3181 #define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
mbed_official 340:28d1f895c6fe 3182 #define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
mbed_official 340:28d1f895c6fe 3183 #define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
mbed_official 340:28d1f895c6fe 3184 #define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
mbed_official 340:28d1f895c6fe 3185 #define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
mbed_official 340:28d1f895c6fe 3186 #define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
mbed_official 340:28d1f895c6fe 3187 #define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
mbed_official 340:28d1f895c6fe 3188 #define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
mbed_official 340:28d1f895c6fe 3189 #define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
mbed_official 340:28d1f895c6fe 3190 #define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
mbed_official 340:28d1f895c6fe 3191 #define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
mbed_official 340:28d1f895c6fe 3192 #define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
mbed_official 340:28d1f895c6fe 3193 #define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
mbed_official 340:28d1f895c6fe 3194 #define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
mbed_official 340:28d1f895c6fe 3195 #define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
mbed_official 340:28d1f895c6fe 3196 #define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
mbed_official 340:28d1f895c6fe 3197 #define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
mbed_official 340:28d1f895c6fe 3198 #define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
mbed_official 340:28d1f895c6fe 3199 #define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
mbed_official 340:28d1f895c6fe 3200 #define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
mbed_official 340:28d1f895c6fe 3201 #define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
mbed_official 340:28d1f895c6fe 3202 #define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
mbed_official 340:28d1f895c6fe 3203 #define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
mbed_official 340:28d1f895c6fe 3204 #define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
mbed_official 340:28d1f895c6fe 3205 #define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
mbed_official 340:28d1f895c6fe 3206 #define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
mbed_official 340:28d1f895c6fe 3207 #define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
mbed_official 340:28d1f895c6fe 3208 #define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
mbed_official 340:28d1f895c6fe 3209 #define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
mbed_official 340:28d1f895c6fe 3210 #define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
mbed_official 340:28d1f895c6fe 3211 #define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
mbed_official 340:28d1f895c6fe 3212 #define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
mbed_official 340:28d1f895c6fe 3213 #define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
mbed_official 340:28d1f895c6fe 3214 #define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
mbed_official 340:28d1f895c6fe 3215 #define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
mbed_official 340:28d1f895c6fe 3216 #define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
mbed_official 340:28d1f895c6fe 3217 #define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
mbed_official 340:28d1f895c6fe 3218 #define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
mbed_official 340:28d1f895c6fe 3219 #define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
mbed_official 340:28d1f895c6fe 3220 #define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
mbed_official 340:28d1f895c6fe 3221 #define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
mbed_official 340:28d1f895c6fe 3222 #define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
mbed_official 340:28d1f895c6fe 3223 #define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
mbed_official 340:28d1f895c6fe 3224 #define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
mbed_official 340:28d1f895c6fe 3225 #define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
mbed_official 340:28d1f895c6fe 3226 #define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
mbed_official 340:28d1f895c6fe 3227 #define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
mbed_official 340:28d1f895c6fe 3228 #define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
mbed_official 340:28d1f895c6fe 3229
mbed_official 340:28d1f895c6fe 3230 /******************* Bit definition for GPIO_IDR register *******************/
mbed_official 340:28d1f895c6fe 3231 #define GPIO_IDR_0 ((uint32_t)0x00000001)
mbed_official 340:28d1f895c6fe 3232 #define GPIO_IDR_1 ((uint32_t)0x00000002)
mbed_official 340:28d1f895c6fe 3233 #define GPIO_IDR_2 ((uint32_t)0x00000004)
mbed_official 340:28d1f895c6fe 3234 #define GPIO_IDR_3 ((uint32_t)0x00000008)
mbed_official 340:28d1f895c6fe 3235 #define GPIO_IDR_4 ((uint32_t)0x00000010)
mbed_official 340:28d1f895c6fe 3236 #define GPIO_IDR_5 ((uint32_t)0x00000020)
mbed_official 340:28d1f895c6fe 3237 #define GPIO_IDR_6 ((uint32_t)0x00000040)
mbed_official 340:28d1f895c6fe 3238 #define GPIO_IDR_7 ((uint32_t)0x00000080)
mbed_official 340:28d1f895c6fe 3239 #define GPIO_IDR_8 ((uint32_t)0x00000100)
mbed_official 340:28d1f895c6fe 3240 #define GPIO_IDR_9 ((uint32_t)0x00000200)
mbed_official 340:28d1f895c6fe 3241 #define GPIO_IDR_10 ((uint32_t)0x00000400)
mbed_official 340:28d1f895c6fe 3242 #define GPIO_IDR_11 ((uint32_t)0x00000800)
mbed_official 340:28d1f895c6fe 3243 #define GPIO_IDR_12 ((uint32_t)0x00001000)
mbed_official 340:28d1f895c6fe 3244 #define GPIO_IDR_13 ((uint32_t)0x00002000)
mbed_official 340:28d1f895c6fe 3245 #define GPIO_IDR_14 ((uint32_t)0x00004000)
mbed_official 340:28d1f895c6fe 3246 #define GPIO_IDR_15 ((uint32_t)0x00008000)
mbed_official 340:28d1f895c6fe 3247
mbed_official 340:28d1f895c6fe 3248 /****************** Bit definition for GPIO_ODR register ********************/
mbed_official 340:28d1f895c6fe 3249 #define GPIO_ODR_0 ((uint32_t)0x00000001)
mbed_official 340:28d1f895c6fe 3250 #define GPIO_ODR_1 ((uint32_t)0x00000002)
mbed_official 340:28d1f895c6fe 3251 #define GPIO_ODR_2 ((uint32_t)0x00000004)
mbed_official 340:28d1f895c6fe 3252 #define GPIO_ODR_3 ((uint32_t)0x00000008)
mbed_official 340:28d1f895c6fe 3253 #define GPIO_ODR_4 ((uint32_t)0x00000010)
mbed_official 340:28d1f895c6fe 3254 #define GPIO_ODR_5 ((uint32_t)0x00000020)
mbed_official 340:28d1f895c6fe 3255 #define GPIO_ODR_6 ((uint32_t)0x00000040)
mbed_official 340:28d1f895c6fe 3256 #define GPIO_ODR_7 ((uint32_t)0x00000080)
mbed_official 340:28d1f895c6fe 3257 #define GPIO_ODR_8 ((uint32_t)0x00000100)
mbed_official 340:28d1f895c6fe 3258 #define GPIO_ODR_9 ((uint32_t)0x00000200)
mbed_official 340:28d1f895c6fe 3259 #define GPIO_ODR_10 ((uint32_t)0x00000400)
mbed_official 340:28d1f895c6fe 3260 #define GPIO_ODR_11 ((uint32_t)0x00000800)
mbed_official 340:28d1f895c6fe 3261 #define GPIO_ODR_12 ((uint32_t)0x00001000)
mbed_official 340:28d1f895c6fe 3262 #define GPIO_ODR_13 ((uint32_t)0x00002000)
mbed_official 340:28d1f895c6fe 3263 #define GPIO_ODR_14 ((uint32_t)0x00004000)
mbed_official 340:28d1f895c6fe 3264 #define GPIO_ODR_15 ((uint32_t)0x00008000)
mbed_official 340:28d1f895c6fe 3265
mbed_official 340:28d1f895c6fe 3266 /****************** Bit definition for GPIO_BSRR register ********************/
mbed_official 340:28d1f895c6fe 3267 #define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
mbed_official 340:28d1f895c6fe 3268 #define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
mbed_official 340:28d1f895c6fe 3269 #define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
mbed_official 340:28d1f895c6fe 3270 #define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
mbed_official 340:28d1f895c6fe 3271 #define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
mbed_official 340:28d1f895c6fe 3272 #define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
mbed_official 340:28d1f895c6fe 3273 #define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
mbed_official 340:28d1f895c6fe 3274 #define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
mbed_official 340:28d1f895c6fe 3275 #define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
mbed_official 340:28d1f895c6fe 3276 #define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
mbed_official 340:28d1f895c6fe 3277 #define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
mbed_official 340:28d1f895c6fe 3278 #define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
mbed_official 340:28d1f895c6fe 3279 #define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
mbed_official 340:28d1f895c6fe 3280 #define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
mbed_official 340:28d1f895c6fe 3281 #define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
mbed_official 340:28d1f895c6fe 3282 #define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
mbed_official 340:28d1f895c6fe 3283 #define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
mbed_official 340:28d1f895c6fe 3284 #define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
mbed_official 340:28d1f895c6fe 3285 #define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
mbed_official 340:28d1f895c6fe 3286 #define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
mbed_official 340:28d1f895c6fe 3287 #define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
mbed_official 340:28d1f895c6fe 3288 #define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
mbed_official 340:28d1f895c6fe 3289 #define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
mbed_official 340:28d1f895c6fe 3290 #define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
mbed_official 340:28d1f895c6fe 3291 #define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
mbed_official 340:28d1f895c6fe 3292 #define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
mbed_official 340:28d1f895c6fe 3293 #define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
mbed_official 340:28d1f895c6fe 3294 #define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
mbed_official 340:28d1f895c6fe 3295 #define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
mbed_official 340:28d1f895c6fe 3296 #define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
mbed_official 340:28d1f895c6fe 3297 #define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
mbed_official 340:28d1f895c6fe 3298 #define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
mbed_official 340:28d1f895c6fe 3299
mbed_official 340:28d1f895c6fe 3300 /****************** Bit definition for GPIO_LCKR register ********************/
mbed_official 340:28d1f895c6fe 3301 #define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
mbed_official 340:28d1f895c6fe 3302 #define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
mbed_official 340:28d1f895c6fe 3303 #define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
mbed_official 340:28d1f895c6fe 3304 #define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
mbed_official 340:28d1f895c6fe 3305 #define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
mbed_official 340:28d1f895c6fe 3306 #define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
mbed_official 340:28d1f895c6fe 3307 #define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
mbed_official 340:28d1f895c6fe 3308 #define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
mbed_official 340:28d1f895c6fe 3309 #define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
mbed_official 340:28d1f895c6fe 3310 #define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
mbed_official 340:28d1f895c6fe 3311 #define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
mbed_official 340:28d1f895c6fe 3312 #define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
mbed_official 340:28d1f895c6fe 3313 #define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
mbed_official 340:28d1f895c6fe 3314 #define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
mbed_official 340:28d1f895c6fe 3315 #define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
mbed_official 340:28d1f895c6fe 3316 #define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
mbed_official 340:28d1f895c6fe 3317 #define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
mbed_official 340:28d1f895c6fe 3318
mbed_official 340:28d1f895c6fe 3319 /****************** Bit definition for GPIO_AFRL register ********************/
mbed_official 340:28d1f895c6fe 3320 #define GPIO_AFRL_AFRL0 ((uint32_t)0x0000000F)
mbed_official 340:28d1f895c6fe 3321 #define GPIO_AFRL_AFRL1 ((uint32_t)0x000000F0)
mbed_official 340:28d1f895c6fe 3322 #define GPIO_AFRL_AFRL2 ((uint32_t)0x00000F00)
mbed_official 340:28d1f895c6fe 3323 #define GPIO_AFRL_AFRL3 ((uint32_t)0x0000F000)
mbed_official 340:28d1f895c6fe 3324 #define GPIO_AFRL_AFRL4 ((uint32_t)0x000F0000)
mbed_official 340:28d1f895c6fe 3325 #define GPIO_AFRL_AFRL5 ((uint32_t)0x00F00000)
mbed_official 340:28d1f895c6fe 3326 #define GPIO_AFRL_AFRL6 ((uint32_t)0x0F000000)
mbed_official 340:28d1f895c6fe 3327 #define GPIO_AFRL_AFRL7 ((uint32_t)0xF0000000)
mbed_official 340:28d1f895c6fe 3328
mbed_official 340:28d1f895c6fe 3329 /****************** Bit definition for GPIO_AFRH register ********************/
mbed_official 340:28d1f895c6fe 3330 #define GPIO_AFRH_AFRH0 ((uint32_t)0x0000000F)
mbed_official 340:28d1f895c6fe 3331 #define GPIO_AFRH_AFRH1 ((uint32_t)0x000000F0)
mbed_official 340:28d1f895c6fe 3332 #define GPIO_AFRH_AFRH2 ((uint32_t)0x00000F00)
mbed_official 340:28d1f895c6fe 3333 #define GPIO_AFRH_AFRH3 ((uint32_t)0x0000F000)
mbed_official 340:28d1f895c6fe 3334 #define GPIO_AFRH_AFRH4 ((uint32_t)0x000F0000)
mbed_official 340:28d1f895c6fe 3335 #define GPIO_AFRH_AFRH5 ((uint32_t)0x00F00000)
mbed_official 340:28d1f895c6fe 3336 #define GPIO_AFRH_AFRH6 ((uint32_t)0x0F000000)
mbed_official 340:28d1f895c6fe 3337 #define GPIO_AFRH_AFRH7 ((uint32_t)0xF0000000)
mbed_official 340:28d1f895c6fe 3338
mbed_official 340:28d1f895c6fe 3339 /****************** Bit definition for GPIO_BRR register *********************/
mbed_official 340:28d1f895c6fe 3340 #define GPIO_BRR_BR_0 ((uint32_t)0x00000001)
mbed_official 340:28d1f895c6fe 3341 #define GPIO_BRR_BR_1 ((uint32_t)0x00000002)
mbed_official 340:28d1f895c6fe 3342 #define GPIO_BRR_BR_2 ((uint32_t)0x00000004)
mbed_official 340:28d1f895c6fe 3343 #define GPIO_BRR_BR_3 ((uint32_t)0x00000008)
mbed_official 340:28d1f895c6fe 3344 #define GPIO_BRR_BR_4 ((uint32_t)0x00000010)
mbed_official 340:28d1f895c6fe 3345 #define GPIO_BRR_BR_5 ((uint32_t)0x00000020)
mbed_official 340:28d1f895c6fe 3346 #define GPIO_BRR_BR_6 ((uint32_t)0x00000040)
mbed_official 340:28d1f895c6fe 3347 #define GPIO_BRR_BR_7 ((uint32_t)0x00000080)
mbed_official 340:28d1f895c6fe 3348 #define GPIO_BRR_BR_8 ((uint32_t)0x00000100)
mbed_official 340:28d1f895c6fe 3349 #define GPIO_BRR_BR_9 ((uint32_t)0x00000200)
mbed_official 340:28d1f895c6fe 3350 #define GPIO_BRR_BR_10 ((uint32_t)0x00000400)
mbed_official 340:28d1f895c6fe 3351 #define GPIO_BRR_BR_11 ((uint32_t)0x00000800)
mbed_official 340:28d1f895c6fe 3352 #define GPIO_BRR_BR_12 ((uint32_t)0x00001000)
mbed_official 340:28d1f895c6fe 3353 #define GPIO_BRR_BR_13 ((uint32_t)0x00002000)
mbed_official 340:28d1f895c6fe 3354 #define GPIO_BRR_BR_14 ((uint32_t)0x00004000)
mbed_official 340:28d1f895c6fe 3355 #define GPIO_BRR_BR_15 ((uint32_t)0x00008000)
mbed_official 340:28d1f895c6fe 3356
mbed_official 340:28d1f895c6fe 3357 /******************************************************************************/
mbed_official 340:28d1f895c6fe 3358 /* */
mbed_official 340:28d1f895c6fe 3359 /* Inter-integrated Circuit Interface (I2C) */
mbed_official 340:28d1f895c6fe 3360 /* */
mbed_official 340:28d1f895c6fe 3361 /******************************************************************************/
mbed_official 340:28d1f895c6fe 3362
mbed_official 340:28d1f895c6fe 3363 /******************* Bit definition for I2C_CR1 register *******************/
mbed_official 340:28d1f895c6fe 3364 #define I2C_CR1_PE ((uint32_t)0x00000001) /*!< Peripheral enable */
mbed_official 340:28d1f895c6fe 3365 #define I2C_CR1_TXIE ((uint32_t)0x00000002) /*!< TX interrupt enable */
mbed_official 340:28d1f895c6fe 3366 #define I2C_CR1_RXIE ((uint32_t)0x00000004) /*!< RX interrupt enable */
mbed_official 340:28d1f895c6fe 3367 #define I2C_CR1_ADDRIE ((uint32_t)0x00000008) /*!< Address match interrupt enable */
mbed_official 340:28d1f895c6fe 3368 #define I2C_CR1_NACKIE ((uint32_t)0x00000010) /*!< NACK received interrupt enable */
mbed_official 340:28d1f895c6fe 3369 #define I2C_CR1_STOPIE ((uint32_t)0x00000020) /*!< STOP detection interrupt enable */
mbed_official 340:28d1f895c6fe 3370 #define I2C_CR1_TCIE ((uint32_t)0x00000040) /*!< Transfer complete interrupt enable */
mbed_official 340:28d1f895c6fe 3371 #define I2C_CR1_ERRIE ((uint32_t)0x00000080) /*!< Errors interrupt enable */
mbed_official 340:28d1f895c6fe 3372 #define I2C_CR1_DFN ((uint32_t)0x00000F00) /*!< Digital noise filter */
mbed_official 340:28d1f895c6fe 3373 #define I2C_CR1_ANFOFF ((uint32_t)0x00001000) /*!< Analog noise filter OFF */
mbed_official 340:28d1f895c6fe 3374 #define I2C_CR1_SWRST ((uint32_t)0x00002000) /*!< Software reset */
mbed_official 340:28d1f895c6fe 3375 #define I2C_CR1_TXDMAEN ((uint32_t)0x00004000) /*!< DMA transmission requests enable */
mbed_official 340:28d1f895c6fe 3376 #define I2C_CR1_RXDMAEN ((uint32_t)0x00008000) /*!< DMA reception requests enable */
mbed_official 340:28d1f895c6fe 3377 #define I2C_CR1_SBC ((uint32_t)0x00010000) /*!< Slave byte control */
mbed_official 340:28d1f895c6fe 3378 #define I2C_CR1_NOSTRETCH ((uint32_t)0x00020000) /*!< Clock stretching disable */
mbed_official 340:28d1f895c6fe 3379 #define I2C_CR1_WUPEN ((uint32_t)0x00040000) /*!< Wakeup from STOP enable */
mbed_official 340:28d1f895c6fe 3380 #define I2C_CR1_GCEN ((uint32_t)0x00080000) /*!< General call enable */
mbed_official 340:28d1f895c6fe 3381 #define I2C_CR1_SMBHEN ((uint32_t)0x00100000) /*!< SMBus host address enable */
mbed_official 340:28d1f895c6fe 3382 #define I2C_CR1_SMBDEN ((uint32_t)0x00200000) /*!< SMBus device default address enable */
mbed_official 340:28d1f895c6fe 3383 #define I2C_CR1_ALERTEN ((uint32_t)0x00400000) /*!< SMBus alert enable */
mbed_official 340:28d1f895c6fe 3384 #define I2C_CR1_PECEN ((uint32_t)0x00800000) /*!< PEC enable */
mbed_official 340:28d1f895c6fe 3385
mbed_official 340:28d1f895c6fe 3386 /****************** Bit definition for I2C_CR2 register ********************/
mbed_official 340:28d1f895c6fe 3387 #define I2C_CR2_SADD ((uint32_t)0x000003FF) /*!< Slave address (master mode) */
mbed_official 340:28d1f895c6fe 3388 #define I2C_CR2_RD_WRN ((uint32_t)0x00000400) /*!< Transfer direction (master mode) */
mbed_official 340:28d1f895c6fe 3389 #define I2C_CR2_ADD10 ((uint32_t)0x00000800) /*!< 10-bit addressing mode (master mode) */
mbed_official 340:28d1f895c6fe 3390 #define I2C_CR2_HEAD10R ((uint32_t)0x00001000) /*!< 10-bit address header only read direction (master mode) */
mbed_official 340:28d1f895c6fe 3391 #define I2C_CR2_START ((uint32_t)0x00002000) /*!< START generation */
mbed_official 340:28d1f895c6fe 3392 #define I2C_CR2_STOP ((uint32_t)0x00004000) /*!< STOP generation (master mode) */
mbed_official 340:28d1f895c6fe 3393 #define I2C_CR2_NACK ((uint32_t)0x00008000) /*!< NACK generation (slave mode) */
mbed_official 340:28d1f895c6fe 3394 #define I2C_CR2_NBYTES ((uint32_t)0x00FF0000) /*!< Number of bytes */
mbed_official 340:28d1f895c6fe 3395 #define I2C_CR2_RELOAD ((uint32_t)0x01000000) /*!< NBYTES reload mode */
mbed_official 340:28d1f895c6fe 3396 #define I2C_CR2_AUTOEND ((uint32_t)0x02000000) /*!< Automatic end mode (master mode) */
mbed_official 340:28d1f895c6fe 3397 #define I2C_CR2_PECBYTE ((uint32_t)0x04000000) /*!< Packet error checking byte */
mbed_official 340:28d1f895c6fe 3398
mbed_official 340:28d1f895c6fe 3399 /******************* Bit definition for I2C_OAR1 register ******************/
mbed_official 340:28d1f895c6fe 3400 #define I2C_OAR1_OA1 ((uint32_t)0x000003FF) /*!< Interface own address 1 */
mbed_official 340:28d1f895c6fe 3401 #define I2C_OAR1_OA1MODE ((uint32_t)0x00000400) /*!< Own address 1 10-bit mode */
mbed_official 340:28d1f895c6fe 3402 #define I2C_OAR1_OA1EN ((uint32_t)0x00008000) /*!< Own address 1 enable */
mbed_official 340:28d1f895c6fe 3403
mbed_official 340:28d1f895c6fe 3404 /******************* Bit definition for I2C_OAR2 register ******************/
mbed_official 340:28d1f895c6fe 3405 #define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /*!< Interface own address 2 */
mbed_official 340:28d1f895c6fe 3406 #define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /*!< Own address 2 masks */
mbed_official 340:28d1f895c6fe 3407 #define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /*!< Own address 2 enable */
mbed_official 340:28d1f895c6fe 3408
mbed_official 340:28d1f895c6fe 3409 /******************* Bit definition for I2C_TIMINGR register ****************/
mbed_official 340:28d1f895c6fe 3410 #define I2C_TIMINGR_SCLL ((uint32_t)0x000000FF) /*!< SCL low period (master mode) */
mbed_official 340:28d1f895c6fe 3411 #define I2C_TIMINGR_SCLH ((uint32_t)0x0000FF00) /*!< SCL high period (master mode) */
mbed_official 340:28d1f895c6fe 3412 #define I2C_TIMINGR_SDADEL ((uint32_t)0x000F0000) /*!< Data hold time */
mbed_official 340:28d1f895c6fe 3413 #define I2C_TIMINGR_SCLDEL ((uint32_t)0x00F00000) /*!< Data setup time */
mbed_official 340:28d1f895c6fe 3414 #define I2C_TIMINGR_PRESC ((uint32_t)0xF0000000) /*!< Timings prescaler */
mbed_official 340:28d1f895c6fe 3415
mbed_official 340:28d1f895c6fe 3416 /******************* Bit definition for I2C_TIMEOUTR register ****************/
mbed_official 340:28d1f895c6fe 3417 #define I2C_TIMEOUTR_TIMEOUTA ((uint32_t)0x00000FFF) /*!< Bus timeout A */
mbed_official 340:28d1f895c6fe 3418 #define I2C_TIMEOUTR_TIDLE ((uint32_t)0x00001000) /*!< Idle clock timeout detection */
mbed_official 340:28d1f895c6fe 3419 #define I2C_TIMEOUTR_TIMOUTEN ((uint32_t)0x00008000) /*!< Clock timeout enable */
mbed_official 340:28d1f895c6fe 3420 #define I2C_TIMEOUTR_TIMEOUTB ((uint32_t)0x0FFF0000) /*!< Bus timeout B*/
mbed_official 340:28d1f895c6fe 3421 #define I2C_TIMEOUTR_TEXTEN ((uint32_t)0x80000000) /*!< Extended clock timeout enable */
mbed_official 340:28d1f895c6fe 3422
mbed_official 340:28d1f895c6fe 3423 /****************** Bit definition for I2C_ISR register ********************/
mbed_official 340:28d1f895c6fe 3424 #define I2C_ISR_TXE ((uint32_t)0x00000001) /*!< Transmit data register empty */
mbed_official 340:28d1f895c6fe 3425 #define I2C_ISR_TXIS ((uint32_t)0x00000002) /*!< Transmit interrupt status */
mbed_official 340:28d1f895c6fe 3426 #define I2C_ISR_RXNE ((uint32_t)0x00000004) /*!< Receive data register not empty */
mbed_official 340:28d1f895c6fe 3427 #define I2C_ISR_ADDR ((uint32_t)0x00000008) /*!< Address matched (slave mode)*/
mbed_official 340:28d1f895c6fe 3428 #define I2C_ISR_NACKF ((uint32_t)0x00000010) /*!< NACK received flag */
mbed_official 340:28d1f895c6fe 3429 #define I2C_ISR_STOPF ((uint32_t)0x00000020) /*!< STOP detection flag */
mbed_official 340:28d1f895c6fe 3430 #define I2C_ISR_TC ((uint32_t)0x00000040) /*!< Transfer complete (master mode) */
mbed_official 340:28d1f895c6fe 3431 #define I2C_ISR_TCR ((uint32_t)0x00000080) /*!< Transfer complete reload */
mbed_official 340:28d1f895c6fe 3432 #define I2C_ISR_BERR ((uint32_t)0x00000100) /*!< Bus error */
mbed_official 340:28d1f895c6fe 3433 #define I2C_ISR_ARLO ((uint32_t)0x00000200) /*!< Arbitration lost */
mbed_official 340:28d1f895c6fe 3434 #define I2C_ISR_OVR ((uint32_t)0x00000400) /*!< Overrun/Underrun */
mbed_official 340:28d1f895c6fe 3435 #define I2C_ISR_PECERR ((uint32_t)0x00000800) /*!< PEC error in reception */
mbed_official 340:28d1f895c6fe 3436 #define I2C_ISR_TIMEOUT ((uint32_t)0x00001000) /*!< Timeout or Tlow detection flag */
mbed_official 340:28d1f895c6fe 3437 #define I2C_ISR_ALERT ((uint32_t)0x00002000) /*!< SMBus alert */
mbed_official 340:28d1f895c6fe 3438 #define I2C_ISR_BUSY ((uint32_t)0x00008000) /*!< Bus busy */
mbed_official 340:28d1f895c6fe 3439 #define I2C_ISR_DIR ((uint32_t)0x00010000) /*!< Transfer direction (slave mode) */
mbed_official 340:28d1f895c6fe 3440 #define I2C_ISR_ADDCODE ((uint32_t)0x00FE0000) /*!< Address match code (slave mode) */
mbed_official 340:28d1f895c6fe 3441
mbed_official 340:28d1f895c6fe 3442 /****************** Bit definition for I2C_ICR register ********************/
mbed_official 340:28d1f895c6fe 3443 #define I2C_ICR_ADDRCF ((uint32_t)0x00000008) /*!< Address matched clear flag */
mbed_official 340:28d1f895c6fe 3444 #define I2C_ICR_NACKCF ((uint32_t)0x00000010) /*!< NACK clear flag */
mbed_official 340:28d1f895c6fe 3445 #define I2C_ICR_STOPCF ((uint32_t)0x00000020) /*!< STOP detection clear flag */
mbed_official 340:28d1f895c6fe 3446 #define I2C_ICR_BERRCF ((uint32_t)0x00000100) /*!< Bus error clear flag */
mbed_official 340:28d1f895c6fe 3447 #define I2C_ICR_ARLOCF ((uint32_t)0x00000200) /*!< Arbitration lost clear flag */
mbed_official 340:28d1f895c6fe 3448 #define I2C_ICR_OVRCF ((uint32_t)0x00000400) /*!< Overrun/Underrun clear flag */
mbed_official 340:28d1f895c6fe 3449 #define I2C_ICR_PECCF ((uint32_t)0x00000800) /*!< PAC error clear flag */
mbed_official 340:28d1f895c6fe 3450 #define I2C_ICR_TIMOUTCF ((uint32_t)0x00001000) /*!< Timeout clear flag */
mbed_official 340:28d1f895c6fe 3451 #define I2C_ICR_ALERTCF ((uint32_t)0x00002000) /*!< Alert clear flag */
mbed_official 340:28d1f895c6fe 3452
mbed_official 340:28d1f895c6fe 3453 /****************** Bit definition for I2C_PECR register *******************/
mbed_official 340:28d1f895c6fe 3454 #define I2C_PECR_PEC ((uint32_t)0x000000FF) /*!< PEC register */
mbed_official 340:28d1f895c6fe 3455
mbed_official 340:28d1f895c6fe 3456 /****************** Bit definition for I2C_RXDR register *********************/
mbed_official 340:28d1f895c6fe 3457 #define I2C_RXDR_RXDATA ((uint32_t)0x000000FF) /*!< 8-bit receive data */
mbed_official 340:28d1f895c6fe 3458
mbed_official 340:28d1f895c6fe 3459 /****************** Bit definition for I2C_TXDR register *******************/
mbed_official 340:28d1f895c6fe 3460 #define I2C_TXDR_TXDATA ((uint32_t)0x000000FF) /*!< 8-bit transmit data */
mbed_official 340:28d1f895c6fe 3461
mbed_official 340:28d1f895c6fe 3462 /*****************************************************************************/
mbed_official 340:28d1f895c6fe 3463 /* */
mbed_official 340:28d1f895c6fe 3464 /* Independent WATCHDOG (IWDG) */
mbed_official 340:28d1f895c6fe 3465 /* */
mbed_official 340:28d1f895c6fe 3466 /*****************************************************************************/
mbed_official 340:28d1f895c6fe 3467 /******************* Bit definition for IWDG_KR register *******************/
mbed_official 340:28d1f895c6fe 3468 #define IWDG_KR_KEY ((uint32_t)0xFFFF) /*!< Key value (write only, read 0000h) */
mbed_official 340:28d1f895c6fe 3469
mbed_official 340:28d1f895c6fe 3470 /******************* Bit definition for IWDG_PR register *******************/
mbed_official 340:28d1f895c6fe 3471 #define IWDG_PR_PR ((uint32_t)0x07) /*!< PR[2:0] (Prescaler divider) */
mbed_official 340:28d1f895c6fe 3472 #define IWDG_PR_PR_0 ((uint32_t)0x01) /*!< Bit 0 */
mbed_official 340:28d1f895c6fe 3473 #define IWDG_PR_PR_1 ((uint32_t)0x02) /*!< Bit 1 */
mbed_official 340:28d1f895c6fe 3474 #define IWDG_PR_PR_2 ((uint32_t)0x04) /*!< Bit 2 */
mbed_official 340:28d1f895c6fe 3475
mbed_official 340:28d1f895c6fe 3476 /******************* Bit definition for IWDG_RLR register ******************/
mbed_official 340:28d1f895c6fe 3477 #define IWDG_RLR_RL ((uint32_t)0x0FFF) /*!< Watchdog counter reload value */
mbed_official 340:28d1f895c6fe 3478
mbed_official 340:28d1f895c6fe 3479 /******************* Bit definition for IWDG_SR register *******************/
mbed_official 340:28d1f895c6fe 3480 #define IWDG_SR_PVU ((uint32_t)0x01) /*!< Watchdog prescaler value update */
mbed_official 340:28d1f895c6fe 3481 #define IWDG_SR_RVU ((uint32_t)0x02) /*!< Watchdog counter reload value update */
mbed_official 340:28d1f895c6fe 3482 #define IWDG_SR_WVU ((uint32_t)0x04) /*!< Watchdog counter window value update */
mbed_official 340:28d1f895c6fe 3483
mbed_official 340:28d1f895c6fe 3484 /******************* Bit definition for IWDG_KR register *******************/
mbed_official 340:28d1f895c6fe 3485 #define IWDG_WINR_WIN ((uint32_t)0x0FFF) /*!< Watchdog counter window value */
mbed_official 340:28d1f895c6fe 3486
mbed_official 340:28d1f895c6fe 3487 /*****************************************************************************/
mbed_official 340:28d1f895c6fe 3488 /* */
mbed_official 340:28d1f895c6fe 3489 /* Power Control (PWR) */
mbed_official 340:28d1f895c6fe 3490 /* */
mbed_official 340:28d1f895c6fe 3491 /*****************************************************************************/
mbed_official 340:28d1f895c6fe 3492
mbed_official 340:28d1f895c6fe 3493 /******************** Bit definition for PWR_CR register *******************/
mbed_official 340:28d1f895c6fe 3494 #define PWR_CR_LPDS ((uint32_t)0x00000001) /*!< Low-power Deepsleep */
mbed_official 340:28d1f895c6fe 3495 #define PWR_CR_PDDS ((uint32_t)0x00000002) /*!< Power Down Deepsleep */
mbed_official 340:28d1f895c6fe 3496 #define PWR_CR_CWUF ((uint32_t)0x00000004) /*!< Clear Wakeup Flag */
mbed_official 340:28d1f895c6fe 3497 #define PWR_CR_CSBF ((uint32_t)0x00000008) /*!< Clear Standby Flag */
mbed_official 340:28d1f895c6fe 3498 #define PWR_CR_PVDE ((uint32_t)0x00000010) /*!< Power Voltage Detector Enable */
mbed_official 340:28d1f895c6fe 3499
mbed_official 340:28d1f895c6fe 3500 #define PWR_CR_PLS ((uint32_t)0x000000E0) /*!< PLS[2:0] bits (PVD Level Selection) */
mbed_official 340:28d1f895c6fe 3501 #define PWR_CR_PLS_0 ((uint32_t)0x00000020) /*!< Bit 0 */
mbed_official 340:28d1f895c6fe 3502 #define PWR_CR_PLS_1 ((uint32_t)0x00000040) /*!< Bit 1 */
mbed_official 340:28d1f895c6fe 3503 #define PWR_CR_PLS_2 ((uint32_t)0x00000080) /*!< Bit 2 */
mbed_official 340:28d1f895c6fe 3504
mbed_official 340:28d1f895c6fe 3505 /*!< PVD level configuration */
mbed_official 340:28d1f895c6fe 3506 #define PWR_CR_PLS_LEV0 ((uint32_t)0x00000000) /*!< PVD level 0 */
mbed_official 340:28d1f895c6fe 3507 #define PWR_CR_PLS_LEV1 ((uint32_t)0x00000020) /*!< PVD level 1 */
mbed_official 340:28d1f895c6fe 3508 #define PWR_CR_PLS_LEV2 ((uint32_t)0x00000040) /*!< PVD level 2 */
mbed_official 340:28d1f895c6fe 3509 #define PWR_CR_PLS_LEV3 ((uint32_t)0x00000060) /*!< PVD level 3 */
mbed_official 340:28d1f895c6fe 3510 #define PWR_CR_PLS_LEV4 ((uint32_t)0x00000080) /*!< PVD level 4 */
mbed_official 340:28d1f895c6fe 3511 #define PWR_CR_PLS_LEV5 ((uint32_t)0x000000A0) /*!< PVD level 5 */
mbed_official 340:28d1f895c6fe 3512 #define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0) /*!< PVD level 6 */
mbed_official 340:28d1f895c6fe 3513 #define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0) /*!< PVD level 7 */
mbed_official 340:28d1f895c6fe 3514
mbed_official 340:28d1f895c6fe 3515 #define PWR_CR_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */
mbed_official 340:28d1f895c6fe 3516
mbed_official 340:28d1f895c6fe 3517 /******************* Bit definition for PWR_CSR register *******************/
mbed_official 340:28d1f895c6fe 3518 #define PWR_CSR_WUF ((uint32_t)0x00000001) /*!< Wakeup Flag */
mbed_official 340:28d1f895c6fe 3519 #define PWR_CSR_SBF ((uint32_t)0x00000002) /*!< Standby Flag */
mbed_official 340:28d1f895c6fe 3520 #define PWR_CSR_PVDO ((uint32_t)0x00000004) /*!< PVD Output */
mbed_official 340:28d1f895c6fe 3521 #define PWR_CSR_VREFINTRDYF ((uint32_t)0x00000008) /*!< Internal voltage reference (VREFINT) ready flag */
mbed_official 340:28d1f895c6fe 3522
mbed_official 340:28d1f895c6fe 3523 #define PWR_CSR_EWUP1 ((uint32_t)0x00000100) /*!< Enable WKUP pin 1 */
mbed_official 340:28d1f895c6fe 3524 #define PWR_CSR_EWUP2 ((uint32_t)0x00000200) /*!< Enable WKUP pin 2 */
mbed_official 340:28d1f895c6fe 3525 #define PWR_CSR_EWUP3 ((uint32_t)0x00000400) /*!< Enable WKUP pin 3 */
mbed_official 340:28d1f895c6fe 3526 #define PWR_CSR_EWUP4 ((uint32_t)0x00000800) /*!< Enable WKUP pin 4 */
mbed_official 340:28d1f895c6fe 3527 #define PWR_CSR_EWUP5 ((uint32_t)0x00001000) /*!< Enable WKUP pin 5 */
mbed_official 340:28d1f895c6fe 3528 #define PWR_CSR_EWUP6 ((uint32_t)0x00002000) /*!< Enable WKUP pin 6 */
mbed_official 340:28d1f895c6fe 3529 #define PWR_CSR_EWUP7 ((uint32_t)0x00004000) /*!< Enable WKUP pin 7 */
mbed_official 340:28d1f895c6fe 3530 #define PWR_CSR_EWUP8 ((uint32_t)0x00008000) /*!< Enable WKUP pin 8 */
mbed_official 340:28d1f895c6fe 3531
mbed_official 340:28d1f895c6fe 3532 /*****************************************************************************/
mbed_official 340:28d1f895c6fe 3533 /* */
mbed_official 340:28d1f895c6fe 3534 /* Reset and Clock Control */
mbed_official 340:28d1f895c6fe 3535 /* */
mbed_official 340:28d1f895c6fe 3536 /*****************************************************************************/
mbed_official 340:28d1f895c6fe 3537
mbed_official 340:28d1f895c6fe 3538 /******************** Bit definition for RCC_CR register *******************/
mbed_official 340:28d1f895c6fe 3539 #define RCC_CR_HSION ((uint32_t)0x00000001) /*!< Internal High Speed clock enable */
mbed_official 340:28d1f895c6fe 3540 #define RCC_CR_HSIRDY ((uint32_t)0x00000002) /*!< Internal High Speed clock ready flag */
mbed_official 340:28d1f895c6fe 3541
mbed_official 340:28d1f895c6fe 3542 #define RCC_CR_HSITRIM ((uint32_t)0x000000F8) /*!< Internal High Speed clock trimming */
mbed_official 340:28d1f895c6fe 3543 #define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008) /*!<Bit 0 */
mbed_official 340:28d1f895c6fe 3544 #define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010) /*!<Bit 1 */
mbed_official 340:28d1f895c6fe 3545 #define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020) /*!<Bit 2 */
mbed_official 340:28d1f895c6fe 3546 #define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040) /*!<Bit 3 */
mbed_official 340:28d1f895c6fe 3547 #define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080) /*!<Bit 4 */
mbed_official 340:28d1f895c6fe 3548
mbed_official 340:28d1f895c6fe 3549 #define RCC_CR_HSICAL ((uint32_t)0x0000FF00) /*!< Internal High Speed clock Calibration */
mbed_official 340:28d1f895c6fe 3550 #define RCC_CR_HSICAL_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 340:28d1f895c6fe 3551 #define RCC_CR_HSICAL_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 340:28d1f895c6fe 3552 #define RCC_CR_HSICAL_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 340:28d1f895c6fe 3553 #define RCC_CR_HSICAL_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 340:28d1f895c6fe 3554 #define RCC_CR_HSICAL_4 ((uint32_t)0x00001000) /*!<Bit 4 */
mbed_official 340:28d1f895c6fe 3555 #define RCC_CR_HSICAL_5 ((uint32_t)0x00002000) /*!<Bit 5 */
mbed_official 340:28d1f895c6fe 3556 #define RCC_CR_HSICAL_6 ((uint32_t)0x00004000) /*!<Bit 6 */
mbed_official 340:28d1f895c6fe 3557 #define RCC_CR_HSICAL_7 ((uint32_t)0x00008000) /*!<Bit 7 */
mbed_official 340:28d1f895c6fe 3558
mbed_official 340:28d1f895c6fe 3559 #define RCC_CR_HSEON ((uint32_t)0x00010000) /*!< External High Speed clock enable */
mbed_official 340:28d1f895c6fe 3560 #define RCC_CR_HSERDY ((uint32_t)0x00020000) /*!< External High Speed clock ready flag */
mbed_official 340:28d1f895c6fe 3561 #define RCC_CR_HSEBYP ((uint32_t)0x00040000) /*!< External High Speed clock Bypass */
mbed_official 340:28d1f895c6fe 3562 #define RCC_CR_CSSON ((uint32_t)0x00080000) /*!< Clock Security System enable */
mbed_official 340:28d1f895c6fe 3563 #define RCC_CR_PLLON ((uint32_t)0x01000000) /*!< PLL enable */
mbed_official 340:28d1f895c6fe 3564 #define RCC_CR_PLLRDY ((uint32_t)0x02000000) /*!< PLL clock ready flag */
mbed_official 340:28d1f895c6fe 3565
mbed_official 340:28d1f895c6fe 3566 /******************** Bit definition for RCC_CFGR register *****************/
mbed_official 340:28d1f895c6fe 3567 /*!< SW configuration */
mbed_official 340:28d1f895c6fe 3568 #define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
mbed_official 340:28d1f895c6fe 3569 #define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 340:28d1f895c6fe 3570 #define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 340:28d1f895c6fe 3571
mbed_official 340:28d1f895c6fe 3572 #define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
mbed_official 340:28d1f895c6fe 3573 #define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
mbed_official 340:28d1f895c6fe 3574 #define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
mbed_official 340:28d1f895c6fe 3575 #define RCC_CFGR_SW_HSI48 ((uint32_t)0x00000003) /*!< HSI48 selected as system clock */
mbed_official 340:28d1f895c6fe 3576
mbed_official 340:28d1f895c6fe 3577 /*!< SWS configuration */
mbed_official 340:28d1f895c6fe 3578 #define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
mbed_official 340:28d1f895c6fe 3579 #define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
mbed_official 340:28d1f895c6fe 3580 #define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
mbed_official 340:28d1f895c6fe 3581
mbed_official 340:28d1f895c6fe 3582 #define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
mbed_official 340:28d1f895c6fe 3583 #define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
mbed_official 340:28d1f895c6fe 3584 #define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
mbed_official 340:28d1f895c6fe 3585 #define RCC_CFGR_SWS_HSI48 ((uint32_t)0x0000000C) /*!< HSI48 oscillator used as system clock */
mbed_official 340:28d1f895c6fe 3586
mbed_official 340:28d1f895c6fe 3587 /*!< HPRE configuration */
mbed_official 340:28d1f895c6fe 3588 #define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
mbed_official 340:28d1f895c6fe 3589 #define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
mbed_official 340:28d1f895c6fe 3590 #define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
mbed_official 340:28d1f895c6fe 3591 #define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
mbed_official 340:28d1f895c6fe 3592 #define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
mbed_official 340:28d1f895c6fe 3593
mbed_official 340:28d1f895c6fe 3594 #define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
mbed_official 340:28d1f895c6fe 3595 #define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
mbed_official 340:28d1f895c6fe 3596 #define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
mbed_official 340:28d1f895c6fe 3597 #define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
mbed_official 340:28d1f895c6fe 3598 #define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
mbed_official 340:28d1f895c6fe 3599 #define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
mbed_official 340:28d1f895c6fe 3600 #define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
mbed_official 340:28d1f895c6fe 3601 #define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
mbed_official 340:28d1f895c6fe 3602 #define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
mbed_official 340:28d1f895c6fe 3603
mbed_official 340:28d1f895c6fe 3604 /*!< PPRE configuration */
mbed_official 340:28d1f895c6fe 3605 #define RCC_CFGR_PPRE ((uint32_t)0x00000700) /*!< PRE[2:0] bits (APB prescaler) */
mbed_official 340:28d1f895c6fe 3606 #define RCC_CFGR_PPRE_0 ((uint32_t)0x00000100) /*!< Bit 0 */
mbed_official 340:28d1f895c6fe 3607 #define RCC_CFGR_PPRE_1 ((uint32_t)0x00000200) /*!< Bit 1 */
mbed_official 340:28d1f895c6fe 3608 #define RCC_CFGR_PPRE_2 ((uint32_t)0x00000400) /*!< Bit 2 */
mbed_official 340:28d1f895c6fe 3609
mbed_official 340:28d1f895c6fe 3610 #define RCC_CFGR_PPRE_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
mbed_official 340:28d1f895c6fe 3611 #define RCC_CFGR_PPRE_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */
mbed_official 340:28d1f895c6fe 3612 #define RCC_CFGR_PPRE_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */
mbed_official 340:28d1f895c6fe 3613 #define RCC_CFGR_PPRE_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */
mbed_official 340:28d1f895c6fe 3614 #define RCC_CFGR_PPRE_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */
mbed_official 340:28d1f895c6fe 3615
mbed_official 340:28d1f895c6fe 3616 /*!< ADCPPRE configuration: obsolete setting for STM32F091xC */
mbed_official 340:28d1f895c6fe 3617 /*#define RCC_CFGR_ADCPRE ((uint32_t)0x00004000)*/ /*!< ADCPRE bit (ADC prescaler) */
mbed_official 340:28d1f895c6fe 3618
mbed_official 340:28d1f895c6fe 3619 /*#define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000)*/ /*!< PCLK divided by 2 */
mbed_official 340:28d1f895c6fe 3620 /*#define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000)*/ /*!< PCLK divided by 4 */
mbed_official 340:28d1f895c6fe 3621
mbed_official 340:28d1f895c6fe 3622 #define RCC_CFGR_PLLSRC ((uint32_t)0x00018000) /*!< PLL entry clock source */
mbed_official 340:28d1f895c6fe 3623 #define RCC_CFGR_PLLSRC_HSI_DIV2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */
mbed_official 340:28d1f895c6fe 3624 #define RCC_CFGR_PLLSRC_HSI_PREDIV ((uint32_t)0x00008000) /*!< HSI/PREDIV clock selected as PLL entry clock source */
mbed_official 340:28d1f895c6fe 3625 #define RCC_CFGR_PLLSRC_HSE_PREDIV ((uint32_t)0x00010000) /*!< HSE/PREDIV clock selected as PLL entry clock source */
mbed_official 340:28d1f895c6fe 3626 #define RCC_CFGR_PLLSRC_HSI48_PREDIV ((uint32_t)0x00018000) /*!< HSI48/PREDIV clock selected as PLL entry clock source */
mbed_official 340:28d1f895c6fe 3627
mbed_official 340:28d1f895c6fe 3628 #define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) /*!< HSE divider for PLL entry */
mbed_official 340:28d1f895c6fe 3629 #define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV1 ((uint32_t)0x00000000) /*!< HSE/PREDIV clock not divided for PLL entry */
mbed_official 340:28d1f895c6fe 3630 #define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV2 ((uint32_t)0x00020000) /*!< HSE/PREDIV clock divided by 2 for PLL entry */
mbed_official 340:28d1f895c6fe 3631
mbed_official 340:28d1f895c6fe 3632 /*!< PLLMUL configuration */
mbed_official 340:28d1f895c6fe 3633 #define RCC_CFGR_PLLMUL ((uint32_t)0x003C0000) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
mbed_official 340:28d1f895c6fe 3634 #define RCC_CFGR_PLLMUL_0 ((uint32_t)0x00040000) /*!< Bit 0 */
mbed_official 340:28d1f895c6fe 3635 #define RCC_CFGR_PLLMUL_1 ((uint32_t)0x00080000) /*!< Bit 1 */
mbed_official 340:28d1f895c6fe 3636 #define RCC_CFGR_PLLMUL_2 ((uint32_t)0x00100000) /*!< Bit 2 */
mbed_official 340:28d1f895c6fe 3637 #define RCC_CFGR_PLLMUL_3 ((uint32_t)0x00200000) /*!< Bit 3 */
mbed_official 340:28d1f895c6fe 3638
mbed_official 340:28d1f895c6fe 3639 #define RCC_CFGR_PLLMUL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */
mbed_official 340:28d1f895c6fe 3640 #define RCC_CFGR_PLLMUL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */
mbed_official 340:28d1f895c6fe 3641 #define RCC_CFGR_PLLMUL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */
mbed_official 340:28d1f895c6fe 3642 #define RCC_CFGR_PLLMUL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */
mbed_official 340:28d1f895c6fe 3643 #define RCC_CFGR_PLLMUL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */
mbed_official 340:28d1f895c6fe 3644 #define RCC_CFGR_PLLMUL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */
mbed_official 340:28d1f895c6fe 3645 #define RCC_CFGR_PLLMUL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */
mbed_official 340:28d1f895c6fe 3646 #define RCC_CFGR_PLLMUL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */
mbed_official 340:28d1f895c6fe 3647 #define RCC_CFGR_PLLMUL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */
mbed_official 340:28d1f895c6fe 3648 #define RCC_CFGR_PLLMUL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */
mbed_official 340:28d1f895c6fe 3649 #define RCC_CFGR_PLLMUL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */
mbed_official 340:28d1f895c6fe 3650 #define RCC_CFGR_PLLMUL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */
mbed_official 340:28d1f895c6fe 3651 #define RCC_CFGR_PLLMUL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */
mbed_official 340:28d1f895c6fe 3652 #define RCC_CFGR_PLLMUL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */
mbed_official 340:28d1f895c6fe 3653 #define RCC_CFGR_PLLMUL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */
mbed_official 340:28d1f895c6fe 3654
mbed_official 340:28d1f895c6fe 3655 /*!< MCO configuration */
mbed_official 340:28d1f895c6fe 3656 #define RCC_CFGR_MCO ((uint32_t)0x0F000000) /*!< MCO[3:0] bits (Microcontroller Clock Output) */
mbed_official 340:28d1f895c6fe 3657 #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */
mbed_official 340:28d1f895c6fe 3658 #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */
mbed_official 340:28d1f895c6fe 3659 #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */
mbed_official 340:28d1f895c6fe 3660 #define RCC_CFGR_MCO_3 ((uint32_t)0x08000000) /*!< Bit 3 */
mbed_official 340:28d1f895c6fe 3661
mbed_official 340:28d1f895c6fe 3662 #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
mbed_official 340:28d1f895c6fe 3663 #define RCC_CFGR_MCO_HSI14 ((uint32_t)0x01000000) /*!< HSI14 clock selected as MCO source */
mbed_official 340:28d1f895c6fe 3664 #define RCC_CFGR_MCO_LSI ((uint32_t)0x02000000) /*!< LSI clock selected as MCO source */
mbed_official 340:28d1f895c6fe 3665 #define RCC_CFGR_MCO_LSE ((uint32_t)0x03000000) /*!< LSE clock selected as MCO source */
mbed_official 340:28d1f895c6fe 3666 #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */
mbed_official 340:28d1f895c6fe 3667 #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */
mbed_official 340:28d1f895c6fe 3668 #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */
mbed_official 340:28d1f895c6fe 3669 #define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */
mbed_official 340:28d1f895c6fe 3670 #define RCC_CFGR_MCO_HSI48 ((uint32_t)0x08000000) /*!< HSI48 clock selected as MCO source */
mbed_official 340:28d1f895c6fe 3671
mbed_official 340:28d1f895c6fe 3672 #define RCC_CFGR_MCOPRE ((uint32_t)0x70000000) /*!< MCO prescaler */
mbed_official 340:28d1f895c6fe 3673 #define RCC_CFGR_MCOPRE_DIV1 ((uint32_t)0x00000000) /*!< MCO is divided by 1 */
mbed_official 340:28d1f895c6fe 3674 #define RCC_CFGR_MCOPRE_DIV2 ((uint32_t)0x10000000) /*!< MCO is divided by 2 */
mbed_official 340:28d1f895c6fe 3675 #define RCC_CFGR_MCOPRE_DIV4 ((uint32_t)0x20000000) /*!< MCO is divided by 4 */
mbed_official 340:28d1f895c6fe 3676 #define RCC_CFGR_MCOPRE_DIV8 ((uint32_t)0x30000000) /*!< MCO is divided by 8 */
mbed_official 340:28d1f895c6fe 3677 #define RCC_CFGR_MCOPRE_DIV16 ((uint32_t)0x40000000) /*!< MCO is divided by 16 */
mbed_official 340:28d1f895c6fe 3678 #define RCC_CFGR_MCOPRE_DIV32 ((uint32_t)0x50000000) /*!< MCO is divided by 32 */
mbed_official 340:28d1f895c6fe 3679 #define RCC_CFGR_MCOPRE_DIV64 ((uint32_t)0x60000000) /*!< MCO is divided by 64 */
mbed_official 340:28d1f895c6fe 3680 #define RCC_CFGR_MCOPRE_DIV128 ((uint32_t)0x70000000) /*!< MCO is divided by 128 */
mbed_official 340:28d1f895c6fe 3681
mbed_official 340:28d1f895c6fe 3682 #define RCC_CFGR_PLLNODIV ((uint32_t)0x80000000) /*!< PLL is not divided to MCO */
mbed_official 340:28d1f895c6fe 3683
mbed_official 340:28d1f895c6fe 3684 /*!<****************** Bit definition for RCC_CIR register *****************/
mbed_official 340:28d1f895c6fe 3685 #define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */
mbed_official 340:28d1f895c6fe 3686 #define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */
mbed_official 340:28d1f895c6fe 3687 #define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */
mbed_official 340:28d1f895c6fe 3688 #define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */
mbed_official 340:28d1f895c6fe 3689 #define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */
mbed_official 340:28d1f895c6fe 3690 #define RCC_CIR_HSI14RDYF ((uint32_t)0x00000020) /*!< HSI14 Ready Interrupt flag */
mbed_official 340:28d1f895c6fe 3691 #define RCC_CIR_HSI48RDYF ((uint32_t)0x00000040) /*!< HSI48 Ready Interrupt flag */
mbed_official 340:28d1f895c6fe 3692 #define RCC_CIR_CSSF ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */
mbed_official 340:28d1f895c6fe 3693 #define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */
mbed_official 340:28d1f895c6fe 3694 #define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */
mbed_official 340:28d1f895c6fe 3695 #define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */
mbed_official 340:28d1f895c6fe 3696 #define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */
mbed_official 340:28d1f895c6fe 3697 #define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */
mbed_official 340:28d1f895c6fe 3698 #define RCC_CIR_HSI14RDYIE ((uint32_t)0x00002000) /*!< HSI14 Ready Interrupt Enable */
mbed_official 340:28d1f895c6fe 3699 #define RCC_CIR_HSI48RDYIE ((uint32_t)0x00004000) /*!< HSI48 Ready Interrupt Enable */
mbed_official 340:28d1f895c6fe 3700 #define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */
mbed_official 340:28d1f895c6fe 3701 #define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */
mbed_official 340:28d1f895c6fe 3702 #define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */
mbed_official 340:28d1f895c6fe 3703 #define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */
mbed_official 340:28d1f895c6fe 3704 #define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */
mbed_official 340:28d1f895c6fe 3705 #define RCC_CIR_HSI14RDYC ((uint32_t)0x00200000) /*!< HSI14 Ready Interrupt Clear */
mbed_official 340:28d1f895c6fe 3706 #define RCC_CIR_HSI48RDYC ((uint32_t)0x00400000) /*!< HSI48 Ready Interrupt Clear */
mbed_official 340:28d1f895c6fe 3707 #define RCC_CIR_CSSC ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */
mbed_official 340:28d1f895c6fe 3708
mbed_official 340:28d1f895c6fe 3709 /***************** Bit definition for RCC_APB2RSTR register ****************/
mbed_official 340:28d1f895c6fe 3710 #define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00000001) /*!< SYSCFG clock reset */
mbed_official 340:28d1f895c6fe 3711 #define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000200) /*!< ADC clock reset */
mbed_official 340:28d1f895c6fe 3712 #define RCC_APB2RSTR_USART8RST ((uint32_t)0x00000080) /*!< USART8 clock reset */
mbed_official 340:28d1f895c6fe 3713 #define RCC_APB2RSTR_USART7RST ((uint32_t)0x00000040) /*!< USART7 clock reset */
mbed_official 340:28d1f895c6fe 3714 #define RCC_APB2RSTR_USART6RST ((uint32_t)0x00000020) /*!< USART6 clock reset */
mbed_official 340:28d1f895c6fe 3715 #define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) /*!< TIM1 clock reset */
mbed_official 340:28d1f895c6fe 3716 #define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /*!< SPI1 clock reset */
mbed_official 340:28d1f895c6fe 3717 #define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /*!< USART1 clock reset */
mbed_official 340:28d1f895c6fe 3718 #define RCC_APB2RSTR_TIM15RST ((uint32_t)0x00010000) /*!< TIM15 clock reset */
mbed_official 340:28d1f895c6fe 3719 #define RCC_APB2RSTR_TIM16RST ((uint32_t)0x00020000) /*!< TIM16 clock reset */
mbed_official 340:28d1f895c6fe 3720 #define RCC_APB2RSTR_TIM17RST ((uint32_t)0x00040000) /*!< TIM17 clock reset */
mbed_official 340:28d1f895c6fe 3721 #define RCC_APB2RSTR_DBGMCURST ((uint32_t)0x00400000) /*!< DBGMCU clock reset */
mbed_official 340:28d1f895c6fe 3722
mbed_official 340:28d1f895c6fe 3723 /*!< Old ADC1 clock reset bit definition maintained for legacy purpose */
mbed_official 340:28d1f895c6fe 3724 #define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADCRST
mbed_official 340:28d1f895c6fe 3725
mbed_official 340:28d1f895c6fe 3726 /***************** Bit definition for RCC_APB1RSTR register ****************/
mbed_official 340:28d1f895c6fe 3727 #define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 clock reset */
mbed_official 340:28d1f895c6fe 3728 #define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /*!< Timer 3 clock reset */
mbed_official 340:28d1f895c6fe 3729 #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 clock reset */
mbed_official 340:28d1f895c6fe 3730 #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 clock reset */
mbed_official 340:28d1f895c6fe 3731 #define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100) /*!< Timer 14 clock reset */
mbed_official 340:28d1f895c6fe 3732 #define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog clock reset */
mbed_official 340:28d1f895c6fe 3733 #define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /*!< SPI2 clock reset */
mbed_official 340:28d1f895c6fe 3734 #define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /*!< USART 2 clock reset */
mbed_official 340:28d1f895c6fe 3735 #define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /*!< USART 3 clock reset */
mbed_official 340:28d1f895c6fe 3736 #define RCC_APB1RSTR_USART4RST ((uint32_t)0x00080000) /*!< USART 4 clock reset */
mbed_official 340:28d1f895c6fe 3737 #define RCC_APB1RSTR_USART5RST ((uint32_t)0x00100000) /*!< USART 5 clock reset */
mbed_official 340:28d1f895c6fe 3738 #define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 clock reset */
mbed_official 340:28d1f895c6fe 3739 #define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 clock reset */
mbed_official 340:28d1f895c6fe 3740 #define RCC_APB1RSTR_CANRST ((uint32_t)0x02000000) /*!< CAN clock reset */
mbed_official 340:28d1f895c6fe 3741 #define RCC_APB1RSTR_CRSRST ((uint32_t)0x08000000) /*!< CRS clock reset */
mbed_official 340:28d1f895c6fe 3742 #define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< PWR clock reset */
mbed_official 340:28d1f895c6fe 3743 #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC clock reset */
mbed_official 340:28d1f895c6fe 3744 #define RCC_APB1RSTR_CECRST ((uint32_t)0x40000000) /*!< CEC clock reset */
mbed_official 340:28d1f895c6fe 3745
mbed_official 340:28d1f895c6fe 3746 /****************** Bit definition for RCC_AHBENR register *****************/
mbed_official 340:28d1f895c6fe 3747 #define RCC_AHBENR_DMAEN ((uint32_t)0x00000001) /*!< DMA1 clock enable */
mbed_official 340:28d1f895c6fe 3748 #define RCC_AHBENR_DMA2EN ((uint32_t)0x00000002) /*!< DMA2 clock enable */
mbed_official 340:28d1f895c6fe 3749 #define RCC_AHBENR_SRAMEN ((uint32_t)0x00000004) /*!< SRAM interface clock enable */
mbed_official 340:28d1f895c6fe 3750 #define RCC_AHBENR_FLITFEN ((uint32_t)0x00000010) /*!< FLITF clock enable */
mbed_official 340:28d1f895c6fe 3751 #define RCC_AHBENR_CRCEN ((uint32_t)0x00000040) /*!< CRC clock enable */
mbed_official 340:28d1f895c6fe 3752 #define RCC_AHBENR_GPIOAEN ((uint32_t)0x00020000) /*!< GPIOA clock enable */
mbed_official 340:28d1f895c6fe 3753 #define RCC_AHBENR_GPIOBEN ((uint32_t)0x00040000) /*!< GPIOB clock enable */
mbed_official 340:28d1f895c6fe 3754 #define RCC_AHBENR_GPIOCEN ((uint32_t)0x00080000) /*!< GPIOC clock enable */
mbed_official 340:28d1f895c6fe 3755 #define RCC_AHBENR_GPIODEN ((uint32_t)0x00100000) /*!< GPIOD clock enable */
mbed_official 340:28d1f895c6fe 3756 #define RCC_AHBENR_GPIOEEN ((uint32_t)0x00200000) /*!< GPIOE clock enable */
mbed_official 340:28d1f895c6fe 3757 #define RCC_AHBENR_GPIOFEN ((uint32_t)0x00400000) /*!< GPIOF clock enable */
mbed_official 340:28d1f895c6fe 3758 #define RCC_AHBENR_TSCEN ((uint32_t)0x01000000) /*!< TS controller clock enable */
mbed_official 340:28d1f895c6fe 3759
mbed_official 340:28d1f895c6fe 3760 /* Old Bit definition maintained for legacy purpose */
mbed_official 340:28d1f895c6fe 3761 #define RCC_AHBENR_DMA1EN RCC_AHBENR_DMAEN /*!< DMA1 clock enable */
mbed_official 340:28d1f895c6fe 3762 #define RCC_AHBENR_TSEN RCC_AHBENR_TSCEN /*!< TS clock enable */
mbed_official 340:28d1f895c6fe 3763
mbed_official 340:28d1f895c6fe 3764 /***************** Bit definition for RCC_APB2ENR register *****************/
mbed_official 340:28d1f895c6fe 3765 #define RCC_APB2ENR_SYSCFGCOMPEN ((uint32_t)0x00000001) /*!< SYSCFG and comparator clock enable */
mbed_official 340:28d1f895c6fe 3766 #define RCC_APB2ENR_ADCEN ((uint32_t)0x00000200) /*!< ADC1 clock enable */
mbed_official 340:28d1f895c6fe 3767 #define RCC_APB2ENR_USART8EN ((uint32_t)0x00000080) /*!< USART8 clock enable */
mbed_official 340:28d1f895c6fe 3768 #define RCC_APB2ENR_USART7EN ((uint32_t)0x00000040) /*!< USART7 clock enable */
mbed_official 340:28d1f895c6fe 3769 #define RCC_APB2ENR_USART6EN ((uint32_t)0x00000020) /*!< USART6 clock enable */
mbed_official 340:28d1f895c6fe 3770 #define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) /*!< TIM1 clock enable */
mbed_official 340:28d1f895c6fe 3771 #define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /*!< SPI1 clock enable */
mbed_official 340:28d1f895c6fe 3772 #define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable */
mbed_official 340:28d1f895c6fe 3773 #define RCC_APB2ENR_TIM15EN ((uint32_t)0x00010000) /*!< TIM15 clock enable */
mbed_official 340:28d1f895c6fe 3774 #define RCC_APB2ENR_TIM16EN ((uint32_t)0x00020000) /*!< TIM16 clock enable */
mbed_official 340:28d1f895c6fe 3775 #define RCC_APB2ENR_TIM17EN ((uint32_t)0x00040000) /*!< TIM17 clock enable */
mbed_official 340:28d1f895c6fe 3776 #define RCC_APB2ENR_DBGMCUEN ((uint32_t)0x00400000) /*!< DBGMCU clock enable */
mbed_official 340:28d1f895c6fe 3777
mbed_official 340:28d1f895c6fe 3778 /* Old Bit definition maintained for legacy purpose */
mbed_official 340:28d1f895c6fe 3779 #define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGCOMPEN /*!< SYSCFG clock enable */
mbed_official 340:28d1f895c6fe 3780 #define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADCEN /*!< ADC1 clock enable */
mbed_official 340:28d1f895c6fe 3781
mbed_official 340:28d1f895c6fe 3782 /***************** Bit definition for RCC_APB1ENR register *****************/
mbed_official 340:28d1f895c6fe 3783 #define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enable */
mbed_official 340:28d1f895c6fe 3784 #define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /*!< Timer 3 clock enable */
mbed_official 340:28d1f895c6fe 3785 #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */
mbed_official 340:28d1f895c6fe 3786 #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */
mbed_official 340:28d1f895c6fe 3787 #define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100) /*!< Timer 14 clock enable */
mbed_official 340:28d1f895c6fe 3788 #define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */
mbed_official 340:28d1f895c6fe 3789 #define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /*!< SPI2 clock enable */
mbed_official 340:28d1f895c6fe 3790 #define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /*!< USART2 clock enable */
mbed_official 340:28d1f895c6fe 3791 #define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /*!< USART3 clock enable */
mbed_official 340:28d1f895c6fe 3792 #define RCC_APB1ENR_USART4EN ((uint32_t)0x00080000) /*!< USART4 clock enable */
mbed_official 340:28d1f895c6fe 3793 #define RCC_APB1ENR_USART5EN ((uint32_t)0x00100000) /*!< USART5 clock enable */
mbed_official 340:28d1f895c6fe 3794 #define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C1 clock enable */
mbed_official 340:28d1f895c6fe 3795 #define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /*!< I2C2 clock enable */
mbed_official 340:28d1f895c6fe 3796 #define RCC_APB1ENR_CANEN ((uint32_t)0x02000000) /*!< CAN clock enable */
mbed_official 340:28d1f895c6fe 3797 #define RCC_APB1ENR_CRSEN ((uint32_t)0x08000000) /*!< CRS clock enable */
mbed_official 340:28d1f895c6fe 3798 #define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< PWR clock enable */
mbed_official 340:28d1f895c6fe 3799 #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC clock enable */
mbed_official 340:28d1f895c6fe 3800 #define RCC_APB1ENR_CECEN ((uint32_t)0x40000000) /*!< CEC clock enable */
mbed_official 340:28d1f895c6fe 3801
mbed_official 340:28d1f895c6fe 3802 /******************* Bit definition for RCC_BDCR register ******************/
mbed_official 340:28d1f895c6fe 3803 #define RCC_BDCR_LSEON ((uint32_t)0x00000001) /*!< External Low Speed oscillator enable */
mbed_official 340:28d1f895c6fe 3804 #define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /*!< External Low Speed oscillator Ready */
mbed_official 340:28d1f895c6fe 3805 #define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) /*!< External Low Speed oscillator Bypass */
mbed_official 340:28d1f895c6fe 3806
mbed_official 340:28d1f895c6fe 3807 #define RCC_BDCR_LSEDRV ((uint32_t)0x00000018) /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
mbed_official 340:28d1f895c6fe 3808 #define RCC_BDCR_LSEDRV_0 ((uint32_t)0x00000008) /*!< Bit 0 */
mbed_official 340:28d1f895c6fe 3809 #define RCC_BDCR_LSEDRV_1 ((uint32_t)0x00000010) /*!< Bit 1 */
mbed_official 340:28d1f895c6fe 3810
mbed_official 340:28d1f895c6fe 3811 #define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) /*!< RTCSEL[1:0] bits (RTC clock source selection) */
mbed_official 340:28d1f895c6fe 3812 #define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */
mbed_official 340:28d1f895c6fe 3813 #define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */
mbed_official 340:28d1f895c6fe 3814
mbed_official 340:28d1f895c6fe 3815 /*!< RTC configuration */
mbed_official 340:28d1f895c6fe 3816 #define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
mbed_official 340:28d1f895c6fe 3817 #define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */
mbed_official 340:28d1f895c6fe 3818 #define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */
mbed_official 340:28d1f895c6fe 3819 #define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 128 used as RTC clock */
mbed_official 340:28d1f895c6fe 3820
mbed_official 340:28d1f895c6fe 3821 #define RCC_BDCR_RTCEN ((uint32_t)0x00008000) /*!< RTC clock enable */
mbed_official 340:28d1f895c6fe 3822 #define RCC_BDCR_BDRST ((uint32_t)0x00010000) /*!< Backup domain software reset */
mbed_official 340:28d1f895c6fe 3823
mbed_official 340:28d1f895c6fe 3824 /******************* Bit definition for RCC_CSR register *******************/
mbed_official 340:28d1f895c6fe 3825 #define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */
mbed_official 340:28d1f895c6fe 3826 #define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */
mbed_official 340:28d1f895c6fe 3827 #define RCC_CSR_V18PWRRSTF ((uint32_t)0x00800000) /*!< V1.8 power domain reset flag */
mbed_official 340:28d1f895c6fe 3828 #define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */
mbed_official 340:28d1f895c6fe 3829 #define RCC_CSR_OBLRSTF ((uint32_t)0x02000000) /*!< OBL reset flag */
mbed_official 340:28d1f895c6fe 3830 #define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */
mbed_official 340:28d1f895c6fe 3831 #define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /*!< POR/PDR reset flag */
mbed_official 340:28d1f895c6fe 3832 #define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */
mbed_official 340:28d1f895c6fe 3833 #define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */
mbed_official 340:28d1f895c6fe 3834 #define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */
mbed_official 340:28d1f895c6fe 3835 #define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */
mbed_official 340:28d1f895c6fe 3836
mbed_official 340:28d1f895c6fe 3837 /* Old Bit definition maintained for legacy purpose */
mbed_official 340:28d1f895c6fe 3838 #define RCC_CSR_OBL RCC_CSR_OBLRSTF /*!< OBL reset flag */
mbed_official 340:28d1f895c6fe 3839
mbed_official 340:28d1f895c6fe 3840 /******************* Bit definition for RCC_AHBRSTR register ***************/
mbed_official 340:28d1f895c6fe 3841 #define RCC_AHBRSTR_GPIOARST ((uint32_t)0x00020000) /*!< GPIOA clock reset */
mbed_official 340:28d1f895c6fe 3842 #define RCC_AHBRSTR_GPIOBRST ((uint32_t)0x00040000) /*!< GPIOB clock reset */
mbed_official 340:28d1f895c6fe 3843 #define RCC_AHBRSTR_GPIOCRST ((uint32_t)0x00080000) /*!< GPIOC clock reset */
mbed_official 340:28d1f895c6fe 3844 #define RCC_AHBRSTR_GPIODRST ((uint32_t)0x00100000) /*!< GPIOD clock reset */
mbed_official 340:28d1f895c6fe 3845 #define RCC_AHBRSTR_GPIOERST ((uint32_t)0x00200000) /*!< GPIOE clock reset */
mbed_official 340:28d1f895c6fe 3846 #define RCC_AHBRSTR_GPIOFRST ((uint32_t)0x00400000) /*!< GPIOF clock reset */
mbed_official 340:28d1f895c6fe 3847 #define RCC_AHBRSTR_TSCRST ((uint32_t)0x01000000) /*!< TS clock reset */
mbed_official 340:28d1f895c6fe 3848
mbed_official 340:28d1f895c6fe 3849 /* Old Bit definition maintained for legacy purpose */
mbed_official 340:28d1f895c6fe 3850 #define RCC_AHBRSTR_TSRST RCC_AHBRSTR_TSCRST /*!< TS clock reset */
mbed_official 340:28d1f895c6fe 3851
mbed_official 340:28d1f895c6fe 3852 /******************* Bit definition for RCC_CFGR2 register *****************/
mbed_official 340:28d1f895c6fe 3853 /*!< PREDIV configuration */
mbed_official 340:28d1f895c6fe 3854 #define RCC_CFGR2_PREDIV ((uint32_t)0x0000000F) /*!< PREDIV[3:0] bits */
mbed_official 340:28d1f895c6fe 3855 #define RCC_CFGR2_PREDIV_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 340:28d1f895c6fe 3856 #define RCC_CFGR2_PREDIV_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 340:28d1f895c6fe 3857 #define RCC_CFGR2_PREDIV_2 ((uint32_t)0x00000004) /*!< Bit 2 */
mbed_official 340:28d1f895c6fe 3858 #define RCC_CFGR2_PREDIV_3 ((uint32_t)0x00000008) /*!< Bit 3 */
mbed_official 340:28d1f895c6fe 3859
mbed_official 340:28d1f895c6fe 3860 #define RCC_CFGR2_PREDIV_DIV1 ((uint32_t)0x00000000) /*!< PREDIV input clock not divided */
mbed_official 340:28d1f895c6fe 3861 #define RCC_CFGR2_PREDIV_DIV2 ((uint32_t)0x00000001) /*!< PREDIV input clock divided by 2 */
mbed_official 340:28d1f895c6fe 3862 #define RCC_CFGR2_PREDIV_DIV3 ((uint32_t)0x00000002) /*!< PREDIV input clock divided by 3 */
mbed_official 340:28d1f895c6fe 3863 #define RCC_CFGR2_PREDIV_DIV4 ((uint32_t)0x00000003) /*!< PREDIV input clock divided by 4 */
mbed_official 340:28d1f895c6fe 3864 #define RCC_CFGR2_PREDIV_DIV5 ((uint32_t)0x00000004) /*!< PREDIV input clock divided by 5 */
mbed_official 340:28d1f895c6fe 3865 #define RCC_CFGR2_PREDIV_DIV6 ((uint32_t)0x00000005) /*!< PREDIV input clock divided by 6 */
mbed_official 340:28d1f895c6fe 3866 #define RCC_CFGR2_PREDIV_DIV7 ((uint32_t)0x00000006) /*!< PREDIV input clock divided by 7 */
mbed_official 340:28d1f895c6fe 3867 #define RCC_CFGR2_PREDIV_DIV8 ((uint32_t)0x00000007) /*!< PREDIV input clock divided by 8 */
mbed_official 340:28d1f895c6fe 3868 #define RCC_CFGR2_PREDIV_DIV9 ((uint32_t)0x00000008) /*!< PREDIV input clock divided by 9 */
mbed_official 340:28d1f895c6fe 3869 #define RCC_CFGR2_PREDIV_DIV10 ((uint32_t)0x00000009) /*!< PREDIV input clock divided by 10 */
mbed_official 340:28d1f895c6fe 3870 #define RCC_CFGR2_PREDIV_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV input clock divided by 11 */
mbed_official 340:28d1f895c6fe 3871 #define RCC_CFGR2_PREDIV_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV input clock divided by 12 */
mbed_official 340:28d1f895c6fe 3872 #define RCC_CFGR2_PREDIV_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV input clock divided by 13 */
mbed_official 340:28d1f895c6fe 3873 #define RCC_CFGR2_PREDIV_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV input clock divided by 14 */
mbed_official 340:28d1f895c6fe 3874 #define RCC_CFGR2_PREDIV_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV input clock divided by 15 */
mbed_official 340:28d1f895c6fe 3875 #define RCC_CFGR2_PREDIV_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV input clock divided by 16 */
mbed_official 340:28d1f895c6fe 3876
mbed_official 340:28d1f895c6fe 3877 /******************* Bit definition for RCC_CFGR3 register *****************/
mbed_official 340:28d1f895c6fe 3878 /*!< USART1 Clock source selection */
mbed_official 340:28d1f895c6fe 3879 #define RCC_CFGR3_USART1SW ((uint32_t)0x00000003) /*!< USART1SW[1:0] bits */
mbed_official 340:28d1f895c6fe 3880 #define RCC_CFGR3_USART1SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 340:28d1f895c6fe 3881 #define RCC_CFGR3_USART1SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 340:28d1f895c6fe 3882
mbed_official 340:28d1f895c6fe 3883 #define RCC_CFGR3_USART1SW_PCLK ((uint32_t)0x00000000) /*!< PCLK clock used as USART1 clock source */
mbed_official 340:28d1f895c6fe 3884 #define RCC_CFGR3_USART1SW_SYSCLK ((uint32_t)0x00000001) /*!< System clock selected as USART1 clock source */
mbed_official 340:28d1f895c6fe 3885 #define RCC_CFGR3_USART1SW_LSE ((uint32_t)0x00000002) /*!< LSE oscillator clock used as USART1 clock source */
mbed_official 340:28d1f895c6fe 3886 #define RCC_CFGR3_USART1SW_HSI ((uint32_t)0x00000003) /*!< HSI oscillator clock used as USART1 clock source */
mbed_official 340:28d1f895c6fe 3887
mbed_official 340:28d1f895c6fe 3888 /*!< I2C1 Clock source selection */
mbed_official 340:28d1f895c6fe 3889 #define RCC_CFGR3_I2C1SW ((uint32_t)0x00000010) /*!< I2C1SW bits */
mbed_official 340:28d1f895c6fe 3890
mbed_official 340:28d1f895c6fe 3891 #define RCC_CFGR3_I2C1SW_HSI ((uint32_t)0x00000000) /*!< HSI oscillator clock used as I2C1 clock source */
mbed_official 340:28d1f895c6fe 3892 #define RCC_CFGR3_I2C1SW_SYSCLK ((uint32_t)0x00000010) /*!< System clock selected as I2C1 clock source */
mbed_official 340:28d1f895c6fe 3893
mbed_official 340:28d1f895c6fe 3894 /*!< CEC Clock source selection */
mbed_official 340:28d1f895c6fe 3895 #define RCC_CFGR3_CECSW ((uint32_t)0x00000040) /*!< CECSW bits */
mbed_official 340:28d1f895c6fe 3896
mbed_official 340:28d1f895c6fe 3897 #define RCC_CFGR3_CECSW_HSI_DIV244 ((uint32_t)0x00000000) /*!< HSI clock divided by 244 selected as HDMI CEC entry clock source */
mbed_official 340:28d1f895c6fe 3898 #define RCC_CFGR3_CECSW_LSE ((uint32_t)0x00000040) /*!< LSE clock selected as HDMI CEC entry clock source */
mbed_official 340:28d1f895c6fe 3899
mbed_official 340:28d1f895c6fe 3900 /*!< USART2 Clock source selection */
mbed_official 340:28d1f895c6fe 3901 #define RCC_CFGR3_USART2SW ((uint32_t)0x00030000) /*!< USART2SW[1:0] bits */
mbed_official 340:28d1f895c6fe 3902 #define RCC_CFGR3_USART2SW_0 ((uint32_t)0x00010000) /*!< Bit 0 */
mbed_official 340:28d1f895c6fe 3903 #define RCC_CFGR3_USART2SW_1 ((uint32_t)0x00020000) /*!< Bit 1 */
mbed_official 340:28d1f895c6fe 3904
mbed_official 340:28d1f895c6fe 3905 #define RCC_CFGR3_USART2SW_PCLK ((uint32_t)0x00000000) /*!< PCLK clock used as USART2 clock source */
mbed_official 340:28d1f895c6fe 3906 #define RCC_CFGR3_USART2SW_SYSCLK ((uint32_t)0x00010000) /*!< System clock selected as USART2 clock source */
mbed_official 340:28d1f895c6fe 3907 #define RCC_CFGR3_USART2SW_LSE ((uint32_t)0x00020000) /*!< LSE oscillator clock used as USART2 clock source */
mbed_official 340:28d1f895c6fe 3908 #define RCC_CFGR3_USART2SW_HSI ((uint32_t)0x00030000) /*!< HSI oscillator clock used as USART2 clock source */
mbed_official 340:28d1f895c6fe 3909
mbed_official 340:28d1f895c6fe 3910 /*!< USART3 Clock source selection */
mbed_official 340:28d1f895c6fe 3911 #define RCC_CFGR3_USART3SW ((uint32_t)0x000C0000) /*!< USART3SW[1:0] bits */
mbed_official 340:28d1f895c6fe 3912 #define RCC_CFGR3_USART3SW_0 ((uint32_t)0x00040000) /*!< Bit 0 */
mbed_official 340:28d1f895c6fe 3913 #define RCC_CFGR3_USART3SW_1 ((uint32_t)0x00080000) /*!< Bit 1 */
mbed_official 340:28d1f895c6fe 3914
mbed_official 340:28d1f895c6fe 3915 #define RCC_CFGR3_USART3SW_PCLK ((uint32_t)0x00000000) /*!< PCLK clock used as USART3 clock source */
mbed_official 340:28d1f895c6fe 3916 #define RCC_CFGR3_USART3SW_SYSCLK ((uint32_t)0x00040000) /*!< System clock selected as USART3 clock source */
mbed_official 340:28d1f895c6fe 3917 #define RCC_CFGR3_USART3SW_LSE ((uint32_t)0x00080000) /*!< LSE oscillator clock used as USART3 clock source */
mbed_official 340:28d1f895c6fe 3918 #define RCC_CFGR3_USART3SW_HSI ((uint32_t)0x000C0000) /*!< HSI oscillator clock used as USART3 clock source */
mbed_official 340:28d1f895c6fe 3919
mbed_official 340:28d1f895c6fe 3920 /******************* Bit definition for RCC_CR2 register *******************/
mbed_official 340:28d1f895c6fe 3921 #define RCC_CR2_HSI14ON ((uint32_t)0x00000001) /*!< Internal High Speed 14MHz clock enable */
mbed_official 340:28d1f895c6fe 3922 #define RCC_CR2_HSI14RDY ((uint32_t)0x00000002) /*!< Internal High Speed 14MHz clock ready flag */
mbed_official 340:28d1f895c6fe 3923 #define RCC_CR2_HSI14DIS ((uint32_t)0x00000004) /*!< Internal High Speed 14MHz clock disable */
mbed_official 340:28d1f895c6fe 3924 #define RCC_CR2_HSI14TRIM ((uint32_t)0x000000F8) /*!< Internal High Speed 14MHz clock trimming */
mbed_official 340:28d1f895c6fe 3925 #define RCC_CR2_HSI14CAL ((uint32_t)0x0000FF00) /*!< Internal High Speed 14MHz clock Calibration */
mbed_official 340:28d1f895c6fe 3926 #define RCC_CR2_HSI48ON ((uint32_t)0x00010000) /*!< Internal High Speed 48MHz clock enable */
mbed_official 340:28d1f895c6fe 3927 #define RCC_CR2_HSI48RDY ((uint32_t)0x00020000) /*!< Internal High Speed 48MHz clock ready flag */
mbed_official 340:28d1f895c6fe 3928 #define RCC_CR2_HSI48CAL ((uint32_t)0xFF000000) /*!< Internal High Speed 48MHz clock Calibration */
mbed_official 340:28d1f895c6fe 3929
mbed_official 340:28d1f895c6fe 3930 /*****************************************************************************/
mbed_official 340:28d1f895c6fe 3931 /* */
mbed_official 340:28d1f895c6fe 3932 /* Real-Time Clock (RTC) */
mbed_official 340:28d1f895c6fe 3933 /* */
mbed_official 340:28d1f895c6fe 3934 /*****************************************************************************/
mbed_official 340:28d1f895c6fe 3935 /******************** Bits definition for RTC_TR register ******************/
mbed_official 340:28d1f895c6fe 3936 #define RTC_TR_PM ((uint32_t)0x00400000)
mbed_official 340:28d1f895c6fe 3937 #define RTC_TR_HT ((uint32_t)0x00300000)
mbed_official 340:28d1f895c6fe 3938 #define RTC_TR_HT_0 ((uint32_t)0x00100000)
mbed_official 340:28d1f895c6fe 3939 #define RTC_TR_HT_1 ((uint32_t)0x00200000)
mbed_official 340:28d1f895c6fe 3940 #define RTC_TR_HU ((uint32_t)0x000F0000)
mbed_official 340:28d1f895c6fe 3941 #define RTC_TR_HU_0 ((uint32_t)0x00010000)
mbed_official 340:28d1f895c6fe 3942 #define RTC_TR_HU_1 ((uint32_t)0x00020000)
mbed_official 340:28d1f895c6fe 3943 #define RTC_TR_HU_2 ((uint32_t)0x00040000)
mbed_official 340:28d1f895c6fe 3944 #define RTC_TR_HU_3 ((uint32_t)0x00080000)
mbed_official 340:28d1f895c6fe 3945 #define RTC_TR_MNT ((uint32_t)0x00007000)
mbed_official 340:28d1f895c6fe 3946 #define RTC_TR_MNT_0 ((uint32_t)0x00001000)
mbed_official 340:28d1f895c6fe 3947 #define RTC_TR_MNT_1 ((uint32_t)0x00002000)
mbed_official 340:28d1f895c6fe 3948 #define RTC_TR_MNT_2 ((uint32_t)0x00004000)
mbed_official 340:28d1f895c6fe 3949 #define RTC_TR_MNU ((uint32_t)0x00000F00)
mbed_official 340:28d1f895c6fe 3950 #define RTC_TR_MNU_0 ((uint32_t)0x00000100)
mbed_official 340:28d1f895c6fe 3951 #define RTC_TR_MNU_1 ((uint32_t)0x00000200)
mbed_official 340:28d1f895c6fe 3952 #define RTC_TR_MNU_2 ((uint32_t)0x00000400)
mbed_official 340:28d1f895c6fe 3953 #define RTC_TR_MNU_3 ((uint32_t)0x00000800)
mbed_official 340:28d1f895c6fe 3954 #define RTC_TR_ST ((uint32_t)0x00000070)
mbed_official 340:28d1f895c6fe 3955 #define RTC_TR_ST_0 ((uint32_t)0x00000010)
mbed_official 340:28d1f895c6fe 3956 #define RTC_TR_ST_1 ((uint32_t)0x00000020)
mbed_official 340:28d1f895c6fe 3957 #define RTC_TR_ST_2 ((uint32_t)0x00000040)
mbed_official 340:28d1f895c6fe 3958 #define RTC_TR_SU ((uint32_t)0x0000000F)
mbed_official 340:28d1f895c6fe 3959 #define RTC_TR_SU_0 ((uint32_t)0x00000001)
mbed_official 340:28d1f895c6fe 3960 #define RTC_TR_SU_1 ((uint32_t)0x00000002)
mbed_official 340:28d1f895c6fe 3961 #define RTC_TR_SU_2 ((uint32_t)0x00000004)
mbed_official 340:28d1f895c6fe 3962 #define RTC_TR_SU_3 ((uint32_t)0x00000008)
mbed_official 340:28d1f895c6fe 3963
mbed_official 340:28d1f895c6fe 3964 /******************** Bits definition for RTC_DR register ******************/
mbed_official 340:28d1f895c6fe 3965 #define RTC_DR_YT ((uint32_t)0x00F00000)
mbed_official 340:28d1f895c6fe 3966 #define RTC_DR_YT_0 ((uint32_t)0x00100000)
mbed_official 340:28d1f895c6fe 3967 #define RTC_DR_YT_1 ((uint32_t)0x00200000)
mbed_official 340:28d1f895c6fe 3968 #define RTC_DR_YT_2 ((uint32_t)0x00400000)
mbed_official 340:28d1f895c6fe 3969 #define RTC_DR_YT_3 ((uint32_t)0x00800000)
mbed_official 340:28d1f895c6fe 3970 #define RTC_DR_YU ((uint32_t)0x000F0000)
mbed_official 340:28d1f895c6fe 3971 #define RTC_DR_YU_0 ((uint32_t)0x00010000)
mbed_official 340:28d1f895c6fe 3972 #define RTC_DR_YU_1 ((uint32_t)0x00020000)
mbed_official 340:28d1f895c6fe 3973 #define RTC_DR_YU_2 ((uint32_t)0x00040000)
mbed_official 340:28d1f895c6fe 3974 #define RTC_DR_YU_3 ((uint32_t)0x00080000)
mbed_official 340:28d1f895c6fe 3975 #define RTC_DR_WDU ((uint32_t)0x0000E000)
mbed_official 340:28d1f895c6fe 3976 #define RTC_DR_WDU_0 ((uint32_t)0x00002000)
mbed_official 340:28d1f895c6fe 3977 #define RTC_DR_WDU_1 ((uint32_t)0x00004000)
mbed_official 340:28d1f895c6fe 3978 #define RTC_DR_WDU_2 ((uint32_t)0x00008000)
mbed_official 340:28d1f895c6fe 3979 #define RTC_DR_MT ((uint32_t)0x00001000)
mbed_official 340:28d1f895c6fe 3980 #define RTC_DR_MU ((uint32_t)0x00000F00)
mbed_official 340:28d1f895c6fe 3981 #define RTC_DR_MU_0 ((uint32_t)0x00000100)
mbed_official 340:28d1f895c6fe 3982 #define RTC_DR_MU_1 ((uint32_t)0x00000200)
mbed_official 340:28d1f895c6fe 3983 #define RTC_DR_MU_2 ((uint32_t)0x00000400)
mbed_official 340:28d1f895c6fe 3984 #define RTC_DR_MU_3 ((uint32_t)0x00000800)
mbed_official 340:28d1f895c6fe 3985 #define RTC_DR_DT ((uint32_t)0x00000030)
mbed_official 340:28d1f895c6fe 3986 #define RTC_DR_DT_0 ((uint32_t)0x00000010)
mbed_official 340:28d1f895c6fe 3987 #define RTC_DR_DT_1 ((uint32_t)0x00000020)
mbed_official 340:28d1f895c6fe 3988 #define RTC_DR_DU ((uint32_t)0x0000000F)
mbed_official 340:28d1f895c6fe 3989 #define RTC_DR_DU_0 ((uint32_t)0x00000001)
mbed_official 340:28d1f895c6fe 3990 #define RTC_DR_DU_1 ((uint32_t)0x00000002)
mbed_official 340:28d1f895c6fe 3991 #define RTC_DR_DU_2 ((uint32_t)0x00000004)
mbed_official 340:28d1f895c6fe 3992 #define RTC_DR_DU_3 ((uint32_t)0x00000008)
mbed_official 340:28d1f895c6fe 3993
mbed_official 340:28d1f895c6fe 3994 /******************** Bits definition for RTC_CR register ******************/
mbed_official 340:28d1f895c6fe 3995 #define RTC_CR_COE ((uint32_t)0x00800000)
mbed_official 340:28d1f895c6fe 3996 #define RTC_CR_OSEL ((uint32_t)0x00600000)
mbed_official 340:28d1f895c6fe 3997 #define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
mbed_official 340:28d1f895c6fe 3998 #define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
mbed_official 340:28d1f895c6fe 3999 #define RTC_CR_POL ((uint32_t)0x00100000)
mbed_official 340:28d1f895c6fe 4000 #define RTC_CR_COSEL ((uint32_t)0x00080000)
mbed_official 340:28d1f895c6fe 4001 #define RTC_CR_BCK ((uint32_t)0x00040000)
mbed_official 340:28d1f895c6fe 4002 #define RTC_CR_SUB1H ((uint32_t)0x00020000)
mbed_official 340:28d1f895c6fe 4003 #define RTC_CR_ADD1H ((uint32_t)0x00010000)
mbed_official 340:28d1f895c6fe 4004 #define RTC_CR_TSIE ((uint32_t)0x00008000)
mbed_official 340:28d1f895c6fe 4005 #define RTC_CR_ALRAIE ((uint32_t)0x00001000)
mbed_official 340:28d1f895c6fe 4006 #define RTC_CR_TSE ((uint32_t)0x00000800)
mbed_official 340:28d1f895c6fe 4007 #define RTC_CR_WUTE ((uint32_t)0x00000400)
mbed_official 340:28d1f895c6fe 4008 #define RTC_CR_ALRAE ((uint32_t)0x00000100)
mbed_official 340:28d1f895c6fe 4009 #define RTC_CR_FMT ((uint32_t)0x00000040)
mbed_official 340:28d1f895c6fe 4010 #define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
mbed_official 340:28d1f895c6fe 4011 #define RTC_CR_REFCKON ((uint32_t)0x00000010)
mbed_official 340:28d1f895c6fe 4012 #define RTC_CR_TSEDGE ((uint32_t)0x00000008)
mbed_official 340:28d1f895c6fe 4013 #define RTC_CR_WUCKSEL ((uint32_t)0x00000007)
mbed_official 340:28d1f895c6fe 4014 #define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001)
mbed_official 340:28d1f895c6fe 4015 #define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002)
mbed_official 340:28d1f895c6fe 4016 #define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004)
mbed_official 340:28d1f895c6fe 4017
mbed_official 340:28d1f895c6fe 4018 /******************** Bits definition for RTC_ISR register *****************/
mbed_official 340:28d1f895c6fe 4019 #define RTC_ISR_RECALPF ((uint32_t)0x00010000)
mbed_official 340:28d1f895c6fe 4020 #define RTC_ISR_TAMP3F ((uint32_t)0x00008000)
mbed_official 340:28d1f895c6fe 4021 #define RTC_ISR_TAMP2F ((uint32_t)0x00004000)
mbed_official 340:28d1f895c6fe 4022 #define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
mbed_official 340:28d1f895c6fe 4023 #define RTC_ISR_TSOVF ((uint32_t)0x00001000)
mbed_official 340:28d1f895c6fe 4024 #define RTC_ISR_TSF ((uint32_t)0x00000800)
mbed_official 340:28d1f895c6fe 4025 #define RTC_ISR_WUTF ((uint32_t)0x00000400)
mbed_official 340:28d1f895c6fe 4026 #define RTC_ISR_ALRAF ((uint32_t)0x00000100)
mbed_official 340:28d1f895c6fe 4027 #define RTC_ISR_INIT ((uint32_t)0x00000080)
mbed_official 340:28d1f895c6fe 4028 #define RTC_ISR_INITF ((uint32_t)0x00000040)
mbed_official 340:28d1f895c6fe 4029 #define RTC_ISR_RSF ((uint32_t)0x00000020)
mbed_official 340:28d1f895c6fe 4030 #define RTC_ISR_INITS ((uint32_t)0x00000010)
mbed_official 340:28d1f895c6fe 4031 #define RTC_ISR_SHPF ((uint32_t)0x00000008)
mbed_official 340:28d1f895c6fe 4032 #define RTC_ISR_WUTWF ((uint32_t)0x00000004)
mbed_official 340:28d1f895c6fe 4033 #define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
mbed_official 340:28d1f895c6fe 4034
mbed_official 340:28d1f895c6fe 4035 /******************** Bits definition for RTC_PRER register ****************/
mbed_official 340:28d1f895c6fe 4036 #define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
mbed_official 340:28d1f895c6fe 4037 #define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF)
mbed_official 340:28d1f895c6fe 4038
mbed_official 340:28d1f895c6fe 4039 /******************** Bits definition for RTC_WUTR register ****************/
mbed_official 340:28d1f895c6fe 4040 #define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
mbed_official 340:28d1f895c6fe 4041
mbed_official 340:28d1f895c6fe 4042 /******************** Bits definition for RTC_ALRMAR register **************/
mbed_official 340:28d1f895c6fe 4043 #define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
mbed_official 340:28d1f895c6fe 4044 #define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
mbed_official 340:28d1f895c6fe 4045 #define RTC_ALRMAR_DT ((uint32_t)0x30000000)
mbed_official 340:28d1f895c6fe 4046 #define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
mbed_official 340:28d1f895c6fe 4047 #define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
mbed_official 340:28d1f895c6fe 4048 #define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
mbed_official 340:28d1f895c6fe 4049 #define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
mbed_official 340:28d1f895c6fe 4050 #define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
mbed_official 340:28d1f895c6fe 4051 #define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
mbed_official 340:28d1f895c6fe 4052 #define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
mbed_official 340:28d1f895c6fe 4053 #define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
mbed_official 340:28d1f895c6fe 4054 #define RTC_ALRMAR_PM ((uint32_t)0x00400000)
mbed_official 340:28d1f895c6fe 4055 #define RTC_ALRMAR_HT ((uint32_t)0x00300000)
mbed_official 340:28d1f895c6fe 4056 #define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
mbed_official 340:28d1f895c6fe 4057 #define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
mbed_official 340:28d1f895c6fe 4058 #define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
mbed_official 340:28d1f895c6fe 4059 #define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
mbed_official 340:28d1f895c6fe 4060 #define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
mbed_official 340:28d1f895c6fe 4061 #define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
mbed_official 340:28d1f895c6fe 4062 #define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
mbed_official 340:28d1f895c6fe 4063 #define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
mbed_official 340:28d1f895c6fe 4064 #define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
mbed_official 340:28d1f895c6fe 4065 #define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
mbed_official 340:28d1f895c6fe 4066 #define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
mbed_official 340:28d1f895c6fe 4067 #define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
mbed_official 340:28d1f895c6fe 4068 #define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
mbed_official 340:28d1f895c6fe 4069 #define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
mbed_official 340:28d1f895c6fe 4070 #define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
mbed_official 340:28d1f895c6fe 4071 #define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
mbed_official 340:28d1f895c6fe 4072 #define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
mbed_official 340:28d1f895c6fe 4073 #define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
mbed_official 340:28d1f895c6fe 4074 #define RTC_ALRMAR_ST ((uint32_t)0x00000070)
mbed_official 340:28d1f895c6fe 4075 #define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
mbed_official 340:28d1f895c6fe 4076 #define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
mbed_official 340:28d1f895c6fe 4077 #define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
mbed_official 340:28d1f895c6fe 4078 #define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
mbed_official 340:28d1f895c6fe 4079 #define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
mbed_official 340:28d1f895c6fe 4080 #define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
mbed_official 340:28d1f895c6fe 4081 #define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
mbed_official 340:28d1f895c6fe 4082 #define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
mbed_official 340:28d1f895c6fe 4083
mbed_official 340:28d1f895c6fe 4084 /******************** Bits definition for RTC_WPR register *****************/
mbed_official 340:28d1f895c6fe 4085 #define RTC_WPR_KEY ((uint32_t)0x000000FF)
mbed_official 340:28d1f895c6fe 4086
mbed_official 340:28d1f895c6fe 4087 /******************** Bits definition for RTC_SSR register *****************/
mbed_official 340:28d1f895c6fe 4088 #define RTC_SSR_SS ((uint32_t)0x0000FFFF)
mbed_official 340:28d1f895c6fe 4089
mbed_official 340:28d1f895c6fe 4090 /******************** Bits definition for RTC_SHIFTR register **************/
mbed_official 340:28d1f895c6fe 4091 #define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
mbed_official 340:28d1f895c6fe 4092 #define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
mbed_official 340:28d1f895c6fe 4093
mbed_official 340:28d1f895c6fe 4094 /******************** Bits definition for RTC_TSTR register ****************/
mbed_official 340:28d1f895c6fe 4095 #define RTC_TSTR_PM ((uint32_t)0x00400000)
mbed_official 340:28d1f895c6fe 4096 #define RTC_TSTR_HT ((uint32_t)0x00300000)
mbed_official 340:28d1f895c6fe 4097 #define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
mbed_official 340:28d1f895c6fe 4098 #define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
mbed_official 340:28d1f895c6fe 4099 #define RTC_TSTR_HU ((uint32_t)0x000F0000)
mbed_official 340:28d1f895c6fe 4100 #define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
mbed_official 340:28d1f895c6fe 4101 #define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
mbed_official 340:28d1f895c6fe 4102 #define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
mbed_official 340:28d1f895c6fe 4103 #define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
mbed_official 340:28d1f895c6fe 4104 #define RTC_TSTR_MNT ((uint32_t)0x00007000)
mbed_official 340:28d1f895c6fe 4105 #define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
mbed_official 340:28d1f895c6fe 4106 #define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
mbed_official 340:28d1f895c6fe 4107 #define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
mbed_official 340:28d1f895c6fe 4108 #define RTC_TSTR_MNU ((uint32_t)0x00000F00)
mbed_official 340:28d1f895c6fe 4109 #define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
mbed_official 340:28d1f895c6fe 4110 #define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
mbed_official 340:28d1f895c6fe 4111 #define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
mbed_official 340:28d1f895c6fe 4112 #define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
mbed_official 340:28d1f895c6fe 4113 #define RTC_TSTR_ST ((uint32_t)0x00000070)
mbed_official 340:28d1f895c6fe 4114 #define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
mbed_official 340:28d1f895c6fe 4115 #define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
mbed_official 340:28d1f895c6fe 4116 #define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
mbed_official 340:28d1f895c6fe 4117 #define RTC_TSTR_SU ((uint32_t)0x0000000F)
mbed_official 340:28d1f895c6fe 4118 #define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
mbed_official 340:28d1f895c6fe 4119 #define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
mbed_official 340:28d1f895c6fe 4120 #define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
mbed_official 340:28d1f895c6fe 4121 #define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
mbed_official 340:28d1f895c6fe 4122
mbed_official 340:28d1f895c6fe 4123 /******************** Bits definition for RTC_TSDR register ****************/
mbed_official 340:28d1f895c6fe 4124 #define RTC_TSDR_WDU ((uint32_t)0x0000E000)
mbed_official 340:28d1f895c6fe 4125 #define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
mbed_official 340:28d1f895c6fe 4126 #define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
mbed_official 340:28d1f895c6fe 4127 #define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
mbed_official 340:28d1f895c6fe 4128 #define RTC_TSDR_MT ((uint32_t)0x00001000)
mbed_official 340:28d1f895c6fe 4129 #define RTC_TSDR_MU ((uint32_t)0x00000F00)
mbed_official 340:28d1f895c6fe 4130 #define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
mbed_official 340:28d1f895c6fe 4131 #define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
mbed_official 340:28d1f895c6fe 4132 #define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
mbed_official 340:28d1f895c6fe 4133 #define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
mbed_official 340:28d1f895c6fe 4134 #define RTC_TSDR_DT ((uint32_t)0x00000030)
mbed_official 340:28d1f895c6fe 4135 #define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
mbed_official 340:28d1f895c6fe 4136 #define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
mbed_official 340:28d1f895c6fe 4137 #define RTC_TSDR_DU ((uint32_t)0x0000000F)
mbed_official 340:28d1f895c6fe 4138 #define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
mbed_official 340:28d1f895c6fe 4139 #define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
mbed_official 340:28d1f895c6fe 4140 #define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
mbed_official 340:28d1f895c6fe 4141 #define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
mbed_official 340:28d1f895c6fe 4142
mbed_official 340:28d1f895c6fe 4143 /******************** Bits definition for RTC_TSSSR register ***************/
mbed_official 340:28d1f895c6fe 4144 #define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)
mbed_official 340:28d1f895c6fe 4145
mbed_official 340:28d1f895c6fe 4146 /******************** Bits definition for RTC_CALR register ****************/
mbed_official 340:28d1f895c6fe 4147 #define RTC_CALR_CALP ((uint32_t)0x00008000)
mbed_official 340:28d1f895c6fe 4148 #define RTC_CALR_CALW8 ((uint32_t)0x00004000)
mbed_official 340:28d1f895c6fe 4149 #define RTC_CALR_CALW16 ((uint32_t)0x00002000)
mbed_official 340:28d1f895c6fe 4150 #define RTC_CALR_CALM ((uint32_t)0x000001FF)
mbed_official 340:28d1f895c6fe 4151 #define RTC_CALR_CALM_0 ((uint32_t)0x00000001)
mbed_official 340:28d1f895c6fe 4152 #define RTC_CALR_CALM_1 ((uint32_t)0x00000002)
mbed_official 340:28d1f895c6fe 4153 #define RTC_CALR_CALM_2 ((uint32_t)0x00000004)
mbed_official 340:28d1f895c6fe 4154 #define RTC_CALR_CALM_3 ((uint32_t)0x00000008)
mbed_official 340:28d1f895c6fe 4155 #define RTC_CALR_CALM_4 ((uint32_t)0x00000010)
mbed_official 340:28d1f895c6fe 4156 #define RTC_CALR_CALM_5 ((uint32_t)0x00000020)
mbed_official 340:28d1f895c6fe 4157 #define RTC_CALR_CALM_6 ((uint32_t)0x00000040)
mbed_official 340:28d1f895c6fe 4158 #define RTC_CALR_CALM_7 ((uint32_t)0x00000080)
mbed_official 340:28d1f895c6fe 4159 #define RTC_CALR_CALM_8 ((uint32_t)0x00000100)
mbed_official 340:28d1f895c6fe 4160
mbed_official 340:28d1f895c6fe 4161 /******************** Bits definition for RTC_TAFCR register ***************/
mbed_official 340:28d1f895c6fe 4162 #define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)
mbed_official 340:28d1f895c6fe 4163 #define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)
mbed_official 340:28d1f895c6fe 4164 #define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)
mbed_official 340:28d1f895c6fe 4165 #define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)
mbed_official 340:28d1f895c6fe 4166 #define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)
mbed_official 340:28d1f895c6fe 4167 #define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)
mbed_official 340:28d1f895c6fe 4168 #define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)
mbed_official 340:28d1f895c6fe 4169 #define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)
mbed_official 340:28d1f895c6fe 4170 #define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)
mbed_official 340:28d1f895c6fe 4171 #define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)
mbed_official 340:28d1f895c6fe 4172 #define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)
mbed_official 340:28d1f895c6fe 4173 #define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)
mbed_official 340:28d1f895c6fe 4174 #define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)
mbed_official 340:28d1f895c6fe 4175 #define RTC_TAFCR_TAMP3TRG ((uint32_t)0x00000040)
mbed_official 340:28d1f895c6fe 4176 #define RTC_TAFCR_TAMP3E ((uint32_t)0x00000020)
mbed_official 340:28d1f895c6fe 4177 #define RTC_TAFCR_TAMP2TRG ((uint32_t)0x00000010)
mbed_official 340:28d1f895c6fe 4178 #define RTC_TAFCR_TAMP2E ((uint32_t)0x00000008)
mbed_official 340:28d1f895c6fe 4179 #define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)
mbed_official 340:28d1f895c6fe 4180 #define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)
mbed_official 340:28d1f895c6fe 4181 #define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)
mbed_official 340:28d1f895c6fe 4182
mbed_official 340:28d1f895c6fe 4183 /******************** Bits definition for RTC_ALRMASSR register ************/
mbed_official 340:28d1f895c6fe 4184 #define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
mbed_official 340:28d1f895c6fe 4185 #define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
mbed_official 340:28d1f895c6fe 4186 #define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
mbed_official 340:28d1f895c6fe 4187 #define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
mbed_official 340:28d1f895c6fe 4188 #define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
mbed_official 340:28d1f895c6fe 4189 #define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
mbed_official 340:28d1f895c6fe 4190
mbed_official 340:28d1f895c6fe 4191 /******************** Bits definition for RTC_BKP0R register ***************/
mbed_official 340:28d1f895c6fe 4192 #define RTC_BKP0R ((uint32_t)0xFFFFFFFF)
mbed_official 340:28d1f895c6fe 4193
mbed_official 340:28d1f895c6fe 4194 /******************** Bits definition for RTC_BKP1R register ***************/
mbed_official 340:28d1f895c6fe 4195 #define RTC_BKP1R ((uint32_t)0xFFFFFFFF)
mbed_official 340:28d1f895c6fe 4196
mbed_official 340:28d1f895c6fe 4197 /******************** Bits definition for RTC_BKP2R register ***************/
mbed_official 340:28d1f895c6fe 4198 #define RTC_BKP2R ((uint32_t)0xFFFFFFFF)
mbed_official 340:28d1f895c6fe 4199
mbed_official 340:28d1f895c6fe 4200 /******************** Bits definition for RTC_BKP3R register ***************/
mbed_official 340:28d1f895c6fe 4201 #define RTC_BKP3R ((uint32_t)0xFFFFFFFF)
mbed_official 340:28d1f895c6fe 4202
mbed_official 340:28d1f895c6fe 4203 /******************** Bits definition for RTC_BKP4R register ***************/
mbed_official 340:28d1f895c6fe 4204 #define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
mbed_official 340:28d1f895c6fe 4205
mbed_official 340:28d1f895c6fe 4206 /******************** Number of backup registers ******************************/
mbed_official 340:28d1f895c6fe 4207 #define RTC_BKP_NUMBER ((uint32_t)0x00000005)
mbed_official 340:28d1f895c6fe 4208
mbed_official 340:28d1f895c6fe 4209 /*****************************************************************************/
mbed_official 340:28d1f895c6fe 4210 /* */
mbed_official 340:28d1f895c6fe 4211 /* Serial Peripheral Interface (SPI) */
mbed_official 340:28d1f895c6fe 4212 /* */
mbed_official 340:28d1f895c6fe 4213 /*****************************************************************************/
mbed_official 340:28d1f895c6fe 4214 /******************* Bit definition for SPI_CR1 register *******************/
mbed_official 340:28d1f895c6fe 4215 #define SPI_CR1_CPHA ((uint32_t)0x00000001) /*!< Clock Phase */
mbed_official 340:28d1f895c6fe 4216 #define SPI_CR1_CPOL ((uint32_t)0x00000002) /*!< Clock Polarity */
mbed_official 340:28d1f895c6fe 4217 #define SPI_CR1_MSTR ((uint32_t)0x00000004) /*!< Master Selection */
mbed_official 340:28d1f895c6fe 4218 #define SPI_CR1_BR ((uint32_t)0x00000038) /*!< BR[2:0] bits (Baud Rate Control) */
mbed_official 340:28d1f895c6fe 4219 #define SPI_CR1_BR_0 ((uint32_t)0x00000008) /*!< Bit 0 */
mbed_official 340:28d1f895c6fe 4220 #define SPI_CR1_BR_1 ((uint32_t)0x00000010) /*!< Bit 1 */
mbed_official 340:28d1f895c6fe 4221 #define SPI_CR1_BR_2 ((uint32_t)0x00000020) /*!< Bit 2 */
mbed_official 340:28d1f895c6fe 4222 #define SPI_CR1_SPE ((uint32_t)0x00000040) /*!< SPI Enable */
mbed_official 340:28d1f895c6fe 4223 #define SPI_CR1_LSBFIRST ((uint32_t)0x00000080) /*!< Frame Format */
mbed_official 340:28d1f895c6fe 4224 #define SPI_CR1_SSI ((uint32_t)0x00000100) /*!< Internal slave select */
mbed_official 340:28d1f895c6fe 4225 #define SPI_CR1_SSM ((uint32_t)0x00000200) /*!< Software slave management */
mbed_official 340:28d1f895c6fe 4226 #define SPI_CR1_RXONLY ((uint32_t)0x00000400) /*!< Receive only */
mbed_official 340:28d1f895c6fe 4227 #define SPI_CR1_CRCL ((uint32_t)0x00000800) /*!< CRC Length */
mbed_official 340:28d1f895c6fe 4228 #define SPI_CR1_CRCNEXT ((uint32_t)0x00001000) /*!< Transmit CRC next */
mbed_official 340:28d1f895c6fe 4229 #define SPI_CR1_CRCEN ((uint32_t)0x00002000) /*!< Hardware CRC calculation enable */
mbed_official 340:28d1f895c6fe 4230 #define SPI_CR1_BIDIOE ((uint32_t)0x00004000) /*!< Output enable in bidirectional mode */
mbed_official 340:28d1f895c6fe 4231 #define SPI_CR1_BIDIMODE ((uint32_t)0x00008000) /*!< Bidirectional data mode enable */
mbed_official 340:28d1f895c6fe 4232
mbed_official 340:28d1f895c6fe 4233 /******************* Bit definition for SPI_CR2 register *******************/
mbed_official 340:28d1f895c6fe 4234 #define SPI_CR2_RXDMAEN ((uint32_t)0x00000001) /*!< Rx Buffer DMA Enable */
mbed_official 340:28d1f895c6fe 4235 #define SPI_CR2_TXDMAEN ((uint32_t)0x00000002) /*!< Tx Buffer DMA Enable */
mbed_official 340:28d1f895c6fe 4236 #define SPI_CR2_SSOE ((uint32_t)0x00000004) /*!< SS Output Enable */
mbed_official 340:28d1f895c6fe 4237 #define SPI_CR2_NSSP ((uint32_t)0x00000008) /*!< NSS pulse management Enable */
mbed_official 340:28d1f895c6fe 4238 #define SPI_CR2_FRF ((uint32_t)0x00000010) /*!< Frame Format Enable */
mbed_official 340:28d1f895c6fe 4239 #define SPI_CR2_ERRIE ((uint32_t)0x00000020) /*!< Error Interrupt Enable */
mbed_official 340:28d1f895c6fe 4240 #define SPI_CR2_RXNEIE ((uint32_t)0x00000040) /*!< RX buffer Not Empty Interrupt Enable */
mbed_official 340:28d1f895c6fe 4241 #define SPI_CR2_TXEIE ((uint32_t)0x00000080) /*!< Tx buffer Empty Interrupt Enable */
mbed_official 340:28d1f895c6fe 4242 #define SPI_CR2_DS ((uint32_t)0x00000F00) /*!< DS[3:0] Data Size */
mbed_official 340:28d1f895c6fe 4243 #define SPI_CR2_DS_0 ((uint32_t)0x00000100) /*!< Bit 0 */
mbed_official 340:28d1f895c6fe 4244 #define SPI_CR2_DS_1 ((uint32_t)0x00000200) /*!< Bit 1 */
mbed_official 340:28d1f895c6fe 4245 #define SPI_CR2_DS_2 ((uint32_t)0x00000400) /*!< Bit 2 */
mbed_official 340:28d1f895c6fe 4246 #define SPI_CR2_DS_3 ((uint32_t)0x00000800) /*!< Bit 3 */
mbed_official 340:28d1f895c6fe 4247 #define SPI_CR2_FRXTH ((uint32_t)0x00001000) /*!< FIFO reception Threshold */
mbed_official 340:28d1f895c6fe 4248 #define SPI_CR2_LDMARX ((uint32_t)0x00002000) /*!< Last DMA transfer for reception */
mbed_official 340:28d1f895c6fe 4249 #define SPI_CR2_LDMATX ((uint32_t)0x00004000) /*!< Last DMA transfer for transmission */
mbed_official 340:28d1f895c6fe 4250
mbed_official 340:28d1f895c6fe 4251 /******************** Bit definition for SPI_SR register *******************/
mbed_official 340:28d1f895c6fe 4252 #define SPI_SR_RXNE ((uint32_t)0x00000001) /*!< Receive buffer Not Empty */
mbed_official 340:28d1f895c6fe 4253 #define SPI_SR_TXE ((uint32_t)0x00000002) /*!< Transmit buffer Empty */
mbed_official 340:28d1f895c6fe 4254 #define SPI_SR_CHSIDE ((uint32_t)0x00000004) /*!< Channel side */
mbed_official 340:28d1f895c6fe 4255 #define SPI_SR_UDR ((uint32_t)0x00000008) /*!< Underrun flag */
mbed_official 340:28d1f895c6fe 4256 #define SPI_SR_CRCERR ((uint32_t)0x00000010) /*!< CRC Error flag */
mbed_official 340:28d1f895c6fe 4257 #define SPI_SR_MODF ((uint32_t)0x00000020) /*!< Mode fault */
mbed_official 340:28d1f895c6fe 4258 #define SPI_SR_OVR ((uint32_t)0x00000040) /*!< Overrun flag */
mbed_official 340:28d1f895c6fe 4259 #define SPI_SR_BSY ((uint32_t)0x00000080) /*!< Busy flag */
mbed_official 340:28d1f895c6fe 4260 #define SPI_SR_FRE ((uint32_t)0x00000100) /*!< TI frame format error */
mbed_official 340:28d1f895c6fe 4261 #define SPI_SR_FRLVL ((uint32_t)0x00000600) /*!< FIFO Reception Level */
mbed_official 340:28d1f895c6fe 4262 #define SPI_SR_FRLVL_0 ((uint32_t)0x00000200) /*!< Bit 0 */
mbed_official 340:28d1f895c6fe 4263 #define SPI_SR_FRLVL_1 ((uint32_t)0x00000400) /*!< Bit 1 */
mbed_official 340:28d1f895c6fe 4264 #define SPI_SR_FTLVL ((uint32_t)0x00001800) /*!< FIFO Transmission Level */
mbed_official 340:28d1f895c6fe 4265 #define SPI_SR_FTLVL_0 ((uint32_t)0x00000800) /*!< Bit 0 */
mbed_official 340:28d1f895c6fe 4266 #define SPI_SR_FTLVL_1 ((uint32_t)0x00001000) /*!< Bit 1 */
mbed_official 340:28d1f895c6fe 4267
mbed_official 340:28d1f895c6fe 4268 /******************** Bit definition for SPI_DR register *******************/
mbed_official 340:28d1f895c6fe 4269 #define SPI_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data Register */
mbed_official 340:28d1f895c6fe 4270
mbed_official 340:28d1f895c6fe 4271 /******************* Bit definition for SPI_CRCPR register *****************/
mbed_official 340:28d1f895c6fe 4272 #define SPI_CRCPR_CRCPOLY ((uint32_t)0xFFFFFFFF) /*!< CRC polynomial register */
mbed_official 340:28d1f895c6fe 4273
mbed_official 340:28d1f895c6fe 4274 /****************** Bit definition for SPI_RXCRCR register *****************/
mbed_official 340:28d1f895c6fe 4275 #define SPI_RXCRCR_RXCRC ((uint32_t)0xFFFFFFFF) /*!< Rx CRC Register */
mbed_official 340:28d1f895c6fe 4276
mbed_official 340:28d1f895c6fe 4277 /****************** Bit definition for SPI_TXCRCR register *****************/
mbed_official 340:28d1f895c6fe 4278 #define SPI_TXCRCR_TXCRC ((uint32_t)0xFFFFFFFF) /*!< Tx CRC Register */
mbed_official 340:28d1f895c6fe 4279
mbed_official 340:28d1f895c6fe 4280 /****************** Bit definition for SPI_I2SCFGR register ****************/
mbed_official 340:28d1f895c6fe 4281 #define SPI_I2SCFGR_CHLEN ((uint32_t)0x00000001) /*!<Channel length (number of bits per audio channel) */
mbed_official 340:28d1f895c6fe 4282 #define SPI_I2SCFGR_DATLEN ((uint32_t)0x00000006) /*!<DATLEN[1:0] bits (Data length to be transferred) */
mbed_official 340:28d1f895c6fe 4283 #define SPI_I2SCFGR_DATLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */
mbed_official 340:28d1f895c6fe 4284 #define SPI_I2SCFGR_DATLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */
mbed_official 340:28d1f895c6fe 4285 #define SPI_I2SCFGR_CKPOL ((uint32_t)0x00000008) /*!<steady state clock polarity */
mbed_official 340:28d1f895c6fe 4286 #define SPI_I2SCFGR_I2SSTD ((uint32_t)0x00000030) /*!<I2SSTD[1:0] bits (I2S standard selection) */
mbed_official 340:28d1f895c6fe 4287 #define SPI_I2SCFGR_I2SSTD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 340:28d1f895c6fe 4288 #define SPI_I2SCFGR_I2SSTD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 340:28d1f895c6fe 4289 #define SPI_I2SCFGR_PCMSYNC ((uint32_t)0x00000080) /*!<PCM frame synchronization */
mbed_official 340:28d1f895c6fe 4290 #define SPI_I2SCFGR_I2SCFG ((uint32_t)0x00000300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */
mbed_official 340:28d1f895c6fe 4291 #define SPI_I2SCFGR_I2SCFG_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 340:28d1f895c6fe 4292 #define SPI_I2SCFGR_I2SCFG_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 340:28d1f895c6fe 4293 #define SPI_I2SCFGR_I2SE ((uint32_t)0x00000400) /*!<I2S Enable */
mbed_official 340:28d1f895c6fe 4294 #define SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) /*!<I2S mode selection */
mbed_official 340:28d1f895c6fe 4295
mbed_official 340:28d1f895c6fe 4296 /****************** Bit definition for SPI_I2SPR register ******************/
mbed_official 340:28d1f895c6fe 4297 #define SPI_I2SPR_I2SDIV ((uint32_t)0x000000FF) /*!<I2S Linear prescaler */
mbed_official 340:28d1f895c6fe 4298 #define SPI_I2SPR_ODD ((uint32_t)0x00000100) /*!<Odd factor for the prescaler */
mbed_official 340:28d1f895c6fe 4299 #define SPI_I2SPR_MCKOE ((uint32_t)0x00000200) /*!<Master Clock Output Enable */
mbed_official 340:28d1f895c6fe 4300
mbed_official 340:28d1f895c6fe 4301 /*****************************************************************************/
mbed_official 340:28d1f895c6fe 4302 /* */
mbed_official 340:28d1f895c6fe 4303 /* System Configuration (SYSCFG) */
mbed_official 340:28d1f895c6fe 4304 /* */
mbed_official 340:28d1f895c6fe 4305 /*****************************************************************************/
mbed_official 340:28d1f895c6fe 4306 /***************** Bit definition for SYSCFG_CFGR1 register ****************/
mbed_official 340:28d1f895c6fe 4307 #define SYSCFG_CFGR1_MEM_MODE ((uint32_t)0x00000003) /*!< SYSCFG_Memory Remap Config */
mbed_official 340:28d1f895c6fe 4308 #define SYSCFG_CFGR1_MEM_MODE_0 ((uint32_t)0x00000001) /*!< SYSCFG_Memory Remap Config Bit 0 */
mbed_official 340:28d1f895c6fe 4309 #define SYSCFG_CFGR1_MEM_MODE_1 ((uint32_t)0x00000002) /*!< SYSCFG_Memory Remap Config Bit 1 */
mbed_official 340:28d1f895c6fe 4310 #define SYSCFG_CFGR1_IRDA_ENV_SEL ((uint32_t)0x000000C0) /*!< IRDA_SEL_ENV config */
mbed_official 340:28d1f895c6fe 4311 #define SYSCFG_CFGR1_IRDA_ENV_SEL_0 ((uint32_t)0x00000040) /*!< IRDA_SEL_ENV Bit 0 */
mbed_official 340:28d1f895c6fe 4312 #define SYSCFG_CFGR1_IRDA_ENV_SEL_1 ((uint32_t)0x00000080) /*!< IRDA_SEL_ENV Bit 1 */
mbed_official 340:28d1f895c6fe 4313 #define SYSCFG_CFGR1_I2C_FMP_PB6 ((uint32_t)0x00010000) /*!< I2C PB6 Fast mode plus */
mbed_official 340:28d1f895c6fe 4314 #define SYSCFG_CFGR1_I2C_FMP_PB7 ((uint32_t)0x00020000) /*!< I2C PB7 Fast mode plus */
mbed_official 340:28d1f895c6fe 4315 #define SYSCFG_CFGR1_I2C_FMP_PB8 ((uint32_t)0x00040000) /*!< I2C PB8 Fast mode plus */
mbed_official 340:28d1f895c6fe 4316 #define SYSCFG_CFGR1_I2C_FMP_PB9 ((uint32_t)0x00080000) /*!< I2C PB9 Fast mode plus */
mbed_official 340:28d1f895c6fe 4317 #define SYSCFG_CFGR1_I2C_FMP_I2C1 ((uint32_t)0x00100000) /*!< Enable Fast Mode Plus on PB10, PB11, PF6 and PF7 */
mbed_official 340:28d1f895c6fe 4318 #define SYSCFG_CFGR1_I2C_FMP_I2C2 ((uint32_t)0x00200000) /*!< Enable I2C2 Fast mode plus */
mbed_official 340:28d1f895c6fe 4319 #define SYSCFG_CFGR1_I2C_FMP_PA9 ((uint32_t)0x00400000) /*!< Enable Fast Mode Plus on PA9 */
mbed_official 340:28d1f895c6fe 4320 #define SYSCFG_CFGR1_I2C_FMP_PA10 ((uint32_t)0x00800000) /*!< Enable Fast Mode Plus on PA10 */
mbed_official 340:28d1f895c6fe 4321
mbed_official 340:28d1f895c6fe 4322 /***************** Bit definition for SYSCFG_EXTICR1 register **************/
mbed_official 340:28d1f895c6fe 4323 #define SYSCFG_EXTICR1_EXTI0 ((uint16_t)0x000F) /*!< EXTI 0 configuration */
mbed_official 340:28d1f895c6fe 4324 #define SYSCFG_EXTICR1_EXTI1 ((uint16_t)0x00F0) /*!< EXTI 1 configuration */
mbed_official 340:28d1f895c6fe 4325 #define SYSCFG_EXTICR1_EXTI2 ((uint16_t)0x0F00) /*!< EXTI 2 configuration */
mbed_official 340:28d1f895c6fe 4326 #define SYSCFG_EXTICR1_EXTI3 ((uint16_t)0xF000) /*!< EXTI 3 configuration */
mbed_official 340:28d1f895c6fe 4327
mbed_official 340:28d1f895c6fe 4328 /**
mbed_official 340:28d1f895c6fe 4329 * @brief EXTI0 configuration
mbed_official 340:28d1f895c6fe 4330 */
mbed_official 340:28d1f895c6fe 4331 #define SYSCFG_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /*!< PA[0] pin */
mbed_official 340:28d1f895c6fe 4332 #define SYSCFG_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /*!< PB[0] pin */
mbed_official 340:28d1f895c6fe 4333 #define SYSCFG_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /*!< PC[0] pin */
mbed_official 340:28d1f895c6fe 4334 #define SYSCFG_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /*!< PD[0] pin */
mbed_official 340:28d1f895c6fe 4335 #define SYSCFG_EXTICR1_EXTI0_PE ((uint16_t)0x0004) /*!< PE[0] pin */
mbed_official 340:28d1f895c6fe 4336 #define SYSCFG_EXTICR1_EXTI0_PF ((uint16_t)0x0005) /*!< PF[0] pin */
mbed_official 340:28d1f895c6fe 4337
mbed_official 340:28d1f895c6fe 4338 /**
mbed_official 340:28d1f895c6fe 4339 * @brief EXTI1 configuration
mbed_official 340:28d1f895c6fe 4340 */
mbed_official 340:28d1f895c6fe 4341 #define SYSCFG_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /*!< PA[1] pin */
mbed_official 340:28d1f895c6fe 4342 #define SYSCFG_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /*!< PB[1] pin */
mbed_official 340:28d1f895c6fe 4343 #define SYSCFG_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /*!< PC[1] pin */
mbed_official 340:28d1f895c6fe 4344 #define SYSCFG_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /*!< PD[1] pin */
mbed_official 340:28d1f895c6fe 4345 #define SYSCFG_EXTICR1_EXTI1_PE ((uint16_t)0x0040) /*!< PE[1] pin */
mbed_official 340:28d1f895c6fe 4346 #define SYSCFG_EXTICR1_EXTI1_PF ((uint16_t)0x0050) /*!< PF[1] pin */
mbed_official 340:28d1f895c6fe 4347
mbed_official 340:28d1f895c6fe 4348 /**
mbed_official 340:28d1f895c6fe 4349 * @brief EXTI2 configuration
mbed_official 340:28d1f895c6fe 4350 */
mbed_official 340:28d1f895c6fe 4351 #define SYSCFG_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /*!< PA[2] pin */
mbed_official 340:28d1f895c6fe 4352 #define SYSCFG_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /*!< PB[2] pin */
mbed_official 340:28d1f895c6fe 4353 #define SYSCFG_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /*!< PC[2] pin */
mbed_official 340:28d1f895c6fe 4354 #define SYSCFG_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /*!< PD[2] pin */
mbed_official 340:28d1f895c6fe 4355 #define SYSCFG_EXTICR1_EXTI2_PE ((uint16_t)0x0400) /*!< PE[2] pin */
mbed_official 340:28d1f895c6fe 4356 #define SYSCFG_EXTICR1_EXTI2_PF ((uint16_t)0x0500) /*!< PF[2] pin */
mbed_official 340:28d1f895c6fe 4357
mbed_official 340:28d1f895c6fe 4358 /**
mbed_official 340:28d1f895c6fe 4359 * @brief EXTI3 configuration
mbed_official 340:28d1f895c6fe 4360 */
mbed_official 340:28d1f895c6fe 4361 #define SYSCFG_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /*!< PA[3] pin */
mbed_official 340:28d1f895c6fe 4362 #define SYSCFG_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /*!< PB[3] pin */
mbed_official 340:28d1f895c6fe 4363 #define SYSCFG_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /*!< PC[3] pin */
mbed_official 340:28d1f895c6fe 4364 #define SYSCFG_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /*!< PD[3] pin */
mbed_official 340:28d1f895c6fe 4365 #define SYSCFG_EXTICR1_EXTI3_PE ((uint16_t)0x4000) /*!< PE[3] pin */
mbed_official 340:28d1f895c6fe 4366 #define SYSCFG_EXTICR1_EXTI3_PF ((uint16_t)0x5000) /*!< PF[3] pin */
mbed_official 340:28d1f895c6fe 4367
mbed_official 340:28d1f895c6fe 4368 /***************** Bit definition for SYSCFG_EXTICR2 register **************/
mbed_official 340:28d1f895c6fe 4369 #define SYSCFG_EXTICR2_EXTI4 ((uint16_t)0x000F) /*!< EXTI 4 configuration */
mbed_official 340:28d1f895c6fe 4370 #define SYSCFG_EXTICR2_EXTI5 ((uint16_t)0x00F0) /*!< EXTI 5 configuration */
mbed_official 340:28d1f895c6fe 4371 #define SYSCFG_EXTICR2_EXTI6 ((uint16_t)0x0F00) /*!< EXTI 6 configuration */
mbed_official 340:28d1f895c6fe 4372 #define SYSCFG_EXTICR2_EXTI7 ((uint16_t)0xF000) /*!< EXTI 7 configuration */
mbed_official 340:28d1f895c6fe 4373
mbed_official 340:28d1f895c6fe 4374 /**
mbed_official 340:28d1f895c6fe 4375 * @brief EXTI4 configuration
mbed_official 340:28d1f895c6fe 4376 */
mbed_official 340:28d1f895c6fe 4377 #define SYSCFG_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /*!< PA[4] pin */
mbed_official 340:28d1f895c6fe 4378 #define SYSCFG_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /*!< PB[4] pin */
mbed_official 340:28d1f895c6fe 4379 #define SYSCFG_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /*!< PC[4] pin */
mbed_official 340:28d1f895c6fe 4380 #define SYSCFG_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /*!< PD[4] pin */
mbed_official 340:28d1f895c6fe 4381 #define SYSCFG_EXTICR2_EXTI4_PE ((uint16_t)0x0004) /*!< PE[4] pin */
mbed_official 340:28d1f895c6fe 4382 #define SYSCFG_EXTICR2_EXTI4_PF ((uint16_t)0x0005) /*!< PF[4] pin */
mbed_official 340:28d1f895c6fe 4383
mbed_official 340:28d1f895c6fe 4384 /**
mbed_official 340:28d1f895c6fe 4385 * @brief EXTI5 configuration
mbed_official 340:28d1f895c6fe 4386 */
mbed_official 340:28d1f895c6fe 4387 #define SYSCFG_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /*!< PA[5] pin */
mbed_official 340:28d1f895c6fe 4388 #define SYSCFG_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /*!< PB[5] pin */
mbed_official 340:28d1f895c6fe 4389 #define SYSCFG_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /*!< PC[5] pin */
mbed_official 340:28d1f895c6fe 4390 #define SYSCFG_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /*!< PD[5] pin */
mbed_official 340:28d1f895c6fe 4391 #define SYSCFG_EXTICR2_EXTI5_PE ((uint16_t)0x0040) /*!< PE[5] pin */
mbed_official 340:28d1f895c6fe 4392 #define SYSCFG_EXTICR2_EXTI5_PF ((uint16_t)0x0050) /*!< PF[5] pin */
mbed_official 340:28d1f895c6fe 4393
mbed_official 340:28d1f895c6fe 4394 /**
mbed_official 340:28d1f895c6fe 4395 * @brief EXTI6 configuration
mbed_official 340:28d1f895c6fe 4396 */
mbed_official 340:28d1f895c6fe 4397 #define SYSCFG_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /*!< PA[6] pin */
mbed_official 340:28d1f895c6fe 4398 #define SYSCFG_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /*!< PB[6] pin */
mbed_official 340:28d1f895c6fe 4399 #define SYSCFG_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /*!< PC[6] pin */
mbed_official 340:28d1f895c6fe 4400 #define SYSCFG_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /*!< PD[6] pin */
mbed_official 340:28d1f895c6fe 4401 #define SYSCFG_EXTICR2_EXTI6_PE ((uint16_t)0x0400) /*!< PE[6] pin */
mbed_official 340:28d1f895c6fe 4402 #define SYSCFG_EXTICR2_EXTI6_PF ((uint16_t)0x0500) /*!< PF[6] pin */
mbed_official 340:28d1f895c6fe 4403
mbed_official 340:28d1f895c6fe 4404 /**
mbed_official 340:28d1f895c6fe 4405 * @brief EXTI7 configuration
mbed_official 340:28d1f895c6fe 4406 */
mbed_official 340:28d1f895c6fe 4407 #define SYSCFG_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /*!< PA[7] pin */
mbed_official 340:28d1f895c6fe 4408 #define SYSCFG_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /*!< PB[7] pin */
mbed_official 340:28d1f895c6fe 4409 #define SYSCFG_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /*!< PC[7] pin */
mbed_official 340:28d1f895c6fe 4410 #define SYSCFG_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /*!< PD[7] pin */
mbed_official 340:28d1f895c6fe 4411 #define SYSCFG_EXTICR2_EXTI7_PE ((uint16_t)0x4000) /*!< PE[7] pin */
mbed_official 340:28d1f895c6fe 4412 #define SYSCFG_EXTICR2_EXTI7_PF ((uint16_t)0x5000) /*!< PF[7] pin */
mbed_official 340:28d1f895c6fe 4413
mbed_official 340:28d1f895c6fe 4414 /***************** Bit definition for SYSCFG_EXTICR3 register **************/
mbed_official 340:28d1f895c6fe 4415 #define SYSCFG_EXTICR3_EXTI8 ((uint16_t)0x000F) /*!< EXTI 8 configuration */
mbed_official 340:28d1f895c6fe 4416 #define SYSCFG_EXTICR3_EXTI9 ((uint16_t)0x00F0) /*!< EXTI 9 configuration */
mbed_official 340:28d1f895c6fe 4417 #define SYSCFG_EXTICR3_EXTI10 ((uint16_t)0x0F00) /*!< EXTI 10 configuration */
mbed_official 340:28d1f895c6fe 4418 #define SYSCFG_EXTICR3_EXTI11 ((uint16_t)0xF000) /*!< EXTI 11 configuration */
mbed_official 340:28d1f895c6fe 4419
mbed_official 340:28d1f895c6fe 4420 /**
mbed_official 340:28d1f895c6fe 4421 * @brief EXTI8 configuration
mbed_official 340:28d1f895c6fe 4422 */
mbed_official 340:28d1f895c6fe 4423 #define SYSCFG_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /*!< PA[8] pin */
mbed_official 340:28d1f895c6fe 4424 #define SYSCFG_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /*!< PB[8] pin */
mbed_official 340:28d1f895c6fe 4425 #define SYSCFG_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /*!< PC[8] pin */
mbed_official 340:28d1f895c6fe 4426 #define SYSCFG_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /*!< PD[8] pin */
mbed_official 340:28d1f895c6fe 4427 #define SYSCFG_EXTICR3_EXTI8_PE ((uint16_t)0x0004) /*!< PE[8] pin */
mbed_official 340:28d1f895c6fe 4428
mbed_official 340:28d1f895c6fe 4429 /**
mbed_official 340:28d1f895c6fe 4430 * @brief EXTI9 configuration
mbed_official 340:28d1f895c6fe 4431 */
mbed_official 340:28d1f895c6fe 4432 #define SYSCFG_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /*!< PA[9] pin */
mbed_official 340:28d1f895c6fe 4433 #define SYSCFG_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /*!< PB[9] pin */
mbed_official 340:28d1f895c6fe 4434 #define SYSCFG_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /*!< PC[9] pin */
mbed_official 340:28d1f895c6fe 4435 #define SYSCFG_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /*!< PD[9] pin */
mbed_official 340:28d1f895c6fe 4436 #define SYSCFG_EXTICR3_EXTI9_PE ((uint16_t)0x0040) /*!< PE[9] pin */
mbed_official 340:28d1f895c6fe 4437 #define SYSCFG_EXTICR3_EXTI9_PF ((uint16_t)0x0050) /*!< PF[9] pin */
mbed_official 340:28d1f895c6fe 4438
mbed_official 340:28d1f895c6fe 4439 /**
mbed_official 340:28d1f895c6fe 4440 * @brief EXTI10 configuration
mbed_official 340:28d1f895c6fe 4441 */
mbed_official 340:28d1f895c6fe 4442 #define SYSCFG_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /*!< PA[10] pin */
mbed_official 340:28d1f895c6fe 4443 #define SYSCFG_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /*!< PB[10] pin */
mbed_official 340:28d1f895c6fe 4444 #define SYSCFG_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /*!< PC[10] pin */
mbed_official 340:28d1f895c6fe 4445 #define SYSCFG_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /*!< PE[10] pin */
mbed_official 340:28d1f895c6fe 4446 #define SYSCFG_EXTICR3_EXTI10_PE ((uint16_t)0x0400) /*!< PD[10] pin */
mbed_official 340:28d1f895c6fe 4447 #define SYSCFG_EXTICR3_EXTI10_PF ((uint16_t)0x0500) /*!< PF[10] pin */
mbed_official 340:28d1f895c6fe 4448
mbed_official 340:28d1f895c6fe 4449 /**
mbed_official 340:28d1f895c6fe 4450 * @brief EXTI11 configuration
mbed_official 340:28d1f895c6fe 4451 */
mbed_official 340:28d1f895c6fe 4452 #define SYSCFG_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /*!< PA[11] pin */
mbed_official 340:28d1f895c6fe 4453 #define SYSCFG_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /*!< PB[11] pin */
mbed_official 340:28d1f895c6fe 4454 #define SYSCFG_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /*!< PC[11] pin */
mbed_official 340:28d1f895c6fe 4455 #define SYSCFG_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /*!< PD[11] pin */
mbed_official 340:28d1f895c6fe 4456 #define SYSCFG_EXTICR3_EXTI11_PE ((uint16_t)0x4000) /*!< PE[11] pin */
mbed_official 340:28d1f895c6fe 4457
mbed_official 340:28d1f895c6fe 4458 /***************** Bit definition for SYSCFG_EXTICR4 register **************/
mbed_official 340:28d1f895c6fe 4459 #define SYSCFG_EXTICR4_EXTI12 ((uint16_t)0x000F) /*!< EXTI 12 configuration */
mbed_official 340:28d1f895c6fe 4460 #define SYSCFG_EXTICR4_EXTI13 ((uint16_t)0x00F0) /*!< EXTI 13 configuration */
mbed_official 340:28d1f895c6fe 4461 #define SYSCFG_EXTICR4_EXTI14 ((uint16_t)0x0F00) /*!< EXTI 14 configuration */
mbed_official 340:28d1f895c6fe 4462 #define SYSCFG_EXTICR4_EXTI15 ((uint16_t)0xF000) /*!< EXTI 15 configuration */
mbed_official 340:28d1f895c6fe 4463
mbed_official 340:28d1f895c6fe 4464 /**
mbed_official 340:28d1f895c6fe 4465 * @brief EXTI12 configuration
mbed_official 340:28d1f895c6fe 4466 */
mbed_official 340:28d1f895c6fe 4467 #define SYSCFG_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /*!< PA[12] pin */
mbed_official 340:28d1f895c6fe 4468 #define SYSCFG_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /*!< PB[12] pin */
mbed_official 340:28d1f895c6fe 4469 #define SYSCFG_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /*!< PC[12] pin */
mbed_official 340:28d1f895c6fe 4470 #define SYSCFG_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /*!< PD[12] pin */
mbed_official 340:28d1f895c6fe 4471 #define SYSCFG_EXTICR4_EXTI12_PE ((uint16_t)0x0004) /*!< PE[12] pin */
mbed_official 340:28d1f895c6fe 4472
mbed_official 340:28d1f895c6fe 4473 /**
mbed_official 340:28d1f895c6fe 4474 * @brief EXTI13 configuration
mbed_official 340:28d1f895c6fe 4475 */
mbed_official 340:28d1f895c6fe 4476 #define SYSCFG_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /*!< PA[13] pin */
mbed_official 340:28d1f895c6fe 4477 #define SYSCFG_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /*!< PB[13] pin */
mbed_official 340:28d1f895c6fe 4478 #define SYSCFG_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /*!< PC[13] pin */
mbed_official 340:28d1f895c6fe 4479 #define SYSCFG_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /*!< PD[13] pin */
mbed_official 340:28d1f895c6fe 4480 #define SYSCFG_EXTICR4_EXTI13_PE ((uint16_t)0x0040) /*!< PE[13] pin */
mbed_official 340:28d1f895c6fe 4481
mbed_official 340:28d1f895c6fe 4482 /**
mbed_official 340:28d1f895c6fe 4483 * @brief EXTI14 configuration
mbed_official 340:28d1f895c6fe 4484 */
mbed_official 340:28d1f895c6fe 4485 #define SYSCFG_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /*!< PA[14] pin */
mbed_official 340:28d1f895c6fe 4486 #define SYSCFG_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /*!< PB[14] pin */
mbed_official 340:28d1f895c6fe 4487 #define SYSCFG_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /*!< PC[14] pin */
mbed_official 340:28d1f895c6fe 4488 #define SYSCFG_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /*!< PD[14] pin */
mbed_official 340:28d1f895c6fe 4489 #define SYSCFG_EXTICR4_EXTI14_PE ((uint16_t)0x0400) /*!< PE[14] pin */
mbed_official 340:28d1f895c6fe 4490
mbed_official 340:28d1f895c6fe 4491 /**
mbed_official 340:28d1f895c6fe 4492 * @brief EXTI15 configuration
mbed_official 340:28d1f895c6fe 4493 */
mbed_official 340:28d1f895c6fe 4494 #define SYSCFG_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /*!< PA[15] pin */
mbed_official 340:28d1f895c6fe 4495 #define SYSCFG_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /*!< PB[15] pin */
mbed_official 340:28d1f895c6fe 4496 #define SYSCFG_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /*!< PC[15] pin */
mbed_official 340:28d1f895c6fe 4497 #define SYSCFG_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /*!< PD[15] pin */
mbed_official 340:28d1f895c6fe 4498 #define SYSCFG_EXTICR4_EXTI15_PE ((uint16_t)0x4000) /*!< PE[15] pin */
mbed_official 340:28d1f895c6fe 4499
mbed_official 340:28d1f895c6fe 4500 /***************** Bit definition for SYSCFG_CFGR2 register ****************/
mbed_official 340:28d1f895c6fe 4501 #define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM0 with Break Input of TIMER1 */
mbed_official 340:28d1f895c6fe 4502 #define SYSCFG_CFGR2_SRAM_PARITY_LOCK ((uint32_t)0x00000002) /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1 */
mbed_official 340:28d1f895c6fe 4503 #define SYSCFG_CFGR2_PVD_LOCK ((uint32_t)0x00000004) /*!< Enables and locks the PVD connection with Timer1 Break Input and also the PVD_EN and PVDSEL[2:0] bits of the Power Control Interface */
mbed_official 340:28d1f895c6fe 4504 #define SYSCFG_CFGR2_SRAM_PEF ((uint32_t)0x00000100) /*!< SRAM Parity error flag */
mbed_official 340:28d1f895c6fe 4505 #define SYSCFG_CFGR2_SRAM_PE SYSCFG_CFGR2_SRAM_PEF /*!< SRAM Parity error flag (define maintained for legacy purpose) */
mbed_official 340:28d1f895c6fe 4506
mbed_official 340:28d1f895c6fe 4507 /***************** Bit definition for SYSCFG_xxx ISR Wrapper register ****************/
mbed_official 340:28d1f895c6fe 4508 #define SYSCFG_ITLINE0_SR_EWDG ((uint32_t)0x00000001) /*!< EWDG interrupt */
mbed_official 340:28d1f895c6fe 4509 #define SYSCFG_ITLINE1_SR_PVDOUT ((uint32_t)0x00000001) /*!< Power voltage detection -> exti[31] Interrupt */
mbed_official 340:28d1f895c6fe 4510 #define SYSCFG_ITLINE1_SR_VDDIO2 ((uint32_t)0x00000002) /*!< VDDIO2 -> exti[16] Interrupt */
mbed_official 340:28d1f895c6fe 4511 #define SYSCFG_ITLINE2_SR_RTC_WAKEUP ((uint32_t)0x00000001) /*!< RTC WAKEUP -> exti[20] Interrupt */
mbed_official 340:28d1f895c6fe 4512 #define SYSCFG_ITLINE2_SR_RTC_TSTAMP ((uint32_t)0x00000002) /*!< RTC Time Stamp -> exti[19] interrupt */
mbed_official 340:28d1f895c6fe 4513 #define SYSCFG_ITLINE2_SR_RTC_ALRA ((uint32_t)0x00000003) /*!< RTC Alarm -> exti[17] interrupt .... */
mbed_official 340:28d1f895c6fe 4514 #define SYSCFG_ITLINE3_SR_FLASH_ITF ((uint32_t)0x00000001) /*!< Flash ITF Interrupt */
mbed_official 340:28d1f895c6fe 4515 #define SYSCFG_ITLINE4_SR_CRS ((uint32_t)0x00000001) /*!< CRS interrupt */
mbed_official 340:28d1f895c6fe 4516 #define SYSCFG_ITLINE4_SR_CLK_CTRL ((uint32_t)0x00000002) /*!< CLK CTRL interrupt */
mbed_official 340:28d1f895c6fe 4517 #define SYSCFG_ITLINE5_SR_EXTI0 ((uint32_t)0x00000001) /*!< External Interrupt 0 */
mbed_official 340:28d1f895c6fe 4518 #define SYSCFG_ITLINE5_SR_EXTI1 ((uint32_t)0x00000002) /*!< External Interrupt 1 */
mbed_official 340:28d1f895c6fe 4519 #define SYSCFG_ITLINE6_SR_EXTI2 ((uint32_t)0x00000001) /*!< External Interrupt 2 */
mbed_official 340:28d1f895c6fe 4520 #define SYSCFG_ITLINE6_SR_EXTI3 ((uint32_t)0x00000002) /*!< External Interrupt 3 */
mbed_official 340:28d1f895c6fe 4521 #define SYSCFG_ITLINE7_SR_EXTI4 ((uint32_t)0x00000001) /*!< External Interrupt 15 to 4 */
mbed_official 340:28d1f895c6fe 4522 #define SYSCFG_ITLINE7_SR_EXTI5 ((uint32_t)0x00000002) /*!< External Interrupt 15 to 4 */
mbed_official 340:28d1f895c6fe 4523 #define SYSCFG_ITLINE7_SR_EXTI6 ((uint32_t)0x00000004) /*!< External Interrupt 15 to 4 */
mbed_official 340:28d1f895c6fe 4524 #define SYSCFG_ITLINE7_SR_EXTI7 ((uint32_t)0x00000008) /*!< External Interrupt 15 to 4 */
mbed_official 340:28d1f895c6fe 4525 #define SYSCFG_ITLINE7_SR_EXTI8 ((uint32_t)0x00000010) /*!< External Interrupt 15 to 4 */
mbed_official 340:28d1f895c6fe 4526 #define SYSCFG_ITLINE7_SR_EXTI9 ((uint32_t)0x00000020) /*!< External Interrupt 15 to 4 */
mbed_official 340:28d1f895c6fe 4527 #define SYSCFG_ITLINE7_SR_EXTI10 ((uint32_t)0x00000040) /*!< External Interrupt 15 to 4 */
mbed_official 340:28d1f895c6fe 4528 #define SYSCFG_ITLINE7_SR_EXTI11 ((uint32_t)0x00000080) /*!< External Interrupt 15 to 4 */
mbed_official 340:28d1f895c6fe 4529 #define SYSCFG_ITLINE7_SR_EXTI12 ((uint32_t)0x00000100) /*!< External Interrupt 15 to 4 */
mbed_official 340:28d1f895c6fe 4530 #define SYSCFG_ITLINE7_SR_EXTI13 ((uint32_t)0x00000200) /*!< External Interrupt 15 to 4 */
mbed_official 340:28d1f895c6fe 4531 #define SYSCFG_ITLINE7_SR_EXTI14 ((uint32_t)0x00000400) /*!< External Interrupt 15 to 4 */
mbed_official 340:28d1f895c6fe 4532 #define SYSCFG_ITLINE7_SR_EXTI15 ((uint32_t)0x00000800) /*!< External Interrupt 15 to 4 */
mbed_official 340:28d1f895c6fe 4533 #define SYSCFG_ITLINE8_SR_TSC_EOA ((uint32_t)0x00000001) /*!< Touch control EOA Interrupt */
mbed_official 340:28d1f895c6fe 4534 #define SYSCFG_ITLINE8_SR_TSC_MCE ((uint32_t)0x00000002) /*!< Touch control MCE Interrupt */
mbed_official 340:28d1f895c6fe 4535 #define SYSCFG_ITLINE9_SR_DMA1_CH1 ((uint32_t)0x00000001) /*!< DMA1 Channel 1 Interrupt */
mbed_official 340:28d1f895c6fe 4536 #define SYSCFG_ITLINE10_SR_DMA1_CH2 ((uint32_t)0x00000001) /*!< DMA1 Channel 2 Interrupt */
mbed_official 340:28d1f895c6fe 4537 #define SYSCFG_ITLINE10_SR_DMA1_CH3 ((uint32_t)0x00000002) /*!< DMA2 Channel 3 Interrupt */
mbed_official 340:28d1f895c6fe 4538 #define SYSCFG_ITLINE10_SR_DMA2_CH1 ((uint32_t)0x00000004) /*!< DMA2 Channel 1 Interrupt */
mbed_official 340:28d1f895c6fe 4539 #define SYSCFG_ITLINE10_SR_DMA2_CH2 ((uint32_t)0x00000008) /*!< DMA2 Channel 2 Interrupt */
mbed_official 340:28d1f895c6fe 4540 #define SYSCFG_ITLINE11_SR_DMA1_CH4 ((uint32_t)0x00000001) /*!< DMA1 Channel 4 Interrupt */
mbed_official 340:28d1f895c6fe 4541 #define SYSCFG_ITLINE11_SR_DMA1_CH5 ((uint32_t)0x00000002) /*!< DMA1 Channel 5 Interrupt */
mbed_official 340:28d1f895c6fe 4542 #define SYSCFG_ITLINE11_SR_DMA1_CH6 ((uint32_t)0x00000004) /*!< DMA1 Channel 6 Interrupt */
mbed_official 340:28d1f895c6fe 4543 #define SYSCFG_ITLINE11_SR_DMA1_CH7 ((uint32_t)0x00000008) /*!< DMA1 Channel 7 Interrupt */
mbed_official 340:28d1f895c6fe 4544 #define SYSCFG_ITLINE11_SR_DMA2_CH3 ((uint32_t)0x00000010) /*!< DMA2 Channel 3 Interrupt */
mbed_official 340:28d1f895c6fe 4545 #define SYSCFG_ITLINE11_SR_DMA2_CH4 ((uint32_t)0x00000020) /*!< DMA2 Channel 4 Interrupt */
mbed_official 340:28d1f895c6fe 4546 #define SYSCFG_ITLINE11_SR_DMA2_CH5 ((uint32_t)0x00000040) /*!< DMA2 Channel 5 Interrupt */
mbed_official 340:28d1f895c6fe 4547 #define SYSCFG_ITLINE12_SR_ADC ((uint32_t)0x00000001) /*!< ADC Interrupt */
mbed_official 340:28d1f895c6fe 4548 #define SYSCFG_ITLINE12_SR_COMP1 ((uint32_t)0x00000002) /*!< COMP1 Interrupt -> exti[21] */
mbed_official 340:28d1f895c6fe 4549 #define SYSCFG_ITLINE12_SR_COMP2 ((uint32_t)0x00000004) /*!< COMP2 Interrupt -> exti[22] */
mbed_official 340:28d1f895c6fe 4550 #define SYSCFG_ITLINE13_SR_TIM1_BRK ((uint32_t)0x00000001) /*!< TIM1 BRK Interrupt */
mbed_official 340:28d1f895c6fe 4551 #define SYSCFG_ITLINE13_SR_TIM1_UPD ((uint32_t)0x00000002) /*!< TIM1 UPD Interrupt */
mbed_official 340:28d1f895c6fe 4552 #define SYSCFG_ITLINE13_SR_TIM1_TRG ((uint32_t)0x00000004) /*!< TIM1 TRG Interrupt */
mbed_official 340:28d1f895c6fe 4553 #define SYSCFG_ITLINE13_SR_TIM1_CCU ((uint32_t)0x00000008) /*!< TIM1 CCU Interrupt */
mbed_official 340:28d1f895c6fe 4554 #define SYSCFG_ITLINE14_SR_TIM1_CC ((uint32_t)0x00000001) /*!< TIM1 CC Interrupt */
mbed_official 340:28d1f895c6fe 4555 #define SYSCFG_ITLINE15_SR_TIM2_GLB ((uint32_t)0x00000001) /*!< TIM2 GLB Interrupt */
mbed_official 340:28d1f895c6fe 4556 #define SYSCFG_ITLINE16_SR_TIM3_GLB ((uint32_t)0x00000001) /*!< TIM3 GLB Interrupt */
mbed_official 340:28d1f895c6fe 4557 #define SYSCFG_ITLINE17_SR_DAC ((uint32_t)0x00000001) /*!< DAC Interrupt */
mbed_official 340:28d1f895c6fe 4558 #define SYSCFG_ITLINE17_SR_TIM6_GLB ((uint32_t)0x00000002) /*!< TIM6 GLB Interrupt */
mbed_official 340:28d1f895c6fe 4559 #define SYSCFG_ITLINE18_SR_TIM7_GLB ((uint32_t)0x00000001) /*!< TIM7 GLB Interrupt */
mbed_official 340:28d1f895c6fe 4560 #define SYSCFG_ITLINE19_SR_TIM14_GLB ((uint32_t)0x00000001) /*!< TIM14 GLB Interrupt */
mbed_official 340:28d1f895c6fe 4561 #define SYSCFG_ITLINE20_SR_TIM15_GLB ((uint32_t)0x00000001) /*!< TIM15 GLB Interrupt */
mbed_official 340:28d1f895c6fe 4562 #define SYSCFG_ITLINE21_SR_TIM16_GLB ((uint32_t)0x00000001) /*!< TIM16 GLB Interrupt */
mbed_official 340:28d1f895c6fe 4563 #define SYSCFG_ITLINE22_SR_TIM17_GLB ((uint32_t)0x00000001) /*!< TIM17 GLB Interrupt */
mbed_official 340:28d1f895c6fe 4564 #define SYSCFG_ITLINE23_SR_I2C1_GLB ((uint32_t)0x00000001) /*!< I2C1 GLB Interrupt -> exti[23] */
mbed_official 340:28d1f895c6fe 4565 #define SYSCFG_ITLINE24_SR_I2C2_GLB ((uint32_t)0x00000001) /*!< I2C2 GLB Interrupt */
mbed_official 340:28d1f895c6fe 4566 #define SYSCFG_ITLINE25_SR_SPI1 ((uint32_t)0x00000001) /*!< SPI1 Interrupt */
mbed_official 340:28d1f895c6fe 4567 #define SYSCFG_ITLINE26_SR_SPI2 ((uint32_t)0x00000001) /*!< SPI2 Interrupt */
mbed_official 340:28d1f895c6fe 4568 #define SYSCFG_ITLINE27_SR_USART1_GLB ((uint32_t)0x00000001) /*!< USART1 GLB Interrupt -> exti[25] */
mbed_official 340:28d1f895c6fe 4569 #define SYSCFG_ITLINE28_SR_USART2_GLB ((uint32_t)0x00000001) /*!< USART2 GLB Interrupt -> exti[26] */
mbed_official 340:28d1f895c6fe 4570 #define SYSCFG_ITLINE29_SR_USART3_GLB ((uint32_t)0x00000001) /*!< USART3 GLB Interrupt -> exti[28] */
mbed_official 340:28d1f895c6fe 4571 #define SYSCFG_ITLINE29_SR_USART4_GLB ((uint32_t)0x00000002) /*!< USART4 GLB Interrupt */
mbed_official 340:28d1f895c6fe 4572 #define SYSCFG_ITLINE29_SR_USART5_GLB ((uint32_t)0x00000004) /*!< USART5 GLB Interrupt */
mbed_official 340:28d1f895c6fe 4573 #define SYSCFG_ITLINE29_SR_USART6_GLB ((uint32_t)0x00000008) /*!< USART6 GLB Interrupt */
mbed_official 340:28d1f895c6fe 4574 #define SYSCFG_ITLINE29_SR_USART7_GLB ((uint32_t)0x00000010) /*!< USART7 GLB Interrupt */
mbed_official 340:28d1f895c6fe 4575 #define SYSCFG_ITLINE29_SR_USART8_GLB ((uint32_t)0x00000020) /*!< USART8 GLB Interrupt */
mbed_official 340:28d1f895c6fe 4576 #define SYSCFG_ITLINE30_SR_CAN ((uint32_t)0x00000001) /*!< CAN Interrupt */
mbed_official 340:28d1f895c6fe 4577 #define SYSCFG_ITLINE30_SR_CEC ((uint32_t)0x00000002) /*!< CEC Interrupt */
mbed_official 340:28d1f895c6fe 4578
mbed_official 340:28d1f895c6fe 4579 /*****************************************************************************/
mbed_official 340:28d1f895c6fe 4580 /* */
mbed_official 340:28d1f895c6fe 4581 /* Timers (TIM) */
mbed_official 340:28d1f895c6fe 4582 /* */
mbed_official 340:28d1f895c6fe 4583 /*****************************************************************************/
mbed_official 340:28d1f895c6fe 4584 /******************* Bit definition for TIM_CR1 register *******************/
mbed_official 340:28d1f895c6fe 4585 #define TIM_CR1_CEN ((uint32_t)0x00000001) /*!<Counter enable */
mbed_official 340:28d1f895c6fe 4586 #define TIM_CR1_UDIS ((uint32_t)0x00000002) /*!<Update disable */
mbed_official 340:28d1f895c6fe 4587 #define TIM_CR1_URS ((uint32_t)0x00000004) /*!<Update request source */
mbed_official 340:28d1f895c6fe 4588 #define TIM_CR1_OPM ((uint32_t)0x00000008) /*!<One pulse mode */
mbed_official 340:28d1f895c6fe 4589 #define TIM_CR1_DIR ((uint32_t)0x00000010) /*!<Direction */
mbed_official 340:28d1f895c6fe 4590
mbed_official 340:28d1f895c6fe 4591 #define TIM_CR1_CMS ((uint32_t)0x00000060) /*!<CMS[1:0] bits (Center-aligned mode selection) */
mbed_official 340:28d1f895c6fe 4592 #define TIM_CR1_CMS_0 ((uint32_t)0x00000020) /*!<Bit 0 */
mbed_official 340:28d1f895c6fe 4593 #define TIM_CR1_CMS_1 ((uint32_t)0x00000040) /*!<Bit 1 */
mbed_official 340:28d1f895c6fe 4594
mbed_official 340:28d1f895c6fe 4595 #define TIM_CR1_ARPE ((uint32_t)0x00000080) /*!<Auto-reload preload enable */
mbed_official 340:28d1f895c6fe 4596
mbed_official 340:28d1f895c6fe 4597 #define TIM_CR1_CKD ((uint32_t)0x00000300) /*!<CKD[1:0] bits (clock division) */
mbed_official 340:28d1f895c6fe 4598 #define TIM_CR1_CKD_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 340:28d1f895c6fe 4599 #define TIM_CR1_CKD_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 340:28d1f895c6fe 4600
mbed_official 340:28d1f895c6fe 4601 /******************* Bit definition for TIM_CR2 register *******************/
mbed_official 340:28d1f895c6fe 4602 #define TIM_CR2_CCPC ((uint32_t)0x00000001) /*!<Capture/Compare Preloaded Control */
mbed_official 340:28d1f895c6fe 4603 #define TIM_CR2_CCUS ((uint32_t)0x00000004) /*!<Capture/Compare Control Update Selection */
mbed_official 340:28d1f895c6fe 4604 #define TIM_CR2_CCDS ((uint32_t)0x00000008) /*!<Capture/Compare DMA Selection */
mbed_official 340:28d1f895c6fe 4605
mbed_official 340:28d1f895c6fe 4606 #define TIM_CR2_MMS ((uint32_t)0x00000070) /*!<MMS[2:0] bits (Master Mode Selection) */
mbed_official 340:28d1f895c6fe 4607 #define TIM_CR2_MMS_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 340:28d1f895c6fe 4608 #define TIM_CR2_MMS_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 340:28d1f895c6fe 4609 #define TIM_CR2_MMS_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 340:28d1f895c6fe 4610
mbed_official 340:28d1f895c6fe 4611 #define TIM_CR2_TI1S ((uint32_t)0x00000080) /*!<TI1 Selection */
mbed_official 340:28d1f895c6fe 4612 #define TIM_CR2_OIS1 ((uint32_t)0x00000100) /*!<Output Idle state 1 (OC1 output) */
mbed_official 340:28d1f895c6fe 4613 #define TIM_CR2_OIS1N ((uint32_t)0x00000200) /*!<Output Idle state 1 (OC1N output) */
mbed_official 340:28d1f895c6fe 4614 #define TIM_CR2_OIS2 ((uint32_t)0x00000400) /*!<Output Idle state 2 (OC2 output) */
mbed_official 340:28d1f895c6fe 4615 #define TIM_CR2_OIS2N ((uint32_t)0x00000800) /*!<Output Idle state 2 (OC2N output) */
mbed_official 340:28d1f895c6fe 4616 #define TIM_CR2_OIS3 ((uint32_t)0x00001000) /*!<Output Idle state 3 (OC3 output) */
mbed_official 340:28d1f895c6fe 4617 #define TIM_CR2_OIS3N ((uint32_t)0x00002000) /*!<Output Idle state 3 (OC3N output) */
mbed_official 340:28d1f895c6fe 4618 #define TIM_CR2_OIS4 ((uint32_t)0x00004000) /*!<Output Idle state 4 (OC4 output) */
mbed_official 340:28d1f895c6fe 4619
mbed_official 340:28d1f895c6fe 4620 /******************* Bit definition for TIM_SMCR register ******************/
mbed_official 340:28d1f895c6fe 4621 #define TIM_SMCR_SMS ((uint32_t)0x00000007) /*!<SMS[2:0] bits (Slave mode selection) */
mbed_official 340:28d1f895c6fe 4622 #define TIM_SMCR_SMS_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 340:28d1f895c6fe 4623 #define TIM_SMCR_SMS_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 340:28d1f895c6fe 4624 #define TIM_SMCR_SMS_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 340:28d1f895c6fe 4625
mbed_official 340:28d1f895c6fe 4626 #define TIM_SMCR_OCCS ((uint32_t)0x00000008) /*!< OCREF clear selection */
mbed_official 340:28d1f895c6fe 4627
mbed_official 340:28d1f895c6fe 4628 #define TIM_SMCR_TS ((uint32_t)0x00000070) /*!<TS[2:0] bits (Trigger selection) */
mbed_official 340:28d1f895c6fe 4629 #define TIM_SMCR_TS_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 340:28d1f895c6fe 4630 #define TIM_SMCR_TS_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 340:28d1f895c6fe 4631 #define TIM_SMCR_TS_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 340:28d1f895c6fe 4632
mbed_official 340:28d1f895c6fe 4633 #define TIM_SMCR_MSM ((uint32_t)0x00000080) /*!<Master/slave mode */
mbed_official 340:28d1f895c6fe 4634
mbed_official 340:28d1f895c6fe 4635 #define TIM_SMCR_ETF ((uint32_t)0x00000F00) /*!<ETF[3:0] bits (External trigger filter) */
mbed_official 340:28d1f895c6fe 4636 #define TIM_SMCR_ETF_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 340:28d1f895c6fe 4637 #define TIM_SMCR_ETF_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 340:28d1f895c6fe 4638 #define TIM_SMCR_ETF_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 340:28d1f895c6fe 4639 #define TIM_SMCR_ETF_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 340:28d1f895c6fe 4640
mbed_official 340:28d1f895c6fe 4641 #define TIM_SMCR_ETPS ((uint32_t)0x00003000) /*!<ETPS[1:0] bits (External trigger prescaler) */
mbed_official 340:28d1f895c6fe 4642 #define TIM_SMCR_ETPS_0 ((uint32_t)0x00001000) /*!<Bit 0 */
mbed_official 340:28d1f895c6fe 4643 #define TIM_SMCR_ETPS_1 ((uint32_t)0x00002000) /*!<Bit 1 */
mbed_official 340:28d1f895c6fe 4644
mbed_official 340:28d1f895c6fe 4645 #define TIM_SMCR_ECE ((uint32_t)0x00004000) /*!<External clock enable */
mbed_official 340:28d1f895c6fe 4646 #define TIM_SMCR_ETP ((uint32_t)0x00008000) /*!<External trigger polarity */
mbed_official 340:28d1f895c6fe 4647
mbed_official 340:28d1f895c6fe 4648 /******************* Bit definition for TIM_DIER register ******************/
mbed_official 340:28d1f895c6fe 4649 #define TIM_DIER_UIE ((uint32_t)0x00000001) /*!<Update interrupt enable */
mbed_official 340:28d1f895c6fe 4650 #define TIM_DIER_CC1IE ((uint32_t)0x00000002) /*!<Capture/Compare 1 interrupt enable */
mbed_official 340:28d1f895c6fe 4651 #define TIM_DIER_CC2IE ((uint32_t)0x00000004) /*!<Capture/Compare 2 interrupt enable */
mbed_official 340:28d1f895c6fe 4652 #define TIM_DIER_CC3IE ((uint32_t)0x00000008) /*!<Capture/Compare 3 interrupt enable */
mbed_official 340:28d1f895c6fe 4653 #define TIM_DIER_CC4IE ((uint32_t)0x00000010) /*!<Capture/Compare 4 interrupt enable */
mbed_official 340:28d1f895c6fe 4654 #define TIM_DIER_COMIE ((uint32_t)0x00000020) /*!<COM interrupt enable */
mbed_official 340:28d1f895c6fe 4655 #define TIM_DIER_TIE ((uint32_t)0x00000040) /*!<Trigger interrupt enable */
mbed_official 340:28d1f895c6fe 4656 #define TIM_DIER_BIE ((uint32_t)0x00000080) /*!<Break interrupt enable */
mbed_official 340:28d1f895c6fe 4657 #define TIM_DIER_UDE ((uint32_t)0x00000100) /*!<Update DMA request enable */
mbed_official 340:28d1f895c6fe 4658 #define TIM_DIER_CC1DE ((uint32_t)0x00000200) /*!<Capture/Compare 1 DMA request enable */
mbed_official 340:28d1f895c6fe 4659 #define TIM_DIER_CC2DE ((uint32_t)0x00000400) /*!<Capture/Compare 2 DMA request enable */
mbed_official 340:28d1f895c6fe 4660 #define TIM_DIER_CC3DE ((uint32_t)0x00000800) /*!<Capture/Compare 3 DMA request enable */
mbed_official 340:28d1f895c6fe 4661 #define TIM_DIER_CC4DE ((uint32_t)0x00001000) /*!<Capture/Compare 4 DMA request enable */
mbed_official 340:28d1f895c6fe 4662 #define TIM_DIER_COMDE ((uint32_t)0x00002000) /*!<COM DMA request enable */
mbed_official 340:28d1f895c6fe 4663 #define TIM_DIER_TDE ((uint32_t)0x00004000) /*!<Trigger DMA request enable */
mbed_official 340:28d1f895c6fe 4664
mbed_official 340:28d1f895c6fe 4665 /******************** Bit definition for TIM_SR register *******************/
mbed_official 340:28d1f895c6fe 4666 #define TIM_SR_UIF ((uint32_t)0x00000001) /*!<Update interrupt Flag */
mbed_official 340:28d1f895c6fe 4667 #define TIM_SR_CC1IF ((uint32_t)0x00000002) /*!<Capture/Compare 1 interrupt Flag */
mbed_official 340:28d1f895c6fe 4668 #define TIM_SR_CC2IF ((uint32_t)0x00000004) /*!<Capture/Compare 2 interrupt Flag */
mbed_official 340:28d1f895c6fe 4669 #define TIM_SR_CC3IF ((uint32_t)0x00000008) /*!<Capture/Compare 3 interrupt Flag */
mbed_official 340:28d1f895c6fe 4670 #define TIM_SR_CC4IF ((uint32_t)0x00000010) /*!<Capture/Compare 4 interrupt Flag */
mbed_official 340:28d1f895c6fe 4671 #define TIM_SR_COMIF ((uint32_t)0x00000020) /*!<COM interrupt Flag */
mbed_official 340:28d1f895c6fe 4672 #define TIM_SR_TIF ((uint32_t)0x00000040) /*!<Trigger interrupt Flag */
mbed_official 340:28d1f895c6fe 4673 #define TIM_SR_BIF ((uint32_t)0x00000080) /*!<Break interrupt Flag */
mbed_official 340:28d1f895c6fe 4674 #define TIM_SR_CC1OF ((uint32_t)0x00000200) /*!<Capture/Compare 1 Overcapture Flag */
mbed_official 340:28d1f895c6fe 4675 #define TIM_SR_CC2OF ((uint32_t)0x00000400) /*!<Capture/Compare 2 Overcapture Flag */
mbed_official 340:28d1f895c6fe 4676 #define TIM_SR_CC3OF ((uint32_t)0x00000800) /*!<Capture/Compare 3 Overcapture Flag */
mbed_official 340:28d1f895c6fe 4677 #define TIM_SR_CC4OF ((uint32_t)0x00001000) /*!<Capture/Compare 4 Overcapture Flag */
mbed_official 340:28d1f895c6fe 4678
mbed_official 340:28d1f895c6fe 4679 /******************* Bit definition for TIM_EGR register *******************/
mbed_official 340:28d1f895c6fe 4680 #define TIM_EGR_UG ((uint32_t)0x00000001) /*!<Update Generation */
mbed_official 340:28d1f895c6fe 4681 #define TIM_EGR_CC1G ((uint32_t)0x00000002) /*!<Capture/Compare 1 Generation */
mbed_official 340:28d1f895c6fe 4682 #define TIM_EGR_CC2G ((uint32_t)0x00000004) /*!<Capture/Compare 2 Generation */
mbed_official 340:28d1f895c6fe 4683 #define TIM_EGR_CC3G ((uint32_t)0x00000008) /*!<Capture/Compare 3 Generation */
mbed_official 340:28d1f895c6fe 4684 #define TIM_EGR_CC4G ((uint32_t)0x00000010) /*!<Capture/Compare 4 Generation */
mbed_official 340:28d1f895c6fe 4685 #define TIM_EGR_COMG ((uint32_t)0x00000020) /*!<Capture/Compare Control Update Generation */
mbed_official 340:28d1f895c6fe 4686 #define TIM_EGR_TG ((uint32_t)0x00000040) /*!<Trigger Generation */
mbed_official 340:28d1f895c6fe 4687 #define TIM_EGR_BG ((uint32_t)0x00000080) /*!<Break Generation */
mbed_official 340:28d1f895c6fe 4688
mbed_official 340:28d1f895c6fe 4689 /****************** Bit definition for TIM_CCMR1 register ******************/
mbed_official 340:28d1f895c6fe 4690 #define TIM_CCMR1_CC1S ((uint32_t)0x00000003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
mbed_official 340:28d1f895c6fe 4691 #define TIM_CCMR1_CC1S_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 340:28d1f895c6fe 4692 #define TIM_CCMR1_CC1S_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 340:28d1f895c6fe 4693
mbed_official 340:28d1f895c6fe 4694 #define TIM_CCMR1_OC1FE ((uint32_t)0x00000004) /*!<Output Compare 1 Fast enable */
mbed_official 340:28d1f895c6fe 4695 #define TIM_CCMR1_OC1PE ((uint32_t)0x00000008) /*!<Output Compare 1 Preload enable */
mbed_official 340:28d1f895c6fe 4696
mbed_official 340:28d1f895c6fe 4697 #define TIM_CCMR1_OC1M ((uint32_t)0x00000070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
mbed_official 340:28d1f895c6fe 4698 #define TIM_CCMR1_OC1M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 340:28d1f895c6fe 4699 #define TIM_CCMR1_OC1M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 340:28d1f895c6fe 4700 #define TIM_CCMR1_OC1M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 340:28d1f895c6fe 4701
mbed_official 340:28d1f895c6fe 4702 #define TIM_CCMR1_OC1CE ((uint32_t)0x00000080) /*!<Output Compare 1Clear Enable */
mbed_official 340:28d1f895c6fe 4703
mbed_official 340:28d1f895c6fe 4704 #define TIM_CCMR1_CC2S ((uint32_t)0x00000300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
mbed_official 340:28d1f895c6fe 4705 #define TIM_CCMR1_CC2S_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 340:28d1f895c6fe 4706 #define TIM_CCMR1_CC2S_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 340:28d1f895c6fe 4707
mbed_official 340:28d1f895c6fe 4708 #define TIM_CCMR1_OC2FE ((uint32_t)0x00000400) /*!<Output Compare 2 Fast enable */
mbed_official 340:28d1f895c6fe 4709 #define TIM_CCMR1_OC2PE ((uint32_t)0x00000800) /*!<Output Compare 2 Preload enable */
mbed_official 340:28d1f895c6fe 4710
mbed_official 340:28d1f895c6fe 4711 #define TIM_CCMR1_OC2M ((uint32_t)0x00007000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
mbed_official 340:28d1f895c6fe 4712 #define TIM_CCMR1_OC2M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
mbed_official 340:28d1f895c6fe 4713 #define TIM_CCMR1_OC2M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
mbed_official 340:28d1f895c6fe 4714 #define TIM_CCMR1_OC2M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
mbed_official 340:28d1f895c6fe 4715
mbed_official 340:28d1f895c6fe 4716 #define TIM_CCMR1_OC2CE ((uint32_t)0x00008000) /*!<Output Compare 2 Clear Enable */
mbed_official 340:28d1f895c6fe 4717
mbed_official 340:28d1f895c6fe 4718 /*---------------------------------------------------------------------------*/
mbed_official 340:28d1f895c6fe 4719
mbed_official 340:28d1f895c6fe 4720 #define TIM_CCMR1_IC1PSC ((uint32_t)0x0000000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
mbed_official 340:28d1f895c6fe 4721 #define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x00000004) /*!<Bit 0 */
mbed_official 340:28d1f895c6fe 4722 #define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x00000008) /*!<Bit 1 */
mbed_official 340:28d1f895c6fe 4723
mbed_official 340:28d1f895c6fe 4724 #define TIM_CCMR1_IC1F ((uint32_t)0x000000F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
mbed_official 340:28d1f895c6fe 4725 #define TIM_CCMR1_IC1F_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 340:28d1f895c6fe 4726 #define TIM_CCMR1_IC1F_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 340:28d1f895c6fe 4727 #define TIM_CCMR1_IC1F_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 340:28d1f895c6fe 4728 #define TIM_CCMR1_IC1F_3 ((uint32_t)0x00000080) /*!<Bit 3 */
mbed_official 340:28d1f895c6fe 4729
mbed_official 340:28d1f895c6fe 4730 #define TIM_CCMR1_IC2PSC ((uint32_t)0x00000C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
mbed_official 340:28d1f895c6fe 4731 #define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x00000400) /*!<Bit 0 */
mbed_official 340:28d1f895c6fe 4732 #define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x00000800) /*!<Bit 1 */
mbed_official 340:28d1f895c6fe 4733
mbed_official 340:28d1f895c6fe 4734 #define TIM_CCMR1_IC2F ((uint32_t)0x0000F000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
mbed_official 340:28d1f895c6fe 4735 #define TIM_CCMR1_IC2F_0 ((uint32_t)0x00001000) /*!<Bit 0 */
mbed_official 340:28d1f895c6fe 4736 #define TIM_CCMR1_IC2F_1 ((uint32_t)0x00002000) /*!<Bit 1 */
mbed_official 340:28d1f895c6fe 4737 #define TIM_CCMR1_IC2F_2 ((uint32_t)0x00004000) /*!<Bit 2 */
mbed_official 340:28d1f895c6fe 4738 #define TIM_CCMR1_IC2F_3 ((uint32_t)0x00008000) /*!<Bit 3 */
mbed_official 340:28d1f895c6fe 4739
mbed_official 340:28d1f895c6fe 4740 /****************** Bit definition for TIM_CCMR2 register ******************/
mbed_official 340:28d1f895c6fe 4741 #define TIM_CCMR2_CC3S ((uint32_t)0x00000003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
mbed_official 340:28d1f895c6fe 4742 #define TIM_CCMR2_CC3S_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 340:28d1f895c6fe 4743 #define TIM_CCMR2_CC3S_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 340:28d1f895c6fe 4744
mbed_official 340:28d1f895c6fe 4745 #define TIM_CCMR2_OC3FE ((uint32_t)0x00000004) /*!<Output Compare 3 Fast enable */
mbed_official 340:28d1f895c6fe 4746 #define TIM_CCMR2_OC3PE ((uint32_t)0x00000008) /*!<Output Compare 3 Preload enable */
mbed_official 340:28d1f895c6fe 4747
mbed_official 340:28d1f895c6fe 4748 #define TIM_CCMR2_OC3M ((uint32_t)0x00000070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
mbed_official 340:28d1f895c6fe 4749 #define TIM_CCMR2_OC3M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 340:28d1f895c6fe 4750 #define TIM_CCMR2_OC3M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 340:28d1f895c6fe 4751 #define TIM_CCMR2_OC3M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 340:28d1f895c6fe 4752
mbed_official 340:28d1f895c6fe 4753 #define TIM_CCMR2_OC3CE ((uint32_t)0x00000080) /*!<Output Compare 3 Clear Enable */
mbed_official 340:28d1f895c6fe 4754
mbed_official 340:28d1f895c6fe 4755 #define TIM_CCMR2_CC4S ((uint32_t)0x00000300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
mbed_official 340:28d1f895c6fe 4756 #define TIM_CCMR2_CC4S_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 340:28d1f895c6fe 4757 #define TIM_CCMR2_CC4S_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 340:28d1f895c6fe 4758
mbed_official 340:28d1f895c6fe 4759 #define TIM_CCMR2_OC4FE ((uint32_t)0x00000400) /*!<Output Compare 4 Fast enable */
mbed_official 340:28d1f895c6fe 4760 #define TIM_CCMR2_OC4PE ((uint32_t)0x00000800) /*!<Output Compare 4 Preload enable */
mbed_official 340:28d1f895c6fe 4761
mbed_official 340:28d1f895c6fe 4762 #define TIM_CCMR2_OC4M ((uint32_t)0x00007000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
mbed_official 340:28d1f895c6fe 4763 #define TIM_CCMR2_OC4M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
mbed_official 340:28d1f895c6fe 4764 #define TIM_CCMR2_OC4M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
mbed_official 340:28d1f895c6fe 4765 #define TIM_CCMR2_OC4M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
mbed_official 340:28d1f895c6fe 4766
mbed_official 340:28d1f895c6fe 4767 #define TIM_CCMR2_OC4CE ((uint32_t)0x00008000) /*!<Output Compare 4 Clear Enable */
mbed_official 340:28d1f895c6fe 4768
mbed_official 340:28d1f895c6fe 4769 /*---------------------------------------------------------------------------*/
mbed_official 340:28d1f895c6fe 4770
mbed_official 340:28d1f895c6fe 4771 #define TIM_CCMR2_IC3PSC ((uint32_t)0x0000000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
mbed_official 340:28d1f895c6fe 4772 #define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x00000004) /*!<Bit 0 */
mbed_official 340:28d1f895c6fe 4773 #define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x00000008) /*!<Bit 1 */
mbed_official 340:28d1f895c6fe 4774
mbed_official 340:28d1f895c6fe 4775 #define TIM_CCMR2_IC3F ((uint32_t)0x000000F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
mbed_official 340:28d1f895c6fe 4776 #define TIM_CCMR2_IC3F_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 340:28d1f895c6fe 4777 #define TIM_CCMR2_IC3F_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 340:28d1f895c6fe 4778 #define TIM_CCMR2_IC3F_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 340:28d1f895c6fe 4779 #define TIM_CCMR2_IC3F_3 ((uint32_t)0x00000080) /*!<Bit 3 */
mbed_official 340:28d1f895c6fe 4780
mbed_official 340:28d1f895c6fe 4781 #define TIM_CCMR2_IC4PSC ((uint32_t)0x00000C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
mbed_official 340:28d1f895c6fe 4782 #define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x00000400) /*!<Bit 0 */
mbed_official 340:28d1f895c6fe 4783 #define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x00000800) /*!<Bit 1 */
mbed_official 340:28d1f895c6fe 4784
mbed_official 340:28d1f895c6fe 4785 #define TIM_CCMR2_IC4F ((uint32_t)0x0000F000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
mbed_official 340:28d1f895c6fe 4786 #define TIM_CCMR2_IC4F_0 ((uint32_t)0x00001000) /*!<Bit 0 */
mbed_official 340:28d1f895c6fe 4787 #define TIM_CCMR2_IC4F_1 ((uint32_t)0x00002000) /*!<Bit 1 */
mbed_official 340:28d1f895c6fe 4788 #define TIM_CCMR2_IC4F_2 ((uint32_t)0x00004000) /*!<Bit 2 */
mbed_official 340:28d1f895c6fe 4789 #define TIM_CCMR2_IC4F_3 ((uint32_t)0x00008000) /*!<Bit 3 */
mbed_official 340:28d1f895c6fe 4790
mbed_official 340:28d1f895c6fe 4791 /******************* Bit definition for TIM_CCER register ******************/
mbed_official 340:28d1f895c6fe 4792 #define TIM_CCER_CC1E ((uint32_t)0x00000001) /*!<Capture/Compare 1 output enable */
mbed_official 340:28d1f895c6fe 4793 #define TIM_CCER_CC1P ((uint32_t)0x00000002) /*!<Capture/Compare 1 output Polarity */
mbed_official 340:28d1f895c6fe 4794 #define TIM_CCER_CC1NE ((uint32_t)0x00000004) /*!<Capture/Compare 1 Complementary output enable */
mbed_official 340:28d1f895c6fe 4795 #define TIM_CCER_CC1NP ((uint32_t)0x00000008) /*!<Capture/Compare 1 Complementary output Polarity */
mbed_official 340:28d1f895c6fe 4796 #define TIM_CCER_CC2E ((uint32_t)0x00000010) /*!<Capture/Compare 2 output enable */
mbed_official 340:28d1f895c6fe 4797 #define TIM_CCER_CC2P ((uint32_t)0x00000020) /*!<Capture/Compare 2 output Polarity */
mbed_official 340:28d1f895c6fe 4798 #define TIM_CCER_CC2NE ((uint32_t)0x00000040) /*!<Capture/Compare 2 Complementary output enable */
mbed_official 340:28d1f895c6fe 4799 #define TIM_CCER_CC2NP ((uint32_t)0x00000080) /*!<Capture/Compare 2 Complementary output Polarity */
mbed_official 340:28d1f895c6fe 4800 #define TIM_CCER_CC3E ((uint32_t)0x00000100) /*!<Capture/Compare 3 output enable */
mbed_official 340:28d1f895c6fe 4801 #define TIM_CCER_CC3P ((uint32_t)0x00000200) /*!<Capture/Compare 3 output Polarity */
mbed_official 340:28d1f895c6fe 4802 #define TIM_CCER_CC3NE ((uint32_t)0x00000400) /*!<Capture/Compare 3 Complementary output enable */
mbed_official 340:28d1f895c6fe 4803 #define TIM_CCER_CC3NP ((uint32_t)0x00000800) /*!<Capture/Compare 3 Complementary output Polarity */
mbed_official 340:28d1f895c6fe 4804 #define TIM_CCER_CC4E ((uint32_t)0x00001000) /*!<Capture/Compare 4 output enable */
mbed_official 340:28d1f895c6fe 4805 #define TIM_CCER_CC4P ((uint32_t)0x00002000) /*!<Capture/Compare 4 output Polarity */
mbed_official 340:28d1f895c6fe 4806 #define TIM_CCER_CC4NP ((uint32_t)0x00008000) /*!<Capture/Compare 4 Complementary output Polarity */
mbed_official 340:28d1f895c6fe 4807
mbed_official 340:28d1f895c6fe 4808 /******************* Bit definition for TIM_CNT register *******************/
mbed_official 340:28d1f895c6fe 4809 #define TIM_CNT_CNT ((uint32_t)0xFFFFFFFF) /*!<Counter Value */
mbed_official 340:28d1f895c6fe 4810
mbed_official 340:28d1f895c6fe 4811 /******************* Bit definition for TIM_PSC register *******************/
mbed_official 340:28d1f895c6fe 4812 #define TIM_PSC_PSC ((uint32_t)0x0000FFFF) /*!<Prescaler Value */
mbed_official 340:28d1f895c6fe 4813
mbed_official 340:28d1f895c6fe 4814 /******************* Bit definition for TIM_ARR register *******************/
mbed_official 340:28d1f895c6fe 4815 #define TIM_ARR_ARR ((uint32_t)0xFFFFFFFF) /*!<actual auto-reload Value */
mbed_official 340:28d1f895c6fe 4816
mbed_official 340:28d1f895c6fe 4817 /******************* Bit definition for TIM_RCR register *******************/
mbed_official 340:28d1f895c6fe 4818 #define TIM_RCR_REP ((uint32_t)0x000000FF) /*!<Repetition Counter Value */
mbed_official 340:28d1f895c6fe 4819
mbed_official 340:28d1f895c6fe 4820 /******************* Bit definition for TIM_CCR1 register ******************/
mbed_official 340:28d1f895c6fe 4821 #define TIM_CCR1_CCR1 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 1 Value */
mbed_official 340:28d1f895c6fe 4822
mbed_official 340:28d1f895c6fe 4823 /******************* Bit definition for TIM_CCR2 register ******************/
mbed_official 340:28d1f895c6fe 4824 #define TIM_CCR2_CCR2 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 2 Value */
mbed_official 340:28d1f895c6fe 4825
mbed_official 340:28d1f895c6fe 4826 /******************* Bit definition for TIM_CCR3 register ******************/
mbed_official 340:28d1f895c6fe 4827 #define TIM_CCR3_CCR3 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 3 Value */
mbed_official 340:28d1f895c6fe 4828
mbed_official 340:28d1f895c6fe 4829 /******************* Bit definition for TIM_CCR4 register ******************/
mbed_official 340:28d1f895c6fe 4830 #define TIM_CCR4_CCR4 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 4 Value */
mbed_official 340:28d1f895c6fe 4831
mbed_official 340:28d1f895c6fe 4832 /******************* Bit definition for TIM_BDTR register ******************/
mbed_official 340:28d1f895c6fe 4833 #define TIM_BDTR_DTG ((uint32_t)0x000000FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
mbed_official 340:28d1f895c6fe 4834 #define TIM_BDTR_DTG_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 340:28d1f895c6fe 4835 #define TIM_BDTR_DTG_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 340:28d1f895c6fe 4836 #define TIM_BDTR_DTG_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 340:28d1f895c6fe 4837 #define TIM_BDTR_DTG_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 340:28d1f895c6fe 4838 #define TIM_BDTR_DTG_4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 340:28d1f895c6fe 4839 #define TIM_BDTR_DTG_5 ((uint32_t)0x00000020) /*!<Bit 5 */
mbed_official 340:28d1f895c6fe 4840 #define TIM_BDTR_DTG_6 ((uint32_t)0x00000040) /*!<Bit 6 */
mbed_official 340:28d1f895c6fe 4841 #define TIM_BDTR_DTG_7 ((uint32_t)0x00000080) /*!<Bit 7 */
mbed_official 340:28d1f895c6fe 4842
mbed_official 340:28d1f895c6fe 4843 #define TIM_BDTR_LOCK ((uint32_t)0x00000300) /*!<LOCK[1:0] bits (Lock Configuration) */
mbed_official 340:28d1f895c6fe 4844 #define TIM_BDTR_LOCK_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 340:28d1f895c6fe 4845 #define TIM_BDTR_LOCK_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 340:28d1f895c6fe 4846
mbed_official 340:28d1f895c6fe 4847 #define TIM_BDTR_OSSI ((uint32_t)0x00000400) /*!<Off-State Selection for Idle mode */
mbed_official 340:28d1f895c6fe 4848 #define TIM_BDTR_OSSR ((uint32_t)0x00000800) /*!<Off-State Selection for Run mode */
mbed_official 340:28d1f895c6fe 4849 #define TIM_BDTR_BKE ((uint32_t)0x00001000) /*!<Break enable */
mbed_official 340:28d1f895c6fe 4850 #define TIM_BDTR_BKP ((uint32_t)0x00002000) /*!<Break Polarity */
mbed_official 340:28d1f895c6fe 4851 #define TIM_BDTR_AOE ((uint32_t)0x00004000) /*!<Automatic Output enable */
mbed_official 340:28d1f895c6fe 4852 #define TIM_BDTR_MOE ((uint32_t)0x00008000) /*!<Main Output enable */
mbed_official 340:28d1f895c6fe 4853
mbed_official 340:28d1f895c6fe 4854 /******************* Bit definition for TIM_DCR register *******************/
mbed_official 340:28d1f895c6fe 4855 #define TIM_DCR_DBA ((uint32_t)0x0000001F) /*!<DBA[4:0] bits (DMA Base Address) */
mbed_official 340:28d1f895c6fe 4856 #define TIM_DCR_DBA_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 340:28d1f895c6fe 4857 #define TIM_DCR_DBA_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 340:28d1f895c6fe 4858 #define TIM_DCR_DBA_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 340:28d1f895c6fe 4859 #define TIM_DCR_DBA_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 340:28d1f895c6fe 4860 #define TIM_DCR_DBA_4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 340:28d1f895c6fe 4861
mbed_official 340:28d1f895c6fe 4862 #define TIM_DCR_DBL ((uint32_t)0x00001F00) /*!<DBL[4:0] bits (DMA Burst Length) */
mbed_official 340:28d1f895c6fe 4863 #define TIM_DCR_DBL_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 340:28d1f895c6fe 4864 #define TIM_DCR_DBL_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 340:28d1f895c6fe 4865 #define TIM_DCR_DBL_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 340:28d1f895c6fe 4866 #define TIM_DCR_DBL_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 340:28d1f895c6fe 4867 #define TIM_DCR_DBL_4 ((uint32_t)0x00001000) /*!<Bit 4 */
mbed_official 340:28d1f895c6fe 4868
mbed_official 340:28d1f895c6fe 4869 /******************* Bit definition for TIM_DMAR register ******************/
mbed_official 340:28d1f895c6fe 4870 #define TIM_DMAR_DMAB ((uint32_t)0x0000FFFF) /*!<DMA register for burst accesses */
mbed_official 340:28d1f895c6fe 4871
mbed_official 340:28d1f895c6fe 4872 /******************* Bit definition for TIM14_OR register ********************/
mbed_official 340:28d1f895c6fe 4873 #define TIM14_OR_TI1_RMP ((uint32_t)0x00000003) /*!<TI1_RMP[1:0] bits (TIM14 Input 4 remap) */
mbed_official 340:28d1f895c6fe 4874 #define TIM14_OR_TI1_RMP_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 340:28d1f895c6fe 4875 #define TIM14_OR_TI1_RMP_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 340:28d1f895c6fe 4876
mbed_official 340:28d1f895c6fe 4877 /******************************************************************************/
mbed_official 340:28d1f895c6fe 4878 /* */
mbed_official 340:28d1f895c6fe 4879 /* Touch Sensing Controller (TSC) */
mbed_official 340:28d1f895c6fe 4880 /* */
mbed_official 340:28d1f895c6fe 4881 /******************************************************************************/
mbed_official 340:28d1f895c6fe 4882 /******************* Bit definition for TSC_CR register *********************/
mbed_official 340:28d1f895c6fe 4883 #define TSC_CR_TSCE ((uint32_t)0x00000001) /*!<Touch sensing controller enable */
mbed_official 340:28d1f895c6fe 4884 #define TSC_CR_START ((uint32_t)0x00000002) /*!<Start acquisition */
mbed_official 340:28d1f895c6fe 4885 #define TSC_CR_AM ((uint32_t)0x00000004) /*!<Acquisition mode */
mbed_official 340:28d1f895c6fe 4886 #define TSC_CR_SYNCPOL ((uint32_t)0x00000008) /*!<Synchronization pin polarity */
mbed_official 340:28d1f895c6fe 4887 #define TSC_CR_IODEF ((uint32_t)0x00000010) /*!<IO default mode */
mbed_official 340:28d1f895c6fe 4888
mbed_official 340:28d1f895c6fe 4889 #define TSC_CR_MCV ((uint32_t)0x000000E0) /*!<MCV[2:0] bits (Max Count Value) */
mbed_official 340:28d1f895c6fe 4890 #define TSC_CR_MCV_0 ((uint32_t)0x00000020) /*!<Bit 0 */
mbed_official 340:28d1f895c6fe 4891 #define TSC_CR_MCV_1 ((uint32_t)0x00000040) /*!<Bit 1 */
mbed_official 340:28d1f895c6fe 4892 #define TSC_CR_MCV_2 ((uint32_t)0x00000080) /*!<Bit 2 */
mbed_official 340:28d1f895c6fe 4893
mbed_official 340:28d1f895c6fe 4894 #define TSC_CR_PGPSC ((uint32_t)0x00007000) /*!<PGPSC[2:0] bits (Pulse Generator Prescaler) */
mbed_official 340:28d1f895c6fe 4895 #define TSC_CR_PGPSC_0 ((uint32_t)0x00001000) /*!<Bit 0 */
mbed_official 340:28d1f895c6fe 4896 #define TSC_CR_PGPSC_1 ((uint32_t)0x00002000) /*!<Bit 1 */
mbed_official 340:28d1f895c6fe 4897 #define TSC_CR_PGPSC_2 ((uint32_t)0x00004000) /*!<Bit 2 */
mbed_official 340:28d1f895c6fe 4898
mbed_official 340:28d1f895c6fe 4899 #define TSC_CR_SSPSC ((uint32_t)0x00008000) /*!<Spread Spectrum Prescaler */
mbed_official 340:28d1f895c6fe 4900 #define TSC_CR_SSE ((uint32_t)0x00010000) /*!<Spread Spectrum Enable */
mbed_official 340:28d1f895c6fe 4901
mbed_official 340:28d1f895c6fe 4902 #define TSC_CR_SSD ((uint32_t)0x00FE0000) /*!<SSD[6:0] bits (Spread Spectrum Deviation) */
mbed_official 340:28d1f895c6fe 4903 #define TSC_CR_SSD_0 ((uint32_t)0x00020000) /*!<Bit 0 */
mbed_official 340:28d1f895c6fe 4904 #define TSC_CR_SSD_1 ((uint32_t)0x00040000) /*!<Bit 1 */
mbed_official 340:28d1f895c6fe 4905 #define TSC_CR_SSD_2 ((uint32_t)0x00080000) /*!<Bit 2 */
mbed_official 340:28d1f895c6fe 4906 #define TSC_CR_SSD_3 ((uint32_t)0x00100000) /*!<Bit 3 */
mbed_official 340:28d1f895c6fe 4907 #define TSC_CR_SSD_4 ((uint32_t)0x00200000) /*!<Bit 4 */
mbed_official 340:28d1f895c6fe 4908 #define TSC_CR_SSD_5 ((uint32_t)0x00400000) /*!<Bit 5 */
mbed_official 340:28d1f895c6fe 4909 #define TSC_CR_SSD_6 ((uint32_t)0x00800000) /*!<Bit 6 */
mbed_official 340:28d1f895c6fe 4910
mbed_official 340:28d1f895c6fe 4911 #define TSC_CR_CTPL ((uint32_t)0x0F000000) /*!<CTPL[3:0] bits (Charge Transfer pulse low) */
mbed_official 340:28d1f895c6fe 4912 #define TSC_CR_CTPL_0 ((uint32_t)0x01000000) /*!<Bit 0 */
mbed_official 340:28d1f895c6fe 4913 #define TSC_CR_CTPL_1 ((uint32_t)0x02000000) /*!<Bit 1 */
mbed_official 340:28d1f895c6fe 4914 #define TSC_CR_CTPL_2 ((uint32_t)0x04000000) /*!<Bit 2 */
mbed_official 340:28d1f895c6fe 4915 #define TSC_CR_CTPL_3 ((uint32_t)0x08000000) /*!<Bit 3 */
mbed_official 340:28d1f895c6fe 4916
mbed_official 340:28d1f895c6fe 4917 #define TSC_CR_CTPH ((uint32_t)0xF0000000) /*!<CTPH[3:0] bits (Charge Transfer pulse high) */
mbed_official 340:28d1f895c6fe 4918 #define TSC_CR_CTPH_0 ((uint32_t)0x10000000) /*!<Bit 0 */
mbed_official 340:28d1f895c6fe 4919 #define TSC_CR_CTPH_1 ((uint32_t)0x20000000) /*!<Bit 1 */
mbed_official 340:28d1f895c6fe 4920 #define TSC_CR_CTPH_2 ((uint32_t)0x40000000) /*!<Bit 2 */
mbed_official 340:28d1f895c6fe 4921 #define TSC_CR_CTPH_3 ((uint32_t)0x80000000) /*!<Bit 3 */
mbed_official 340:28d1f895c6fe 4922
mbed_official 340:28d1f895c6fe 4923 /******************* Bit definition for TSC_IER register ********************/
mbed_official 340:28d1f895c6fe 4924 #define TSC_IER_EOAIE ((uint32_t)0x00000001) /*!<End of acquisition interrupt enable */
mbed_official 340:28d1f895c6fe 4925 #define TSC_IER_MCEIE ((uint32_t)0x00000002) /*!<Max count error interrupt enable */
mbed_official 340:28d1f895c6fe 4926
mbed_official 340:28d1f895c6fe 4927 /******************* Bit definition for TSC_ICR register ********************/
mbed_official 340:28d1f895c6fe 4928 #define TSC_ICR_EOAIC ((uint32_t)0x00000001) /*!<End of acquisition interrupt clear */
mbed_official 340:28d1f895c6fe 4929 #define TSC_ICR_MCEIC ((uint32_t)0x00000002) /*!<Max count error interrupt clear */
mbed_official 340:28d1f895c6fe 4930
mbed_official 340:28d1f895c6fe 4931 /******************* Bit definition for TSC_ISR register ********************/
mbed_official 340:28d1f895c6fe 4932 #define TSC_ISR_EOAF ((uint32_t)0x00000001) /*!<End of acquisition flag */
mbed_official 340:28d1f895c6fe 4933 #define TSC_ISR_MCEF ((uint32_t)0x00000002) /*!<Max count error flag */
mbed_official 340:28d1f895c6fe 4934
mbed_official 340:28d1f895c6fe 4935 /******************* Bit definition for TSC_IOHCR register ******************/
mbed_official 340:28d1f895c6fe 4936 #define TSC_IOHCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 schmitt trigger hysteresis mode */
mbed_official 340:28d1f895c6fe 4937 #define TSC_IOHCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 schmitt trigger hysteresis mode */
mbed_official 340:28d1f895c6fe 4938 #define TSC_IOHCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 schmitt trigger hysteresis mode */
mbed_official 340:28d1f895c6fe 4939 #define TSC_IOHCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 schmitt trigger hysteresis mode */
mbed_official 340:28d1f895c6fe 4940 #define TSC_IOHCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 schmitt trigger hysteresis mode */
mbed_official 340:28d1f895c6fe 4941 #define TSC_IOHCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 schmitt trigger hysteresis mode */
mbed_official 340:28d1f895c6fe 4942 #define TSC_IOHCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 schmitt trigger hysteresis mode */
mbed_official 340:28d1f895c6fe 4943 #define TSC_IOHCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 schmitt trigger hysteresis mode */
mbed_official 340:28d1f895c6fe 4944 #define TSC_IOHCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 schmitt trigger hysteresis mode */
mbed_official 340:28d1f895c6fe 4945 #define TSC_IOHCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 schmitt trigger hysteresis mode */
mbed_official 340:28d1f895c6fe 4946 #define TSC_IOHCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 schmitt trigger hysteresis mode */
mbed_official 340:28d1f895c6fe 4947 #define TSC_IOHCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 schmitt trigger hysteresis mode */
mbed_official 340:28d1f895c6fe 4948 #define TSC_IOHCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 schmitt trigger hysteresis mode */
mbed_official 340:28d1f895c6fe 4949 #define TSC_IOHCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 schmitt trigger hysteresis mode */
mbed_official 340:28d1f895c6fe 4950 #define TSC_IOHCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 schmitt trigger hysteresis mode */
mbed_official 340:28d1f895c6fe 4951 #define TSC_IOHCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 schmitt trigger hysteresis mode */
mbed_official 340:28d1f895c6fe 4952 #define TSC_IOHCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 schmitt trigger hysteresis mode */
mbed_official 340:28d1f895c6fe 4953 #define TSC_IOHCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 schmitt trigger hysteresis mode */
mbed_official 340:28d1f895c6fe 4954 #define TSC_IOHCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 schmitt trigger hysteresis mode */
mbed_official 340:28d1f895c6fe 4955 #define TSC_IOHCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 schmitt trigger hysteresis mode */
mbed_official 340:28d1f895c6fe 4956 #define TSC_IOHCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 schmitt trigger hysteresis mode */
mbed_official 340:28d1f895c6fe 4957 #define TSC_IOHCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 schmitt trigger hysteresis mode */
mbed_official 340:28d1f895c6fe 4958 #define TSC_IOHCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 schmitt trigger hysteresis mode */
mbed_official 340:28d1f895c6fe 4959 #define TSC_IOHCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 schmitt trigger hysteresis mode */
mbed_official 340:28d1f895c6fe 4960 #define TSC_IOHCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 schmitt trigger hysteresis mode */
mbed_official 340:28d1f895c6fe 4961 #define TSC_IOHCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 schmitt trigger hysteresis mode */
mbed_official 340:28d1f895c6fe 4962 #define TSC_IOHCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 schmitt trigger hysteresis mode */
mbed_official 340:28d1f895c6fe 4963 #define TSC_IOHCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 schmitt trigger hysteresis mode */
mbed_official 340:28d1f895c6fe 4964 #define TSC_IOHCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 schmitt trigger hysteresis mode */
mbed_official 340:28d1f895c6fe 4965 #define TSC_IOHCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 schmitt trigger hysteresis mode */
mbed_official 340:28d1f895c6fe 4966 #define TSC_IOHCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 schmitt trigger hysteresis mode */
mbed_official 340:28d1f895c6fe 4967 #define TSC_IOHCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 schmitt trigger hysteresis mode */
mbed_official 340:28d1f895c6fe 4968
mbed_official 340:28d1f895c6fe 4969 /******************* Bit definition for TSC_IOASCR register *****************/
mbed_official 340:28d1f895c6fe 4970 #define TSC_IOASCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 analog switch enable */
mbed_official 340:28d1f895c6fe 4971 #define TSC_IOASCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 analog switch enable */
mbed_official 340:28d1f895c6fe 4972 #define TSC_IOASCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 analog switch enable */
mbed_official 340:28d1f895c6fe 4973 #define TSC_IOASCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 analog switch enable */
mbed_official 340:28d1f895c6fe 4974 #define TSC_IOASCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 analog switch enable */
mbed_official 340:28d1f895c6fe 4975 #define TSC_IOASCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 analog switch enable */
mbed_official 340:28d1f895c6fe 4976 #define TSC_IOASCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 analog switch enable */
mbed_official 340:28d1f895c6fe 4977 #define TSC_IOASCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 analog switch enable */
mbed_official 340:28d1f895c6fe 4978 #define TSC_IOASCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 analog switch enable */
mbed_official 340:28d1f895c6fe 4979 #define TSC_IOASCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 analog switch enable */
mbed_official 340:28d1f895c6fe 4980 #define TSC_IOASCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 analog switch enable */
mbed_official 340:28d1f895c6fe 4981 #define TSC_IOASCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 analog switch enable */
mbed_official 340:28d1f895c6fe 4982 #define TSC_IOASCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 analog switch enable */
mbed_official 340:28d1f895c6fe 4983 #define TSC_IOASCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 analog switch enable */
mbed_official 340:28d1f895c6fe 4984 #define TSC_IOASCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 analog switch enable */
mbed_official 340:28d1f895c6fe 4985 #define TSC_IOASCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 analog switch enable */
mbed_official 340:28d1f895c6fe 4986 #define TSC_IOASCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 analog switch enable */
mbed_official 340:28d1f895c6fe 4987 #define TSC_IOASCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 analog switch enable */
mbed_official 340:28d1f895c6fe 4988 #define TSC_IOASCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 analog switch enable */
mbed_official 340:28d1f895c6fe 4989 #define TSC_IOASCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 analog switch enable */
mbed_official 340:28d1f895c6fe 4990 #define TSC_IOASCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 analog switch enable */
mbed_official 340:28d1f895c6fe 4991 #define TSC_IOASCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 analog switch enable */
mbed_official 340:28d1f895c6fe 4992 #define TSC_IOASCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 analog switch enable */
mbed_official 340:28d1f895c6fe 4993 #define TSC_IOASCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 analog switch enable */
mbed_official 340:28d1f895c6fe 4994 #define TSC_IOASCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 analog switch enable */
mbed_official 340:28d1f895c6fe 4995 #define TSC_IOASCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 analog switch enable */
mbed_official 340:28d1f895c6fe 4996 #define TSC_IOASCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 analog switch enable */
mbed_official 340:28d1f895c6fe 4997 #define TSC_IOASCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 analog switch enable */
mbed_official 340:28d1f895c6fe 4998 #define TSC_IOASCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 analog switch enable */
mbed_official 340:28d1f895c6fe 4999 #define TSC_IOASCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 analog switch enable */
mbed_official 340:28d1f895c6fe 5000 #define TSC_IOASCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 analog switch enable */
mbed_official 340:28d1f895c6fe 5001 #define TSC_IOASCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 analog switch enable */
mbed_official 340:28d1f895c6fe 5002
mbed_official 340:28d1f895c6fe 5003 /******************* Bit definition for TSC_IOSCR register ******************/
mbed_official 340:28d1f895c6fe 5004 #define TSC_IOSCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 sampling mode */
mbed_official 340:28d1f895c6fe 5005 #define TSC_IOSCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 sampling mode */
mbed_official 340:28d1f895c6fe 5006 #define TSC_IOSCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 sampling mode */
mbed_official 340:28d1f895c6fe 5007 #define TSC_IOSCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 sampling mode */
mbed_official 340:28d1f895c6fe 5008 #define TSC_IOSCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 sampling mode */
mbed_official 340:28d1f895c6fe 5009 #define TSC_IOSCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 sampling mode */
mbed_official 340:28d1f895c6fe 5010 #define TSC_IOSCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 sampling mode */
mbed_official 340:28d1f895c6fe 5011 #define TSC_IOSCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 sampling mode */
mbed_official 340:28d1f895c6fe 5012 #define TSC_IOSCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 sampling mode */
mbed_official 340:28d1f895c6fe 5013 #define TSC_IOSCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 sampling mode */
mbed_official 340:28d1f895c6fe 5014 #define TSC_IOSCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 sampling mode */
mbed_official 340:28d1f895c6fe 5015 #define TSC_IOSCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 sampling mode */
mbed_official 340:28d1f895c6fe 5016 #define TSC_IOSCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 sampling mode */
mbed_official 340:28d1f895c6fe 5017 #define TSC_IOSCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 sampling mode */
mbed_official 340:28d1f895c6fe 5018 #define TSC_IOSCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 sampling mode */
mbed_official 340:28d1f895c6fe 5019 #define TSC_IOSCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 sampling mode */
mbed_official 340:28d1f895c6fe 5020 #define TSC_IOSCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 sampling mode */
mbed_official 340:28d1f895c6fe 5021 #define TSC_IOSCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 sampling mode */
mbed_official 340:28d1f895c6fe 5022 #define TSC_IOSCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 sampling mode */
mbed_official 340:28d1f895c6fe 5023 #define TSC_IOSCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 sampling mode */
mbed_official 340:28d1f895c6fe 5024 #define TSC_IOSCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 sampling mode */
mbed_official 340:28d1f895c6fe 5025 #define TSC_IOSCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 sampling mode */
mbed_official 340:28d1f895c6fe 5026 #define TSC_IOSCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 sampling mode */
mbed_official 340:28d1f895c6fe 5027 #define TSC_IOSCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 sampling mode */
mbed_official 340:28d1f895c6fe 5028 #define TSC_IOSCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 sampling mode */
mbed_official 340:28d1f895c6fe 5029 #define TSC_IOSCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 sampling mode */
mbed_official 340:28d1f895c6fe 5030 #define TSC_IOSCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 sampling mode */
mbed_official 340:28d1f895c6fe 5031 #define TSC_IOSCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 sampling mode */
mbed_official 340:28d1f895c6fe 5032 #define TSC_IOSCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 sampling mode */
mbed_official 340:28d1f895c6fe 5033 #define TSC_IOSCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 sampling mode */
mbed_official 340:28d1f895c6fe 5034 #define TSC_IOSCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 sampling mode */
mbed_official 340:28d1f895c6fe 5035 #define TSC_IOSCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 sampling mode */
mbed_official 340:28d1f895c6fe 5036
mbed_official 340:28d1f895c6fe 5037 /******************* Bit definition for TSC_IOCCR register ******************/
mbed_official 340:28d1f895c6fe 5038 #define TSC_IOCCR_G1_IO1 ((uint32_t)0x00000001) /*!<GROUP1_IO1 channel mode */
mbed_official 340:28d1f895c6fe 5039 #define TSC_IOCCR_G1_IO2 ((uint32_t)0x00000002) /*!<GROUP1_IO2 channel mode */
mbed_official 340:28d1f895c6fe 5040 #define TSC_IOCCR_G1_IO3 ((uint32_t)0x00000004) /*!<GROUP1_IO3 channel mode */
mbed_official 340:28d1f895c6fe 5041 #define TSC_IOCCR_G1_IO4 ((uint32_t)0x00000008) /*!<GROUP1_IO4 channel mode */
mbed_official 340:28d1f895c6fe 5042 #define TSC_IOCCR_G2_IO1 ((uint32_t)0x00000010) /*!<GROUP2_IO1 channel mode */
mbed_official 340:28d1f895c6fe 5043 #define TSC_IOCCR_G2_IO2 ((uint32_t)0x00000020) /*!<GROUP2_IO2 channel mode */
mbed_official 340:28d1f895c6fe 5044 #define TSC_IOCCR_G2_IO3 ((uint32_t)0x00000040) /*!<GROUP2_IO3 channel mode */
mbed_official 340:28d1f895c6fe 5045 #define TSC_IOCCR_G2_IO4 ((uint32_t)0x00000080) /*!<GROUP2_IO4 channel mode */
mbed_official 340:28d1f895c6fe 5046 #define TSC_IOCCR_G3_IO1 ((uint32_t)0x00000100) /*!<GROUP3_IO1 channel mode */
mbed_official 340:28d1f895c6fe 5047 #define TSC_IOCCR_G3_IO2 ((uint32_t)0x00000200) /*!<GROUP3_IO2 channel mode */
mbed_official 340:28d1f895c6fe 5048 #define TSC_IOCCR_G3_IO3 ((uint32_t)0x00000400) /*!<GROUP3_IO3 channel mode */
mbed_official 340:28d1f895c6fe 5049 #define TSC_IOCCR_G3_IO4 ((uint32_t)0x00000800) /*!<GROUP3_IO4 channel mode */
mbed_official 340:28d1f895c6fe 5050 #define TSC_IOCCR_G4_IO1 ((uint32_t)0x00001000) /*!<GROUP4_IO1 channel mode */
mbed_official 340:28d1f895c6fe 5051 #define TSC_IOCCR_G4_IO2 ((uint32_t)0x00002000) /*!<GROUP4_IO2 channel mode */
mbed_official 340:28d1f895c6fe 5052 #define TSC_IOCCR_G4_IO3 ((uint32_t)0x00004000) /*!<GROUP4_IO3 channel mode */
mbed_official 340:28d1f895c6fe 5053 #define TSC_IOCCR_G4_IO4 ((uint32_t)0x00008000) /*!<GROUP4_IO4 channel mode */
mbed_official 340:28d1f895c6fe 5054 #define TSC_IOCCR_G5_IO1 ((uint32_t)0x00010000) /*!<GROUP5_IO1 channel mode */
mbed_official 340:28d1f895c6fe 5055 #define TSC_IOCCR_G5_IO2 ((uint32_t)0x00020000) /*!<GROUP5_IO2 channel mode */
mbed_official 340:28d1f895c6fe 5056 #define TSC_IOCCR_G5_IO3 ((uint32_t)0x00040000) /*!<GROUP5_IO3 channel mode */
mbed_official 340:28d1f895c6fe 5057 #define TSC_IOCCR_G5_IO4 ((uint32_t)0x00080000) /*!<GROUP5_IO4 channel mode */
mbed_official 340:28d1f895c6fe 5058 #define TSC_IOCCR_G6_IO1 ((uint32_t)0x00100000) /*!<GROUP6_IO1 channel mode */
mbed_official 340:28d1f895c6fe 5059 #define TSC_IOCCR_G6_IO2 ((uint32_t)0x00200000) /*!<GROUP6_IO2 channel mode */
mbed_official 340:28d1f895c6fe 5060 #define TSC_IOCCR_G6_IO3 ((uint32_t)0x00400000) /*!<GROUP6_IO3 channel mode */
mbed_official 340:28d1f895c6fe 5061 #define TSC_IOCCR_G6_IO4 ((uint32_t)0x00800000) /*!<GROUP6_IO4 channel mode */
mbed_official 340:28d1f895c6fe 5062 #define TSC_IOCCR_G7_IO1 ((uint32_t)0x01000000) /*!<GROUP7_IO1 channel mode */
mbed_official 340:28d1f895c6fe 5063 #define TSC_IOCCR_G7_IO2 ((uint32_t)0x02000000) /*!<GROUP7_IO2 channel mode */
mbed_official 340:28d1f895c6fe 5064 #define TSC_IOCCR_G7_IO3 ((uint32_t)0x04000000) /*!<GROUP7_IO3 channel mode */
mbed_official 340:28d1f895c6fe 5065 #define TSC_IOCCR_G7_IO4 ((uint32_t)0x08000000) /*!<GROUP7_IO4 channel mode */
mbed_official 340:28d1f895c6fe 5066 #define TSC_IOCCR_G8_IO1 ((uint32_t)0x10000000) /*!<GROUP8_IO1 channel mode */
mbed_official 340:28d1f895c6fe 5067 #define TSC_IOCCR_G8_IO2 ((uint32_t)0x20000000) /*!<GROUP8_IO2 channel mode */
mbed_official 340:28d1f895c6fe 5068 #define TSC_IOCCR_G8_IO3 ((uint32_t)0x40000000) /*!<GROUP8_IO3 channel mode */
mbed_official 340:28d1f895c6fe 5069 #define TSC_IOCCR_G8_IO4 ((uint32_t)0x80000000) /*!<GROUP8_IO4 channel mode */
mbed_official 340:28d1f895c6fe 5070
mbed_official 340:28d1f895c6fe 5071 /******************* Bit definition for TSC_IOGCSR register *****************/
mbed_official 340:28d1f895c6fe 5072 #define TSC_IOGCSR_G1E ((uint32_t)0x00000001) /*!<Analog IO GROUP1 enable */
mbed_official 340:28d1f895c6fe 5073 #define TSC_IOGCSR_G2E ((uint32_t)0x00000002) /*!<Analog IO GROUP2 enable */
mbed_official 340:28d1f895c6fe 5074 #define TSC_IOGCSR_G3E ((uint32_t)0x00000004) /*!<Analog IO GROUP3 enable */
mbed_official 340:28d1f895c6fe 5075 #define TSC_IOGCSR_G4E ((uint32_t)0x00000008) /*!<Analog IO GROUP4 enable */
mbed_official 340:28d1f895c6fe 5076 #define TSC_IOGCSR_G5E ((uint32_t)0x00000010) /*!<Analog IO GROUP5 enable */
mbed_official 340:28d1f895c6fe 5077 #define TSC_IOGCSR_G6E ((uint32_t)0x00000020) /*!<Analog IO GROUP6 enable */
mbed_official 340:28d1f895c6fe 5078 #define TSC_IOGCSR_G7E ((uint32_t)0x00000040) /*!<Analog IO GROUP7 enable */
mbed_official 340:28d1f895c6fe 5079 #define TSC_IOGCSR_G8E ((uint32_t)0x00000080) /*!<Analog IO GROUP8 enable */
mbed_official 340:28d1f895c6fe 5080 #define TSC_IOGCSR_G1S ((uint32_t)0x00010000) /*!<Analog IO GROUP1 status */
mbed_official 340:28d1f895c6fe 5081 #define TSC_IOGCSR_G2S ((uint32_t)0x00020000) /*!<Analog IO GROUP2 status */
mbed_official 340:28d1f895c6fe 5082 #define TSC_IOGCSR_G3S ((uint32_t)0x00040000) /*!<Analog IO GROUP3 status */
mbed_official 340:28d1f895c6fe 5083 #define TSC_IOGCSR_G4S ((uint32_t)0x00080000) /*!<Analog IO GROUP4 status */
mbed_official 340:28d1f895c6fe 5084 #define TSC_IOGCSR_G5S ((uint32_t)0x00100000) /*!<Analog IO GROUP5 status */
mbed_official 340:28d1f895c6fe 5085 #define TSC_IOGCSR_G6S ((uint32_t)0x00200000) /*!<Analog IO GROUP6 status */
mbed_official 340:28d1f895c6fe 5086 #define TSC_IOGCSR_G7S ((uint32_t)0x00400000) /*!<Analog IO GROUP7 status */
mbed_official 340:28d1f895c6fe 5087 #define TSC_IOGCSR_G8S ((uint32_t)0x00800000) /*!<Analog IO GROUP8 status */
mbed_official 340:28d1f895c6fe 5088
mbed_official 340:28d1f895c6fe 5089 /******************* Bit definition for TSC_IOGXCR register *****************/
mbed_official 340:28d1f895c6fe 5090 #define TSC_IOGXCR_CNT ((uint32_t)0x00003FFF) /*!<CNT[13:0] bits (Counter value) */
mbed_official 340:28d1f895c6fe 5091
mbed_official 340:28d1f895c6fe 5092 /******************************************************************************/
mbed_official 340:28d1f895c6fe 5093 /* */
mbed_official 340:28d1f895c6fe 5094 /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
mbed_official 340:28d1f895c6fe 5095 /* */
mbed_official 340:28d1f895c6fe 5096 /******************************************************************************/
mbed_official 340:28d1f895c6fe 5097 /****************** Bit definition for USART_CR1 register *******************/
mbed_official 340:28d1f895c6fe 5098 #define USART_CR1_UE ((uint32_t)0x00000001) /*!< USART Enable */
mbed_official 340:28d1f895c6fe 5099 #define USART_CR1_UESM ((uint32_t)0x00000002) /*!< USART Enable in STOP Mode */
mbed_official 340:28d1f895c6fe 5100 #define USART_CR1_RE ((uint32_t)0x00000004) /*!< Receiver Enable */
mbed_official 340:28d1f895c6fe 5101 #define USART_CR1_TE ((uint32_t)0x00000008) /*!< Transmitter Enable */
mbed_official 340:28d1f895c6fe 5102 #define USART_CR1_IDLEIE ((uint32_t)0x00000010) /*!< IDLE Interrupt Enable */
mbed_official 340:28d1f895c6fe 5103 #define USART_CR1_RXNEIE ((uint32_t)0x00000020) /*!< RXNE Interrupt Enable */
mbed_official 340:28d1f895c6fe 5104 #define USART_CR1_TCIE ((uint32_t)0x00000040) /*!< Transmission Complete Interrupt Enable */
mbed_official 340:28d1f895c6fe 5105 #define USART_CR1_TXEIE ((uint32_t)0x00000080) /*!< TXE Interrupt Enable */
mbed_official 340:28d1f895c6fe 5106 #define USART_CR1_PEIE ((uint32_t)0x00000100) /*!< PE Interrupt Enable */
mbed_official 340:28d1f895c6fe 5107 #define USART_CR1_PS ((uint32_t)0x00000200) /*!< Parity Selection */
mbed_official 340:28d1f895c6fe 5108 #define USART_CR1_PCE ((uint32_t)0x00000400) /*!< Parity Control Enable */
mbed_official 340:28d1f895c6fe 5109 #define USART_CR1_WAKE ((uint32_t)0x00000800) /*!< Receiver Wakeup method */
mbed_official 340:28d1f895c6fe 5110 #define USART_CR1_M0 ((uint32_t)0x00001000) /*!< Word length bit 0 */
mbed_official 340:28d1f895c6fe 5111 #define USART_CR1_MME ((uint32_t)0x00002000) /*!< Mute Mode Enable */
mbed_official 340:28d1f895c6fe 5112 #define USART_CR1_CMIE ((uint32_t)0x00004000) /*!< Character match interrupt enable */
mbed_official 340:28d1f895c6fe 5113 #define USART_CR1_OVER8 ((uint32_t)0x00008000) /*!< Oversampling by 8-bit or 16-bit mode */
mbed_official 340:28d1f895c6fe 5114 #define USART_CR1_DEDT ((uint32_t)0x001F0000) /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
mbed_official 340:28d1f895c6fe 5115 #define USART_CR1_DEDT_0 ((uint32_t)0x00010000) /*!< Bit 0 */
mbed_official 340:28d1f895c6fe 5116 #define USART_CR1_DEDT_1 ((uint32_t)0x00020000) /*!< Bit 1 */
mbed_official 340:28d1f895c6fe 5117 #define USART_CR1_DEDT_2 ((uint32_t)0x00040000) /*!< Bit 2 */
mbed_official 340:28d1f895c6fe 5118 #define USART_CR1_DEDT_3 ((uint32_t)0x00080000) /*!< Bit 3 */
mbed_official 340:28d1f895c6fe 5119 #define USART_CR1_DEDT_4 ((uint32_t)0x00100000) /*!< Bit 4 */
mbed_official 340:28d1f895c6fe 5120 #define USART_CR1_DEAT ((uint32_t)0x03E00000) /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
mbed_official 340:28d1f895c6fe 5121 #define USART_CR1_DEAT_0 ((uint32_t)0x00200000) /*!< Bit 0 */
mbed_official 340:28d1f895c6fe 5122 #define USART_CR1_DEAT_1 ((uint32_t)0x00400000) /*!< Bit 1 */
mbed_official 340:28d1f895c6fe 5123 #define USART_CR1_DEAT_2 ((uint32_t)0x00800000) /*!< Bit 2 */
mbed_official 340:28d1f895c6fe 5124 #define USART_CR1_DEAT_3 ((uint32_t)0x01000000) /*!< Bit 3 */
mbed_official 340:28d1f895c6fe 5125 #define USART_CR1_DEAT_4 ((uint32_t)0x02000000) /*!< Bit 4 */
mbed_official 340:28d1f895c6fe 5126 #define USART_CR1_RTOIE ((uint32_t)0x04000000) /*!< Receive Time Out interrupt enable */
mbed_official 340:28d1f895c6fe 5127 #define USART_CR1_EOBIE ((uint32_t)0x08000000) /*!< End of Block interrupt enable */
mbed_official 340:28d1f895c6fe 5128 #define USART_CR1_M1 ((uint32_t)0x10000000) /*!< Word length bit 1 */
mbed_official 340:28d1f895c6fe 5129 #define USART_CR1_M ((uint32_t)0x10001000) /*!< [M1:M0] Word length */
mbed_official 340:28d1f895c6fe 5130
mbed_official 340:28d1f895c6fe 5131 /****************** Bit definition for USART_CR2 register *******************/
mbed_official 340:28d1f895c6fe 5132 #define USART_CR2_ADDM7 ((uint32_t)0x00000010) /*!< 7-bit or 4-bit Address Detection */
mbed_official 340:28d1f895c6fe 5133 #define USART_CR2_LBDL ((uint32_t)0x00000020) /*!< LIN Break Detection Length */
mbed_official 340:28d1f895c6fe 5134 #define USART_CR2_LBDIE ((uint32_t)0x00000040) /*!< LIN Break Detection Interrupt Enable */
mbed_official 340:28d1f895c6fe 5135 #define USART_CR2_LBCL ((uint32_t)0x00000100) /*!< Last Bit Clock pulse */
mbed_official 340:28d1f895c6fe 5136 #define USART_CR2_CPHA ((uint32_t)0x00000200) /*!< Clock Phase */
mbed_official 340:28d1f895c6fe 5137 #define USART_CR2_CPOL ((uint32_t)0x00000400) /*!< Clock Polarity */
mbed_official 340:28d1f895c6fe 5138 #define USART_CR2_CLKEN ((uint32_t)0x00000800) /*!< Clock Enable */
mbed_official 340:28d1f895c6fe 5139 #define USART_CR2_STOP ((uint32_t)0x00003000) /*!< STOP[1:0] bits (STOP bits) */
mbed_official 340:28d1f895c6fe 5140 #define USART_CR2_STOP_0 ((uint32_t)0x00001000) /*!< Bit 0 */
mbed_official 340:28d1f895c6fe 5141 #define USART_CR2_STOP_1 ((uint32_t)0x00002000) /*!< Bit 1 */
mbed_official 340:28d1f895c6fe 5142 #define USART_CR2_LINEN ((uint32_t)0x00004000) /*!< LIN mode enable */
mbed_official 340:28d1f895c6fe 5143 #define USART_CR2_SWAP ((uint32_t)0x00008000) /*!< SWAP TX/RX pins */
mbed_official 340:28d1f895c6fe 5144 #define USART_CR2_RXINV ((uint32_t)0x00010000) /*!< RX pin active level inversion */
mbed_official 340:28d1f895c6fe 5145 #define USART_CR2_TXINV ((uint32_t)0x00020000) /*!< TX pin active level inversion */
mbed_official 340:28d1f895c6fe 5146 #define USART_CR2_DATAINV ((uint32_t)0x00040000) /*!< Binary data inversion */
mbed_official 340:28d1f895c6fe 5147 #define USART_CR2_MSBFIRST ((uint32_t)0x00080000) /*!< Most Significant Bit First */
mbed_official 340:28d1f895c6fe 5148 #define USART_CR2_ABREN ((uint32_t)0x00100000) /*!< Auto Baud-Rate Enable*/
mbed_official 340:28d1f895c6fe 5149 #define USART_CR2_ABRMODE ((uint32_t)0x00600000) /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
mbed_official 340:28d1f895c6fe 5150 #define USART_CR2_ABRMODE_0 ((uint32_t)0x00200000) /*!< Bit 0 */
mbed_official 340:28d1f895c6fe 5151 #define USART_CR2_ABRMODE_1 ((uint32_t)0x00400000) /*!< Bit 1 */
mbed_official 340:28d1f895c6fe 5152 #define USART_CR2_RTOEN ((uint32_t)0x00800000) /*!< Receiver Time-Out enable */
mbed_official 340:28d1f895c6fe 5153 #define USART_CR2_ADD ((uint32_t)0xFF000000) /*!< Address of the USART node */
mbed_official 340:28d1f895c6fe 5154
mbed_official 340:28d1f895c6fe 5155 /****************** Bit definition for USART_CR3 register *******************/
mbed_official 340:28d1f895c6fe 5156 #define USART_CR3_EIE ((uint32_t)0x00000001) /*!< Error Interrupt Enable */
mbed_official 340:28d1f895c6fe 5157 #define USART_CR3_IREN ((uint32_t)0x00000002) /*!< IrDA mode Enable */
mbed_official 340:28d1f895c6fe 5158 #define USART_CR3_IRLP ((uint32_t)0x00000004) /*!< IrDA Low-Power */
mbed_official 340:28d1f895c6fe 5159 #define USART_CR3_HDSEL ((uint32_t)0x00000008) /*!< Half-Duplex Selection */
mbed_official 340:28d1f895c6fe 5160 #define USART_CR3_NACK ((uint32_t)0x00000010) /*!< SmartCard NACK enable */
mbed_official 340:28d1f895c6fe 5161 #define USART_CR3_SCEN ((uint32_t)0x00000020) /*!< SmartCard mode enable */
mbed_official 340:28d1f895c6fe 5162 #define USART_CR3_DMAR ((uint32_t)0x00000040) /*!< DMA Enable Receiver */
mbed_official 340:28d1f895c6fe 5163 #define USART_CR3_DMAT ((uint32_t)0x00000080) /*!< DMA Enable Transmitter */
mbed_official 340:28d1f895c6fe 5164 #define USART_CR3_RTSE ((uint32_t)0x00000100) /*!< RTS Enable */
mbed_official 340:28d1f895c6fe 5165 #define USART_CR3_CTSE ((uint32_t)0x00000200) /*!< CTS Enable */
mbed_official 340:28d1f895c6fe 5166 #define USART_CR3_CTSIE ((uint32_t)0x00000400) /*!< CTS Interrupt Enable */
mbed_official 340:28d1f895c6fe 5167 #define USART_CR3_ONEBIT ((uint32_t)0x00000800) /*!< One sample bit method enable */
mbed_official 340:28d1f895c6fe 5168 #define USART_CR3_OVRDIS ((uint32_t)0x00001000) /*!< Overrun Disable */
mbed_official 340:28d1f895c6fe 5169 #define USART_CR3_DDRE ((uint32_t)0x00002000) /*!< DMA Disable on Reception Error */
mbed_official 340:28d1f895c6fe 5170 #define USART_CR3_DEM ((uint32_t)0x00004000) /*!< Driver Enable Mode */
mbed_official 340:28d1f895c6fe 5171 #define USART_CR3_DEP ((uint32_t)0x00008000) /*!< Driver Enable Polarity Selection */
mbed_official 340:28d1f895c6fe 5172 #define USART_CR3_SCARCNT ((uint32_t)0x000E0000) /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
mbed_official 340:28d1f895c6fe 5173 #define USART_CR3_SCARCNT_0 ((uint32_t)0x00020000) /*!< Bit 0 */
mbed_official 340:28d1f895c6fe 5174 #define USART_CR3_SCARCNT_1 ((uint32_t)0x00040000) /*!< Bit 1 */
mbed_official 340:28d1f895c6fe 5175 #define USART_CR3_SCARCNT_2 ((uint32_t)0x00080000) /*!< Bit 2 */
mbed_official 340:28d1f895c6fe 5176 #define USART_CR3_WUS ((uint32_t)0x00300000) /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
mbed_official 340:28d1f895c6fe 5177 #define USART_CR3_WUS_0 ((uint32_t)0x00100000) /*!< Bit 0 */
mbed_official 340:28d1f895c6fe 5178 #define USART_CR3_WUS_1 ((uint32_t)0x00200000) /*!< Bit 1 */
mbed_official 340:28d1f895c6fe 5179 #define USART_CR3_WUFIE ((uint32_t)0x00400000) /*!< Wake Up Interrupt Enable */
mbed_official 340:28d1f895c6fe 5180
mbed_official 340:28d1f895c6fe 5181 /****************** Bit definition for USART_BRR register *******************/
mbed_official 340:28d1f895c6fe 5182 #define USART_BRR_DIV_FRACTION ((uint32_t)0x0000000F) /*!< Fraction of USARTDIV */
mbed_official 340:28d1f895c6fe 5183 #define USART_BRR_DIV_MANTISSA ((uint32_t)0x0000FFF0) /*!< Mantissa of USARTDIV */
mbed_official 340:28d1f895c6fe 5184
mbed_official 340:28d1f895c6fe 5185 /****************** Bit definition for USART_GTPR register ******************/
mbed_official 340:28d1f895c6fe 5186 #define USART_GTPR_PSC ((uint32_t)0x000000FF) /*!< PSC[7:0] bits (Prescaler value) */
mbed_official 340:28d1f895c6fe 5187 #define USART_GTPR_GT ((uint32_t)0x0000FF00) /*!< GT[7:0] bits (Guard time value) */
mbed_official 340:28d1f895c6fe 5188
mbed_official 340:28d1f895c6fe 5189
mbed_official 340:28d1f895c6fe 5190 /******************* Bit definition for USART_RTOR register *****************/
mbed_official 340:28d1f895c6fe 5191 #define USART_RTOR_RTO ((uint32_t)0x00FFFFFF) /*!< Receiver Time Out Value */
mbed_official 340:28d1f895c6fe 5192 #define USART_RTOR_BLEN ((uint32_t)0xFF000000) /*!< Block Length */
mbed_official 340:28d1f895c6fe 5193
mbed_official 340:28d1f895c6fe 5194 /******************* Bit definition for USART_RQR register ******************/
mbed_official 340:28d1f895c6fe 5195 #define USART_RQR_ABRRQ ((uint32_t)0x00000001) /*!< Auto-Baud Rate Request */
mbed_official 340:28d1f895c6fe 5196 #define USART_RQR_SBKRQ ((uint32_t)0x00000002) /*!< Send Break Request */
mbed_official 340:28d1f895c6fe 5197 #define USART_RQR_MMRQ ((uint32_t)0x00000004) /*!< Mute Mode Request */
mbed_official 340:28d1f895c6fe 5198 #define USART_RQR_RXFRQ ((uint32_t)0x00000008) /*!< Receive Data flush Request */
mbed_official 340:28d1f895c6fe 5199 #define USART_RQR_TXFRQ ((uint32_t)0x00000010) /*!< Transmit data flush Request */
mbed_official 340:28d1f895c6fe 5200
mbed_official 340:28d1f895c6fe 5201 /******************* Bit definition for USART_ISR register ******************/
mbed_official 340:28d1f895c6fe 5202 #define USART_ISR_PE ((uint32_t)0x00000001) /*!< Parity Error */
mbed_official 340:28d1f895c6fe 5203 #define USART_ISR_FE ((uint32_t)0x00000002) /*!< Framing Error */
mbed_official 340:28d1f895c6fe 5204 #define USART_ISR_NE ((uint32_t)0x00000004) /*!< Noise detected Flag */
mbed_official 340:28d1f895c6fe 5205 #define USART_ISR_ORE ((uint32_t)0x00000008) /*!< OverRun Error */
mbed_official 340:28d1f895c6fe 5206 #define USART_ISR_IDLE ((uint32_t)0x00000010) /*!< IDLE line detected */
mbed_official 340:28d1f895c6fe 5207 #define USART_ISR_RXNE ((uint32_t)0x00000020) /*!< Read Data Register Not Empty */
mbed_official 340:28d1f895c6fe 5208 #define USART_ISR_TC ((uint32_t)0x00000040) /*!< Transmission Complete */
mbed_official 340:28d1f895c6fe 5209 #define USART_ISR_TXE ((uint32_t)0x00000080) /*!< Transmit Data Register Empty */
mbed_official 340:28d1f895c6fe 5210 #define USART_ISR_LBDF ((uint32_t)0x00000100) /*!< LIN Break Detection Flag */
mbed_official 340:28d1f895c6fe 5211 #define USART_ISR_CTSIF ((uint32_t)0x00000200) /*!< CTS interrupt flag */
mbed_official 340:28d1f895c6fe 5212 #define USART_ISR_CTS ((uint32_t)0x00000400) /*!< CTS flag */
mbed_official 340:28d1f895c6fe 5213 #define USART_ISR_RTOF ((uint32_t)0x00000800) /*!< Receiver Time Out */
mbed_official 340:28d1f895c6fe 5214 #define USART_ISR_EOBF ((uint32_t)0x00001000) /*!< End Of Block Flag */
mbed_official 340:28d1f895c6fe 5215 #define USART_ISR_ABRE ((uint32_t)0x00004000) /*!< Auto-Baud Rate Error */
mbed_official 340:28d1f895c6fe 5216 #define USART_ISR_ABRF ((uint32_t)0x00008000) /*!< Auto-Baud Rate Flag */
mbed_official 340:28d1f895c6fe 5217 #define USART_ISR_BUSY ((uint32_t)0x00010000) /*!< Busy Flag */
mbed_official 340:28d1f895c6fe 5218 #define USART_ISR_CMF ((uint32_t)0x00020000) /*!< Character Match Flag */
mbed_official 340:28d1f895c6fe 5219 #define USART_ISR_SBKF ((uint32_t)0x00040000) /*!< Send Break Flag */
mbed_official 340:28d1f895c6fe 5220 #define USART_ISR_RWU ((uint32_t)0x00080000) /*!< Receive Wake Up from mute mode Flag */
mbed_official 340:28d1f895c6fe 5221 #define USART_ISR_WUF ((uint32_t)0x00100000) /*!< Wake Up from stop mode Flag */
mbed_official 340:28d1f895c6fe 5222 #define USART_ISR_TEACK ((uint32_t)0x00200000) /*!< Transmit Enable Acknowledge Flag */
mbed_official 340:28d1f895c6fe 5223 #define USART_ISR_REACK ((uint32_t)0x00400000) /*!< Receive Enable Acknowledge Flag */
mbed_official 340:28d1f895c6fe 5224
mbed_official 340:28d1f895c6fe 5225 /******************* Bit definition for USART_ICR register ******************/
mbed_official 340:28d1f895c6fe 5226 #define USART_ICR_PECF ((uint32_t)0x00000001) /*!< Parity Error Clear Flag */
mbed_official 340:28d1f895c6fe 5227 #define USART_ICR_FECF ((uint32_t)0x00000002) /*!< Framing Error Clear Flag */
mbed_official 340:28d1f895c6fe 5228 #define USART_ICR_NCF ((uint32_t)0x00000004) /*!< Noise detected Clear Flag */
mbed_official 340:28d1f895c6fe 5229 #define USART_ICR_ORECF ((uint32_t)0x00000008) /*!< OverRun Error Clear Flag */
mbed_official 340:28d1f895c6fe 5230 #define USART_ICR_IDLECF ((uint32_t)0x00000010) /*!< IDLE line detected Clear Flag */
mbed_official 340:28d1f895c6fe 5231 #define USART_ICR_TCCF ((uint32_t)0x00000040) /*!< Transmission Complete Clear Flag */
mbed_official 340:28d1f895c6fe 5232 #define USART_ICR_LBDCF ((uint32_t)0x00000100) /*!< LIN Break Detection Clear Flag */
mbed_official 340:28d1f895c6fe 5233 #define USART_ICR_CTSCF ((uint32_t)0x00000200) /*!< CTS Interrupt Clear Flag */
mbed_official 340:28d1f895c6fe 5234 #define USART_ICR_RTOCF ((uint32_t)0x00000800) /*!< Receiver Time Out Clear Flag */
mbed_official 340:28d1f895c6fe 5235 #define USART_ICR_EOBCF ((uint32_t)0x00001000) /*!< End Of Block Clear Flag */
mbed_official 340:28d1f895c6fe 5236 #define USART_ICR_CMCF ((uint32_t)0x00020000) /*!< Character Match Clear Flag */
mbed_official 340:28d1f895c6fe 5237 #define USART_ICR_WUCF ((uint32_t)0x00100000) /*!< Wake Up from stop mode Clear Flag */
mbed_official 340:28d1f895c6fe 5238
mbed_official 340:28d1f895c6fe 5239 /******************* Bit definition for USART_RDR register ******************/
mbed_official 340:28d1f895c6fe 5240 #define USART_RDR_RDR ((uint16_t)0x01FF) /*!< RDR[8:0] bits (Receive Data value) */
mbed_official 340:28d1f895c6fe 5241
mbed_official 340:28d1f895c6fe 5242 /******************* Bit definition for USART_TDR register ******************/
mbed_official 340:28d1f895c6fe 5243 #define USART_TDR_TDR ((uint16_t)0x01FF) /*!< TDR[8:0] bits (Transmit Data value) */
mbed_official 340:28d1f895c6fe 5244
mbed_official 340:28d1f895c6fe 5245 /******************************************************************************/
mbed_official 340:28d1f895c6fe 5246 /* */
mbed_official 340:28d1f895c6fe 5247 /* Window WATCHDOG (WWDG) */
mbed_official 340:28d1f895c6fe 5248 /* */
mbed_official 340:28d1f895c6fe 5249 /******************************************************************************/
mbed_official 340:28d1f895c6fe 5250 /******************* Bit definition for WWDG_CR register ********************/
mbed_official 340:28d1f895c6fe 5251 #define WWDG_CR_T ((uint32_t)0x7F) /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
mbed_official 340:28d1f895c6fe 5252 #define WWDG_CR_T0 ((uint32_t)0x01) /*!<Bit 0 */
mbed_official 340:28d1f895c6fe 5253 #define WWDG_CR_T1 ((uint32_t)0x02) /*!<Bit 1 */
mbed_official 340:28d1f895c6fe 5254 #define WWDG_CR_T2 ((uint32_t)0x04) /*!<Bit 2 */
mbed_official 340:28d1f895c6fe 5255 #define WWDG_CR_T3 ((uint32_t)0x08) /*!<Bit 3 */
mbed_official 340:28d1f895c6fe 5256 #define WWDG_CR_T4 ((uint32_t)0x10) /*!<Bit 4 */
mbed_official 340:28d1f895c6fe 5257 #define WWDG_CR_T5 ((uint32_t)0x20) /*!<Bit 5 */
mbed_official 340:28d1f895c6fe 5258 #define WWDG_CR_T6 ((uint32_t)0x40) /*!<Bit 6 */
mbed_official 340:28d1f895c6fe 5259
mbed_official 340:28d1f895c6fe 5260 #define WWDG_CR_WDGA ((uint32_t)0x80) /*!<Activation bit */
mbed_official 340:28d1f895c6fe 5261
mbed_official 340:28d1f895c6fe 5262 /******************* Bit definition for WWDG_CFR register *******************/
mbed_official 340:28d1f895c6fe 5263 #define WWDG_CFR_W ((uint32_t)0x007F) /*!<W[6:0] bits (7-bit window value) */
mbed_official 340:28d1f895c6fe 5264 #define WWDG_CFR_W0 ((uint32_t)0x0001) /*!<Bit 0 */
mbed_official 340:28d1f895c6fe 5265 #define WWDG_CFR_W1 ((uint32_t)0x0002) /*!<Bit 1 */
mbed_official 340:28d1f895c6fe 5266 #define WWDG_CFR_W2 ((uint32_t)0x0004) /*!<Bit 2 */
mbed_official 340:28d1f895c6fe 5267 #define WWDG_CFR_W3 ((uint32_t)0x0008) /*!<Bit 3 */
mbed_official 340:28d1f895c6fe 5268 #define WWDG_CFR_W4 ((uint32_t)0x0010) /*!<Bit 4 */
mbed_official 340:28d1f895c6fe 5269 #define WWDG_CFR_W5 ((uint32_t)0x0020) /*!<Bit 5 */
mbed_official 340:28d1f895c6fe 5270 #define WWDG_CFR_W6 ((uint32_t)0x0040) /*!<Bit 6 */
mbed_official 340:28d1f895c6fe 5271
mbed_official 340:28d1f895c6fe 5272 #define WWDG_CFR_WDGTB ((uint32_t)0x0180) /*!<WDGTB[1:0] bits (Timer Base) */
mbed_official 340:28d1f895c6fe 5273 #define WWDG_CFR_WDGTB0 ((uint32_t)0x0080) /*!<Bit 0 */
mbed_official 340:28d1f895c6fe 5274 #define WWDG_CFR_WDGTB1 ((uint32_t)0x0100) /*!<Bit 1 */
mbed_official 340:28d1f895c6fe 5275
mbed_official 340:28d1f895c6fe 5276 #define WWDG_CFR_EWI ((uint32_t)0x0200) /*!<Early Wakeup Interrupt */
mbed_official 340:28d1f895c6fe 5277
mbed_official 340:28d1f895c6fe 5278 /******************* Bit definition for WWDG_SR register ********************/
mbed_official 340:28d1f895c6fe 5279 #define WWDG_SR_EWIF ((uint32_t)0x01) /*!<Early Wakeup Interrupt Flag */
mbed_official 340:28d1f895c6fe 5280
mbed_official 340:28d1f895c6fe 5281 /**
mbed_official 340:28d1f895c6fe 5282 * @}
mbed_official 340:28d1f895c6fe 5283 */
mbed_official 340:28d1f895c6fe 5284
mbed_official 340:28d1f895c6fe 5285 /**
mbed_official 340:28d1f895c6fe 5286 * @}
mbed_official 340:28d1f895c6fe 5287 */
mbed_official 340:28d1f895c6fe 5288
mbed_official 340:28d1f895c6fe 5289
mbed_official 340:28d1f895c6fe 5290 /** @addtogroup Exported_macro
mbed_official 340:28d1f895c6fe 5291 * @{
mbed_official 340:28d1f895c6fe 5292 */
mbed_official 340:28d1f895c6fe 5293
mbed_official 340:28d1f895c6fe 5294 /****************************** ADC Instances *********************************/
mbed_official 340:28d1f895c6fe 5295 #define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
mbed_official 340:28d1f895c6fe 5296
mbed_official 340:28d1f895c6fe 5297 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC)
mbed_official 340:28d1f895c6fe 5298
mbed_official 340:28d1f895c6fe 5299 /******************************* CAN Instances ********************************/
mbed_official 340:28d1f895c6fe 5300 #define IS_CAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CAN)
mbed_official 340:28d1f895c6fe 5301
mbed_official 340:28d1f895c6fe 5302 /****************************** COMP Instances *********************************/
mbed_official 340:28d1f895c6fe 5303 #define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
mbed_official 340:28d1f895c6fe 5304 ((INSTANCE) == COMP2))
mbed_official 340:28d1f895c6fe 5305
mbed_official 340:28d1f895c6fe 5306 #define IS_COMP_DAC1SWITCH_INSTANCE(INSTANCE) ((INSTANCE) == COMP1)
mbed_official 340:28d1f895c6fe 5307
mbed_official 340:28d1f895c6fe 5308 #define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2)
mbed_official 340:28d1f895c6fe 5309
mbed_official 340:28d1f895c6fe 5310 /****************************** CEC Instances *********************************/
mbed_official 340:28d1f895c6fe 5311 #define IS_CEC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CEC)
mbed_official 340:28d1f895c6fe 5312
mbed_official 340:28d1f895c6fe 5313 /****************************** CRC Instances *********************************/
mbed_official 340:28d1f895c6fe 5314 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
mbed_official 340:28d1f895c6fe 5315
mbed_official 340:28d1f895c6fe 5316 /******************************* DAC Instances ********************************/
mbed_official 340:28d1f895c6fe 5317 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
mbed_official 340:28d1f895c6fe 5318
mbed_official 340:28d1f895c6fe 5319 /******************************* DMA Instances ******************************/
mbed_official 340:28d1f895c6fe 5320 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
mbed_official 340:28d1f895c6fe 5321 ((INSTANCE) == DMA1_Channel2) || \
mbed_official 340:28d1f895c6fe 5322 ((INSTANCE) == DMA1_Channel3) || \
mbed_official 340:28d1f895c6fe 5323 ((INSTANCE) == DMA1_Channel4) || \
mbed_official 340:28d1f895c6fe 5324 ((INSTANCE) == DMA1_Channel5) || \
mbed_official 340:28d1f895c6fe 5325 ((INSTANCE) == DMA1_Channel6) || \
mbed_official 340:28d1f895c6fe 5326 ((INSTANCE) == DMA1_Channel7) || \
mbed_official 340:28d1f895c6fe 5327 ((INSTANCE) == DMA2_Channel1) || \
mbed_official 340:28d1f895c6fe 5328 ((INSTANCE) == DMA2_Channel2) || \
mbed_official 340:28d1f895c6fe 5329 ((INSTANCE) == DMA2_Channel3) || \
mbed_official 340:28d1f895c6fe 5330 ((INSTANCE) == DMA2_Channel4) || \
mbed_official 340:28d1f895c6fe 5331 ((INSTANCE) == DMA2_Channel5))
mbed_official 340:28d1f895c6fe 5332
mbed_official 340:28d1f895c6fe 5333 /****************************** GPIO Instances ********************************/
mbed_official 441:d2c15dda23c1 5334 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
mbed_official 441:d2c15dda23c1 5335 ((INSTANCE) == GPIOB) || \
mbed_official 441:d2c15dda23c1 5336 ((INSTANCE) == GPIOC) || \
mbed_official 441:d2c15dda23c1 5337 ((INSTANCE) == GPIOD) || \
mbed_official 441:d2c15dda23c1 5338 ((INSTANCE) == GPIOE) || \
mbed_official 441:d2c15dda23c1 5339 ((INSTANCE) == GPIOF))
mbed_official 441:d2c15dda23c1 5340
mbed_official 441:d2c15dda23c1 5341 #define IS_GPIO_AF_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
mbed_official 441:d2c15dda23c1 5342 ((INSTANCE) == GPIOB) || \
mbed_official 441:d2c15dda23c1 5343 ((INSTANCE) == GPIOC) || \
mbed_official 441:d2c15dda23c1 5344 ((INSTANCE) == GPIOD) || \
mbed_official 441:d2c15dda23c1 5345 ((INSTANCE) == GPIOE) || \
mbed_official 441:d2c15dda23c1 5346 ((INSTANCE) == GPIOF))
mbed_official 441:d2c15dda23c1 5347
mbed_official 340:28d1f895c6fe 5348 #define IS_GPIO_LOCK_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
mbed_official 340:28d1f895c6fe 5349 ((INSTANCE) == GPIOB))
mbed_official 340:28d1f895c6fe 5350
mbed_official 340:28d1f895c6fe 5351 /****************************** I2C Instances *********************************/
mbed_official 340:28d1f895c6fe 5352 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
mbed_official 340:28d1f895c6fe 5353 ((INSTANCE) == I2C2))
mbed_official 340:28d1f895c6fe 5354
mbed_official 340:28d1f895c6fe 5355 /****************************** I2S Instances *********************************/
mbed_official 340:28d1f895c6fe 5356 #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
mbed_official 340:28d1f895c6fe 5357 ((INSTANCE) == SPI2))
mbed_official 340:28d1f895c6fe 5358
mbed_official 340:28d1f895c6fe 5359 /****************************** IWDG Instances ********************************/
mbed_official 340:28d1f895c6fe 5360 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
mbed_official 340:28d1f895c6fe 5361
mbed_official 340:28d1f895c6fe 5362 /****************************** RTC Instances *********************************/
mbed_official 340:28d1f895c6fe 5363 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
mbed_official 340:28d1f895c6fe 5364
mbed_official 340:28d1f895c6fe 5365 /****************************** SMBUS Instances *********************************/
mbed_official 340:28d1f895c6fe 5366 #define IS_SMBUS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
mbed_official 340:28d1f895c6fe 5367
mbed_official 340:28d1f895c6fe 5368 /****************************** SPI Instances *********************************/
mbed_official 340:28d1f895c6fe 5369 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
mbed_official 340:28d1f895c6fe 5370 ((INSTANCE) == SPI2))
mbed_official 340:28d1f895c6fe 5371
mbed_official 340:28d1f895c6fe 5372 /****************************** TIM Instances *********************************/
mbed_official 340:28d1f895c6fe 5373 #define IS_TIM_INSTANCE(INSTANCE)\
mbed_official 340:28d1f895c6fe 5374 (((INSTANCE) == TIM1) || \
mbed_official 340:28d1f895c6fe 5375 ((INSTANCE) == TIM2) || \
mbed_official 340:28d1f895c6fe 5376 ((INSTANCE) == TIM3) || \
mbed_official 340:28d1f895c6fe 5377 ((INSTANCE) == TIM6) || \
mbed_official 340:28d1f895c6fe 5378 ((INSTANCE) == TIM7) || \
mbed_official 340:28d1f895c6fe 5379 ((INSTANCE) == TIM14) || \
mbed_official 340:28d1f895c6fe 5380 ((INSTANCE) == TIM15) || \
mbed_official 340:28d1f895c6fe 5381 ((INSTANCE) == TIM16) || \
mbed_official 340:28d1f895c6fe 5382 ((INSTANCE) == TIM17))
mbed_official 340:28d1f895c6fe 5383
mbed_official 340:28d1f895c6fe 5384 #define IS_TIM_CC1_INSTANCE(INSTANCE)\
mbed_official 340:28d1f895c6fe 5385 (((INSTANCE) == TIM1) || \
mbed_official 340:28d1f895c6fe 5386 ((INSTANCE) == TIM2) || \
mbed_official 340:28d1f895c6fe 5387 ((INSTANCE) == TIM3) || \
mbed_official 340:28d1f895c6fe 5388 ((INSTANCE) == TIM14) || \
mbed_official 340:28d1f895c6fe 5389 ((INSTANCE) == TIM15) || \
mbed_official 340:28d1f895c6fe 5390 ((INSTANCE) == TIM16) || \
mbed_official 340:28d1f895c6fe 5391 ((INSTANCE) == TIM17))
mbed_official 340:28d1f895c6fe 5392
mbed_official 340:28d1f895c6fe 5393 #define IS_TIM_CC2_INSTANCE(INSTANCE)\
mbed_official 340:28d1f895c6fe 5394 (((INSTANCE) == TIM1) || \
mbed_official 340:28d1f895c6fe 5395 ((INSTANCE) == TIM2) || \
mbed_official 340:28d1f895c6fe 5396 ((INSTANCE) == TIM3) || \
mbed_official 340:28d1f895c6fe 5397 ((INSTANCE) == TIM15))
mbed_official 340:28d1f895c6fe 5398
mbed_official 340:28d1f895c6fe 5399 #define IS_TIM_CC3_INSTANCE(INSTANCE)\
mbed_official 340:28d1f895c6fe 5400 (((INSTANCE) == TIM1) || \
mbed_official 340:28d1f895c6fe 5401 ((INSTANCE) == TIM2) || \
mbed_official 340:28d1f895c6fe 5402 ((INSTANCE) == TIM3))
mbed_official 340:28d1f895c6fe 5403
mbed_official 340:28d1f895c6fe 5404 #define IS_TIM_CC4_INSTANCE(INSTANCE)\
mbed_official 340:28d1f895c6fe 5405 (((INSTANCE) == TIM1) || \
mbed_official 340:28d1f895c6fe 5406 ((INSTANCE) == TIM2) || \
mbed_official 340:28d1f895c6fe 5407 ((INSTANCE) == TIM3))
mbed_official 340:28d1f895c6fe 5408
mbed_official 340:28d1f895c6fe 5409 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
mbed_official 340:28d1f895c6fe 5410 (((INSTANCE) == TIM1) || \
mbed_official 340:28d1f895c6fe 5411 ((INSTANCE) == TIM2) || \
mbed_official 340:28d1f895c6fe 5412 ((INSTANCE) == TIM3))
mbed_official 340:28d1f895c6fe 5413
mbed_official 340:28d1f895c6fe 5414 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
mbed_official 340:28d1f895c6fe 5415 (((INSTANCE) == TIM1) || \
mbed_official 340:28d1f895c6fe 5416 ((INSTANCE) == TIM2) || \
mbed_official 340:28d1f895c6fe 5417 ((INSTANCE) == TIM3))
mbed_official 340:28d1f895c6fe 5418
mbed_official 340:28d1f895c6fe 5419 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
mbed_official 340:28d1f895c6fe 5420 (((INSTANCE) == TIM1) || \
mbed_official 340:28d1f895c6fe 5421 ((INSTANCE) == TIM2) || \
mbed_official 340:28d1f895c6fe 5422 ((INSTANCE) == TIM3) || \
mbed_official 340:28d1f895c6fe 5423 ((INSTANCE) == TIM15))
mbed_official 340:28d1f895c6fe 5424
mbed_official 340:28d1f895c6fe 5425 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
mbed_official 340:28d1f895c6fe 5426 (((INSTANCE) == TIM1) || \
mbed_official 340:28d1f895c6fe 5427 ((INSTANCE) == TIM2) || \
mbed_official 340:28d1f895c6fe 5428 ((INSTANCE) == TIM3) || \
mbed_official 340:28d1f895c6fe 5429 ((INSTANCE) == TIM15))
mbed_official 340:28d1f895c6fe 5430
mbed_official 340:28d1f895c6fe 5431 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
mbed_official 340:28d1f895c6fe 5432 (((INSTANCE) == TIM1) || \
mbed_official 340:28d1f895c6fe 5433 ((INSTANCE) == TIM2) || \
mbed_official 340:28d1f895c6fe 5434 ((INSTANCE) == TIM3))
mbed_official 340:28d1f895c6fe 5435
mbed_official 340:28d1f895c6fe 5436 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\
mbed_official 340:28d1f895c6fe 5437 (((INSTANCE) == TIM1) || \
mbed_official 340:28d1f895c6fe 5438 ((INSTANCE) == TIM2) || \
mbed_official 340:28d1f895c6fe 5439 ((INSTANCE) == TIM3))
mbed_official 340:28d1f895c6fe 5440
mbed_official 340:28d1f895c6fe 5441 #define IS_TIM_HALL_INTERFACE_INSTANCE(INSTANCE)\
mbed_official 340:28d1f895c6fe 5442 (((INSTANCE) == TIM1))
mbed_official 340:28d1f895c6fe 5443
mbed_official 340:28d1f895c6fe 5444 #define IS_TIM_XOR_INSTANCE(INSTANCE)\
mbed_official 340:28d1f895c6fe 5445 (((INSTANCE) == TIM1) || \
mbed_official 340:28d1f895c6fe 5446 ((INSTANCE) == TIM2) || \
mbed_official 340:28d1f895c6fe 5447 ((INSTANCE) == TIM3))
mbed_official 340:28d1f895c6fe 5448
mbed_official 340:28d1f895c6fe 5449 #define IS_TIM_MASTER_INSTANCE(INSTANCE)\
mbed_official 340:28d1f895c6fe 5450 (((INSTANCE) == TIM1) || \
mbed_official 340:28d1f895c6fe 5451 ((INSTANCE) == TIM2) || \
mbed_official 340:28d1f895c6fe 5452 ((INSTANCE) == TIM3) || \
mbed_official 340:28d1f895c6fe 5453 ((INSTANCE) == TIM6) || \
mbed_official 340:28d1f895c6fe 5454 ((INSTANCE) == TIM7) || \
mbed_official 340:28d1f895c6fe 5455 ((INSTANCE) == TIM15))
mbed_official 340:28d1f895c6fe 5456
mbed_official 340:28d1f895c6fe 5457 #define IS_TIM_SLAVE_INSTANCE(INSTANCE)\
mbed_official 340:28d1f895c6fe 5458 (((INSTANCE) == TIM1) || \
mbed_official 340:28d1f895c6fe 5459 ((INSTANCE) == TIM2) || \
mbed_official 340:28d1f895c6fe 5460 ((INSTANCE) == TIM3) || \
mbed_official 340:28d1f895c6fe 5461 ((INSTANCE) == TIM15))
mbed_official 340:28d1f895c6fe 5462
mbed_official 340:28d1f895c6fe 5463 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)\
mbed_official 340:28d1f895c6fe 5464 ((INSTANCE) == TIM2)
mbed_official 340:28d1f895c6fe 5465
mbed_official 340:28d1f895c6fe 5466 #define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
mbed_official 340:28d1f895c6fe 5467 (((INSTANCE) == TIM1) || \
mbed_official 340:28d1f895c6fe 5468 ((INSTANCE) == TIM2) || \
mbed_official 340:28d1f895c6fe 5469 ((INSTANCE) == TIM3) || \
mbed_official 340:28d1f895c6fe 5470 ((INSTANCE) == TIM15) || \
mbed_official 340:28d1f895c6fe 5471 ((INSTANCE) == TIM16) || \
mbed_official 340:28d1f895c6fe 5472 ((INSTANCE) == TIM17))
mbed_official 340:28d1f895c6fe 5473
mbed_official 340:28d1f895c6fe 5474 #define IS_TIM_BREAK_INSTANCE(INSTANCE)\
mbed_official 340:28d1f895c6fe 5475 (((INSTANCE) == TIM1) || \
mbed_official 340:28d1f895c6fe 5476 ((INSTANCE) == TIM15) || \
mbed_official 340:28d1f895c6fe 5477 ((INSTANCE) == TIM16) || \
mbed_official 340:28d1f895c6fe 5478 ((INSTANCE) == TIM17))
mbed_official 340:28d1f895c6fe 5479
mbed_official 340:28d1f895c6fe 5480 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
mbed_official 340:28d1f895c6fe 5481 ((((INSTANCE) == TIM1) && \
mbed_official 340:28d1f895c6fe 5482 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 340:28d1f895c6fe 5483 ((CHANNEL) == TIM_CHANNEL_2) || \
mbed_official 340:28d1f895c6fe 5484 ((CHANNEL) == TIM_CHANNEL_3) || \
mbed_official 340:28d1f895c6fe 5485 ((CHANNEL) == TIM_CHANNEL_4))) \
mbed_official 340:28d1f895c6fe 5486 || \
mbed_official 340:28d1f895c6fe 5487 (((INSTANCE) == TIM2) && \
mbed_official 340:28d1f895c6fe 5488 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 340:28d1f895c6fe 5489 ((CHANNEL) == TIM_CHANNEL_2) || \
mbed_official 340:28d1f895c6fe 5490 ((CHANNEL) == TIM_CHANNEL_3) || \
mbed_official 340:28d1f895c6fe 5491 ((CHANNEL) == TIM_CHANNEL_4))) \
mbed_official 340:28d1f895c6fe 5492 || \
mbed_official 340:28d1f895c6fe 5493 (((INSTANCE) == TIM3) && \
mbed_official 340:28d1f895c6fe 5494 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 340:28d1f895c6fe 5495 ((CHANNEL) == TIM_CHANNEL_2) || \
mbed_official 340:28d1f895c6fe 5496 ((CHANNEL) == TIM_CHANNEL_3) || \
mbed_official 340:28d1f895c6fe 5497 ((CHANNEL) == TIM_CHANNEL_4))) \
mbed_official 340:28d1f895c6fe 5498 || \
mbed_official 340:28d1f895c6fe 5499 (((INSTANCE) == TIM14) && \
mbed_official 340:28d1f895c6fe 5500 (((CHANNEL) == TIM_CHANNEL_1))) \
mbed_official 340:28d1f895c6fe 5501 || \
mbed_official 340:28d1f895c6fe 5502 (((INSTANCE) == TIM15) && \
mbed_official 340:28d1f895c6fe 5503 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 340:28d1f895c6fe 5504 ((CHANNEL) == TIM_CHANNEL_2))) \
mbed_official 340:28d1f895c6fe 5505 || \
mbed_official 340:28d1f895c6fe 5506 (((INSTANCE) == TIM16) && \
mbed_official 340:28d1f895c6fe 5507 (((CHANNEL) == TIM_CHANNEL_1))) \
mbed_official 340:28d1f895c6fe 5508 || \
mbed_official 340:28d1f895c6fe 5509 (((INSTANCE) == TIM17) && \
mbed_official 340:28d1f895c6fe 5510 (((CHANNEL) == TIM_CHANNEL_1))))
mbed_official 340:28d1f895c6fe 5511
mbed_official 340:28d1f895c6fe 5512 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
mbed_official 340:28d1f895c6fe 5513 ((((INSTANCE) == TIM1) && \
mbed_official 340:28d1f895c6fe 5514 (((CHANNEL) == TIM_CHANNEL_1) || \
mbed_official 340:28d1f895c6fe 5515 ((CHANNEL) == TIM_CHANNEL_2) || \
mbed_official 340:28d1f895c6fe 5516 ((CHANNEL) == TIM_CHANNEL_3))) \
mbed_official 340:28d1f895c6fe 5517 || \
mbed_official 340:28d1f895c6fe 5518 (((INSTANCE) == TIM15) && \
mbed_official 340:28d1f895c6fe 5519 ((CHANNEL) == TIM_CHANNEL_1)) \
mbed_official 340:28d1f895c6fe 5520 || \
mbed_official 340:28d1f895c6fe 5521 (((INSTANCE) == TIM16) && \
mbed_official 340:28d1f895c6fe 5522 ((CHANNEL) == TIM_CHANNEL_1)) \
mbed_official 340:28d1f895c6fe 5523 || \
mbed_official 340:28d1f895c6fe 5524 (((INSTANCE) == TIM17) && \
mbed_official 340:28d1f895c6fe 5525 ((CHANNEL) == TIM_CHANNEL_1)))
mbed_official 340:28d1f895c6fe 5526
mbed_official 340:28d1f895c6fe 5527 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
mbed_official 340:28d1f895c6fe 5528 (((INSTANCE) == TIM1) || \
mbed_official 340:28d1f895c6fe 5529 ((INSTANCE) == TIM2) || \
mbed_official 340:28d1f895c6fe 5530 ((INSTANCE) == TIM3))
mbed_official 340:28d1f895c6fe 5531
mbed_official 340:28d1f895c6fe 5532 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
mbed_official 340:28d1f895c6fe 5533 (((INSTANCE) == TIM1) || \
mbed_official 340:28d1f895c6fe 5534 ((INSTANCE) == TIM15) || \
mbed_official 340:28d1f895c6fe 5535 ((INSTANCE) == TIM16) || \
mbed_official 340:28d1f895c6fe 5536 ((INSTANCE) == TIM17))
mbed_official 340:28d1f895c6fe 5537
mbed_official 340:28d1f895c6fe 5538 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
mbed_official 340:28d1f895c6fe 5539 (((INSTANCE) == TIM1) || \
mbed_official 340:28d1f895c6fe 5540 ((INSTANCE) == TIM2) || \
mbed_official 340:28d1f895c6fe 5541 ((INSTANCE) == TIM3) || \
mbed_official 340:28d1f895c6fe 5542 ((INSTANCE) == TIM14) || \
mbed_official 340:28d1f895c6fe 5543 ((INSTANCE) == TIM15) || \
mbed_official 340:28d1f895c6fe 5544 ((INSTANCE) == TIM16) || \
mbed_official 340:28d1f895c6fe 5545 ((INSTANCE) == TIM17))
mbed_official 340:28d1f895c6fe 5546
mbed_official 340:28d1f895c6fe 5547 #define IS_TIM_DMA_INSTANCE(INSTANCE)\
mbed_official 340:28d1f895c6fe 5548 (((INSTANCE) == TIM1) || \
mbed_official 340:28d1f895c6fe 5549 ((INSTANCE) == TIM2) || \
mbed_official 340:28d1f895c6fe 5550 ((INSTANCE) == TIM3) || \
mbed_official 340:28d1f895c6fe 5551 ((INSTANCE) == TIM6) || \
mbed_official 340:28d1f895c6fe 5552 ((INSTANCE) == TIM7) || \
mbed_official 340:28d1f895c6fe 5553 ((INSTANCE) == TIM15) || \
mbed_official 340:28d1f895c6fe 5554 ((INSTANCE) == TIM16) || \
mbed_official 340:28d1f895c6fe 5555 ((INSTANCE) == TIM17))
mbed_official 340:28d1f895c6fe 5556
mbed_official 340:28d1f895c6fe 5557 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\
mbed_official 340:28d1f895c6fe 5558 (((INSTANCE) == TIM1) || \
mbed_official 340:28d1f895c6fe 5559 ((INSTANCE) == TIM2) || \
mbed_official 340:28d1f895c6fe 5560 ((INSTANCE) == TIM3) || \
mbed_official 340:28d1f895c6fe 5561 ((INSTANCE) == TIM15) || \
mbed_official 340:28d1f895c6fe 5562 ((INSTANCE) == TIM16) || \
mbed_official 340:28d1f895c6fe 5563 ((INSTANCE) == TIM17))
mbed_official 340:28d1f895c6fe 5564
mbed_official 340:28d1f895c6fe 5565 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\
mbed_official 340:28d1f895c6fe 5566 (((INSTANCE) == TIM1) || \
mbed_official 340:28d1f895c6fe 5567 ((INSTANCE) == TIM15) || \
mbed_official 340:28d1f895c6fe 5568 ((INSTANCE) == TIM16) || \
mbed_official 340:28d1f895c6fe 5569 ((INSTANCE) == TIM17))
mbed_official 340:28d1f895c6fe 5570
mbed_official 340:28d1f895c6fe 5571 #define IS_TIM_REMAP_INSTANCE(INSTANCE)\
mbed_official 340:28d1f895c6fe 5572 ((INSTANCE) == TIM14)
mbed_official 340:28d1f895c6fe 5573
mbed_official 340:28d1f895c6fe 5574 /****************************** TSC Instances *********************************/
mbed_official 340:28d1f895c6fe 5575 #define IS_TSC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == TSC)
mbed_official 340:28d1f895c6fe 5576
mbed_official 340:28d1f895c6fe 5577 /*********************** UART Instances : IRDA mode ***************************/
mbed_official 340:28d1f895c6fe 5578 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 340:28d1f895c6fe 5579 ((INSTANCE) == USART2) || \
mbed_official 340:28d1f895c6fe 5580 ((INSTANCE) == USART3))
mbed_official 340:28d1f895c6fe 5581
mbed_official 340:28d1f895c6fe 5582 /********************* UART Instances : Smard card mode ***********************/
mbed_official 340:28d1f895c6fe 5583 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 340:28d1f895c6fe 5584 ((INSTANCE) == USART2) || \
mbed_official 340:28d1f895c6fe 5585 ((INSTANCE) == USART3))
mbed_official 340:28d1f895c6fe 5586
mbed_official 340:28d1f895c6fe 5587 /******************** USART Instances : Synchronous mode **********************/
mbed_official 340:28d1f895c6fe 5588 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 340:28d1f895c6fe 5589 ((INSTANCE) == USART2) || \
mbed_official 340:28d1f895c6fe 5590 ((INSTANCE) == USART3) || \
mbed_official 340:28d1f895c6fe 5591 ((INSTANCE) == USART4) || \
mbed_official 340:28d1f895c6fe 5592 ((INSTANCE) == USART5) || \
mbed_official 340:28d1f895c6fe 5593 ((INSTANCE) == USART6) || \
mbed_official 340:28d1f895c6fe 5594 ((INSTANCE) == USART7) || \
mbed_official 340:28d1f895c6fe 5595 ((INSTANCE) == USART8))
mbed_official 340:28d1f895c6fe 5596
mbed_official 340:28d1f895c6fe 5597 /******************** USART Instances : auto Baud rate detection **************/
mbed_official 340:28d1f895c6fe 5598 #define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 340:28d1f895c6fe 5599 ((INSTANCE) == USART2) || \
mbed_official 340:28d1f895c6fe 5600 ((INSTANCE) == USART3))
mbed_official 340:28d1f895c6fe 5601
mbed_official 340:28d1f895c6fe 5602 /******************** UART Instances : Asynchronous mode **********************/
mbed_official 340:28d1f895c6fe 5603 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 340:28d1f895c6fe 5604 ((INSTANCE) == USART2) || \
mbed_official 340:28d1f895c6fe 5605 ((INSTANCE) == USART3) || \
mbed_official 340:28d1f895c6fe 5606 ((INSTANCE) == USART4) || \
mbed_official 340:28d1f895c6fe 5607 ((INSTANCE) == USART5) || \
mbed_official 340:28d1f895c6fe 5608 ((INSTANCE) == USART6) || \
mbed_official 340:28d1f895c6fe 5609 ((INSTANCE) == USART7) || \
mbed_official 340:28d1f895c6fe 5610 ((INSTANCE) == USART8))
mbed_official 340:28d1f895c6fe 5611
mbed_official 340:28d1f895c6fe 5612 /******************** UART Instances : Half-Duplex mode **********************/
mbed_official 340:28d1f895c6fe 5613 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 340:28d1f895c6fe 5614 ((INSTANCE) == USART2) || \
mbed_official 340:28d1f895c6fe 5615 ((INSTANCE) == USART3) || \
mbed_official 340:28d1f895c6fe 5616 ((INSTANCE) == USART4) || \
mbed_official 340:28d1f895c6fe 5617 ((INSTANCE) == USART5) || \
mbed_official 340:28d1f895c6fe 5618 ((INSTANCE) == USART6) || \
mbed_official 340:28d1f895c6fe 5619 ((INSTANCE) == USART7) || \
mbed_official 340:28d1f895c6fe 5620 ((INSTANCE) == USART8))
mbed_official 340:28d1f895c6fe 5621
mbed_official 340:28d1f895c6fe 5622 /****************** UART Instances : Hardware Flow control ********************/
mbed_official 340:28d1f895c6fe 5623 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 340:28d1f895c6fe 5624 ((INSTANCE) == USART2) || \
mbed_official 340:28d1f895c6fe 5625 ((INSTANCE) == USART3) || \
mbed_official 340:28d1f895c6fe 5626 ((INSTANCE) == USART4) || \
mbed_official 340:28d1f895c6fe 5627 ((INSTANCE) == USART5) || \
mbed_official 340:28d1f895c6fe 5628 ((INSTANCE) == USART6) || \
mbed_official 340:28d1f895c6fe 5629 ((INSTANCE) == USART7) || \
mbed_official 340:28d1f895c6fe 5630 ((INSTANCE) == USART8))
mbed_official 340:28d1f895c6fe 5631
mbed_official 340:28d1f895c6fe 5632 /****************** UART Instances : LIN mode ********************/
mbed_official 340:28d1f895c6fe 5633 #define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 340:28d1f895c6fe 5634 ((INSTANCE) == USART2) || \
mbed_official 340:28d1f895c6fe 5635 ((INSTANCE) == USART3))
mbed_official 340:28d1f895c6fe 5636
mbed_official 340:28d1f895c6fe 5637 /****************** UART Instances : wakeup from stop mode ********************/
mbed_official 340:28d1f895c6fe 5638 #define IS_UART_WAKEUP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 340:28d1f895c6fe 5639 ((INSTANCE) == USART2) || \
mbed_official 340:28d1f895c6fe 5640 ((INSTANCE) == USART3))
mbed_official 340:28d1f895c6fe 5641
mbed_official 340:28d1f895c6fe 5642 /****************** UART Instances : Auto Baud Rate detection ********************/
mbed_official 340:28d1f895c6fe 5643 #define IS_UART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 340:28d1f895c6fe 5644 ((INSTANCE) == USART2) || \
mbed_official 340:28d1f895c6fe 5645 ((INSTANCE) == USART3))
mbed_official 340:28d1f895c6fe 5646
mbed_official 340:28d1f895c6fe 5647 /****************** UART Instances : Driver enable detection ********************/
mbed_official 340:28d1f895c6fe 5648 #define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
mbed_official 340:28d1f895c6fe 5649 ((INSTANCE) == USART2) || \
mbed_official 340:28d1f895c6fe 5650 ((INSTANCE) == USART3) || \
mbed_official 340:28d1f895c6fe 5651 ((INSTANCE) == USART4) || \
mbed_official 340:28d1f895c6fe 5652 ((INSTANCE) == USART5) || \
mbed_official 340:28d1f895c6fe 5653 ((INSTANCE) == USART6) || \
mbed_official 340:28d1f895c6fe 5654 ((INSTANCE) == USART7) || \
mbed_official 340:28d1f895c6fe 5655 ((INSTANCE) == USART8))
mbed_official 340:28d1f895c6fe 5656
mbed_official 340:28d1f895c6fe 5657 /****************************** WWDG Instances ********************************/
mbed_official 340:28d1f895c6fe 5658 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
mbed_official 340:28d1f895c6fe 5659
mbed_official 340:28d1f895c6fe 5660 /**
mbed_official 340:28d1f895c6fe 5661 * @}
mbed_official 340:28d1f895c6fe 5662 */
mbed_official 340:28d1f895c6fe 5663
mbed_official 340:28d1f895c6fe 5664 /******************************************************************************/
mbed_official 340:28d1f895c6fe 5665 /* For a painless codes migration between the STM32F3xx device product */
mbed_official 340:28d1f895c6fe 5666 /* lines, the aliases defined below are put in place to overcome the */
mbed_official 340:28d1f895c6fe 5667 /* differences in the interrupt handlers and IRQn definitions. */
mbed_official 340:28d1f895c6fe 5668 /* No need to update developed interrupt code when moving across */
mbed_official 340:28d1f895c6fe 5669 /* product lines within the same STM32L0 Family */
mbed_official 340:28d1f895c6fe 5670 /******************************************************************************/
mbed_official 340:28d1f895c6fe 5671
mbed_official 340:28d1f895c6fe 5672 /* Aliases for __IRQn */
mbed_official 340:28d1f895c6fe 5673 #define PVD_IRQn PVD_VDDIO2_IRQn
mbed_official 340:28d1f895c6fe 5674 #define VDDIO2_IRQn PVD_VDDIO2_IRQn
mbed_official 340:28d1f895c6fe 5675 #define RCC_IRQn RCC_CRS_IRQn
mbed_official 340:28d1f895c6fe 5676 #define DMA1_Channel1_IRQn DMA1_Ch1_IRQn
mbed_official 340:28d1f895c6fe 5677 #define DMA1_Channel2_3_IRQn DMA1_Ch2_3_DMA2_Ch1_2_IRQn
mbed_official 340:28d1f895c6fe 5678 #define DMA1_Channel4_5_IRQn DMA1_Ch4_7_DMA2_Ch3_5_IRQn
mbed_official 340:28d1f895c6fe 5679 #define DMA1_Channel4_5_6_7_IRQn DMA1_Ch4_7_DMA2_Ch3_5_IRQn
mbed_official 340:28d1f895c6fe 5680 #define ADC1_IRQn ADC1_COMP_IRQn
mbed_official 340:28d1f895c6fe 5681 #define TIM6_IRQn TIM6_DAC_IRQn
mbed_official 340:28d1f895c6fe 5682 #define USART3_4_IRQn USART3_8_IRQn
mbed_official 340:28d1f895c6fe 5683
mbed_official 340:28d1f895c6fe 5684 /* Aliases for __IRQHandler */
mbed_official 340:28d1f895c6fe 5685 #define PVD_IRQHandler PVD_VDDIO2_IRQHandler
mbed_official 340:28d1f895c6fe 5686 #define VDDIO2_IRQHandler PVD_VDDIO2_IRQHandler
mbed_official 340:28d1f895c6fe 5687 #define RCC_IRQHandler RCC_CRS_IRQHandler
mbed_official 340:28d1f895c6fe 5688 #define DMA1_Channel1_IRQHandler DMA1_Ch1_IRQHandler
mbed_official 340:28d1f895c6fe 5689 #define DMA1_Channel2_3_IRQHandler DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler
mbed_official 340:28d1f895c6fe 5690 #define DMA1_Channel4_5_IRQHandler DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler
mbed_official 340:28d1f895c6fe 5691 #define DMA1_Channel4_5_6_7_IRQHandler DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler
mbed_official 340:28d1f895c6fe 5692 #define ADC1_IRQHandler ADC1_COMP_IRQHandler
mbed_official 340:28d1f895c6fe 5693 #define TIM6_IRQHandler TIM6_DAC_IRQHandler
mbed_official 340:28d1f895c6fe 5694 #define USART3_4_IRQHandler USART3_8_IRQHandler
mbed_official 340:28d1f895c6fe 5695
mbed_official 340:28d1f895c6fe 5696 #ifdef __cplusplus
mbed_official 340:28d1f895c6fe 5697 }
mbed_official 340:28d1f895c6fe 5698 #endif /* __cplusplus */
mbed_official 340:28d1f895c6fe 5699
mbed_official 340:28d1f895c6fe 5700 #endif /* __STM32F091xC_H */
mbed_official 340:28d1f895c6fe 5701
mbed_official 340:28d1f895c6fe 5702 /**
mbed_official 340:28d1f895c6fe 5703 * @}
mbed_official 340:28d1f895c6fe 5704 */
mbed_official 340:28d1f895c6fe 5705
mbed_official 340:28d1f895c6fe 5706 /**
mbed_official 340:28d1f895c6fe 5707 * @}
mbed_official 340:28d1f895c6fe 5708 */
mbed_official 340:28d1f895c6fe 5709
mbed_official 340:28d1f895c6fe 5710 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/