mbed official / mbed-src

mbed library sources

Dependents:   Encrypted my_mbed lklk CyaSSL_DTLS_Cellular ... more

Superseded

This library was superseded by mbed-dev - https://os.mbed.com/users/mbed_official/code/mbed-dev/.

Development branch of the mbed library sources. This library is kept in synch with the latest changes from the mbed SDK and it is not guaranteed to work.

If you are looking for a stable and tested release, please import one of the official mbed library releases:

Import librarymbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Last commit 20 Feb 2019 by mbed official

targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/MBRZA1H.h@579:53297373a894, 2015-07-01 (annotated)

Committer:
mbed_official
Date:
Wed Jul 01 09:45:11 2015 +0100
Revision:
579:53297373a894
Parent:
500:04797f1feae2 
Synchronized with git revision d5b4d2ab9c47edb4dc5776e7177b0c2263459081



Full URL: https://github.com/mbedmicro/mbed/commit/d5b4d2ab9c47edb4dc5776e7177b0c2263459081/



Initial version of drivers for SAMR21

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 390:35c2c1cf29cd 1 /*******************************************************************************
mbed_official 390:35c2c1cf29cd 2 * DISCLAIMER
mbed_official 390:35c2c1cf29cd 3 * This software is supplied by Renesas Electronics Corporation and is only
mbed_official 390:35c2c1cf29cd 4 * intended for use with Renesas products. No other uses are authorized. This
mbed_official 390:35c2c1cf29cd 5 * software is owned by Renesas Electronics Corporation and is protected under
mbed_official 390:35c2c1cf29cd 6 * all applicable laws, including copyright laws.
mbed_official 390:35c2c1cf29cd 7 * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
mbed_official 390:35c2c1cf29cd 8 * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
mbed_official 390:35c2c1cf29cd 9 * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
mbed_official 390:35c2c1cf29cd 10 * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
mbed_official 390:35c2c1cf29cd 11 * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
mbed_official 390:35c2c1cf29cd 12 * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
mbed_official 390:35c2c1cf29cd 13 * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
mbed_official 390:35c2c1cf29cd 14 * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
mbed_official 390:35c2c1cf29cd 15 * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
mbed_official 390:35c2c1cf29cd 16 * Renesas reserves the right, without notice, to make changes to this software
mbed_official 390:35c2c1cf29cd 17 * and to discontinue the availability of this software. By using this software,
mbed_official 390:35c2c1cf29cd 18 * you agree to the additional terms and conditions found by accessing the
mbed_official 390:35c2c1cf29cd 19 * following link:
mbed_official 390:35c2c1cf29cd 20 * http://www.renesas.com/disclaimer
mbed_official 390:35c2c1cf29cd 21 * Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
mbed_official 390:35c2c1cf29cd 22 *******************************************************************************/
mbed_official 390:35c2c1cf29cd 23 /**************************************************************************//**
mbed_official 390:35c2c1cf29cd 24 * @file MBRZA1H.h
mbed_official 390:35c2c1cf29cd 25 * @brief CMSIS Cortex-A9 Core Peripheral Access Layer Header File for
mbed_official 390:35c2c1cf29cd 26 * Renesas MBRZA1H Device Series
mbed_official 390:35c2c1cf29cd 27 * @version
mbed_official 390:35c2c1cf29cd 28 * @date 19 Sept 2013
mbed_official 390:35c2c1cf29cd 29 *
mbed_official 390:35c2c1cf29cd 30 * @note
mbed_official 390:35c2c1cf29cd 31 *
mbed_official 390:35c2c1cf29cd 32 ******************************************************************************/
mbed_official 390:35c2c1cf29cd 33
mbed_official 390:35c2c1cf29cd 34 #ifndef __MBRZA1H_H__
mbed_official 390:35c2c1cf29cd 35 #define __MBRZA1H_H__
mbed_official 390:35c2c1cf29cd 36
mbed_official 390:35c2c1cf29cd 37 #ifdef __cplusplus
mbed_official 390:35c2c1cf29cd 38 extern "C" {
mbed_official 390:35c2c1cf29cd 39 #endif
mbed_official 390:35c2c1cf29cd 40
mbed_official 390:35c2c1cf29cd 41
mbed_official 390:35c2c1cf29cd 42 /* ------------------------- Interrupt Number Definition ------------------------ */
mbed_official 390:35c2c1cf29cd 43
mbed_official 390:35c2c1cf29cd 44 typedef enum IRQn
mbed_official 390:35c2c1cf29cd 45 {
mbed_official 390:35c2c1cf29cd 46 /****** SGI Interrupts Numbers ****************************************/
mbed_official 390:35c2c1cf29cd 47 SGI0_IRQn = 0,
mbed_official 390:35c2c1cf29cd 48 SGI1_IRQn = 1,
mbed_official 390:35c2c1cf29cd 49 SGI2_IRQn = 2,
mbed_official 390:35c2c1cf29cd 50 SGI3_IRQn = 3,
mbed_official 390:35c2c1cf29cd 51 SGI4_IRQn = 4,
mbed_official 390:35c2c1cf29cd 52 SGI5_IRQn = 5,
mbed_official 390:35c2c1cf29cd 53 SGI6_IRQn = 6,
mbed_official 390:35c2c1cf29cd 54 SGI7_IRQn = 7,
mbed_official 390:35c2c1cf29cd 55 SGI8_IRQn = 8,
mbed_official 390:35c2c1cf29cd 56 SGI9_IRQn = 9,
mbed_official 390:35c2c1cf29cd 57 SGI10_IRQn = 10,
mbed_official 390:35c2c1cf29cd 58 SGI11_IRQn = 11,
mbed_official 390:35c2c1cf29cd 59 SGI12_IRQn = 12,
mbed_official 390:35c2c1cf29cd 60 SGI13_IRQn = 13,
mbed_official 390:35c2c1cf29cd 61 SGI14_IRQn = 14,
mbed_official 390:35c2c1cf29cd 62 SGI15_IRQn = 15,
mbed_official 390:35c2c1cf29cd 63
mbed_official 390:35c2c1cf29cd 64 /****** Cortex-A9 Processor Exceptions Numbers ****************************************/
mbed_official 390:35c2c1cf29cd 65 /* 16 - 578 */
mbed_official 390:35c2c1cf29cd 66 PMUIRQ0_IRQn = 16,
mbed_official 390:35c2c1cf29cd 67 COMMRX0_IRQn = 17,
mbed_official 390:35c2c1cf29cd 68 COMMTX0_IRQn = 18,
mbed_official 390:35c2c1cf29cd 69 CTIIRQ0_IRQn = 19,
mbed_official 390:35c2c1cf29cd 70
mbed_official 390:35c2c1cf29cd 71 IRQ0_IRQn = 32,
mbed_official 390:35c2c1cf29cd 72 IRQ1_IRQn = 33,
mbed_official 390:35c2c1cf29cd 73 IRQ2_IRQn = 34,
mbed_official 390:35c2c1cf29cd 74 IRQ3_IRQn = 35,
mbed_official 390:35c2c1cf29cd 75 IRQ4_IRQn = 36,
mbed_official 390:35c2c1cf29cd 76 IRQ5_IRQn = 37,
mbed_official 390:35c2c1cf29cd 77 IRQ6_IRQn = 38,
mbed_official 390:35c2c1cf29cd 78 IRQ7_IRQn = 39,
mbed_official 390:35c2c1cf29cd 79
mbed_official 390:35c2c1cf29cd 80 PL310ERR_IRQn = 40,
mbed_official 390:35c2c1cf29cd 81
mbed_official 390:35c2c1cf29cd 82 DMAINT0_IRQn = 41, /*!< DMAC Interrupt */
mbed_official 390:35c2c1cf29cd 83 DMAINT1_IRQn = 42, /*!< DMAC Interrupt */
mbed_official 390:35c2c1cf29cd 84 DMAINT2_IRQn = 43, /*!< DMAC Interrupt */
mbed_official 390:35c2c1cf29cd 85 DMAINT3_IRQn = 44, /*!< DMAC Interrupt */
mbed_official 390:35c2c1cf29cd 86 DMAINT4_IRQn = 45, /*!< DMAC Interrupt */
mbed_official 390:35c2c1cf29cd 87 DMAINT5_IRQn = 46, /*!< DMAC Interrupt */
mbed_official 390:35c2c1cf29cd 88 DMAINT6_IRQn = 47, /*!< DMAC Interrupt */
mbed_official 390:35c2c1cf29cd 89 DMAINT7_IRQn = 48, /*!< DMAC Interrupt */
mbed_official 390:35c2c1cf29cd 90 DMAINT8_IRQn = 49, /*!< DMAC Interrupt */
mbed_official 390:35c2c1cf29cd 91 DMAINT9_IRQn = 50, /*!< DMAC Interrupt */
mbed_official 390:35c2c1cf29cd 92 DMAINT10_IRQn = 51, /*!< DMAC Interrupt */
mbed_official 390:35c2c1cf29cd 93 DMAINT11_IRQn = 52, /*!< DMAC Interrupt */
mbed_official 390:35c2c1cf29cd 94 DMAINT12_IRQn = 53, /*!< DMAC Interrupt */
mbed_official 390:35c2c1cf29cd 95 DMAINT13_IRQn = 54, /*!< DMAC Interrupt */
mbed_official 390:35c2c1cf29cd 96 DMAINT14_IRQn = 55, /*!< DMAC Interrupt */
mbed_official 390:35c2c1cf29cd 97 DMAINT15_IRQn = 56, /*!< DMAC Interrupt */
mbed_official 390:35c2c1cf29cd 98 DMAERR_IRQn = 57, /*!< DMAC Interrupt */
mbed_official 390:35c2c1cf29cd 99
mbed_official 390:35c2c1cf29cd 100 /* 58-72 Reserved */
mbed_official 390:35c2c1cf29cd 101
mbed_official 390:35c2c1cf29cd 102 USBI0_IRQn = 73,
mbed_official 390:35c2c1cf29cd 103 USBI1_IRQn = 74,
mbed_official 390:35c2c1cf29cd 104
mbed_official 390:35c2c1cf29cd 105 S0_VI_VSYNC0_IRQn = 75,
mbed_official 390:35c2c1cf29cd 106 S0_LO_VSYNC0_IRQn = 76,
mbed_official 390:35c2c1cf29cd 107 S0_VSYNCERR0_IRQn = 77,
mbed_official 390:35c2c1cf29cd 108 GR3_VLINE0_IRQn = 78,
mbed_official 390:35c2c1cf29cd 109 S0_VFIELD0_IRQn = 79,
mbed_official 390:35c2c1cf29cd 110 IV1_VBUFERR0_IRQn = 80,
mbed_official 390:35c2c1cf29cd 111 IV3_VBUFERR0_IRQn = 81,
mbed_official 390:35c2c1cf29cd 112 IV5_VBUFERR0_IRQn = 82,
mbed_official 390:35c2c1cf29cd 113 IV6_VBUFERR0_IRQn = 83,
mbed_official 390:35c2c1cf29cd 114 S0_WLINE0_IRQn = 84,
mbed_official 390:35c2c1cf29cd 115 S1_VI_VSYNC0_IRQn = 85,
mbed_official 390:35c2c1cf29cd 116 S1_LO_VSYNC0_IRQn = 86,
mbed_official 390:35c2c1cf29cd 117 S1_VSYNCERR0_IRQn = 87,
mbed_official 390:35c2c1cf29cd 118 S1_VFIELD0_IRQn = 88,
mbed_official 390:35c2c1cf29cd 119 IV2_VBUFERR0_IRQn = 89,
mbed_official 390:35c2c1cf29cd 120 IV4_VBUFERR0_IRQn = 90,
mbed_official 390:35c2c1cf29cd 121 S1_WLINE0_IRQn = 91,
mbed_official 390:35c2c1cf29cd 122 OIR_VI_VSYNC0_IRQn = 92,
mbed_official 390:35c2c1cf29cd 123 OIR_LO_VSYNC0_IRQn = 93,
mbed_official 390:35c2c1cf29cd 124 OIR_VSYNCERR0_IRQn = 94,
mbed_official 390:35c2c1cf29cd 125 OIR_VFIELD0_IRQn = 95,
mbed_official 390:35c2c1cf29cd 126 IV7_VBUFERR0_IRQn = 96,
mbed_official 390:35c2c1cf29cd 127 IV8_VBUFERR0_IRQn = 97,
mbed_official 390:35c2c1cf29cd 128 /* 98 Reserved */
mbed_official 390:35c2c1cf29cd 129 S0_VI_VSYNC1_IRQn = 99,
mbed_official 390:35c2c1cf29cd 130 S0_LO_VSYNC1_IRQn = 100,
mbed_official 390:35c2c1cf29cd 131 S0_VSYNCERR1_IRQn = 101,
mbed_official 390:35c2c1cf29cd 132 GR3_VLINE1_IRQn = 102,
mbed_official 390:35c2c1cf29cd 133 S0_VFIELD1_IRQn = 103,
mbed_official 390:35c2c1cf29cd 134 IV1_VBUFERR1_IRQn = 104,
mbed_official 390:35c2c1cf29cd 135 IV3_VBUFERR1_IRQn = 105,
mbed_official 390:35c2c1cf29cd 136 IV5_VBUFERR1_IRQn = 106,
mbed_official 390:35c2c1cf29cd 137 IV6_VBUFERR1_IRQn = 107,
mbed_official 390:35c2c1cf29cd 138 S0_WLINE1_IRQn = 108,
mbed_official 390:35c2c1cf29cd 139 S1_VI_VSYNC1_IRQn = 109,
mbed_official 390:35c2c1cf29cd 140 S1_LO_VSYNC1_IRQn = 110,
mbed_official 390:35c2c1cf29cd 141 S1_VSYNCERR1_IRQn = 111,
mbed_official 390:35c2c1cf29cd 142 S1_VFIELD1_IRQn = 112,
mbed_official 390:35c2c1cf29cd 143 IV2_VBUFERR1_IRQn = 113,
mbed_official 390:35c2c1cf29cd 144 IV4_VBUFERR1_IRQn = 114,
mbed_official 390:35c2c1cf29cd 145 S1_WLINE1_IRQn = 115,
mbed_official 390:35c2c1cf29cd 146 OIR_VI_VSYNC1_IRQn = 116,
mbed_official 390:35c2c1cf29cd 147 OIR_LO_VSYNC1_IRQn = 117,
mbed_official 390:35c2c1cf29cd 148 OIR_VSYNCERR1_IRQn = 118,
mbed_official 390:35c2c1cf29cd 149 OIR_VFIELD1_IRQn = 119,
mbed_official 390:35c2c1cf29cd 150 IV7_VBUFERR1_IRQn = 120,
mbed_official 390:35c2c1cf29cd 151 IV8_VBUFERR1_IRQn = 121,
mbed_official 390:35c2c1cf29cd 152 /* Reserved = 122 */
mbed_official 390:35c2c1cf29cd 153
mbed_official 390:35c2c1cf29cd 154 IMRDI_IRQn = 123,
mbed_official 390:35c2c1cf29cd 155 IMR2I0_IRQn = 124,
mbed_official 390:35c2c1cf29cd 156 IMR2I1_IRQn = 125,
mbed_official 390:35c2c1cf29cd 157
mbed_official 390:35c2c1cf29cd 158 JEDI_IRQn = 126,
mbed_official 390:35c2c1cf29cd 159 JDTI_IRQn = 127,
mbed_official 390:35c2c1cf29cd 160
mbed_official 390:35c2c1cf29cd 161 CMP0_IRQn = 128,
mbed_official 390:35c2c1cf29cd 162 CMP1_IRQn = 129,
mbed_official 390:35c2c1cf29cd 163
mbed_official 390:35c2c1cf29cd 164 INT0_IRQn = 130,
mbed_official 390:35c2c1cf29cd 165 INT1_IRQn = 131,
mbed_official 390:35c2c1cf29cd 166 INT2_IRQn = 132,
mbed_official 390:35c2c1cf29cd 167 INT3_IRQn = 133,
mbed_official 390:35c2c1cf29cd 168
mbed_official 390:35c2c1cf29cd 169 OSTMI0TINT_IRQn = 134, /*!< OSTM Interrupt */
mbed_official 390:35c2c1cf29cd 170 OSTMI1TINT_IRQn = 135, /*!< OSTM Interrupt */
mbed_official 390:35c2c1cf29cd 171
mbed_official 390:35c2c1cf29cd 172 CMI_IRQn = 136,
mbed_official 390:35c2c1cf29cd 173 WTOUT_IRQn = 137,
mbed_official 390:35c2c1cf29cd 174
mbed_official 390:35c2c1cf29cd 175 ITI_IRQn = 138,
mbed_official 390:35c2c1cf29cd 176
mbed_official 390:35c2c1cf29cd 177 TGI0A_IRQn = 139,
mbed_official 390:35c2c1cf29cd 178 TGI0B_IRQn = 140,
mbed_official 390:35c2c1cf29cd 179 TGI0C_IRQn = 141,
mbed_official 390:35c2c1cf29cd 180 TGI0D_IRQn = 142,
mbed_official 390:35c2c1cf29cd 181 TGI0V_IRQn = 143,
mbed_official 390:35c2c1cf29cd 182 TGI0E_IRQn = 144,
mbed_official 390:35c2c1cf29cd 183 TGI0F_IRQn = 145,
mbed_official 390:35c2c1cf29cd 184 TGI1A_IRQn = 146,
mbed_official 390:35c2c1cf29cd 185 TGI1B_IRQn = 147,
mbed_official 390:35c2c1cf29cd 186 TGI1V_IRQn = 148,
mbed_official 390:35c2c1cf29cd 187 TGI1U_IRQn = 149,
mbed_official 390:35c2c1cf29cd 188 TGI2A_IRQn = 150,
mbed_official 390:35c2c1cf29cd 189 TGI2B_IRQn = 151,
mbed_official 390:35c2c1cf29cd 190 TGI2V_IRQn = 152,
mbed_official 390:35c2c1cf29cd 191 TGI2U_IRQn = 153,
mbed_official 390:35c2c1cf29cd 192 TGI3A_IRQn = 154,
mbed_official 390:35c2c1cf29cd 193 TGI3B_IRQn = 155,
mbed_official 390:35c2c1cf29cd 194 TGI3C_IRQn = 156,
mbed_official 390:35c2c1cf29cd 195 TGI3D_IRQn = 157,
mbed_official 390:35c2c1cf29cd 196 TGI3V_IRQn = 158,
mbed_official 390:35c2c1cf29cd 197 TGI4A_IRQn = 159,
mbed_official 390:35c2c1cf29cd 198 TGI4B_IRQn = 160,
mbed_official 390:35c2c1cf29cd 199 TGI4C_IRQn = 161,
mbed_official 390:35c2c1cf29cd 200 TGI4D_IRQn = 162,
mbed_official 390:35c2c1cf29cd 201 TGI4V_IRQn = 163,
mbed_official 390:35c2c1cf29cd 202
mbed_official 390:35c2c1cf29cd 203 CMI1_IRQn = 164,
mbed_official 390:35c2c1cf29cd 204 CMI2_IRQn = 165,
mbed_official 390:35c2c1cf29cd 205
mbed_official 390:35c2c1cf29cd 206 SGDEI0_IRQn = 166,
mbed_official 390:35c2c1cf29cd 207 SGDEI1_IRQn = 167,
mbed_official 390:35c2c1cf29cd 208 SGDEI2_IRQn = 168,
mbed_official 390:35c2c1cf29cd 209 SGDEI3_IRQn = 169,
mbed_official 390:35c2c1cf29cd 210
mbed_official 390:35c2c1cf29cd 211 ADI_IRQn = 170,
mbed_official 390:35c2c1cf29cd 212 LMTI_IRQn = 171,
mbed_official 390:35c2c1cf29cd 213
mbed_official 390:35c2c1cf29cd 214 SSII0_IRQn = 172, /*!< SSIF Interrupt */
mbed_official 390:35c2c1cf29cd 215 SSIRXI0_IRQn = 173, /*!< SSIF Interrupt */
mbed_official 390:35c2c1cf29cd 216 SSITXI0_IRQn = 174, /*!< SSIF Interrupt */
mbed_official 390:35c2c1cf29cd 217 SSII1_IRQn = 175, /*!< SSIF Interrupt */
mbed_official 390:35c2c1cf29cd 218 SSIRXI1_IRQn = 176, /*!< SSIF Interrupt */
mbed_official 390:35c2c1cf29cd 219 SSITXI1_IRQn = 177, /*!< SSIF Interrupt */
mbed_official 390:35c2c1cf29cd 220 SSII2_IRQn = 178, /*!< SSIF Interrupt */
mbed_official 390:35c2c1cf29cd 221 SSIRTI2_IRQn = 179, /*!< SSIF Interrupt */
mbed_official 390:35c2c1cf29cd 222 SSII3_IRQn = 180, /*!< SSIF Interrupt */
mbed_official 390:35c2c1cf29cd 223 SSIRXI3_IRQn = 181, /*!< SSIF Interrupt */
mbed_official 390:35c2c1cf29cd 224 SSITXI3_IRQn = 182, /*!< SSIF Interrupt */
mbed_official 390:35c2c1cf29cd 225 SSII4_IRQn = 183, /*!< SSIF Interrupt */
mbed_official 390:35c2c1cf29cd 226 SSIRTI4_IRQn = 184, /*!< SSIF Interrupt */
mbed_official 390:35c2c1cf29cd 227 SSII5_IRQn = 185, /*!< SSIF Interrupt */
mbed_official 390:35c2c1cf29cd 228 SSIRXI5_IRQn = 186, /*!< SSIF Interrupt */
mbed_official 390:35c2c1cf29cd 229 SSITXI5_IRQn = 187, /*!< SSIF Interrupt */
mbed_official 390:35c2c1cf29cd 230
mbed_official 390:35c2c1cf29cd 231 SPDIFI_IRQn = 188,
mbed_official 390:35c2c1cf29cd 232
mbed_official 390:35c2c1cf29cd 233 INTIICTEI0_IRQn = 189, /*!< RIIC Interrupt */
mbed_official 390:35c2c1cf29cd 234 INTIICRI0_IRQn = 190, /*!< RIIC Interrupt */
mbed_official 390:35c2c1cf29cd 235 INTIICTI0_IRQn = 191, /*!< RIIC Interrupt */
mbed_official 390:35c2c1cf29cd 236 INTIICSPI0_IRQn = 192, /*!< RIIC Interrupt */
mbed_official 390:35c2c1cf29cd 237 INTIICSTI0_IRQn = 193, /*!< RIIC Interrupt */
mbed_official 390:35c2c1cf29cd 238 INTIICNAKI0_IRQn = 194, /*!< RIIC Interrupt */
mbed_official 390:35c2c1cf29cd 239 INTIICALI0_IRQn = 195, /*!< RIIC Interrupt */
mbed_official 390:35c2c1cf29cd 240 INTIICTMOI0_IRQn = 196, /*!< RIIC Interrupt */
mbed_official 390:35c2c1cf29cd 241 INTIICTEI1_IRQn = 197, /*!< RIIC Interrupt */
mbed_official 390:35c2c1cf29cd 242 INTIICRI1_IRQn = 198, /*!< RIIC Interrupt */
mbed_official 390:35c2c1cf29cd 243 INTIICTI1_IRQn = 199, /*!< RIIC Interrupt */
mbed_official 390:35c2c1cf29cd 244 INTIICSPI1_IRQn = 200, /*!< RIIC Interrupt */
mbed_official 390:35c2c1cf29cd 245 INTIICSTI1_IRQn = 201, /*!< RIIC Interrupt */
mbed_official 390:35c2c1cf29cd 246 INTIICNAKI1_IRQn = 202, /*!< RIIC Interrupt */
mbed_official 390:35c2c1cf29cd 247 INTIICALI1_IRQn = 203, /*!< RIIC Interrupt */
mbed_official 390:35c2c1cf29cd 248 INTIICTMOI1_IRQn = 204, /*!< RIIC Interrupt */
mbed_official 390:35c2c1cf29cd 249 INTIICTEI2_IRQn = 205, /*!< RIIC Interrupt */
mbed_official 390:35c2c1cf29cd 250 INTIICRI2_IRQn = 206, /*!< RIIC Interrupt */
mbed_official 390:35c2c1cf29cd 251 INTIICTI2_IRQn = 207, /*!< RIIC Interrupt */
mbed_official 390:35c2c1cf29cd 252 INTIICSPI2_IRQn = 208, /*!< RIIC Interrupt */
mbed_official 390:35c2c1cf29cd 253 INTIICSTI2_IRQn = 209, /*!< RIIC Interrupt */
mbed_official 390:35c2c1cf29cd 254 INTIICNAKI2_IRQn = 210, /*!< RIIC Interrupt */
mbed_official 390:35c2c1cf29cd 255 INTIICALI2_IRQn = 211, /*!< RIIC Interrupt */
mbed_official 390:35c2c1cf29cd 256 INTIICTMOI2_IRQn = 212, /*!< RIIC Interrupt */
mbed_official 390:35c2c1cf29cd 257 INTIICTEI3_IRQn = 213, /*!< RIIC Interrupt */
mbed_official 390:35c2c1cf29cd 258 INTIICRI3_IRQn = 214, /*!< RIIC Interrupt */
mbed_official 390:35c2c1cf29cd 259 INTIICTI3_IRQn = 215, /*!< RIIC Interrupt */
mbed_official 390:35c2c1cf29cd 260 INTIICSPI3_IRQn = 216, /*!< RIIC Interrupt */
mbed_official 390:35c2c1cf29cd 261 INTIICSTI3_IRQn = 217, /*!< RIIC Interrupt */
mbed_official 390:35c2c1cf29cd 262 INTIICNAKI3_IRQn = 218, /*!< RIIC Interrupt */
mbed_official 390:35c2c1cf29cd 263 INTIICALI3_IRQn = 219, /*!< RIIC Interrupt */
mbed_official 390:35c2c1cf29cd 264 INTIICTMOI3_IRQn = 220, /*!< RIIC Interrupt */
mbed_official 390:35c2c1cf29cd 265
mbed_official 390:35c2c1cf29cd 266 SCIFBRI0_IRQn = 221, /*!< SCIF Interrupt */
mbed_official 390:35c2c1cf29cd 267 SCIFERI0_IRQn = 222, /*!< SCIF Interrupt */
mbed_official 390:35c2c1cf29cd 268 SCIFRXI0_IRQn = 223, /*!< SCIF Interrupt */
mbed_official 390:35c2c1cf29cd 269 SCIFTXI0_IRQn = 224, /*!< SCIF Interrupt */
mbed_official 390:35c2c1cf29cd 270 SCIFBRI1_IRQn = 225, /*!< SCIF Interrupt */
mbed_official 390:35c2c1cf29cd 271 SCIFERI1_IRQn = 226, /*!< SCIF Interrupt */
mbed_official 390:35c2c1cf29cd 272 SCIFRXI1_IRQn = 227, /*!< SCIF Interrupt */
mbed_official 390:35c2c1cf29cd 273 SCIFTXI1_IRQn = 228, /*!< SCIF Interrupt */
mbed_official 390:35c2c1cf29cd 274 SCIFBRI2_IRQn = 229, /*!< SCIF Interrupt */
mbed_official 390:35c2c1cf29cd 275 SCIFERI2_IRQn = 230, /*!< SCIF Interrupt */
mbed_official 390:35c2c1cf29cd 276 SCIFRXI2_IRQn = 231, /*!< SCIF Interrupt */
mbed_official 390:35c2c1cf29cd 277 SCIFTXI2_IRQn = 232, /*!< SCIF Interrupt */
mbed_official 390:35c2c1cf29cd 278 SCIFBRI3_IRQn = 233, /*!< SCIF Interrupt */
mbed_official 390:35c2c1cf29cd 279 SCIFERI3_IRQn = 234, /*!< SCIF Interrupt */
mbed_official 390:35c2c1cf29cd 280 SCIFRXI3_IRQn = 235, /*!< SCIF Interrupt */
mbed_official 390:35c2c1cf29cd 281 SCIFTXI3_IRQn = 236, /*!< SCIF Interrupt */
mbed_official 390:35c2c1cf29cd 282 SCIFBRI4_IRQn = 237, /*!< SCIF Interrupt */
mbed_official 390:35c2c1cf29cd 283 SCIFERI4_IRQn = 238, /*!< SCIF Interrupt */
mbed_official 390:35c2c1cf29cd 284 SCIFRXI4_IRQn = 239, /*!< SCIF Interrupt */
mbed_official 390:35c2c1cf29cd 285 SCIFTXI4_IRQn = 240, /*!< SCIF Interrupt */
mbed_official 390:35c2c1cf29cd 286 SCIFBRI5_IRQn = 241, /*!< SCIF Interrupt */
mbed_official 390:35c2c1cf29cd 287 SCIFERI5_IRQn = 242, /*!< SCIF Interrupt */
mbed_official 390:35c2c1cf29cd 288 SCIFRXI5_IRQn = 243, /*!< SCIF Interrupt */
mbed_official 390:35c2c1cf29cd 289 SCIFTXI5_IRQn = 244, /*!< SCIF Interrupt */
mbed_official 390:35c2c1cf29cd 290 SCIFBRI6_IRQn = 245, /*!< SCIF Interrupt */
mbed_official 390:35c2c1cf29cd 291 SCIFERI6_IRQn = 246, /*!< SCIF Interrupt */
mbed_official 390:35c2c1cf29cd 292 SCIFRXI6_IRQn = 247, /*!< SCIF Interrupt */
mbed_official 390:35c2c1cf29cd 293 SCIFTXI6_IRQn = 248, /*!< SCIF Interrupt */
mbed_official 390:35c2c1cf29cd 294 SCIFBRI7_IRQn = 249, /*!< SCIF Interrupt */
mbed_official 390:35c2c1cf29cd 295 SCIFERI7_IRQn = 250, /*!< SCIF Interrupt */
mbed_official 390:35c2c1cf29cd 296 SCIFRXI7_IRQn = 251, /*!< SCIF Interrupt */
mbed_official 390:35c2c1cf29cd 297 SCIFTXI7_IRQn = 252, /*!< SCIF Interrupt */
mbed_official 390:35c2c1cf29cd 298
mbed_official 390:35c2c1cf29cd 299 INTRCANGERR_IRQn = 253,
mbed_official 390:35c2c1cf29cd 300 INTRCANGRECC_IRQn = 254,
mbed_official 390:35c2c1cf29cd 301 INTRCAN0REC_IRQn = 255,
mbed_official 390:35c2c1cf29cd 302 INTRCAN0ERR_IRQn = 256,
mbed_official 390:35c2c1cf29cd 303 INTRCAN0TRX_IRQn = 257,
mbed_official 390:35c2c1cf29cd 304 INTRCAN1REC_IRQn = 258,
mbed_official 390:35c2c1cf29cd 305 INTRCAN1ERR_IRQn = 259,
mbed_official 390:35c2c1cf29cd 306 INTRCAN1TRX_IRQn = 260,
mbed_official 390:35c2c1cf29cd 307 INTRCAN2REC_IRQn = 261,
mbed_official 390:35c2c1cf29cd 308 INTRCAN2ERR_IRQn = 262,
mbed_official 390:35c2c1cf29cd 309 INTRCAN2TRX_IRQn = 263,
mbed_official 390:35c2c1cf29cd 310 INTRCAN3REC_IRQn = 264,
mbed_official 390:35c2c1cf29cd 311 INTRCAN3ERR_IRQn = 265,
mbed_official 390:35c2c1cf29cd 312 INTRCAN3TRX_IRQn = 266,
mbed_official 390:35c2c1cf29cd 313 INTRCAN4REC_IRQn = 267,
mbed_official 390:35c2c1cf29cd 314 INTRCAN4ERR_IRQn = 268,
mbed_official 390:35c2c1cf29cd 315 INTRCAN4TRX_IRQn = 269,
mbed_official 390:35c2c1cf29cd 316
mbed_official 390:35c2c1cf29cd 317 RSPISPEI0_IRQn = 270, /*!< RSPI Interrupt */
mbed_official 390:35c2c1cf29cd 318 RSPISPRI0_IRQn = 271, /*!< RSPI Interrupt */
mbed_official 390:35c2c1cf29cd 319 RSPISPTI0_IRQn = 272, /*!< RSPI Interrupt */
mbed_official 390:35c2c1cf29cd 320 RSPISPEI1_IRQn = 273, /*!< RSPI Interrupt */
mbed_official 390:35c2c1cf29cd 321 RSPISPRI1_IRQn = 274, /*!< RSPI Interrupt */
mbed_official 390:35c2c1cf29cd 322 RSPISPTI1_IRQn = 275, /*!< RSPI Interrupt */
mbed_official 390:35c2c1cf29cd 323 RSPISPEI2_IRQn = 276, /*!< RSPI Interrupt */
mbed_official 390:35c2c1cf29cd 324 RSPISPRI2_IRQn = 277, /*!< RSPI Interrupt */
mbed_official 390:35c2c1cf29cd 325 RSPISPTI2_IRQn = 278, /*!< RSPI Interrupt */
mbed_official 390:35c2c1cf29cd 326 RSPISPEI3_IRQn = 279, /*!< RSPI Interrupt */
mbed_official 390:35c2c1cf29cd 327 RSPISPRI3_IRQn = 280, /*!< RSPI Interrupt */
mbed_official 390:35c2c1cf29cd 328 RSPISPTI3_IRQn = 281, /*!< RSPI Interrupt */
mbed_official 390:35c2c1cf29cd 329 RSPISPEI4_IRQn = 282, /*!< RSPI Interrupt */
mbed_official 390:35c2c1cf29cd 330 RSPISPRI4_IRQn = 283, /*!< RSPI Interrupt */
mbed_official 390:35c2c1cf29cd 331 RSPISPTI4_IRQn = 284, /*!< RSPI Interrupt */
mbed_official 390:35c2c1cf29cd 332
mbed_official 390:35c2c1cf29cd 333 IEBBTD_IRQn = 285,
mbed_official 390:35c2c1cf29cd 334 IEBBTERR_IRQn = 286,
mbed_official 390:35c2c1cf29cd 335 IEBBTSTA_IRQn = 287,
mbed_official 390:35c2c1cf29cd 336 IEBBTV_IRQn = 288,
mbed_official 390:35c2c1cf29cd 337
mbed_official 390:35c2c1cf29cd 338 ISY_IRQn = 289,
mbed_official 390:35c2c1cf29cd 339 IERR_IRQn = 290,
mbed_official 390:35c2c1cf29cd 340 ITARG_IRQn = 291,
mbed_official 390:35c2c1cf29cd 341 ISEC_IRQn = 292,
mbed_official 390:35c2c1cf29cd 342 IBUF_IRQn = 293,
mbed_official 390:35c2c1cf29cd 343 IREADY_IRQn = 294,
mbed_official 390:35c2c1cf29cd 344
mbed_official 390:35c2c1cf29cd 345 STERB_IRQn = 295,
mbed_official 390:35c2c1cf29cd 346 FLTENDI_IRQn = 296,
mbed_official 390:35c2c1cf29cd 347 FLTREQ0I_IRQn = 297,
mbed_official 390:35c2c1cf29cd 348 FLTREQ1I_IRQn = 298,
mbed_official 390:35c2c1cf29cd 349
mbed_official 390:35c2c1cf29cd 350 MMC0_IRQn = 299,
mbed_official 390:35c2c1cf29cd 351 MMC1_IRQn = 300,
mbed_official 390:35c2c1cf29cd 352 MMC2_IRQn = 301,
mbed_official 390:35c2c1cf29cd 353
mbed_official 390:35c2c1cf29cd 354 SCHI0_3_IRQn = 302,
mbed_official 390:35c2c1cf29cd 355 SDHI0_0_IRQn = 303,
mbed_official 390:35c2c1cf29cd 356 SDHI0_1_IRQn = 304,
mbed_official 390:35c2c1cf29cd 357 SCHI1_3_IRQn = 305,
mbed_official 390:35c2c1cf29cd 358 SDHI1_0_IRQn = 306,
mbed_official 390:35c2c1cf29cd 359 SDHI1_1_IRQn = 307,
mbed_official 390:35c2c1cf29cd 360
mbed_official 390:35c2c1cf29cd 361 ARM_IRQn = 308,
mbed_official 390:35c2c1cf29cd 362 PRD_IRQn = 309,
mbed_official 390:35c2c1cf29cd 363 CUP_IRQn = 310,
mbed_official 390:35c2c1cf29cd 364
mbed_official 390:35c2c1cf29cd 365 SCUAI0_IRQn = 311,
mbed_official 390:35c2c1cf29cd 366 SCUAI1_IRQn = 312,
mbed_official 390:35c2c1cf29cd 367 SCUFDI0_IRQn = 313,
mbed_official 390:35c2c1cf29cd 368 SCUFDI1_IRQn = 314,
mbed_official 390:35c2c1cf29cd 369 SCUFDI2_IRQn = 315,
mbed_official 390:35c2c1cf29cd 370 SCUFDI3_IRQn = 316,
mbed_official 390:35c2c1cf29cd 371 SCUFUI0_IRQn = 317,
mbed_official 390:35c2c1cf29cd 372 SCUFUI1_IRQn = 318,
mbed_official 390:35c2c1cf29cd 373 SCUFUI2_IRQn = 319,
mbed_official 390:35c2c1cf29cd 374 SCUFUI3_IRQn = 320,
mbed_official 390:35c2c1cf29cd 375 SCUDVI0_IRQn = 321,
mbed_official 390:35c2c1cf29cd 376 SCUDVI1_IRQn = 322,
mbed_official 390:35c2c1cf29cd 377 SCUDVI2_IRQn = 323,
mbed_official 390:35c2c1cf29cd 378 SCUDVI3_IRQn = 324,
mbed_official 390:35c2c1cf29cd 379
mbed_official 390:35c2c1cf29cd 380 MLB_CINT_IRQn = 325,
mbed_official 390:35c2c1cf29cd 381 MLB_SINT_IRQn = 326,
mbed_official 390:35c2c1cf29cd 382
mbed_official 390:35c2c1cf29cd 383 DRC10_IRQn = 327,
mbed_official 390:35c2c1cf29cd 384 DRC11_IRQn = 328,
mbed_official 390:35c2c1cf29cd 385
mbed_official 390:35c2c1cf29cd 386 /* 329-330 Reserved */
mbed_official 390:35c2c1cf29cd 387
mbed_official 390:35c2c1cf29cd 388 LINI0_INT_T_IRQn = 331,
mbed_official 390:35c2c1cf29cd 389 LINI0_INT_R_IRQn = 332,
mbed_official 390:35c2c1cf29cd 390 LINI0_INT_S_IRQn = 333,
mbed_official 390:35c2c1cf29cd 391 LINI0_INT_M_IRQn = 334,
mbed_official 390:35c2c1cf29cd 392 LINI1_INT_T_IRQn = 335,
mbed_official 390:35c2c1cf29cd 393 LINI1_INT_R_IRQn = 336,
mbed_official 390:35c2c1cf29cd 394 LINI1_INT_S_IRQn = 337,
mbed_official 390:35c2c1cf29cd 395 LINI1_INT_M_IRQn = 338,
mbed_official 390:35c2c1cf29cd 396
mbed_official 390:35c2c1cf29cd 397 /* 339-346 Reserved */
mbed_official 390:35c2c1cf29cd 398
mbed_official 390:35c2c1cf29cd 399 SCIERI0_IRQn = 347,
mbed_official 390:35c2c1cf29cd 400 SCIRXI0_IRQn = 348,
mbed_official 390:35c2c1cf29cd 401 SCITXI0_IRQn = 349,
mbed_official 390:35c2c1cf29cd 402 SCITEI0_IRQn = 350,
mbed_official 390:35c2c1cf29cd 403 SCIERI1_IRQn = 351,
mbed_official 390:35c2c1cf29cd 404 SCIRXI1_IRQn = 352,
mbed_official 390:35c2c1cf29cd 405 SCITXI1_IRQn = 353,
mbed_official 390:35c2c1cf29cd 406 SCITEI1_IRQn = 354,
mbed_official 390:35c2c1cf29cd 407
mbed_official 390:35c2c1cf29cd 408 AVBI_DATA = 355,
mbed_official 390:35c2c1cf29cd 409 AVBI_ERROR = 356,
mbed_official 390:35c2c1cf29cd 410 AVBI_MANAGE = 357,
mbed_official 390:35c2c1cf29cd 411 AVBI_MAC = 358,
mbed_official 390:35c2c1cf29cd 412
mbed_official 390:35c2c1cf29cd 413 ETHERI_IRQn = 359,
mbed_official 390:35c2c1cf29cd 414
mbed_official 390:35c2c1cf29cd 415 /* 360-363 Reserved */
mbed_official 390:35c2c1cf29cd 416
mbed_official 390:35c2c1cf29cd 417 CEUI_IRQn = 364,
mbed_official 390:35c2c1cf29cd 418
mbed_official 390:35c2c1cf29cd 419 /* 365-380 Reserved */
mbed_official 390:35c2c1cf29cd 420
mbed_official 390:35c2c1cf29cd 421
mbed_official 390:35c2c1cf29cd 422 H2XMLB_ERRINT_IRQn = 381,
mbed_official 390:35c2c1cf29cd 423 H2XIC1_ERRINT_IRQn = 382,
mbed_official 390:35c2c1cf29cd 424 X2HPERI1_ERRINT_IRQn = 383,
mbed_official 390:35c2c1cf29cd 425 X2HPERR2_ERRINT_IRQn = 384,
mbed_official 390:35c2c1cf29cd 426 X2HPERR34_ERRINT_IRQn= 385,
mbed_official 390:35c2c1cf29cd 427 X2HPERR5_ERRINT_IRQn = 386,
mbed_official 390:35c2c1cf29cd 428 X2HPERR67_ERRINT_IRQn= 387,
mbed_official 390:35c2c1cf29cd 429 X2HDBGR_ERRINT_IRQn = 388,
mbed_official 390:35c2c1cf29cd 430 X2HBSC_ERRINT_IRQn = 389,
mbed_official 390:35c2c1cf29cd 431 X2HSPI1_ERRINT_IRQn = 390,
mbed_official 390:35c2c1cf29cd 432 X2HSPI2_ERRINT_IRQn = 391,
mbed_official 390:35c2c1cf29cd 433 PRRI_IRQn = 392,
mbed_official 390:35c2c1cf29cd 434
mbed_official 390:35c2c1cf29cd 435 IFEI0_IRQn = 393,
mbed_official 390:35c2c1cf29cd 436 OFFI0_IRQn = 394,
mbed_official 390:35c2c1cf29cd 437 PFVEI0_IRQn = 395,
mbed_official 390:35c2c1cf29cd 438 IFEI1_IRQn = 396,
mbed_official 390:35c2c1cf29cd 439 OFFI1_IRQn = 397,
mbed_official 390:35c2c1cf29cd 440 PFVEI1_IRQn = 398,
mbed_official 390:35c2c1cf29cd 441
mbed_official 390:35c2c1cf29cd 442 /* 399-415 Reserved */
mbed_official 390:35c2c1cf29cd 443 TINT0_IRQn = 416,
mbed_official 390:35c2c1cf29cd 444 TINT1_IRQn = 417,
mbed_official 390:35c2c1cf29cd 445 TINT2_IRQn = 418,
mbed_official 390:35c2c1cf29cd 446 TINT3_IRQn = 419,
mbed_official 390:35c2c1cf29cd 447 TINT4_IRQn = 420,
mbed_official 390:35c2c1cf29cd 448 TINT5_IRQn = 421,
mbed_official 390:35c2c1cf29cd 449 TINT6_IRQn = 422,
mbed_official 390:35c2c1cf29cd 450 TINT7_IRQn = 423,
mbed_official 390:35c2c1cf29cd 451 TINT8_IRQn = 424,
mbed_official 390:35c2c1cf29cd 452 TINT9_IRQn = 425,
mbed_official 390:35c2c1cf29cd 453 TINT10_IRQn = 426,
mbed_official 390:35c2c1cf29cd 454 TINT11_IRQn = 427,
mbed_official 390:35c2c1cf29cd 455 TINT12_IRQn = 428,
mbed_official 390:35c2c1cf29cd 456 TINT13_IRQn = 429,
mbed_official 390:35c2c1cf29cd 457 TINT14_IRQn = 430,
mbed_official 390:35c2c1cf29cd 458 TINT15_IRQn = 431,
mbed_official 390:35c2c1cf29cd 459 TINT16_IRQn = 432,
mbed_official 390:35c2c1cf29cd 460 TINT17_IRQn = 433,
mbed_official 390:35c2c1cf29cd 461 TINT18_IRQn = 434,
mbed_official 390:35c2c1cf29cd 462 TINT19_IRQn = 435,
mbed_official 390:35c2c1cf29cd 463 TINT20_IRQn = 436,
mbed_official 390:35c2c1cf29cd 464 TINT21_IRQn = 437,
mbed_official 390:35c2c1cf29cd 465 TINT22_IRQn = 438,
mbed_official 390:35c2c1cf29cd 466 TINT23_IRQn = 439,
mbed_official 390:35c2c1cf29cd 467 TINT24_IRQn = 440,
mbed_official 390:35c2c1cf29cd 468 TINT25_IRQn = 441,
mbed_official 390:35c2c1cf29cd 469 TINT26_IRQn = 442,
mbed_official 390:35c2c1cf29cd 470 TINT27_IRQn = 443,
mbed_official 390:35c2c1cf29cd 471 TINT28_IRQn = 444,
mbed_official 390:35c2c1cf29cd 472 TINT29_IRQn = 445,
mbed_official 390:35c2c1cf29cd 473 TINT30_IRQn = 446,
mbed_official 390:35c2c1cf29cd 474 TINT31_IRQn = 447,
mbed_official 390:35c2c1cf29cd 475 TINT32_IRQn = 448,
mbed_official 390:35c2c1cf29cd 476 TINT33_IRQn = 449,
mbed_official 390:35c2c1cf29cd 477 TINT34_IRQn = 450,
mbed_official 390:35c2c1cf29cd 478 TINT35_IRQn = 451,
mbed_official 390:35c2c1cf29cd 479 TINT36_IRQn = 452,
mbed_official 390:35c2c1cf29cd 480 TINT37_IRQn = 453,
mbed_official 390:35c2c1cf29cd 481 TINT38_IRQn = 454,
mbed_official 390:35c2c1cf29cd 482 TINT39_IRQn = 455,
mbed_official 390:35c2c1cf29cd 483 TINT40_IRQn = 456,
mbed_official 390:35c2c1cf29cd 484 TINT41_IRQn = 457,
mbed_official 390:35c2c1cf29cd 485 TINT42_IRQn = 458,
mbed_official 390:35c2c1cf29cd 486 TINT43_IRQn = 459,
mbed_official 390:35c2c1cf29cd 487 TINT44_IRQn = 460,
mbed_official 390:35c2c1cf29cd 488 TINT45_IRQn = 461,
mbed_official 390:35c2c1cf29cd 489 TINT46_IRQn = 462,
mbed_official 390:35c2c1cf29cd 490 TINT47_IRQn = 463,
mbed_official 390:35c2c1cf29cd 491 TINT48_IRQn = 464,
mbed_official 390:35c2c1cf29cd 492 TINT49_IRQn = 465,
mbed_official 390:35c2c1cf29cd 493 TINT50_IRQn = 466,
mbed_official 390:35c2c1cf29cd 494 TINT51_IRQn = 467,
mbed_official 390:35c2c1cf29cd 495 TINT52_IRQn = 468,
mbed_official 390:35c2c1cf29cd 496 TINT53_IRQn = 469,
mbed_official 390:35c2c1cf29cd 497 TINT54_IRQn = 470,
mbed_official 390:35c2c1cf29cd 498 TINT55_IRQn = 471,
mbed_official 390:35c2c1cf29cd 499 TINT56_IRQn = 472,
mbed_official 390:35c2c1cf29cd 500 TINT57_IRQn = 473,
mbed_official 390:35c2c1cf29cd 501 TINT58_IRQn = 474,
mbed_official 390:35c2c1cf29cd 502 TINT59_IRQn = 475,
mbed_official 390:35c2c1cf29cd 503 TINT60_IRQn = 476,
mbed_official 390:35c2c1cf29cd 504 TINT61_IRQn = 477,
mbed_official 390:35c2c1cf29cd 505 TINT62_IRQn = 478,
mbed_official 390:35c2c1cf29cd 506 TINT63_IRQn = 479,
mbed_official 390:35c2c1cf29cd 507 TINT64_IRQn = 480,
mbed_official 390:35c2c1cf29cd 508 TINT65_IRQn = 481,
mbed_official 390:35c2c1cf29cd 509 TINT66_IRQn = 482,
mbed_official 390:35c2c1cf29cd 510 TINT67_IRQn = 483,
mbed_official 390:35c2c1cf29cd 511 TINT68_IRQn = 484,
mbed_official 390:35c2c1cf29cd 512 TINT69_IRQn = 485,
mbed_official 390:35c2c1cf29cd 513 TINT70_IRQn = 486,
mbed_official 390:35c2c1cf29cd 514 TINT71_IRQn = 487,
mbed_official 390:35c2c1cf29cd 515 TINT72_IRQn = 488,
mbed_official 390:35c2c1cf29cd 516 TINT73_IRQn = 489,
mbed_official 390:35c2c1cf29cd 517 TINT74_IRQn = 490,
mbed_official 390:35c2c1cf29cd 518 TINT75_IRQn = 491,
mbed_official 390:35c2c1cf29cd 519 TINT76_IRQn = 492,
mbed_official 390:35c2c1cf29cd 520 TINT77_IRQn = 493,
mbed_official 390:35c2c1cf29cd 521 TINT78_IRQn = 494,
mbed_official 390:35c2c1cf29cd 522 TINT79_IRQn = 495,
mbed_official 390:35c2c1cf29cd 523 TINT80_IRQn = 496,
mbed_official 390:35c2c1cf29cd 524 TINT81_IRQn = 497,
mbed_official 390:35c2c1cf29cd 525 TINT82_IRQn = 498,
mbed_official 390:35c2c1cf29cd 526 TINT83_IRQn = 499,
mbed_official 390:35c2c1cf29cd 527 TINT84_IRQn = 500,
mbed_official 390:35c2c1cf29cd 528 TINT85_IRQn = 501,
mbed_official 390:35c2c1cf29cd 529 TINT86_IRQn = 502,
mbed_official 390:35c2c1cf29cd 530 TINT87_IRQn = 503,
mbed_official 390:35c2c1cf29cd 531 TINT88_IRQn = 504,
mbed_official 390:35c2c1cf29cd 532 TINT89_IRQn = 505,
mbed_official 390:35c2c1cf29cd 533 TINT90_IRQn = 506,
mbed_official 390:35c2c1cf29cd 534 TINT91_IRQn = 507,
mbed_official 390:35c2c1cf29cd 535 TINT92_IRQn = 508,
mbed_official 390:35c2c1cf29cd 536 TINT93_IRQn = 509,
mbed_official 390:35c2c1cf29cd 537 TINT94_IRQn = 510,
mbed_official 390:35c2c1cf29cd 538 TINT95_IRQn = 511,
mbed_official 390:35c2c1cf29cd 539 TINT96_IRQn = 512,
mbed_official 390:35c2c1cf29cd 540 TINT97_IRQn = 513,
mbed_official 390:35c2c1cf29cd 541 TINT98_IRQn = 514,
mbed_official 390:35c2c1cf29cd 542 TINT99_IRQn = 515,
mbed_official 390:35c2c1cf29cd 543 TINT100_IRQn = 516,
mbed_official 390:35c2c1cf29cd 544 TINT101_IRQn = 517,
mbed_official 390:35c2c1cf29cd 545 TINT102_IRQn = 518,
mbed_official 390:35c2c1cf29cd 546 TINT103_IRQn = 519,
mbed_official 390:35c2c1cf29cd 547 TINT104_IRQn = 520,
mbed_official 390:35c2c1cf29cd 548 TINT105_IRQn = 521,
mbed_official 390:35c2c1cf29cd 549 TINT106_IRQn = 522,
mbed_official 390:35c2c1cf29cd 550 TINT107_IRQn = 523,
mbed_official 390:35c2c1cf29cd 551 TINT108_IRQn = 524,
mbed_official 390:35c2c1cf29cd 552 TINT109_IRQn = 525,
mbed_official 390:35c2c1cf29cd 553 TINT110_IRQn = 526,
mbed_official 390:35c2c1cf29cd 554 TINT111_IRQn = 527,
mbed_official 390:35c2c1cf29cd 555 TINT112_IRQn = 528,
mbed_official 390:35c2c1cf29cd 556 TINT113_IRQn = 529,
mbed_official 390:35c2c1cf29cd 557 TINT114_IRQn = 530,
mbed_official 390:35c2c1cf29cd 558 TINT115_IRQn = 531,
mbed_official 390:35c2c1cf29cd 559 TINT116_IRQn = 532,
mbed_official 390:35c2c1cf29cd 560 TINT117_IRQn = 533,
mbed_official 390:35c2c1cf29cd 561 TINT118_IRQn = 534,
mbed_official 390:35c2c1cf29cd 562 TINT119_IRQn = 535,
mbed_official 390:35c2c1cf29cd 563 TINT120_IRQn = 536,
mbed_official 390:35c2c1cf29cd 564 TINT121_IRQn = 537,
mbed_official 390:35c2c1cf29cd 565 TINT122_IRQn = 538,
mbed_official 390:35c2c1cf29cd 566 TINT123_IRQn = 539,
mbed_official 390:35c2c1cf29cd 567 TINT124_IRQn = 540,
mbed_official 390:35c2c1cf29cd 568 TINT125_IRQn = 541,
mbed_official 390:35c2c1cf29cd 569 TINT126_IRQn = 542,
mbed_official 390:35c2c1cf29cd 570 TINT127_IRQn = 543,
mbed_official 390:35c2c1cf29cd 571 TINT128_IRQn = 544,
mbed_official 390:35c2c1cf29cd 572 TINT129_IRQn = 545,
mbed_official 390:35c2c1cf29cd 573 TINT130_IRQn = 546,
mbed_official 390:35c2c1cf29cd 574 TINT131_IRQn = 547,
mbed_official 390:35c2c1cf29cd 575 TINT132_IRQn = 548,
mbed_official 390:35c2c1cf29cd 576 TINT133_IRQn = 549,
mbed_official 390:35c2c1cf29cd 577 TINT134_IRQn = 550,
mbed_official 390:35c2c1cf29cd 578 TINT135_IRQn = 551,
mbed_official 390:35c2c1cf29cd 579 TINT136_IRQn = 552,
mbed_official 390:35c2c1cf29cd 580 TINT137_IRQn = 553,
mbed_official 390:35c2c1cf29cd 581 TINT138_IRQn = 554,
mbed_official 390:35c2c1cf29cd 582 TINT139_IRQn = 555,
mbed_official 390:35c2c1cf29cd 583 TINT140_IRQn = 556,
mbed_official 390:35c2c1cf29cd 584 TINT141_IRQn = 557,
mbed_official 390:35c2c1cf29cd 585 TINT142_IRQn = 558,
mbed_official 390:35c2c1cf29cd 586 TINT143_IRQn = 559,
mbed_official 390:35c2c1cf29cd 587 TINT144_IRQn = 560,
mbed_official 390:35c2c1cf29cd 588 TINT145_IRQn = 561,
mbed_official 390:35c2c1cf29cd 589 TINT146_IRQn = 562,
mbed_official 390:35c2c1cf29cd 590 TINT147_IRQn = 563,
mbed_official 390:35c2c1cf29cd 591 TINT148_IRQn = 564,
mbed_official 390:35c2c1cf29cd 592 TINT149_IRQn = 565,
mbed_official 390:35c2c1cf29cd 593 TINT150_IRQn = 566,
mbed_official 390:35c2c1cf29cd 594 TINT151_IRQn = 567,
mbed_official 390:35c2c1cf29cd 595 TINT152_IRQn = 568,
mbed_official 390:35c2c1cf29cd 596 TINT153_IRQn = 569,
mbed_official 390:35c2c1cf29cd 597 TINT154_IRQn = 570,
mbed_official 390:35c2c1cf29cd 598 TINT155_IRQn = 571,
mbed_official 390:35c2c1cf29cd 599 TINT156_IRQn = 572,
mbed_official 390:35c2c1cf29cd 600 TINT157_IRQn = 573,
mbed_official 390:35c2c1cf29cd 601 TINT158_IRQn = 574,
mbed_official 390:35c2c1cf29cd 602 TINT159_IRQn = 575,
mbed_official 390:35c2c1cf29cd 603 TINT160_IRQn = 576,
mbed_official 390:35c2c1cf29cd 604 TINT161_IRQn = 577,
mbed_official 390:35c2c1cf29cd 605 TINT162_IRQn = 578,
mbed_official 390:35c2c1cf29cd 606 TINT163_IRQn = 579,
mbed_official 390:35c2c1cf29cd 607 TINT164_IRQn = 580,
mbed_official 390:35c2c1cf29cd 608 TINT165_IRQn = 581,
mbed_official 390:35c2c1cf29cd 609 TINT166_IRQn = 582,
mbed_official 390:35c2c1cf29cd 610 TINT167_IRQn = 583,
mbed_official 390:35c2c1cf29cd 611 TINT168_IRQn = 584,
mbed_official 390:35c2c1cf29cd 612 TINT169_IRQn = 585,
mbed_official 390:35c2c1cf29cd 613 TINT170_IRQn = 586
mbed_official 390:35c2c1cf29cd 614
mbed_official 390:35c2c1cf29cd 615 } IRQn_Type;
mbed_official 390:35c2c1cf29cd 616
mbed_official 390:35c2c1cf29cd 617 #define Renesas_RZ_A1_IRQ_MAX TINT170_IRQn
mbed_official 390:35c2c1cf29cd 618
mbed_official 390:35c2c1cf29cd 619 /* -------- Configuration of the Cortex-A9 Processor and Core Peripherals ------- */
mbed_official 390:35c2c1cf29cd 620 #define __CA9_REV 0x0000 /*!< Core revision r0 */
mbed_official 390:35c2c1cf29cd 621
mbed_official 390:35c2c1cf29cd 622 #define __MPU_PRESENT 1 /*!< MPU present or not */
mbed_official 390:35c2c1cf29cd 623
mbed_official 390:35c2c1cf29cd 624 #define __FPU_PRESENT 1 /*!< FPU present or not */
mbed_official 390:35c2c1cf29cd 625
mbed_official 390:35c2c1cf29cd 626 #define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */
mbed_official 390:35c2c1cf29cd 627 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
mbed_official 390:35c2c1cf29cd 628
mbed_official 390:35c2c1cf29cd 629 #include <core_ca9.h>
mbed_official 390:35c2c1cf29cd 630 #include "system_MBRZA1H.h"
mbed_official 390:35c2c1cf29cd 631
mbed_official 390:35c2c1cf29cd 632
mbed_official 390:35c2c1cf29cd 633 /******************************************************************************/
mbed_official 390:35c2c1cf29cd 634 /* Device Specific Peripheral Section */
mbed_official 390:35c2c1cf29cd 635 /******************************************************************************/
mbed_official 390:35c2c1cf29cd 636 /** @addtogroup Renesas_RZ_A1_Peripherals Renesas_RZ_A1 Peripherals
mbed_official 390:35c2c1cf29cd 637 Renesas_RZ_A1 Device Specific Peripheral registers structures
mbed_official 390:35c2c1cf29cd 638 @{
mbed_official 390:35c2c1cf29cd 639 */
mbed_official 390:35c2c1cf29cd 640
mbed_official 390:35c2c1cf29cd 641 #if defined ( __CC_ARM )
mbed_official 390:35c2c1cf29cd 642 #pragma anon_unions
mbed_official 390:35c2c1cf29cd 643 #endif
mbed_official 390:35c2c1cf29cd 644
mbed_official 390:35c2c1cf29cd 645 #include "pl310.h"
mbed_official 390:35c2c1cf29cd 646 #include "gic.h"
mbed_official 500:04797f1feae2 647 #include "nvic_wrapper.h"
mbed_official 500:04797f1feae2 648 #include "cmsis_nvic.h"
mbed_official 390:35c2c1cf29cd 649
mbed_official 390:35c2c1cf29cd 650 #include "ostm_iodefine.h"
mbed_official 390:35c2c1cf29cd 651 #include "gpio_iodefine.h"
mbed_official 390:35c2c1cf29cd 652 #include "cpg_iodefine.h"
mbed_official 390:35c2c1cf29cd 653 #include "l2c_iodefine.h"
mbed_official 390:35c2c1cf29cd 654
mbed_official 390:35c2c1cf29cd 655 #if defined ( __CC_ARM )
mbed_official 390:35c2c1cf29cd 656 #pragma no_anon_unions
mbed_official 390:35c2c1cf29cd 657 #endif
mbed_official 390:35c2c1cf29cd 658
mbed_official 390:35c2c1cf29cd 659 /*@}*/ /* end of group Renesas_RZ_A1_Peripherals */
mbed_official 390:35c2c1cf29cd 660
mbed_official 390:35c2c1cf29cd 661
mbed_official 390:35c2c1cf29cd 662 /******************************************************************************/
mbed_official 390:35c2c1cf29cd 663 /* Peripheral memory map */
mbed_official 390:35c2c1cf29cd 664 /******************************************************************************/
mbed_official 390:35c2c1cf29cd 665 /** @addtogroup Renesas_RZ_A1_MemoryMap Renesas_RZ_A1 Memory Mapping
mbed_official 390:35c2c1cf29cd 666 @{
mbed_official 390:35c2c1cf29cd 667 */
mbed_official 390:35c2c1cf29cd 668
mbed_official 390:35c2c1cf29cd 669 /* R7S72100 CPU board */
mbed_official 390:35c2c1cf29cd 670 #define Renesas_RZ_A1_NORFLASH_BASE0 (0x00000000UL) /*!< (FLASH0 ) Base Address */
mbed_official 390:35c2c1cf29cd 671 #define Renesas_RZ_A1_NORFLASH_BASE1 (0x04000000UL) /*!< (FLASH1 ) Base Address */
mbed_official 390:35c2c1cf29cd 672 #define Renesas_RZ_A1_SDRAM_BASE0 (0x08000000UL) /*!< (SDRAM0 ) Base Address */
mbed_official 390:35c2c1cf29cd 673 #define Renesas_RZ_A1_SDRAM_BASE1 (0x0C000000UL) /*!< (SDRAM1 ) Base Address */
mbed_official 390:35c2c1cf29cd 674 #define Renesas_RZ_A1_USER_AREA0 (0x10000000UL) /*!< (USER0 ) Base Address */
mbed_official 390:35c2c1cf29cd 675 #define Renesas_RZ_A1_USER_AREA1 (0x14000000UL) /*!< (USER1 ) Base Address */
mbed_official 390:35c2c1cf29cd 676 #define Renesas_RZ_A1_SPI_IO0 (0x18000000UL) /*!< (SPI_IO0 ) Base Address */
mbed_official 390:35c2c1cf29cd 677 #define Renesas_RZ_A1_SPI_IO1 (0x1C000000UL) /*!< (SPI_IO1 ) Base Address */
mbed_official 390:35c2c1cf29cd 678 #define Renesas_RZ_A1_ONCHIP_SRAM_BASE (0x20000000UL) /*!< (SRAM_OC ) Base Address */
mbed_official 390:35c2c1cf29cd 679 #define Renesas_RZ_A1_SPI_MIO_BASE (0x3fe00000UL) /*!< (SPI_MIO ) Base Address */
mbed_official 390:35c2c1cf29cd 680 #define Renesas_RZ_A1_BSC_BASE (0x3ff00000UL) /*!< (BSC ) Base Address */
mbed_official 390:35c2c1cf29cd 681 #define Renesas_RZ_A1_PERIPH_BASE0 (0xe8000000UL) /*!< (PERIPH0 ) Base Address */
mbed_official 390:35c2c1cf29cd 682 #define Renesas_RZ_A1_PERIPH_BASE1 (0xfcf00000UL) /*!< (PERIPH1 ) Base Address */
mbed_official 390:35c2c1cf29cd 683 #define Renesas_RZ_A1_GIC_DISTRIBUTOR_BASE (0xe8201000UL) /*!< (GIC DIST ) Base Address */
mbed_official 390:35c2c1cf29cd 684 #define Renesas_RZ_A1_GIC_INTERFACE_BASE (0xe8202000UL) /*!< (GIC CPU IF) Base Address */
mbed_official 390:35c2c1cf29cd 685 #define Renesas_RZ_A1_PL310_BASE (0x3ffff000UL) /*!< (PL310 ) Base Address */
mbed_official 390:35c2c1cf29cd 686 #define Renesas_RZ_A1_ONCHIP_SRAM_NC_BASE (0x60000000UL) /*!< (SRAM_OC ) Base Address */
mbed_official 390:35c2c1cf29cd 687
mbed_official 390:35c2c1cf29cd 688 //Following macros define the descriptors and attributes used to define the Renesas_RZ_A1 MMU flat-map
mbed_official 390:35c2c1cf29cd 689 //Sect_Normal. Outer & inner wb/wa, non-shareable, executable, rw, domain 0.
mbed_official 390:35c2c1cf29cd 690 #define section_normal(descriptor_l1, region) region.rg_t = SECTION; \
mbed_official 390:35c2c1cf29cd 691 region.domain = 0x0; \
mbed_official 390:35c2c1cf29cd 692 region.e_t = ECC_DISABLED; \
mbed_official 390:35c2c1cf29cd 693 region.g_t = GLOBAL; \
mbed_official 390:35c2c1cf29cd 694 region.inner_norm_t = WB_WA; \
mbed_official 390:35c2c1cf29cd 695 region.outer_norm_t = WB_WA; \
mbed_official 390:35c2c1cf29cd 696 region.mem_t = NORMAL; \
mbed_official 390:35c2c1cf29cd 697 region.sec_t = NON_SECURE; \
mbed_official 390:35c2c1cf29cd 698 region.xn_t = EXECUTE; \
mbed_official 390:35c2c1cf29cd 699 region.priv_t = RW; \
mbed_official 390:35c2c1cf29cd 700 region.user_t = RW; \
mbed_official 390:35c2c1cf29cd 701 region.sh_t = NON_SHARED; \
mbed_official 390:35c2c1cf29cd 702 __get_section_descriptor(&descriptor_l1, region);
mbed_official 390:35c2c1cf29cd 703
mbed_official 390:35c2c1cf29cd 704 #define section_normal_nc(descriptor_l1, region) region.rg_t = SECTION; \
mbed_official 390:35c2c1cf29cd 705 region.domain = 0x0; \
mbed_official 390:35c2c1cf29cd 706 region.e_t = ECC_DISABLED; \
mbed_official 390:35c2c1cf29cd 707 region.g_t = GLOBAL; \
mbed_official 390:35c2c1cf29cd 708 region.inner_norm_t = NON_CACHEABLE; \
mbed_official 390:35c2c1cf29cd 709 region.outer_norm_t = NON_CACHEABLE; \
mbed_official 390:35c2c1cf29cd 710 region.mem_t = NORMAL; \
mbed_official 390:35c2c1cf29cd 711 region.sec_t = SECURE; \
mbed_official 390:35c2c1cf29cd 712 region.xn_t = EXECUTE; \
mbed_official 390:35c2c1cf29cd 713 region.priv_t = RW; \
mbed_official 390:35c2c1cf29cd 714 region.user_t = RW; \
mbed_official 390:35c2c1cf29cd 715 region.sh_t = NON_SHARED; \
mbed_official 390:35c2c1cf29cd 716 __get_section_descriptor(&descriptor_l1, region);
mbed_official 390:35c2c1cf29cd 717
mbed_official 390:35c2c1cf29cd 718 //Sect_Normal_Cod. Outer & inner wb/wa, non-shareable, executable, ro, domain 0.
mbed_official 390:35c2c1cf29cd 719 #define section_normal_cod(descriptor_l1, region) region.rg_t = SECTION; \
mbed_official 390:35c2c1cf29cd 720 region.domain = 0x0; \
mbed_official 390:35c2c1cf29cd 721 region.e_t = ECC_DISABLED; \
mbed_official 390:35c2c1cf29cd 722 region.g_t = GLOBAL; \
mbed_official 390:35c2c1cf29cd 723 region.inner_norm_t = WB_WA; \
mbed_official 390:35c2c1cf29cd 724 region.outer_norm_t = WB_WA; \
mbed_official 390:35c2c1cf29cd 725 region.mem_t = NORMAL; \
mbed_official 390:35c2c1cf29cd 726 region.sec_t = NON_SECURE; \
mbed_official 390:35c2c1cf29cd 727 region.xn_t = EXECUTE; \
mbed_official 390:35c2c1cf29cd 728 region.priv_t = READ; \
mbed_official 390:35c2c1cf29cd 729 region.user_t = READ; \
mbed_official 390:35c2c1cf29cd 730 region.sh_t = NON_SHARED; \
mbed_official 390:35c2c1cf29cd 731 __get_section_descriptor(&descriptor_l1, region);
mbed_official 390:35c2c1cf29cd 732
mbed_official 390:35c2c1cf29cd 733 //Sect_Normal_RO. Sect_Normal_Cod, but not executable
mbed_official 390:35c2c1cf29cd 734 #define section_normal_ro(descriptor_l1, region) region.rg_t = SECTION; \
mbed_official 390:35c2c1cf29cd 735 region.domain = 0x0; \
mbed_official 390:35c2c1cf29cd 736 region.e_t = ECC_DISABLED; \
mbed_official 390:35c2c1cf29cd 737 region.g_t = GLOBAL; \
mbed_official 390:35c2c1cf29cd 738 region.inner_norm_t = WB_WA; \
mbed_official 390:35c2c1cf29cd 739 region.outer_norm_t = WB_WA; \
mbed_official 390:35c2c1cf29cd 740 region.mem_t = NORMAL; \
mbed_official 390:35c2c1cf29cd 741 region.sec_t = NON_SECURE; \
mbed_official 390:35c2c1cf29cd 742 region.xn_t = NON_EXECUTE; \
mbed_official 390:35c2c1cf29cd 743 region.priv_t = READ; \
mbed_official 390:35c2c1cf29cd 744 region.user_t = READ; \
mbed_official 390:35c2c1cf29cd 745 region.sh_t = NON_SHARED; \
mbed_official 390:35c2c1cf29cd 746 __get_section_descriptor(&descriptor_l1, region);
mbed_official 390:35c2c1cf29cd 747
mbed_official 390:35c2c1cf29cd 748 //Sect_Normal_RW. Sect_Normal_Cod, but writeable and not executable
mbed_official 390:35c2c1cf29cd 749 #define section_normal_rw(descriptor_l1, region) region.rg_t = SECTION; \
mbed_official 390:35c2c1cf29cd 750 region.domain = 0x0; \
mbed_official 390:35c2c1cf29cd 751 region.e_t = ECC_DISABLED; \
mbed_official 390:35c2c1cf29cd 752 region.g_t = GLOBAL; \
mbed_official 390:35c2c1cf29cd 753 region.inner_norm_t = WB_WA; \
mbed_official 390:35c2c1cf29cd 754 region.outer_norm_t = WB_WA; \
mbed_official 390:35c2c1cf29cd 755 region.mem_t = NORMAL; \
mbed_official 390:35c2c1cf29cd 756 region.sec_t = NON_SECURE; \
mbed_official 390:35c2c1cf29cd 757 region.xn_t = NON_EXECUTE; \
mbed_official 390:35c2c1cf29cd 758 region.priv_t = RW; \
mbed_official 390:35c2c1cf29cd 759 region.user_t = RW; \
mbed_official 390:35c2c1cf29cd 760 region.sh_t = NON_SHARED; \
mbed_official 390:35c2c1cf29cd 761 __get_section_descriptor(&descriptor_l1, region);
mbed_official 390:35c2c1cf29cd 762 //Sect_SO. Strongly-ordered (therefore shareable), not executable, rw, domain 0, base addr 0
mbed_official 390:35c2c1cf29cd 763 #define section_so(descriptor_l1, region) region.rg_t = SECTION; \
mbed_official 390:35c2c1cf29cd 764 region.domain = 0x0; \
mbed_official 390:35c2c1cf29cd 765 region.e_t = ECC_DISABLED; \
mbed_official 390:35c2c1cf29cd 766 region.g_t = GLOBAL; \
mbed_official 390:35c2c1cf29cd 767 region.inner_norm_t = NON_CACHEABLE; \
mbed_official 390:35c2c1cf29cd 768 region.outer_norm_t = NON_CACHEABLE; \
mbed_official 390:35c2c1cf29cd 769 region.mem_t = STRONGLY_ORDERED; \
mbed_official 390:35c2c1cf29cd 770 region.sec_t = SECURE; \
mbed_official 390:35c2c1cf29cd 771 region.xn_t = NON_EXECUTE; \
mbed_official 390:35c2c1cf29cd 772 region.priv_t = RW; \
mbed_official 390:35c2c1cf29cd 773 region.user_t = RW; \
mbed_official 390:35c2c1cf29cd 774 region.sh_t = NON_SHARED; \
mbed_official 390:35c2c1cf29cd 775 __get_section_descriptor(&descriptor_l1, region);
mbed_official 390:35c2c1cf29cd 776
mbed_official 390:35c2c1cf29cd 777 //Sect_Device_RO. Device, non-shareable, non-executable, ro, domain 0, base addr 0
mbed_official 390:35c2c1cf29cd 778 #define section_device_ro(descriptor_l1, region) region.rg_t = SECTION; \
mbed_official 390:35c2c1cf29cd 779 region.domain = 0x0; \
mbed_official 390:35c2c1cf29cd 780 region.e_t = ECC_DISABLED; \
mbed_official 390:35c2c1cf29cd 781 region.g_t = GLOBAL; \
mbed_official 390:35c2c1cf29cd 782 region.inner_norm_t = NON_CACHEABLE; \
mbed_official 390:35c2c1cf29cd 783 region.outer_norm_t = NON_CACHEABLE; \
mbed_official 390:35c2c1cf29cd 784 region.mem_t = STRONGLY_ORDERED; \
mbed_official 390:35c2c1cf29cd 785 region.sec_t = SECURE; \
mbed_official 390:35c2c1cf29cd 786 region.xn_t = NON_EXECUTE; \
mbed_official 390:35c2c1cf29cd 787 region.priv_t = READ; \
mbed_official 390:35c2c1cf29cd 788 region.user_t = READ; \
mbed_official 390:35c2c1cf29cd 789 region.sh_t = NON_SHARED; \
mbed_official 390:35c2c1cf29cd 790 __get_section_descriptor(&descriptor_l1, region);
mbed_official 390:35c2c1cf29cd 791
mbed_official 390:35c2c1cf29cd 792 //Sect_Device_RW. Sect_Device_RO, but writeable
mbed_official 390:35c2c1cf29cd 793 #define section_device_rw(descriptor_l1, region) region.rg_t = SECTION; \
mbed_official 390:35c2c1cf29cd 794 region.domain = 0x0; \
mbed_official 390:35c2c1cf29cd 795 region.e_t = ECC_DISABLED; \
mbed_official 390:35c2c1cf29cd 796 region.g_t = GLOBAL; \
mbed_official 390:35c2c1cf29cd 797 region.inner_norm_t = NON_CACHEABLE; \
mbed_official 390:35c2c1cf29cd 798 region.outer_norm_t = NON_CACHEABLE; \
mbed_official 390:35c2c1cf29cd 799 region.mem_t = STRONGLY_ORDERED; \
mbed_official 390:35c2c1cf29cd 800 region.sec_t = SECURE; \
mbed_official 390:35c2c1cf29cd 801 region.xn_t = NON_EXECUTE; \
mbed_official 390:35c2c1cf29cd 802 region.priv_t = RW; \
mbed_official 390:35c2c1cf29cd 803 region.user_t = RW; \
mbed_official 390:35c2c1cf29cd 804 region.sh_t = NON_SHARED; \
mbed_official 390:35c2c1cf29cd 805 __get_section_descriptor(&descriptor_l1, region);
mbed_official 390:35c2c1cf29cd 806 //Page_4k_Device_RW. Shared device, not executable, rw, domain 0
mbed_official 390:35c2c1cf29cd 807 #define page4k_device_rw(descriptor_l1, descriptor_l2, region) region.rg_t = PAGE_4k; \
mbed_official 390:35c2c1cf29cd 808 region.domain = 0x0; \
mbed_official 390:35c2c1cf29cd 809 region.e_t = ECC_DISABLED; \
mbed_official 390:35c2c1cf29cd 810 region.g_t = GLOBAL; \
mbed_official 390:35c2c1cf29cd 811 region.inner_norm_t = NON_CACHEABLE; \
mbed_official 390:35c2c1cf29cd 812 region.outer_norm_t = NON_CACHEABLE; \
mbed_official 390:35c2c1cf29cd 813 region.mem_t = SHARED_DEVICE; \
mbed_official 390:35c2c1cf29cd 814 region.sec_t = SECURE; \
mbed_official 390:35c2c1cf29cd 815 region.xn_t = NON_EXECUTE; \
mbed_official 390:35c2c1cf29cd 816 region.priv_t = RW; \
mbed_official 390:35c2c1cf29cd 817 region.user_t = RW; \
mbed_official 390:35c2c1cf29cd 818 region.sh_t = NON_SHARED; \
mbed_official 390:35c2c1cf29cd 819 __get_page_descriptor(&descriptor_l1, &descriptor_l2, region);
mbed_official 390:35c2c1cf29cd 820
mbed_official 390:35c2c1cf29cd 821 //Page_64k_Device_RW. Shared device, not executable, rw, domain 0
mbed_official 390:35c2c1cf29cd 822 #define page64k_device_rw(descriptor_l1, descriptor_l2, region) region.rg_t = PAGE_64k; \
mbed_official 390:35c2c1cf29cd 823 region.domain = 0x0; \
mbed_official 390:35c2c1cf29cd 824 region.e_t = ECC_DISABLED; \
mbed_official 390:35c2c1cf29cd 825 region.g_t = GLOBAL; \
mbed_official 390:35c2c1cf29cd 826 region.inner_norm_t = NON_CACHEABLE; \
mbed_official 390:35c2c1cf29cd 827 region.outer_norm_t = NON_CACHEABLE; \
mbed_official 390:35c2c1cf29cd 828 region.mem_t = SHARED_DEVICE; \
mbed_official 390:35c2c1cf29cd 829 region.sec_t = SECURE; \
mbed_official 390:35c2c1cf29cd 830 region.xn_t = NON_EXECUTE; \
mbed_official 390:35c2c1cf29cd 831 region.priv_t = RW; \
mbed_official 390:35c2c1cf29cd 832 region.user_t = RW; \
mbed_official 390:35c2c1cf29cd 833 region.sh_t = NON_SHARED; \
mbed_official 390:35c2c1cf29cd 834 __get_page_descriptor(&descriptor_l1, &descriptor_l2, region);
mbed_official 390:35c2c1cf29cd 835
mbed_official 390:35c2c1cf29cd 836 /*@}*/ /* end of group Renesas_RZ_A1_MemoryMap */
mbed_official 390:35c2c1cf29cd 837
mbed_official 390:35c2c1cf29cd 838 /******************************************************************************/
mbed_official 390:35c2c1cf29cd 839 /* Clock Settings */
mbed_official 390:35c2c1cf29cd 840 /******************************************************************************/
mbed_official 390:35c2c1cf29cd 841 /** @addtogroup Renesas_RZ_A1_H_Clocks Renesas_RZ_A1 Clock definitions
mbed_official 390:35c2c1cf29cd 842 @{
mbed_official 390:35c2c1cf29cd 843 */
mbed_official 390:35c2c1cf29cd 844
mbed_official 390:35c2c1cf29cd 845 /*
mbed_official 390:35c2c1cf29cd 846 * Clock Mode 0 settings
mbed_official 390:35c2c1cf29cd 847 * SW1-4(MD_CLK):ON
mbed_official 390:35c2c1cf29cd 848 * SW1-5(MD_CLKS):ON
mbed_official 390:35c2c1cf29cd 849 * FRQCR=0x1035
mbed_official 390:35c2c1cf29cd 850 * CLKEN2 = 0b - unstable
mbed_official 390:35c2c1cf29cd 851 * CLKEN[1:0]=01b - Output, Low, Low
mbed_official 390:35c2c1cf29cd 852 * IFC[1:0] =00b - CPU clock is 1/1 PLL clock
mbed_official 390:35c2c1cf29cd 853 * FRQCR2=0x0001
mbed_official 390:35c2c1cf29cd 854 * GFC[1:0] =01b - Graphic clock is 2/3 bus clock
mbed_official 390:35c2c1cf29cd 855 */
mbed_official 390:35c2c1cf29cd 856 #define CM0_RENESAS_RZ_A1_CLKIN ( 13333333u)
mbed_official 390:35c2c1cf29cd 857 #define CM0_RENESAS_RZ_A1_CLKO ( 66666666u)
mbed_official 390:35c2c1cf29cd 858 #define CM0_RENESAS_RZ_A1_I_CLK (400000000u)
mbed_official 390:35c2c1cf29cd 859 #define CM0_RENESAS_RZ_A1_G_CLK (266666666u)
mbed_official 390:35c2c1cf29cd 860 #define CM0_RENESAS_RZ_A1_B_CLK (133333333u)
mbed_official 390:35c2c1cf29cd 861 #define CM0_RENESAS_RZ_A1_P1_CLK ( 66666666u)
mbed_official 390:35c2c1cf29cd 862 #define CM0_RENESAS_RZ_A1_P0_CLK ( 33333333u)
mbed_official 390:35c2c1cf29cd 863
mbed_official 390:35c2c1cf29cd 864 /*
mbed_official 390:35c2c1cf29cd 865 * Clock Mode 1 settings
mbed_official 390:35c2c1cf29cd 866 * SW1-4(MD_CLK):OFF
mbed_official 390:35c2c1cf29cd 867 * SW1-5(MD_CLKS):ON
mbed_official 390:35c2c1cf29cd 868 * FRQCR=0x1335
mbed_official 390:35c2c1cf29cd 869 * CLKEN2 = 0b - unstable
mbed_official 390:35c2c1cf29cd 870 * CLKEN[1:0]=01b - Output, Low, Low
mbed_official 390:35c2c1cf29cd 871 * IFC[1:0] =11b - CPU clock is 1/3 PLL clock
mbed_official 390:35c2c1cf29cd 872 * FRQCR2=0x0003
mbed_official 390:35c2c1cf29cd 873 * GFC[1:0] =11b - graphic clock is 1/3 bus clock
mbed_official 390:35c2c1cf29cd 874 */
mbed_official 390:35c2c1cf29cd 875 #define CM1_RENESAS_RZ_A1_CLKIN ( 48000000u)
mbed_official 390:35c2c1cf29cd 876 #define CM1_RENESAS_RZ_A1_CLKO ( 64000000u)
mbed_official 390:35c2c1cf29cd 877 #define CM1_RENESAS_RZ_A1_I_CLK (128000000u)
mbed_official 390:35c2c1cf29cd 878 #define CM1_RENESAS_RZ_A1_G_CLK (128000000u)
mbed_official 390:35c2c1cf29cd 879 #define CM1_RENESAS_RZ_A1_B_CLK (128000000u)
mbed_official 390:35c2c1cf29cd 880 #define CM1_RENESAS_RZ_A1_P1_CLK ( 64000000u)
mbed_official 390:35c2c1cf29cd 881 #define CM1_RENESAS_RZ_A1_P0_CLK ( 32000000u)
mbed_official 390:35c2c1cf29cd 882
mbed_official 390:35c2c1cf29cd 883 /*@}*/ /* end of group Renesas_RZ_A1_Clocks */
mbed_official 390:35c2c1cf29cd 884
mbed_official 390:35c2c1cf29cd 885 /******************************************************************************/
mbed_official 390:35c2c1cf29cd 886 /* CPG Settings */
mbed_official 390:35c2c1cf29cd 887 /******************************************************************************/
mbed_official 390:35c2c1cf29cd 888 /** @addtogroup Renesas_RZ_A1_H_CPG Renesas_RZ_A1 CPG Bit definitions
mbed_official 390:35c2c1cf29cd 889 @{
mbed_official 390:35c2c1cf29cd 890 */
mbed_official 390:35c2c1cf29cd 891
mbed_official 390:35c2c1cf29cd 892 #define CPG_FRQCR_SHIFT_CKOEN2 (14)
mbed_official 390:35c2c1cf29cd 893 #define CPG_FRQCR_BIT_CKOEN2 (0x1 << CPG_FRQCR_SHIFT_CKOEN2)
mbed_official 390:35c2c1cf29cd 894 #define CPG_FRQCR_SHIFT_CKOEN0 (12)
mbed_official 390:35c2c1cf29cd 895 #define CPG_FRQCR_BITS_CKOEN0 (0x3 << CPG_FRQCR_SHIFT_CKOEN0)
mbed_official 390:35c2c1cf29cd 896 #define CPG_FRQCR_SHIFT_IFC (8)
mbed_official 390:35c2c1cf29cd 897 #define CPG_FRQCR_BITS_IFC (0x3 << CPG_FRQCR_SHIFT_IFC)
mbed_official 390:35c2c1cf29cd 898
mbed_official 390:35c2c1cf29cd 899 #define CPG_FRQCR2_SHIFT_GFC (0)
mbed_official 390:35c2c1cf29cd 900 #define CPG_FRQCR2_BITS_GFC (0x3 << CPG_FRQCR2_SHIFT_GFC)
mbed_official 390:35c2c1cf29cd 901
mbed_official 390:35c2c1cf29cd 902
mbed_official 390:35c2c1cf29cd 903 #define CPG_STBCR1_BIT_STBY (0x80u)
mbed_official 390:35c2c1cf29cd 904 #define CPG_STBCR1_BIT_DEEP (0x40u)
mbed_official 390:35c2c1cf29cd 905 #define CPG_STBCR2_BIT_HIZ (0x80u)
mbed_official 390:35c2c1cf29cd 906 #define CPG_STBCR2_BIT_MSTP20 (0x01u) /* CoreSight */
mbed_official 390:35c2c1cf29cd 907 #define CPG_STBCR3_BIT_MSTP37 (0x80u) /* IEBus */
mbed_official 390:35c2c1cf29cd 908 #define CPG_STBCR3_BIT_MSTP36 (0x40u) /* IrDA */
mbed_official 390:35c2c1cf29cd 909 #define CPG_STBCR3_BIT_MSTP35 (0x20u) /* LIN0 */
mbed_official 390:35c2c1cf29cd 910 #define CPG_STBCR3_BIT_MSTP34 (0x10u) /* LIN1 */
mbed_official 390:35c2c1cf29cd 911 #define CPG_STBCR3_BIT_MSTP33 (0x08u) /* Multi-Function Timer */
mbed_official 390:35c2c1cf29cd 912 #define CPG_STBCR3_BIT_MSTP32 (0x04u) /* CAN */
mbed_official 390:35c2c1cf29cd 913 #define CPG_STBCR3_BIT_MSTP30 (0x01u) /* Motor Control PWM Timer */
mbed_official 390:35c2c1cf29cd 914 #define CPG_STBCR4_BIT_MSTP47 (0x80u) /* SCIF0 */
mbed_official 390:35c2c1cf29cd 915 #define CPG_STBCR4_BIT_MSTP46 (0x40u) /* SCIF1 */
mbed_official 390:35c2c1cf29cd 916 #define CPG_STBCR4_BIT_MSTP45 (0x20u) /* SCIF2 */
mbed_official 390:35c2c1cf29cd 917 #define CPG_STBCR4_BIT_MSTP44 (0x10u) /* SCIF3 */
mbed_official 390:35c2c1cf29cd 918 #define CPG_STBCR4_BIT_MSTP43 (0x08u) /* SCIF4 */
mbed_official 390:35c2c1cf29cd 919 #define CPG_STBCR4_BIT_MSTP42 (0x04u) /* SCIF5 */
mbed_official 390:35c2c1cf29cd 920 #define CPG_STBCR4_BIT_MSTP41 (0x02u) /* SCIF6 */
mbed_official 390:35c2c1cf29cd 921 #define CPG_STBCR4_BIT_MSTP40 (0x01u) /* SCIF7 */
mbed_official 390:35c2c1cf29cd 922 #define CPG_STBCR5_BIT_MSTP57 (0x80u) /* SCI0 */
mbed_official 390:35c2c1cf29cd 923 #define CPG_STBCR5_BIT_MSTP56 (0x40u) /* SCI1 */
mbed_official 390:35c2c1cf29cd 924 #define CPG_STBCR5_BIT_MSTP55 (0x20u) /* Sound Generator0 */
mbed_official 390:35c2c1cf29cd 925 #define CPG_STBCR5_BIT_MSTP54 (0x10u) /* Sound Generator1 */
mbed_official 390:35c2c1cf29cd 926 #define CPG_STBCR5_BIT_MSTP53 (0x08u) /* Sound Generator2 */
mbed_official 390:35c2c1cf29cd 927 #define CPG_STBCR5_BIT_MSTP52 (0x04u) /* Sound Generator3 */
mbed_official 390:35c2c1cf29cd 928 #define CPG_STBCR5_BIT_MSTP51 (0x02u) /* OSTM0 */
mbed_official 390:35c2c1cf29cd 929 #define CPG_STBCR5_BIT_MSTP50 (0x01u) /* OSTM1 */
mbed_official 390:35c2c1cf29cd 930 #define CPG_STBCR6_BIT_MSTP67 (0x80u) /* General A/D Comvertor */
mbed_official 390:35c2c1cf29cd 931 #define CPG_STBCR6_BIT_MSTP66 (0x40u) /* Capture Engine */
mbed_official 390:35c2c1cf29cd 932 #define CPG_STBCR6_BIT_MSTP65 (0x20u) /* Display out comparison0 */
mbed_official 390:35c2c1cf29cd 933 #define CPG_STBCR6_BIT_MSTP64 (0x10u) /* Display out comparison1 */
mbed_official 390:35c2c1cf29cd 934 #define CPG_STBCR6_BIT_MSTP63 (0x08u) /* Dynamic Range Compalator0 */
mbed_official 390:35c2c1cf29cd 935 #define CPG_STBCR6_BIT_MSTP62 (0x04u) /* Dynamic Range Compalator1 */
mbed_official 390:35c2c1cf29cd 936 #define CPG_STBCR6_BIT_MSTP61 (0x02u) /* JPEG Decoder */
mbed_official 390:35c2c1cf29cd 937 #define CPG_STBCR6_BIT_MSTP60 (0x01u) /* Realtime Clock */
mbed_official 390:35c2c1cf29cd 938 #define CPG_STBCR7_BIT_MSTP77 (0x80u) /* Video Decoder0 */
mbed_official 390:35c2c1cf29cd 939 #define CPG_STBCR7_BIT_MSTP76 (0x40u) /* Video Decoder1 */
mbed_official 390:35c2c1cf29cd 940 #define CPG_STBCR7_BIT_MSTP74 (0x10u) /* Ether */
mbed_official 390:35c2c1cf29cd 941 #define CPG_STBCR7_BIT_MSTP73 (0x04u) /* NAND Flash Memory Controller */
mbed_official 390:35c2c1cf29cd 942 #define CPG_STBCR7_BIT_MSTP71 (0x02u) /* USB0 */
mbed_official 390:35c2c1cf29cd 943 #define CPG_STBCR7_BIT_MSTP70 (0x01u) /* USB1 */
mbed_official 390:35c2c1cf29cd 944 #define CPG_STBCR8_BIT_MSTP87 (0x80u) /* IMR-LS2_0 */
mbed_official 390:35c2c1cf29cd 945 #define CPG_STBCR8_BIT_MSTP86 (0x40u) /* IMR-LS2_1 */
mbed_official 390:35c2c1cf29cd 946 #define CPG_STBCR8_BIT_MSTP85 (0x20u) /* IMR-LSD */
mbed_official 390:35c2c1cf29cd 947 #define CPG_STBCR8_BIT_MSTP84 (0x10u) /* MMC Host Interface */
mbed_official 390:35c2c1cf29cd 948 #define CPG_STBCR8_BIT_MSTP83 (0x08u) /* MediaLB */
mbed_official 390:35c2c1cf29cd 949 #define CPG_STBCR8_BIT_MSTP81 (0x02u) /* SCUX */
mbed_official 390:35c2c1cf29cd 950 #define CPG_STBCR9_BIT_MSTP97 (0x80u) /* RIIC0 */
mbed_official 390:35c2c1cf29cd 951 #define CPG_STBCR9_BIT_MSTP96 (0x40u) /* RIIC1 */
mbed_official 390:35c2c1cf29cd 952 #define CPG_STBCR9_BIT_MSTP95 (0x20u) /* RIIC2 */
mbed_official 390:35c2c1cf29cd 953 #define CPG_STBCR9_BIT_MSTP94 (0x10u) /* RIIC3 */
mbed_official 390:35c2c1cf29cd 954 #define CPG_STBCR9_BIT_MSTP93 (0x08u) /* SPI Multi I/O Bus Controller0 */
mbed_official 390:35c2c1cf29cd 955 #define CPG_STBCR9_BIT_MSTP92 (0x04u) /* SPI Multi I/O Bus Controller1 */
mbed_official 390:35c2c1cf29cd 956 #define CPG_STBCR9_BIT_MSTP91 (0x02u) /* VDC5_0 */
mbed_official 390:35c2c1cf29cd 957 #define CPG_STBCR9_BIT_MSTP90 (0x01u) /* VDC5_1 */
mbed_official 390:35c2c1cf29cd 958 #define CPG_STBCR10_BIT_MSTP107 (0x80u) /* RSPI0 */
mbed_official 390:35c2c1cf29cd 959 #define CPG_STBCR10_BIT_MSTP106 (0x40u) /* RSPI1 */
mbed_official 390:35c2c1cf29cd 960 #define CPG_STBCR10_BIT_MSTP105 (0x20u) /* RSPI2 */
mbed_official 390:35c2c1cf29cd 961 #define CPG_STBCR10_BIT_MSTP104 (0x10u) /* RSPI3 */
mbed_official 390:35c2c1cf29cd 962 #define CPG_STBCR10_BIT_MSTP103 (0x08u) /* RSPI4 */
mbed_official 390:35c2c1cf29cd 963 #define CPG_STBCR10_BIT_MSTP102 (0x04u) /* ROMDEC */
mbed_official 390:35c2c1cf29cd 964 #define CPG_STBCR10_BIT_MSTP101 (0x02u) /* SPIDF */
mbed_official 390:35c2c1cf29cd 965 #define CPG_STBCR10_BIT_MSTP100 (0x01u) /* OpenVG */
mbed_official 390:35c2c1cf29cd 966 #define CPG_STBCR11_BIT_MSTP115 (0x20u) /* SSIF0 */
mbed_official 390:35c2c1cf29cd 967 #define CPG_STBCR11_BIT_MSTP114 (0x10u) /* SSIF1 */
mbed_official 390:35c2c1cf29cd 968 #define CPG_STBCR11_BIT_MSTP113 (0x08u) /* SSIF2 */
mbed_official 390:35c2c1cf29cd 969 #define CPG_STBCR11_BIT_MSTP112 (0x04u) /* SSIF3 */
mbed_official 390:35c2c1cf29cd 970 #define CPG_STBCR11_BIT_MSTP111 (0x02u) /* SSIF4 */
mbed_official 390:35c2c1cf29cd 971 #define CPG_STBCR11_BIT_MSTP110 (0x01u) /* SSIF5 */
mbed_official 390:35c2c1cf29cd 972 #define CPG_STBCR12_BIT_MSTP123 (0x08u) /* SD Host Interface00 */
mbed_official 390:35c2c1cf29cd 973 #define CPG_STBCR12_BIT_MSTP122 (0x04u) /* SD Host Interface01 */
mbed_official 390:35c2c1cf29cd 974 #define CPG_STBCR12_BIT_MSTP121 (0x02u) /* SD Host Interface10 */
mbed_official 390:35c2c1cf29cd 975 #define CPG_STBCR12_BIT_MSTP120 (0x01u) /* SD Host Interface11 */
mbed_official 390:35c2c1cf29cd 976 #define CPG_CSTBCR1_BIT_CMSTP11 (0x02u) /* PFV */
mbed_official 390:35c2c1cf29cd 977 #define CPG_SWRSTCR1_BIT_AXTALE (0x80u) /* AUDIO_X1 */
mbed_official 390:35c2c1cf29cd 978 #define CPG_SWRSTCR1_BIT_SRST16 (0x40u) /* SSIF0 */
mbed_official 390:35c2c1cf29cd 979 #define CPG_SWRSTCR1_BIT_SRST15 (0x20u) /* SSIF1 */
mbed_official 390:35c2c1cf29cd 980 #define CPG_SWRSTCR1_BIT_SRST14 (0x10u) /* SSIF2 */
mbed_official 390:35c2c1cf29cd 981 #define CPG_SWRSTCR1_BIT_SRST13 (0x08u) /* SSIF3 */
mbed_official 390:35c2c1cf29cd 982 #define CPG_SWRSTCR1_BIT_SRST12 (0x04u) /* SSIF4 */
mbed_official 390:35c2c1cf29cd 983 #define CPG_SWRSTCR1_BIT_SRST11 (0x02u) /* SSIF5 */
mbed_official 390:35c2c1cf29cd 984 #define CPG_SWRSTCR2_BIT_SRST27 (0x80u) /* Display out comparison0 */
mbed_official 390:35c2c1cf29cd 985 #define CPG_SWRSTCR2_BIT_SRST26 (0x40u) /* Display out comparison1 */
mbed_official 390:35c2c1cf29cd 986 #define CPG_SWRSTCR2_BIT_SRST25 (0x20u) /* Dynamic Range Compalator0 */
mbed_official 390:35c2c1cf29cd 987 #define CPG_SWRSTCR2_BIT_SRST24 (0x10u) /* Dynamic Range Compalator1 */
mbed_official 390:35c2c1cf29cd 988 #define CPG_SWRSTCR2_BIT_SRST23 (0x08u) /* VDC5_0 */
mbed_official 390:35c2c1cf29cd 989 #define CPG_SWRSTCR2_BIT_SRST22 (0x04u) /* VDC5_1 */
mbed_official 390:35c2c1cf29cd 990 #define CPG_SWRSTCR2_BIT_SRST21 (0x02u) /* JPEG Decoder */
mbed_official 390:35c2c1cf29cd 991 #define CPG_SWRSTCR3_BIT_SRST36 (0x40u) /* DMA */
mbed_official 390:35c2c1cf29cd 992 #define CPG_SWRSTCR3_BIT_SRST35 (0x20u) /* IMR-LS2_0 */
mbed_official 390:35c2c1cf29cd 993 #define CPG_SWRSTCR3_BIT_SRST34 (0x10u) /* IMR-LS2_1 */
mbed_official 390:35c2c1cf29cd 994 #define CPG_SWRSTCR3_BIT_SRST33 (0x08u) /* IMR-LSD? */
mbed_official 390:35c2c1cf29cd 995 #define CPG_SWRSTCR3_BIT_SRST32 (0x04u) /* OpenVG */
mbed_official 390:35c2c1cf29cd 996 #define CPG_SWRSTCR3_BIT_SRST31 (0x02u) /* Capture Engine */
mbed_official 390:35c2c1cf29cd 997 #define CPG_SWRSTCR4_BIT_SRST41 (0x02u) /* Video Decoder0 */
mbed_official 390:35c2c1cf29cd 998 #define CPG_SWRSTCR4_BIT_SRST40 (0x01u) /* Video Decoder1 */
mbed_official 390:35c2c1cf29cd 999 #define CPG_SYSCR1_BIT_VRAME4 (0x10u) /* VRAM E Page4 */
mbed_official 390:35c2c1cf29cd 1000 #define CPG_SYSCR1_BIT_VRAME3 (0x08u) /* VRAM E Page3 */
mbed_official 390:35c2c1cf29cd 1001 #define CPG_SYSCR1_BIT_VRAME2 (0x04u) /* VRAM E Page2 */
mbed_official 390:35c2c1cf29cd 1002 #define CPG_SYSCR1_BIT_VRAME1 (0x02u) /* VRAM E Page1 */
mbed_official 390:35c2c1cf29cd 1003 #define CPG_SYSCR1_BIT_VRAME0 (0x01u) /* VRAM E Page0 */
mbed_official 390:35c2c1cf29cd 1004 #define CPG_SYSCR2_BIT_VRAMWE4 (0x10u) /* VRAM WE Page4 */
mbed_official 390:35c2c1cf29cd 1005 #define CPG_SYSCR2_BIT_VRAMWE3 (0x08u) /* VRAM WE Page3 */
mbed_official 390:35c2c1cf29cd 1006 #define CPG_SYSCR2_BIT_VRAMWE2 (0x04u) /* VRAM WE Page2 */
mbed_official 390:35c2c1cf29cd 1007 #define CPG_SYSCR2_BIT_VRAMWE1 (0x02u) /* VRAM WE Page1 */
mbed_official 390:35c2c1cf29cd 1008 #define CPG_SYSCR2_BIT_VRAMWE0 (0x01u) /* VRAM WE Page0 */
mbed_official 390:35c2c1cf29cd 1009 #define CPG_SYSCR3_BIT_RRAMWE3 (0x08u) /* RRAM WE Page3 */
mbed_official 390:35c2c1cf29cd 1010 #define CPG_SYSCR3_BIT_RRAMWE2 (0x04u) /* RRAM WE Page2 */
mbed_official 390:35c2c1cf29cd 1011 #define CPG_SYSCR3_BIT_RRAMWE1 (0x02u) /* RRAM WE Page1 */
mbed_official 390:35c2c1cf29cd 1012 #define CPG_SYSCR3_BIT_RRAMWE0 (0x01u) /* RRAM WE Page0 */
mbed_official 390:35c2c1cf29cd 1013
mbed_official 390:35c2c1cf29cd 1014 /*@}*/ /* end of group Renesas_RZ_A1_CPG */
mbed_official 390:35c2c1cf29cd 1015
mbed_official 390:35c2c1cf29cd 1016 /******************************************************************************/
mbed_official 390:35c2c1cf29cd 1017 /* GPIO Settings */
mbed_official 390:35c2c1cf29cd 1018 /******************************************************************************/
mbed_official 390:35c2c1cf29cd 1019 /** @addtogroup Renesas_RZ_A1_H_GPIO Renesas_RZ_A1 GPIO Bit definitions
mbed_official 390:35c2c1cf29cd 1020 @{
mbed_official 390:35c2c1cf29cd 1021 */
mbed_official 390:35c2c1cf29cd 1022
mbed_official 390:35c2c1cf29cd 1023 #define GPIO_BIT_N0 (1u << 0)
mbed_official 390:35c2c1cf29cd 1024 #define GPIO_BIT_N1 (1u << 1)
mbed_official 390:35c2c1cf29cd 1025 #define GPIO_BIT_N2 (1u << 2)
mbed_official 390:35c2c1cf29cd 1026 #define GPIO_BIT_N3 (1u << 3)
mbed_official 390:35c2c1cf29cd 1027 #define GPIO_BIT_N4 (1u << 4)
mbed_official 390:35c2c1cf29cd 1028 #define GPIO_BIT_N5 (1u << 5)
mbed_official 390:35c2c1cf29cd 1029 #define GPIO_BIT_N6 (1u << 6)
mbed_official 390:35c2c1cf29cd 1030 #define GPIO_BIT_N7 (1u << 7)
mbed_official 390:35c2c1cf29cd 1031 #define GPIO_BIT_N8 (1u << 8)
mbed_official 390:35c2c1cf29cd 1032 #define GPIO_BIT_N9 (1u << 9)
mbed_official 390:35c2c1cf29cd 1033 #define GPIO_BIT_N10 (1u << 10)
mbed_official 390:35c2c1cf29cd 1034 #define GPIO_BIT_N11 (1u << 11)
mbed_official 390:35c2c1cf29cd 1035 #define GPIO_BIT_N12 (1u << 12)
mbed_official 390:35c2c1cf29cd 1036 #define GPIO_BIT_N13 (1u << 13)
mbed_official 390:35c2c1cf29cd 1037 #define GPIO_BIT_N14 (1u << 14)
mbed_official 390:35c2c1cf29cd 1038 #define GPIO_BIT_N15 (1u << 15)
mbed_official 390:35c2c1cf29cd 1039
mbed_official 390:35c2c1cf29cd 1040
mbed_official 390:35c2c1cf29cd 1041 #define MD_BOOT10_MASK (0x3)
mbed_official 390:35c2c1cf29cd 1042
mbed_official 390:35c2c1cf29cd 1043 #define MD_BOOT10_BM0 (0x0)
mbed_official 390:35c2c1cf29cd 1044 #define MD_BOOT10_BM1 (0x2)
mbed_official 390:35c2c1cf29cd 1045 #define MD_BOOT10_BM3 (0x1)
mbed_official 390:35c2c1cf29cd 1046 #define MD_BOOT10_BM4_5 (0x3)
mbed_official 390:35c2c1cf29cd 1047
mbed_official 390:35c2c1cf29cd 1048 #define MD_CLK (1u << 2)
mbed_official 390:35c2c1cf29cd 1049 #define MD_CLKS (1u << 3)
mbed_official 390:35c2c1cf29cd 1050
mbed_official 390:35c2c1cf29cd 1051 /*@}*/ /* end of group Renesas_RZ_A1_GPIO */
mbed_official 390:35c2c1cf29cd 1052
mbed_official 390:35c2c1cf29cd 1053 #ifdef __cplusplus
mbed_official 390:35c2c1cf29cd 1054 }
mbed_official 390:35c2c1cf29cd 1055 #endif
mbed_official 390:35c2c1cf29cd 1056
mbed_official 390:35c2c1cf29cd 1057 #endif // __MBRZA1H_H__