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Last commit 20 Feb 2019 by mbed official

targets/cmsis/TARGET_Freescale/TARGET_MCU_K64F/system_MK64F12.c@579:53297373a894, 2015-07-01 (annotated)

Committer:
mbed_official
Date:
Wed Jul 01 09:45:11 2015 +0100
Revision:
579:53297373a894
Parent:
324:406fd2029f23 
Synchronized with git revision d5b4d2ab9c47edb4dc5776e7177b0c2263459081



Full URL: https://github.com/mbedmicro/mbed/commit/d5b4d2ab9c47edb4dc5776e7177b0c2263459081/



Initial version of drivers for SAMR21

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 146:f64d43ff0c18 1 /*
mbed_official 146:f64d43ff0c18 2 ** ###################################################################
mbed_official 146:f64d43ff0c18 3 ** Processor: MK64FN1M0VMD12
mbed_official 324:406fd2029f23 4 ** Compilers: Keil ARM C/C++ Compiler
mbed_official 146:f64d43ff0c18 5 ** Freescale C/C++ for Embedded ARM
mbed_official 146:f64d43ff0c18 6 ** GNU C Compiler
mbed_official 146:f64d43ff0c18 7 ** GNU C Compiler - CodeSourcery Sourcery G++
mbed_official 146:f64d43ff0c18 8 ** IAR ANSI C/C++ Compiler for ARM
mbed_official 146:f64d43ff0c18 9 **
mbed_official 324:406fd2029f23 10 ** Reference manual: K64P144M120SF5RM, Rev.2, January 2014
mbed_official 324:406fd2029f23 11 ** Version: rev. 2.5, 2014-02-10
mbed_official 324:406fd2029f23 12 ** Build: b140611
mbed_official 146:f64d43ff0c18 13 **
mbed_official 146:f64d43ff0c18 14 ** Abstract:
mbed_official 146:f64d43ff0c18 15 ** Provides a system configuration function and a global variable that
mbed_official 146:f64d43ff0c18 16 ** contains the system frequency. It configures the device and initializes
mbed_official 146:f64d43ff0c18 17 ** the oscillator (PLL) that is part of the microcontroller device.
mbed_official 146:f64d43ff0c18 18 **
mbed_official 324:406fd2029f23 19 ** Copyright (c) 2014 Freescale Semiconductor, Inc.
mbed_official 324:406fd2029f23 20 ** All rights reserved.
mbed_official 324:406fd2029f23 21 **
mbed_official 324:406fd2029f23 22 ** Redistribution and use in source and binary forms, with or without modification,
mbed_official 324:406fd2029f23 23 ** are permitted provided that the following conditions are met:
mbed_official 324:406fd2029f23 24 **
mbed_official 324:406fd2029f23 25 ** o Redistributions of source code must retain the above copyright notice, this list
mbed_official 324:406fd2029f23 26 ** of conditions and the following disclaimer.
mbed_official 324:406fd2029f23 27 **
mbed_official 324:406fd2029f23 28 ** o Redistributions in binary form must reproduce the above copyright notice, this
mbed_official 324:406fd2029f23 29 ** list of conditions and the following disclaimer in the documentation and/or
mbed_official 324:406fd2029f23 30 ** other materials provided with the distribution.
mbed_official 324:406fd2029f23 31 **
mbed_official 324:406fd2029f23 32 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
mbed_official 324:406fd2029f23 33 ** contributors may be used to endorse or promote products derived from this
mbed_official 324:406fd2029f23 34 ** software without specific prior written permission.
mbed_official 324:406fd2029f23 35 **
mbed_official 324:406fd2029f23 36 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
mbed_official 324:406fd2029f23 37 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
mbed_official 324:406fd2029f23 38 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 324:406fd2029f23 39 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
mbed_official 324:406fd2029f23 40 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
mbed_official 324:406fd2029f23 41 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
mbed_official 324:406fd2029f23 42 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
mbed_official 324:406fd2029f23 43 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
mbed_official 324:406fd2029f23 44 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
mbed_official 324:406fd2029f23 45 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 146:f64d43ff0c18 46 **
mbed_official 146:f64d43ff0c18 47 ** http: www.freescale.com
mbed_official 146:f64d43ff0c18 48 ** mail: support@freescale.com
mbed_official 146:f64d43ff0c18 49 **
mbed_official 146:f64d43ff0c18 50 ** Revisions:
mbed_official 146:f64d43ff0c18 51 ** - rev. 1.0 (2013-08-12)
mbed_official 146:f64d43ff0c18 52 ** Initial version.
mbed_official 146:f64d43ff0c18 53 ** - rev. 2.0 (2013-10-29)
mbed_official 146:f64d43ff0c18 54 ** Register accessor macros added to the memory map.
mbed_official 146:f64d43ff0c18 55 ** Symbols for Processor Expert memory map compatibility added to the memory map.
mbed_official 146:f64d43ff0c18 56 ** Startup file for gcc has been updated according to CMSIS 3.2.
mbed_official 146:f64d43ff0c18 57 ** System initialization updated.
mbed_official 146:f64d43ff0c18 58 ** MCG - registers updated.
mbed_official 146:f64d43ff0c18 59 ** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
mbed_official 324:406fd2029f23 60 ** - rev. 2.1 (2013-10-30)
mbed_official 146:f64d43ff0c18 61 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
mbed_official 324:406fd2029f23 62 ** - rev. 2.2 (2013-12-09)
mbed_official 324:406fd2029f23 63 ** DMA - EARS register removed.
mbed_official 324:406fd2029f23 64 ** AIPS0, AIPS1 - MPRA register updated.
mbed_official 324:406fd2029f23 65 ** - rev. 2.3 (2014-01-24)
mbed_official 324:406fd2029f23 66 ** Update according to reference manual rev. 2
mbed_official 324:406fd2029f23 67 ** ENET, MCG, MCM, SIM, USB - registers updated
mbed_official 324:406fd2029f23 68 ** - rev. 2.4 (2014-02-10)
mbed_official 324:406fd2029f23 69 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
mbed_official 324:406fd2029f23 70 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
mbed_official 324:406fd2029f23 71 ** - rev. 2.5 (2014-02-10)
mbed_official 324:406fd2029f23 72 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
mbed_official 324:406fd2029f23 73 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
mbed_official 324:406fd2029f23 74 ** Module access macro module_BASES replaced by module_BASE_PTRS.
mbed_official 146:f64d43ff0c18 75 **
mbed_official 146:f64d43ff0c18 76 ** ###################################################################
mbed_official 146:f64d43ff0c18 77 */
mbed_official 146:f64d43ff0c18 78
mbed_official 146:f64d43ff0c18 79 /*!
mbed_official 146:f64d43ff0c18 80 * @file MK64F12
mbed_official 324:406fd2029f23 81 * @version 2.5
mbed_official 324:406fd2029f23 82 * @date 2014-02-10
mbed_official 146:f64d43ff0c18 83 * @brief Device specific configuration file for MK64F12 (implementation file)
mbed_official 146:f64d43ff0c18 84 *
mbed_official 146:f64d43ff0c18 85 * Provides a system configuration function and a global variable that contains
mbed_official 146:f64d43ff0c18 86 * the system frequency. It configures the device and initializes the oscillator
mbed_official 146:f64d43ff0c18 87 * (PLL) that is part of the microcontroller device.
mbed_official 146:f64d43ff0c18 88 */
mbed_official 146:f64d43ff0c18 89
mbed_official 146:f64d43ff0c18 90 #include <stdint.h>
mbed_official 324:406fd2029f23 91 #include "cmsis.h"
mbed_official 146:f64d43ff0c18 92
mbed_official 146:f64d43ff0c18 93
mbed_official 146:f64d43ff0c18 94
mbed_official 146:f64d43ff0c18 95 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 96 -- Core clock
mbed_official 146:f64d43ff0c18 97 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 98
mbed_official 146:f64d43ff0c18 99 uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
mbed_official 146:f64d43ff0c18 100
mbed_official 146:f64d43ff0c18 101 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 102 -- SystemInit()
mbed_official 146:f64d43ff0c18 103 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 104
mbed_official 146:f64d43ff0c18 105 void SystemInit (void) {
mbed_official 146:f64d43ff0c18 106 #if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
mbed_official 146:f64d43ff0c18 107 SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access */
mbed_official 146:f64d43ff0c18 108 #endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
mbed_official 146:f64d43ff0c18 109 #if (DISABLE_WDOG)
mbed_official 146:f64d43ff0c18 110 /* WDOG->UNLOCK: WDOGUNLOCK=0xC520 */
mbed_official 146:f64d43ff0c18 111 WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xC520); /* Key 1 */
mbed_official 146:f64d43ff0c18 112 /* WDOG->UNLOCK: WDOGUNLOCK=0xD928 */
mbed_official 146:f64d43ff0c18 113 WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xD928); /* Key 2 */
mbed_official 146:f64d43ff0c18 114 /* WDOG->STCTRLH: ?=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,?=0,?=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */
mbed_official 146:f64d43ff0c18 115 WDOG->STCTRLH = WDOG_STCTRLH_BYTESEL(0x00) |
mbed_official 146:f64d43ff0c18 116 WDOG_STCTRLH_WAITEN_MASK |
mbed_official 146:f64d43ff0c18 117 WDOG_STCTRLH_STOPEN_MASK |
mbed_official 146:f64d43ff0c18 118 WDOG_STCTRLH_ALLOWUPDATE_MASK |
mbed_official 146:f64d43ff0c18 119 WDOG_STCTRLH_CLKSRC_MASK |
mbed_official 146:f64d43ff0c18 120 0x0100U;
mbed_official 146:f64d43ff0c18 121 #endif /* (DISABLE_WDOG) */
mbed_official 324:406fd2029f23 122 if((RCM->SRS0 & RCM_SRS0_WAKEUP_MASK) != 0x00U)
mbed_official 146:f64d43ff0c18 123 {
mbed_official 324:406fd2029f23 124 if((PMC->REGSC & PMC_REGSC_ACKISO_MASK) != 0x00U)
mbed_official 324:406fd2029f23 125 {
mbed_official 324:406fd2029f23 126 PMC->REGSC |= PMC_REGSC_ACKISO_MASK; /* Release hold with ACKISO: Only has an effect if recovering from VLLSx.*/
mbed_official 324:406fd2029f23 127 }
mbed_official 324:406fd2029f23 128 } else {
mbed_official 324:406fd2029f23 129 #ifdef SYSTEM_RTC_CR_VALUE
mbed_official 324:406fd2029f23 130 SIM_SCGC6 |= SIM_SCGC6_RTC_MASK;
mbed_official 324:406fd2029f23 131 if ((RTC_CR & RTC_CR_OSCE_MASK) == 0x00U) { /* Only if the OSCILLATOR is not already enabled */
mbed_official 324:406fd2029f23 132 RTC_CR = (uint32_t)((RTC_CR & (uint32_t)~(uint32_t)(RTC_CR_SC2P_MASK | RTC_CR_SC4P_MASK | RTC_CR_SC8P_MASK | RTC_CR_SC16P_MASK)) | (uint32_t)SYSTEM_RTC_CR_VALUE);
mbed_official 324:406fd2029f23 133 RTC_CR |= (uint32_t)RTC_CR_OSCE_MASK;
mbed_official 324:406fd2029f23 134 RTC_CR &= (uint32_t)~(uint32_t)RTC_CR_CLKO_MASK;
mbed_official 324:406fd2029f23 135 }
mbed_official 324:406fd2029f23 136 #endif
mbed_official 146:f64d43ff0c18 137 }
mbed_official 146:f64d43ff0c18 138
mbed_official 324:406fd2029f23 139 /* Power mode protection initialization */
mbed_official 324:406fd2029f23 140 #ifdef SYSTEM_SMC_PMPROT_VALUE
mbed_official 324:406fd2029f23 141 SMC->PMPROT = SYSTEM_SMC_PMPROT_VALUE;
mbed_official 324:406fd2029f23 142 #endif
mbed_official 324:406fd2029f23 143
mbed_official 324:406fd2029f23 144 /* System clock initialization */
mbed_official 324:406fd2029f23 145 /* Internal reference clock trim initialization */
mbed_official 324:406fd2029f23 146 #if defined(SLOW_TRIM_ADDRESS)
mbed_official 324:406fd2029f23 147 if ( *((uint8_t*)SLOW_TRIM_ADDRESS) != 0xFFU) { /* Skip if non-volatile flash memory is erased */
mbed_official 324:406fd2029f23 148 MCG->C3 = *((uint8_t*)SLOW_TRIM_ADDRESS);
mbed_official 324:406fd2029f23 149 #endif /* defined(SLOW_TRIM_ADDRESS) */
mbed_official 324:406fd2029f23 150 #if defined(SLOW_FINE_TRIM_ADDRESS)
mbed_official 324:406fd2029f23 151 MCG->C4 = (MCG->C4 & ~(MCG_C4_SCFTRIM_MASK)) | ((*((uint8_t*) SLOW_FINE_TRIM_ADDRESS)) & MCG_C4_SCFTRIM_MASK);
mbed_official 324:406fd2029f23 152 #endif
mbed_official 324:406fd2029f23 153 #if defined(FAST_TRIM_ADDRESS)
mbed_official 324:406fd2029f23 154 MCG->C4 = (MCG->C4 & ~(MCG_C4_FCTRIM_MASK)) |((*((uint8_t*) FAST_TRIM_ADDRESS)) & MCG_C4_FCTRIM_MASK);
mbed_official 146:f64d43ff0c18 155 #endif
mbed_official 324:406fd2029f23 156 #if defined(FAST_FINE_TRIM_ADDRESS)
mbed_official 324:406fd2029f23 157 MCG->C2 = (MCG->C2 & ~(MCG_C2_FCFTRIM_MASK)) | ((*((uint8_t*)FAST_TRIM_ADDRESS)) & MCG_C2_FCFTRIM_MASK);
mbed_official 324:406fd2029f23 158 #endif /* defined(FAST_FINE_TRIM_ADDRESS) */
mbed_official 324:406fd2029f23 159 #if defined(SLOW_TRIM_ADDRESS)
mbed_official 146:f64d43ff0c18 160 }
mbed_official 324:406fd2029f23 161 #endif /* defined(SLOW_TRIM_ADDRESS) */
mbed_official 324:406fd2029f23 162
mbed_official 324:406fd2029f23 163 /* Set system prescalers and clock sources */
mbed_official 324:406fd2029f23 164 SIM->CLKDIV1 = SYSTEM_SIM_CLKDIV1_VALUE; /* Set system prescalers */
mbed_official 324:406fd2029f23 165 SIM->SOPT1 = ((SIM->SOPT1) & (uint32_t)(~(SIM_SOPT1_OSC32KSEL_MASK))) | ((SYSTEM_SIM_SOPT1_VALUE) & (SIM_SOPT1_OSC32KSEL_MASK)); /* Set 32 kHz clock source (ERCLK32K) */
mbed_official 324:406fd2029f23 166 SIM->SOPT2 = ((SIM->SOPT2) & (uint32_t)(~(SIM_SOPT2_PLLFLLSEL_MASK))) | ((SYSTEM_SIM_SOPT2_VALUE) & (SIM_SOPT2_PLLFLLSEL_MASK)); /* Selects the high frequency clock for various peripheral clocking options. */
mbed_official 324:406fd2029f23 167 #if ((MCG_MODE == MCG_MODE_FEI) || (MCG_MODE == MCG_MODE_FBI) || (MCG_MODE == MCG_MODE_BLPI))
mbed_official 324:406fd2029f23 168 /* Set MCG and OSC */
mbed_official 324:406fd2029f23 169 #if ((((SYSTEM_OSC_CR_VALUE) & OSC_CR_ERCLKEN_MASK) != 0x00U) || ((((SYSTEM_MCG_C5_VALUE) & MCG_C5_PLLCLKEN0_MASK) != 0x00U) && (((SYSTEM_MCG_C7_VALUE) & MCG_C7_OSCSEL_MASK) == 0x00U)))
mbed_official 324:406fd2029f23 170 /* SIM_SCGC5: PORTA=1 */
mbed_official 324:406fd2029f23 171 SIM_SCGC5 |= SIM_SCGC5_PORTA_MASK;
mbed_official 324:406fd2029f23 172 /* PORTA_PCR18: ISF=0,MUX=0 */
mbed_official 324:406fd2029f23 173 PORTA_PCR18 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
mbed_official 324:406fd2029f23 174 if (((SYSTEM_MCG_C2_VALUE) & MCG_C2_EREFS_MASK) != 0x00U) {
mbed_official 324:406fd2029f23 175 /* PORTA_PCR19: ISF=0,MUX=0 */
mbed_official 324:406fd2029f23 176 PORTA_PCR19 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
mbed_official 146:f64d43ff0c18 177 }
mbed_official 324:406fd2029f23 178 #endif
mbed_official 324:406fd2029f23 179 MCG->SC = SYSTEM_MCG_SC_VALUE; /* Set SC (fast clock internal reference divider) */
mbed_official 324:406fd2029f23 180 MCG->C1 = SYSTEM_MCG_C1_VALUE; /* Set C1 (clock source selection, FLL ext. reference divider, int. reference enable etc.) */
mbed_official 324:406fd2029f23 181 /* Check that the source of the FLL reference clock is the requested one. */
mbed_official 324:406fd2029f23 182 if (((SYSTEM_MCG_C1_VALUE) & MCG_C1_IREFS_MASK) != 0x00U) {
mbed_official 324:406fd2029f23 183 while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) {
mbed_official 324:406fd2029f23 184 }
mbed_official 324:406fd2029f23 185 } else {
mbed_official 324:406fd2029f23 186 while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) {
mbed_official 324:406fd2029f23 187 }
mbed_official 146:f64d43ff0c18 188 }
mbed_official 324:406fd2029f23 189 MCG->C2 = (MCG->C2 & (uint8_t)(~(MCG_C2_FCFTRIM_MASK))) | (SYSTEM_MCG_C2_VALUE & (uint8_t)(~(MCG_C2_LP_MASK))); /* Set C2 (freq. range, ext. and int. reference selection etc. excluding trim bits; low power bit is set later) */
mbed_official 324:406fd2029f23 190 MCG->C4 = ((SYSTEM_MCG_C4_VALUE) & (uint8_t)(~(MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK))) | (MCG->C4 & (MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK)); /* Set C4 (FLL output; trim values not changed) */
mbed_official 324:406fd2029f23 191 OSC->CR = SYSTEM_OSC_CR_VALUE; /* Set OSC_CR (OSCERCLK enable, oscillator capacitor load) */
mbed_official 324:406fd2029f23 192 MCG->C7 = SYSTEM_MCG_C7_VALUE; /* Set C7 (OSC Clock Select) */
mbed_official 324:406fd2029f23 193 #if (MCG_MODE == MCG_MODE_BLPI)
mbed_official 324:406fd2029f23 194 /* BLPI specific */
mbed_official 324:406fd2029f23 195 MCG->C2 |= (MCG_C2_LP_MASK); /* Disable FLL and PLL in bypass mode */
mbed_official 324:406fd2029f23 196 #endif
mbed_official 324:406fd2029f23 197
mbed_official 324:406fd2029f23 198 #else /* MCG_MODE */
mbed_official 324:406fd2029f23 199 /* Set MCG and OSC */
mbed_official 324:406fd2029f23 200 #if (((SYSTEM_OSC_CR_VALUE) & OSC_CR_ERCLKEN_MASK) != 0x00U) || (((SYSTEM_MCG_C7_VALUE) & MCG_C7_OSCSEL_MASK) == 0x00U)
mbed_official 324:406fd2029f23 201 /* SIM_SCGC5: PORTA=1 */
mbed_official 324:406fd2029f23 202 SIM_SCGC5 |= SIM_SCGC5_PORTA_MASK;
mbed_official 324:406fd2029f23 203 /* PORTA_PCR18: ISF=0,MUX=0 */
mbed_official 324:406fd2029f23 204 PORTA_PCR18 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
mbed_official 324:406fd2029f23 205 if (((SYSTEM_MCG_C2_VALUE) & MCG_C2_EREFS_MASK) != 0x00U) {
mbed_official 324:406fd2029f23 206 /* PORTA_PCR19: ISF=0,MUX=0 */
mbed_official 324:406fd2029f23 207 PORTA_PCR19 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
mbed_official 146:f64d43ff0c18 208 }
mbed_official 146:f64d43ff0c18 209 #endif
mbed_official 324:406fd2029f23 210 MCG->SC = SYSTEM_MCG_SC_VALUE; /* Set SC (fast clock internal reference divider) */
mbed_official 324:406fd2029f23 211 MCG->C2 = (MCG->C2 & (uint8_t)(~(MCG_C2_FCFTRIM_MASK))) | (SYSTEM_MCG_C2_VALUE & (uint8_t)(~(MCG_C2_LP_MASK))); /* Set C2 (freq. range, ext. and int. reference selection etc. excluding trim bits; low power bit is set later) */
mbed_official 324:406fd2029f23 212 OSC->CR = SYSTEM_OSC_CR_VALUE; /* Set OSC_CR (OSCERCLK enable, oscillator capacitor load) */
mbed_official 324:406fd2029f23 213 MCG->C7 = SYSTEM_MCG_C7_VALUE; /* Set C7 (OSC Clock Select) */
mbed_official 324:406fd2029f23 214 #if (MCG_MODE == MCG_MODE_PEE)
mbed_official 324:406fd2029f23 215 MCG->C1 = (SYSTEM_MCG_C1_VALUE) | MCG_C1_CLKS(0x02); /* Set C1 (clock source selection, FLL ext. reference divider, int. reference enable etc.) - PBE mode*/
mbed_official 324:406fd2029f23 216 #else
mbed_official 324:406fd2029f23 217 MCG->C1 = SYSTEM_MCG_C1_VALUE; /* Set C1 (clock source selection, FLL ext. reference divider, int. reference enable etc.) */
mbed_official 324:406fd2029f23 218 #endif
mbed_official 324:406fd2029f23 219 if ((((SYSTEM_MCG_C2_VALUE) & MCG_C2_EREFS_MASK) != 0x00U) && (((SYSTEM_MCG_C7_VALUE) & MCG_C7_OSCSEL_MASK) == 0x00U)) {
mbed_official 324:406fd2029f23 220 while((MCG->S & MCG_S_OSCINIT0_MASK) == 0x00U) { /* Check that the oscillator is running */
mbed_official 324:406fd2029f23 221 }
mbed_official 324:406fd2029f23 222 }
mbed_official 324:406fd2029f23 223 /* Check that the source of the FLL reference clock is the requested one. */
mbed_official 324:406fd2029f23 224 if (((SYSTEM_MCG_C1_VALUE) & MCG_C1_IREFS_MASK) != 0x00U) {
mbed_official 324:406fd2029f23 225 while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) {
mbed_official 324:406fd2029f23 226 }
mbed_official 324:406fd2029f23 227 } else {
mbed_official 324:406fd2029f23 228 while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) {
mbed_official 324:406fd2029f23 229 }
mbed_official 324:406fd2029f23 230 }
mbed_official 324:406fd2029f23 231 MCG->C4 = ((SYSTEM_MCG_C4_VALUE) & (uint8_t)(~(MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK))) | (MCG->C4 & (MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK)); /* Set C4 (FLL output; trim values not changed) */
mbed_official 324:406fd2029f23 232 #endif /* MCG_MODE */
mbed_official 324:406fd2029f23 233
mbed_official 324:406fd2029f23 234 /* Common for all MCG modes */
mbed_official 324:406fd2029f23 235
mbed_official 324:406fd2029f23 236 /* PLL clock can be used to generate clock for some devices regardless of clock generator (MCGOUTCLK) mode. */
mbed_official 324:406fd2029f23 237 MCG->C5 = (SYSTEM_MCG_C5_VALUE) & (uint8_t)(~(MCG_C5_PLLCLKEN0_MASK)); /* Set C5 (PLL settings, PLL reference divider etc.) */
mbed_official 324:406fd2029f23 238 MCG->C6 = (SYSTEM_MCG_C6_VALUE) & (uint8_t)~(MCG_C6_PLLS_MASK); /* Set C6 (PLL select, VCO divider etc.) */
mbed_official 324:406fd2029f23 239 if ((SYSTEM_MCG_C5_VALUE) & MCG_C5_PLLCLKEN0_MASK) {
mbed_official 324:406fd2029f23 240 MCG->C5 |= MCG_C5_PLLCLKEN0_MASK; /* PLL clock enable in mode other than PEE or PBE */
mbed_official 324:406fd2029f23 241 }
mbed_official 324:406fd2029f23 242 /* BLPE, PEE and PBE MCG mode specific */
mbed_official 324:406fd2029f23 243
mbed_official 324:406fd2029f23 244 #if (MCG_MODE == MCG_MODE_BLPE)
mbed_official 324:406fd2029f23 245 MCG->C2 |= (MCG_C2_LP_MASK); /* Disable FLL and PLL in bypass mode */
mbed_official 324:406fd2029f23 246 #elif ((MCG_MODE == MCG_MODE_PBE) || (MCG_MODE == MCG_MODE_PEE))
mbed_official 324:406fd2029f23 247 MCG->C6 |= (MCG_C6_PLLS_MASK); /* Set C6 (PLL select, VCO divider etc.) */
mbed_official 324:406fd2029f23 248 while((MCG->S & MCG_S_LOCK0_MASK) == 0x00U) { /* Wait until PLL is locked*/
mbed_official 324:406fd2029f23 249 }
mbed_official 324:406fd2029f23 250 #if (MCG_MODE == MCG_MODE_PEE)
mbed_official 324:406fd2029f23 251 MCG->C1 &= (uint8_t)~(MCG_C1_CLKS_MASK);
mbed_official 324:406fd2029f23 252 #endif
mbed_official 324:406fd2029f23 253 #endif
mbed_official 324:406fd2029f23 254 #if ((MCG_MODE == MCG_MODE_FEI) || (MCG_MODE == MCG_MODE_FEE))
mbed_official 324:406fd2029f23 255 while((MCG->S & MCG_S_CLKST_MASK) != 0x00U) { /* Wait until output of the FLL is selected */
mbed_official 324:406fd2029f23 256 }
mbed_official 324:406fd2029f23 257 #elif ((MCG_MODE == MCG_MODE_FBI) || (MCG_MODE == MCG_MODE_BLPI))
mbed_official 324:406fd2029f23 258 while((MCG->S & MCG_S_CLKST_MASK) != 0x04U) { /* Wait until internal reference clock is selected as MCG output */
mbed_official 324:406fd2029f23 259 }
mbed_official 324:406fd2029f23 260 #elif ((MCG_MODE == MCG_MODE_FBE) || (MCG_MODE == MCG_MODE_PBE) || (MCG_MODE == MCG_MODE_BLPE))
mbed_official 324:406fd2029f23 261 while((MCG->S & MCG_S_CLKST_MASK) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
mbed_official 324:406fd2029f23 262 }
mbed_official 324:406fd2029f23 263 #elif (MCG_MODE == MCG_MODE_PEE)
mbed_official 324:406fd2029f23 264 while((MCG->S & MCG_S_CLKST_MASK) != 0x0CU) { /* Wait until output of the PLL is selected */
mbed_official 324:406fd2029f23 265 }
mbed_official 324:406fd2029f23 266 #endif
mbed_official 324:406fd2029f23 267 #if (((SYSTEM_SMC_PMCTRL_VALUE) & SMC_PMCTRL_RUNM_MASK) == (0x02U << SMC_PMCTRL_RUNM_SHIFT))
mbed_official 324:406fd2029f23 268 SMC->PMCTRL = (uint8_t)((SYSTEM_SMC_PMCTRL_VALUE) & (SMC_PMCTRL_RUNM_MASK)); /* Enable VLPR mode */
mbed_official 324:406fd2029f23 269 while(SMC->PMSTAT != 0x04U) { /* Wait until the system is in VLPR mode */
mbed_official 324:406fd2029f23 270 }
mbed_official 324:406fd2029f23 271 #endif
mbed_official 324:406fd2029f23 272
mbed_official 324:406fd2029f23 273 #if defined(SYSTEM_SIM_CLKDIV2_VALUE)
mbed_official 324:406fd2029f23 274 SIM->CLKDIV2 = ((SIM->CLKDIV2) & (uint32_t)(~(SIM_CLKDIV2_USBFRAC_MASK | SIM_CLKDIV2_USBDIV_MASK))) | ((SYSTEM_SIM_CLKDIV2_VALUE) & (SIM_CLKDIV2_USBFRAC_MASK | SIM_CLKDIV2_USBDIV_MASK)); /* Selects the USB clock divider. */
mbed_official 324:406fd2029f23 275 #endif
mbed_official 324:406fd2029f23 276
mbed_official 324:406fd2029f23 277 /* PLL loss of lock interrupt request initialization */
mbed_official 324:406fd2029f23 278 if (((SYSTEM_MCG_C6_VALUE) & MCG_C6_LOLIE0_MASK) != 0U) {
mbed_official 324:406fd2029f23 279 NVIC_EnableIRQ(MCG_IRQn); /* Enable PLL loss of lock interrupt request */
mbed_official 324:406fd2029f23 280 }
mbed_official 146:f64d43ff0c18 281 }
mbed_official 146:f64d43ff0c18 282
mbed_official 146:f64d43ff0c18 283 /* ----------------------------------------------------------------------------
mbed_official 146:f64d43ff0c18 284 -- SystemCoreClockUpdate()
mbed_official 146:f64d43ff0c18 285 ---------------------------------------------------------------------------- */
mbed_official 146:f64d43ff0c18 286
mbed_official 146:f64d43ff0c18 287 void SystemCoreClockUpdate (void) {
mbed_official 324:406fd2029f23 288 uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */
mbed_official 324:406fd2029f23 289 uint16_t Divider;
mbed_official 146:f64d43ff0c18 290
mbed_official 324:406fd2029f23 291 if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x00U) {
mbed_official 146:f64d43ff0c18 292 /* Output of FLL or PLL is selected */
mbed_official 324:406fd2029f23 293 if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U) {
mbed_official 146:f64d43ff0c18 294 /* FLL is selected */
mbed_official 324:406fd2029f23 295 if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U) {
mbed_official 146:f64d43ff0c18 296 /* External reference clock is selected */
mbed_official 324:406fd2029f23 297 switch (MCG->C7 & MCG_C7_OSCSEL_MASK) {
mbed_official 324:406fd2029f23 298 case 0x00U:
mbed_official 324:406fd2029f23 299 MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
mbed_official 324:406fd2029f23 300 break;
mbed_official 324:406fd2029f23 301 case 0x01U:
mbed_official 324:406fd2029f23 302 MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
mbed_official 324:406fd2029f23 303 break;
mbed_official 324:406fd2029f23 304 case 0x02U:
mbed_official 324:406fd2029f23 305 default:
mbed_official 324:406fd2029f23 306 MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
mbed_official 324:406fd2029f23 307 break;
mbed_official 324:406fd2029f23 308 }
mbed_official 324:406fd2029f23 309 if (((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) && ((MCG->C7 & MCG_C7_OSCSEL_MASK) != 0x01U)) {
mbed_official 324:406fd2029f23 310 switch (MCG->C1 & MCG_C1_FRDIV_MASK) {
mbed_official 324:406fd2029f23 311 case 0x38U:
mbed_official 324:406fd2029f23 312 Divider = 1536U;
mbed_official 324:406fd2029f23 313 break;
mbed_official 324:406fd2029f23 314 case 0x30U:
mbed_official 324:406fd2029f23 315 Divider = 1280U;
mbed_official 324:406fd2029f23 316 break;
mbed_official 324:406fd2029f23 317 default:
mbed_official 324:406fd2029f23 318 Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
mbed_official 324:406fd2029f23 319 break;
mbed_official 324:406fd2029f23 320 }
mbed_official 324:406fd2029f23 321 } else {/* ((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) */
mbed_official 324:406fd2029f23 322 Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
mbed_official 324:406fd2029f23 323 }
mbed_official 324:406fd2029f23 324 MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
mbed_official 324:406fd2029f23 325 } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
mbed_official 324:406fd2029f23 326 MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
mbed_official 324:406fd2029f23 327 } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
mbed_official 146:f64d43ff0c18 328 /* Select correct multiplier to calculate the MCG output clock */
mbed_official 146:f64d43ff0c18 329 switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
mbed_official 324:406fd2029f23 330 case 0x00U:
mbed_official 324:406fd2029f23 331 MCGOUTClock *= 640U;
mbed_official 146:f64d43ff0c18 332 break;
mbed_official 324:406fd2029f23 333 case 0x20U:
mbed_official 324:406fd2029f23 334 MCGOUTClock *= 1280U;
mbed_official 146:f64d43ff0c18 335 break;
mbed_official 324:406fd2029f23 336 case 0x40U:
mbed_official 324:406fd2029f23 337 MCGOUTClock *= 1920U;
mbed_official 146:f64d43ff0c18 338 break;
mbed_official 324:406fd2029f23 339 case 0x60U:
mbed_official 324:406fd2029f23 340 MCGOUTClock *= 2560U;
mbed_official 146:f64d43ff0c18 341 break;
mbed_official 324:406fd2029f23 342 case 0x80U:
mbed_official 324:406fd2029f23 343 MCGOUTClock *= 732U;
mbed_official 146:f64d43ff0c18 344 break;
mbed_official 324:406fd2029f23 345 case 0xA0U:
mbed_official 324:406fd2029f23 346 MCGOUTClock *= 1464U;
mbed_official 146:f64d43ff0c18 347 break;
mbed_official 324:406fd2029f23 348 case 0xC0U:
mbed_official 324:406fd2029f23 349 MCGOUTClock *= 2197U;
mbed_official 146:f64d43ff0c18 350 break;
mbed_official 324:406fd2029f23 351 case 0xE0U:
mbed_official 324:406fd2029f23 352 MCGOUTClock *= 2929U;
mbed_official 146:f64d43ff0c18 353 break;
mbed_official 146:f64d43ff0c18 354 default:
mbed_official 146:f64d43ff0c18 355 break;
mbed_official 146:f64d43ff0c18 356 }
mbed_official 324:406fd2029f23 357 } else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
mbed_official 146:f64d43ff0c18 358 /* PLL is selected */
mbed_official 324:406fd2029f23 359 Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV0_MASK) + 0x01U);
mbed_official 324:406fd2029f23 360 MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */
mbed_official 324:406fd2029f23 361 Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV0_MASK) + 24U);
mbed_official 324:406fd2029f23 362 MCGOUTClock *= Divider; /* Calculate the MCG output clock */
mbed_official 324:406fd2029f23 363 } /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
mbed_official 324:406fd2029f23 364 } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40U) {
mbed_official 146:f64d43ff0c18 365 /* Internal reference clock is selected */
mbed_official 324:406fd2029f23 366 if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U) {
mbed_official 324:406fd2029f23 367 MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
mbed_official 324:406fd2029f23 368 } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
mbed_official 324:406fd2029f23 369 Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT));
mbed_official 324:406fd2029f23 370 MCGOUTClock = (uint32_t) (CPU_INT_FAST_CLK_HZ / Divider); /* Fast internal reference clock selected */
mbed_official 324:406fd2029f23 371 } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
mbed_official 324:406fd2029f23 372 } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U) {
mbed_official 146:f64d43ff0c18 373 /* External reference clock is selected */
mbed_official 324:406fd2029f23 374 switch (MCG->C7 & MCG_C7_OSCSEL_MASK) {
mbed_official 324:406fd2029f23 375 case 0x00U:
mbed_official 324:406fd2029f23 376 MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
mbed_official 324:406fd2029f23 377 break;
mbed_official 324:406fd2029f23 378 case 0x01U:
mbed_official 324:406fd2029f23 379 MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
mbed_official 324:406fd2029f23 380 break;
mbed_official 324:406fd2029f23 381 case 0x02U:
mbed_official 324:406fd2029f23 382 default:
mbed_official 324:406fd2029f23 383 MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
mbed_official 324:406fd2029f23 384 break;
mbed_official 324:406fd2029f23 385 }
mbed_official 324:406fd2029f23 386 } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
mbed_official 146:f64d43ff0c18 387 /* Reserved value */
mbed_official 146:f64d43ff0c18 388 return;
mbed_official 324:406fd2029f23 389 } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
mbed_official 324:406fd2029f23 390 SystemCoreClock = (MCGOUTClock / (0x01U + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
mbed_official 146:f64d43ff0c18 391 }