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Last commit 20 Feb 2019 by mbed official

targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/system_MKL43Z4.h@579:53297373a894, 2015-07-01 (annotated)

Committer:
mbed_official
Date:
Wed Jul 01 09:45:11 2015 +0100
Revision:
579:53297373a894
Parent:
363:12a245e5c745 
Synchronized with git revision d5b4d2ab9c47edb4dc5776e7177b0c2263459081



Full URL: https://github.com/mbedmicro/mbed/commit/d5b4d2ab9c47edb4dc5776e7177b0c2263459081/



Initial version of drivers for SAMR21

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 363:12a245e5c745 1 /*
mbed_official 363:12a245e5c745 2 ** ###################################################################
mbed_official 363:12a245e5c745 3 ** Processors: MKL43Z256VLH4
mbed_official 363:12a245e5c745 4 ** MKL43Z128VLH4
mbed_official 363:12a245e5c745 5 ** MKL43Z64VLH4
mbed_official 363:12a245e5c745 6 ** MKL43Z256VMP4
mbed_official 363:12a245e5c745 7 ** MKL43Z128VMP4
mbed_official 363:12a245e5c745 8 ** MKL43Z64VMP4
mbed_official 363:12a245e5c745 9 **
mbed_official 363:12a245e5c745 10 ** Compilers: Keil ARM C/C++ Compiler
mbed_official 363:12a245e5c745 11 ** Freescale C/C++ for Embedded ARM
mbed_official 363:12a245e5c745 12 ** GNU C Compiler
mbed_official 363:12a245e5c745 13 ** GNU C Compiler - CodeSourcery Sourcery G++
mbed_official 363:12a245e5c745 14 ** IAR ANSI C/C++ Compiler for ARM
mbed_official 363:12a245e5c745 15 **
mbed_official 363:12a245e5c745 16 ** Reference manual: KL43P64M48SF6RM, Rev.3, Aug 2014
mbed_official 363:12a245e5c745 17 ** Version: rev. 1.4, 2014-09-01
mbed_official 363:12a245e5c745 18 ** Build: b140904
mbed_official 363:12a245e5c745 19 **
mbed_official 363:12a245e5c745 20 ** Abstract:
mbed_official 363:12a245e5c745 21 ** Provides a system configuration function and a global variable that
mbed_official 363:12a245e5c745 22 ** contains the system frequency. It configures the device and initializes
mbed_official 363:12a245e5c745 23 ** the oscillator (PLL) that is part of the microcontroller device.
mbed_official 363:12a245e5c745 24 **
mbed_official 363:12a245e5c745 25 ** Copyright (c) 2014 Freescale Semiconductor, Inc.
mbed_official 363:12a245e5c745 26 ** All rights reserved.
mbed_official 363:12a245e5c745 27 **
mbed_official 363:12a245e5c745 28 ** Redistribution and use in source and binary forms, with or without modification,
mbed_official 363:12a245e5c745 29 ** are permitted provided that the following conditions are met:
mbed_official 363:12a245e5c745 30 **
mbed_official 363:12a245e5c745 31 ** o Redistributions of source code must retain the above copyright notice, this list
mbed_official 363:12a245e5c745 32 ** of conditions and the following disclaimer.
mbed_official 363:12a245e5c745 33 **
mbed_official 363:12a245e5c745 34 ** o Redistributions in binary form must reproduce the above copyright notice, this
mbed_official 363:12a245e5c745 35 ** list of conditions and the following disclaimer in the documentation and/or
mbed_official 363:12a245e5c745 36 ** other materials provided with the distribution.
mbed_official 363:12a245e5c745 37 **
mbed_official 363:12a245e5c745 38 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
mbed_official 363:12a245e5c745 39 ** contributors may be used to endorse or promote products derived from this
mbed_official 363:12a245e5c745 40 ** software without specific prior written permission.
mbed_official 363:12a245e5c745 41 **
mbed_official 363:12a245e5c745 42 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
mbed_official 363:12a245e5c745 43 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
mbed_official 363:12a245e5c745 44 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 363:12a245e5c745 45 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
mbed_official 363:12a245e5c745 46 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
mbed_official 363:12a245e5c745 47 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
mbed_official 363:12a245e5c745 48 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
mbed_official 363:12a245e5c745 49 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
mbed_official 363:12a245e5c745 50 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
mbed_official 363:12a245e5c745 51 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 363:12a245e5c745 52 **
mbed_official 363:12a245e5c745 53 ** http: www.freescale.com
mbed_official 363:12a245e5c745 54 ** mail: support@freescale.com
mbed_official 363:12a245e5c745 55 **
mbed_official 363:12a245e5c745 56 ** Revisions:
mbed_official 363:12a245e5c745 57 ** - rev. 1.0 (2014-03-27)
mbed_official 363:12a245e5c745 58 ** Initial version.
mbed_official 363:12a245e5c745 59 ** - rev. 1.1 (2014-05-26)
mbed_official 363:12a245e5c745 60 ** I2S registers TCR2/RCR2 and others were changed.
mbed_official 363:12a245e5c745 61 ** FLEXIO register FLEXIO_VERID has now bitfields: FEATURE, MINOR, MAJOR.
mbed_official 363:12a245e5c745 62 ** Names of the bitfields of the FLEXIO_SHIFTBUF have been changed to the appropriate register name e.g.: FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS.
mbed_official 363:12a245e5c745 63 ** Peripheral_BASES macros has been changed to Peripheral_BASE_PTRS, e.g.: ADC_BASES to ADC_BASE_PTRS.
mbed_official 363:12a245e5c745 64 ** Clock configuration for high range external oscillator has been added.
mbed_official 363:12a245e5c745 65 ** RFSYS module access has been added.
mbed_official 363:12a245e5c745 66 ** - rev. 1.2 (2014-07-10)
mbed_official 363:12a245e5c745 67 ** GPIO - Renamed modules PTA,PTB,PTC,PTD,PTE to GPIOA,GPIOB,GPIOC,GPIOD,GPIOE.
mbed_official 363:12a245e5c745 68 ** UART0 - UART0 module renamed to UART2.
mbed_official 363:12a245e5c745 69 ** I2S - removed MDR register.
mbed_official 363:12a245e5c745 70 ** - rev. 1.3 (2014-08-21)
mbed_official 363:12a245e5c745 71 ** UART2 - Removed ED register.
mbed_official 363:12a245e5c745 72 ** UART2 - Removed MODEM register.
mbed_official 363:12a245e5c745 73 ** UART2 - Removed IR register.
mbed_official 363:12a245e5c745 74 ** UART2 - Removed PFIFO register.
mbed_official 363:12a245e5c745 75 ** UART2 - Removed CFIFO register.
mbed_official 363:12a245e5c745 76 ** UART2 - Removed SFIFO register.
mbed_official 363:12a245e5c745 77 ** UART2 - Removed TWFIFO register.
mbed_official 363:12a245e5c745 78 ** UART2 - Removed TCFIFO register.
mbed_official 363:12a245e5c745 79 ** UART2 - Removed RWFIFO register.
mbed_official 363:12a245e5c745 80 ** UART2 - Removed RCFIFO register.
mbed_official 363:12a245e5c745 81 ** USB - Removed bitfield REG_EN in CLK_RECOVER_IRC_EN register.
mbed_official 363:12a245e5c745 82 ** SIM - Changed bitfield value MCGIRCLK to LIRC_CLK of bitfield CLKOUTSEL in SOPT2 register.
mbed_official 363:12a245e5c745 83 ** SIM - Removed bitfield DIEID in SDID register.
mbed_official 363:12a245e5c745 84 ** - rev. 1.4 (2014-09-01)
mbed_official 363:12a245e5c745 85 ** USB - USB0_CTL0 was renamed to USB0_OTGCTL register.
mbed_official 363:12a245e5c745 86 ** USB - USB0_CTL1 was renamed to USB0_CTL register.
mbed_official 363:12a245e5c745 87 **
mbed_official 363:12a245e5c745 88 ** ###################################################################
mbed_official 363:12a245e5c745 89 */
mbed_official 363:12a245e5c745 90
mbed_official 363:12a245e5c745 91 /*!
mbed_official 363:12a245e5c745 92 * @file MKL43Z4
mbed_official 363:12a245e5c745 93 * @version 1.4
mbed_official 363:12a245e5c745 94 * @date 2014-09-01
mbed_official 363:12a245e5c745 95 * @brief Device specific configuration file for MKL43Z4 (header file)
mbed_official 363:12a245e5c745 96 *
mbed_official 363:12a245e5c745 97 * Provides a system configuration function and a global variable that contains
mbed_official 363:12a245e5c745 98 * the system frequency. It configures the device and initializes the oscillator
mbed_official 363:12a245e5c745 99 * (PLL) that is part of the microcontroller device.
mbed_official 363:12a245e5c745 100 */
mbed_official 363:12a245e5c745 101
mbed_official 363:12a245e5c745 102 #ifndef SYSTEM_MKL43Z4_H_
mbed_official 363:12a245e5c745 103 #define SYSTEM_MKL43Z4_H_ /**< Symbol preventing repeated inclusion */
mbed_official 363:12a245e5c745 104
mbed_official 363:12a245e5c745 105 #ifdef __cplusplus
mbed_official 363:12a245e5c745 106 extern "C" {
mbed_official 363:12a245e5c745 107 #endif
mbed_official 363:12a245e5c745 108
mbed_official 363:12a245e5c745 109 #include <stdint.h>
mbed_official 363:12a245e5c745 110
mbed_official 363:12a245e5c745 111
mbed_official 363:12a245e5c745 112 #ifndef DISABLE_WDOG
mbed_official 363:12a245e5c745 113 #define DISABLE_WDOG 1
mbed_official 363:12a245e5c745 114 #endif
mbed_official 363:12a245e5c745 115
mbed_official 363:12a245e5c745 116 #define ACK_ISOLATION 1
mbed_official 363:12a245e5c745 117
mbed_official 363:12a245e5c745 118 #ifndef CLOCK_SETUP
mbed_official 363:12a245e5c745 119 #define CLOCK_SETUP 1
mbed_official 363:12a245e5c745 120 #endif
mbed_official 363:12a245e5c745 121
mbed_official 363:12a245e5c745 122 /* MCG_Lite mode constants */
mbed_official 363:12a245e5c745 123
mbed_official 363:12a245e5c745 124 #define MCG_MODE_LIRC_8M 0U
mbed_official 363:12a245e5c745 125 #define MCG_MODE_HIRC 1U
mbed_official 363:12a245e5c745 126 #define MCG_MODE_LIRC_2M 2U
mbed_official 363:12a245e5c745 127 #define MCG_MODE_EXT 3U
mbed_official 363:12a245e5c745 128
mbed_official 363:12a245e5c745 129 /* Predefined clock setups
mbed_official 363:12a245e5c745 130 0 ... Multipurpose Clock Generator Lite (MCG_Lite) in Low-frequency Internal Reference Clock 8 MHz (LIRC 8 MHz) mode
mbed_official 363:12a245e5c745 131 Default part configuration.
mbed_official 363:12a245e5c745 132 Core clock/Bus clock derived from the internal clock source 8 MHz
mbed_official 363:12a245e5c745 133 Core clock = 4MHz, BusClock = 2MHz, USB FS clock derived from external clock USB_CLKIN (applicable only for derivatived with USB)
mbed_official 363:12a245e5c745 134 1 ... Multipurpose Clock Generator Lite (MCG_Lite) in High-frequency Internal Reference Clock (HIRC) mode
mbed_official 363:12a245e5c745 135 Maximum achievable clock frequency configuration using internal clock.
mbed_official 363:12a245e5c745 136 Core clock/Bus clock derived from the internal clock source 48MHz
mbed_official 363:12a245e5c745 137 Core clock = 48MHz, BusClock = 24MHz, USB FS clock derived from external clock USB_CLKIN (applicable only for derivatived with USB)
mbed_official 363:12a245e5c745 138 2 ... Multipurpose Clock Generator Lite (MCG_Lite) in External Oscillator (EXT) mode
mbed_official 363:12a245e5c745 139 Core clock/Bus clock derived directly from the external crystal 32.768kHz
mbed_official 363:12a245e5c745 140 The clock settings is ready for Very Low Power Run mode.
mbed_official 363:12a245e5c745 141 Core clock = 32.768kHz, BusClock = 32.768kHz, USB FS clock derived from external clock USB_CLKIN (applicable only for derivatived with USB)
mbed_official 363:12a245e5c745 142 3 ... Multipurpose Clock Generator Lite (MCG_Lite) in Low-frequency Internal Reference Clock 2 MHz (LIRC 2 MHz) mode
mbed_official 363:12a245e5c745 143 Core clock/Bus clock derived from the internal clock source 2 MHz
mbed_official 363:12a245e5c745 144 The clock settings is ready for Very Low Power Run mode.
mbed_official 363:12a245e5c745 145 Core clock = 2MHz, BusClock = 1MHz, USB FS clock derived from external clock USB_CLKIN (applicable only for derivatived with USB)
mbed_official 363:12a245e5c745 146 4 ... Multipurpose Clock Generator Lite (MCG_Lite) in High-frequency Internal Reference Clock (HIRC) mode
mbed_official 363:12a245e5c745 147 USB clock setup - for USB to receive internal 48MHz clock derived from HIRC.
mbed_official 363:12a245e5c745 148 Core clock/Bus clock derived from the internal clock source 48MHz
mbed_official 363:12a245e5c745 149 Core clock = 48MHz, BusClock = 24MHz, USB FS clock derived from HIRC (MCGPCLK)
mbed_official 363:12a245e5c745 150 5 ... Multipurpose Clock Generator Lite (MCG_Lite) in External Oscillator (EXT) mode
mbed_official 363:12a245e5c745 151 Core clock/Bus clock derived directly from the external crystal 8 MHz
mbed_official 363:12a245e5c745 152 Core clock = 8MHz, BusClock = 4MHz, USB FS clock derived from external clock USB_CLKIN (applicable only for derivatived with USB)
mbed_official 363:12a245e5c745 153 */
mbed_official 363:12a245e5c745 154
mbed_official 363:12a245e5c745 155 /* Define clock source values */
mbed_official 363:12a245e5c745 156
mbed_official 363:12a245e5c745 157 #define CPU_XTAL_CLK_HZ 32768u /* Value of the external crystal or oscillator clock frequency in Hz */
mbed_official 363:12a245e5c745 158 #define CPU_INT_FAST_CLK_HZ 48000000u /* Value of the fast internal oscillator clock frequency in Hz */
mbed_official 363:12a245e5c745 159 #define CPU_INT_IRC_CLK_HZ 48000000u /* Value of the 48M internal oscillator clock frequency in Hz */
mbed_official 363:12a245e5c745 160
mbed_official 363:12a245e5c745 161 /* Low power mode enable */
mbed_official 363:12a245e5c745 162 /* SMC_PMPROT: AVLP=1,AVLLS=1 */
mbed_official 363:12a245e5c745 163 #define SMC_PMPROT_VALUE 0x22u /* SMC_PMPROT */
mbed_official 363:12a245e5c745 164
mbed_official 363:12a245e5c745 165 #if (CLOCK_SETUP == 0)
mbed_official 363:12a245e5c745 166 #define DEFAULT_SYSTEM_CLOCK 4000000u /* Default System clock value */
mbed_official 363:12a245e5c745 167 #define CPU_INT_SLOW_CLK_HZ 8000000u /* Value of the slow internal oscillator clock frequency in Hz */
mbed_official 363:12a245e5c745 168 #define MCG_MODE MCG_MODE_LIRC_8M /* Clock generator mode */
mbed_official 363:12a245e5c745 169 /* MCG_C1: CLKS=1,IRCLKEN=1,IREFSTEN=0 */
mbed_official 363:12a245e5c745 170 #define MCG_C1_VALUE 0x42u /* MCG_C1 */
mbed_official 363:12a245e5c745 171 /* MCG_C2: RANGE0=0,HGO0=0,EREFS0=0,IRCS=1 */
mbed_official 363:12a245e5c745 172 #define MCG_C2_VALUE 0x01u /* MCG_C2 */
mbed_official 363:12a245e5c745 173 /* MCG_SC: FCRDIV=0 */
mbed_official 363:12a245e5c745 174 #define MCG_SC_VALUE 0x00u /* MCG_SC */
mbed_official 363:12a245e5c745 175 /* MCG_MC: HIRCEN=0 LIRC_DIV2=0 */
mbed_official 363:12a245e5c745 176 #define MCG_MC_VALUE 0x00u /* MCG_MC */
mbed_official 363:12a245e5c745 177 /* OSC0_CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
mbed_official 363:12a245e5c745 178 #define OSC0_CR_VALUE 0x00u /* OSC0_CR */
mbed_official 363:12a245e5c745 179 /* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
mbed_official 363:12a245e5c745 180 #define SMC_PMCTRL_VALUE 0x00u /* SMC_PMCTRL */
mbed_official 363:12a245e5c745 181 /* SIM_CLKDIV1: OUTDIV1=1,OUTDIV4=1 */
mbed_official 363:12a245e5c745 182 #define SYSTEM_SIM_CLKDIV1_VALUE 0x10010000u /* SIM_CLKDIV1 */
mbed_official 363:12a245e5c745 183 /* SIM_SOPT1: OSC32KSEL=0,OSC32KOUT=0 */
mbed_official 363:12a245e5c745 184 #define SYSTEM_SIM_SOPT1_VALUE 0x00000000u /* SIM_SOPT1 */
mbed_official 363:12a245e5c745 185 /* SIM_SOPT2: LPUART1SRC=0,LPUART0SRC=0,TPMSRC=3,FLEXIOSRC=0,USBSRC=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
mbed_official 363:12a245e5c745 186 #define SYSTEM_SIM_SOPT2_VALUE 0x03000000u /* SIM_SOPT2 */
mbed_official 363:12a245e5c745 187 #elif (CLOCK_SETUP == 1)
mbed_official 363:12a245e5c745 188 #define DEFAULT_SYSTEM_CLOCK 48000000u /* Default System clock value */
mbed_official 363:12a245e5c745 189 #define CPU_INT_SLOW_CLK_HZ 8000000u /* Value of the slow internal oscillator clock frequency in Hz */
mbed_official 363:12a245e5c745 190 #define MCG_MODE MCG_MODE_HIRC /* Clock generator mode */
mbed_official 363:12a245e5c745 191 /* MCG_C1: CLKS=0,IRCLKEN=0,IREFSTEN=0 */
mbed_official 363:12a245e5c745 192 #define MCG_C1_VALUE 0x00u /* MCG_C1 */
mbed_official 363:12a245e5c745 193 /* MCG_C2: RANGE0=0,HGO0=0,EREFS0=0,IRCS=1 */
mbed_official 363:12a245e5c745 194 #define MCG_C2_VALUE 0x01u /* MCG_C2 */
mbed_official 363:12a245e5c745 195 /* MCG_SC: FCRDIV=0 */
mbed_official 363:12a245e5c745 196 #define MCG_SC_VALUE 0x00u /* MCG_SC */
mbed_official 363:12a245e5c745 197 /* MCG_MC: HIRCEN=1 LIRC_DIV2=0 */
mbed_official 363:12a245e5c745 198 #define MCG_MC_VALUE 0x80u /* MCG_MC */
mbed_official 363:12a245e5c745 199 /* OSC0_CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
mbed_official 363:12a245e5c745 200 #define OSC0_CR_VALUE 0x00u /* OSC0_CR */
mbed_official 363:12a245e5c745 201 /* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
mbed_official 363:12a245e5c745 202 #define SMC_PMCTRL_VALUE 0x00u /* SMC_PMCTRL */
mbed_official 363:12a245e5c745 203 /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV4=1 */
mbed_official 363:12a245e5c745 204 #define SYSTEM_SIM_CLKDIV1_VALUE 0x10000u /* SIM_CLKDIV1 */
mbed_official 363:12a245e5c745 205 /* SIM_SOPT1: OSC32KSEL=0,OSC32KOUT=0 */
mbed_official 363:12a245e5c745 206 #define SYSTEM_SIM_SOPT1_VALUE 0x00000000u /* SIM_SOPT1 */
mbed_official 363:12a245e5c745 207 /* SIM_SOPT2: LPUART1SRC=0,LPUART0SRC=0,TPMSRC=3,FLEXIOSRC=0,USBSRC=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
mbed_official 363:12a245e5c745 208 #define SYSTEM_SIM_SOPT2_VALUE 0x03000000U /* SIM_SOPT2 */
mbed_official 363:12a245e5c745 209 #elif (CLOCK_SETUP == 2)
mbed_official 363:12a245e5c745 210 #define DEFAULT_SYSTEM_CLOCK 32768u /* Default System clock value */
mbed_official 363:12a245e5c745 211 #define CPU_INT_SLOW_CLK_HZ 8000000u /* Value of the slow internal oscillator clock frequency in Hz */
mbed_official 363:12a245e5c745 212 #define MCG_MODE MCG_MODE_EXT /* Clock generator mode */
mbed_official 363:12a245e5c745 213 /* MCG_C1: CLKS=2,IRCLKEN=1,IREFSTEN=0 */
mbed_official 363:12a245e5c745 214 #define MCG_C1_VALUE 0x82u /* MCG_C1 */
mbed_official 363:12a245e5c745 215 /* MCG_C2: RANGE0=0,HGO0=0,EREFS0=1,IRCS=1 */
mbed_official 363:12a245e5c745 216 #define MCG_C2_VALUE 0x05u /* MCG_C2 */
mbed_official 363:12a245e5c745 217 /* MCG_SC: FCRDIV=0 */
mbed_official 363:12a245e5c745 218 #define MCG_SC_VALUE 0x00u /* MCG_SC */
mbed_official 363:12a245e5c745 219 /* MCG_MC: HIRCEN=0 LIRC_DIV2=0 */
mbed_official 363:12a245e5c745 220 #define MCG_MC_VALUE 0x00u /* MCG_MC */
mbed_official 363:12a245e5c745 221 /* OSC0_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
mbed_official 363:12a245e5c745 222 #define OSC0_CR_VALUE 0x80u /* OSC0_CR */
mbed_official 363:12a245e5c745 223 /* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
mbed_official 363:12a245e5c745 224 #define SMC_PMCTRL_VALUE 0x00u /* SMC_PMCTRL */
mbed_official 363:12a245e5c745 225 /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV4=0 */
mbed_official 363:12a245e5c745 226 #define SYSTEM_SIM_CLKDIV1_VALUE 0x00u /* SIM_CLKDIV1 */
mbed_official 363:12a245e5c745 227 /* SIM_SOPT1: OSC32KSEL=0,OSC32KOUT=0 */
mbed_official 363:12a245e5c745 228 #define SYSTEM_SIM_SOPT1_VALUE 0x00000000u /* SIM_SOPT1 */
mbed_official 363:12a245e5c745 229 /* SIM_SOPT2: LPUART1SRC=0,LPUART0SRC=0,TPMSRC=2,FLEXIOSRC=0,USBSRC=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
mbed_official 363:12a245e5c745 230 #define SYSTEM_SIM_SOPT2_VALUE 0x02000000u /* SIM_SOPT2 */
mbed_official 363:12a245e5c745 231 #elif (CLOCK_SETUP == 3)
mbed_official 363:12a245e5c745 232 #define DEFAULT_SYSTEM_CLOCK 2000000u /* Default System clock value */
mbed_official 363:12a245e5c745 233 #define CPU_INT_SLOW_CLK_HZ 2000000u /* Value of the slow internal oscillator clock frequency in Hz */
mbed_official 363:12a245e5c745 234 #define MCG_MODE MCG_MODE_LIRC_2M /* Clock generator mode */
mbed_official 363:12a245e5c745 235 /* MCG_C1: CLKS=1,IRCLKEN=1,IREFSTEN=0 */
mbed_official 363:12a245e5c745 236 #define MCG_C1_VALUE 0x42u /* MCG_C1 */
mbed_official 363:12a245e5c745 237 /* MCG_C2: RANGE0=0,HGO0=0,EREFS0=0,IRCS=0 */
mbed_official 363:12a245e5c745 238 #define MCG_C2_VALUE 0x00u /* MCG_C2 */
mbed_official 363:12a245e5c745 239 /* MCG_SC: FCRDIV=0 */
mbed_official 363:12a245e5c745 240 #define MCG_SC_VALUE 0x00u /* MCG_SC */
mbed_official 363:12a245e5c745 241 /* MCG_MC: HIRCEN=0 LIRC_DIV2=0 */
mbed_official 363:12a245e5c745 242 #define MCG_MC_VALUE 0x00u /* MCG_MC */
mbed_official 363:12a245e5c745 243 /* OSC0_CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
mbed_official 363:12a245e5c745 244 #define OSC0_CR_VALUE 0x00u /* OSC0_CR */
mbed_official 363:12a245e5c745 245 /* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
mbed_official 363:12a245e5c745 246 #define SMC_PMCTRL_VALUE 0x00u /* SMC_PMCTRL */
mbed_official 363:12a245e5c745 247 /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV4=1 */
mbed_official 363:12a245e5c745 248 #define SYSTEM_SIM_CLKDIV1_VALUE 0x10000u /* SIM_CLKDIV1 */
mbed_official 363:12a245e5c745 249 /* SIM_SOPT1: OSC32KSEL=0,OSC32KOUT=0 */
mbed_official 363:12a245e5c745 250 #define SYSTEM_SIM_SOPT1_VALUE 0x00000000u /* SIM_SOPT1 */
mbed_official 363:12a245e5c745 251 /* SIM_SOPT2: LPUART1SRC=0,LPUART0SRC=0,TPMSRC=3,FLEXIOSRC=0,USBSRC=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
mbed_official 363:12a245e5c745 252 #define SYSTEM_SIM_SOPT2_VALUE 0x03000000u /* SIM_SOPT2 */
mbed_official 363:12a245e5c745 253 #elif (CLOCK_SETUP == 4)
mbed_official 363:12a245e5c745 254 #define DEFAULT_SYSTEM_CLOCK 2000000u /* Default System clock value */
mbed_official 363:12a245e5c745 255 #define CPU_INT_SLOW_CLK_HZ 8000000u /* Value of the slow internal oscillator clock frequency in Hz */
mbed_official 363:12a245e5c745 256 #define MCG_MODE MCG_MODE_LIRC_2M /* Clock generator mode */
mbed_official 363:12a245e5c745 257 /* MCG_C1: CLKS=0,IRCLKEN=1,IREFSTEN=0 */
mbed_official 363:12a245e5c745 258 #define MCG_C1_VALUE 0x02u /* MCG_C1 */
mbed_official 363:12a245e5c745 259 /* MCG_C2: RANGE0=0,HGO0=0,EREFS0=0,IRCS=1 */
mbed_official 363:12a245e5c745 260 #define MCG_C2_VALUE 0x01u /* MCG_C2 */
mbed_official 363:12a245e5c745 261 /* MCG_SC: FCRDIV=0 */
mbed_official 363:12a245e5c745 262 #define MCG_SC_VALUE 0x00u /* MCG_SC */
mbed_official 363:12a245e5c745 263 /* MCG_MC: HIRCEN=1 LIRC_DIV2=0 */
mbed_official 363:12a245e5c745 264 #define MCG_MC_VALUE 0x80u /* MCG_MC */
mbed_official 363:12a245e5c745 265 /* OSC0_CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
mbed_official 363:12a245e5c745 266 #define OSC0_CR_VALUE 0x00u /* OSC0_CR */
mbed_official 363:12a245e5c745 267 /* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
mbed_official 363:12a245e5c745 268 #define SMC_PMCTRL_VALUE 0x00u /* SMC_PMCTRL */
mbed_official 363:12a245e5c745 269 /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV4=1 */
mbed_official 363:12a245e5c745 270 #define SYSTEM_SIM_CLKDIV1_VALUE 0x10000u /* SIM_CLKDIV1 */
mbed_official 363:12a245e5c745 271 /* SIM_SOPT1: OSC32KSEL=0,OSC32KOUT=0 */
mbed_official 363:12a245e5c745 272 #define SYSTEM_SIM_SOPT1_VALUE 0x00000000u /* SIM_SOPT1 */
mbed_official 363:12a245e5c745 273 /* SIM_SOPT2: LPUART1SRC=0,LPUART0SRC=0,TPMSRC=3,FLEXIOSRC=0,USBSRC=1,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
mbed_official 363:12a245e5c745 274 #define SYSTEM_SIM_SOPT2_VALUE 0x03040000u /* SIM_SOPT2 */
mbed_official 363:12a245e5c745 275 #elif (CLOCK_SETUP == 5)
mbed_official 363:12a245e5c745 276 #define DEFAULT_SYSTEM_CLOCK 2000000u /* Default System clock value */
mbed_official 363:12a245e5c745 277 #define CPU_INT_SLOW_CLK_HZ 2000000u /* Value of the slow internal oscillator clock frequency in Hz */
mbed_official 363:12a245e5c745 278 #define MCG_MODE MCG_MODE_LIRC_2M /* Clock generator mode */
mbed_official 363:12a245e5c745 279 /* MCG_C1: CLKS=2,IRCLKEN=0,IREFSTEN=0 */
mbed_official 363:12a245e5c745 280 #define MCG_C1_VALUE 0x80u /* MCG_C1 */
mbed_official 363:12a245e5c745 281 /* MCG_C2: RANGE0=1,HGO0=0,EREFS0=1,IRCS=1 */
mbed_official 363:12a245e5c745 282 #define MCG_C2_VALUE 0x15u /* MCG_C2 */
mbed_official 363:12a245e5c745 283 /* MCG_SC: FCRDIV=0 */
mbed_official 363:12a245e5c745 284 #define MCG_SC_VALUE 0x00u /* MCG_SC */
mbed_official 363:12a245e5c745 285 /* MCG_MC: HIRCEN=0 LIRC_DIV2=0 */
mbed_official 363:12a245e5c745 286 #define MCG_MC_VALUE 0x00u /* MCG_MC */
mbed_official 363:12a245e5c745 287 /* OSC0_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
mbed_official 363:12a245e5c745 288 #define OSC0_CR_VALUE 0x80u /* OSC0_CR */
mbed_official 363:12a245e5c745 289 /* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
mbed_official 363:12a245e5c745 290 #define SMC_PMCTRL_VALUE 0x00u /* SMC_PMCTRL */
mbed_official 363:12a245e5c745 291 /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV4=1 */
mbed_official 363:12a245e5c745 292 #define SYSTEM_SIM_CLKDIV1_VALUE 0x10000u /* SIM_CLKDIV1 */
mbed_official 363:12a245e5c745 293 /* SIM_SOPT1: OSC32KSEL=0,OSC32KOUT=0 */
mbed_official 363:12a245e5c745 294 #define SYSTEM_SIM_SOPT1_VALUE 0x00000000u /* SIM_SOPT1 */
mbed_official 363:12a245e5c745 295 /* SIM_SOPT2: LPUART1SRC=0,LPUART0SRC=0,TPMSRC=3,FLEXIOSRC=0,USBSRC=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
mbed_official 363:12a245e5c745 296 #define SYSTEM_SIM_SOPT2_VALUE 0x03000000u /* SIM_SOPT2 */
mbed_official 363:12a245e5c745 297 #else
mbed_official 363:12a245e5c745 298 #error The selected clock setup is not supported.
mbed_official 363:12a245e5c745 299 #endif /* (CLOCK_SETUP == 5) */
mbed_official 363:12a245e5c745 300
mbed_official 363:12a245e5c745 301
mbed_official 363:12a245e5c745 302 /**
mbed_official 363:12a245e5c745 303 * @brief System clock frequency (core clock)
mbed_official 363:12a245e5c745 304 *
mbed_official 363:12a245e5c745 305 * The system clock frequency supplied to the SysTick timer and the processor
mbed_official 363:12a245e5c745 306 * core clock. This variable can be used by the user application to setup the
mbed_official 363:12a245e5c745 307 * SysTick timer or configure other parameters. It may also be used by debugger to
mbed_official 363:12a245e5c745 308 * query the frequency of the debug timer or configure the trace clock speed
mbed_official 363:12a245e5c745 309 * SystemCoreClock is initialized with a correct predefined value.
mbed_official 363:12a245e5c745 310 */
mbed_official 363:12a245e5c745 311 extern uint32_t SystemCoreClock;
mbed_official 363:12a245e5c745 312
mbed_official 363:12a245e5c745 313 /**
mbed_official 363:12a245e5c745 314 * @brief Setup the microcontroller system.
mbed_official 363:12a245e5c745 315 *
mbed_official 363:12a245e5c745 316 * Typically this function configures the oscillator (PLL) that is part of the
mbed_official 363:12a245e5c745 317 * microcontroller device. For systems with variable clock speed it also updates
mbed_official 363:12a245e5c745 318 * the variable SystemCoreClock. SystemInit is called from startup_device file.
mbed_official 363:12a245e5c745 319 */
mbed_official 363:12a245e5c745 320 void SystemInit (void);
mbed_official 363:12a245e5c745 321
mbed_official 363:12a245e5c745 322 /**
mbed_official 363:12a245e5c745 323 * @brief Updates the SystemCoreClock variable.
mbed_official 363:12a245e5c745 324 *
mbed_official 363:12a245e5c745 325 * It must be called whenever the core clock is changed during program
mbed_official 363:12a245e5c745 326 * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
mbed_official 363:12a245e5c745 327 * the current core clock.
mbed_official 363:12a245e5c745 328 */
mbed_official 363:12a245e5c745 329 void SystemCoreClockUpdate (void);
mbed_official 363:12a245e5c745 330
mbed_official 363:12a245e5c745 331 #ifdef __cplusplus
mbed_official 363:12a245e5c745 332 }
mbed_official 363:12a245e5c745 333 #endif
mbed_official 363:12a245e5c745 334
mbed_official 363:12a245e5c745 335 #endif /* #if !defined(SYSTEM_MKL43Z4_H_) */