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Last commit 20 Feb 2019 by mbed official

targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/system_MKL43Z4.c@579:53297373a894, 2015-07-01 (annotated)

Committer:
mbed_official
Date:
Wed Jul 01 09:45:11 2015 +0100
Revision:
579:53297373a894
Parent:
363:12a245e5c745 
Synchronized with git revision d5b4d2ab9c47edb4dc5776e7177b0c2263459081



Full URL: https://github.com/mbedmicro/mbed/commit/d5b4d2ab9c47edb4dc5776e7177b0c2263459081/



Initial version of drivers for SAMR21

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 363:12a245e5c745 1 /*
mbed_official 363:12a245e5c745 2 ** ###################################################################
mbed_official 363:12a245e5c745 3 ** Processors: MKL43Z256VLH4
mbed_official 363:12a245e5c745 4 ** MKL43Z128VLH4
mbed_official 363:12a245e5c745 5 ** MKL43Z64VLH4
mbed_official 363:12a245e5c745 6 ** MKL43Z256VMP4
mbed_official 363:12a245e5c745 7 ** MKL43Z128VMP4
mbed_official 363:12a245e5c745 8 ** MKL43Z64VMP4
mbed_official 363:12a245e5c745 9 **
mbed_official 363:12a245e5c745 10 ** Compilers: Keil ARM C/C++ Compiler
mbed_official 363:12a245e5c745 11 ** Freescale C/C++ for Embedded ARM
mbed_official 363:12a245e5c745 12 ** GNU C Compiler
mbed_official 363:12a245e5c745 13 ** GNU C Compiler - CodeSourcery Sourcery G++
mbed_official 363:12a245e5c745 14 ** IAR ANSI C/C++ Compiler for ARM
mbed_official 363:12a245e5c745 15 **
mbed_official 363:12a245e5c745 16 ** Reference manual: KL43P64M48SF6RM, Rev.3, Aug 2014
mbed_official 363:12a245e5c745 17 ** Version: rev. 1.4, 2014-09-01
mbed_official 363:12a245e5c745 18 ** Build: b140904
mbed_official 363:12a245e5c745 19 **
mbed_official 363:12a245e5c745 20 ** Abstract:
mbed_official 363:12a245e5c745 21 ** Provides a system configuration function and a global variable that
mbed_official 363:12a245e5c745 22 ** contains the system frequency. It configures the device and initializes
mbed_official 363:12a245e5c745 23 ** the oscillator (PLL) that is part of the microcontroller device.
mbed_official 363:12a245e5c745 24 **
mbed_official 363:12a245e5c745 25 ** Copyright (c) 2014 Freescale Semiconductor, Inc.
mbed_official 363:12a245e5c745 26 ** All rights reserved.
mbed_official 363:12a245e5c745 27 **
mbed_official 363:12a245e5c745 28 ** Redistribution and use in source and binary forms, with or without modification,
mbed_official 363:12a245e5c745 29 ** are permitted provided that the following conditions are met:
mbed_official 363:12a245e5c745 30 **
mbed_official 363:12a245e5c745 31 ** o Redistributions of source code must retain the above copyright notice, this list
mbed_official 363:12a245e5c745 32 ** of conditions and the following disclaimer.
mbed_official 363:12a245e5c745 33 **
mbed_official 363:12a245e5c745 34 ** o Redistributions in binary form must reproduce the above copyright notice, this
mbed_official 363:12a245e5c745 35 ** list of conditions and the following disclaimer in the documentation and/or
mbed_official 363:12a245e5c745 36 ** other materials provided with the distribution.
mbed_official 363:12a245e5c745 37 **
mbed_official 363:12a245e5c745 38 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
mbed_official 363:12a245e5c745 39 ** contributors may be used to endorse or promote products derived from this
mbed_official 363:12a245e5c745 40 ** software without specific prior written permission.
mbed_official 363:12a245e5c745 41 **
mbed_official 363:12a245e5c745 42 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
mbed_official 363:12a245e5c745 43 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
mbed_official 363:12a245e5c745 44 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 363:12a245e5c745 45 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
mbed_official 363:12a245e5c745 46 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
mbed_official 363:12a245e5c745 47 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
mbed_official 363:12a245e5c745 48 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
mbed_official 363:12a245e5c745 49 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
mbed_official 363:12a245e5c745 50 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
mbed_official 363:12a245e5c745 51 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 363:12a245e5c745 52 **
mbed_official 363:12a245e5c745 53 ** http: www.freescale.com
mbed_official 363:12a245e5c745 54 ** mail: support@freescale.com
mbed_official 363:12a245e5c745 55 **
mbed_official 363:12a245e5c745 56 ** Revisions:
mbed_official 363:12a245e5c745 57 ** - rev. 1.0 (2014-03-27)
mbed_official 363:12a245e5c745 58 ** Initial version.
mbed_official 363:12a245e5c745 59 ** - rev. 1.1 (2014-05-26)
mbed_official 363:12a245e5c745 60 ** I2S registers TCR2/RCR2 and others were changed.
mbed_official 363:12a245e5c745 61 ** FLEXIO register FLEXIO_VERID has now bitfields: FEATURE, MINOR, MAJOR.
mbed_official 363:12a245e5c745 62 ** Names of the bitfields of the FLEXIO_SHIFTBUF have been changed to the appropriate register name e.g.: FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS.
mbed_official 363:12a245e5c745 63 ** Peripheral_BASES macros has been changed to Peripheral_BASE_PTRS, e.g.: ADC_BASES to ADC_BASE_PTRS.
mbed_official 363:12a245e5c745 64 ** Clock configuration for high range external oscillator has been added.
mbed_official 363:12a245e5c745 65 ** RFSYS module access has been added.
mbed_official 363:12a245e5c745 66 ** - rev. 1.2 (2014-07-10)
mbed_official 363:12a245e5c745 67 ** GPIO - Renamed modules PTA,PTB,PTC,PTD,PTE to GPIOA,GPIOB,GPIOC,GPIOD,GPIOE.
mbed_official 363:12a245e5c745 68 ** UART0 - UART0 module renamed to UART2.
mbed_official 363:12a245e5c745 69 ** I2S - removed MDR register.
mbed_official 363:12a245e5c745 70 ** - rev. 1.3 (2014-08-21)
mbed_official 363:12a245e5c745 71 ** UART2 - Removed ED register.
mbed_official 363:12a245e5c745 72 ** UART2 - Removed MODEM register.
mbed_official 363:12a245e5c745 73 ** UART2 - Removed IR register.
mbed_official 363:12a245e5c745 74 ** UART2 - Removed PFIFO register.
mbed_official 363:12a245e5c745 75 ** UART2 - Removed CFIFO register.
mbed_official 363:12a245e5c745 76 ** UART2 - Removed SFIFO register.
mbed_official 363:12a245e5c745 77 ** UART2 - Removed TWFIFO register.
mbed_official 363:12a245e5c745 78 ** UART2 - Removed TCFIFO register.
mbed_official 363:12a245e5c745 79 ** UART2 - Removed RWFIFO register.
mbed_official 363:12a245e5c745 80 ** UART2 - Removed RCFIFO register.
mbed_official 363:12a245e5c745 81 ** USB - Removed bitfield REG_EN in CLK_RECOVER_IRC_EN register.
mbed_official 363:12a245e5c745 82 ** SIM - Changed bitfield value MCGIRCLK to LIRC_CLK of bitfield CLKOUTSEL in SOPT2 register.
mbed_official 363:12a245e5c745 83 ** SIM - Removed bitfield DIEID in SDID register.
mbed_official 363:12a245e5c745 84 ** - rev. 1.4 (2014-09-01)
mbed_official 363:12a245e5c745 85 ** USB - USB0_CTL0 was renamed to USB0_OTGCTL register.
mbed_official 363:12a245e5c745 86 ** USB - USB0_CTL1 was renamed to USB0_CTL register.
mbed_official 363:12a245e5c745 87 **
mbed_official 363:12a245e5c745 88 ** ###################################################################
mbed_official 363:12a245e5c745 89 */
mbed_official 363:12a245e5c745 90
mbed_official 363:12a245e5c745 91 /*!
mbed_official 363:12a245e5c745 92 * @file MKL43Z4
mbed_official 363:12a245e5c745 93 * @version 1.4
mbed_official 363:12a245e5c745 94 * @date 2014-09-01
mbed_official 363:12a245e5c745 95 * @brief Device specific configuration file for MKL43Z4 (implementation file)
mbed_official 363:12a245e5c745 96 *
mbed_official 363:12a245e5c745 97 * Provides a system configuration function and a global variable that contains
mbed_official 363:12a245e5c745 98 * the system frequency. It configures the device and initializes the oscillator
mbed_official 363:12a245e5c745 99 * (PLL) that is part of the microcontroller device.
mbed_official 363:12a245e5c745 100 */
mbed_official 363:12a245e5c745 101
mbed_official 363:12a245e5c745 102 #include <stdint.h>
mbed_official 363:12a245e5c745 103 #include "MKL43Z4.h"
mbed_official 363:12a245e5c745 104
mbed_official 363:12a245e5c745 105
mbed_official 363:12a245e5c745 106
mbed_official 363:12a245e5c745 107 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 108 -- Core clock
mbed_official 363:12a245e5c745 109 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 110
mbed_official 363:12a245e5c745 111 uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
mbed_official 363:12a245e5c745 112
mbed_official 363:12a245e5c745 113 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 114 -- SystemInit()
mbed_official 363:12a245e5c745 115 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 116
mbed_official 363:12a245e5c745 117 void SystemInit (void) {
mbed_official 363:12a245e5c745 118
mbed_official 363:12a245e5c745 119 #if (ACK_ISOLATION)
mbed_official 363:12a245e5c745 120 if(PMC->REGSC & PMC_REGSC_ACKISO_MASK) {
mbed_official 363:12a245e5c745 121 PMC->REGSC |= PMC_REGSC_ACKISO_MASK; /* VLLSx recovery */
mbed_official 363:12a245e5c745 122 }
mbed_official 363:12a245e5c745 123 #endif
mbed_official 363:12a245e5c745 124
mbed_official 363:12a245e5c745 125 #if (DISABLE_WDOG)
mbed_official 363:12a245e5c745 126 /* SIM->COPC: ?=0,COPCLKSEL=0,COPDBGEN=0,COPSTPEN=0,COPT=0,COPCLKS=0,COPW=0 */
mbed_official 363:12a245e5c745 127 SIM->COPC = (uint32_t)0x00u;
mbed_official 363:12a245e5c745 128 #endif /* (DISABLE_WDOG) */
mbed_official 363:12a245e5c745 129
mbed_official 363:12a245e5c745 130 /* Power mode protection initialization */
mbed_official 363:12a245e5c745 131 #ifdef SMC_PMPROT_VALUE
mbed_official 363:12a245e5c745 132 SMC->PMPROT = SMC_PMPROT_VALUE;
mbed_official 363:12a245e5c745 133 #endif
mbed_official 363:12a245e5c745 134
mbed_official 363:12a245e5c745 135 /* System clock initialization */
mbed_official 363:12a245e5c745 136
mbed_official 363:12a245e5c745 137 /* Set system prescalers and clock sources */
mbed_official 363:12a245e5c745 138 SIM->CLKDIV1 = SYSTEM_SIM_CLKDIV1_VALUE; /* Set system prescalers */
mbed_official 363:12a245e5c745 139 SIM->SOPT1 = ((SIM->SOPT1) & (uint32_t)(~(SIM_SOPT1_OSC32KSEL_MASK))) | ((SYSTEM_SIM_SOPT1_VALUE) & (SIM_SOPT1_OSC32KSEL_MASK)); /* Set 32 kHz clock source (ERCLK32K) */
mbed_official 363:12a245e5c745 140 #define SOPT2_WRITE_MASK ((SIM_SOPT2_USBSRC_MASK) | (SIM_SOPT2_TPMSRC_MASK) | (SIM_SOPT2_LPUART0SRC_MASK) | (SIM_SOPT2_LPUART1SRC_MASK)) /* define mask of written bits. */
mbed_official 363:12a245e5c745 141 SIM->SOPT2 = ((SIM->SOPT2) & (uint32_t)(~SOPT2_WRITE_MASK)) | ((SYSTEM_SIM_SOPT2_VALUE) & SOPT2_WRITE_MASK); /* Selects the clock source for the TPM counter clock. */
mbed_official 363:12a245e5c745 142 #if (MCG_MODE == MCG_MODE_LIRC_2M || MCG_MODE == MCG_MODE_LIRC_8M || MCG_MODE == MCG_MODE_HIRC)
mbed_official 363:12a245e5c745 143 /* Set MCG and OSC0 */
mbed_official 363:12a245e5c745 144 #if (((OSC0_CR_VALUE) & OSC_CR_ERCLKEN_MASK) != 0x00U)
mbed_official 363:12a245e5c745 145 /* SIM_SCGC5: PORTA=1 */
mbed_official 363:12a245e5c745 146 SIM_SCGC5 |= SIM_SCGC5_PORTA_MASK;
mbed_official 363:12a245e5c745 147 /* PORTA_PCR3: ISF=0,MUX=0 */
mbed_official 363:12a245e5c745 148 PORTA_PCR18 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
mbed_official 363:12a245e5c745 149 if (((MCG_C2_VALUE) & MCG_C2_EREFS0_MASK) != 0x00U) {
mbed_official 363:12a245e5c745 150 PORTA_PCR19 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
mbed_official 363:12a245e5c745 151 }
mbed_official 363:12a245e5c745 152 #endif
mbed_official 363:12a245e5c745 153 MCG->SC = MCG_SC_VALUE; /* Set SC (internal reference clock divider) */
mbed_official 363:12a245e5c745 154 MCG->MC = MCG_MC_VALUE; /* Set MC (high-frequency IRC enable, second LIRC divider) */
mbed_official 363:12a245e5c745 155 MCG->C1 = MCG_C1_VALUE; /* Set C1 (clock source selection, int. reference enable etc.) */
mbed_official 363:12a245e5c745 156 MCG->C2 = MCG_C2_VALUE; /* Set C2 (ext. and int. reference clock selection) */
mbed_official 363:12a245e5c745 157 OSC0->CR = OSC0_CR_VALUE; /* Set OSC0_CR (OSCERCLK enable, oscillator capacitor load) */
mbed_official 363:12a245e5c745 158
mbed_official 363:12a245e5c745 159 #else /* MCG_MODE */
mbed_official 363:12a245e5c745 160 /* Set MCG and OSC0 */
mbed_official 363:12a245e5c745 161 /* SIM_SCGC5: PORTA=1 */
mbed_official 363:12a245e5c745 162 SIM_SCGC5 |= SIM_SCGC5_PORTA_MASK;
mbed_official 363:12a245e5c745 163 /* PORTA_PCR3: ISF=0,MUX=0 */
mbed_official 363:12a245e5c745 164 PORTA_PCR18 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
mbed_official 363:12a245e5c745 165 if (((MCG_C2_VALUE) & MCG_C2_EREFS0_MASK) != 0x00U) {
mbed_official 363:12a245e5c745 166 PORTA_PCR19 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
mbed_official 363:12a245e5c745 167 }
mbed_official 363:12a245e5c745 168 MCG->SC = MCG_SC_VALUE; /* Set SC (internal reference clock divider) */
mbed_official 363:12a245e5c745 169 MCG->C2 = MCG_C2_VALUE; /* Set C2 (ext. and int. reference clock selection) */
mbed_official 363:12a245e5c745 170 OSC0->CR = OSC0_CR_VALUE; /* Set OSC0_CR (OSCERCLK enable, oscillator capacitor load) */
mbed_official 363:12a245e5c745 171 MCG->C1 = MCG_C1_VALUE; /* Set C1 (clock source selection, int. reference enable etc.) */
mbed_official 363:12a245e5c745 172 MCG->MC = MCG_MC_VALUE; /* Set MC (high-frequency IRC enable, second LIRC divider) */
mbed_official 363:12a245e5c745 173 if (((MCG_C2_VALUE) & MCG_C2_EREFS0_MASK) != 0U) {
mbed_official 363:12a245e5c745 174 while((MCG->S & MCG_S_OSCINIT0_MASK) == 0x00U) { /* Check that the oscillator is running */
mbed_official 363:12a245e5c745 175 }
mbed_official 363:12a245e5c745 176 }
mbed_official 363:12a245e5c745 177 #endif /* MCG_MODE */
mbed_official 363:12a245e5c745 178
mbed_official 363:12a245e5c745 179 /* Common for all MCG modes */
mbed_official 363:12a245e5c745 180
mbed_official 363:12a245e5c745 181 #if (MCG_MODE == MCG_MODE_HIRC)
mbed_official 363:12a245e5c745 182 while((MCG->S & MCG_S_CLKST_MASK) != 0x00U) { /* Wait until high internal reference clock is selected as MCG_Lite output */
mbed_official 363:12a245e5c745 183 }
mbed_official 363:12a245e5c745 184 #elif (MCG_MODE == MCG_MODE_LIRC_2M || MCG_MODE == MCG_MODE_LIRC_8M)
mbed_official 363:12a245e5c745 185 while((MCG->S & MCG_S_CLKST_MASK) != 0x04U) { /* Wait until low internal reference clock is selected as MCG_Lite output */
mbed_official 363:12a245e5c745 186 }
mbed_official 363:12a245e5c745 187 #elif (MCG_MODE == MCG_MODE_EXT)
mbed_official 363:12a245e5c745 188 while((MCG->S & MCG_S_CLKST_MASK) != 0x08U) { /* Wait until external reference clock is selected as MCG_Lite output */
mbed_official 363:12a245e5c745 189 }
mbed_official 363:12a245e5c745 190 #endif
mbed_official 363:12a245e5c745 191 if (((SMC_PMCTRL_VALUE) & SMC_PMCTRL_RUNM_MASK) == SMC_PMCTRL_RUNM(0x02U)) {
mbed_official 363:12a245e5c745 192 SMC->PMCTRL = (uint8_t)((SMC_PMCTRL_VALUE) & (SMC_PMCTRL_RUNM_MASK)); /* Enable VLPR mode */
mbed_official 363:12a245e5c745 193 while(SMC->PMSTAT != 0x04U) { /* Wait until the system is in VLPR mode */
mbed_official 363:12a245e5c745 194 }
mbed_official 363:12a245e5c745 195 }
mbed_official 363:12a245e5c745 196
mbed_official 363:12a245e5c745 197 }
mbed_official 363:12a245e5c745 198
mbed_official 363:12a245e5c745 199 /* ----------------------------------------------------------------------------
mbed_official 363:12a245e5c745 200 -- SystemCoreClockUpdate()
mbed_official 363:12a245e5c745 201 ---------------------------------------------------------------------------- */
mbed_official 363:12a245e5c745 202
mbed_official 363:12a245e5c745 203 void SystemCoreClockUpdate (void) {
mbed_official 363:12a245e5c745 204
mbed_official 363:12a245e5c745 205 uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */
mbed_official 363:12a245e5c745 206 uint16_t Divider;
mbed_official 363:12a245e5c745 207
mbed_official 363:12a245e5c745 208 if ((MCG->S & MCG_S_CLKST_MASK) == 0x00U) {
mbed_official 363:12a245e5c745 209 /* High internal reference clock is selected */
mbed_official 363:12a245e5c745 210 MCGOUTClock = CPU_INT_FAST_CLK_HZ; /* Fast internal reference clock selected */
mbed_official 363:12a245e5c745 211 } else if ((MCG->S & MCG_S_CLKST_MASK) == 0x04U) {
mbed_official 363:12a245e5c745 212 /* Internal reference clock is selected */
mbed_official 363:12a245e5c745 213 Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT));
mbed_official 363:12a245e5c745 214 MCGOUTClock = (uint32_t) (CPU_INT_SLOW_CLK_HZ / Divider); /* Slow internal reference clock 8MHz selected */
mbed_official 363:12a245e5c745 215 } else if ((MCG->S & MCG_S_CLKST_MASK) == 0x08U) {
mbed_official 363:12a245e5c745 216 /* External reference clock is selected */
mbed_official 363:12a245e5c745 217 MCGOUTClock = CPU_XTAL_CLK_HZ;
mbed_official 363:12a245e5c745 218 } else {
mbed_official 363:12a245e5c745 219 /* Reserved value */
mbed_official 363:12a245e5c745 220 return;
mbed_official 363:12a245e5c745 221 } /* (!((MCG->S & MCG_S_CLKST_MASK) == 0x08U)) */
mbed_official 363:12a245e5c745 222 SystemCoreClock = (MCGOUTClock / (0x01U + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
mbed_official 363:12a245e5c745 223
mbed_official 363:12a245e5c745 224 }