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targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_spi.c@380:510f0c3515e3, 2014-11-03 (annotated)

Committer:: mbed_official
Date:: Mon Nov 03 10:15:07 2014 +0000
Revision:: 380:510f0c3515e3
Parent:: targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_spi.c@369:2e96f1b71984
Child:: 532:fe11edbda85c

Synchronized with git revision 417f470ba9f4882d7079611cbc576afd9c49b0ef

Full URL: https://github.com/mbedmicro/mbed/commit/417f470ba9f4882d7079611cbc576afd9c49b0ef/

Targets: Factorisation of NUCLEO_F401RE and F411RE cmsis folders

Who changed what in which revision?

User	Revision	Line number	New contents of line
mbed_official	87:085cde657901	1	/**
mbed_official	87:085cde657901	2	******************************************************************************
mbed_official	87:085cde657901	3	* @file stm32f4xx_hal_spi.c
mbed_official	87:085cde657901	4	* @author MCD Application Team
mbed_official	369:2e96f1b71984	5	* @version V1.1.0
mbed_official	369:2e96f1b71984	6	* @date 19-June-2014
mbed_official	87:085cde657901	7	* @brief SPI HAL module driver.
mbed_official	87:085cde657901	8	*
mbed_official	87:085cde657901	9	* This file provides firmware functions to manage the following
mbed_official	87:085cde657901	10	* functionalities of the Serial Peripheral Interface (SPI) peripheral:
mbed_official	87:085cde657901	11	* + Initialization and de-initialization functions
mbed_official	87:085cde657901	12	* + IO operation functions
mbed_official	87:085cde657901	13	* + Peripheral Control functions
mbed_official	87:085cde657901	14	* + Peripheral State functions
mbed_official	87:085cde657901	15	@verbatim
mbed_official	87:085cde657901	16	==============================================================================
mbed_official	87:085cde657901	17	##### How to use this driver #####
mbed_official	87:085cde657901	18	==============================================================================
mbed_official	87:085cde657901	19	[..]
mbed_official	87:085cde657901	20	The SPI HAL driver can be used as follows:
mbed_official	87:085cde657901	21
mbed_official	87:085cde657901	22	(#) Declare a SPI_HandleTypeDef handle structure, for example:
mbed_official	87:085cde657901	23	SPI_HandleTypeDef hspi;
mbed_official	87:085cde657901	24
mbed_official	226:b062af740e40	25	(#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit ()API:
mbed_official	87:085cde657901	26	(##) Enable the SPIx interface clock
mbed_official	87:085cde657901	27	(##) SPI pins configuration
mbed_official	87:085cde657901	28	(+++) Enable the clock for the SPI GPIOs
mbed_official	87:085cde657901	29	(+++) Configure these SPI pins as alternate function push-pull
mbed_official	87:085cde657901	30	(##) NVIC configuration if you need to use interrupt process
mbed_official	87:085cde657901	31	(+++) Configure the SPIx interrupt priority
mbed_official	87:085cde657901	32	(+++) Enable the NVIC SPI IRQ handle
mbed_official	87:085cde657901	33	(##) DMA Configuration if you need to use DMA process
mbed_official	87:085cde657901	34	(+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive stream
mbed_official	87:085cde657901	35	(+++) Enable the DMAx interface clock using
mbed_official	87:085cde657901	36	(+++) Configure the DMA handle parameters
mbed_official	87:085cde657901	37	(+++) Configure the DMA Tx or Rx Stream
mbed_official	87:085cde657901	38	(+++) Associate the initilalized hdma_tx handle to the hspi DMA Tx or Rx handle
mbed_official	87:085cde657901	39	(+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream
mbed_official	87:085cde657901	40
mbed_official	87:085cde657901	41	(#) Program the Mode, Direction , Data size, Baudrate Prescaler, NSS
mbed_official	87:085cde657901	42	management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.
mbed_official	87:085cde657901	43
mbed_official	87:085cde657901	44	(#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
mbed_official	87:085cde657901	45	(++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
mbed_official	226:b062af740e40	46	by calling the customed HAL_SPI_MspInit() API.
mbed_official	369:2e96f1b71984	47	[..]
mbed_official	369:2e96f1b71984	48	Circular mode restriction:
mbed_official	369:2e96f1b71984	49	(#) The DMA circular mode cannot be used when the SPI is configured in these modes:
mbed_official	369:2e96f1b71984	50	(##) Master 2Lines RxOnly
mbed_official	369:2e96f1b71984	51	(##) Master 1Line Rx
mbed_official	369:2e96f1b71984	52	(#) The CRC feature is not managed when the DMA circular mode is enabled
mbed_official	369:2e96f1b71984	53	(#) When the SPI DMA Pause/Stop features are used, we must use the following APIs
mbed_official	369:2e96f1b71984	54	the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks
mbed_official	369:2e96f1b71984	55
mbed_official	369:2e96f1b71984	56
mbed_official	87:085cde657901	57
mbed_official	87:085cde657901	58	@endverbatim
mbed_official	87:085cde657901	59	******************************************************************************
mbed_official	87:085cde657901	60	* @attention
mbed_official	87:085cde657901	61	*
mbed_official	87:085cde657901	62	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
mbed_official	87:085cde657901	63	*
mbed_official	87:085cde657901	64	* Redistribution and use in source and binary forms, with or without modification,
mbed_official	87:085cde657901	65	* are permitted provided that the following conditions are met:
mbed_official	87:085cde657901	66	* 1. Redistributions of source code must retain the above copyright notice,
mbed_official	87:085cde657901	67	* this list of conditions and the following disclaimer.
mbed_official	87:085cde657901	68	* 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official	87:085cde657901	69	* this list of conditions and the following disclaimer in the documentation
mbed_official	87:085cde657901	70	* and/or other materials provided with the distribution.
mbed_official	87:085cde657901	71	* 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official	87:085cde657901	72	* may be used to endorse or promote products derived from this software
mbed_official	87:085cde657901	73	* without specific prior written permission.
mbed_official	87:085cde657901	74	*
mbed_official	87:085cde657901	75	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official	87:085cde657901	76	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official	87:085cde657901	77	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official	87:085cde657901	78	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official	87:085cde657901	79	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official	87:085cde657901	80	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official	87:085cde657901	81	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official	87:085cde657901	82	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official	87:085cde657901	83	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official	87:085cde657901	84	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official	87:085cde657901	85	*
mbed_official	87:085cde657901	86	******************************************************************************
mbed_official	87:085cde657901	87	*/
mbed_official	87:085cde657901	88
mbed_official	87:085cde657901	89	/* Includes ------------------------------------------------------------------*/
mbed_official	87:085cde657901	90	#include "stm32f4xx_hal.h"
mbed_official	87:085cde657901	91
mbed_official	87:085cde657901	92	/** @addtogroup STM32F4xx_HAL_Driver
mbed_official	87:085cde657901	93	* @{
mbed_official	87:085cde657901	94	*/
mbed_official	87:085cde657901	95
mbed_official	87:085cde657901	96	/** @defgroup SPI
mbed_official	87:085cde657901	97	* @brief SPI HAL module driver
mbed_official	87:085cde657901	98	* @{
mbed_official	87:085cde657901	99	*/
mbed_official	87:085cde657901	100
mbed_official	87:085cde657901	101	#ifdef HAL_SPI_MODULE_ENABLED
mbed_official	87:085cde657901	102
mbed_official	87:085cde657901	103	/* Private typedef -----------------------------------------------------------*/
mbed_official	87:085cde657901	104	/* Private define ------------------------------------------------------------*/
mbed_official	87:085cde657901	105	#define SPI_TIMEOUT_VALUE 10
mbed_official	87:085cde657901	106	/* Private macro -------------------------------------------------------------*/
mbed_official	87:085cde657901	107	/* Private variables ---------------------------------------------------------*/
mbed_official	87:085cde657901	108	/* Private function prototypes -----------------------------------------------*/
mbed_official	87:085cde657901	109	static void SPI_TxCloseIRQHandler(SPI_HandleTypeDef *hspi);
mbed_official	87:085cde657901	110	static void SPI_TxISR(SPI_HandleTypeDef *hspi);
mbed_official	106:ced8cbb51063	111	static void SPI_RxCloseIRQHandler(SPI_HandleTypeDef *hspi);
mbed_official	87:085cde657901	112	static void SPI_2LinesRxISR(SPI_HandleTypeDef *hspi);
mbed_official	87:085cde657901	113	static void SPI_RxISR(SPI_HandleTypeDef *hspi);
mbed_official	87:085cde657901	114	static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
mbed_official	87:085cde657901	115	static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
mbed_official	87:085cde657901	116	static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);
mbed_official	369:2e96f1b71984	117	static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma);
mbed_official	369:2e96f1b71984	118	static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma);
mbed_official	369:2e96f1b71984	119	static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma);
mbed_official	87:085cde657901	120	static void SPI_DMAError(DMA_HandleTypeDef *hdma);
mbed_official	87:085cde657901	121	static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
mbed_official	87:085cde657901	122
mbed_official	87:085cde657901	123	/* Private functions ---------------------------------------------------------*/
mbed_official	87:085cde657901	124
mbed_official	87:085cde657901	125	/** @defgroup SPI_Private_Functions
mbed_official	87:085cde657901	126	* @{
mbed_official	87:085cde657901	127	*/
mbed_official	87:085cde657901	128
mbed_official	87:085cde657901	129	/** @defgroup SPI_Group1 Initialization and de-initialization functions
mbed_official	87:085cde657901	130	* @brief Initialization and Configuration functions
mbed_official	87:085cde657901	131	*
mbed_official	87:085cde657901	132	@verbatim
mbed_official	87:085cde657901	133	===============================================================================
mbed_official	87:085cde657901	134	##### Initialization and de-initialization functions #####
mbed_official	87:085cde657901	135	===============================================================================
mbed_official	87:085cde657901	136	[..] This subsection provides a set of functions allowing to initialize and
mbed_official	87:085cde657901	137	de-initialiaze the SPIx peripheral:
mbed_official	87:085cde657901	138
mbed_official	226:b062af740e40	139	(+) User must implement HAL_SPI_MspInit() function in which he configures
mbed_official	87:085cde657901	140	all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
mbed_official	87:085cde657901	141
mbed_official	87:085cde657901	142	(+) Call the function HAL_SPI_Init() to configure the selected device with
mbed_official	87:085cde657901	143	the selected configuration:
mbed_official	87:085cde657901	144	(++) Mode
mbed_official	87:085cde657901	145	(++) Direction
mbed_official	87:085cde657901	146	(++) Data Size
mbed_official	87:085cde657901	147	(++) Clock Polarity and Phase
mbed_official	87:085cde657901	148	(++) NSS Management
mbed_official	87:085cde657901	149	(++) BaudRate Prescaler
mbed_official	87:085cde657901	150	(++) FirstBit
mbed_official	87:085cde657901	151	(++) TIMode
mbed_official	87:085cde657901	152	(++) CRC Calculation
mbed_official	87:085cde657901	153	(++) CRC Polynomial if CRC enabled
mbed_official	87:085cde657901	154
mbed_official	87:085cde657901	155	(+) Call the function HAL_SPI_DeInit() to restore the default configuration
mbed_official	87:085cde657901	156	of the selected SPIx periperal.
mbed_official	87:085cde657901	157
mbed_official	87:085cde657901	158	@endverbatim
mbed_official	87:085cde657901	159	* @{
mbed_official	87:085cde657901	160	*/
mbed_official	87:085cde657901	161
mbed_official	87:085cde657901	162	/**
mbed_official	87:085cde657901	163	* @brief Initializes the SPI according to the specified parameters
mbed_official	87:085cde657901	164	* in the SPI_InitTypeDef and create the associated handle.
mbed_official	226:b062af740e40	165	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	166	* the configuration information for SPI module.
mbed_official	87:085cde657901	167	* @retval HAL status
mbed_official	87:085cde657901	168	*/
mbed_official	87:085cde657901	169	HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
mbed_official	87:085cde657901	170	{
mbed_official	87:085cde657901	171	/* Check the SPI handle allocation */
mbed_official	369:2e96f1b71984	172	if(hspi == HAL_NULL)
mbed_official	87:085cde657901	173	{
mbed_official	87:085cde657901	174	return HAL_ERROR;
mbed_official	87:085cde657901	175	}
mbed_official	87:085cde657901	176
mbed_official	87:085cde657901	177	/* Check the parameters */
mbed_official	87:085cde657901	178	assert_param(IS_SPI_MODE(hspi->Init.Mode));
mbed_official	87:085cde657901	179	assert_param(IS_SPI_DIRECTION_MODE(hspi->Init.Direction));
mbed_official	87:085cde657901	180	assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
mbed_official	87:085cde657901	181	assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
mbed_official	87:085cde657901	182	assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
mbed_official	87:085cde657901	183	assert_param(IS_SPI_NSS(hspi->Init.NSS));
mbed_official	87:085cde657901	184	assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
mbed_official	87:085cde657901	185	assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
mbed_official	87:085cde657901	186	assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
mbed_official	87:085cde657901	187	assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
mbed_official	87:085cde657901	188	assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
mbed_official	87:085cde657901	189
mbed_official	87:085cde657901	190	if(hspi->State == HAL_SPI_STATE_RESET)
mbed_official	87:085cde657901	191	{
mbed_official	87:085cde657901	192	/* Init the low level hardware : GPIO, CLOCK, NVIC... */
mbed_official	87:085cde657901	193	HAL_SPI_MspInit(hspi);
mbed_official	87:085cde657901	194	}
mbed_official	87:085cde657901	195
mbed_official	87:085cde657901	196	hspi->State = HAL_SPI_STATE_BUSY;
mbed_official	87:085cde657901	197
mbed_official	87:085cde657901	198	/* Disble the selected SPI peripheral */
mbed_official	87:085cde657901	199	__HAL_SPI_DISABLE(hspi);
mbed_official	87:085cde657901	200
mbed_official	87:085cde657901	201	/----------------------- SPIx CR1 & CR2 Configuration ---------------------/
mbed_official	87:085cde657901	202	/* Configure : SPI Mode, Communication Mode, Data size, Clock polarity and phase, NSS management,
mbed_official	87:085cde657901	203	Communication speed, First bit and CRC calculation state */
mbed_official	87:085cde657901	204	hspi->Instance->CR1 = (hspi->Init.Mode \| hspi->Init.Direction \| hspi->Init.DataSize \|
mbed_official	87:085cde657901	205	hspi->Init.CLKPolarity \| hspi->Init.CLKPhase \| (hspi->Init.NSS & SPI_CR1_SSM) \|
mbed_official	87:085cde657901	206	hspi->Init.BaudRatePrescaler \| hspi->Init.FirstBit \| hspi->Init.CRCCalculation);
mbed_official	87:085cde657901	207
mbed_official	87:085cde657901	208	/* Configure : NSS management */
mbed_official	87:085cde657901	209	hspi->Instance->CR2 = (((hspi->Init.NSS >> 16) & SPI_CR2_SSOE) \| hspi->Init.TIMode);
mbed_official	87:085cde657901	210
mbed_official	87:085cde657901	211	/---------------------------- SPIx CRCPOLY Configuration ------------------/
mbed_official	87:085cde657901	212	/* Configure : CRC Polynomial */
mbed_official	87:085cde657901	213	hspi->Instance->CRCPR = hspi->Init.CRCPolynomial;
mbed_official	87:085cde657901	214
mbed_official	87:085cde657901	215	/* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
mbed_official	87:085cde657901	216	hspi->Instance->I2SCFGR &= (uint32_t)(~SPI_I2SCFGR_I2SMOD);
mbed_official	87:085cde657901	217
mbed_official	87:085cde657901	218	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official	87:085cde657901	219	hspi->State = HAL_SPI_STATE_READY;
mbed_official	87:085cde657901	220
mbed_official	87:085cde657901	221	return HAL_OK;
mbed_official	87:085cde657901	222	}
mbed_official	87:085cde657901	223
mbed_official	87:085cde657901	224	/**
mbed_official	87:085cde657901	225	* @brief DeInitializes the SPI peripheral
mbed_official	226:b062af740e40	226	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	227	* the configuration information for SPI module.
mbed_official	87:085cde657901	228	* @retval HAL status
mbed_official	87:085cde657901	229	*/
mbed_official	87:085cde657901	230	HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
mbed_official	87:085cde657901	231	{
mbed_official	87:085cde657901	232	/* Check the SPI handle allocation */
mbed_official	369:2e96f1b71984	233	if(hspi == HAL_NULL)
mbed_official	87:085cde657901	234	{
mbed_official	87:085cde657901	235	return HAL_ERROR;
mbed_official	87:085cde657901	236	}
mbed_official	87:085cde657901	237
mbed_official	87:085cde657901	238	/* Disable the SPI Peripheral Clock */
mbed_official	87:085cde657901	239	__HAL_SPI_DISABLE(hspi);
mbed_official	87:085cde657901	240
mbed_official	87:085cde657901	241	/* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
mbed_official	87:085cde657901	242	HAL_SPI_MspDeInit(hspi);
mbed_official	87:085cde657901	243
mbed_official	87:085cde657901	244	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official	87:085cde657901	245	hspi->State = HAL_SPI_STATE_RESET;
mbed_official	87:085cde657901	246
mbed_official	106:ced8cbb51063	247	/* Release Lock */
mbed_official	106:ced8cbb51063	248	__HAL_UNLOCK(hspi);
mbed_official	106:ced8cbb51063	249
mbed_official	87:085cde657901	250	return HAL_OK;
mbed_official	87:085cde657901	251	}
mbed_official	87:085cde657901	252
mbed_official	87:085cde657901	253	/**
mbed_official	87:085cde657901	254	* @brief SPI MSP Init
mbed_official	226:b062af740e40	255	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	256	* the configuration information for SPI module.
mbed_official	87:085cde657901	257	* @retval None
mbed_official	87:085cde657901	258	*/
mbed_official	87:085cde657901	259	__weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
mbed_official	87:085cde657901	260	{
mbed_official	87:085cde657901	261	/* NOTE : This function Should not be modified, when the callback is needed,
mbed_official	87:085cde657901	262	the HAL_SPI_MspInit could be implenetd in the user file
mbed_official	87:085cde657901	263	*/
mbed_official	87:085cde657901	264	}
mbed_official	87:085cde657901	265
mbed_official	87:085cde657901	266	/**
mbed_official	87:085cde657901	267	* @brief SPI MSP DeInit
mbed_official	226:b062af740e40	268	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	269	* the configuration information for SPI module.
mbed_official	87:085cde657901	270	* @retval None
mbed_official	87:085cde657901	271	*/
mbed_official	87:085cde657901	272	__weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
mbed_official	87:085cde657901	273	{
mbed_official	87:085cde657901	274	/* NOTE : This function Should not be modified, when the callback is needed,
mbed_official	87:085cde657901	275	the HAL_SPI_MspDeInit could be implenetd in the user file
mbed_official	87:085cde657901	276	*/
mbed_official	87:085cde657901	277	}
mbed_official	87:085cde657901	278
mbed_official	87:085cde657901	279	/**
mbed_official	87:085cde657901	280	* @}
mbed_official	87:085cde657901	281	*/
mbed_official	87:085cde657901	282
mbed_official	87:085cde657901	283	/** @defgroup SPI_Group2 IO operation functions
mbed_official	87:085cde657901	284	* @brief Data transfers functions
mbed_official	87:085cde657901	285	*
mbed_official	87:085cde657901	286	@verbatim
mbed_official	87:085cde657901	287	==============================================================================
mbed_official	87:085cde657901	288	##### IO operation functions #####
mbed_official	87:085cde657901	289	===============================================================================
mbed_official	87:085cde657901	290	This subsection provides a set of functions allowing to manage the SPI
mbed_official	87:085cde657901	291	data transfers.
mbed_official	87:085cde657901	292
mbed_official	87:085cde657901	293	[..] The SPI supports master and slave mode :
mbed_official	87:085cde657901	294
mbed_official	226:b062af740e40	295	(#) There are two modes of transfer:
mbed_official	87:085cde657901	296	(++) Blocking mode: The communication is performed in polling mode.
mbed_official	87:085cde657901	297	The HAL status of all data processing is returned by the same function
mbed_official	87:085cde657901	298	after finishing transfer.
mbed_official	87:085cde657901	299	(++) No-Blocking mode: The communication is performed using Interrupts
mbed_official	226:b062af740e40	300	or DMA, These APIs return the HAL status.
mbed_official	87:085cde657901	301	The end of the data processing will be indicated through the
mbed_official	87:085cde657901	302	dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
mbed_official	87:085cde657901	303	using DMA mode.
mbed_official	87:085cde657901	304	The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
mbed_official	87:085cde657901	305	will be executed respectivelly at the end of the transmit or Receive process
mbed_official	87:085cde657901	306	The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected
mbed_official	87:085cde657901	307
mbed_official	226:b062af740e40	308	(#) Blocking mode APIs are :
mbed_official	87:085cde657901	309	(++) HAL_SPI_Transmit()in 1Line (simplex) and 2Lines (full duplex) mode
mbed_official	87:085cde657901	310	(++) HAL_SPI_Receive() in 1Line (simplex) and 2Lines (full duplex) mode
mbed_official	87:085cde657901	311	(++) HAL_SPI_TransmitReceive() in full duplex mode
mbed_official	87:085cde657901	312
mbed_official	226:b062af740e40	313	(#) Non Blocking mode API's with Interrupt are :
mbed_official	87:085cde657901	314	(++) HAL_SPI_Transmit_IT()in 1Line (simplex) and 2Lines (full duplex) mode
mbed_official	87:085cde657901	315	(++) HAL_SPI_Receive_IT() in 1Line (simplex) and 2Lines (full duplex) mode
mbed_official	87:085cde657901	316	(++) HAL_SPI_TransmitReceive_IT()in full duplex mode
mbed_official	87:085cde657901	317	(++) HAL_SPI_IRQHandler()
mbed_official	87:085cde657901	318
mbed_official	226:b062af740e40	319	(#) Non Blocking mode functions with DMA are :
mbed_official	87:085cde657901	320	(++) HAL_SPI_Transmit_DMA()in 1Line (simplex) and 2Lines (full duplex) mode
mbed_official	87:085cde657901	321	(++) HAL_SPI_Receive_DMA() in 1Line (simplex) and 2Lines (full duplex) mode
mbed_official	87:085cde657901	322	(++) HAL_SPI_TransmitReceie_DMA() in full duplex mode
mbed_official	87:085cde657901	323
mbed_official	226:b062af740e40	324	(#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
mbed_official	87:085cde657901	325	(++) HAL_SPI_TxCpltCallback()
mbed_official	87:085cde657901	326	(++) HAL_SPI_RxCpltCallback()
mbed_official	87:085cde657901	327	(++) HAL_SPI_ErrorCallback()
mbed_official	87:085cde657901	328	(++) HAL_SPI_TxRxCpltCallback()
mbed_official	87:085cde657901	329
mbed_official	87:085cde657901	330	@endverbatim
mbed_official	87:085cde657901	331	* @{
mbed_official	87:085cde657901	332	*/
mbed_official	87:085cde657901	333
mbed_official	87:085cde657901	334	/**
mbed_official	87:085cde657901	335	* @brief Transmit an amount of data in blocking mode
mbed_official	226:b062af740e40	336	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	337	* the configuration information for SPI module.
mbed_official	87:085cde657901	338	* @param pData: pointer to data buffer
mbed_official	87:085cde657901	339	* @param Size: amount of data to be sent
mbed_official	87:085cde657901	340	* @param Timeout: Timeout duration
mbed_official	87:085cde657901	341	* @retval HAL status
mbed_official	87:085cde657901	342	*/
mbed_official	87:085cde657901	343	HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size, uint32_t Timeout)
mbed_official	87:085cde657901	344	{
mbed_official	87:085cde657901	345
mbed_official	87:085cde657901	346	if(hspi->State == HAL_SPI_STATE_READY)
mbed_official	87:085cde657901	347	{
mbed_official	369:2e96f1b71984	348	if((pData == HAL_NULL ) \|\| (Size == 0))
mbed_official	87:085cde657901	349	{
mbed_official	87:085cde657901	350	return HAL_ERROR;
mbed_official	87:085cde657901	351	}
mbed_official	87:085cde657901	352
mbed_official	87:085cde657901	353	/* Check the parameters */
mbed_official	87:085cde657901	354	assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
mbed_official	87:085cde657901	355
mbed_official	87:085cde657901	356	/* Process Locked */
mbed_official	87:085cde657901	357	__HAL_LOCK(hspi);
mbed_official	87:085cde657901	358
mbed_official	87:085cde657901	359	/* Configure communication */
mbed_official	87:085cde657901	360	hspi->State = HAL_SPI_STATE_BUSY_TX;
mbed_official	87:085cde657901	361	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official	87:085cde657901	362
mbed_official	87:085cde657901	363	hspi->pTxBuffPtr = pData;
mbed_official	87:085cde657901	364	hspi->TxXferSize = Size;
mbed_official	87:085cde657901	365	hspi->TxXferCount = Size;
mbed_official	87:085cde657901	366
mbed_official	87:085cde657901	367	/Init field not used in handle to zero /
mbed_official	87:085cde657901	368	hspi->TxISR = 0;
mbed_official	87:085cde657901	369	hspi->RxISR = 0;
mbed_official	87:085cde657901	370	hspi->RxXferSize = 0;
mbed_official	87:085cde657901	371	hspi->RxXferCount = 0;
mbed_official	87:085cde657901	372
mbed_official	87:085cde657901	373	/* Reset CRC Calculation */
mbed_official	87:085cde657901	374	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	87:085cde657901	375	{
mbed_official	87:085cde657901	376	__HAL_SPI_RESET_CRC(hspi);
mbed_official	87:085cde657901	377	}
mbed_official	87:085cde657901	378
mbed_official	87:085cde657901	379	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
mbed_official	87:085cde657901	380	{
mbed_official	87:085cde657901	381	/* Configure communication direction : 1Line */
mbed_official	87:085cde657901	382	__HAL_SPI_1LINE_TX(hspi);
mbed_official	87:085cde657901	383	}
mbed_official	87:085cde657901	384
mbed_official	87:085cde657901	385	/* Check if the SPI is already enabled */
mbed_official	87:085cde657901	386	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official	87:085cde657901	387	{
mbed_official	87:085cde657901	388	/* Enable SPI peripheral */
mbed_official	87:085cde657901	389	__HAL_SPI_ENABLE(hspi);
mbed_official	87:085cde657901	390	}
mbed_official	87:085cde657901	391
mbed_official	87:085cde657901	392	/* Transmit data in 8 Bit mode */
mbed_official	87:085cde657901	393	if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
mbed_official	87:085cde657901	394	{
mbed_official	369:2e96f1b71984	395	if((hspi->Init.Mode == SPI_MODE_SLAVE)\|\| (hspi->TxXferCount == 0x01))
mbed_official	369:2e96f1b71984	396	{
mbed_official	369:2e96f1b71984	397	hspi->Instance->DR = (*hspi->pTxBuffPtr++);
mbed_official	369:2e96f1b71984	398	hspi->TxXferCount--;
mbed_official	369:2e96f1b71984	399	}
mbed_official	87:085cde657901	400	while(hspi->TxXferCount > 0)
mbed_official	87:085cde657901	401	{
mbed_official	87:085cde657901	402	/* Wait until TXE flag is set to send data */
mbed_official	87:085cde657901	403	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
mbed_official	87:085cde657901	404	{
mbed_official	87:085cde657901	405	return HAL_TIMEOUT;
mbed_official	87:085cde657901	406	}
mbed_official	87:085cde657901	407	hspi->Instance->DR = (*hspi->pTxBuffPtr++);
mbed_official	87:085cde657901	408	hspi->TxXferCount--;
mbed_official	87:085cde657901	409	}
mbed_official	87:085cde657901	410	/* Enable CRC Transmission */
mbed_official	87:085cde657901	411	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	87:085cde657901	412	{
mbed_official	87:085cde657901	413	hspi->Instance->CR1 \|= SPI_CR1_CRCNEXT;
mbed_official	87:085cde657901	414	}
mbed_official	87:085cde657901	415	}
mbed_official	87:085cde657901	416	/* Transmit data in 16 Bit mode */
mbed_official	87:085cde657901	417	else
mbed_official	87:085cde657901	418	{
mbed_official	369:2e96f1b71984	419	if((hspi->Init.Mode == SPI_MODE_SLAVE) \|\| (hspi->TxXferCount == 0x01))
mbed_official	369:2e96f1b71984	420	{
mbed_official	369:2e96f1b71984	421	hspi->Instance->DR = ((uint16_t)hspi->pTxBuffPtr);
mbed_official	369:2e96f1b71984	422	hspi->pTxBuffPtr+=2;
mbed_official	369:2e96f1b71984	423	hspi->TxXferCount--;
mbed_official	369:2e96f1b71984	424	}
mbed_official	87:085cde657901	425	while(hspi->TxXferCount > 0)
mbed_official	87:085cde657901	426	{
mbed_official	87:085cde657901	427	/* Wait until TXE flag is set to send data */
mbed_official	87:085cde657901	428	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
mbed_official	87:085cde657901	429	{
mbed_official	87:085cde657901	430	return HAL_TIMEOUT;
mbed_official	87:085cde657901	431	}
mbed_official	87:085cde657901	432	hspi->Instance->DR = ((uint16_t)hspi->pTxBuffPtr);
mbed_official	87:085cde657901	433	hspi->pTxBuffPtr+=2;
mbed_official	87:085cde657901	434	hspi->TxXferCount--;
mbed_official	87:085cde657901	435	}
mbed_official	87:085cde657901	436	/* Enable CRC Transmission */
mbed_official	87:085cde657901	437	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	87:085cde657901	438	{
mbed_official	87:085cde657901	439	hspi->Instance->CR1 \|= SPI_CR1_CRCNEXT;
mbed_official	87:085cde657901	440	}
mbed_official	87:085cde657901	441	}
mbed_official	87:085cde657901	442
mbed_official	87:085cde657901	443	/* Wait until TXE flag is set to send data */
mbed_official	87:085cde657901	444	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
mbed_official	87:085cde657901	445	{
mbed_official	87:085cde657901	446	hspi->ErrorCode \|= HAL_SPI_ERROR_FLAG;
mbed_official	87:085cde657901	447	return HAL_TIMEOUT;
mbed_official	87:085cde657901	448	}
mbed_official	87:085cde657901	449
mbed_official	87:085cde657901	450	/* Wait until Busy flag is reset before disabling SPI */
mbed_official	87:085cde657901	451	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, Timeout) != HAL_OK)
mbed_official	87:085cde657901	452	{
mbed_official	87:085cde657901	453	hspi->ErrorCode \|= HAL_SPI_ERROR_FLAG;
mbed_official	87:085cde657901	454	return HAL_TIMEOUT;
mbed_official	87:085cde657901	455	}
mbed_official	87:085cde657901	456
mbed_official	87:085cde657901	457	/* Clear OVERUN flag in 2 Lines communication mode because received is not read */
mbed_official	87:085cde657901	458	if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
mbed_official	87:085cde657901	459	{
mbed_official	87:085cde657901	460	__HAL_SPI_CLEAR_OVRFLAG(hspi);
mbed_official	87:085cde657901	461	}
mbed_official	87:085cde657901	462
mbed_official	87:085cde657901	463	hspi->State = HAL_SPI_STATE_READY;
mbed_official	87:085cde657901	464
mbed_official	87:085cde657901	465	/* Process Unlocked */
mbed_official	87:085cde657901	466	__HAL_UNLOCK(hspi);
mbed_official	87:085cde657901	467
mbed_official	87:085cde657901	468	return HAL_OK;
mbed_official	87:085cde657901	469	}
mbed_official	87:085cde657901	470	else
mbed_official	87:085cde657901	471	{
mbed_official	87:085cde657901	472	return HAL_BUSY;
mbed_official	87:085cde657901	473	}
mbed_official	87:085cde657901	474	}
mbed_official	87:085cde657901	475
mbed_official	87:085cde657901	476	/**
mbed_official	87:085cde657901	477	* @brief Receive an amount of data in blocking mode
mbed_official	226:b062af740e40	478	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	479	* the configuration information for SPI module.
mbed_official	87:085cde657901	480	* @param pData: pointer to data buffer
mbed_official	87:085cde657901	481	* @param Size: amount of data to be sent
mbed_official	87:085cde657901	482	* @param Timeout: Timeout duration
mbed_official	87:085cde657901	483	* @retval HAL status
mbed_official	87:085cde657901	484	*/
mbed_official	87:085cde657901	485	HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size, uint32_t Timeout)
mbed_official	87:085cde657901	486	{
mbed_official	87:085cde657901	487	__IO uint16_t tmpreg;
mbed_official	87:085cde657901	488	uint32_t tmp = 0;
mbed_official	87:085cde657901	489
mbed_official	87:085cde657901	490	if(hspi->State == HAL_SPI_STATE_READY)
mbed_official	87:085cde657901	491	{
mbed_official	369:2e96f1b71984	492	if((pData == HAL_NULL ) \|\| (Size == 0))
mbed_official	87:085cde657901	493	{
mbed_official	87:085cde657901	494	return HAL_ERROR;
mbed_official	87:085cde657901	495	}
mbed_official	87:085cde657901	496
mbed_official	87:085cde657901	497	/* Process Locked */
mbed_official	87:085cde657901	498	__HAL_LOCK(hspi);
mbed_official	87:085cde657901	499
mbed_official	87:085cde657901	500	/* Configure communication */
mbed_official	87:085cde657901	501	hspi->State = HAL_SPI_STATE_BUSY_RX;
mbed_official	87:085cde657901	502	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official	87:085cde657901	503
mbed_official	87:085cde657901	504	hspi->pRxBuffPtr = pData;
mbed_official	87:085cde657901	505	hspi->RxXferSize = Size;
mbed_official	87:085cde657901	506	hspi->RxXferCount = Size;
mbed_official	87:085cde657901	507
mbed_official	87:085cde657901	508	/Init field not used in handle to zero /
mbed_official	87:085cde657901	509	hspi->RxISR = 0;
mbed_official	87:085cde657901	510	hspi->TxISR = 0;
mbed_official	87:085cde657901	511	hspi->TxXferSize = 0;
mbed_official	87:085cde657901	512	hspi->TxXferCount = 0;
mbed_official	87:085cde657901	513
mbed_official	87:085cde657901	514	/* Configure communication direction : 1Line */
mbed_official	87:085cde657901	515	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
mbed_official	87:085cde657901	516	{
mbed_official	87:085cde657901	517	__HAL_SPI_1LINE_RX(hspi);
mbed_official	87:085cde657901	518	}
mbed_official	87:085cde657901	519
mbed_official	87:085cde657901	520	/* Reset CRC Calculation */
mbed_official	87:085cde657901	521	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	87:085cde657901	522	{
mbed_official	87:085cde657901	523	__HAL_SPI_RESET_CRC(hspi);
mbed_official	87:085cde657901	524	}
mbed_official	87:085cde657901	525
mbed_official	87:085cde657901	526	if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
mbed_official	87:085cde657901	527	{
mbed_official	87:085cde657901	528	/* Process Unlocked */
mbed_official	87:085cde657901	529	__HAL_UNLOCK(hspi);
mbed_official	87:085cde657901	530
mbed_official	87:085cde657901	531	/* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
mbed_official	87:085cde657901	532	return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout);
mbed_official	87:085cde657901	533	}
mbed_official	87:085cde657901	534
mbed_official	87:085cde657901	535	/* Check if the SPI is already enabled */
mbed_official	87:085cde657901	536	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official	87:085cde657901	537	{
mbed_official	87:085cde657901	538	/* Enable SPI peripheral */
mbed_official	87:085cde657901	539	__HAL_SPI_ENABLE(hspi);
mbed_official	87:085cde657901	540	}
mbed_official	87:085cde657901	541
mbed_official	87:085cde657901	542	/* Receive data in 8 Bit mode */
mbed_official	87:085cde657901	543	if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
mbed_official	87:085cde657901	544	{
mbed_official	87:085cde657901	545	while(hspi->RxXferCount > 1)
mbed_official	87:085cde657901	546	{
mbed_official	87:085cde657901	547	/* Wait until RXNE flag is set */
mbed_official	87:085cde657901	548	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
mbed_official	87:085cde657901	549	{
mbed_official	87:085cde657901	550	return HAL_TIMEOUT;
mbed_official	87:085cde657901	551	}
mbed_official	87:085cde657901	552
mbed_official	87:085cde657901	553	(*hspi->pRxBuffPtr++) = hspi->Instance->DR;
mbed_official	87:085cde657901	554	hspi->RxXferCount--;
mbed_official	87:085cde657901	555	}
mbed_official	87:085cde657901	556	/* Enable CRC Transmission */
mbed_official	87:085cde657901	557	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	87:085cde657901	558	{
mbed_official	87:085cde657901	559	hspi->Instance->CR1 \|= SPI_CR1_CRCNEXT;
mbed_official	87:085cde657901	560	}
mbed_official	87:085cde657901	561	}
mbed_official	87:085cde657901	562	/* Receive data in 16 Bit mode */
mbed_official	87:085cde657901	563	else
mbed_official	87:085cde657901	564	{
mbed_official	87:085cde657901	565	while(hspi->RxXferCount > 1)
mbed_official	87:085cde657901	566	{
mbed_official	87:085cde657901	567	/* Wait until RXNE flag is set to read data */
mbed_official	87:085cde657901	568	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
mbed_official	87:085cde657901	569	{
mbed_official	87:085cde657901	570	return HAL_TIMEOUT;
mbed_official	87:085cde657901	571	}
mbed_official	87:085cde657901	572
mbed_official	87:085cde657901	573	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
mbed_official	87:085cde657901	574	hspi->pRxBuffPtr+=2;
mbed_official	87:085cde657901	575	hspi->RxXferCount--;
mbed_official	87:085cde657901	576	}
mbed_official	87:085cde657901	577	/* Enable CRC Transmission */
mbed_official	87:085cde657901	578	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	87:085cde657901	579	{
mbed_official	87:085cde657901	580	hspi->Instance->CR1 \|= SPI_CR1_CRCNEXT;
mbed_official	87:085cde657901	581	}
mbed_official	87:085cde657901	582	}
mbed_official	87:085cde657901	583
mbed_official	87:085cde657901	584	/* Wait until RXNE flag is set */
mbed_official	87:085cde657901	585	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
mbed_official	87:085cde657901	586	{
mbed_official	87:085cde657901	587	return HAL_TIMEOUT;
mbed_official	87:085cde657901	588	}
mbed_official	87:085cde657901	589
mbed_official	87:085cde657901	590	/* Receive last data in 8 Bit mode */
mbed_official	87:085cde657901	591	if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
mbed_official	87:085cde657901	592	{
mbed_official	87:085cde657901	593	(*hspi->pRxBuffPtr++) = hspi->Instance->DR;
mbed_official	87:085cde657901	594	}
mbed_official	87:085cde657901	595	/* Receive last data in 16 Bit mode */
mbed_official	87:085cde657901	596	else
mbed_official	87:085cde657901	597	{
mbed_official	87:085cde657901	598	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
mbed_official	87:085cde657901	599	hspi->pRxBuffPtr+=2;
mbed_official	87:085cde657901	600	}
mbed_official	87:085cde657901	601	hspi->RxXferCount--;
mbed_official	87:085cde657901	602
mbed_official	87:085cde657901	603	/* Wait until RXNE flag is set: CRC Received */
mbed_official	87:085cde657901	604	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	87:085cde657901	605	{
mbed_official	87:085cde657901	606	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
mbed_official	87:085cde657901	607	{
mbed_official	87:085cde657901	608	hspi->ErrorCode \|= HAL_SPI_ERROR_CRC;
mbed_official	87:085cde657901	609	return HAL_TIMEOUT;
mbed_official	87:085cde657901	610	}
mbed_official	87:085cde657901	611
mbed_official	87:085cde657901	612	/* Read CRC to Flush RXNE flag */
mbed_official	87:085cde657901	613	tmpreg = hspi->Instance->DR;
mbed_official	87:085cde657901	614	}
mbed_official	87:085cde657901	615
mbed_official	87:085cde657901	616	if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)\|\|(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
mbed_official	87:085cde657901	617	{
mbed_official	87:085cde657901	618	/* Disable SPI peripheral */
mbed_official	87:085cde657901	619	__HAL_SPI_DISABLE(hspi);
mbed_official	87:085cde657901	620	}
mbed_official	87:085cde657901	621
mbed_official	87:085cde657901	622	hspi->State = HAL_SPI_STATE_READY;
mbed_official	87:085cde657901	623
mbed_official	87:085cde657901	624	tmp = __HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR);
mbed_official	87:085cde657901	625	/* Check if CRC error occurred */
mbed_official	87:085cde657901	626	if((hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) && (tmp != RESET))
mbed_official	87:085cde657901	627	{
mbed_official	87:085cde657901	628	hspi->ErrorCode \|= HAL_SPI_ERROR_CRC;
mbed_official	87:085cde657901	629
mbed_official	87:085cde657901	630	/* Reset CRC Calculation */
mbed_official	87:085cde657901	631	__HAL_SPI_RESET_CRC(hspi);
mbed_official	87:085cde657901	632
mbed_official	87:085cde657901	633	/* Process Unlocked */
mbed_official	87:085cde657901	634	__HAL_UNLOCK(hspi);
mbed_official	87:085cde657901	635
mbed_official	87:085cde657901	636	return HAL_ERROR;
mbed_official	87:085cde657901	637	}
mbed_official	87:085cde657901	638
mbed_official	87:085cde657901	639	/* Process Unlocked */
mbed_official	87:085cde657901	640	__HAL_UNLOCK(hspi);
mbed_official	87:085cde657901	641
mbed_official	87:085cde657901	642	return HAL_OK;
mbed_official	87:085cde657901	643	}
mbed_official	87:085cde657901	644	else
mbed_official	87:085cde657901	645	{
mbed_official	87:085cde657901	646	return HAL_BUSY;
mbed_official	87:085cde657901	647	}
mbed_official	87:085cde657901	648	}
mbed_official	87:085cde657901	649
mbed_official	87:085cde657901	650	/**
mbed_official	87:085cde657901	651	* @brief Transmit and Receive an amount of data in blocking mode
mbed_official	226:b062af740e40	652	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	653	* the configuration information for SPI module.
mbed_official	87:085cde657901	654	* @param pTxData: pointer to transmission data buffer
mbed_official	87:085cde657901	655	* @param pRxData: pointer to reception data buffer to be
mbed_official	87:085cde657901	656	* @param Size: amount of data to be sent
mbed_official	87:085cde657901	657	* @param Timeout: Timeout duration
mbed_official	87:085cde657901	658	* @retval HAL status
mbed_official	87:085cde657901	659	*/
mbed_official	87:085cde657901	660	HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef hspi, uint8_t pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
mbed_official	87:085cde657901	661	{
mbed_official	87:085cde657901	662	__IO uint16_t tmpreg;
mbed_official	369:2e96f1b71984	663	uint32_t tmpstate = 0, tmp = 0;
mbed_official	87:085cde657901	664
mbed_official	369:2e96f1b71984	665	tmpstate = hspi->State;
mbed_official	369:2e96f1b71984	666	if((tmpstate == HAL_SPI_STATE_READY) \|\| (tmpstate == HAL_SPI_STATE_BUSY_RX))
mbed_official	87:085cde657901	667	{
mbed_official	369:2e96f1b71984	668	if((pTxData == HAL_NULL ) \|\| (pRxData == HAL_NULL ) \|\| (Size == 0))
mbed_official	87:085cde657901	669	{
mbed_official	87:085cde657901	670	return HAL_ERROR;
mbed_official	87:085cde657901	671	}
mbed_official	87:085cde657901	672
mbed_official	87:085cde657901	673	/* Check the parameters */
mbed_official	87:085cde657901	674	assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
mbed_official	87:085cde657901	675
mbed_official	87:085cde657901	676	/* Process Locked */
mbed_official	87:085cde657901	677	__HAL_LOCK(hspi);
mbed_official	87:085cde657901	678
mbed_official	87:085cde657901	679	/* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
mbed_official	87:085cde657901	680	if(hspi->State == HAL_SPI_STATE_READY)
mbed_official	87:085cde657901	681	{
mbed_official	106:ced8cbb51063	682	hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
mbed_official	87:085cde657901	683	}
mbed_official	87:085cde657901	684
mbed_official	87:085cde657901	685	/* Configure communication */
mbed_official	87:085cde657901	686	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official	87:085cde657901	687
mbed_official	87:085cde657901	688	hspi->pRxBuffPtr = pRxData;
mbed_official	87:085cde657901	689	hspi->RxXferSize = Size;
mbed_official	87:085cde657901	690	hspi->RxXferCount = Size;
mbed_official	87:085cde657901	691
mbed_official	87:085cde657901	692	hspi->pTxBuffPtr = pTxData;
mbed_official	87:085cde657901	693	hspi->TxXferSize = Size;
mbed_official	87:085cde657901	694	hspi->TxXferCount = Size;
mbed_official	87:085cde657901	695
mbed_official	87:085cde657901	696	/Init field not used in handle to zero /
mbed_official	87:085cde657901	697	hspi->RxISR = 0;
mbed_official	87:085cde657901	698	hspi->TxISR = 0;
mbed_official	87:085cde657901	699
mbed_official	87:085cde657901	700	/* Reset CRC Calculation */
mbed_official	87:085cde657901	701	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	87:085cde657901	702	{
mbed_official	87:085cde657901	703	__HAL_SPI_RESET_CRC(hspi);
mbed_official	87:085cde657901	704	}
mbed_official	87:085cde657901	705
mbed_official	87:085cde657901	706	/* Check if the SPI is already enabled */
mbed_official	87:085cde657901	707	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official	87:085cde657901	708	{
mbed_official	87:085cde657901	709	/* Enable SPI peripheral */
mbed_official	87:085cde657901	710	__HAL_SPI_ENABLE(hspi);
mbed_official	87:085cde657901	711	}
mbed_official	87:085cde657901	712
mbed_official	87:085cde657901	713	/* Transmit and Receive data in 16 Bit mode */
mbed_official	87:085cde657901	714	if(hspi->Init.DataSize == SPI_DATASIZE_16BIT)
mbed_official	87:085cde657901	715	{
mbed_official	369:2e96f1b71984	716	if((hspi->Init.Mode == SPI_MODE_SLAVE) \|\| ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->TxXferCount == 0x01)))
mbed_official	369:2e96f1b71984	717	{
mbed_official	369:2e96f1b71984	718	hspi->Instance->DR = ((uint16_t)hspi->pTxBuffPtr);
mbed_official	369:2e96f1b71984	719	hspi->pTxBuffPtr+=2;
mbed_official	369:2e96f1b71984	720	hspi->TxXferCount--;
mbed_official	369:2e96f1b71984	721	}
mbed_official	87:085cde657901	722	if(hspi->TxXferCount == 0)
mbed_official	87:085cde657901	723	{
mbed_official	87:085cde657901	724	/* Enable CRC Transmission */
mbed_official	87:085cde657901	725	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	87:085cde657901	726	{
mbed_official	87:085cde657901	727	hspi->Instance->CR1 \|= SPI_CR1_CRCNEXT;
mbed_official	87:085cde657901	728	}
mbed_official	87:085cde657901	729
mbed_official	87:085cde657901	730	/* Wait until RXNE flag is set */
mbed_official	87:085cde657901	731	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
mbed_official	87:085cde657901	732	{
mbed_official	87:085cde657901	733	return HAL_TIMEOUT;
mbed_official	87:085cde657901	734	}
mbed_official	87:085cde657901	735
mbed_official	87:085cde657901	736	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
mbed_official	87:085cde657901	737	hspi->pRxBuffPtr+=2;
mbed_official	87:085cde657901	738	hspi->RxXferCount--;
mbed_official	87:085cde657901	739	}
mbed_official	87:085cde657901	740	else
mbed_official	87:085cde657901	741	{
mbed_official	87:085cde657901	742	while(hspi->TxXferCount > 0)
mbed_official	87:085cde657901	743	{
mbed_official	87:085cde657901	744	/* Wait until TXE flag is set to send data */
mbed_official	87:085cde657901	745	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
mbed_official	87:085cde657901	746	{
mbed_official	87:085cde657901	747	return HAL_TIMEOUT;
mbed_official	87:085cde657901	748	}
mbed_official	87:085cde657901	749
mbed_official	87:085cde657901	750	hspi->Instance->DR = ((uint16_t)hspi->pTxBuffPtr);
mbed_official	87:085cde657901	751	hspi->pTxBuffPtr+=2;
mbed_official	87:085cde657901	752	hspi->TxXferCount--;
mbed_official	87:085cde657901	753
mbed_official	87:085cde657901	754	/* Enable CRC Transmission */
mbed_official	87:085cde657901	755	if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED))
mbed_official	87:085cde657901	756	{
mbed_official	87:085cde657901	757	hspi->Instance->CR1 \|= SPI_CR1_CRCNEXT;
mbed_official	87:085cde657901	758	}
mbed_official	87:085cde657901	759
mbed_official	87:085cde657901	760	/* Wait until RXNE flag is set */
mbed_official	87:085cde657901	761	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
mbed_official	87:085cde657901	762	{
mbed_official	87:085cde657901	763	return HAL_TIMEOUT;
mbed_official	87:085cde657901	764	}
mbed_official	369:2e96f1b71984	765
mbed_official	87:085cde657901	766	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
mbed_official	87:085cde657901	767	hspi->pRxBuffPtr+=2;
mbed_official	87:085cde657901	768	hspi->RxXferCount--;
mbed_official	87:085cde657901	769	}
mbed_official	369:2e96f1b71984	770	/* Receive the last byte */
mbed_official	369:2e96f1b71984	771	if(hspi->Init.Mode == SPI_MODE_SLAVE)
mbed_official	87:085cde657901	772	{
mbed_official	369:2e96f1b71984	773	/* Wait until RXNE flag is set */
mbed_official	369:2e96f1b71984	774	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
mbed_official	369:2e96f1b71984	775	{
mbed_official	369:2e96f1b71984	776	return HAL_TIMEOUT;
mbed_official	369:2e96f1b71984	777	}
mbed_official	369:2e96f1b71984	778
mbed_official	369:2e96f1b71984	779	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
mbed_official	369:2e96f1b71984	780	hspi->pRxBuffPtr+=2;
mbed_official	369:2e96f1b71984	781	hspi->RxXferCount--;
mbed_official	87:085cde657901	782	}
mbed_official	87:085cde657901	783	}
mbed_official	87:085cde657901	784	}
mbed_official	87:085cde657901	785	/* Transmit and Receive data in 8 Bit mode */
mbed_official	87:085cde657901	786	else
mbed_official	87:085cde657901	787	{
mbed_official	369:2e96f1b71984	788	if((hspi->Init.Mode == SPI_MODE_SLAVE) \|\| ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->TxXferCount == 0x01)))
mbed_official	369:2e96f1b71984	789	{
mbed_official	369:2e96f1b71984	790	hspi->Instance->DR = (*hspi->pTxBuffPtr++);
mbed_official	369:2e96f1b71984	791	hspi->TxXferCount--;
mbed_official	369:2e96f1b71984	792	}
mbed_official	87:085cde657901	793	if(hspi->TxXferCount == 0)
mbed_official	87:085cde657901	794	{
mbed_official	87:085cde657901	795	/* Enable CRC Transmission */
mbed_official	87:085cde657901	796	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	87:085cde657901	797	{
mbed_official	87:085cde657901	798	hspi->Instance->CR1 \|= SPI_CR1_CRCNEXT;
mbed_official	87:085cde657901	799	}
mbed_official	87:085cde657901	800
mbed_official	87:085cde657901	801	/* Wait until RXNE flag is set */
mbed_official	87:085cde657901	802	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
mbed_official	87:085cde657901	803	{
mbed_official	87:085cde657901	804	return HAL_TIMEOUT;
mbed_official	87:085cde657901	805	}
mbed_official	87:085cde657901	806
mbed_official	87:085cde657901	807	(*hspi->pRxBuffPtr) = hspi->Instance->DR;
mbed_official	87:085cde657901	808	hspi->RxXferCount--;
mbed_official	87:085cde657901	809	}
mbed_official	87:085cde657901	810	else
mbed_official	87:085cde657901	811	{
mbed_official	87:085cde657901	812	while(hspi->TxXferCount > 0)
mbed_official	87:085cde657901	813	{
mbed_official	87:085cde657901	814	/* Wait until TXE flag is set to send data */
mbed_official	87:085cde657901	815	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
mbed_official	87:085cde657901	816	{
mbed_official	87:085cde657901	817	return HAL_TIMEOUT;
mbed_official	87:085cde657901	818	}
mbed_official	87:085cde657901	819
mbed_official	87:085cde657901	820	hspi->Instance->DR = (*hspi->pTxBuffPtr++);
mbed_official	87:085cde657901	821	hspi->TxXferCount--;
mbed_official	87:085cde657901	822
mbed_official	87:085cde657901	823	/* Enable CRC Transmission */
mbed_official	87:085cde657901	824	if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED))
mbed_official	87:085cde657901	825	{
mbed_official	87:085cde657901	826	hspi->Instance->CR1 \|= SPI_CR1_CRCNEXT;
mbed_official	87:085cde657901	827	}
mbed_official	87:085cde657901	828
mbed_official	369:2e96f1b71984	829	/* Wait until RXNE flag is set */
mbed_official	369:2e96f1b71984	830	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
mbed_official	369:2e96f1b71984	831	{
mbed_official	369:2e96f1b71984	832	return HAL_TIMEOUT;
mbed_official	369:2e96f1b71984	833	}
mbed_official	369:2e96f1b71984	834
mbed_official	369:2e96f1b71984	835	(*hspi->pRxBuffPtr++) = hspi->Instance->DR;
mbed_official	369:2e96f1b71984	836	hspi->RxXferCount--;
mbed_official	369:2e96f1b71984	837	}
mbed_official	369:2e96f1b71984	838	if(hspi->Init.Mode == SPI_MODE_SLAVE)
mbed_official	369:2e96f1b71984	839	{
mbed_official	87:085cde657901	840	/* Wait until RXNE flag is set */
mbed_official	87:085cde657901	841	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
mbed_official	87:085cde657901	842	{
mbed_official	87:085cde657901	843	return HAL_TIMEOUT;
mbed_official	87:085cde657901	844	}
mbed_official	369:2e96f1b71984	845
mbed_official	87:085cde657901	846	(*hspi->pRxBuffPtr++) = hspi->Instance->DR;
mbed_official	87:085cde657901	847	hspi->RxXferCount--;
mbed_official	87:085cde657901	848	}
mbed_official	87:085cde657901	849	}
mbed_official	87:085cde657901	850	}
mbed_official	87:085cde657901	851
mbed_official	87:085cde657901	852	/* Read CRC from DR to close CRC calculation process */
mbed_official	87:085cde657901	853	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	87:085cde657901	854	{
mbed_official	87:085cde657901	855	/* Wait until RXNE flag is set */
mbed_official	87:085cde657901	856	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
mbed_official	87:085cde657901	857	{
mbed_official	87:085cde657901	858	hspi->ErrorCode \|= HAL_SPI_ERROR_CRC;
mbed_official	87:085cde657901	859	return HAL_TIMEOUT;
mbed_official	87:085cde657901	860	}
mbed_official	87:085cde657901	861	/* Read CRC */
mbed_official	87:085cde657901	862	tmpreg = hspi->Instance->DR;
mbed_official	87:085cde657901	863	}
mbed_official	87:085cde657901	864
mbed_official	87:085cde657901	865	/* Wait until Busy flag is reset before disabling SPI */
mbed_official	87:085cde657901	866	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, Timeout) != HAL_OK)
mbed_official	87:085cde657901	867	{
mbed_official	87:085cde657901	868	hspi->ErrorCode \|= HAL_SPI_ERROR_FLAG;
mbed_official	87:085cde657901	869	return HAL_TIMEOUT;
mbed_official	87:085cde657901	870	}
mbed_official	87:085cde657901	871
mbed_official	87:085cde657901	872	hspi->State = HAL_SPI_STATE_READY;
mbed_official	87:085cde657901	873
mbed_official	87:085cde657901	874	tmp = __HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR);
mbed_official	87:085cde657901	875	/* Check if CRC error occurred */
mbed_official	87:085cde657901	876	if((hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) && (tmp != RESET))
mbed_official	87:085cde657901	877	{
mbed_official	87:085cde657901	878	hspi->ErrorCode \|= HAL_SPI_ERROR_CRC;
mbed_official	87:085cde657901	879
mbed_official	87:085cde657901	880	/* Reset CRC Calculation */
mbed_official	87:085cde657901	881	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	87:085cde657901	882	{
mbed_official	87:085cde657901	883	__HAL_SPI_RESET_CRC(hspi);
mbed_official	87:085cde657901	884	}
mbed_official	87:085cde657901	885
mbed_official	87:085cde657901	886	/* Process Unlocked */
mbed_official	87:085cde657901	887	__HAL_UNLOCK(hspi);
mbed_official	87:085cde657901	888
mbed_official	87:085cde657901	889	return HAL_ERROR;
mbed_official	87:085cde657901	890	}
mbed_official	87:085cde657901	891
mbed_official	87:085cde657901	892	/* Process Unlocked */
mbed_official	87:085cde657901	893	__HAL_UNLOCK(hspi);
mbed_official	87:085cde657901	894
mbed_official	87:085cde657901	895	return HAL_OK;
mbed_official	87:085cde657901	896	}
mbed_official	87:085cde657901	897	else
mbed_official	87:085cde657901	898	{
mbed_official	87:085cde657901	899	return HAL_BUSY;
mbed_official	87:085cde657901	900	}
mbed_official	87:085cde657901	901	}
mbed_official	87:085cde657901	902
mbed_official	87:085cde657901	903	/**
mbed_official	87:085cde657901	904	* @brief Transmit an amount of data in no-blocking mode with Interrupt
mbed_official	226:b062af740e40	905	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	906	* the configuration information for SPI module.
mbed_official	87:085cde657901	907	* @param pData: pointer to data buffer
mbed_official	87:085cde657901	908	* @param Size: amount of data to be sent
mbed_official	87:085cde657901	909	* @retval HAL status
mbed_official	87:085cde657901	910	*/
mbed_official	87:085cde657901	911	HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
mbed_official	87:085cde657901	912	{
mbed_official	87:085cde657901	913	if(hspi->State == HAL_SPI_STATE_READY)
mbed_official	87:085cde657901	914	{
mbed_official	369:2e96f1b71984	915	if((pData == HAL_NULL) \|\| (Size == 0))
mbed_official	87:085cde657901	916	{
mbed_official	87:085cde657901	917	return HAL_ERROR;
mbed_official	87:085cde657901	918	}
mbed_official	87:085cde657901	919
mbed_official	87:085cde657901	920	/* Check the parameters */
mbed_official	87:085cde657901	921	assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
mbed_official	87:085cde657901	922
mbed_official	87:085cde657901	923	/* Process Locked */
mbed_official	87:085cde657901	924	__HAL_LOCK(hspi);
mbed_official	87:085cde657901	925
mbed_official	87:085cde657901	926	/* Configure communication */
mbed_official	87:085cde657901	927	hspi->State = HAL_SPI_STATE_BUSY_TX;
mbed_official	87:085cde657901	928	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official	87:085cde657901	929
mbed_official	87:085cde657901	930	hspi->TxISR = &SPI_TxISR;
mbed_official	87:085cde657901	931	hspi->pTxBuffPtr = pData;
mbed_official	87:085cde657901	932	hspi->TxXferSize = Size;
mbed_official	87:085cde657901	933	hspi->TxXferCount = Size;
mbed_official	87:085cde657901	934
mbed_official	87:085cde657901	935	/Init field not used in handle to zero /
mbed_official	87:085cde657901	936	hspi->RxISR = 0;
mbed_official	87:085cde657901	937	hspi->RxXferSize = 0;
mbed_official	87:085cde657901	938	hspi->RxXferCount = 0;
mbed_official	87:085cde657901	939
mbed_official	87:085cde657901	940	/* Configure communication direction : 1Line */
mbed_official	87:085cde657901	941	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
mbed_official	87:085cde657901	942	{
mbed_official	87:085cde657901	943	__HAL_SPI_1LINE_TX(hspi);
mbed_official	87:085cde657901	944	}
mbed_official	87:085cde657901	945
mbed_official	87:085cde657901	946	/* Reset CRC Calculation */
mbed_official	87:085cde657901	947	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	87:085cde657901	948	{
mbed_official	87:085cde657901	949	__HAL_SPI_RESET_CRC(hspi);
mbed_official	87:085cde657901	950	}
mbed_official	87:085cde657901	951
mbed_official	87:085cde657901	952	if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
mbed_official	87:085cde657901	953	{
mbed_official	87:085cde657901	954	__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE));
mbed_official	87:085cde657901	955	}else
mbed_official	87:085cde657901	956	{
mbed_official	87:085cde657901	957	/* Enable TXE and ERR interrupt */
mbed_official	87:085cde657901	958	__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_ERR));
mbed_official	87:085cde657901	959	}
mbed_official	87:085cde657901	960	/* Process Unlocked */
mbed_official	87:085cde657901	961	__HAL_UNLOCK(hspi);
mbed_official	87:085cde657901	962
mbed_official	87:085cde657901	963	/* Check if the SPI is already enabled */
mbed_official	87:085cde657901	964	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official	87:085cde657901	965	{
mbed_official	87:085cde657901	966	/* Enable SPI peripheral */
mbed_official	87:085cde657901	967	__HAL_SPI_ENABLE(hspi);
mbed_official	87:085cde657901	968	}
mbed_official	87:085cde657901	969
mbed_official	87:085cde657901	970	return HAL_OK;
mbed_official	87:085cde657901	971	}
mbed_official	87:085cde657901	972	else
mbed_official	87:085cde657901	973	{
mbed_official	87:085cde657901	974	return HAL_BUSY;
mbed_official	87:085cde657901	975	}
mbed_official	87:085cde657901	976	}
mbed_official	87:085cde657901	977
mbed_official	87:085cde657901	978	/**
mbed_official	87:085cde657901	979	* @brief Receive an amount of data in no-blocking mode with Interrupt
mbed_official	226:b062af740e40	980	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	981	* the configuration information for SPI module.
mbed_official	87:085cde657901	982	* @param pData: pointer to data buffer
mbed_official	87:085cde657901	983	* @param Size: amount of data to be sent
mbed_official	87:085cde657901	984	* @retval HAL status
mbed_official	87:085cde657901	985	*/
mbed_official	87:085cde657901	986	HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
mbed_official	87:085cde657901	987	{
mbed_official	87:085cde657901	988	if(hspi->State == HAL_SPI_STATE_READY)
mbed_official	87:085cde657901	989	{
mbed_official	369:2e96f1b71984	990	if((pData == HAL_NULL) \|\| (Size == 0))
mbed_official	87:085cde657901	991	{
mbed_official	87:085cde657901	992	return HAL_ERROR;
mbed_official	87:085cde657901	993	}
mbed_official	87:085cde657901	994
mbed_official	87:085cde657901	995	/* Process Locked */
mbed_official	87:085cde657901	996	__HAL_LOCK(hspi);
mbed_official	87:085cde657901	997
mbed_official	87:085cde657901	998	/* Configure communication */
mbed_official	87:085cde657901	999	hspi->State = HAL_SPI_STATE_BUSY_RX;
mbed_official	87:085cde657901	1000	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official	87:085cde657901	1001
mbed_official	87:085cde657901	1002	hspi->RxISR = &SPI_RxISR;
mbed_official	87:085cde657901	1003	hspi->pRxBuffPtr = pData;
mbed_official	87:085cde657901	1004	hspi->RxXferSize = Size;
mbed_official	87:085cde657901	1005	hspi->RxXferCount = Size ;
mbed_official	87:085cde657901	1006
mbed_official	87:085cde657901	1007	/Init field not used in handle to zero /
mbed_official	87:085cde657901	1008	hspi->TxISR = 0;
mbed_official	87:085cde657901	1009	hspi->TxXferSize = 0;
mbed_official	87:085cde657901	1010	hspi->TxXferCount = 0;
mbed_official	87:085cde657901	1011
mbed_official	87:085cde657901	1012	/* Configure communication direction : 1Line */
mbed_official	87:085cde657901	1013	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
mbed_official	87:085cde657901	1014	{
mbed_official	87:085cde657901	1015	__HAL_SPI_1LINE_RX(hspi);
mbed_official	87:085cde657901	1016	}
mbed_official	87:085cde657901	1017	else if((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
mbed_official	87:085cde657901	1018	{
mbed_official	87:085cde657901	1019	/* Process Unlocked */
mbed_official	87:085cde657901	1020	__HAL_UNLOCK(hspi);
mbed_official	87:085cde657901	1021
mbed_official	87:085cde657901	1022	/* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
mbed_official	87:085cde657901	1023	return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size);
mbed_official	87:085cde657901	1024	}
mbed_official	87:085cde657901	1025
mbed_official	87:085cde657901	1026	/* Reset CRC Calculation */
mbed_official	87:085cde657901	1027	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	87:085cde657901	1028	{
mbed_official	87:085cde657901	1029	__HAL_SPI_RESET_CRC(hspi);
mbed_official	87:085cde657901	1030	}
mbed_official	87:085cde657901	1031
mbed_official	87:085cde657901	1032	/* Enable TXE and ERR interrupt */
mbed_official	87:085cde657901	1033	__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE \| SPI_IT_ERR));
mbed_official	87:085cde657901	1034
mbed_official	87:085cde657901	1035	/* Process Unlocked */
mbed_official	87:085cde657901	1036	__HAL_UNLOCK(hspi);
mbed_official	87:085cde657901	1037
mbed_official	87:085cde657901	1038	/* Note : The SPI must be enabled after unlocking current process
mbed_official	87:085cde657901	1039	to avoid the risk of SPI interrupt handle execution before current
mbed_official	87:085cde657901	1040	process unlock */
mbed_official	87:085cde657901	1041
mbed_official	87:085cde657901	1042	/* Check if the SPI is already enabled */
mbed_official	87:085cde657901	1043	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official	87:085cde657901	1044	{
mbed_official	87:085cde657901	1045	/* Enable SPI peripheral */
mbed_official	87:085cde657901	1046	__HAL_SPI_ENABLE(hspi);
mbed_official	87:085cde657901	1047	}
mbed_official	87:085cde657901	1048
mbed_official	87:085cde657901	1049	return HAL_OK;
mbed_official	87:085cde657901	1050	}
mbed_official	87:085cde657901	1051	else
mbed_official	87:085cde657901	1052	{
mbed_official	87:085cde657901	1053	return HAL_BUSY;
mbed_official	87:085cde657901	1054	}
mbed_official	87:085cde657901	1055	}
mbed_official	87:085cde657901	1056
mbed_official	87:085cde657901	1057	/**
mbed_official	87:085cde657901	1058	* @brief Transmit and Receive an amount of data in no-blocking mode with Interrupt
mbed_official	226:b062af740e40	1059	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	1060	* the configuration information for SPI module.
mbed_official	87:085cde657901	1061	* @param pTxData: pointer to transmission data buffer
mbed_official	87:085cde657901	1062	* @param pRxData: pointer to reception data buffer to be
mbed_official	87:085cde657901	1063	* @param Size: amount of data to be sent
mbed_official	87:085cde657901	1064	* @retval HAL status
mbed_official	87:085cde657901	1065	*/
mbed_official	87:085cde657901	1066	HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef hspi, uint8_t pTxData, uint8_t *pRxData, uint16_t Size)
mbed_official	87:085cde657901	1067	{
mbed_official	369:2e96f1b71984	1068	uint32_t tmpstate = 0;
mbed_official	87:085cde657901	1069
mbed_official	369:2e96f1b71984	1070	tmpstate = hspi->State;
mbed_official	369:2e96f1b71984	1071	if((tmpstate == HAL_SPI_STATE_READY) \|\| \
mbed_official	369:2e96f1b71984	1072	((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmpstate == HAL_SPI_STATE_BUSY_RX)))
mbed_official	87:085cde657901	1073	{
mbed_official	369:2e96f1b71984	1074	if((pTxData == HAL_NULL ) \|\| (pRxData == HAL_NULL ) \|\| (Size == 0))
mbed_official	87:085cde657901	1075	{
mbed_official	87:085cde657901	1076	return HAL_ERROR;
mbed_official	87:085cde657901	1077	}
mbed_official	87:085cde657901	1078
mbed_official	87:085cde657901	1079	/* Check the parameters */
mbed_official	87:085cde657901	1080	assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
mbed_official	87:085cde657901	1081
mbed_official	87:085cde657901	1082	/* Process locked */
mbed_official	87:085cde657901	1083	__HAL_LOCK(hspi);
mbed_official	87:085cde657901	1084
mbed_official	87:085cde657901	1085	/* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
mbed_official	369:2e96f1b71984	1086	if(hspi->State != HAL_SPI_STATE_BUSY_RX)
mbed_official	87:085cde657901	1087	{
mbed_official	106:ced8cbb51063	1088	hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
mbed_official	87:085cde657901	1089	}
mbed_official	87:085cde657901	1090
mbed_official	87:085cde657901	1091	/* Configure communication */
mbed_official	87:085cde657901	1092	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official	87:085cde657901	1093
mbed_official	87:085cde657901	1094	hspi->TxISR = &SPI_TxISR;
mbed_official	87:085cde657901	1095	hspi->pTxBuffPtr = pTxData;
mbed_official	87:085cde657901	1096	hspi->TxXferSize = Size;
mbed_official	87:085cde657901	1097	hspi->TxXferCount = Size;
mbed_official	87:085cde657901	1098
mbed_official	87:085cde657901	1099	hspi->RxISR = &SPI_2LinesRxISR;
mbed_official	87:085cde657901	1100	hspi->pRxBuffPtr = pRxData;
mbed_official	87:085cde657901	1101	hspi->RxXferSize = Size;
mbed_official	87:085cde657901	1102	hspi->RxXferCount = Size;
mbed_official	87:085cde657901	1103
mbed_official	87:085cde657901	1104	/* Reset CRC Calculation */
mbed_official	87:085cde657901	1105	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	87:085cde657901	1106	{
mbed_official	87:085cde657901	1107	__HAL_SPI_RESET_CRC(hspi);
mbed_official	87:085cde657901	1108	}
mbed_official	87:085cde657901	1109
mbed_official	87:085cde657901	1110	/* Enable TXE, RXNE and ERR interrupt */
mbed_official	87:085cde657901	1111	__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_RXNE \| SPI_IT_ERR));
mbed_official	87:085cde657901	1112
mbed_official	87:085cde657901	1113	/* Process Unlocked */
mbed_official	87:085cde657901	1114	__HAL_UNLOCK(hspi);
mbed_official	87:085cde657901	1115
mbed_official	87:085cde657901	1116	/* Check if the SPI is already enabled */
mbed_official	87:085cde657901	1117	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official	87:085cde657901	1118	{
mbed_official	87:085cde657901	1119	/* Enable SPI peripheral */
mbed_official	87:085cde657901	1120	__HAL_SPI_ENABLE(hspi);
mbed_official	87:085cde657901	1121	}
mbed_official	87:085cde657901	1122
mbed_official	87:085cde657901	1123	return HAL_OK;
mbed_official	87:085cde657901	1124	}
mbed_official	87:085cde657901	1125	else
mbed_official	87:085cde657901	1126	{
mbed_official	87:085cde657901	1127	return HAL_BUSY;
mbed_official	87:085cde657901	1128	}
mbed_official	87:085cde657901	1129	}
mbed_official	87:085cde657901	1130
mbed_official	87:085cde657901	1131	/**
mbed_official	87:085cde657901	1132	* @brief Transmit an amount of data in no-blocking mode with DMA
mbed_official	226:b062af740e40	1133	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	1134	* the configuration information for SPI module.
mbed_official	87:085cde657901	1135	* @param pData: pointer to data buffer
mbed_official	87:085cde657901	1136	* @param Size: amount of data to be sent
mbed_official	87:085cde657901	1137	* @retval HAL status
mbed_official	87:085cde657901	1138	*/
mbed_official	87:085cde657901	1139	HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
mbed_official	87:085cde657901	1140	{
mbed_official	87:085cde657901	1141	if(hspi->State == HAL_SPI_STATE_READY)
mbed_official	87:085cde657901	1142	{
mbed_official	369:2e96f1b71984	1143	if((pData == HAL_NULL) \|\| (Size == 0))
mbed_official	87:085cde657901	1144	{
mbed_official	87:085cde657901	1145	return HAL_ERROR;
mbed_official	87:085cde657901	1146	}
mbed_official	87:085cde657901	1147
mbed_official	87:085cde657901	1148	/* Check the parameters */
mbed_official	87:085cde657901	1149	assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
mbed_official	87:085cde657901	1150
mbed_official	87:085cde657901	1151	/* Process Locked */
mbed_official	87:085cde657901	1152	__HAL_LOCK(hspi);
mbed_official	87:085cde657901	1153
mbed_official	87:085cde657901	1154	/* Configure communication */
mbed_official	87:085cde657901	1155	hspi->State = HAL_SPI_STATE_BUSY_TX;
mbed_official	87:085cde657901	1156	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official	87:085cde657901	1157
mbed_official	87:085cde657901	1158	hspi->pTxBuffPtr = pData;
mbed_official	87:085cde657901	1159	hspi->TxXferSize = Size;
mbed_official	87:085cde657901	1160	hspi->TxXferCount = Size;
mbed_official	87:085cde657901	1161
mbed_official	87:085cde657901	1162	/Init field not used in handle to zero /
mbed_official	87:085cde657901	1163	hspi->TxISR = 0;
mbed_official	87:085cde657901	1164	hspi->RxISR = 0;
mbed_official	87:085cde657901	1165	hspi->RxXferSize = 0;
mbed_official	87:085cde657901	1166	hspi->RxXferCount = 0;
mbed_official	87:085cde657901	1167
mbed_official	87:085cde657901	1168	/* Configure communication direction : 1Line */
mbed_official	87:085cde657901	1169	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
mbed_official	87:085cde657901	1170	{
mbed_official	87:085cde657901	1171	__HAL_SPI_1LINE_TX(hspi);
mbed_official	87:085cde657901	1172	}
mbed_official	87:085cde657901	1173
mbed_official	87:085cde657901	1174	/* Reset CRC Calculation */
mbed_official	87:085cde657901	1175	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	87:085cde657901	1176	{
mbed_official	87:085cde657901	1177	__HAL_SPI_RESET_CRC(hspi);
mbed_official	87:085cde657901	1178	}
mbed_official	87:085cde657901	1179
mbed_official	369:2e96f1b71984	1180	/* Set the SPI TxDMA Half transfer complete callback */
mbed_official	369:2e96f1b71984	1181	hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt;
mbed_official	369:2e96f1b71984	1182
mbed_official	87:085cde657901	1183	/* Set the SPI TxDMA transfer complete callback */
mbed_official	87:085cde657901	1184	hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt;
mbed_official	87:085cde657901	1185
mbed_official	87:085cde657901	1186	/* Set the DMA error callback */
mbed_official	87:085cde657901	1187	hspi->hdmatx->XferErrorCallback = SPI_DMAError;
mbed_official	87:085cde657901	1188
mbed_official	87:085cde657901	1189	/* Enable the Tx DMA Stream */
mbed_official	87:085cde657901	1190	HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
mbed_official	87:085cde657901	1191
mbed_official	87:085cde657901	1192	/* Enable Tx DMA Request */
mbed_official	87:085cde657901	1193	hspi->Instance->CR2 \|= SPI_CR2_TXDMAEN;
mbed_official	87:085cde657901	1194
mbed_official	87:085cde657901	1195	/* Process Unlocked */
mbed_official	87:085cde657901	1196	__HAL_UNLOCK(hspi);
mbed_official	87:085cde657901	1197
mbed_official	87:085cde657901	1198	/* Check if the SPI is already enabled */
mbed_official	87:085cde657901	1199	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official	87:085cde657901	1200	{
mbed_official	87:085cde657901	1201	/* Enable SPI peripheral */
mbed_official	87:085cde657901	1202	__HAL_SPI_ENABLE(hspi);
mbed_official	87:085cde657901	1203	}
mbed_official	87:085cde657901	1204
mbed_official	87:085cde657901	1205	return HAL_OK;
mbed_official	87:085cde657901	1206	}
mbed_official	87:085cde657901	1207	else
mbed_official	87:085cde657901	1208	{
mbed_official	87:085cde657901	1209	return HAL_BUSY;
mbed_official	87:085cde657901	1210	}
mbed_official	87:085cde657901	1211	}
mbed_official	87:085cde657901	1212
mbed_official	87:085cde657901	1213	/**
mbed_official	87:085cde657901	1214	* @brief Receive an amount of data in no-blocking mode with DMA
mbed_official	226:b062af740e40	1215	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	1216	* the configuration information for SPI module.
mbed_official	87:085cde657901	1217	* @param pData: pointer to data buffer
mbed_official	87:085cde657901	1218	* @note When the CRC feature is enabled the pData Length must be Size + 1.
mbed_official	87:085cde657901	1219	* @param Size: amount of data to be sent
mbed_official	87:085cde657901	1220	* @retval HAL status
mbed_official	87:085cde657901	1221	*/
mbed_official	87:085cde657901	1222	HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
mbed_official	87:085cde657901	1223	{
mbed_official	87:085cde657901	1224	if(hspi->State == HAL_SPI_STATE_READY)
mbed_official	87:085cde657901	1225	{
mbed_official	369:2e96f1b71984	1226	if((pData == HAL_NULL) \|\| (Size == 0))
mbed_official	87:085cde657901	1227	{
mbed_official	87:085cde657901	1228	return HAL_ERROR;
mbed_official	87:085cde657901	1229	}
mbed_official	87:085cde657901	1230
mbed_official	87:085cde657901	1231	/* Process Locked */
mbed_official	87:085cde657901	1232	__HAL_LOCK(hspi);
mbed_official	87:085cde657901	1233
mbed_official	87:085cde657901	1234	/* Configure communication */
mbed_official	87:085cde657901	1235	hspi->State = HAL_SPI_STATE_BUSY_RX;
mbed_official	87:085cde657901	1236	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official	87:085cde657901	1237
mbed_official	87:085cde657901	1238	hspi->pRxBuffPtr = pData;
mbed_official	87:085cde657901	1239	hspi->RxXferSize = Size;
mbed_official	87:085cde657901	1240	hspi->RxXferCount = Size;
mbed_official	87:085cde657901	1241
mbed_official	87:085cde657901	1242	/Init field not used in handle to zero /
mbed_official	87:085cde657901	1243	hspi->RxISR = 0;
mbed_official	87:085cde657901	1244	hspi->TxISR = 0;
mbed_official	87:085cde657901	1245	hspi->TxXferSize = 0;
mbed_official	87:085cde657901	1246	hspi->TxXferCount = 0;
mbed_official	87:085cde657901	1247
mbed_official	87:085cde657901	1248	/* Configure communication direction : 1Line */
mbed_official	87:085cde657901	1249	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
mbed_official	87:085cde657901	1250	{
mbed_official	87:085cde657901	1251	__HAL_SPI_1LINE_RX(hspi);
mbed_official	87:085cde657901	1252	}
mbed_official	87:085cde657901	1253	else if((hspi->Init.Direction == SPI_DIRECTION_2LINES)&&(hspi->Init.Mode == SPI_MODE_MASTER))
mbed_official	87:085cde657901	1254	{
mbed_official	87:085cde657901	1255	/* Process Unlocked */
mbed_official	87:085cde657901	1256	__HAL_UNLOCK(hspi);
mbed_official	87:085cde657901	1257
mbed_official	87:085cde657901	1258	/* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
mbed_official	87:085cde657901	1259	return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size);
mbed_official	87:085cde657901	1260	}
mbed_official	87:085cde657901	1261
mbed_official	87:085cde657901	1262	/* Reset CRC Calculation */
mbed_official	87:085cde657901	1263	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	87:085cde657901	1264	{
mbed_official	87:085cde657901	1265	__HAL_SPI_RESET_CRC(hspi);
mbed_official	87:085cde657901	1266	}
mbed_official	87:085cde657901	1267
mbed_official	369:2e96f1b71984	1268	/* Set the SPI RxDMA Half transfer complete callback */
mbed_official	369:2e96f1b71984	1269	hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
mbed_official	369:2e96f1b71984	1270
mbed_official	87:085cde657901	1271	/* Set the SPI Rx DMA transfer complete callback */
mbed_official	87:085cde657901	1272	hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
mbed_official	87:085cde657901	1273
mbed_official	87:085cde657901	1274	/* Set the DMA error callback */
mbed_official	87:085cde657901	1275	hspi->hdmarx->XferErrorCallback = SPI_DMAError;
mbed_official	87:085cde657901	1276
mbed_official	87:085cde657901	1277	/* Enable the Rx DMA Stream */
mbed_official	87:085cde657901	1278	HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
mbed_official	87:085cde657901	1279
mbed_official	87:085cde657901	1280	/* Enable Rx DMA Request */
mbed_official	87:085cde657901	1281	hspi->Instance->CR2 \|= SPI_CR2_RXDMAEN;
mbed_official	87:085cde657901	1282
mbed_official	87:085cde657901	1283	/* Process Unlocked */
mbed_official	87:085cde657901	1284	__HAL_UNLOCK(hspi);
mbed_official	87:085cde657901	1285
mbed_official	87:085cde657901	1286	/* Check if the SPI is already enabled */
mbed_official	87:085cde657901	1287	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official	87:085cde657901	1288	{
mbed_official	87:085cde657901	1289	/* Enable SPI peripheral */
mbed_official	87:085cde657901	1290	__HAL_SPI_ENABLE(hspi);
mbed_official	87:085cde657901	1291	}
mbed_official	87:085cde657901	1292
mbed_official	87:085cde657901	1293	return HAL_OK;
mbed_official	87:085cde657901	1294	}
mbed_official	87:085cde657901	1295	else
mbed_official	87:085cde657901	1296	{
mbed_official	87:085cde657901	1297	return HAL_BUSY;
mbed_official	87:085cde657901	1298	}
mbed_official	87:085cde657901	1299	}
mbed_official	87:085cde657901	1300
mbed_official	87:085cde657901	1301	/**
mbed_official	87:085cde657901	1302	* @brief Transmit and Receive an amount of data in no-blocking mode with DMA
mbed_official	226:b062af740e40	1303	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	1304	* the configuration information for SPI module.
mbed_official	87:085cde657901	1305	* @param pTxData: pointer to transmission data buffer
mbed_official	87:085cde657901	1306	* @param pRxData: pointer to reception data buffer
mbed_official	87:085cde657901	1307	* @note When the CRC feature is enabled the pRxData Length must be Size + 1
mbed_official	87:085cde657901	1308	* @param Size: amount of data to be sent
mbed_official	87:085cde657901	1309	* @retval HAL status
mbed_official	87:085cde657901	1310	*/
mbed_official	87:085cde657901	1311	HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef hspi, uint8_t pTxData, uint8_t *pRxData, uint16_t Size)
mbed_official	87:085cde657901	1312	{
mbed_official	87:085cde657901	1313	uint32_t tmpstate = 0;
mbed_official	87:085cde657901	1314	tmpstate = hspi->State;
mbed_official	369:2e96f1b71984	1315	if((tmpstate == HAL_SPI_STATE_READY) \|\| ((hspi->Init.Mode == SPI_MODE_MASTER) && \
mbed_official	369:2e96f1b71984	1316	(hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmpstate == HAL_SPI_STATE_BUSY_RX)))
mbed_official	87:085cde657901	1317	{
mbed_official	369:2e96f1b71984	1318	if((pTxData == HAL_NULL ) \|\| (pRxData == HAL_NULL ) \|\| (Size == 0))
mbed_official	87:085cde657901	1319	{
mbed_official	87:085cde657901	1320	return HAL_ERROR;
mbed_official	87:085cde657901	1321	}
mbed_official	87:085cde657901	1322
mbed_official	87:085cde657901	1323	/* Check the parameters */
mbed_official	87:085cde657901	1324	assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
mbed_official	87:085cde657901	1325
mbed_official	87:085cde657901	1326	/* Process locked */
mbed_official	87:085cde657901	1327	__HAL_LOCK(hspi);
mbed_official	87:085cde657901	1328
mbed_official	87:085cde657901	1329	/* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
mbed_official	369:2e96f1b71984	1330	if(hspi->State != HAL_SPI_STATE_BUSY_RX)
mbed_official	87:085cde657901	1331	{
mbed_official	106:ced8cbb51063	1332	hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
mbed_official	87:085cde657901	1333	}
mbed_official	87:085cde657901	1334
mbed_official	87:085cde657901	1335	/* Configure communication */
mbed_official	87:085cde657901	1336	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official	87:085cde657901	1337
mbed_official	87:085cde657901	1338	hspi->pTxBuffPtr = (uint8_t*)pTxData;
mbed_official	87:085cde657901	1339	hspi->TxXferSize = Size;
mbed_official	87:085cde657901	1340	hspi->TxXferCount = Size;
mbed_official	87:085cde657901	1341
mbed_official	87:085cde657901	1342	hspi->pRxBuffPtr = (uint8_t*)pRxData;
mbed_official	87:085cde657901	1343	hspi->RxXferSize = Size;
mbed_official	87:085cde657901	1344	hspi->RxXferCount = Size;
mbed_official	87:085cde657901	1345
mbed_official	87:085cde657901	1346	/Init field not used in handle to zero /
mbed_official	87:085cde657901	1347	hspi->RxISR = 0;
mbed_official	87:085cde657901	1348	hspi->TxISR = 0;
mbed_official	87:085cde657901	1349
mbed_official	87:085cde657901	1350	/* Reset CRC Calculation */
mbed_official	87:085cde657901	1351	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	87:085cde657901	1352	{
mbed_official	87:085cde657901	1353	__HAL_SPI_RESET_CRC(hspi);
mbed_official	87:085cde657901	1354	}
mbed_official	87:085cde657901	1355
mbed_official	106:ced8cbb51063	1356	/* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */
mbed_official	106:ced8cbb51063	1357	if(hspi->State == HAL_SPI_STATE_BUSY_RX)
mbed_official	106:ced8cbb51063	1358	{
mbed_official	369:2e96f1b71984	1359	/* Set the SPI Rx DMA Half transfer complete callback */
mbed_official	369:2e96f1b71984	1360	hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
mbed_official	369:2e96f1b71984	1361
mbed_official	106:ced8cbb51063	1362	hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
mbed_official	106:ced8cbb51063	1363	}
mbed_official	106:ced8cbb51063	1364	else
mbed_official	106:ced8cbb51063	1365	{
mbed_official	369:2e96f1b71984	1366	/* Set the SPI Tx/Rx DMA Half transfer complete callback */
mbed_official	369:2e96f1b71984	1367	hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;
mbed_official	369:2e96f1b71984	1368
mbed_official	106:ced8cbb51063	1369	hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt;
mbed_official	106:ced8cbb51063	1370	}
mbed_official	87:085cde657901	1371
mbed_official	87:085cde657901	1372	/* Set the DMA error callback */
mbed_official	87:085cde657901	1373	hspi->hdmarx->XferErrorCallback = SPI_DMAError;
mbed_official	87:085cde657901	1374
mbed_official	87:085cde657901	1375	/* Enable the Rx DMA Stream */
mbed_official	87:085cde657901	1376	HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
mbed_official	87:085cde657901	1377
mbed_official	87:085cde657901	1378	/* Enable Rx DMA Request */
mbed_official	87:085cde657901	1379	hspi->Instance->CR2 \|= SPI_CR2_RXDMAEN;
mbed_official	87:085cde657901	1380
mbed_official	369:2e96f1b71984	1381	/* Set the SPI Tx DMA transfer complete callback as HAL_NULL because the communication closing
mbed_official	87:085cde657901	1382	is performed in DMA reception complete callback */
mbed_official	369:2e96f1b71984	1383	hspi->hdmatx->XferCpltCallback = HAL_NULL;
mbed_official	87:085cde657901	1384
mbed_official	87:085cde657901	1385	/* Set the DMA error callback */
mbed_official	87:085cde657901	1386	hspi->hdmatx->XferErrorCallback = SPI_DMAError;
mbed_official	87:085cde657901	1387
mbed_official	87:085cde657901	1388	/* Enable the Tx DMA Stream */
mbed_official	87:085cde657901	1389	HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
mbed_official	87:085cde657901	1390
mbed_official	369:2e96f1b71984	1391	/* Check if the SPI is already enabled */
mbed_official	87:085cde657901	1392	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official	87:085cde657901	1393	{
mbed_official	87:085cde657901	1394	/* Enable SPI peripheral */
mbed_official	87:085cde657901	1395	__HAL_SPI_ENABLE(hspi);
mbed_official	87:085cde657901	1396	}
mbed_official	87:085cde657901	1397
mbed_official	369:2e96f1b71984	1398	/* Enable Tx DMA Request */
mbed_official	369:2e96f1b71984	1399	hspi->Instance->CR2 \|= SPI_CR2_TXDMAEN;
mbed_official	369:2e96f1b71984	1400
mbed_official	369:2e96f1b71984	1401	/* Process Unlocked */
mbed_official	369:2e96f1b71984	1402	__HAL_UNLOCK(hspi);
mbed_official	87:085cde657901	1403	return HAL_OK;
mbed_official	87:085cde657901	1404	}
mbed_official	87:085cde657901	1405	else
mbed_official	87:085cde657901	1406	{
mbed_official	87:085cde657901	1407	return HAL_BUSY;
mbed_official	87:085cde657901	1408	}
mbed_official	87:085cde657901	1409	}
mbed_official	87:085cde657901	1410
mbed_official	369:2e96f1b71984	1411
mbed_official	369:2e96f1b71984	1412	/**
mbed_official	369:2e96f1b71984	1413	* @brief Pauses the DMA Transfer.
mbed_official	369:2e96f1b71984	1414	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	369:2e96f1b71984	1415	* the configuration information for the specified SPI module.
mbed_official	369:2e96f1b71984	1416	* @retval HAL status
mbed_official	369:2e96f1b71984	1417	*/
mbed_official	369:2e96f1b71984	1418	HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi)
mbed_official	369:2e96f1b71984	1419	{
mbed_official	369:2e96f1b71984	1420	/* Process Locked */
mbed_official	369:2e96f1b71984	1421	__HAL_LOCK(hspi);
mbed_official	369:2e96f1b71984	1422
mbed_official	369:2e96f1b71984	1423	/* Disable the SPI DMA Tx & Rx requests */
mbed_official	369:2e96f1b71984	1424	hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
mbed_official	369:2e96f1b71984	1425	hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
mbed_official	369:2e96f1b71984	1426
mbed_official	369:2e96f1b71984	1427	/* Process Unlocked */
mbed_official	369:2e96f1b71984	1428	__HAL_UNLOCK(hspi);
mbed_official	369:2e96f1b71984	1429
mbed_official	369:2e96f1b71984	1430	return HAL_OK;
mbed_official	369:2e96f1b71984	1431	}
mbed_official	369:2e96f1b71984	1432
mbed_official	369:2e96f1b71984	1433	/**
mbed_official	369:2e96f1b71984	1434	* @brief Resumes the DMA Transfer.
mbed_official	369:2e96f1b71984	1435	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	369:2e96f1b71984	1436	* the configuration information for the specified SPI module.
mbed_official	369:2e96f1b71984	1437	* @retval HAL status
mbed_official	369:2e96f1b71984	1438	*/
mbed_official	369:2e96f1b71984	1439	HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi)
mbed_official	369:2e96f1b71984	1440	{
mbed_official	369:2e96f1b71984	1441	/* Process Locked */
mbed_official	369:2e96f1b71984	1442	__HAL_LOCK(hspi);
mbed_official	369:2e96f1b71984	1443
mbed_official	369:2e96f1b71984	1444	/* Enable the SPI DMA Tx & Rx requests */
mbed_official	369:2e96f1b71984	1445	hspi->Instance->CR2 \|= SPI_CR2_TXDMAEN;
mbed_official	369:2e96f1b71984	1446	hspi->Instance->CR2 \|= SPI_CR2_RXDMAEN;
mbed_official	369:2e96f1b71984	1447
mbed_official	369:2e96f1b71984	1448	/* Process Unlocked */
mbed_official	369:2e96f1b71984	1449	__HAL_UNLOCK(hspi);
mbed_official	369:2e96f1b71984	1450
mbed_official	369:2e96f1b71984	1451	return HAL_OK;
mbed_official	369:2e96f1b71984	1452	}
mbed_official	369:2e96f1b71984	1453
mbed_official	369:2e96f1b71984	1454	/**
mbed_official	369:2e96f1b71984	1455	* @brief Stops the DMA Transfer.
mbed_official	369:2e96f1b71984	1456	* @param huart: pointer to a UART_HandleTypeDef structure that contains
mbed_official	369:2e96f1b71984	1457	* the configuration information for the specified UART module.
mbed_official	369:2e96f1b71984	1458	* @retval HAL status
mbed_official	369:2e96f1b71984	1459	*/
mbed_official	369:2e96f1b71984	1460	HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)
mbed_official	369:2e96f1b71984	1461	{
mbed_official	369:2e96f1b71984	1462	/* The Lock is not implemented on this API to allow the user application
mbed_official	369:2e96f1b71984	1463	to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback():
mbed_official	369:2e96f1b71984	1464	when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
mbed_official	369:2e96f1b71984	1465	and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback()
mbed_official	369:2e96f1b71984	1466	*/
mbed_official	369:2e96f1b71984	1467
mbed_official	369:2e96f1b71984	1468	/* Abort the SPI DMA tx Stream */
mbed_official	369:2e96f1b71984	1469	if(hspi->hdmatx != HAL_NULL)
mbed_official	369:2e96f1b71984	1470	{
mbed_official	369:2e96f1b71984	1471	HAL_DMA_Abort(hspi->hdmatx);
mbed_official	369:2e96f1b71984	1472	}
mbed_official	369:2e96f1b71984	1473	/* Abort the SPI DMA rx Stream */
mbed_official	369:2e96f1b71984	1474	if(hspi->hdmarx != HAL_NULL)
mbed_official	369:2e96f1b71984	1475	{
mbed_official	369:2e96f1b71984	1476	HAL_DMA_Abort(hspi->hdmarx);
mbed_official	369:2e96f1b71984	1477	}
mbed_official	369:2e96f1b71984	1478
mbed_official	369:2e96f1b71984	1479	/* Disable the SPI DMA Tx & Rx requests */
mbed_official	369:2e96f1b71984	1480	hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
mbed_official	369:2e96f1b71984	1481	hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
mbed_official	369:2e96f1b71984	1482
mbed_official	369:2e96f1b71984	1483	hspi->State = HAL_SPI_STATE_READY;
mbed_official	369:2e96f1b71984	1484
mbed_official	369:2e96f1b71984	1485	return HAL_OK;
mbed_official	369:2e96f1b71984	1486	}
mbed_official	369:2e96f1b71984	1487
mbed_official	87:085cde657901	1488	/**
mbed_official	87:085cde657901	1489	* @brief This function handles SPI interrupt request.
mbed_official	226:b062af740e40	1490	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	1491	* the configuration information for SPI module.
mbed_official	87:085cde657901	1492	* @retval HAL status
mbed_official	87:085cde657901	1493	*/
mbed_official	87:085cde657901	1494	void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
mbed_official	87:085cde657901	1495	{
mbed_official	87:085cde657901	1496	uint32_t tmp1 = 0, tmp2 = 0, tmp3 = 0;
mbed_official	87:085cde657901	1497
mbed_official	87:085cde657901	1498	tmp1 = __HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE);
mbed_official	87:085cde657901	1499	tmp2 = __HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_RXNE);
mbed_official	87:085cde657901	1500	tmp3 = __HAL_SPI_GET_FLAG(hspi, SPI_FLAG_OVR);
mbed_official	87:085cde657901	1501	/* SPI in mode Receiver and Overrun not occurred ---------------------------*/
mbed_official	87:085cde657901	1502	if((tmp1 != RESET) && (tmp2 != RESET) && (tmp3 == RESET))
mbed_official	87:085cde657901	1503	{
mbed_official	87:085cde657901	1504	hspi->RxISR(hspi);
mbed_official	87:085cde657901	1505	return;
mbed_official	87:085cde657901	1506	}
mbed_official	87:085cde657901	1507
mbed_official	87:085cde657901	1508	tmp1 = __HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE);
mbed_official	87:085cde657901	1509	tmp2 = __HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_TXE);
mbed_official	87:085cde657901	1510	/* SPI in mode Tramitter ---------------------------------------------------*/
mbed_official	87:085cde657901	1511	if((tmp1 != RESET) && (tmp2 != RESET))
mbed_official	87:085cde657901	1512	{
mbed_official	87:085cde657901	1513	hspi->TxISR(hspi);
mbed_official	87:085cde657901	1514	return;
mbed_official	87:085cde657901	1515	}
mbed_official	87:085cde657901	1516
mbed_official	87:085cde657901	1517	if(__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_ERR) != RESET)
mbed_official	87:085cde657901	1518	{
mbed_official	226:b062af740e40	1519	/* SPI CRC error interrupt occurred ---------------------------------------*/
mbed_official	87:085cde657901	1520	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
mbed_official	87:085cde657901	1521	{
mbed_official	87:085cde657901	1522	hspi->ErrorCode \|= HAL_SPI_ERROR_CRC;
mbed_official	87:085cde657901	1523	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
mbed_official	87:085cde657901	1524	}
mbed_official	226:b062af740e40	1525	/* SPI Mode Fault error interrupt occurred --------------------------------*/
mbed_official	87:085cde657901	1526	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_MODF) != RESET)
mbed_official	87:085cde657901	1527	{
mbed_official	87:085cde657901	1528	hspi->ErrorCode \|= HAL_SPI_ERROR_MODF;
mbed_official	87:085cde657901	1529	__HAL_SPI_CLEAR_MODFFLAG(hspi);
mbed_official	87:085cde657901	1530	}
mbed_official	87:085cde657901	1531
mbed_official	226:b062af740e40	1532	/* SPI Overrun error interrupt occurred -----------------------------------*/
mbed_official	87:085cde657901	1533	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_OVR) != RESET)
mbed_official	87:085cde657901	1534	{
mbed_official	87:085cde657901	1535	if(hspi->State != HAL_SPI_STATE_BUSY_TX)
mbed_official	87:085cde657901	1536	{
mbed_official	87:085cde657901	1537	hspi->ErrorCode \|= HAL_SPI_ERROR_OVR;
mbed_official	87:085cde657901	1538	__HAL_SPI_CLEAR_OVRFLAG(hspi);
mbed_official	87:085cde657901	1539	}
mbed_official	87:085cde657901	1540	}
mbed_official	87:085cde657901	1541
mbed_official	226:b062af740e40	1542	/* SPI Frame error interrupt occurred -------------------------------------*/
mbed_official	87:085cde657901	1543	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_FRE) != RESET)
mbed_official	87:085cde657901	1544	{
mbed_official	87:085cde657901	1545	hspi->ErrorCode \|= HAL_SPI_ERROR_FRE;
mbed_official	87:085cde657901	1546	__HAL_SPI_CLEAR_FREFLAG(hspi);
mbed_official	87:085cde657901	1547	}
mbed_official	87:085cde657901	1548
mbed_official	87:085cde657901	1549	/* Call the Error call Back in case of Errors */
mbed_official	87:085cde657901	1550	if(hspi->ErrorCode!=HAL_SPI_ERROR_NONE)
mbed_official	87:085cde657901	1551	{
mbed_official	87:085cde657901	1552	hspi->State = HAL_SPI_STATE_READY;
mbed_official	87:085cde657901	1553	HAL_SPI_ErrorCallback(hspi);
mbed_official	87:085cde657901	1554	}
mbed_official	87:085cde657901	1555	}
mbed_official	87:085cde657901	1556	}
mbed_official	87:085cde657901	1557
mbed_official	87:085cde657901	1558	/**
mbed_official	87:085cde657901	1559	* @brief Tx Transfer completed callbacks
mbed_official	226:b062af740e40	1560	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	1561	* the configuration information for SPI module.
mbed_official	87:085cde657901	1562	* @retval None
mbed_official	87:085cde657901	1563	*/
mbed_official	87:085cde657901	1564	__weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
mbed_official	87:085cde657901	1565	{
mbed_official	87:085cde657901	1566	/* NOTE : This function Should not be modified, when the callback is needed,
mbed_official	87:085cde657901	1567	the HAL_SPI_TxCpltCallback could be implenetd in the user file
mbed_official	87:085cde657901	1568	*/
mbed_official	87:085cde657901	1569	}
mbed_official	87:085cde657901	1570
mbed_official	87:085cde657901	1571	/**
mbed_official	87:085cde657901	1572	* @brief Rx Transfer completed callbacks
mbed_official	226:b062af740e40	1573	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	1574	* the configuration information for SPI module.
mbed_official	87:085cde657901	1575	* @retval None
mbed_official	87:085cde657901	1576	*/
mbed_official	87:085cde657901	1577	__weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
mbed_official	87:085cde657901	1578	{
mbed_official	87:085cde657901	1579	/* NOTE : This function Should not be modified, when the callback is needed,
mbed_official	87:085cde657901	1580	the HAL_SPI_RxCpltCallback() could be implenetd in the user file
mbed_official	87:085cde657901	1581	*/
mbed_official	87:085cde657901	1582	}
mbed_official	87:085cde657901	1583
mbed_official	87:085cde657901	1584	/**
mbed_official	87:085cde657901	1585	* @brief Tx and Rx Transfer completed callbacks
mbed_official	226:b062af740e40	1586	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	1587	* the configuration information for SPI module.
mbed_official	87:085cde657901	1588	* @retval None
mbed_official	87:085cde657901	1589	*/
mbed_official	87:085cde657901	1590	__weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
mbed_official	87:085cde657901	1591	{
mbed_official	87:085cde657901	1592	/* NOTE : This function Should not be modified, when the callback is needed,
mbed_official	87:085cde657901	1593	the HAL_SPI_TxRxCpltCallback() could be implenetd in the user file
mbed_official	87:085cde657901	1594	*/
mbed_official	87:085cde657901	1595	}
mbed_official	87:085cde657901	1596
mbed_official	87:085cde657901	1597	/**
mbed_official	369:2e96f1b71984	1598	* @brief Tx Half Transfer completed callbacks
mbed_official	369:2e96f1b71984	1599	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	369:2e96f1b71984	1600	* the configuration information for SPI module.
mbed_official	369:2e96f1b71984	1601	* @retval None
mbed_official	369:2e96f1b71984	1602	*/
mbed_official	369:2e96f1b71984	1603	__weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)
mbed_official	369:2e96f1b71984	1604	{
mbed_official	369:2e96f1b71984	1605	/* NOTE : This function Should not be modified, when the callback is needed,
mbed_official	369:2e96f1b71984	1606	the HAL_SPI_TxHalfCpltCallback could be implenetd in the user file
mbed_official	369:2e96f1b71984	1607	*/
mbed_official	369:2e96f1b71984	1608	}
mbed_official	369:2e96f1b71984	1609
mbed_official	369:2e96f1b71984	1610	/**
mbed_official	369:2e96f1b71984	1611	* @brief Rx Half Transfer completed callbacks
mbed_official	369:2e96f1b71984	1612	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	369:2e96f1b71984	1613	* the configuration information for SPI module.
mbed_official	369:2e96f1b71984	1614	* @retval None
mbed_official	369:2e96f1b71984	1615	*/
mbed_official	369:2e96f1b71984	1616	__weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)
mbed_official	369:2e96f1b71984	1617	{
mbed_official	369:2e96f1b71984	1618	/* NOTE : This function Should not be modified, when the callback is needed,
mbed_official	369:2e96f1b71984	1619	the HAL_SPI_RxHalfCpltCallback() could be implenetd in the user file
mbed_official	369:2e96f1b71984	1620	*/
mbed_official	369:2e96f1b71984	1621	}
mbed_official	369:2e96f1b71984	1622
mbed_official	369:2e96f1b71984	1623	/**
mbed_official	369:2e96f1b71984	1624	* @brief Tx and Rx Transfer completed callbacks
mbed_official	369:2e96f1b71984	1625	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	369:2e96f1b71984	1626	* the configuration information for SPI module.
mbed_official	369:2e96f1b71984	1627	* @retval None
mbed_official	369:2e96f1b71984	1628	*/
mbed_official	369:2e96f1b71984	1629	__weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
mbed_official	369:2e96f1b71984	1630	{
mbed_official	369:2e96f1b71984	1631	/* NOTE : This function Should not be modified, when the callback is needed,
mbed_official	369:2e96f1b71984	1632	the HAL_SPI_TxRxHalfCpltCallback() could be implenetd in the user file
mbed_official	369:2e96f1b71984	1633	*/
mbed_official	369:2e96f1b71984	1634	}
mbed_official	369:2e96f1b71984	1635
mbed_official	369:2e96f1b71984	1636	/**
mbed_official	87:085cde657901	1637	* @brief SPI error callbacks
mbed_official	226:b062af740e40	1638	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	1639	* the configuration information for SPI module.
mbed_official	87:085cde657901	1640	* @retval None
mbed_official	87:085cde657901	1641	*/
mbed_official	87:085cde657901	1642	__weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
mbed_official	87:085cde657901	1643	{
mbed_official	87:085cde657901	1644	/* NOTE : - This function Should not be modified, when the callback is needed,
mbed_official	87:085cde657901	1645	the HAL_SPI_ErrorCallback() could be implenetd in the user file.
mbed_official	87:085cde657901	1646	- The ErrorCode parameter in the hspi handle is updated by the SPI processes
mbed_official	226:b062af740e40	1647	and user can use HAL_SPI_GetError() API to check the latest error occurred.
mbed_official	87:085cde657901	1648	*/
mbed_official	87:085cde657901	1649	}
mbed_official	87:085cde657901	1650
mbed_official	87:085cde657901	1651	/**
mbed_official	87:085cde657901	1652	* @}
mbed_official	87:085cde657901	1653	*/
mbed_official	87:085cde657901	1654
mbed_official	87:085cde657901	1655	/** @defgroup SPI_Group3 Peripheral State and Errors functions
mbed_official	87:085cde657901	1656	* @brief SPI control functions
mbed_official	87:085cde657901	1657	*
mbed_official	87:085cde657901	1658	@verbatim
mbed_official	87:085cde657901	1659	===============================================================================
mbed_official	87:085cde657901	1660	##### Peripheral State and Errors functions #####
mbed_official	87:085cde657901	1661	===============================================================================
mbed_official	87:085cde657901	1662	[..]
mbed_official	87:085cde657901	1663	This subsection provides a set of functions allowing to control the SPI.
mbed_official	87:085cde657901	1664	(+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral
mbed_official	87:085cde657901	1665	(+) HAL_SPI_GetError() check in run-time Errors occurring during communication
mbed_official	87:085cde657901	1666	@endverbatim
mbed_official	87:085cde657901	1667	* @{
mbed_official	87:085cde657901	1668	*/
mbed_official	87:085cde657901	1669
mbed_official	87:085cde657901	1670	/**
mbed_official	87:085cde657901	1671	* @brief Return the SPI state
mbed_official	226:b062af740e40	1672	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	1673	* the configuration information for SPI module.
mbed_official	226:b062af740e40	1674	* @retval HAL state
mbed_official	87:085cde657901	1675	*/
mbed_official	87:085cde657901	1676	HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
mbed_official	87:085cde657901	1677	{
mbed_official	87:085cde657901	1678	return hspi->State;
mbed_official	87:085cde657901	1679	}
mbed_official	87:085cde657901	1680
mbed_official	87:085cde657901	1681	/**
mbed_official	87:085cde657901	1682	* @brief Return the SPI error code
mbed_official	226:b062af740e40	1683	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	1684	* the configuration information for SPI module.
mbed_official	87:085cde657901	1685	* @retval SPI Error Code
mbed_official	87:085cde657901	1686	*/
mbed_official	87:085cde657901	1687	HAL_SPI_ErrorTypeDef HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
mbed_official	87:085cde657901	1688	{
mbed_official	87:085cde657901	1689	return hspi->ErrorCode;
mbed_official	87:085cde657901	1690	}
mbed_official	87:085cde657901	1691
mbed_official	87:085cde657901	1692	/**
mbed_official	87:085cde657901	1693	* @}
mbed_official	87:085cde657901	1694	*/
mbed_official	87:085cde657901	1695
mbed_official	87:085cde657901	1696	/**
mbed_official	87:085cde657901	1697	* @brief Interrupt Handler to close Tx transfer
mbed_official	226:b062af740e40	1698	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	1699	* the configuration information for SPI module.
mbed_official	87:085cde657901	1700	* @retval void
mbed_official	87:085cde657901	1701	*/
mbed_official	87:085cde657901	1702	static void SPI_TxCloseIRQHandler(SPI_HandleTypeDef *hspi)
mbed_official	87:085cde657901	1703	{
mbed_official	106:ced8cbb51063	1704	/* Wait until TXE flag is set to send data */
mbed_official	106:ced8cbb51063	1705	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
mbed_official	87:085cde657901	1706	{
mbed_official	106:ced8cbb51063	1707	hspi->ErrorCode \|= HAL_SPI_ERROR_FLAG;
mbed_official	87:085cde657901	1708	}
mbed_official	87:085cde657901	1709
mbed_official	87:085cde657901	1710	/* Disable TXE interrupt */
mbed_official	87:085cde657901	1711	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE ));
mbed_official	87:085cde657901	1712
mbed_official	87:085cde657901	1713	/* Disable ERR interrupt if Receive process is finished */
mbed_official	87:085cde657901	1714	if(__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_RXNE) == RESET)
mbed_official	87:085cde657901	1715	{
mbed_official	87:085cde657901	1716	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_ERR));
mbed_official	87:085cde657901	1717
mbed_official	87:085cde657901	1718	/* Wait until Busy flag is reset before disabling SPI */
mbed_official	87:085cde657901	1719	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
mbed_official	87:085cde657901	1720	{
mbed_official	87:085cde657901	1721	hspi->ErrorCode \|= HAL_SPI_ERROR_FLAG;
mbed_official	87:085cde657901	1722	}
mbed_official	87:085cde657901	1723
mbed_official	87:085cde657901	1724	/* Clear OVERUN flag in 2 Lines communication mode because received is not read */
mbed_official	87:085cde657901	1725	if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
mbed_official	87:085cde657901	1726	{
mbed_official	87:085cde657901	1727	__HAL_SPI_CLEAR_OVRFLAG(hspi);
mbed_official	87:085cde657901	1728	}
mbed_official	87:085cde657901	1729
mbed_official	87:085cde657901	1730	/* Check if Errors has been detected during transfer */
mbed_official	87:085cde657901	1731	if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
mbed_official	87:085cde657901	1732	{
mbed_official	87:085cde657901	1733	/* Check if we are in Tx or in Rx/Tx Mode */
mbed_official	87:085cde657901	1734	if(hspi->State == HAL_SPI_STATE_BUSY_TX_RX)
mbed_official	87:085cde657901	1735	{
mbed_official	106:ced8cbb51063	1736	/* Set state to READY before run the Callback Complete */
mbed_official	106:ced8cbb51063	1737	hspi->State = HAL_SPI_STATE_READY;
mbed_official	87:085cde657901	1738	HAL_SPI_TxRxCpltCallback(hspi);
mbed_official	87:085cde657901	1739	}
mbed_official	87:085cde657901	1740	else
mbed_official	87:085cde657901	1741	{
mbed_official	106:ced8cbb51063	1742	/* Set state to READY before run the Callback Complete */
mbed_official	106:ced8cbb51063	1743	hspi->State = HAL_SPI_STATE_READY;
mbed_official	106:ced8cbb51063	1744	HAL_SPI_TxCpltCallback(hspi);
mbed_official	87:085cde657901	1745	}
mbed_official	87:085cde657901	1746	}
mbed_official	87:085cde657901	1747	else
mbed_official	87:085cde657901	1748	{
mbed_official	106:ced8cbb51063	1749	/* Set state to READY before run the Callback Complete */
mbed_official	106:ced8cbb51063	1750	hspi->State = HAL_SPI_STATE_READY;
mbed_official	87:085cde657901	1751	/* Call Error call back in case of Error */
mbed_official	87:085cde657901	1752	HAL_SPI_ErrorCallback(hspi);
mbed_official	87:085cde657901	1753	}
mbed_official	87:085cde657901	1754	}
mbed_official	87:085cde657901	1755	}
mbed_official	87:085cde657901	1756
mbed_official	87:085cde657901	1757	/**
mbed_official	87:085cde657901	1758	* @brief Interrupt Handler to transmit amount of data in no-blocking mode
mbed_official	226:b062af740e40	1759	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	1760	* the configuration information for SPI module.
mbed_official	87:085cde657901	1761	* @retval void
mbed_official	87:085cde657901	1762	*/
mbed_official	87:085cde657901	1763	static void SPI_TxISR(SPI_HandleTypeDef *hspi)
mbed_official	87:085cde657901	1764	{
mbed_official	87:085cde657901	1765	/* Transmit data in 8 Bit mode */
mbed_official	87:085cde657901	1766	if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
mbed_official	87:085cde657901	1767	{
mbed_official	87:085cde657901	1768	hspi->Instance->DR = (*hspi->pTxBuffPtr++);
mbed_official	87:085cde657901	1769	}
mbed_official	87:085cde657901	1770	/* Transmit data in 16 Bit mode */
mbed_official	87:085cde657901	1771	else
mbed_official	87:085cde657901	1772	{
mbed_official	87:085cde657901	1773	hspi->Instance->DR = ((uint16_t)hspi->pTxBuffPtr);
mbed_official	87:085cde657901	1774	hspi->pTxBuffPtr+=2;
mbed_official	87:085cde657901	1775	}
mbed_official	87:085cde657901	1776	hspi->TxXferCount--;
mbed_official	87:085cde657901	1777
mbed_official	87:085cde657901	1778	if(hspi->TxXferCount == 0)
mbed_official	87:085cde657901	1779	{
mbed_official	87:085cde657901	1780	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	87:085cde657901	1781	{
mbed_official	87:085cde657901	1782	/* calculate and transfer CRC on Tx line */
mbed_official	87:085cde657901	1783	hspi->Instance->CR1 \|= SPI_CR1_CRCNEXT;
mbed_official	87:085cde657901	1784	}
mbed_official	87:085cde657901	1785	SPI_TxCloseIRQHandler(hspi);
mbed_official	87:085cde657901	1786	}
mbed_official	87:085cde657901	1787	}
mbed_official	87:085cde657901	1788
mbed_official	87:085cde657901	1789	/**
mbed_official	87:085cde657901	1790	* @brief Interrupt Handler to close Rx transfer
mbed_official	226:b062af740e40	1791	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	1792	* the configuration information for SPI module.
mbed_official	87:085cde657901	1793	* @retval void
mbed_official	87:085cde657901	1794	*/
mbed_official	106:ced8cbb51063	1795	static void SPI_RxCloseIRQHandler(SPI_HandleTypeDef *hspi)
mbed_official	87:085cde657901	1796	{
mbed_official	87:085cde657901	1797	__IO uint16_t tmpreg;
mbed_official	87:085cde657901	1798
mbed_official	87:085cde657901	1799	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	87:085cde657901	1800	{
mbed_official	87:085cde657901	1801	/* Wait until RXNE flag is set to send data */
mbed_official	87:085cde657901	1802	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
mbed_official	87:085cde657901	1803	{
mbed_official	87:085cde657901	1804	hspi->ErrorCode \|= HAL_SPI_ERROR_FLAG;
mbed_official	87:085cde657901	1805	}
mbed_official	87:085cde657901	1806
mbed_official	87:085cde657901	1807	/* Read CRC to reset RXNE flag */
mbed_official	87:085cde657901	1808	tmpreg = hspi->Instance->DR;
mbed_official	87:085cde657901	1809
mbed_official	87:085cde657901	1810	/* Wait until RXNE flag is set to send data */
mbed_official	87:085cde657901	1811	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
mbed_official	87:085cde657901	1812	{
mbed_official	87:085cde657901	1813	hspi->ErrorCode \|= HAL_SPI_ERROR_FLAG;
mbed_official	87:085cde657901	1814	}
mbed_official	87:085cde657901	1815
mbed_official	87:085cde657901	1816	/* Check if CRC error occurred */
mbed_official	87:085cde657901	1817	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
mbed_official	87:085cde657901	1818	{
mbed_official	87:085cde657901	1819	hspi->ErrorCode \|= HAL_SPI_ERROR_CRC;
mbed_official	87:085cde657901	1820
mbed_official	87:085cde657901	1821	/* Reset CRC Calculation */
mbed_official	87:085cde657901	1822	__HAL_SPI_RESET_CRC(hspi);
mbed_official	87:085cde657901	1823	}
mbed_official	87:085cde657901	1824	}
mbed_official	87:085cde657901	1825
mbed_official	87:085cde657901	1826	/* Disable RXNE and ERR interrupt */
mbed_official	87:085cde657901	1827	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE));
mbed_official	87:085cde657901	1828
mbed_official	87:085cde657901	1829	/* if Transmit process is finished */
mbed_official	87:085cde657901	1830	if(__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_TXE) == RESET)
mbed_official	87:085cde657901	1831	{
mbed_official	87:085cde657901	1832	/* Disable ERR interrupt */
mbed_official	87:085cde657901	1833	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_ERR));
mbed_official	87:085cde657901	1834
mbed_official	87:085cde657901	1835	if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)\|\|(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
mbed_official	87:085cde657901	1836	{
mbed_official	87:085cde657901	1837	/* Disable SPI peripheral */
mbed_official	87:085cde657901	1838	__HAL_SPI_DISABLE(hspi);
mbed_official	87:085cde657901	1839	}
mbed_official	87:085cde657901	1840
mbed_official	87:085cde657901	1841	/* Check if Errors has been detected during transfer */
mbed_official	87:085cde657901	1842	if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
mbed_official	87:085cde657901	1843	{
mbed_official	87:085cde657901	1844	/* Check if we are in Rx or in Rx/Tx Mode */
mbed_official	87:085cde657901	1845	if(hspi->State == HAL_SPI_STATE_BUSY_TX_RX)
mbed_official	87:085cde657901	1846	{
mbed_official	106:ced8cbb51063	1847	/* Set state to READY before run the Callback Complete */
mbed_official	106:ced8cbb51063	1848	hspi->State = HAL_SPI_STATE_READY;
mbed_official	87:085cde657901	1849	HAL_SPI_TxRxCpltCallback(hspi);
mbed_official	369:2e96f1b71984	1850	}
mbed_official	369:2e96f1b71984	1851	else
mbed_official	87:085cde657901	1852	{
mbed_official	106:ced8cbb51063	1853	/* Set state to READY before run the Callback Complete */
mbed_official	106:ced8cbb51063	1854	hspi->State = HAL_SPI_STATE_READY;
mbed_official	87:085cde657901	1855	HAL_SPI_RxCpltCallback(hspi);
mbed_official	87:085cde657901	1856	}
mbed_official	87:085cde657901	1857	}
mbed_official	87:085cde657901	1858	else
mbed_official	87:085cde657901	1859	{
mbed_official	106:ced8cbb51063	1860	/* Set state to READY before run the Callback Complete */
mbed_official	106:ced8cbb51063	1861	hspi->State = HAL_SPI_STATE_READY;
mbed_official	87:085cde657901	1862	/* Call Error call back in case of Error */
mbed_official	87:085cde657901	1863	HAL_SPI_ErrorCallback(hspi);
mbed_official	87:085cde657901	1864	}
mbed_official	87:085cde657901	1865	}
mbed_official	87:085cde657901	1866	}
mbed_official	87:085cde657901	1867
mbed_official	87:085cde657901	1868	/**
mbed_official	87:085cde657901	1869	* @brief Interrupt Handler to receive amount of data in 2Lines mode
mbed_official	226:b062af740e40	1870	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	1871	* the configuration information for SPI module.
mbed_official	87:085cde657901	1872	* @retval void
mbed_official	87:085cde657901	1873	*/
mbed_official	87:085cde657901	1874	static void SPI_2LinesRxISR(SPI_HandleTypeDef *hspi)
mbed_official	87:085cde657901	1875	{
mbed_official	87:085cde657901	1876	/* Receive data in 8 Bit mode */
mbed_official	87:085cde657901	1877	if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
mbed_official	87:085cde657901	1878	{
mbed_official	87:085cde657901	1879	(*hspi->pRxBuffPtr++) = hspi->Instance->DR;
mbed_official	87:085cde657901	1880	}
mbed_official	87:085cde657901	1881	/* Receive data in 16 Bit mode */
mbed_official	87:085cde657901	1882	else
mbed_official	87:085cde657901	1883	{
mbed_official	87:085cde657901	1884	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
mbed_official	87:085cde657901	1885	hspi->pRxBuffPtr+=2;
mbed_official	87:085cde657901	1886	}
mbed_official	87:085cde657901	1887	hspi->RxXferCount--;
mbed_official	87:085cde657901	1888
mbed_official	87:085cde657901	1889	if(hspi->RxXferCount==0)
mbed_official	87:085cde657901	1890	{
mbed_official	106:ced8cbb51063	1891	SPI_RxCloseIRQHandler(hspi);
mbed_official	87:085cde657901	1892	}
mbed_official	87:085cde657901	1893	}
mbed_official	87:085cde657901	1894
mbed_official	87:085cde657901	1895	/**
mbed_official	87:085cde657901	1896	* @brief Interrupt Handler to receive amount of data in no-blocking mode
mbed_official	226:b062af740e40	1897	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	1898	* the configuration information for SPI module.
mbed_official	87:085cde657901	1899	* @retval void
mbed_official	87:085cde657901	1900	*/
mbed_official	87:085cde657901	1901	static void SPI_RxISR(SPI_HandleTypeDef *hspi)
mbed_official	87:085cde657901	1902	{
mbed_official	87:085cde657901	1903	/* Receive data in 8 Bit mode */
mbed_official	87:085cde657901	1904	if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
mbed_official	87:085cde657901	1905	{
mbed_official	87:085cde657901	1906	(*hspi->pRxBuffPtr++) = hspi->Instance->DR;
mbed_official	87:085cde657901	1907	}
mbed_official	87:085cde657901	1908	/* Receive data in 16 Bit mode */
mbed_official	87:085cde657901	1909	else
mbed_official	87:085cde657901	1910	{
mbed_official	87:085cde657901	1911	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
mbed_official	87:085cde657901	1912	hspi->pRxBuffPtr+=2;
mbed_official	87:085cde657901	1913	}
mbed_official	87:085cde657901	1914	hspi->RxXferCount--;
mbed_official	87:085cde657901	1915
mbed_official	87:085cde657901	1916	/* Enable CRC Transmission */
mbed_official	87:085cde657901	1917	if((hspi->RxXferCount == 1) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED))
mbed_official	87:085cde657901	1918	{
mbed_official	87:085cde657901	1919	/* Set CRC Next to calculate CRC on Rx side */
mbed_official	87:085cde657901	1920	hspi->Instance->CR1 \|= SPI_CR1_CRCNEXT;
mbed_official	87:085cde657901	1921	}
mbed_official	87:085cde657901	1922
mbed_official	87:085cde657901	1923	if(hspi->RxXferCount == 0)
mbed_official	87:085cde657901	1924	{
mbed_official	106:ced8cbb51063	1925	SPI_RxCloseIRQHandler(hspi);
mbed_official	87:085cde657901	1926	}
mbed_official	87:085cde657901	1927	}
mbed_official	87:085cde657901	1928
mbed_official	87:085cde657901	1929	/**
mbed_official	87:085cde657901	1930	* @brief DMA SPI transmit process complete callback
mbed_official	226:b062af740e40	1931	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	1932	* the configuration information for the specified DMA module.
mbed_official	87:085cde657901	1933	* @retval None
mbed_official	87:085cde657901	1934	*/
mbed_official	87:085cde657901	1935	static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
mbed_official	87:085cde657901	1936	{
mbed_official	87:085cde657901	1937	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official	87:085cde657901	1938
mbed_official	369:2e96f1b71984	1939	/* DMA Normal Mode */
mbed_official	369:2e96f1b71984	1940	if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
mbed_official	87:085cde657901	1941	{
mbed_official	369:2e96f1b71984	1942	/* Wait until TXE flag is set to send data */
mbed_official	369:2e96f1b71984	1943	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
mbed_official	369:2e96f1b71984	1944	{
mbed_official	369:2e96f1b71984	1945	hspi->ErrorCode \|= HAL_SPI_ERROR_FLAG;
mbed_official	369:2e96f1b71984	1946	}
mbed_official	369:2e96f1b71984	1947	/* Disable Tx DMA Request */
mbed_official	369:2e96f1b71984	1948	hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
mbed_official	87:085cde657901	1949
mbed_official	369:2e96f1b71984	1950	/* Wait until Busy flag is reset before disabling SPI */
mbed_official	369:2e96f1b71984	1951	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
mbed_official	369:2e96f1b71984	1952	{
mbed_official	369:2e96f1b71984	1953	hspi->ErrorCode \|= HAL_SPI_ERROR_FLAG;
mbed_official	369:2e96f1b71984	1954	}
mbed_official	369:2e96f1b71984	1955
mbed_official	369:2e96f1b71984	1956	hspi->TxXferCount = 0;
mbed_official	369:2e96f1b71984	1957
mbed_official	369:2e96f1b71984	1958	hspi->State = HAL_SPI_STATE_READY;
mbed_official	87:085cde657901	1959	}
mbed_official	87:085cde657901	1960
mbed_official	87:085cde657901	1961	/* Clear OVERUN flag in 2 Lines communication mode because received is not read */
mbed_official	87:085cde657901	1962	if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
mbed_official	87:085cde657901	1963	{
mbed_official	369:2e96f1b71984	1964	__HAL_SPI_CLEAR_OVRFLAG(hspi);
mbed_official	87:085cde657901	1965	}
mbed_official	87:085cde657901	1966
mbed_official	87:085cde657901	1967	/* Check if Errors has been detected during transfer */
mbed_official	87:085cde657901	1968	if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
mbed_official	87:085cde657901	1969	{
mbed_official	87:085cde657901	1970	HAL_SPI_ErrorCallback(hspi);
mbed_official	87:085cde657901	1971	}
mbed_official	87:085cde657901	1972	else
mbed_official	87:085cde657901	1973	{
mbed_official	87:085cde657901	1974	HAL_SPI_TxCpltCallback(hspi);
mbed_official	87:085cde657901	1975	}
mbed_official	87:085cde657901	1976	}
mbed_official	87:085cde657901	1977
mbed_official	87:085cde657901	1978	/**
mbed_official	87:085cde657901	1979	* @brief DMA SPI receive process complete callback
mbed_official	226:b062af740e40	1980	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	1981	* the configuration information for the specified DMA module.
mbed_official	87:085cde657901	1982	* @retval None
mbed_official	87:085cde657901	1983	*/
mbed_official	87:085cde657901	1984	static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
mbed_official	87:085cde657901	1985	{
mbed_official	87:085cde657901	1986	__IO uint16_t tmpreg;
mbed_official	369:2e96f1b71984	1987
mbed_official	87:085cde657901	1988	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official	369:2e96f1b71984	1989	/* DMA Normal mode */
mbed_official	369:2e96f1b71984	1990	if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
mbed_official	87:085cde657901	1991	{
mbed_official	369:2e96f1b71984	1992	if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)\|\|(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
mbed_official	87:085cde657901	1993	{
mbed_official	369:2e96f1b71984	1994	/* Disable SPI peripheral */
mbed_official	369:2e96f1b71984	1995	__HAL_SPI_DISABLE(hspi);
mbed_official	87:085cde657901	1996	}
mbed_official	369:2e96f1b71984	1997
mbed_official	369:2e96f1b71984	1998	/* Disable Rx DMA Request */
mbed_official	369:2e96f1b71984	1999	hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
mbed_official	369:2e96f1b71984	2000	/* Disable Tx DMA Request (done by default to handle the case Master RX direction 2 lines) */
mbed_official	369:2e96f1b71984	2001	hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
mbed_official	369:2e96f1b71984	2002
mbed_official	369:2e96f1b71984	2003	hspi->RxXferCount = 0;
mbed_official	369:2e96f1b71984	2004	hspi->State = HAL_SPI_STATE_READY;
mbed_official	369:2e96f1b71984	2005
mbed_official	369:2e96f1b71984	2006
mbed_official	369:2e96f1b71984	2007	/* Reset CRC Calculation */
mbed_official	369:2e96f1b71984	2008	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	87:085cde657901	2009	{
mbed_official	369:2e96f1b71984	2010	/* Wait until RXNE flag is set to send data */
mbed_official	369:2e96f1b71984	2011	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
mbed_official	369:2e96f1b71984	2012	{
mbed_official	369:2e96f1b71984	2013	hspi->ErrorCode \|= HAL_SPI_ERROR_FLAG;
mbed_official	369:2e96f1b71984	2014	}
mbed_official	369:2e96f1b71984	2015
mbed_official	369:2e96f1b71984	2016	/* Read CRC */
mbed_official	369:2e96f1b71984	2017	tmpreg = hspi->Instance->DR;
mbed_official	369:2e96f1b71984	2018
mbed_official	369:2e96f1b71984	2019	/* Wait until RXNE flag is set */
mbed_official	369:2e96f1b71984	2020	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
mbed_official	369:2e96f1b71984	2021	{
mbed_official	369:2e96f1b71984	2022	hspi->ErrorCode \|= HAL_SPI_ERROR_FLAG;
mbed_official	369:2e96f1b71984	2023	}
mbed_official	369:2e96f1b71984	2024
mbed_official	369:2e96f1b71984	2025	/* Check if CRC error occurred */
mbed_official	369:2e96f1b71984	2026	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
mbed_official	369:2e96f1b71984	2027	{
mbed_official	369:2e96f1b71984	2028	hspi->ErrorCode \|= HAL_SPI_ERROR_CRC;
mbed_official	369:2e96f1b71984	2029	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
mbed_official	369:2e96f1b71984	2030	}
mbed_official	87:085cde657901	2031	}
mbed_official	369:2e96f1b71984	2032
mbed_official	369:2e96f1b71984	2033	/* Check if Errors has been detected during transfer */
mbed_official	369:2e96f1b71984	2034	if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
mbed_official	369:2e96f1b71984	2035	{
mbed_official	369:2e96f1b71984	2036	HAL_SPI_ErrorCallback(hspi);
mbed_official	369:2e96f1b71984	2037	}
mbed_official	369:2e96f1b71984	2038	else
mbed_official	369:2e96f1b71984	2039	{
mbed_official	369:2e96f1b71984	2040	HAL_SPI_RxCpltCallback(hspi);
mbed_official	369:2e96f1b71984	2041	}
mbed_official	87:085cde657901	2042	}
mbed_official	87:085cde657901	2043	else
mbed_official	87:085cde657901	2044	{
mbed_official	87:085cde657901	2045	HAL_SPI_RxCpltCallback(hspi);
mbed_official	87:085cde657901	2046	}
mbed_official	87:085cde657901	2047	}
mbed_official	87:085cde657901	2048
mbed_official	87:085cde657901	2049	/**
mbed_official	87:085cde657901	2050	* @brief DMA SPI transmit receive process complete callback
mbed_official	226:b062af740e40	2051	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	2052	* the configuration information for the specified DMA module.
mbed_official	87:085cde657901	2053	* @retval None
mbed_official	87:085cde657901	2054	*/
mbed_official	87:085cde657901	2055	static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
mbed_official	87:085cde657901	2056	{
mbed_official	87:085cde657901	2057	__IO uint16_t tmpreg;
mbed_official	369:2e96f1b71984	2058
mbed_official	87:085cde657901	2059	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official	369:2e96f1b71984	2060	if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
mbed_official	87:085cde657901	2061	{
mbed_official	369:2e96f1b71984	2062	/* Reset CRC Calculation */
mbed_official	369:2e96f1b71984	2063	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	87:085cde657901	2064	{
mbed_official	369:2e96f1b71984	2065	/* Check if CRC is done on going (RXNE flag set) */
mbed_official	369:2e96f1b71984	2066	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) == HAL_OK)
mbed_official	87:085cde657901	2067	{
mbed_official	369:2e96f1b71984	2068	/* Wait until RXNE flag is set to send data */
mbed_official	369:2e96f1b71984	2069	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
mbed_official	369:2e96f1b71984	2070	{
mbed_official	369:2e96f1b71984	2071	hspi->ErrorCode \|= HAL_SPI_ERROR_FLAG;
mbed_official	369:2e96f1b71984	2072	}
mbed_official	369:2e96f1b71984	2073	}
mbed_official	369:2e96f1b71984	2074	/* Read CRC */
mbed_official	369:2e96f1b71984	2075	tmpreg = hspi->Instance->DR;
mbed_official	369:2e96f1b71984	2076
mbed_official	369:2e96f1b71984	2077	/* Check if CRC error occurred */
mbed_official	369:2e96f1b71984	2078	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
mbed_official	369:2e96f1b71984	2079	{
mbed_official	369:2e96f1b71984	2080	hspi->ErrorCode \|= HAL_SPI_ERROR_CRC;
mbed_official	369:2e96f1b71984	2081	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
mbed_official	87:085cde657901	2082	}
mbed_official	87:085cde657901	2083	}
mbed_official	87:085cde657901	2084
mbed_official	369:2e96f1b71984	2085	/* Wait until TXE flag is set to send data */
mbed_official	369:2e96f1b71984	2086	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
mbed_official	369:2e96f1b71984	2087	{
mbed_official	369:2e96f1b71984	2088	hspi->ErrorCode \|= HAL_SPI_ERROR_FLAG;
mbed_official	369:2e96f1b71984	2089	}
mbed_official	369:2e96f1b71984	2090	/* Disable Tx DMA Request */
mbed_official	369:2e96f1b71984	2091	hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
mbed_official	369:2e96f1b71984	2092
mbed_official	369:2e96f1b71984	2093	/* Wait until Busy flag is reset before disabling SPI */
mbed_official	369:2e96f1b71984	2094	if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
mbed_official	369:2e96f1b71984	2095	{
mbed_official	369:2e96f1b71984	2096	hspi->ErrorCode \|= HAL_SPI_ERROR_FLAG;
mbed_official	369:2e96f1b71984	2097	}
mbed_official	369:2e96f1b71984	2098
mbed_official	369:2e96f1b71984	2099	/* Disable Rx DMA Request */
mbed_official	369:2e96f1b71984	2100	hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
mbed_official	369:2e96f1b71984	2101
mbed_official	369:2e96f1b71984	2102	hspi->TxXferCount = 0;
mbed_official	369:2e96f1b71984	2103	hspi->RxXferCount = 0;
mbed_official	369:2e96f1b71984	2104
mbed_official	369:2e96f1b71984	2105	hspi->State = HAL_SPI_STATE_READY;
mbed_official	369:2e96f1b71984	2106
mbed_official	369:2e96f1b71984	2107
mbed_official	369:2e96f1b71984	2108	/* Check if Errors has been detected during transfer */
mbed_official	369:2e96f1b71984	2109	if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
mbed_official	369:2e96f1b71984	2110	{
mbed_official	369:2e96f1b71984	2111	HAL_SPI_ErrorCallback(hspi);
mbed_official	369:2e96f1b71984	2112	}
mbed_official	369:2e96f1b71984	2113	else
mbed_official	369:2e96f1b71984	2114	{
mbed_official	369:2e96f1b71984	2115	HAL_SPI_TxRxCpltCallback(hspi);
mbed_official	369:2e96f1b71984	2116	}
mbed_official	87:085cde657901	2117	}
mbed_official	87:085cde657901	2118	else
mbed_official	87:085cde657901	2119	{
mbed_official	87:085cde657901	2120	HAL_SPI_TxRxCpltCallback(hspi);
mbed_official	87:085cde657901	2121	}
mbed_official	87:085cde657901	2122	}
mbed_official	87:085cde657901	2123
mbed_official	87:085cde657901	2124	/**
mbed_official	369:2e96f1b71984	2125	* @brief DMA SPI half transmit process complete callback
mbed_official	369:2e96f1b71984	2126	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
mbed_official	369:2e96f1b71984	2127	* the configuration information for the specified DMA module.
mbed_official	369:2e96f1b71984	2128	* @retval None
mbed_official	369:2e96f1b71984	2129	*/
mbed_official	369:2e96f1b71984	2130	static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)
mbed_official	369:2e96f1b71984	2131	{
mbed_official	369:2e96f1b71984	2132	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official	369:2e96f1b71984	2133
mbed_official	369:2e96f1b71984	2134	HAL_SPI_TxHalfCpltCallback(hspi);
mbed_official	369:2e96f1b71984	2135	}
mbed_official	369:2e96f1b71984	2136
mbed_official	369:2e96f1b71984	2137	/**
mbed_official	369:2e96f1b71984	2138	* @brief DMA SPI half receive process complete callback
mbed_official	369:2e96f1b71984	2139	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
mbed_official	369:2e96f1b71984	2140	* the configuration information for the specified DMA module.
mbed_official	369:2e96f1b71984	2141	* @retval None
mbed_official	369:2e96f1b71984	2142	*/
mbed_official	369:2e96f1b71984	2143	static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)
mbed_official	369:2e96f1b71984	2144	{
mbed_official	369:2e96f1b71984	2145	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official	369:2e96f1b71984	2146
mbed_official	369:2e96f1b71984	2147	HAL_SPI_RxHalfCpltCallback(hspi);
mbed_official	369:2e96f1b71984	2148	}
mbed_official	369:2e96f1b71984	2149
mbed_official	369:2e96f1b71984	2150	/**
mbed_official	369:2e96f1b71984	2151	* @brief DMA SPI Half transmit receive process complete callback
mbed_official	369:2e96f1b71984	2152	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
mbed_official	369:2e96f1b71984	2153	* the configuration information for the specified DMA module.
mbed_official	369:2e96f1b71984	2154	* @retval None
mbed_official	369:2e96f1b71984	2155	*/
mbed_official	369:2e96f1b71984	2156	static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)
mbed_official	369:2e96f1b71984	2157	{
mbed_official	369:2e96f1b71984	2158	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official	369:2e96f1b71984	2159
mbed_official	369:2e96f1b71984	2160	HAL_SPI_TxRxHalfCpltCallback(hspi);
mbed_official	369:2e96f1b71984	2161	}
mbed_official	369:2e96f1b71984	2162
mbed_official	369:2e96f1b71984	2163	/**
mbed_official	87:085cde657901	2164	* @brief DMA SPI communication error callback
mbed_official	226:b062af740e40	2165	* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	2166	* the configuration information for the specified DMA module.
mbed_official	87:085cde657901	2167	* @retval None
mbed_official	87:085cde657901	2168	*/
mbed_official	87:085cde657901	2169	static void SPI_DMAError(DMA_HandleTypeDef *hdma)
mbed_official	87:085cde657901	2170	{
mbed_official	87:085cde657901	2171	SPI_HandleTypeDef* hspi = (SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official	87:085cde657901	2172	hspi->TxXferCount = 0;
mbed_official	87:085cde657901	2173	hspi->RxXferCount = 0;
mbed_official	87:085cde657901	2174	hspi->State= HAL_SPI_STATE_READY;
mbed_official	87:085cde657901	2175	hspi->ErrorCode \|= HAL_SPI_ERROR_DMA;
mbed_official	87:085cde657901	2176	HAL_SPI_ErrorCallback(hspi);
mbed_official	87:085cde657901	2177	}
mbed_official	87:085cde657901	2178
mbed_official	87:085cde657901	2179	/**
mbed_official	87:085cde657901	2180	* @brief This function handles SPI Communication Timeout.
mbed_official	226:b062af740e40	2181	* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official	226:b062af740e40	2182	* the configuration information for SPI module.
mbed_official	87:085cde657901	2183	* @retval HAL status
mbed_official	87:085cde657901	2184	*/
mbed_official	87:085cde657901	2185	static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
mbed_official	87:085cde657901	2186	{
mbed_official	369:2e96f1b71984	2187	uint32_t tickstart = 0;
mbed_official	87:085cde657901	2188
mbed_official	369:2e96f1b71984	2189	/* Get tick */
mbed_official	369:2e96f1b71984	2190	tickstart = HAL_GetTick();
mbed_official	87:085cde657901	2191
mbed_official	87:085cde657901	2192	/* Wait until flag is set */
mbed_official	87:085cde657901	2193	if(Status == RESET)
mbed_official	87:085cde657901	2194	{
mbed_official	87:085cde657901	2195	while(__HAL_SPI_GET_FLAG(hspi, Flag) == RESET)
mbed_official	87:085cde657901	2196	{
mbed_official	87:085cde657901	2197	if(Timeout != HAL_MAX_DELAY)
mbed_official	87:085cde657901	2198	{
mbed_official	369:2e96f1b71984	2199	if((Timeout == 0)\|\|((HAL_GetTick() - tickstart ) > Timeout))
mbed_official	87:085cde657901	2200	{
mbed_official	87:085cde657901	2201	/* Disable the SPI and reset the CRC: the CRC value should be cleared
mbed_official	87:085cde657901	2202	on both master and slave sides in order to resynchronize the master
mbed_official	87:085cde657901	2203	and slave for their respective CRC calculation */
mbed_official	87:085cde657901	2204
mbed_official	87:085cde657901	2205	/* Disable TXE, RXNE and ERR interrupts for the interrupt process */
mbed_official	87:085cde657901	2206	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_RXNE \| SPI_IT_ERR));
mbed_official	87:085cde657901	2207
mbed_official	87:085cde657901	2208	/* Disable SPI peripheral */
mbed_official	87:085cde657901	2209	__HAL_SPI_DISABLE(hspi);
mbed_official	87:085cde657901	2210
mbed_official	87:085cde657901	2211	/* Reset CRC Calculation */
mbed_official	87:085cde657901	2212	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	87:085cde657901	2213	{
mbed_official	87:085cde657901	2214	__HAL_SPI_RESET_CRC(hspi);
mbed_official	87:085cde657901	2215	}
mbed_official	87:085cde657901	2216
mbed_official	87:085cde657901	2217	hspi->State= HAL_SPI_STATE_READY;
mbed_official	87:085cde657901	2218
mbed_official	87:085cde657901	2219	/* Process Unlocked */
mbed_official	87:085cde657901	2220	__HAL_UNLOCK(hspi);
mbed_official	87:085cde657901	2221
mbed_official	87:085cde657901	2222	return HAL_TIMEOUT;
mbed_official	87:085cde657901	2223	}
mbed_official	87:085cde657901	2224	}
mbed_official	87:085cde657901	2225	}
mbed_official	87:085cde657901	2226	}
mbed_official	87:085cde657901	2227	else
mbed_official	87:085cde657901	2228	{
mbed_official	87:085cde657901	2229	while(__HAL_SPI_GET_FLAG(hspi, Flag) != RESET)
mbed_official	87:085cde657901	2230	{
mbed_official	87:085cde657901	2231	if(Timeout != HAL_MAX_DELAY)
mbed_official	87:085cde657901	2232	{
mbed_official	369:2e96f1b71984	2233	if((Timeout == 0)\|\|((HAL_GetTick() - tickstart ) > Timeout))
mbed_official	87:085cde657901	2234	{
mbed_official	87:085cde657901	2235	/* Disable the SPI and reset the CRC: the CRC value should be cleared
mbed_official	87:085cde657901	2236	on both master and slave sides in order to resynchronize the master
mbed_official	87:085cde657901	2237	and slave for their respective CRC calculation */
mbed_official	87:085cde657901	2238
mbed_official	87:085cde657901	2239	/* Disable TXE, RXNE and ERR interrupts for the interrupt process */
mbed_official	87:085cde657901	2240	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_RXNE \| SPI_IT_ERR));
mbed_official	87:085cde657901	2241
mbed_official	87:085cde657901	2242	/* Disable SPI peripheral */
mbed_official	87:085cde657901	2243	__HAL_SPI_DISABLE(hspi);
mbed_official	87:085cde657901	2244
mbed_official	87:085cde657901	2245	/* Reset CRC Calculation */
mbed_official	87:085cde657901	2246	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	87:085cde657901	2247	{
mbed_official	87:085cde657901	2248	__HAL_SPI_RESET_CRC(hspi);
mbed_official	87:085cde657901	2249	}
mbed_official	87:085cde657901	2250
mbed_official	87:085cde657901	2251	hspi->State= HAL_SPI_STATE_READY;
mbed_official	87:085cde657901	2252
mbed_official	87:085cde657901	2253	/* Process Unlocked */
mbed_official	87:085cde657901	2254	__HAL_UNLOCK(hspi);
mbed_official	87:085cde657901	2255
mbed_official	87:085cde657901	2256	return HAL_TIMEOUT;
mbed_official	87:085cde657901	2257	}
mbed_official	87:085cde657901	2258	}
mbed_official	87:085cde657901	2259	}
mbed_official	87:085cde657901	2260	}
mbed_official	87:085cde657901	2261	return HAL_OK;
mbed_official	87:085cde657901	2262	}
mbed_official	87:085cde657901	2263
mbed_official	87:085cde657901	2264
mbed_official	87:085cde657901	2265	/**
mbed_official	87:085cde657901	2266	* @}
mbed_official	87:085cde657901	2267	*/
mbed_official	87:085cde657901	2268
mbed_official	87:085cde657901	2269	#endif /* HAL_SPI_MODULE_ENABLED */
mbed_official	87:085cde657901	2270	/**
mbed_official	87:085cde657901	2271	* @}
mbed_official	87:085cde657901	2272	*/
mbed_official	87:085cde657901	2273
mbed_official	87:085cde657901	2274	/**
mbed_official	87:085cde657901	2275	* @}
mbed_official	87:085cde657901	2276	*/
mbed_official	87:085cde657901	2277
mbed_official	87:085cde657901	2278	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/