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Last commit 20 Feb 2019 by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_dma2d.c@380:510f0c3515e3, 2014-11-03 (annotated)

Committer:
mbed_official
Date:
Mon Nov 03 10:15:07 2014 +0000
Revision:
380:510f0c3515e3
Parent:
targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_dma2d.c@369:2e96f1b71984
Child:
384:ef87175507f1
Synchronized with git revision 417f470ba9f4882d7079611cbc576afd9c49b0ef



Full URL: https://github.com/mbedmicro/mbed/commit/417f470ba9f4882d7079611cbc576afd9c49b0ef/



Targets: Factorisation of NUCLEO_F401RE and F411RE cmsis folders

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 87:085cde657901 1 /**
mbed_official 87:085cde657901 2 ******************************************************************************
mbed_official 87:085cde657901 3 * @file stm32f4xx_hal_dma2d.c
mbed_official 87:085cde657901 4 * @author MCD Application Team
mbed_official 369:2e96f1b71984 5 * @version V1.1.0
mbed_official 369:2e96f1b71984 6 * @date 19-June-2014
mbed_official 87:085cde657901 7 * @brief DMA2D HAL module driver.
mbed_official 87:085cde657901 8 * This file provides firmware functions to manage the following
mbed_official 87:085cde657901 9 * functionalities of the DMA2D peripheral:
mbed_official 87:085cde657901 10 * + Initialization and de-initialization functions
mbed_official 87:085cde657901 11 * + IO operation functions
mbed_official 87:085cde657901 12 * + Peripheral Control functions
mbed_official 87:085cde657901 13 * + Peripheral State and Errors functions
mbed_official 87:085cde657901 14 *
mbed_official 87:085cde657901 15 @verbatim
mbed_official 87:085cde657901 16 ==============================================================================
mbed_official 87:085cde657901 17 ##### How to use this driver #####
mbed_official 87:085cde657901 18 ==============================================================================
mbed_official 87:085cde657901 19 [..]
mbed_official 87:085cde657901 20 (#) Program the required configuration through following parameters:
mbed_official 87:085cde657901 21 the Transfer Mode, the output color mode and the output offset using
mbed_official 87:085cde657901 22 HAL_DMA2D_Init() function.
mbed_official 87:085cde657901 23
mbed_official 87:085cde657901 24 (#) Program the required configuration through following parameters:
mbed_official 87:085cde657901 25 the input color mode, the input color, input alpha value, alpha mode
mbed_official 87:085cde657901 26 and the input offset using HAL_DMA2D_ConfigLayer() function for foreground
mbed_official 87:085cde657901 27 or/and background layer.
mbed_official 87:085cde657901 28
mbed_official 87:085cde657901 29 *** Polling mode IO operation ***
mbed_official 87:085cde657901 30 =================================
mbed_official 87:085cde657901 31 [..]
mbed_official 87:085cde657901 32 (+) Configure the pdata, Destination and data length and Enable
mbed_official 87:085cde657901 33 the transfer using HAL_DMA2D_Start()
mbed_official 87:085cde657901 34 (+) Wait for end of transfer using HAL_DMA2D_PollForTransfer(), at this stage
mbed_official 87:085cde657901 35 user can specify the value of timeout according to his end application.
mbed_official 87:085cde657901 36
mbed_official 87:085cde657901 37 *** Interrupt mode IO operation ***
mbed_official 87:085cde657901 38 ===================================
mbed_official 87:085cde657901 39 [..]
mbed_official 87:085cde657901 40 (#) Configure the pdata, Destination and data length and Enable
mbed_official 87:085cde657901 41 the transfer using HAL_DMA2D_Start_IT()
mbed_official 87:085cde657901 42 (#) Use HAL_DMA2D_IRQHandler() called under DMA2D_IRQHandler() Interrupt subroutine
mbed_official 87:085cde657901 43 (#) At the end of data transfer HAL_DMA2D_IRQHandler() function is executed and user can
mbed_official 87:085cde657901 44 add his own function by customization of function pointer XferCpltCallback and
mbed_official 87:085cde657901 45 XferErrorCallback (i.e a member of DMA2D handle structure).
mbed_official 87:085cde657901 46
mbed_official 87:085cde657901 47 -@- In Register-to-Memory transfer mode, the pdata parameter is the register
mbed_official 87:085cde657901 48 color, in Memory-to-memory or memory-to-memory with pixel format
mbed_official 369:2e96f1b71984 49 conversion the pdata is the source address.
mbed_official 87:085cde657901 50
mbed_official 87:085cde657901 51 -@- Configure the foreground source address, the background source address,
mbed_official 87:085cde657901 52 the Destination and data length and Enable the transfer using
mbed_official 87:085cde657901 53 HAL_DMA2D_BlendingStart() in polling mode and HAL_DMA2D_BlendingStart_IT()
mbed_official 87:085cde657901 54 in interrupt mode.
mbed_official 87:085cde657901 55
mbed_official 87:085cde657901 56 -@- HAL_DMA2D_BlendingStart() and HAL_DMA2D_BlendingStart_IT() functions
mbed_official 87:085cde657901 57 are used if the memory to memory with blending transfer mode is selected.
mbed_official 87:085cde657901 58
mbed_official 87:085cde657901 59 (#) Optionally, configure and enable the CLUT using HAL_DMA2D_ConfigCLUT()
mbed_official 87:085cde657901 60 HAL_DMA2D_EnableCLUT() functions.
mbed_official 87:085cde657901 61
mbed_official 87:085cde657901 62 (#) Optionally, configure and enable LineInterrupt using the following function:
mbed_official 87:085cde657901 63 HAL_DMA2D_ProgramLineEvent().
mbed_official 87:085cde657901 64
mbed_official 87:085cde657901 65 (#) The transfer can be suspended, continued and aborted using the following
mbed_official 87:085cde657901 66 functions: HAL_DMA2D_Suspend(), HAL_DMA2D_Resume(), HAL_DMA2D_Abort().
mbed_official 87:085cde657901 67
mbed_official 87:085cde657901 68 (#) To control DMA2D state you can use the following function: HAL_DMA2D_GetState()
mbed_official 87:085cde657901 69
mbed_official 87:085cde657901 70 *** DMA2D HAL driver macros list ***
mbed_official 87:085cde657901 71 =============================================
mbed_official 87:085cde657901 72 [..]
mbed_official 226:b062af740e40 73 Below the list of most used macros in DMA2D HAL driver :
mbed_official 87:085cde657901 74
mbed_official 87:085cde657901 75 (+) __HAL_DMA2D_ENABLE: Enable the DMA2D peripheral.
mbed_official 87:085cde657901 76 (+) __HAL_DMA2D_DISABLE: Disable the DMA2D peripheral.
mbed_official 87:085cde657901 77 (+) __HAL_DMA2D_GET_FLAG: Get the DMA2D pending flags.
mbed_official 226:b062af740e40 78 (+) __HAL_DMA2D_CLEAR_FLAG: Clear the DMA2D pending flags.
mbed_official 226:b062af740e40 79 (+) __HAL_DMA2D_ENABLE_IT: Enable the specified DMA2D interrupts.
mbed_official 226:b062af740e40 80 (+) __HAL_DMA2D_DISABLE_IT: Disable the specified DMA2D interrupts.
mbed_official 226:b062af740e40 81 (+) __HAL_DMA2D_GET_IT_SOURCE: Check whether the specified DMA2D interrupt has occurred or not.
mbed_official 87:085cde657901 82
mbed_official 87:085cde657901 83 [..]
mbed_official 87:085cde657901 84 (@) You can refer to the DMA2D HAL driver header file for more useful macros
mbed_official 87:085cde657901 85
mbed_official 87:085cde657901 86 @endverbatim
mbed_official 87:085cde657901 87 ******************************************************************************
mbed_official 87:085cde657901 88 * @attention
mbed_official 87:085cde657901 89 *
mbed_official 87:085cde657901 90 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
mbed_official 87:085cde657901 91 *
mbed_official 87:085cde657901 92 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 87:085cde657901 93 * are permitted provided that the following conditions are met:
mbed_official 87:085cde657901 94 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 87:085cde657901 95 * this list of conditions and the following disclaimer.
mbed_official 87:085cde657901 96 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 87:085cde657901 97 * this list of conditions and the following disclaimer in the documentation
mbed_official 87:085cde657901 98 * and/or other materials provided with the distribution.
mbed_official 87:085cde657901 99 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 87:085cde657901 100 * may be used to endorse or promote products derived from this software
mbed_official 87:085cde657901 101 * without specific prior written permission.
mbed_official 87:085cde657901 102 *
mbed_official 87:085cde657901 103 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 87:085cde657901 104 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 87:085cde657901 105 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 87:085cde657901 106 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 87:085cde657901 107 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 87:085cde657901 108 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 87:085cde657901 109 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 87:085cde657901 110 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 87:085cde657901 111 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 87:085cde657901 112 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 87:085cde657901 113 *
mbed_official 87:085cde657901 114 ******************************************************************************
mbed_official 87:085cde657901 115 */
mbed_official 87:085cde657901 116
mbed_official 87:085cde657901 117 /* Includes ------------------------------------------------------------------*/
mbed_official 87:085cde657901 118 #include "stm32f4xx_hal.h"
mbed_official 87:085cde657901 119
mbed_official 87:085cde657901 120 /** @addtogroup STM32F4xx_HAL_Driver
mbed_official 87:085cde657901 121 * @{
mbed_official 87:085cde657901 122 */
mbed_official 87:085cde657901 123 /** @defgroup DMA2D
mbed_official 87:085cde657901 124 * @brief DMA2D HAL module driver
mbed_official 87:085cde657901 125 * @{
mbed_official 87:085cde657901 126 */
mbed_official 87:085cde657901 127
mbed_official 87:085cde657901 128 #ifdef HAL_DMA2D_MODULE_ENABLED
mbed_official 87:085cde657901 129
mbed_official 106:ced8cbb51063 130 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
mbed_official 87:085cde657901 131
mbed_official 87:085cde657901 132 /* Private typedef -----------------------------------------------------------*/
mbed_official 87:085cde657901 133 /* Private define ------------------------------------------------------------*/
mbed_official 87:085cde657901 134 #define HAL_TIMEOUT_DMA2D_ABORT ((uint32_t)1000) /* 1s */
mbed_official 87:085cde657901 135 #define HAL_TIMEOUT_DMA2D_SUSPEND ((uint32_t)1000) /* 1s */
mbed_official 87:085cde657901 136 /* Private macro -------------------------------------------------------------*/
mbed_official 87:085cde657901 137 /* Private variables ---------------------------------------------------------*/
mbed_official 87:085cde657901 138 /* Private function prototypes -----------------------------------------------*/
mbed_official 87:085cde657901 139 static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Heigh);
mbed_official 87:085cde657901 140
mbed_official 87:085cde657901 141 /* Private functions ---------------------------------------------------------*/
mbed_official 87:085cde657901 142
mbed_official 87:085cde657901 143 /** @defgroup DMA2D_Private_Functions
mbed_official 87:085cde657901 144 * @{
mbed_official 87:085cde657901 145 */
mbed_official 87:085cde657901 146
mbed_official 87:085cde657901 147 /** @defgroup DMA2D_Group1 Initialization and Configuration functions
mbed_official 87:085cde657901 148 * @brief Initialization and Configuration functions
mbed_official 87:085cde657901 149 *
mbed_official 87:085cde657901 150 @verbatim
mbed_official 87:085cde657901 151 ===============================================================================
mbed_official 87:085cde657901 152 ##### Initialization and Configuration functions #####
mbed_official 87:085cde657901 153 ===============================================================================
mbed_official 87:085cde657901 154 [..] This section provides functions allowing to:
mbed_official 87:085cde657901 155 (+) Initialize and configure the DMA2D
mbed_official 87:085cde657901 156 (+) De-initialize the DMA2D
mbed_official 87:085cde657901 157
mbed_official 87:085cde657901 158 @endverbatim
mbed_official 87:085cde657901 159 * @{
mbed_official 87:085cde657901 160 */
mbed_official 87:085cde657901 161
mbed_official 87:085cde657901 162 /**
mbed_official 87:085cde657901 163 * @brief Initializes the DMA2D according to the specified
mbed_official 87:085cde657901 164 * parameters in the DMA2D_InitTypeDef and create the associated handle.
mbed_official 87:085cde657901 165 * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
mbed_official 87:085cde657901 166 * the configuration information for the DMA2D.
mbed_official 87:085cde657901 167 * @retval HAL status
mbed_official 87:085cde657901 168 */
mbed_official 87:085cde657901 169 HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d)
mbed_official 87:085cde657901 170 {
mbed_official 87:085cde657901 171 uint32_t tmp = 0;
mbed_official 87:085cde657901 172
mbed_official 87:085cde657901 173 /* Check the DMA2D peripheral state */
mbed_official 87:085cde657901 174 if(hdma2d == NULL)
mbed_official 87:085cde657901 175 {
mbed_official 87:085cde657901 176 return HAL_ERROR;
mbed_official 87:085cde657901 177 }
mbed_official 87:085cde657901 178
mbed_official 87:085cde657901 179 /* Check the parameters */
mbed_official 87:085cde657901 180 assert_param(IS_DMA2D_ALL_INSTANCE(hdma2d->Instance));
mbed_official 87:085cde657901 181 assert_param(IS_DMA2D_MODE(hdma2d->Init.Mode));
mbed_official 87:085cde657901 182 assert_param(IS_DMA2D_CMODE(hdma2d->Init.ColorMode));
mbed_official 87:085cde657901 183 assert_param(IS_DMA2D_OFFSET(hdma2d->Init.OutputOffset));
mbed_official 87:085cde657901 184
mbed_official 87:085cde657901 185 if(hdma2d->State == HAL_DMA2D_STATE_RESET)
mbed_official 87:085cde657901 186 {
mbed_official 87:085cde657901 187 /* Init the low level hardware */
mbed_official 87:085cde657901 188 HAL_DMA2D_MspInit(hdma2d);
mbed_official 87:085cde657901 189 }
mbed_official 87:085cde657901 190
mbed_official 87:085cde657901 191 /* Change DMA2D peripheral state */
mbed_official 87:085cde657901 192 hdma2d->State = HAL_DMA2D_STATE_BUSY;
mbed_official 87:085cde657901 193
mbed_official 87:085cde657901 194 /* DMA2D CR register configuration -------------------------------------------*/
mbed_official 87:085cde657901 195 /* Get the CR register value */
mbed_official 87:085cde657901 196 tmp = hdma2d->Instance->CR;
mbed_official 87:085cde657901 197
mbed_official 87:085cde657901 198 /* Clear Mode bits */
mbed_official 87:085cde657901 199 tmp &= (uint32_t)~DMA2D_CR_MODE;
mbed_official 87:085cde657901 200
mbed_official 87:085cde657901 201 /* Prepare the value to be wrote to the CR register */
mbed_official 87:085cde657901 202 tmp |= hdma2d->Init.Mode;
mbed_official 87:085cde657901 203
mbed_official 87:085cde657901 204 /* Write to DMA2D CR register */
mbed_official 87:085cde657901 205 hdma2d->Instance->CR = tmp;
mbed_official 87:085cde657901 206
mbed_official 87:085cde657901 207 /* DMA2D OPFCCR register configuration ---------------------------------------*/
mbed_official 87:085cde657901 208 /* Get the OPFCCR register value */
mbed_official 87:085cde657901 209 tmp = hdma2d->Instance->OPFCCR;
mbed_official 87:085cde657901 210
mbed_official 87:085cde657901 211 /* Clear Color Mode bits */
mbed_official 87:085cde657901 212 tmp &= (uint32_t)~DMA2D_OPFCCR_CM;
mbed_official 87:085cde657901 213
mbed_official 87:085cde657901 214 /* Prepare the value to be wrote to the OPFCCR register */
mbed_official 87:085cde657901 215 tmp |= hdma2d->Init.ColorMode;
mbed_official 87:085cde657901 216
mbed_official 87:085cde657901 217 /* Write to DMA2D OPFCCR register */
mbed_official 87:085cde657901 218 hdma2d->Instance->OPFCCR = tmp;
mbed_official 87:085cde657901 219
mbed_official 87:085cde657901 220 /* DMA2D OOR register configuration ------------------------------------------*/
mbed_official 87:085cde657901 221 /* Get the OOR register value */
mbed_official 87:085cde657901 222 tmp = hdma2d->Instance->OOR;
mbed_official 87:085cde657901 223
mbed_official 87:085cde657901 224 /* Clear Offset bits */
mbed_official 87:085cde657901 225 tmp &= (uint32_t)~DMA2D_OOR_LO;
mbed_official 87:085cde657901 226
mbed_official 87:085cde657901 227 /* Prepare the value to be wrote to the OOR register */
mbed_official 87:085cde657901 228 tmp |= hdma2d->Init.OutputOffset;
mbed_official 87:085cde657901 229
mbed_official 87:085cde657901 230 /* Write to DMA2D OOR register */
mbed_official 87:085cde657901 231 hdma2d->Instance->OOR = tmp;
mbed_official 87:085cde657901 232
mbed_official 87:085cde657901 233 /* Update error code */
mbed_official 87:085cde657901 234 hdma2d->ErrorCode = HAL_DMA2D_ERROR_NONE;
mbed_official 87:085cde657901 235
mbed_official 87:085cde657901 236 /* Initialize the DMA2D state*/
mbed_official 87:085cde657901 237 hdma2d->State = HAL_DMA2D_STATE_READY;
mbed_official 87:085cde657901 238
mbed_official 87:085cde657901 239 return HAL_OK;
mbed_official 87:085cde657901 240 }
mbed_official 87:085cde657901 241
mbed_official 87:085cde657901 242 /**
mbed_official 87:085cde657901 243 * @brief Deinitializes the DMA2D peripheral registers to their default reset
mbed_official 87:085cde657901 244 * values.
mbed_official 87:085cde657901 245 * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
mbed_official 87:085cde657901 246 * the configuration information for the DMA2D.
mbed_official 87:085cde657901 247 * @retval None
mbed_official 87:085cde657901 248 */
mbed_official 87:085cde657901 249
mbed_official 87:085cde657901 250 HAL_StatusTypeDef HAL_DMA2D_DeInit(DMA2D_HandleTypeDef *hdma2d)
mbed_official 87:085cde657901 251 {
mbed_official 87:085cde657901 252 /* Check the DMA2D peripheral state */
mbed_official 87:085cde657901 253 if(hdma2d == NULL)
mbed_official 87:085cde657901 254 {
mbed_official 87:085cde657901 255 return HAL_ERROR;
mbed_official 87:085cde657901 256 }
mbed_official 87:085cde657901 257
mbed_official 87:085cde657901 258 /* DeInit the low level hardware */
mbed_official 87:085cde657901 259 HAL_DMA2D_MspDeInit(hdma2d);
mbed_official 87:085cde657901 260
mbed_official 87:085cde657901 261 /* Update error code */
mbed_official 87:085cde657901 262 hdma2d->ErrorCode = HAL_DMA2D_ERROR_NONE;
mbed_official 87:085cde657901 263
mbed_official 87:085cde657901 264 /* Initialize the DMA2D state*/
mbed_official 87:085cde657901 265 hdma2d->State = HAL_DMA2D_STATE_RESET;
mbed_official 87:085cde657901 266
mbed_official 106:ced8cbb51063 267 /* Release Lock */
mbed_official 106:ced8cbb51063 268 __HAL_UNLOCK(hdma2d);
mbed_official 106:ced8cbb51063 269
mbed_official 87:085cde657901 270 return HAL_OK;
mbed_official 87:085cde657901 271 }
mbed_official 87:085cde657901 272
mbed_official 87:085cde657901 273 /**
mbed_official 87:085cde657901 274 * @brief Initializes the DMA2D MSP.
mbed_official 87:085cde657901 275 * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
mbed_official 87:085cde657901 276 * the configuration information for the DMA2D.
mbed_official 87:085cde657901 277 * @retval None
mbed_official 87:085cde657901 278 */
mbed_official 87:085cde657901 279 __weak void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d)
mbed_official 87:085cde657901 280 {
mbed_official 87:085cde657901 281 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 87:085cde657901 282 the HAL_DMA2D_MspInit could be implemented in the user file
mbed_official 87:085cde657901 283 */
mbed_official 87:085cde657901 284 }
mbed_official 87:085cde657901 285
mbed_official 87:085cde657901 286 /**
mbed_official 87:085cde657901 287 * @brief DeInitializes the DMA2D MSP.
mbed_official 87:085cde657901 288 * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
mbed_official 87:085cde657901 289 * the configuration information for the DMA2D.
mbed_official 87:085cde657901 290 * @retval None
mbed_official 87:085cde657901 291 */
mbed_official 87:085cde657901 292 __weak void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d)
mbed_official 87:085cde657901 293 {
mbed_official 87:085cde657901 294 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 87:085cde657901 295 the HAL_DMA2D_MspDeInit could be implemented in the user file
mbed_official 87:085cde657901 296 */
mbed_official 87:085cde657901 297 }
mbed_official 87:085cde657901 298
mbed_official 87:085cde657901 299 /**
mbed_official 87:085cde657901 300 * @}
mbed_official 87:085cde657901 301 */
mbed_official 87:085cde657901 302
mbed_official 87:085cde657901 303 /** @defgroup DMA2D_Group2 IO operation functions
mbed_official 87:085cde657901 304 * @brief IO operation functions
mbed_official 87:085cde657901 305 *
mbed_official 87:085cde657901 306 @verbatim
mbed_official 87:085cde657901 307 ===============================================================================
mbed_official 87:085cde657901 308 ##### IO operation functions #####
mbed_official 87:085cde657901 309 ===============================================================================
mbed_official 87:085cde657901 310 [..] This section provides functions allowing to:
mbed_official 87:085cde657901 311 (+) Configure the pdata, destination address and data size and
mbed_official 87:085cde657901 312 Start DMA2D transfer.
mbed_official 87:085cde657901 313 (+) Configure the source for foreground and background, destination address
mbed_official 87:085cde657901 314 and data size and Start MultiBuffer DMA2D transfer.
mbed_official 87:085cde657901 315 (+) Configure the pdata, destination address and data size and
mbed_official 87:085cde657901 316 Start DMA2D transfer with interrupt.
mbed_official 87:085cde657901 317 (+) Configure the source for foreground and background, destination address
mbed_official 87:085cde657901 318 and data size and Start MultiBuffer DMA2D transfer with interrupt.
mbed_official 87:085cde657901 319 (+) Abort DMA2D transfer.
mbed_official 87:085cde657901 320 (+) Suspend DMA2D transfer.
mbed_official 87:085cde657901 321 (+) Continue DMA2D transfer.
mbed_official 226:b062af740e40 322 (+) Poll for transfer complete.
mbed_official 226:b062af740e40 323 (+) handle DMA2D interrupt request.
mbed_official 87:085cde657901 324
mbed_official 87:085cde657901 325 @endverbatim
mbed_official 87:085cde657901 326 * @{
mbed_official 87:085cde657901 327 */
mbed_official 87:085cde657901 328
mbed_official 87:085cde657901 329 /**
mbed_official 87:085cde657901 330 * @brief Start the DMA2D Transfer.
mbed_official 87:085cde657901 331 * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
mbed_official 87:085cde657901 332 * the configuration information for the DMA2D.
mbed_official 87:085cde657901 333 * @param pdata: Configure the source memory Buffer address if
mbed_official 87:085cde657901 334 * the memory to memory or memory to memory with pixel format
mbed_official 87:085cde657901 335 * conversion DMA2D mode is selected, and configure
mbed_official 369:2e96f1b71984 336 * the color value if register to memory DMA2D mode is selected.
mbed_official 87:085cde657901 337 * @param DstAddress: The destination memory Buffer address.
mbed_official 87:085cde657901 338 * @param Width: The width of data to be transferred from source to destination.
mbed_official 87:085cde657901 339 * @param Heigh: The heigh of data to be transferred from source to destination.
mbed_official 87:085cde657901 340 * @retval HAL status
mbed_official 87:085cde657901 341 */
mbed_official 87:085cde657901 342 HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Heigh)
mbed_official 87:085cde657901 343 {
mbed_official 87:085cde657901 344 /* Process locked */
mbed_official 87:085cde657901 345 __HAL_LOCK(hdma2d);
mbed_official 87:085cde657901 346
mbed_official 87:085cde657901 347 /* Change DMA2D peripheral state */
mbed_official 87:085cde657901 348 hdma2d->State = HAL_DMA2D_STATE_BUSY;
mbed_official 87:085cde657901 349
mbed_official 87:085cde657901 350 /* Check the parameters */
mbed_official 87:085cde657901 351 assert_param(IS_DMA2D_LINE(Heigh));
mbed_official 87:085cde657901 352 assert_param(IS_DMA2D_PIXEL(Width));
mbed_official 87:085cde657901 353
mbed_official 87:085cde657901 354 /* Disable the Peripheral */
mbed_official 87:085cde657901 355 __HAL_DMA2D_DISABLE(hdma2d);
mbed_official 87:085cde657901 356
mbed_official 87:085cde657901 357 /* Configure the source, destination address and the data size */
mbed_official 87:085cde657901 358 DMA2D_SetConfig(hdma2d, pdata, DstAddress, Width, Heigh);
mbed_official 87:085cde657901 359
mbed_official 87:085cde657901 360 /* Enable the Peripheral */
mbed_official 87:085cde657901 361 __HAL_DMA2D_ENABLE(hdma2d);
mbed_official 87:085cde657901 362
mbed_official 87:085cde657901 363 return HAL_OK;
mbed_official 87:085cde657901 364 }
mbed_official 87:085cde657901 365
mbed_official 87:085cde657901 366 /**
mbed_official 87:085cde657901 367 * @brief Start the DMA2D Transfer with interrupt enabled.
mbed_official 87:085cde657901 368 * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
mbed_official 87:085cde657901 369 * the configuration information for the DMA2D.
mbed_official 87:085cde657901 370 * @param pdata: Configure the source memory Buffer address if
mbed_official 87:085cde657901 371 * the memory to memory or memory to memory with pixel format
mbed_official 87:085cde657901 372 * conversion DMA2D mode is selected, and configure
mbed_official 369:2e96f1b71984 373 * the color value if register to memory DMA2D mode is selected.
mbed_official 87:085cde657901 374 * @param DstAddress: The destination memory Buffer address.
mbed_official 87:085cde657901 375 * @param Width: The width of data to be transferred from source to destination.
mbed_official 87:085cde657901 376 * @param Heigh: The heigh of data to be transferred from source to destination.
mbed_official 87:085cde657901 377 * @retval HAL status
mbed_official 87:085cde657901 378 */
mbed_official 87:085cde657901 379 HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Heigh)
mbed_official 87:085cde657901 380 {
mbed_official 87:085cde657901 381 /* Process locked */
mbed_official 87:085cde657901 382 __HAL_LOCK(hdma2d);
mbed_official 87:085cde657901 383
mbed_official 87:085cde657901 384 /* Change DMA2D peripheral state */
mbed_official 87:085cde657901 385 hdma2d->State = HAL_DMA2D_STATE_BUSY;
mbed_official 87:085cde657901 386
mbed_official 87:085cde657901 387 /* Check the parameters */
mbed_official 87:085cde657901 388 assert_param(IS_DMA2D_LINE(Heigh));
mbed_official 87:085cde657901 389 assert_param(IS_DMA2D_PIXEL(Width));
mbed_official 87:085cde657901 390
mbed_official 87:085cde657901 391 /* Disable the Peripheral */
mbed_official 87:085cde657901 392 __HAL_DMA2D_DISABLE(hdma2d);
mbed_official 87:085cde657901 393
mbed_official 87:085cde657901 394 /* Configure the source, destination address and the data size */
mbed_official 87:085cde657901 395 DMA2D_SetConfig(hdma2d, pdata, DstAddress, Width, Heigh);
mbed_official 87:085cde657901 396
mbed_official 87:085cde657901 397 /* Enable the transfer complete interrupt */
mbed_official 87:085cde657901 398 __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC);
mbed_official 87:085cde657901 399
mbed_official 87:085cde657901 400 /* Enable the transfer Error interrupt */
mbed_official 87:085cde657901 401 __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TE);
mbed_official 87:085cde657901 402
mbed_official 87:085cde657901 403 /* Enable the Peripheral */
mbed_official 87:085cde657901 404 __HAL_DMA2D_ENABLE(hdma2d);
mbed_official 87:085cde657901 405
mbed_official 87:085cde657901 406 /* Enable the configuration error interrupt */
mbed_official 87:085cde657901 407 __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CE);
mbed_official 87:085cde657901 408
mbed_official 87:085cde657901 409 return HAL_OK;
mbed_official 87:085cde657901 410 }
mbed_official 87:085cde657901 411
mbed_official 87:085cde657901 412 /**
mbed_official 87:085cde657901 413 * @brief Start the multi-source DMA2D Transfer.
mbed_official 87:085cde657901 414 * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
mbed_official 87:085cde657901 415 * the configuration information for the DMA2D.
mbed_official 87:085cde657901 416 * @param SrcAddress1: The source memory Buffer address of the foreground layer.
mbed_official 369:2e96f1b71984 417 * @param SrcAddress2: The source memory Buffer address of the background layer.
mbed_official 87:085cde657901 418 * @param DstAddress: The destination memory Buffer address
mbed_official 87:085cde657901 419 * @param Width: The width of data to be transferred from source to destination.
mbed_official 87:085cde657901 420 * @param Heigh: The heigh of data to be transferred from source to destination.
mbed_official 87:085cde657901 421 * @retval HAL status
mbed_official 87:085cde657901 422 */
mbed_official 87:085cde657901 423 HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Heigh)
mbed_official 87:085cde657901 424 {
mbed_official 87:085cde657901 425 /* Process locked */
mbed_official 87:085cde657901 426 __HAL_LOCK(hdma2d);
mbed_official 87:085cde657901 427
mbed_official 87:085cde657901 428 /* Change DMA2D peripheral state */
mbed_official 87:085cde657901 429 hdma2d->State = HAL_DMA2D_STATE_BUSY;
mbed_official 87:085cde657901 430
mbed_official 87:085cde657901 431 /* Check the parameters */
mbed_official 87:085cde657901 432 assert_param(IS_DMA2D_LINE(Heigh));
mbed_official 87:085cde657901 433 assert_param(IS_DMA2D_PIXEL(Width));
mbed_official 87:085cde657901 434
mbed_official 87:085cde657901 435 /* Disable the Peripheral */
mbed_official 87:085cde657901 436 __HAL_DMA2D_DISABLE(hdma2d);
mbed_official 87:085cde657901 437
mbed_official 87:085cde657901 438 /* Configure DMA2D Stream source2 address */
mbed_official 87:085cde657901 439 hdma2d->Instance->BGMAR = SrcAddress2;
mbed_official 87:085cde657901 440
mbed_official 87:085cde657901 441 /* Configure the source, destination address and the data size */
mbed_official 87:085cde657901 442 DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Heigh);
mbed_official 87:085cde657901 443
mbed_official 87:085cde657901 444 /* Enable the Peripheral */
mbed_official 87:085cde657901 445 __HAL_DMA2D_ENABLE(hdma2d);
mbed_official 87:085cde657901 446
mbed_official 87:085cde657901 447 return HAL_OK;
mbed_official 87:085cde657901 448 }
mbed_official 87:085cde657901 449
mbed_official 87:085cde657901 450 /**
mbed_official 87:085cde657901 451 * @brief Start the multi-source DMA2D Transfer with interrupt enabled.
mbed_official 87:085cde657901 452 * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
mbed_official 87:085cde657901 453 * the configuration information for the DMA2D.
mbed_official 87:085cde657901 454 * @param SrcAddress1: The source memory Buffer address of the foreground layer.
mbed_official 369:2e96f1b71984 455 * @param SrcAddress2: The source memory Buffer address of the background layer.
mbed_official 87:085cde657901 456 * @param DstAddress: The destination memory Buffer address.
mbed_official 87:085cde657901 457 * @param Width: The width of data to be transferred from source to destination.
mbed_official 87:085cde657901 458 * @param Heigh: The heigh of data to be transferred from source to destination.
mbed_official 87:085cde657901 459 * @retval HAL status
mbed_official 87:085cde657901 460 */
mbed_official 87:085cde657901 461 HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Heigh)
mbed_official 87:085cde657901 462 {
mbed_official 87:085cde657901 463 /* Process locked */
mbed_official 87:085cde657901 464 __HAL_LOCK(hdma2d);
mbed_official 87:085cde657901 465
mbed_official 87:085cde657901 466 /* Change DMA2D peripheral state */
mbed_official 87:085cde657901 467 hdma2d->State = HAL_DMA2D_STATE_BUSY;
mbed_official 87:085cde657901 468
mbed_official 87:085cde657901 469 /* Check the parameters */
mbed_official 87:085cde657901 470 assert_param(IS_DMA2D_LINE(Heigh));
mbed_official 87:085cde657901 471 assert_param(IS_DMA2D_PIXEL(Width));
mbed_official 87:085cde657901 472
mbed_official 87:085cde657901 473 /* Disable the Peripheral */
mbed_official 87:085cde657901 474 __HAL_DMA2D_DISABLE(hdma2d);
mbed_official 369:2e96f1b71984 475
mbed_official 369:2e96f1b71984 476 /* Configure DMA2D Stream source2 address */
mbed_official 369:2e96f1b71984 477 hdma2d->Instance->BGMAR = SrcAddress2;
mbed_official 87:085cde657901 478
mbed_official 87:085cde657901 479 /* Configure the source, destination address and the data size */
mbed_official 87:085cde657901 480 DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Heigh);
mbed_official 87:085cde657901 481
mbed_official 87:085cde657901 482 /* Enable the configuration error interrupt */
mbed_official 87:085cde657901 483 __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CE);
mbed_official 87:085cde657901 484
mbed_official 87:085cde657901 485 /* Enable the transfer complete interrupt */
mbed_official 87:085cde657901 486 __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC);
mbed_official 87:085cde657901 487
mbed_official 87:085cde657901 488 /* Enable the transfer Error interrupt */
mbed_official 87:085cde657901 489 __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TE);
mbed_official 87:085cde657901 490
mbed_official 87:085cde657901 491 /* Enable the Peripheral */
mbed_official 87:085cde657901 492 __HAL_DMA2D_ENABLE(hdma2d);
mbed_official 87:085cde657901 493
mbed_official 87:085cde657901 494 return HAL_OK;
mbed_official 87:085cde657901 495 }
mbed_official 87:085cde657901 496
mbed_official 87:085cde657901 497 /**
mbed_official 87:085cde657901 498 * @brief Abort the DMA2D Transfer.
mbed_official 87:085cde657901 499 * @param hdma2d : pointer to a DMA2D_HandleTypeDef structure that contains
mbed_official 87:085cde657901 500 * the configuration information for the DMA2D.
mbed_official 87:085cde657901 501 * @retval HAL status
mbed_official 87:085cde657901 502 */
mbed_official 87:085cde657901 503 HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d)
mbed_official 87:085cde657901 504 {
mbed_official 369:2e96f1b71984 505 uint32_t tickstart = 0;
mbed_official 87:085cde657901 506
mbed_official 87:085cde657901 507 /* Disable the DMA2D */
mbed_official 87:085cde657901 508 __HAL_DMA2D_DISABLE(hdma2d);
mbed_official 87:085cde657901 509
mbed_official 369:2e96f1b71984 510 /* Get tick */
mbed_official 369:2e96f1b71984 511 tickstart = HAL_GetTick();
mbed_official 87:085cde657901 512
mbed_official 87:085cde657901 513 /* Check if the DMA2D is effectively disabled */
mbed_official 87:085cde657901 514 while((hdma2d->Instance->CR & DMA2D_CR_START) != 0)
mbed_official 87:085cde657901 515 {
mbed_official 369:2e96f1b71984 516 if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA2D_ABORT)
mbed_official 87:085cde657901 517 {
mbed_official 87:085cde657901 518 /* Update error code */
mbed_official 87:085cde657901 519 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
mbed_official 87:085cde657901 520
mbed_official 87:085cde657901 521 /* Change the DMA2D state */
mbed_official 87:085cde657901 522 hdma2d->State= HAL_DMA2D_STATE_TIMEOUT;
mbed_official 87:085cde657901 523
mbed_official 87:085cde657901 524 /* Process Unlocked */
mbed_official 87:085cde657901 525 __HAL_UNLOCK(hdma2d);
mbed_official 87:085cde657901 526
mbed_official 87:085cde657901 527 return HAL_TIMEOUT;
mbed_official 87:085cde657901 528 }
mbed_official 87:085cde657901 529 }
mbed_official 87:085cde657901 530 /* Process Unlocked */
mbed_official 87:085cde657901 531 __HAL_UNLOCK(hdma2d);
mbed_official 87:085cde657901 532
mbed_official 87:085cde657901 533 /* Change the DMA2D state*/
mbed_official 87:085cde657901 534 hdma2d->State = HAL_DMA2D_STATE_READY;
mbed_official 87:085cde657901 535
mbed_official 87:085cde657901 536 return HAL_OK;
mbed_official 87:085cde657901 537 }
mbed_official 87:085cde657901 538
mbed_official 87:085cde657901 539 /**
mbed_official 87:085cde657901 540 * @brief Suspend the DMA2D Transfer.
mbed_official 87:085cde657901 541 * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
mbed_official 87:085cde657901 542 * the configuration information for the DMA2D.
mbed_official 87:085cde657901 543 * @retval HAL status
mbed_official 87:085cde657901 544 */
mbed_official 87:085cde657901 545 HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d)
mbed_official 87:085cde657901 546 {
mbed_official 369:2e96f1b71984 547 uint32_t tickstart = 0;
mbed_official 87:085cde657901 548
mbed_official 87:085cde657901 549 /* Suspend the DMA2D transfer */
mbed_official 87:085cde657901 550 hdma2d->Instance->CR |= DMA2D_CR_SUSP;
mbed_official 87:085cde657901 551
mbed_official 369:2e96f1b71984 552 /* Get tick */
mbed_official 369:2e96f1b71984 553 tickstart = HAL_GetTick();
mbed_official 87:085cde657901 554
mbed_official 87:085cde657901 555 /* Check if the DMA2D is effectively suspended */
mbed_official 87:085cde657901 556 while((hdma2d->Instance->CR & DMA2D_CR_SUSP) != DMA2D_CR_SUSP)
mbed_official 87:085cde657901 557 {
mbed_official 369:2e96f1b71984 558 if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA2D_SUSPEND)
mbed_official 87:085cde657901 559 {
mbed_official 87:085cde657901 560 /* Update error code */
mbed_official 87:085cde657901 561 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
mbed_official 87:085cde657901 562
mbed_official 87:085cde657901 563 /* Change the DMA2D state */
mbed_official 87:085cde657901 564 hdma2d->State= HAL_DMA2D_STATE_TIMEOUT;
mbed_official 87:085cde657901 565
mbed_official 87:085cde657901 566 return HAL_TIMEOUT;
mbed_official 87:085cde657901 567 }
mbed_official 87:085cde657901 568 }
mbed_official 87:085cde657901 569 /* Change the DMA2D state*/
mbed_official 87:085cde657901 570 hdma2d->State = HAL_DMA2D_STATE_SUSPEND;
mbed_official 87:085cde657901 571
mbed_official 87:085cde657901 572 return HAL_OK;
mbed_official 87:085cde657901 573 }
mbed_official 87:085cde657901 574
mbed_official 87:085cde657901 575 /**
mbed_official 87:085cde657901 576 * @brief Resume the DMA2D Transfer.
mbed_official 87:085cde657901 577 * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
mbed_official 87:085cde657901 578 * the configuration information for the DMA2D.
mbed_official 87:085cde657901 579 * @retval HAL status
mbed_official 87:085cde657901 580 */
mbed_official 87:085cde657901 581 HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d)
mbed_official 87:085cde657901 582 {
mbed_official 87:085cde657901 583 /* Resume the DMA2D transfer */
mbed_official 87:085cde657901 584 hdma2d->Instance->CR &= ~DMA2D_CR_SUSP;
mbed_official 87:085cde657901 585
mbed_official 87:085cde657901 586 /* Change the DMA2D state*/
mbed_official 87:085cde657901 587 hdma2d->State = HAL_DMA2D_STATE_BUSY;
mbed_official 87:085cde657901 588
mbed_official 87:085cde657901 589 return HAL_OK;
mbed_official 87:085cde657901 590 }
mbed_official 87:085cde657901 591
mbed_official 87:085cde657901 592 /**
mbed_official 87:085cde657901 593 * @brief Polling for transfer complete or CLUT loading.
mbed_official 87:085cde657901 594 * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
mbed_official 87:085cde657901 595 * the configuration information for the DMA2D.
mbed_official 87:085cde657901 596 * @param Timeout: Timeout duration
mbed_official 87:085cde657901 597 * @retval HAL status
mbed_official 87:085cde657901 598 */
mbed_official 87:085cde657901 599 HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout)
mbed_official 87:085cde657901 600 {
mbed_official 87:085cde657901 601 uint32_t tmp, tmp1;
mbed_official 369:2e96f1b71984 602 uint32_t tickstart = 0;
mbed_official 87:085cde657901 603
mbed_official 87:085cde657901 604 /* Polling for DMA2D transfer */
mbed_official 87:085cde657901 605 if((hdma2d->Instance->CR & DMA2D_CR_START) != 0)
mbed_official 87:085cde657901 606 {
mbed_official 369:2e96f1b71984 607 /* Get tick */
mbed_official 369:2e96f1b71984 608 tickstart = HAL_GetTick();
mbed_official 87:085cde657901 609
mbed_official 87:085cde657901 610 while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_TC) == RESET)
mbed_official 87:085cde657901 611 {
mbed_official 87:085cde657901 612 tmp = __HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CE);
mbed_official 87:085cde657901 613 tmp1 = __HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_TE);
mbed_official 87:085cde657901 614
mbed_official 87:085cde657901 615 if((tmp != RESET) || (tmp1 != RESET))
mbed_official 87:085cde657901 616 {
mbed_official 87:085cde657901 617 /* Clear the transfer and configuration error flags */
mbed_official 87:085cde657901 618 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CE);
mbed_official 87:085cde657901 619 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TE);
mbed_official 87:085cde657901 620
mbed_official 87:085cde657901 621 /* Change DMA2D state */
mbed_official 87:085cde657901 622 hdma2d->State= HAL_DMA2D_STATE_ERROR;
mbed_official 87:085cde657901 623
mbed_official 87:085cde657901 624 /* Process unlocked */
mbed_official 87:085cde657901 625 __HAL_UNLOCK(hdma2d);
mbed_official 87:085cde657901 626
mbed_official 87:085cde657901 627 return HAL_ERROR;
mbed_official 87:085cde657901 628 }
mbed_official 87:085cde657901 629 /* Check for the Timeout */
mbed_official 87:085cde657901 630 if(Timeout != HAL_MAX_DELAY)
mbed_official 87:085cde657901 631 {
mbed_official 369:2e96f1b71984 632 if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
mbed_official 87:085cde657901 633 {
mbed_official 87:085cde657901 634 /* Process unlocked */
mbed_official 87:085cde657901 635 __HAL_UNLOCK(hdma2d);
mbed_official 87:085cde657901 636
mbed_official 87:085cde657901 637 /* Update error code */
mbed_official 87:085cde657901 638 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
mbed_official 87:085cde657901 639
mbed_official 87:085cde657901 640 /* Change the DMA2D state */
mbed_official 87:085cde657901 641 hdma2d->State= HAL_DMA2D_STATE_TIMEOUT;
mbed_official 87:085cde657901 642
mbed_official 87:085cde657901 643 return HAL_TIMEOUT;
mbed_official 87:085cde657901 644 }
mbed_official 87:085cde657901 645 }
mbed_official 87:085cde657901 646 }
mbed_official 87:085cde657901 647 }
mbed_official 87:085cde657901 648 /* Polling for CLUT loading */
mbed_official 87:085cde657901 649 if((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) != 0)
mbed_official 87:085cde657901 650 {
mbed_official 369:2e96f1b71984 651 /* Get tick */
mbed_official 369:2e96f1b71984 652 tickstart = HAL_GetTick();
mbed_official 87:085cde657901 653
mbed_official 87:085cde657901 654 while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CTC) == RESET)
mbed_official 87:085cde657901 655 {
mbed_official 87:085cde657901 656 if((__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CAE) != RESET))
mbed_official 87:085cde657901 657 {
mbed_official 87:085cde657901 658 /* Clear the transfer and configuration error flags */
mbed_official 87:085cde657901 659 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CAE);
mbed_official 87:085cde657901 660
mbed_official 87:085cde657901 661 /* Change DMA2D state */
mbed_official 87:085cde657901 662 hdma2d->State= HAL_DMA2D_STATE_ERROR;
mbed_official 87:085cde657901 663
mbed_official 87:085cde657901 664 return HAL_ERROR;
mbed_official 87:085cde657901 665 }
mbed_official 87:085cde657901 666 /* Check for the Timeout */
mbed_official 87:085cde657901 667 if(Timeout != HAL_MAX_DELAY)
mbed_official 87:085cde657901 668 {
mbed_official 369:2e96f1b71984 669 if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
mbed_official 87:085cde657901 670 {
mbed_official 87:085cde657901 671 /* Update error code */
mbed_official 87:085cde657901 672 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
mbed_official 87:085cde657901 673
mbed_official 87:085cde657901 674 /* Change the DMA2D state */
mbed_official 87:085cde657901 675 hdma2d->State= HAL_DMA2D_STATE_TIMEOUT;
mbed_official 87:085cde657901 676
mbed_official 87:085cde657901 677 return HAL_TIMEOUT;
mbed_official 87:085cde657901 678 }
mbed_official 87:085cde657901 679 }
mbed_official 87:085cde657901 680 }
mbed_official 87:085cde657901 681 }
mbed_official 87:085cde657901 682 /* Clear the transfer complete flag */
mbed_official 87:085cde657901 683 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC);
mbed_official 87:085cde657901 684
mbed_official 87:085cde657901 685 /* Clear the CLUT loading flag */
mbed_official 87:085cde657901 686 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CTC);
mbed_official 87:085cde657901 687
mbed_official 87:085cde657901 688 /* Change DMA2D state */
mbed_official 87:085cde657901 689 hdma2d->State = HAL_DMA2D_STATE_READY;
mbed_official 87:085cde657901 690
mbed_official 87:085cde657901 691 /* Process unlocked */
mbed_official 87:085cde657901 692 __HAL_UNLOCK(hdma2d);
mbed_official 87:085cde657901 693
mbed_official 87:085cde657901 694 return HAL_OK;
mbed_official 87:085cde657901 695 }
mbed_official 87:085cde657901 696 /**
mbed_official 87:085cde657901 697 * @brief Handles DMA2D interrupt request.
mbed_official 87:085cde657901 698 * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
mbed_official 87:085cde657901 699 * the configuration information for the DMA2D.
mbed_official 87:085cde657901 700 * @retval HAL status
mbed_official 87:085cde657901 701 */
mbed_official 87:085cde657901 702 void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d)
mbed_official 87:085cde657901 703 {
mbed_official 87:085cde657901 704 /* Transfer Error Interrupt management ***************************************/
mbed_official 87:085cde657901 705 if(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_TE) != RESET)
mbed_official 87:085cde657901 706 {
mbed_official 106:ced8cbb51063 707 if(__HAL_DMA2D_GET_IT_SOURCE(hdma2d, DMA2D_IT_TE) != RESET)
mbed_official 87:085cde657901 708 {
mbed_official 87:085cde657901 709 /* Disable the transfer Error interrupt */
mbed_official 87:085cde657901 710 __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TE);
mbed_official 87:085cde657901 711
mbed_official 87:085cde657901 712 /* Update error code */
mbed_official 87:085cde657901 713 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE;
mbed_official 87:085cde657901 714
mbed_official 87:085cde657901 715 /* Clear the transfer error flag */
mbed_official 87:085cde657901 716 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TE);
mbed_official 87:085cde657901 717
mbed_official 87:085cde657901 718 /* Change DMA2D state */
mbed_official 87:085cde657901 719 hdma2d->State = HAL_DMA2D_STATE_ERROR;
mbed_official 87:085cde657901 720
mbed_official 87:085cde657901 721 /* Process Unlocked */
mbed_official 87:085cde657901 722 __HAL_UNLOCK(hdma2d);
mbed_official 87:085cde657901 723
mbed_official 87:085cde657901 724 if(hdma2d->XferErrorCallback != NULL)
mbed_official 87:085cde657901 725 {
mbed_official 87:085cde657901 726 /* Transfer error Callback */
mbed_official 87:085cde657901 727 hdma2d->XferErrorCallback(hdma2d);
mbed_official 87:085cde657901 728 }
mbed_official 87:085cde657901 729 }
mbed_official 87:085cde657901 730 }
mbed_official 87:085cde657901 731 /* Configuration Error Interrupt management **********************************/
mbed_official 87:085cde657901 732 if(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CE) != RESET)
mbed_official 87:085cde657901 733 {
mbed_official 106:ced8cbb51063 734 if(__HAL_DMA2D_GET_IT_SOURCE(hdma2d, DMA2D_IT_CE) != RESET)
mbed_official 87:085cde657901 735 {
mbed_official 87:085cde657901 736 /* Disable the Configuration Error interrupt */
mbed_official 87:085cde657901 737 __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CE);
mbed_official 87:085cde657901 738
mbed_official 87:085cde657901 739 /* Clear the Configuration error flag */
mbed_official 87:085cde657901 740 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CE);
mbed_official 87:085cde657901 741
mbed_official 87:085cde657901 742 /* Update error code */
mbed_official 87:085cde657901 743 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE;
mbed_official 87:085cde657901 744
mbed_official 87:085cde657901 745 /* Change DMA2D state */
mbed_official 87:085cde657901 746 hdma2d->State = HAL_DMA2D_STATE_ERROR;
mbed_official 87:085cde657901 747
mbed_official 87:085cde657901 748 /* Process Unlocked */
mbed_official 87:085cde657901 749 __HAL_UNLOCK(hdma2d);
mbed_official 87:085cde657901 750
mbed_official 87:085cde657901 751 if(hdma2d->XferErrorCallback != NULL)
mbed_official 87:085cde657901 752 {
mbed_official 87:085cde657901 753 /* Transfer error Callback */
mbed_official 87:085cde657901 754 hdma2d->XferErrorCallback(hdma2d);
mbed_official 87:085cde657901 755 }
mbed_official 87:085cde657901 756 }
mbed_official 87:085cde657901 757 }
mbed_official 87:085cde657901 758 /* Transfer Complete Interrupt management ************************************/
mbed_official 87:085cde657901 759 if(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_TC) != RESET)
mbed_official 87:085cde657901 760 {
mbed_official 106:ced8cbb51063 761 if(__HAL_DMA2D_GET_IT_SOURCE(hdma2d, DMA2D_IT_TC) != RESET)
mbed_official 87:085cde657901 762 {
mbed_official 87:085cde657901 763 /* Disable the transfer complete interrupt */
mbed_official 87:085cde657901 764 __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TC);
mbed_official 87:085cde657901 765
mbed_official 87:085cde657901 766 /* Clear the transfer complete flag */
mbed_official 87:085cde657901 767 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC);
mbed_official 87:085cde657901 768
mbed_official 87:085cde657901 769 /* Update error code */
mbed_official 87:085cde657901 770 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_NONE;
mbed_official 87:085cde657901 771
mbed_official 87:085cde657901 772 /* Change DMA2D state */
mbed_official 87:085cde657901 773 hdma2d->State = HAL_DMA2D_STATE_READY;
mbed_official 87:085cde657901 774
mbed_official 87:085cde657901 775 /* Process Unlocked */
mbed_official 87:085cde657901 776 __HAL_UNLOCK(hdma2d);
mbed_official 87:085cde657901 777
mbed_official 87:085cde657901 778 if(hdma2d->XferCpltCallback != NULL)
mbed_official 87:085cde657901 779 {
mbed_official 87:085cde657901 780 /* Transfer complete Callback */
mbed_official 87:085cde657901 781 hdma2d->XferCpltCallback(hdma2d);
mbed_official 87:085cde657901 782 }
mbed_official 87:085cde657901 783 }
mbed_official 87:085cde657901 784 }
mbed_official 87:085cde657901 785 }
mbed_official 87:085cde657901 786
mbed_official 87:085cde657901 787 /**
mbed_official 87:085cde657901 788 * @}
mbed_official 87:085cde657901 789 */
mbed_official 87:085cde657901 790
mbed_official 87:085cde657901 791 /** @defgroup DMA2D_Group3 Peripheral Control functions
mbed_official 87:085cde657901 792 * @brief Peripheral Control functions
mbed_official 87:085cde657901 793 *
mbed_official 87:085cde657901 794 @verbatim
mbed_official 87:085cde657901 795 ===============================================================================
mbed_official 87:085cde657901 796 ##### Peripheral Control functions #####
mbed_official 87:085cde657901 797 ===============================================================================
mbed_official 87:085cde657901 798 [..] This section provides functions allowing to:
mbed_official 87:085cde657901 799 (+) Configure the DMA2D foreground or/and background parameters.
mbed_official 87:085cde657901 800 (+) Configure the DMA2D CLUT transfer.
mbed_official 87:085cde657901 801 (+) Enable DMA2D CLUT.
mbed_official 87:085cde657901 802 (+) Disable DMA2D CLUT.
mbed_official 87:085cde657901 803 (+) Configure the line watermark
mbed_official 87:085cde657901 804
mbed_official 87:085cde657901 805 @endverbatim
mbed_official 87:085cde657901 806 * @{
mbed_official 87:085cde657901 807 */
mbed_official 87:085cde657901 808 /**
mbed_official 87:085cde657901 809 * @brief Configure the DMA2D Layer according to the specified
mbed_official 87:085cde657901 810 * parameters in the DMA2D_InitTypeDef and create the associated handle.
mbed_official 226:b062af740e40 811 * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 812 * the configuration information for the DMA2D.
mbed_official 226:b062af740e40 813 * @param LayerIdx: DMA2D Layer index.
mbed_official 87:085cde657901 814 * This parameter can be one of the following values:
mbed_official 87:085cde657901 815 * 0(background) / 1(foreground)
mbed_official 87:085cde657901 816 * @retval HAL status
mbed_official 87:085cde657901 817 */
mbed_official 87:085cde657901 818 HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
mbed_official 87:085cde657901 819 {
mbed_official 87:085cde657901 820 DMA2D_LayerCfgTypeDef *pLayerCfg = &hdma2d->LayerCfg[LayerIdx];
mbed_official 87:085cde657901 821
mbed_official 87:085cde657901 822 uint32_t tmp = 0;
mbed_official 87:085cde657901 823
mbed_official 87:085cde657901 824 /* Process locked */
mbed_official 87:085cde657901 825 __HAL_LOCK(hdma2d);
mbed_official 87:085cde657901 826
mbed_official 87:085cde657901 827 /* Change DMA2D peripheral state */
mbed_official 87:085cde657901 828 hdma2d->State = HAL_DMA2D_STATE_BUSY;
mbed_official 87:085cde657901 829
mbed_official 87:085cde657901 830 /* Check the parameters */
mbed_official 87:085cde657901 831 assert_param(IS_DMA2D_LAYER(LayerIdx));
mbed_official 87:085cde657901 832 assert_param(IS_DMA2D_OFFSET(pLayerCfg->InputOffset));
mbed_official 87:085cde657901 833 if(hdma2d->Init.Mode != DMA2D_R2M)
mbed_official 87:085cde657901 834 {
mbed_official 87:085cde657901 835 assert_param(IS_DMA2D_INPUT_COLOR_MODE(pLayerCfg->InputColorMode));
mbed_official 87:085cde657901 836 if(hdma2d->Init.Mode != DMA2D_M2M)
mbed_official 87:085cde657901 837 {
mbed_official 87:085cde657901 838 assert_param(IS_DMA2D_ALPHA_MODE(pLayerCfg->AlphaMode));
mbed_official 87:085cde657901 839 }
mbed_official 87:085cde657901 840 }
mbed_official 87:085cde657901 841
mbed_official 87:085cde657901 842 /* Configure the background DMA2D layer */
mbed_official 87:085cde657901 843 if(LayerIdx == 0)
mbed_official 87:085cde657901 844 {
mbed_official 87:085cde657901 845 /* DMA2D BGPFCR register configuration -----------------------------------*/
mbed_official 87:085cde657901 846 /* Get the BGPFCCR register value */
mbed_official 87:085cde657901 847 tmp = hdma2d->Instance->BGPFCCR;
mbed_official 87:085cde657901 848
mbed_official 87:085cde657901 849 /* Clear Input color mode, alpha value and alpha mode bits */
mbed_official 87:085cde657901 850 tmp &= (uint32_t)~(DMA2D_BGPFCCR_CM | DMA2D_BGPFCCR_AM | DMA2D_BGPFCCR_ALPHA);
mbed_official 87:085cde657901 851
mbed_official 369:2e96f1b71984 852 if ((pLayerCfg->InputColorMode == CM_A4) || (pLayerCfg->InputColorMode == CM_A8))
mbed_official 369:2e96f1b71984 853 {
mbed_official 369:2e96f1b71984 854 /* Prepare the value to be wrote to the BGPFCCR register */
mbed_official 369:2e96f1b71984 855 tmp |= (pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << 16) | ((pLayerCfg->InputAlpha) & 0xFF000000));
mbed_official 369:2e96f1b71984 856 }
mbed_official 369:2e96f1b71984 857 else
mbed_official 369:2e96f1b71984 858 {
mbed_official 369:2e96f1b71984 859 /* Prepare the value to be wrote to the BGPFCCR register */
mbed_official 369:2e96f1b71984 860 tmp |= (pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << 16) | (pLayerCfg->InputAlpha << 24));
mbed_official 369:2e96f1b71984 861 }
mbed_official 87:085cde657901 862
mbed_official 87:085cde657901 863 /* Write to DMA2D BGPFCCR register */
mbed_official 87:085cde657901 864 hdma2d->Instance->BGPFCCR = tmp;
mbed_official 87:085cde657901 865
mbed_official 87:085cde657901 866 /* DMA2D BGOR register configuration -------------------------------------*/
mbed_official 87:085cde657901 867 /* Get the BGOR register value */
mbed_official 87:085cde657901 868 tmp = hdma2d->Instance->BGOR;
mbed_official 87:085cde657901 869
mbed_official 87:085cde657901 870 /* Clear colors bits */
mbed_official 87:085cde657901 871 tmp &= (uint32_t)~DMA2D_BGOR_LO;
mbed_official 87:085cde657901 872
mbed_official 87:085cde657901 873 /* Prepare the value to be wrote to the BGOR register */
mbed_official 87:085cde657901 874 tmp |= pLayerCfg->InputOffset;
mbed_official 87:085cde657901 875
mbed_official 87:085cde657901 876 /* Write to DMA2D BGOR register */
mbed_official 87:085cde657901 877 hdma2d->Instance->BGOR = tmp;
mbed_official 369:2e96f1b71984 878
mbed_official 369:2e96f1b71984 879 if ((pLayerCfg->InputColorMode == CM_A4) || (pLayerCfg->InputColorMode == CM_A8))
mbed_official 369:2e96f1b71984 880 {
mbed_official 369:2e96f1b71984 881 /* Prepare the value to be wrote to the BGCOLR register */
mbed_official 369:2e96f1b71984 882 tmp |= ((pLayerCfg->InputAlpha) & 0x00FFFFFF);
mbed_official 369:2e96f1b71984 883
mbed_official 369:2e96f1b71984 884 /* Write to DMA2D BGCOLR register */
mbed_official 369:2e96f1b71984 885 hdma2d->Instance->BGCOLR = tmp;
mbed_official 369:2e96f1b71984 886 }
mbed_official 87:085cde657901 887 }
mbed_official 87:085cde657901 888 /* Configure the foreground DMA2D layer */
mbed_official 87:085cde657901 889 else
mbed_official 87:085cde657901 890 {
mbed_official 87:085cde657901 891 /* DMA2D FGPFCR register configuration -----------------------------------*/
mbed_official 87:085cde657901 892 /* Get the FGPFCCR register value */
mbed_official 87:085cde657901 893 tmp = hdma2d->Instance->FGPFCCR;
mbed_official 87:085cde657901 894
mbed_official 87:085cde657901 895 /* Clear Input color mode, alpha value and alpha mode bits */
mbed_official 87:085cde657901 896 tmp &= (uint32_t)~(DMA2D_FGPFCCR_CM | DMA2D_FGPFCCR_AM | DMA2D_FGPFCCR_ALPHA);
mbed_official 87:085cde657901 897
mbed_official 369:2e96f1b71984 898 if ((pLayerCfg->InputColorMode == CM_A4) || (pLayerCfg->InputColorMode == CM_A8))
mbed_official 369:2e96f1b71984 899 {
mbed_official 369:2e96f1b71984 900 /* Prepare the value to be wrote to the FGPFCCR register */
mbed_official 369:2e96f1b71984 901 tmp |= (pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << 16) | ((pLayerCfg->InputAlpha) & 0xFF000000));
mbed_official 369:2e96f1b71984 902 }
mbed_official 369:2e96f1b71984 903 else
mbed_official 369:2e96f1b71984 904 {
mbed_official 369:2e96f1b71984 905 /* Prepare the value to be wrote to the FGPFCCR register */
mbed_official 369:2e96f1b71984 906 tmp |= (pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << 16) | (pLayerCfg->InputAlpha << 24));
mbed_official 369:2e96f1b71984 907 }
mbed_official 87:085cde657901 908
mbed_official 87:085cde657901 909 /* Write to DMA2D FGPFCCR register */
mbed_official 87:085cde657901 910 hdma2d->Instance->FGPFCCR = tmp;
mbed_official 87:085cde657901 911
mbed_official 87:085cde657901 912 /* DMA2D FGOR register configuration -------------------------------------*/
mbed_official 87:085cde657901 913 /* Get the FGOR register value */
mbed_official 87:085cde657901 914 tmp = hdma2d->Instance->FGOR;
mbed_official 87:085cde657901 915
mbed_official 87:085cde657901 916 /* Clear colors bits */
mbed_official 87:085cde657901 917 tmp &= (uint32_t)~DMA2D_FGOR_LO;
mbed_official 87:085cde657901 918
mbed_official 87:085cde657901 919 /* Prepare the value to be wrote to the FGOR register */
mbed_official 87:085cde657901 920 tmp |= pLayerCfg->InputOffset;
mbed_official 87:085cde657901 921
mbed_official 87:085cde657901 922 /* Write to DMA2D FGOR register */
mbed_official 87:085cde657901 923 hdma2d->Instance->FGOR = tmp;
mbed_official 369:2e96f1b71984 924
mbed_official 369:2e96f1b71984 925 if ((pLayerCfg->InputColorMode == CM_A4) || (pLayerCfg->InputColorMode == CM_A8))
mbed_official 369:2e96f1b71984 926 {
mbed_official 369:2e96f1b71984 927 /* Prepare the value to be wrote to the FGCOLR register */
mbed_official 369:2e96f1b71984 928 tmp |= ((pLayerCfg->InputAlpha) & 0x00FFFFFF);
mbed_official 369:2e96f1b71984 929
mbed_official 369:2e96f1b71984 930 /* Write to DMA2D FGCOLR register */
mbed_official 369:2e96f1b71984 931 hdma2d->Instance->FGCOLR = tmp;
mbed_official 369:2e96f1b71984 932 }
mbed_official 87:085cde657901 933 }
mbed_official 87:085cde657901 934 /* Initialize the DMA2D state*/
mbed_official 87:085cde657901 935 hdma2d->State = HAL_DMA2D_STATE_READY;
mbed_official 87:085cde657901 936
mbed_official 87:085cde657901 937 /* Process unlocked */
mbed_official 87:085cde657901 938 __HAL_UNLOCK(hdma2d);
mbed_official 87:085cde657901 939
mbed_official 87:085cde657901 940 return HAL_OK;
mbed_official 87:085cde657901 941 }
mbed_official 87:085cde657901 942
mbed_official 87:085cde657901 943 /**
mbed_official 87:085cde657901 944 * @brief Configure the DMA2D CLUT Transfer.
mbed_official 87:085cde657901 945 * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
mbed_official 87:085cde657901 946 * the configuration information for the DMA2D.
mbed_official 87:085cde657901 947 * @param CLUTCfg: pointer to a DMA2D_CLUTCfgTypeDef structure that contains
mbed_official 87:085cde657901 948 * the configuration information for the color look up table.
mbed_official 226:b062af740e40 949 * @param LayerIdx: DMA2D Layer index.
mbed_official 87:085cde657901 950 * This parameter can be one of the following values:
mbed_official 87:085cde657901 951 * 0(background) / 1(foreground)
mbed_official 87:085cde657901 952 * @retval HAL status
mbed_official 87:085cde657901 953 */
mbed_official 87:085cde657901 954 HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
mbed_official 87:085cde657901 955 {
mbed_official 87:085cde657901 956 uint32_t tmp = 0, tmp1 = 0;
mbed_official 87:085cde657901 957
mbed_official 87:085cde657901 958 /* Check the parameters */
mbed_official 87:085cde657901 959 assert_param(IS_DMA2D_LAYER(LayerIdx));
mbed_official 87:085cde657901 960 assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode));
mbed_official 87:085cde657901 961 assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size));
mbed_official 87:085cde657901 962
mbed_official 87:085cde657901 963 /* Configure the CLUT of the background DMA2D layer */
mbed_official 87:085cde657901 964 if(LayerIdx == 0)
mbed_official 87:085cde657901 965 {
mbed_official 87:085cde657901 966 /* Get the BGCMAR register value */
mbed_official 87:085cde657901 967 tmp = hdma2d->Instance->BGCMAR;
mbed_official 87:085cde657901 968
mbed_official 87:085cde657901 969 /* Clear CLUT address bits */
mbed_official 87:085cde657901 970 tmp &= (uint32_t)~DMA2D_BGCMAR_MA;
mbed_official 87:085cde657901 971
mbed_official 87:085cde657901 972 /* Prepare the value to be wrote to the BGCMAR register */
mbed_official 87:085cde657901 973 tmp |= (uint32_t)CLUTCfg.pCLUT;
mbed_official 87:085cde657901 974
mbed_official 87:085cde657901 975 /* Write to DMA2D BGCMAR register */
mbed_official 87:085cde657901 976 hdma2d->Instance->BGCMAR = tmp;
mbed_official 87:085cde657901 977
mbed_official 87:085cde657901 978 /* Get the BGPFCCR register value */
mbed_official 87:085cde657901 979 tmp = hdma2d->Instance->BGPFCCR;
mbed_official 87:085cde657901 980
mbed_official 87:085cde657901 981 /* Clear CLUT size and CLUT address bits */
mbed_official 87:085cde657901 982 tmp &= (uint32_t)~(DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM);
mbed_official 87:085cde657901 983
mbed_official 87:085cde657901 984 /* Get the CLUT size */
mbed_official 87:085cde657901 985 tmp1 = CLUTCfg.Size << 16;
mbed_official 87:085cde657901 986
mbed_official 87:085cde657901 987 /* Prepare the value to be wrote to the BGPFCCR register */
mbed_official 87:085cde657901 988 tmp |= (CLUTCfg.CLUTColorMode | tmp1);
mbed_official 87:085cde657901 989
mbed_official 87:085cde657901 990 /* Write to DMA2D BGPFCCR register */
mbed_official 87:085cde657901 991 hdma2d->Instance->BGPFCCR = tmp;
mbed_official 87:085cde657901 992 }
mbed_official 87:085cde657901 993 /* Configure the CLUT of the foreground DMA2D layer */
mbed_official 87:085cde657901 994 else
mbed_official 87:085cde657901 995 {
mbed_official 87:085cde657901 996 /* Get the FGCMAR register value */
mbed_official 87:085cde657901 997 tmp = hdma2d->Instance->FGCMAR;
mbed_official 87:085cde657901 998
mbed_official 87:085cde657901 999 /* Clear CLUT address bits */
mbed_official 87:085cde657901 1000 tmp &= (uint32_t)~DMA2D_FGCMAR_MA;
mbed_official 87:085cde657901 1001
mbed_official 87:085cde657901 1002 /* Prepare the value to be wrote to the FGCMAR register */
mbed_official 87:085cde657901 1003 tmp |= (uint32_t)CLUTCfg.pCLUT;
mbed_official 87:085cde657901 1004
mbed_official 87:085cde657901 1005 /* Write to DMA2D FGCMAR register */
mbed_official 87:085cde657901 1006 hdma2d->Instance->FGCMAR = tmp;
mbed_official 87:085cde657901 1007
mbed_official 87:085cde657901 1008 /* Get the FGPFCCR register value */
mbed_official 87:085cde657901 1009 tmp = hdma2d->Instance->FGPFCCR;
mbed_official 87:085cde657901 1010
mbed_official 87:085cde657901 1011 /* Clear CLUT size and CLUT address bits */
mbed_official 87:085cde657901 1012 tmp &= (uint32_t)~(DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM);
mbed_official 87:085cde657901 1013
mbed_official 87:085cde657901 1014 /* Get the CLUT size */
mbed_official 87:085cde657901 1015 tmp1 = CLUTCfg.Size << 8;
mbed_official 87:085cde657901 1016
mbed_official 87:085cde657901 1017 /* Prepare the value to be wrote to the FGPFCCR register */
mbed_official 87:085cde657901 1018 tmp |= (CLUTCfg.CLUTColorMode | tmp1);
mbed_official 87:085cde657901 1019
mbed_official 87:085cde657901 1020 /* Write to DMA2D FGPFCCR register */
mbed_official 87:085cde657901 1021 hdma2d->Instance->FGPFCCR = tmp;
mbed_official 87:085cde657901 1022 }
mbed_official 87:085cde657901 1023
mbed_official 87:085cde657901 1024 return HAL_OK;
mbed_official 87:085cde657901 1025 }
mbed_official 87:085cde657901 1026
mbed_official 87:085cde657901 1027 /**
mbed_official 87:085cde657901 1028 * @brief Enable the DMA2D CLUT Transfer.
mbed_official 87:085cde657901 1029 * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
mbed_official 87:085cde657901 1030 * the configuration information for the DMA2D.
mbed_official 226:b062af740e40 1031 * @param LayerIdx: DMA2D Layer index.
mbed_official 87:085cde657901 1032 * This parameter can be one of the following values:
mbed_official 87:085cde657901 1033 * 0(background) / 1(foreground)
mbed_official 87:085cde657901 1034 * @retval HAL status
mbed_official 87:085cde657901 1035 */
mbed_official 87:085cde657901 1036 HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
mbed_official 87:085cde657901 1037 {
mbed_official 87:085cde657901 1038 /* Check the parameters */
mbed_official 87:085cde657901 1039 assert_param(IS_DMA2D_LAYER(LayerIdx));
mbed_official 87:085cde657901 1040
mbed_official 87:085cde657901 1041 if(LayerIdx == 0)
mbed_official 87:085cde657901 1042 {
mbed_official 87:085cde657901 1043 /* Enable the CLUT loading for the background */
mbed_official 87:085cde657901 1044 hdma2d->Instance->BGPFCCR |= DMA2D_BGPFCCR_START;
mbed_official 87:085cde657901 1045 }
mbed_official 87:085cde657901 1046 else
mbed_official 87:085cde657901 1047 {
mbed_official 87:085cde657901 1048 /* Enable the CLUT loading for the foreground */
mbed_official 87:085cde657901 1049 hdma2d->Instance->FGPFCCR |= DMA2D_FGPFCCR_START;
mbed_official 87:085cde657901 1050 }
mbed_official 87:085cde657901 1051
mbed_official 87:085cde657901 1052 return HAL_OK;
mbed_official 87:085cde657901 1053 }
mbed_official 87:085cde657901 1054
mbed_official 87:085cde657901 1055 /**
mbed_official 87:085cde657901 1056 * @brief Disable the DMA2D CLUT Transfer.
mbed_official 87:085cde657901 1057 * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
mbed_official 87:085cde657901 1058 * the configuration information for the DMA2D.
mbed_official 226:b062af740e40 1059 * @param LayerIdx: DMA2D Layer index.
mbed_official 87:085cde657901 1060 * This parameter can be one of the following values:
mbed_official 87:085cde657901 1061 * 0(background) / 1(foreground)
mbed_official 87:085cde657901 1062 * @retval HAL status
mbed_official 87:085cde657901 1063 */
mbed_official 87:085cde657901 1064 HAL_StatusTypeDef HAL_DMA2D_DisableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
mbed_official 87:085cde657901 1065 {
mbed_official 87:085cde657901 1066 /* Check the parameters */
mbed_official 87:085cde657901 1067 assert_param(IS_DMA2D_LAYER(LayerIdx));
mbed_official 87:085cde657901 1068
mbed_official 87:085cde657901 1069 if(LayerIdx == 0)
mbed_official 87:085cde657901 1070 {
mbed_official 87:085cde657901 1071 /* Disable the CLUT loading for the background */
mbed_official 87:085cde657901 1072 hdma2d->Instance->BGPFCCR &= ~DMA2D_BGPFCCR_START;
mbed_official 87:085cde657901 1073 }
mbed_official 87:085cde657901 1074 else
mbed_official 87:085cde657901 1075 {
mbed_official 87:085cde657901 1076 /* Disable the CLUT loading for the foreground */
mbed_official 87:085cde657901 1077 hdma2d->Instance->FGPFCCR &= ~DMA2D_FGPFCCR_START;
mbed_official 87:085cde657901 1078 }
mbed_official 87:085cde657901 1079
mbed_official 87:085cde657901 1080 return HAL_OK;
mbed_official 87:085cde657901 1081 }
mbed_official 87:085cde657901 1082
mbed_official 87:085cde657901 1083 /**
mbed_official 87:085cde657901 1084 * @brief Define the configuration of the line watermark .
mbed_official 87:085cde657901 1085 * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
mbed_official 87:085cde657901 1086 * the configuration information for the DMA2D.
mbed_official 87:085cde657901 1087 * @param Line: Line Watermark configuration.
mbed_official 226:b062af740e40 1088 * @retval HAL status
mbed_official 87:085cde657901 1089 */
mbed_official 87:085cde657901 1090
mbed_official 87:085cde657901 1091 HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line)
mbed_official 87:085cde657901 1092 {
mbed_official 87:085cde657901 1093 /* Process locked */
mbed_official 87:085cde657901 1094 __HAL_LOCK(hdma2d);
mbed_official 87:085cde657901 1095
mbed_official 87:085cde657901 1096 /* Change DMA2D peripheral state */
mbed_official 87:085cde657901 1097 hdma2d->State = HAL_DMA2D_STATE_BUSY;
mbed_official 87:085cde657901 1098
mbed_official 87:085cde657901 1099 /* Check the parameters */
mbed_official 87:085cde657901 1100 assert_param(IS_DMA2D_LineWatermark(Line));
mbed_official 87:085cde657901 1101
mbed_official 87:085cde657901 1102 /* Sets the Line watermark configuration */
mbed_official 87:085cde657901 1103 DMA2D->LWR = (uint32_t)Line;
mbed_official 87:085cde657901 1104
mbed_official 87:085cde657901 1105 /* Initialize the DMA2D state*/
mbed_official 87:085cde657901 1106 hdma2d->State = HAL_DMA2D_STATE_READY;
mbed_official 87:085cde657901 1107
mbed_official 87:085cde657901 1108 /* Process unlocked */
mbed_official 87:085cde657901 1109 __HAL_UNLOCK(hdma2d);
mbed_official 87:085cde657901 1110
mbed_official 87:085cde657901 1111 return HAL_OK;
mbed_official 87:085cde657901 1112 }
mbed_official 87:085cde657901 1113
mbed_official 87:085cde657901 1114 /**
mbed_official 87:085cde657901 1115 * @}
mbed_official 87:085cde657901 1116 */
mbed_official 87:085cde657901 1117
mbed_official 87:085cde657901 1118 /** @defgroup DMA2D_Group4 Peripheral State functions
mbed_official 87:085cde657901 1119 * @brief Peripheral State functions
mbed_official 87:085cde657901 1120 *
mbed_official 87:085cde657901 1121 @verbatim
mbed_official 87:085cde657901 1122 ===============================================================================
mbed_official 87:085cde657901 1123 ##### Peripheral State and Errors functions #####
mbed_official 87:085cde657901 1124 ===============================================================================
mbed_official 87:085cde657901 1125 [..]
mbed_official 226:b062af740e40 1126 This subsection provides functions allowing to :
mbed_official 87:085cde657901 1127 (+) Check the DMA2D state
mbed_official 87:085cde657901 1128 (+) Get error code
mbed_official 87:085cde657901 1129
mbed_official 87:085cde657901 1130 @endverbatim
mbed_official 87:085cde657901 1131 * @{
mbed_official 87:085cde657901 1132 */
mbed_official 87:085cde657901 1133
mbed_official 87:085cde657901 1134 /**
mbed_official 87:085cde657901 1135 * @brief Return the DMA2D state
mbed_official 87:085cde657901 1136 * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
mbed_official 87:085cde657901 1137 * the configuration information for the DMA2D.
mbed_official 87:085cde657901 1138 * @retval HAL state
mbed_official 87:085cde657901 1139 */
mbed_official 87:085cde657901 1140 HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d)
mbed_official 87:085cde657901 1141 {
mbed_official 87:085cde657901 1142 return hdma2d->State;
mbed_official 87:085cde657901 1143 }
mbed_official 87:085cde657901 1144
mbed_official 87:085cde657901 1145 /**
mbed_official 87:085cde657901 1146 * @brief Return the DMA2D error code
mbed_official 87:085cde657901 1147 * @param hdma2d : pointer to a DMA2D_HandleTypeDef structure that contains
mbed_official 87:085cde657901 1148 * the configuration information for DMA2D.
mbed_official 87:085cde657901 1149 * @retval DMA2D Error Code
mbed_official 87:085cde657901 1150 */
mbed_official 87:085cde657901 1151 uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d)
mbed_official 87:085cde657901 1152 {
mbed_official 87:085cde657901 1153 return hdma2d->ErrorCode;
mbed_official 87:085cde657901 1154 }
mbed_official 87:085cde657901 1155
mbed_official 87:085cde657901 1156 /**
mbed_official 87:085cde657901 1157 * @}
mbed_official 87:085cde657901 1158 */
mbed_official 87:085cde657901 1159
mbed_official 87:085cde657901 1160
mbed_official 87:085cde657901 1161 /**
mbed_official 87:085cde657901 1162 * @brief Set the DMA2D Transfer parameter.
mbed_official 87:085cde657901 1163 * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
mbed_official 87:085cde657901 1164 * the configuration information for the specified DMA2D.
mbed_official 87:085cde657901 1165 * @param pdata: The source memory Buffer address
mbed_official 87:085cde657901 1166 * @param DstAddress: The destination memory Buffer address
mbed_official 87:085cde657901 1167 * @param Width: The width of data to be transferred from source to destination.
mbed_official 87:085cde657901 1168 * @param Heigh: The heigh of data to be transferred from source to destination.
mbed_official 87:085cde657901 1169 * @retval HAL status
mbed_official 87:085cde657901 1170 */
mbed_official 87:085cde657901 1171 static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Heigh)
mbed_official 87:085cde657901 1172 {
mbed_official 87:085cde657901 1173 uint32_t tmp = 0;
mbed_official 87:085cde657901 1174 uint32_t tmp1 = 0;
mbed_official 87:085cde657901 1175 uint32_t tmp2 = 0;
mbed_official 87:085cde657901 1176 uint32_t tmp3 = 0;
mbed_official 87:085cde657901 1177 uint32_t tmp4 = 0;
mbed_official 87:085cde657901 1178
mbed_official 87:085cde657901 1179 tmp = Width << 16;
mbed_official 87:085cde657901 1180
mbed_official 87:085cde657901 1181 /* Configure DMA2D data size */
mbed_official 87:085cde657901 1182 hdma2d->Instance->NLR = (Heigh | tmp);
mbed_official 87:085cde657901 1183
mbed_official 87:085cde657901 1184 /* Configure DMA2D destination address */
mbed_official 87:085cde657901 1185 hdma2d->Instance->OMAR = DstAddress;
mbed_official 87:085cde657901 1186
mbed_official 87:085cde657901 1187 /* Register to memory DMA2D mode selected */
mbed_official 87:085cde657901 1188 if (hdma2d->Init.Mode == DMA2D_R2M)
mbed_official 87:085cde657901 1189 {
mbed_official 87:085cde657901 1190 tmp1 = pdata & DMA2D_OCOLR_ALPHA_1;
mbed_official 87:085cde657901 1191 tmp2 = pdata & DMA2D_OCOLR_RED_1;
mbed_official 87:085cde657901 1192 tmp3 = pdata & DMA2D_OCOLR_GREEN_1;
mbed_official 87:085cde657901 1193 tmp4 = pdata & DMA2D_OCOLR_BLUE_1;
mbed_official 87:085cde657901 1194
mbed_official 87:085cde657901 1195 /* Prepare the value to be wrote to the OCOLR register according to the color mode */
mbed_official 87:085cde657901 1196 if (hdma2d->Init.ColorMode == DMA2D_ARGB8888)
mbed_official 87:085cde657901 1197 {
mbed_official 87:085cde657901 1198 tmp = (tmp3 | tmp2 | tmp1| tmp4);
mbed_official 87:085cde657901 1199 }
mbed_official 87:085cde657901 1200 else if (hdma2d->Init.ColorMode == DMA2D_RGB888)
mbed_official 87:085cde657901 1201 {
mbed_official 87:085cde657901 1202 tmp = (tmp3 | tmp2 | tmp4);
mbed_official 87:085cde657901 1203 }
mbed_official 87:085cde657901 1204 else if (hdma2d->Init.ColorMode == DMA2D_RGB565)
mbed_official 87:085cde657901 1205 {
mbed_official 87:085cde657901 1206 tmp2 = (tmp2 >> 19);
mbed_official 87:085cde657901 1207 tmp3 = (tmp3 >> 10);
mbed_official 87:085cde657901 1208 tmp4 = (tmp4 >> 3 );
mbed_official 87:085cde657901 1209 tmp = ((tmp3 << 5) | (tmp2 << 11) | tmp4);
mbed_official 87:085cde657901 1210 }
mbed_official 87:085cde657901 1211 else if (hdma2d->Init.ColorMode == DMA2D_ARGB1555)
mbed_official 87:085cde657901 1212 {
mbed_official 87:085cde657901 1213 tmp1 = (tmp1 >> 31);
mbed_official 87:085cde657901 1214 tmp2 = (tmp2 >> 19);
mbed_official 87:085cde657901 1215 tmp3 = (tmp3 >> 11);
mbed_official 87:085cde657901 1216 tmp4 = (tmp4 >> 3 );
mbed_official 87:085cde657901 1217 tmp = ((tmp3 << 5) | (tmp2 << 10) | (tmp1 << 15) | tmp4);
mbed_official 87:085cde657901 1218 }
mbed_official 87:085cde657901 1219 else /* DMA2D_CMode = DMA2D_ARGB4444 */
mbed_official 87:085cde657901 1220 {
mbed_official 87:085cde657901 1221 tmp1 = (tmp1 >> 28);
mbed_official 87:085cde657901 1222 tmp2 = (tmp2 >> 20);
mbed_official 87:085cde657901 1223 tmp3 = (tmp3 >> 12);
mbed_official 87:085cde657901 1224 tmp4 = (tmp4 >> 4 );
mbed_official 87:085cde657901 1225 tmp = ((tmp3 << 4) | (tmp2 << 8) | (tmp1 << 12) | tmp4);
mbed_official 87:085cde657901 1226 }
mbed_official 87:085cde657901 1227 /* Write to DMA2D OCOLR register */
mbed_official 87:085cde657901 1228 hdma2d->Instance->OCOLR = tmp;
mbed_official 369:2e96f1b71984 1229 }
mbed_official 87:085cde657901 1230 else /* M2M, M2M_PFC or M2M_Blending DMA2D Mode */
mbed_official 87:085cde657901 1231 {
mbed_official 87:085cde657901 1232 /* Configure DMA2D source address */
mbed_official 87:085cde657901 1233 hdma2d->Instance->FGMAR = pdata;
mbed_official 87:085cde657901 1234 }
mbed_official 87:085cde657901 1235 }
mbed_official 87:085cde657901 1236
mbed_official 87:085cde657901 1237 /**
mbed_official 87:085cde657901 1238 * @}
mbed_official 87:085cde657901 1239 */
mbed_official 106:ced8cbb51063 1240 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
mbed_official 87:085cde657901 1241 #endif /* HAL_DMA2D_MODULE_ENABLED */
mbed_official 87:085cde657901 1242 /**
mbed_official 87:085cde657901 1243 * @}
mbed_official 87:085cde657901 1244 */
mbed_official 87:085cde657901 1245
mbed_official 87:085cde657901 1246 /**
mbed_official 87:085cde657901 1247 * @}
mbed_official 87:085cde657901 1248 */
mbed_official 87:085cde657901 1249
mbed_official 87:085cde657901 1250 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/