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Last commit 20 Feb 2019 by mbed official

targets/cmsis/TARGET_NXP/TARGET_LPC43XX/system_LPC43xx.h@20:4263a77256ae, 2013-09-10 (annotated)

Committer:
bogdanm
Date:
Tue Sep 10 15:14:19 2013 +0300
Revision:
20:4263a77256ae
Child:
256:76fd9a263045
Sync with git revision 171dda705c947bf910926a0b73d6a4797802554d

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 20:4263a77256ae 1 /*
bogdanm 20:4263a77256ae 2 * @brief LPC43xx/LPC18xx mcu header
bogdanm 20:4263a77256ae 3 *
bogdanm 20:4263a77256ae 4 * Copyright(C) NXP Semiconductors, 2012
bogdanm 20:4263a77256ae 5 * All rights reserved.
bogdanm 20:4263a77256ae 6 *
bogdanm 20:4263a77256ae 7 * Software that is described herein is for illustrative purposes only
bogdanm 20:4263a77256ae 8 * which provides customers with programming information regarding the
bogdanm 20:4263a77256ae 9 * LPC products. This software is supplied "AS IS" without any warranties of
bogdanm 20:4263a77256ae 10 * any kind, and NXP Semiconductors and its licensor disclaim any and
bogdanm 20:4263a77256ae 11 * all warranties, express or implied, including all implied warranties of
bogdanm 20:4263a77256ae 12 * merchantability, fitness for a particular purpose and non-infringement of
bogdanm 20:4263a77256ae 13 * intellectual property rights. NXP Semiconductors assumes no responsibility
bogdanm 20:4263a77256ae 14 * or liability for the use of the software, conveys no license or rights under any
bogdanm 20:4263a77256ae 15 * patent, copyright, mask work right, or any other intellectual property rights in
bogdanm 20:4263a77256ae 16 * or to any products. NXP Semiconductors reserves the right to make changes
bogdanm 20:4263a77256ae 17 * in the software without notification. NXP Semiconductors also makes no
bogdanm 20:4263a77256ae 18 * representation or warranty that such application will be suitable for the
bogdanm 20:4263a77256ae 19 * specified use without further testing or modification.
bogdanm 20:4263a77256ae 20 *
bogdanm 20:4263a77256ae 21 * Permission to use, copy, modify, and distribute this software and its
bogdanm 20:4263a77256ae 22 * documentation is hereby granted, under NXP Semiconductors' and its
bogdanm 20:4263a77256ae 23 * licensor's relevant copyrights in the software, without fee, provided that it
bogdanm 20:4263a77256ae 24 * is used in conjunction with NXP Semiconductors microcontrollers. This
bogdanm 20:4263a77256ae 25 * copyright, permission, and disclaimer notice must appear in all copies of
bogdanm 20:4263a77256ae 26 * this code.
bogdanm 20:4263a77256ae 27 */
bogdanm 20:4263a77256ae 28
bogdanm 20:4263a77256ae 29 #ifndef __SYSTEM_LPC43XX_H
bogdanm 20:4263a77256ae 30 #define __SYSTEM_LPC43XX_H
bogdanm 20:4263a77256ae 31
bogdanm 20:4263a77256ae 32 #ifdef __cplusplus
bogdanm 20:4263a77256ae 33 extern "C" {
bogdanm 20:4263a77256ae 34 #endif
bogdanm 20:4263a77256ae 35
bogdanm 20:4263a77256ae 36 /* System initialization options */
bogdanm 20:4263a77256ae 37 #define PIN_SETUP 1 /* Configure pins during initialization */
bogdanm 20:4263a77256ae 38 #define CLOCK_SETUP 1 /* Configure clocks during initialization */
bogdanm 20:4263a77256ae 39 #define MEMORY_SETUP 0 /* Configure external memory during init */
bogdanm 20:4263a77256ae 40 #define SPIFI_INIT 1 /* Initialize SPIFI */
bogdanm 20:4263a77256ae 41
bogdanm 20:4263a77256ae 42 /* Crystal frequency into device */
bogdanm 20:4263a77256ae 43 #define CRYSTAL_MAIN_FREQ_IN 12000000
bogdanm 20:4263a77256ae 44
bogdanm 20:4263a77256ae 45 /* Crystal frequency into device for RTC/32K input */
bogdanm 20:4263a77256ae 46 #define CRYSTAL_32K_FREQ_IN 32768
bogdanm 20:4263a77256ae 47
bogdanm 20:4263a77256ae 48 /* Default CPU clock frequency */
bogdanm 20:4263a77256ae 49 #if defined(CHIP_LPC43XX)
bogdanm 20:4263a77256ae 50 #define MAX_CLOCK_FREQ (204000000)
bogdanm 20:4263a77256ae 51 #else
bogdanm 20:4263a77256ae 52 #define MAX_CLOCK_FREQ (180000000)
bogdanm 20:4263a77256ae 53 #endif
bogdanm 20:4263a77256ae 54
bogdanm 20:4263a77256ae 55 #if defined(__FPU_PRESENT) && __FPU_PRESENT == 1
bogdanm 20:4263a77256ae 56 /* FPU declarations */
bogdanm 20:4263a77256ae 57 #define LPC_CPACR 0xE000ED88
bogdanm 20:4263a77256ae 58
bogdanm 20:4263a77256ae 59 #define SCB_MVFR0 0xE000EF40
bogdanm 20:4263a77256ae 60 #define SCB_MVFR0_RESET 0x10110021
bogdanm 20:4263a77256ae 61
bogdanm 20:4263a77256ae 62 #define SCB_MVFR1 0xE000EF44
bogdanm 20:4263a77256ae 63 #define SCB_MVFR1_RESET 0x11000011
bogdanm 20:4263a77256ae 64
bogdanm 20:4263a77256ae 65 #if defined(__ARMCC_VERSION)
bogdanm 20:4263a77256ae 66 void fpuInit(void) __attribute__ ((section("BOOTSTRAP_CODE")));
bogdanm 20:4263a77256ae 67 #else
bogdanm 20:4263a77256ae 68 extern void fpuInit(void);
bogdanm 20:4263a77256ae 69 #endif
bogdanm 20:4263a77256ae 70 #endif
bogdanm 20:4263a77256ae 71
bogdanm 20:4263a77256ae 72 extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
bogdanm 20:4263a77256ae 73
bogdanm 20:4263a77256ae 74 /**
bogdanm 20:4263a77256ae 75 * Initialize the system
bogdanm 20:4263a77256ae 76 *
bogdanm 20:4263a77256ae 77 * @param none
bogdanm 20:4263a77256ae 78 * @return none
bogdanm 20:4263a77256ae 79 *
bogdanm 20:4263a77256ae 80 * @brief Setup the microcontroller system.
bogdanm 20:4263a77256ae 81 * Initialize the System and update the SystemCoreClock variable.
bogdanm 20:4263a77256ae 82 */
bogdanm 20:4263a77256ae 83 extern void SystemInit (void);
bogdanm 20:4263a77256ae 84
bogdanm 20:4263a77256ae 85 #ifdef __cplusplus
bogdanm 20:4263a77256ae 86 }
bogdanm 20:4263a77256ae 87 #endif
bogdanm 20:4263a77256ae 88
bogdanm 20:4263a77256ae 89 #endif /* __SYSTEM_LPC43XX_H */