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Last commit 20 Feb 2019 by mbed official

targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/uart/fsl_uart_features.h@324:406fd2029f23, 2014-09-18 (annotated)

Committer:
mbed_official
Date:
Thu Sep 18 14:00:17 2014 +0100
Revision:
324:406fd2029f23
Parent:
149:1fb5f62b92bd 
Synchronized with git revision a73f28e6fbca9559fbed2726410eeb4c0534a4a5



Full URL: https://github.com/mbedmicro/mbed/commit/a73f28e6fbca9559fbed2726410eeb4c0534a4a5/



Extended #476, which does not break ethernet for K64F

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 146:f64d43ff0c18 1 /*
mbed_official 324:406fd2029f23 2 ** ###################################################################
mbed_official 324:406fd2029f23 3 ** Version: rev. 1.0, 2014-05-14
mbed_official 324:406fd2029f23 4 ** Build: b140515
mbed_official 324:406fd2029f23 5 **
mbed_official 324:406fd2029f23 6 ** Abstract:
mbed_official 324:406fd2029f23 7 ** Chip specific module features.
mbed_official 324:406fd2029f23 8 **
mbed_official 324:406fd2029f23 9 ** Copyright: 2014 Freescale Semiconductor, Inc.
mbed_official 324:406fd2029f23 10 ** All rights reserved.
mbed_official 324:406fd2029f23 11 **
mbed_official 324:406fd2029f23 12 ** Redistribution and use in source and binary forms, with or without modification,
mbed_official 324:406fd2029f23 13 ** are permitted provided that the following conditions are met:
mbed_official 324:406fd2029f23 14 **
mbed_official 324:406fd2029f23 15 ** o Redistributions of source code must retain the above copyright notice, this list
mbed_official 324:406fd2029f23 16 ** of conditions and the following disclaimer.
mbed_official 324:406fd2029f23 17 **
mbed_official 324:406fd2029f23 18 ** o Redistributions in binary form must reproduce the above copyright notice, this
mbed_official 324:406fd2029f23 19 ** list of conditions and the following disclaimer in the documentation and/or
mbed_official 324:406fd2029f23 20 ** other materials provided with the distribution.
mbed_official 324:406fd2029f23 21 **
mbed_official 324:406fd2029f23 22 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
mbed_official 324:406fd2029f23 23 ** contributors may be used to endorse or promote products derived from this
mbed_official 324:406fd2029f23 24 ** software without specific prior written permission.
mbed_official 324:406fd2029f23 25 **
mbed_official 324:406fd2029f23 26 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
mbed_official 324:406fd2029f23 27 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
mbed_official 324:406fd2029f23 28 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 324:406fd2029f23 29 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
mbed_official 324:406fd2029f23 30 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
mbed_official 324:406fd2029f23 31 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
mbed_official 324:406fd2029f23 32 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
mbed_official 324:406fd2029f23 33 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
mbed_official 324:406fd2029f23 34 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
mbed_official 324:406fd2029f23 35 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 324:406fd2029f23 36 **
mbed_official 324:406fd2029f23 37 ** http: www.freescale.com
mbed_official 324:406fd2029f23 38 ** mail: support@freescale.com
mbed_official 324:406fd2029f23 39 **
mbed_official 324:406fd2029f23 40 ** Revisions:
mbed_official 324:406fd2029f23 41 ** - rev. 1.0 (2014-05-14)
mbed_official 324:406fd2029f23 42 ** Customer release.
mbed_official 324:406fd2029f23 43 **
mbed_official 324:406fd2029f23 44 ** ###################################################################
mbed_official 324:406fd2029f23 45 */
mbed_official 324:406fd2029f23 46
mbed_official 146:f64d43ff0c18 47 #if !defined(__FSL_UART_FEATURES_H__)
mbed_official 146:f64d43ff0c18 48 #define __FSL_UART_FEATURES_H__
mbed_official 146:f64d43ff0c18 49
mbed_official 324:406fd2029f23 50 #if defined(CPU_MK02FN128VFM10) || defined(CPU_MK02FN64VFM10) || defined(CPU_MK02FN128VLF10) || defined(CPU_MK02FN64VLF10) || \
mbed_official 324:406fd2029f23 51 defined(CPU_MK02FN128VLH10) || defined(CPU_MK02FN64VLH10) || defined(CPU_MKV30F128VFM10) || defined(CPU_MKV30F64VFM10) || \
mbed_official 324:406fd2029f23 52 defined(CPU_MKV30F128VLF10) || defined(CPU_MKV30F64VLF10) || defined(CPU_MKV30F128VLH10) || defined(CPU_MKV30F64VLH10)
mbed_official 324:406fd2029f23 53 /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */
mbed_official 146:f64d43ff0c18 54 #define FSL_FEATURE_UART_HAS_IRQ_EXTENDED_FUNCTIONS (1)
mbed_official 324:406fd2029f23 55 /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */
mbed_official 146:f64d43ff0c18 56 #define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORT (0)
mbed_official 324:406fd2029f23 57 #define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORTn(x) \
mbed_official 324:406fd2029f23 58 ((x) == 0 ? (0) : \
mbed_official 324:406fd2029f23 59 ((x) == 1 ? (0) : (-1)))
mbed_official 324:406fd2029f23 60 /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */
mbed_official 146:f64d43ff0c18 61 #define FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1)
mbed_official 324:406fd2029f23 62 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
mbed_official 324:406fd2029f23 63 #define FSL_FEATURE_UART_HAS_FIFO (1)
mbed_official 324:406fd2029f23 64 /* @brief Hardware flow control (RTS, CTS) is supported. */
mbed_official 324:406fd2029f23 65 #define FSL_FEATURE_UART_HAS_MODEM_SUPPORT (1)
mbed_official 324:406fd2029f23 66 /* @brief Infrared (modulation) is supported. */
mbed_official 324:406fd2029f23 67 #define FSL_FEATURE_UART_HAS_IR_SUPPORT (1)
mbed_official 324:406fd2029f23 68 /* @brief 2 bits long stop bit is available. */
mbed_official 324:406fd2029f23 69 #define FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT (0)
mbed_official 324:406fd2029f23 70 /* @brief Maximal data width without parity bit. */
mbed_official 324:406fd2029f23 71 #define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORT (0)
mbed_official 324:406fd2029f23 72 #define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORTn(x) \
mbed_official 324:406fd2029f23 73 ((x) == 0 ? (0) : \
mbed_official 324:406fd2029f23 74 ((x) == 1 ? (0) : (-1)))
mbed_official 324:406fd2029f23 75 /* @brief Baud rate fine adjustment is available. */
mbed_official 324:406fd2029f23 76 #define FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (1)
mbed_official 324:406fd2029f23 77 /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */
mbed_official 324:406fd2029f23 78 #define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (0)
mbed_official 324:406fd2029f23 79 #define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORTn(x) \
mbed_official 324:406fd2029f23 80 ((x) == 0 ? (0) : \
mbed_official 324:406fd2029f23 81 ((x) == 1 ? (0) : (-1)))
mbed_official 324:406fd2029f23 82 /* @brief Baud rate oversampling is available. */
mbed_official 324:406fd2029f23 83 #define FSL_FEATURE_UART_HAS_RX_RESYNC_SUPPORT (0)
mbed_official 324:406fd2029f23 84 /* @brief Baud rate oversampling is available. */
mbed_official 324:406fd2029f23 85 #define FSL_FEATURE_UART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (0)
mbed_official 324:406fd2029f23 86 /* @brief Peripheral type. */
mbed_official 324:406fd2029f23 87 #define FSL_FEATURE_UART_IS_SCI (0)
mbed_official 324:406fd2029f23 88 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
mbed_official 324:406fd2029f23 89 #define FSL_FEATURE_UART_FIFO_SIZE (8)
mbed_official 324:406fd2029f23 90 #define FSL_FEATURE_UART_FIFO_SIZEn(x) \
mbed_official 324:406fd2029f23 91 ((x) == 0 ? (8) : \
mbed_official 324:406fd2029f23 92 ((x) == 1 ? (1) : (-1)))
mbed_official 324:406fd2029f23 93 /* @brief Maximal data width without parity bit. */
mbed_official 324:406fd2029f23 94 #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_NO_PARITY (9)
mbed_official 324:406fd2029f23 95 #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_NO_PARITYn(x) \
mbed_official 324:406fd2029f23 96 ((x) == 0 ? (9) : \
mbed_official 324:406fd2029f23 97 ((x) == 1 ? (9) : (-1)))
mbed_official 324:406fd2029f23 98 /* @brief Maximal data width with parity bit. */
mbed_official 324:406fd2029f23 99 #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_PARITY (10)
mbed_official 324:406fd2029f23 100 #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_PARITYn(x) \
mbed_official 324:406fd2029f23 101 ((x) == 0 ? (10) : \
mbed_official 324:406fd2029f23 102 ((x) == 1 ? (10) : (-1)))
mbed_official 324:406fd2029f23 103 /* @brief Supports two match addresses to filter incoming frames. */
mbed_official 324:406fd2029f23 104 #define FSL_FEATURE_UART_HAS_ADDRESS_MATCHING (1)
mbed_official 324:406fd2029f23 105 #define FSL_FEATURE_UART_HAS_ADDRESS_MATCHINGn(x) \
mbed_official 324:406fd2029f23 106 ((x) == 0 ? (1) : \
mbed_official 324:406fd2029f23 107 ((x) == 1 ? (1) : (-1)))
mbed_official 324:406fd2029f23 108 /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */
mbed_official 324:406fd2029f23 109 #define FSL_FEATURE_UART_HAS_DMA_ENABLE (0)
mbed_official 324:406fd2029f23 110 #define FSL_FEATURE_UART_HAS_DMA_ENABLEn(x) \
mbed_official 324:406fd2029f23 111 ((x) == 0 ? (0) : \
mbed_official 324:406fd2029f23 112 ((x) == 1 ? (0) : (-1)))
mbed_official 324:406fd2029f23 113 /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */
mbed_official 324:406fd2029f23 114 #define FSL_FEATURE_UART_HAS_DMA_SELECT (1)
mbed_official 324:406fd2029f23 115 #define FSL_FEATURE_UART_HAS_DMA_SELECTn(x) \
mbed_official 324:406fd2029f23 116 ((x) == 0 ? (1) : \
mbed_official 324:406fd2029f23 117 ((x) == 1 ? (1) : (-1)))
mbed_official 324:406fd2029f23 118 /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */
mbed_official 324:406fd2029f23 119 #define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECT (1)
mbed_official 324:406fd2029f23 120 #define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECTn(x) \
mbed_official 324:406fd2029f23 121 ((x) == 0 ? (1) : \
mbed_official 324:406fd2029f23 122 ((x) == 1 ? (1) : (-1)))
mbed_official 324:406fd2029f23 123 /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */
mbed_official 324:406fd2029f23 124 #define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORT (0)
mbed_official 324:406fd2029f23 125 #define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORTn(x) \
mbed_official 324:406fd2029f23 126 ((x) == 0 ? (0) : \
mbed_official 324:406fd2029f23 127 ((x) == 1 ? (0) : (-1)))
mbed_official 324:406fd2029f23 128 /* @brief Has improved smart card (ISO7816 protocol) support. */
mbed_official 324:406fd2029f23 129 #define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT (0)
mbed_official 324:406fd2029f23 130 #define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORTn(x) \
mbed_official 324:406fd2029f23 131 ((x) == 0 ? (0) : \
mbed_official 324:406fd2029f23 132 ((x) == 1 ? (0) : (-1)))
mbed_official 324:406fd2029f23 133 /* @brief Has local operation network (CEA709.1-B protocol) support. */
mbed_official 324:406fd2029f23 134 #define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0)
mbed_official 324:406fd2029f23 135 #define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORTn(x) \
mbed_official 324:406fd2029f23 136 ((x) == 0 ? (0) : \
mbed_official 324:406fd2029f23 137 ((x) == 1 ? (0) : (-1)))
mbed_official 324:406fd2029f23 138 /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */
mbed_official 324:406fd2029f23 139 #define FSL_FEATURE_UART_HAS_32BIT_REGISTERS (0)
mbed_official 324:406fd2029f23 140 #elif defined(CPU_MK20DX128VMP5) || defined(CPU_MK20DN128VMP5) || defined(CPU_MK20DX64VMP5) || defined(CPU_MK20DN64VMP5) || \
mbed_official 324:406fd2029f23 141 defined(CPU_MK20DX32VMP5) || defined(CPU_MK20DN32VMP5) || defined(CPU_MK20DX128VLH5) || defined(CPU_MK20DN128VLH5) || \
mbed_official 324:406fd2029f23 142 defined(CPU_MK20DX64VLH5) || defined(CPU_MK20DN64VLH5) || defined(CPU_MK20DX32VLH5) || defined(CPU_MK20DN32VLH5) || \
mbed_official 324:406fd2029f23 143 defined(CPU_MK20DX128VFT5) || defined(CPU_MK20DN128VFT5) || defined(CPU_MK20DX64VFT5) || defined(CPU_MK20DN64VFT5) || \
mbed_official 324:406fd2029f23 144 defined(CPU_MK20DX32VFT5) || defined(CPU_MK20DN32VFT5) || defined(CPU_MK20DX128VLF5) || defined(CPU_MK20DN128VLF5) || \
mbed_official 324:406fd2029f23 145 defined(CPU_MK20DX64VLF5) || defined(CPU_MK20DN64VLF5) || defined(CPU_MK20DX32VLF5) || defined(CPU_MK20DN32VLF5)
mbed_official 324:406fd2029f23 146 /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */
mbed_official 324:406fd2029f23 147 #define FSL_FEATURE_UART_HAS_IRQ_EXTENDED_FUNCTIONS (0)
mbed_official 324:406fd2029f23 148 /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */
mbed_official 324:406fd2029f23 149 #define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORT (0)
mbed_official 324:406fd2029f23 150 #define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORTn(x) \
mbed_official 324:406fd2029f23 151 ((x) == 0 ? (0) : \
mbed_official 324:406fd2029f23 152 ((x) == 1 ? (0) : \
mbed_official 324:406fd2029f23 153 ((x) == 2 ? (0) : (-1))))
mbed_official 324:406fd2029f23 154 /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */
mbed_official 324:406fd2029f23 155 #define FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1)
mbed_official 324:406fd2029f23 156 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
mbed_official 146:f64d43ff0c18 157 #define FSL_FEATURE_UART_HAS_FIFO (1)
mbed_official 324:406fd2029f23 158 /* @brief Hardware flow control (RTS, CTS) is supported. */
mbed_official 146:f64d43ff0c18 159 #define FSL_FEATURE_UART_HAS_MODEM_SUPPORT (1)
mbed_official 324:406fd2029f23 160 /* @brief Infrared (modulation) is supported. */
mbed_official 146:f64d43ff0c18 161 #define FSL_FEATURE_UART_HAS_IR_SUPPORT (1)
mbed_official 324:406fd2029f23 162 /* @brief 2 bits long stop bit is available. */
mbed_official 324:406fd2029f23 163 #define FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT (0)
mbed_official 324:406fd2029f23 164 /* @brief Maximal data width without parity bit. */
mbed_official 324:406fd2029f23 165 #define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORT (0)
mbed_official 324:406fd2029f23 166 #define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORTn(x) \
mbed_official 324:406fd2029f23 167 ((x) == 0 ? (0) : \
mbed_official 324:406fd2029f23 168 ((x) == 1 ? (0) : \
mbed_official 324:406fd2029f23 169 ((x) == 2 ? (0) : (-1))))
mbed_official 324:406fd2029f23 170 /* @brief Baud rate fine adjustment is available. */
mbed_official 324:406fd2029f23 171 #define FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (1)
mbed_official 324:406fd2029f23 172 /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */
mbed_official 324:406fd2029f23 173 #define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (0)
mbed_official 324:406fd2029f23 174 #define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORTn(x) \
mbed_official 324:406fd2029f23 175 ((x) == 0 ? (0) : \
mbed_official 324:406fd2029f23 176 ((x) == 1 ? (0) : \
mbed_official 324:406fd2029f23 177 ((x) == 2 ? (0) : (-1))))
mbed_official 324:406fd2029f23 178 /* @brief Baud rate oversampling is available. */
mbed_official 324:406fd2029f23 179 #define FSL_FEATURE_UART_HAS_RX_RESYNC_SUPPORT (0)
mbed_official 324:406fd2029f23 180 /* @brief Baud rate oversampling is available. */
mbed_official 324:406fd2029f23 181 #define FSL_FEATURE_UART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (0)
mbed_official 324:406fd2029f23 182 /* @brief Peripheral type. */
mbed_official 324:406fd2029f23 183 #define FSL_FEATURE_UART_IS_SCI (0)
mbed_official 324:406fd2029f23 184 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
mbed_official 324:406fd2029f23 185 #define FSL_FEATURE_UART_FIFO_SIZE (8)
mbed_official 324:406fd2029f23 186 #define FSL_FEATURE_UART_FIFO_SIZEn(x) \
mbed_official 324:406fd2029f23 187 ((x) == 0 ? (8) : \
mbed_official 324:406fd2029f23 188 ((x) == 1 ? (1) : \
mbed_official 324:406fd2029f23 189 ((x) == 2 ? (1) : (-1))))
mbed_official 324:406fd2029f23 190 /* @brief Maximal data width without parity bit. */
mbed_official 324:406fd2029f23 191 #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_NO_PARITY (9)
mbed_official 324:406fd2029f23 192 #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_NO_PARITYn(x) \
mbed_official 324:406fd2029f23 193 ((x) == 0 ? (9) : \
mbed_official 324:406fd2029f23 194 ((x) == 1 ? (9) : \
mbed_official 324:406fd2029f23 195 ((x) == 2 ? (9) : (-1))))
mbed_official 324:406fd2029f23 196 /* @brief Maximal data width with parity bit. */
mbed_official 324:406fd2029f23 197 #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_PARITY (10)
mbed_official 324:406fd2029f23 198 #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_PARITYn(x) \
mbed_official 324:406fd2029f23 199 ((x) == 0 ? (10) : \
mbed_official 324:406fd2029f23 200 ((x) == 1 ? (10) : \
mbed_official 324:406fd2029f23 201 ((x) == 2 ? (10) : (-1))))
mbed_official 324:406fd2029f23 202 /* @brief Supports two match addresses to filter incoming frames. */
mbed_official 324:406fd2029f23 203 #define FSL_FEATURE_UART_HAS_ADDRESS_MATCHING (1)
mbed_official 324:406fd2029f23 204 #define FSL_FEATURE_UART_HAS_ADDRESS_MATCHINGn(x) \
mbed_official 324:406fd2029f23 205 ((x) == 0 ? (1) : \
mbed_official 324:406fd2029f23 206 ((x) == 1 ? (1) : \
mbed_official 324:406fd2029f23 207 ((x) == 2 ? (1) : (-1))))
mbed_official 324:406fd2029f23 208 /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */
mbed_official 324:406fd2029f23 209 #define FSL_FEATURE_UART_HAS_DMA_ENABLE (0)
mbed_official 324:406fd2029f23 210 #define FSL_FEATURE_UART_HAS_DMA_ENABLEn(x) \
mbed_official 324:406fd2029f23 211 ((x) == 0 ? (0) : \
mbed_official 324:406fd2029f23 212 ((x) == 1 ? (0) : \
mbed_official 324:406fd2029f23 213 ((x) == 2 ? (0) : (-1))))
mbed_official 324:406fd2029f23 214 /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */
mbed_official 324:406fd2029f23 215 #define FSL_FEATURE_UART_HAS_DMA_SELECT (1)
mbed_official 324:406fd2029f23 216 #define FSL_FEATURE_UART_HAS_DMA_SELECTn(x) \
mbed_official 324:406fd2029f23 217 ((x) == 0 ? (1) : \
mbed_official 324:406fd2029f23 218 ((x) == 1 ? (1) : \
mbed_official 324:406fd2029f23 219 ((x) == 2 ? (1) : (-1))))
mbed_official 324:406fd2029f23 220 /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */
mbed_official 324:406fd2029f23 221 #define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECT (1)
mbed_official 324:406fd2029f23 222 #define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECTn(x) \
mbed_official 324:406fd2029f23 223 ((x) == 0 ? (1) : \
mbed_official 324:406fd2029f23 224 ((x) == 1 ? (1) : \
mbed_official 324:406fd2029f23 225 ((x) == 2 ? (1) : (-1))))
mbed_official 324:406fd2029f23 226 /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */
mbed_official 324:406fd2029f23 227 #define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORT (1)
mbed_official 324:406fd2029f23 228 #define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORTn(x) \
mbed_official 324:406fd2029f23 229 ((x) == 0 ? (1) : \
mbed_official 324:406fd2029f23 230 ((x) == 1 ? (0) : \
mbed_official 324:406fd2029f23 231 ((x) == 2 ? (0) : (-1))))
mbed_official 324:406fd2029f23 232 /* @brief Has improved smart card (ISO7816 protocol) support. */
mbed_official 324:406fd2029f23 233 #define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT (0)
mbed_official 324:406fd2029f23 234 #define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORTn(x) \
mbed_official 324:406fd2029f23 235 ((x) == 0 ? (0) : \
mbed_official 324:406fd2029f23 236 ((x) == 1 ? (0) : \
mbed_official 324:406fd2029f23 237 ((x) == 2 ? (0) : (-1))))
mbed_official 324:406fd2029f23 238 /* @brief Has local operation network (CEA709.1-B protocol) support. */
mbed_official 324:406fd2029f23 239 #define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (1)
mbed_official 324:406fd2029f23 240 #define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORTn(x) \
mbed_official 324:406fd2029f23 241 ((x) == 0 ? (1) : \
mbed_official 324:406fd2029f23 242 ((x) == 1 ? (0) : \
mbed_official 324:406fd2029f23 243 ((x) == 2 ? (0) : (-1))))
mbed_official 324:406fd2029f23 244 /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */
mbed_official 324:406fd2029f23 245 #define FSL_FEATURE_UART_HAS_32BIT_REGISTERS (0)
mbed_official 324:406fd2029f23 246 #elif defined(CPU_MK20DX128VFM5) || defined(CPU_MK20DN128VFM5) || defined(CPU_MK20DX64VFM5) || defined(CPU_MK20DN64VFM5) || \
mbed_official 324:406fd2029f23 247 defined(CPU_MK20DX32VFM5) || defined(CPU_MK20DN32VFM5)
mbed_official 324:406fd2029f23 248 /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */
mbed_official 324:406fd2029f23 249 #define FSL_FEATURE_UART_HAS_IRQ_EXTENDED_FUNCTIONS (0)
mbed_official 324:406fd2029f23 250 /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */
mbed_official 324:406fd2029f23 251 #define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORT (0)
mbed_official 324:406fd2029f23 252 #define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORTn(x) \
mbed_official 324:406fd2029f23 253 ((x) == 0 ? (0) : \
mbed_official 324:406fd2029f23 254 ((x) == 1 ? (0) : (-1)))
mbed_official 324:406fd2029f23 255 /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */
mbed_official 324:406fd2029f23 256 #define FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1)
mbed_official 324:406fd2029f23 257 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
mbed_official 324:406fd2029f23 258 #define FSL_FEATURE_UART_HAS_FIFO (1)
mbed_official 324:406fd2029f23 259 /* @brief Hardware flow control (RTS, CTS) is supported. */
mbed_official 324:406fd2029f23 260 #define FSL_FEATURE_UART_HAS_MODEM_SUPPORT (1)
mbed_official 324:406fd2029f23 261 /* @brief Infrared (modulation) is supported. */
mbed_official 324:406fd2029f23 262 #define FSL_FEATURE_UART_HAS_IR_SUPPORT (1)
mbed_official 324:406fd2029f23 263 /* @brief 2 bits long stop bit is available. */
mbed_official 146:f64d43ff0c18 264 #define FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT (0)
mbed_official 324:406fd2029f23 265 /* @brief Maximal data width without parity bit. */
mbed_official 146:f64d43ff0c18 266 #define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORT (0)
mbed_official 324:406fd2029f23 267 #define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORTn(x) \
mbed_official 324:406fd2029f23 268 ((x) == 0 ? (0) : \
mbed_official 324:406fd2029f23 269 ((x) == 1 ? (0) : (-1)))
mbed_official 324:406fd2029f23 270 /* @brief Baud rate fine adjustment is available. */
mbed_official 146:f64d43ff0c18 271 #define FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (1)
mbed_official 324:406fd2029f23 272 /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */
mbed_official 324:406fd2029f23 273 #define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (0)
mbed_official 324:406fd2029f23 274 #define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORTn(x) \
mbed_official 324:406fd2029f23 275 ((x) == 0 ? (0) : \
mbed_official 324:406fd2029f23 276 ((x) == 1 ? (0) : (-1)))
mbed_official 324:406fd2029f23 277 /* @brief Baud rate oversampling is available. */
mbed_official 324:406fd2029f23 278 #define FSL_FEATURE_UART_HAS_RX_RESYNC_SUPPORT (0)
mbed_official 324:406fd2029f23 279 /* @brief Baud rate oversampling is available. */
mbed_official 324:406fd2029f23 280 #define FSL_FEATURE_UART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (0)
mbed_official 324:406fd2029f23 281 /* @brief Peripheral type. */
mbed_official 324:406fd2029f23 282 #define FSL_FEATURE_UART_IS_SCI (0)
mbed_official 324:406fd2029f23 283 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
mbed_official 324:406fd2029f23 284 #define FSL_FEATURE_UART_FIFO_SIZE (8)
mbed_official 324:406fd2029f23 285 #define FSL_FEATURE_UART_FIFO_SIZEn(x) \
mbed_official 324:406fd2029f23 286 ((x) == 0 ? (8) : \
mbed_official 324:406fd2029f23 287 ((x) == 1 ? (1) : (-1)))
mbed_official 324:406fd2029f23 288 /* @brief Maximal data width without parity bit. */
mbed_official 324:406fd2029f23 289 #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_NO_PARITY (9)
mbed_official 324:406fd2029f23 290 #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_NO_PARITYn(x) \
mbed_official 324:406fd2029f23 291 ((x) == 0 ? (9) : \
mbed_official 324:406fd2029f23 292 ((x) == 1 ? (9) : (-1)))
mbed_official 324:406fd2029f23 293 /* @brief Maximal data width with parity bit. */
mbed_official 324:406fd2029f23 294 #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_PARITY (10)
mbed_official 324:406fd2029f23 295 #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_PARITYn(x) \
mbed_official 324:406fd2029f23 296 ((x) == 0 ? (10) : \
mbed_official 324:406fd2029f23 297 ((x) == 1 ? (10) : (-1)))
mbed_official 324:406fd2029f23 298 /* @brief Supports two match addresses to filter incoming frames. */
mbed_official 324:406fd2029f23 299 #define FSL_FEATURE_UART_HAS_ADDRESS_MATCHING (1)
mbed_official 324:406fd2029f23 300 #define FSL_FEATURE_UART_HAS_ADDRESS_MATCHINGn(x) \
mbed_official 324:406fd2029f23 301 ((x) == 0 ? (1) : \
mbed_official 324:406fd2029f23 302 ((x) == 1 ? (1) : (-1)))
mbed_official 324:406fd2029f23 303 /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */
mbed_official 324:406fd2029f23 304 #define FSL_FEATURE_UART_HAS_DMA_ENABLE (0)
mbed_official 324:406fd2029f23 305 #define FSL_FEATURE_UART_HAS_DMA_ENABLEn(x) \
mbed_official 324:406fd2029f23 306 ((x) == 0 ? (0) : \
mbed_official 324:406fd2029f23 307 ((x) == 1 ? (0) : (-1)))
mbed_official 324:406fd2029f23 308 /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */
mbed_official 324:406fd2029f23 309 #define FSL_FEATURE_UART_HAS_DMA_SELECT (1)
mbed_official 324:406fd2029f23 310 #define FSL_FEATURE_UART_HAS_DMA_SELECTn(x) \
mbed_official 324:406fd2029f23 311 ((x) == 0 ? (1) : \
mbed_official 324:406fd2029f23 312 ((x) == 1 ? (1) : (-1)))
mbed_official 324:406fd2029f23 313 /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */
mbed_official 324:406fd2029f23 314 #define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECT (1)
mbed_official 324:406fd2029f23 315 #define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECTn(x) \
mbed_official 324:406fd2029f23 316 ((x) == 0 ? (1) : \
mbed_official 324:406fd2029f23 317 ((x) == 1 ? (1) : (-1)))
mbed_official 324:406fd2029f23 318 /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */
mbed_official 324:406fd2029f23 319 #define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORT (1)
mbed_official 324:406fd2029f23 320 #define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORTn(x) \
mbed_official 324:406fd2029f23 321 ((x) == 0 ? (1) : \
mbed_official 324:406fd2029f23 322 ((x) == 1 ? (0) : (-1)))
mbed_official 324:406fd2029f23 323 /* @brief Has improved smart card (ISO7816 protocol) support. */
mbed_official 324:406fd2029f23 324 #define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT (0)
mbed_official 324:406fd2029f23 325 #define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORTn(x) \
mbed_official 324:406fd2029f23 326 ((x) == 0 ? (0) : \
mbed_official 324:406fd2029f23 327 ((x) == 1 ? (0) : (-1)))
mbed_official 324:406fd2029f23 328 /* @brief Has local operation network (CEA709.1-B protocol) support. */
mbed_official 324:406fd2029f23 329 #define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (1)
mbed_official 324:406fd2029f23 330 #define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORTn(x) \
mbed_official 324:406fd2029f23 331 ((x) == 0 ? (1) : \
mbed_official 324:406fd2029f23 332 ((x) == 1 ? (0) : (-1)))
mbed_official 324:406fd2029f23 333 /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */
mbed_official 324:406fd2029f23 334 #define FSL_FEATURE_UART_HAS_32BIT_REGISTERS (0)
mbed_official 324:406fd2029f23 335 #elif defined(CPU_MK22FN128VDC10) || defined(CPU_MK22FN128VLH10) || defined(CPU_MK22FN128VLL10) || defined(CPU_MK22FN128VMP10) || \
mbed_official 324:406fd2029f23 336 defined(CPU_MK22FN256VDC12) || defined(CPU_MK22FN256VLH12) || defined(CPU_MK22FN256VLL12) || defined(CPU_MK22FN256VMP12) || \
mbed_official 324:406fd2029f23 337 defined(CPU_MK22FN512VDC12) || defined(CPU_MK22FN512VLH12) || defined(CPU_MK22FN512VLL12) || defined(CPU_MKV31F128VLH10) || \
mbed_official 324:406fd2029f23 338 defined(CPU_MKV31F128VLL10) || defined(CPU_MKV31F256VLH12) || defined(CPU_MKV31F256VLL12) || defined(CPU_MKV31F512VLH12) || \
mbed_official 324:406fd2029f23 339 defined(CPU_MKV31F512VLL12)
mbed_official 324:406fd2029f23 340 /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */
mbed_official 324:406fd2029f23 341 #define FSL_FEATURE_UART_HAS_IRQ_EXTENDED_FUNCTIONS (1)
mbed_official 324:406fd2029f23 342 /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */
mbed_official 324:406fd2029f23 343 #define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORT (0)
mbed_official 324:406fd2029f23 344 #define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORTn(x) \
mbed_official 324:406fd2029f23 345 ((x) == 0 ? (0) : \
mbed_official 324:406fd2029f23 346 ((x) == 1 ? (0) : \
mbed_official 324:406fd2029f23 347 ((x) == 2 ? (0) : (-1))))
mbed_official 324:406fd2029f23 348 /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */
mbed_official 324:406fd2029f23 349 #define FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1)
mbed_official 324:406fd2029f23 350 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
mbed_official 324:406fd2029f23 351 #define FSL_FEATURE_UART_HAS_FIFO (1)
mbed_official 324:406fd2029f23 352 /* @brief Hardware flow control (RTS, CTS) is supported. */
mbed_official 324:406fd2029f23 353 #define FSL_FEATURE_UART_HAS_MODEM_SUPPORT (1)
mbed_official 324:406fd2029f23 354 /* @brief Infrared (modulation) is supported. */
mbed_official 324:406fd2029f23 355 #define FSL_FEATURE_UART_HAS_IR_SUPPORT (1)
mbed_official 324:406fd2029f23 356 /* @brief 2 bits long stop bit is available. */
mbed_official 324:406fd2029f23 357 #define FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT (0)
mbed_official 324:406fd2029f23 358 /* @brief Maximal data width without parity bit. */
mbed_official 324:406fd2029f23 359 #define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORT (0)
mbed_official 324:406fd2029f23 360 #define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORTn(x) \
mbed_official 324:406fd2029f23 361 ((x) == 0 ? (0) : \
mbed_official 324:406fd2029f23 362 ((x) == 1 ? (0) : \
mbed_official 324:406fd2029f23 363 ((x) == 2 ? (0) : (-1))))
mbed_official 324:406fd2029f23 364 /* @brief Baud rate fine adjustment is available. */
mbed_official 324:406fd2029f23 365 #define FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (1)
mbed_official 324:406fd2029f23 366 /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */
mbed_official 146:f64d43ff0c18 367 #define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (0)
mbed_official 324:406fd2029f23 368 #define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORTn(x) \
mbed_official 324:406fd2029f23 369 ((x) == 0 ? (0) : \
mbed_official 324:406fd2029f23 370 ((x) == 1 ? (0) : \
mbed_official 324:406fd2029f23 371 ((x) == 2 ? (0) : (-1))))
mbed_official 324:406fd2029f23 372 /* @brief Baud rate oversampling is available. */
mbed_official 146:f64d43ff0c18 373 #define FSL_FEATURE_UART_HAS_RX_RESYNC_SUPPORT (0)
mbed_official 324:406fd2029f23 374 /* @brief Baud rate oversampling is available. */
mbed_official 146:f64d43ff0c18 375 #define FSL_FEATURE_UART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (0)
mbed_official 324:406fd2029f23 376 /* @brief Peripheral type. */
mbed_official 324:406fd2029f23 377 #define FSL_FEATURE_UART_IS_SCI (0)
mbed_official 324:406fd2029f23 378 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
mbed_official 324:406fd2029f23 379 #define FSL_FEATURE_UART_FIFO_SIZE (8)
mbed_official 324:406fd2029f23 380 #define FSL_FEATURE_UART_FIFO_SIZEn(x) \
mbed_official 324:406fd2029f23 381 ((x) == 0 ? (8) : \
mbed_official 324:406fd2029f23 382 ((x) == 1 ? (1) : \
mbed_official 324:406fd2029f23 383 ((x) == 2 ? (1) : (-1))))
mbed_official 324:406fd2029f23 384 /* @brief Maximal data width without parity bit. */
mbed_official 324:406fd2029f23 385 #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_NO_PARITY (9)
mbed_official 324:406fd2029f23 386 #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_NO_PARITYn(x) \
mbed_official 324:406fd2029f23 387 ((x) == 0 ? (9) : \
mbed_official 324:406fd2029f23 388 ((x) == 1 ? (9) : \
mbed_official 324:406fd2029f23 389 ((x) == 2 ? (9) : (-1))))
mbed_official 324:406fd2029f23 390 /* @brief Maximal data width with parity bit. */
mbed_official 324:406fd2029f23 391 #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_PARITY (10)
mbed_official 324:406fd2029f23 392 #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_PARITYn(x) \
mbed_official 324:406fd2029f23 393 ((x) == 0 ? (10) : \
mbed_official 324:406fd2029f23 394 ((x) == 1 ? (10) : \
mbed_official 324:406fd2029f23 395 ((x) == 2 ? (10) : (-1))))
mbed_official 324:406fd2029f23 396 /* @brief Supports two match addresses to filter incoming frames. */
mbed_official 324:406fd2029f23 397 #define FSL_FEATURE_UART_HAS_ADDRESS_MATCHING (1)
mbed_official 324:406fd2029f23 398 #define FSL_FEATURE_UART_HAS_ADDRESS_MATCHINGn(x) \
mbed_official 324:406fd2029f23 399 ((x) == 0 ? (1) : \
mbed_official 324:406fd2029f23 400 ((x) == 1 ? (1) : \
mbed_official 324:406fd2029f23 401 ((x) == 2 ? (1) : (-1))))
mbed_official 324:406fd2029f23 402 /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */
mbed_official 324:406fd2029f23 403 #define FSL_FEATURE_UART_HAS_DMA_ENABLE (0)
mbed_official 324:406fd2029f23 404 #define FSL_FEATURE_UART_HAS_DMA_ENABLEn(x) \
mbed_official 324:406fd2029f23 405 ((x) == 0 ? (0) : \
mbed_official 324:406fd2029f23 406 ((x) == 1 ? (0) : \
mbed_official 324:406fd2029f23 407 ((x) == 2 ? (0) : (-1))))
mbed_official 324:406fd2029f23 408 /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */
mbed_official 324:406fd2029f23 409 #define FSL_FEATURE_UART_HAS_DMA_SELECT (1)
mbed_official 324:406fd2029f23 410 #define FSL_FEATURE_UART_HAS_DMA_SELECTn(x) \
mbed_official 324:406fd2029f23 411 ((x) == 0 ? (1) : \
mbed_official 324:406fd2029f23 412 ((x) == 1 ? (1) : \
mbed_official 324:406fd2029f23 413 ((x) == 2 ? (1) : (-1))))
mbed_official 324:406fd2029f23 414 /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */
mbed_official 324:406fd2029f23 415 #define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECT (1)
mbed_official 324:406fd2029f23 416 #define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECTn(x) \
mbed_official 324:406fd2029f23 417 ((x) == 0 ? (1) : \
mbed_official 324:406fd2029f23 418 ((x) == 1 ? (1) : \
mbed_official 324:406fd2029f23 419 ((x) == 2 ? (1) : (-1))))
mbed_official 324:406fd2029f23 420 /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */
mbed_official 324:406fd2029f23 421 #define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORT (1)
mbed_official 324:406fd2029f23 422 #define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORTn(x) \
mbed_official 324:406fd2029f23 423 ((x) == 0 ? (1) : \
mbed_official 324:406fd2029f23 424 ((x) == 1 ? (0) : \
mbed_official 324:406fd2029f23 425 ((x) == 2 ? (0) : (-1))))
mbed_official 324:406fd2029f23 426 /* @brief Has improved smart card (ISO7816 protocol) support. */
mbed_official 324:406fd2029f23 427 #define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT (1)
mbed_official 324:406fd2029f23 428 #define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORTn(x) \
mbed_official 324:406fd2029f23 429 ((x) == 0 ? (1) : \
mbed_official 324:406fd2029f23 430 ((x) == 1 ? (0) : \
mbed_official 324:406fd2029f23 431 ((x) == 2 ? (0) : (-1))))
mbed_official 324:406fd2029f23 432 /* @brief Has local operation network (CEA709.1-B protocol) support. */
mbed_official 324:406fd2029f23 433 #define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0)
mbed_official 324:406fd2029f23 434 #define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORTn(x) \
mbed_official 324:406fd2029f23 435 ((x) == 0 ? (0) : \
mbed_official 324:406fd2029f23 436 ((x) == 1 ? (0) : \
mbed_official 324:406fd2029f23 437 ((x) == 2 ? (0) : (-1))))
mbed_official 324:406fd2029f23 438 /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */
mbed_official 324:406fd2029f23 439 #define FSL_FEATURE_UART_HAS_32BIT_REGISTERS (0)
mbed_official 324:406fd2029f23 440 #elif defined(CPU_MK24FN1M0VDC12) || defined(CPU_MK24FN1M0VLL12) || defined(CPU_MK24FN1M0VLQ12) || defined(CPU_MK24FN256VDC12) || \
mbed_official 324:406fd2029f23 441 defined(CPU_MK63FN1M0VLQ12) || defined(CPU_MK63FN1M0VMD12) || defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FN1M0VDC12) || \
mbed_official 324:406fd2029f23 442 defined(CPU_MK64FX512VLL12) || defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FN1M0VLQ12) || \
mbed_official 324:406fd2029f23 443 defined(CPU_MK64FX512VMD12) || defined(CPU_MK64FN1M0VMD12)
mbed_official 324:406fd2029f23 444 /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */
mbed_official 324:406fd2029f23 445 #define FSL_FEATURE_UART_HAS_IRQ_EXTENDED_FUNCTIONS (1)
mbed_official 324:406fd2029f23 446 /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */
mbed_official 324:406fd2029f23 447 #define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORT (0)
mbed_official 324:406fd2029f23 448 #define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORTn(x) \
mbed_official 324:406fd2029f23 449 ((x) == 0 ? (0) : \
mbed_official 324:406fd2029f23 450 ((x) == 1 ? (0) : \
mbed_official 324:406fd2029f23 451 ((x) == 2 ? (0) : \
mbed_official 324:406fd2029f23 452 ((x) == 3 ? (0) : \
mbed_official 324:406fd2029f23 453 ((x) == 4 ? (0) : \
mbed_official 324:406fd2029f23 454 ((x) == 5 ? (0) : (-1)))))))
mbed_official 324:406fd2029f23 455 /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */
mbed_official 324:406fd2029f23 456 #define FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1)
mbed_official 324:406fd2029f23 457 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
mbed_official 324:406fd2029f23 458 #define FSL_FEATURE_UART_HAS_FIFO (1)
mbed_official 324:406fd2029f23 459 /* @brief Hardware flow control (RTS, CTS) is supported. */
mbed_official 324:406fd2029f23 460 #define FSL_FEATURE_UART_HAS_MODEM_SUPPORT (1)
mbed_official 324:406fd2029f23 461 /* @brief Infrared (modulation) is supported. */
mbed_official 324:406fd2029f23 462 #define FSL_FEATURE_UART_HAS_IR_SUPPORT (1)
mbed_official 324:406fd2029f23 463 /* @brief 2 bits long stop bit is available. */
mbed_official 324:406fd2029f23 464 #define FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT (1)
mbed_official 324:406fd2029f23 465 /* @brief Maximal data width without parity bit. */
mbed_official 324:406fd2029f23 466 #define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORT (0)
mbed_official 324:406fd2029f23 467 #define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORTn(x) \
mbed_official 324:406fd2029f23 468 ((x) == 0 ? (0) : \
mbed_official 324:406fd2029f23 469 ((x) == 1 ? (0) : \
mbed_official 324:406fd2029f23 470 ((x) == 2 ? (0) : \
mbed_official 324:406fd2029f23 471 ((x) == 3 ? (0) : \
mbed_official 324:406fd2029f23 472 ((x) == 4 ? (0) : \
mbed_official 324:406fd2029f23 473 ((x) == 5 ? (0) : (-1)))))))
mbed_official 324:406fd2029f23 474 /* @brief Baud rate fine adjustment is available. */
mbed_official 324:406fd2029f23 475 #define FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (1)
mbed_official 324:406fd2029f23 476 /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */
mbed_official 324:406fd2029f23 477 #define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (0)
mbed_official 324:406fd2029f23 478 #define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORTn(x) \
mbed_official 324:406fd2029f23 479 ((x) == 0 ? (0) : \
mbed_official 324:406fd2029f23 480 ((x) == 1 ? (0) : \
mbed_official 324:406fd2029f23 481 ((x) == 2 ? (0) : \
mbed_official 324:406fd2029f23 482 ((x) == 3 ? (0) : \
mbed_official 324:406fd2029f23 483 ((x) == 4 ? (0) : \
mbed_official 324:406fd2029f23 484 ((x) == 5 ? (0) : (-1)))))))
mbed_official 324:406fd2029f23 485 /* @brief Baud rate oversampling is available. */
mbed_official 324:406fd2029f23 486 #define FSL_FEATURE_UART_HAS_RX_RESYNC_SUPPORT (0)
mbed_official 324:406fd2029f23 487 /* @brief Baud rate oversampling is available. */
mbed_official 324:406fd2029f23 488 #define FSL_FEATURE_UART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (0)
mbed_official 324:406fd2029f23 489 /* @brief Peripheral type. */
mbed_official 324:406fd2029f23 490 #define FSL_FEATURE_UART_IS_SCI (0)
mbed_official 324:406fd2029f23 491 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
mbed_official 324:406fd2029f23 492 #define FSL_FEATURE_UART_FIFO_SIZE (8)
mbed_official 146:f64d43ff0c18 493 #define FSL_FEATURE_UART_FIFO_SIZEn(x) \
mbed_official 146:f64d43ff0c18 494 ((x) == 0 ? (8) : \
mbed_official 146:f64d43ff0c18 495 ((x) == 1 ? (8) : \
mbed_official 146:f64d43ff0c18 496 ((x) == 2 ? (1) : \
mbed_official 146:f64d43ff0c18 497 ((x) == 3 ? (1) : \
mbed_official 146:f64d43ff0c18 498 ((x) == 4 ? (1) : \
mbed_official 146:f64d43ff0c18 499 ((x) == 5 ? (1) : (-1)))))))
mbed_official 324:406fd2029f23 500 /* @brief Maximal data width without parity bit. */
mbed_official 146:f64d43ff0c18 501 #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_NO_PARITY (9)
mbed_official 324:406fd2029f23 502 #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_NO_PARITYn(x) \
mbed_official 324:406fd2029f23 503 ((x) == 0 ? (9) : \
mbed_official 324:406fd2029f23 504 ((x) == 1 ? (9) : \
mbed_official 324:406fd2029f23 505 ((x) == 2 ? (9) : \
mbed_official 324:406fd2029f23 506 ((x) == 3 ? (9) : \
mbed_official 324:406fd2029f23 507 ((x) == 4 ? (9) : \
mbed_official 324:406fd2029f23 508 ((x) == 5 ? (9) : (-1)))))))
mbed_official 324:406fd2029f23 509 /* @brief Maximal data width with parity bit. */
mbed_official 324:406fd2029f23 510 #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_PARITY (10)
mbed_official 324:406fd2029f23 511 #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_PARITYn(x) \
mbed_official 324:406fd2029f23 512 ((x) == 0 ? (10) : \
mbed_official 324:406fd2029f23 513 ((x) == 1 ? (10) : \
mbed_official 324:406fd2029f23 514 ((x) == 2 ? (10) : \
mbed_official 324:406fd2029f23 515 ((x) == 3 ? (10) : \
mbed_official 324:406fd2029f23 516 ((x) == 4 ? (10) : \
mbed_official 324:406fd2029f23 517 ((x) == 5 ? (10) : (-1)))))))
mbed_official 324:406fd2029f23 518 /* @brief Supports two match addresses to filter incoming frames. */
mbed_official 146:f64d43ff0c18 519 #define FSL_FEATURE_UART_HAS_ADDRESS_MATCHING (1)
mbed_official 324:406fd2029f23 520 #define FSL_FEATURE_UART_HAS_ADDRESS_MATCHINGn(x) \
mbed_official 324:406fd2029f23 521 ((x) == 0 ? (1) : \
mbed_official 324:406fd2029f23 522 ((x) == 1 ? (1) : \
mbed_official 324:406fd2029f23 523 ((x) == 2 ? (1) : \
mbed_official 324:406fd2029f23 524 ((x) == 3 ? (1) : \
mbed_official 324:406fd2029f23 525 ((x) == 4 ? (1) : \
mbed_official 324:406fd2029f23 526 ((x) == 5 ? (1) : (-1)))))))
mbed_official 324:406fd2029f23 527 /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */
mbed_official 146:f64d43ff0c18 528 #define FSL_FEATURE_UART_HAS_DMA_ENABLE (0)
mbed_official 324:406fd2029f23 529 #define FSL_FEATURE_UART_HAS_DMA_ENABLEn(x) \
mbed_official 324:406fd2029f23 530 ((x) == 0 ? (0) : \
mbed_official 324:406fd2029f23 531 ((x) == 1 ? (0) : \
mbed_official 324:406fd2029f23 532 ((x) == 2 ? (0) : \
mbed_official 324:406fd2029f23 533 ((x) == 3 ? (0) : \
mbed_official 324:406fd2029f23 534 ((x) == 4 ? (0) : \
mbed_official 324:406fd2029f23 535 ((x) == 5 ? (0) : (-1)))))))
mbed_official 324:406fd2029f23 536 /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */
mbed_official 146:f64d43ff0c18 537 #define FSL_FEATURE_UART_HAS_DMA_SELECT (1)
mbed_official 324:406fd2029f23 538 #define FSL_FEATURE_UART_HAS_DMA_SELECTn(x) \
mbed_official 324:406fd2029f23 539 ((x) == 0 ? (1) : \
mbed_official 324:406fd2029f23 540 ((x) == 1 ? (1) : \
mbed_official 324:406fd2029f23 541 ((x) == 2 ? (1) : \
mbed_official 324:406fd2029f23 542 ((x) == 3 ? (1) : \
mbed_official 324:406fd2029f23 543 ((x) == 4 ? (1) : \
mbed_official 324:406fd2029f23 544 ((x) == 5 ? (1) : (-1)))))))
mbed_official 324:406fd2029f23 545 /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */
mbed_official 146:f64d43ff0c18 546 #define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECT (1)
mbed_official 324:406fd2029f23 547 #define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECTn(x) \
mbed_official 324:406fd2029f23 548 ((x) == 0 ? (1) : \
mbed_official 324:406fd2029f23 549 ((x) == 1 ? (1) : \
mbed_official 324:406fd2029f23 550 ((x) == 2 ? (1) : \
mbed_official 324:406fd2029f23 551 ((x) == 3 ? (1) : \
mbed_official 324:406fd2029f23 552 ((x) == 4 ? (1) : \
mbed_official 324:406fd2029f23 553 ((x) == 5 ? (1) : (-1)))))))
mbed_official 324:406fd2029f23 554 /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */
mbed_official 324:406fd2029f23 555 #define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORT (1)
mbed_official 146:f64d43ff0c18 556 #define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORTn(x) \
mbed_official 146:f64d43ff0c18 557 ((x) == 0 ? (1) : \
mbed_official 146:f64d43ff0c18 558 ((x) == 1 ? (0) : \
mbed_official 146:f64d43ff0c18 559 ((x) == 2 ? (0) : \
mbed_official 146:f64d43ff0c18 560 ((x) == 3 ? (0) : \
mbed_official 146:f64d43ff0c18 561 ((x) == 4 ? (0) : \
mbed_official 146:f64d43ff0c18 562 ((x) == 5 ? (0) : (-1)))))))
mbed_official 324:406fd2029f23 563 /* @brief Has improved smart card (ISO7816 protocol) support. */
mbed_official 146:f64d43ff0c18 564 #define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT (0)
mbed_official 324:406fd2029f23 565 #define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORTn(x) \
mbed_official 324:406fd2029f23 566 ((x) == 0 ? (0) : \
mbed_official 324:406fd2029f23 567 ((x) == 1 ? (0) : \
mbed_official 324:406fd2029f23 568 ((x) == 2 ? (0) : \
mbed_official 324:406fd2029f23 569 ((x) == 3 ? (0) : \
mbed_official 324:406fd2029f23 570 ((x) == 4 ? (0) : \
mbed_official 324:406fd2029f23 571 ((x) == 5 ? (0) : (-1)))))))
mbed_official 324:406fd2029f23 572 /* @brief Has local operation network (CEA709.1-B protocol) support. */
mbed_official 324:406fd2029f23 573 #define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0)
mbed_official 324:406fd2029f23 574 #define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORTn(x) \
mbed_official 324:406fd2029f23 575 ((x) == 0 ? (0) : \
mbed_official 324:406fd2029f23 576 ((x) == 1 ? (0) : \
mbed_official 324:406fd2029f23 577 ((x) == 2 ? (0) : \
mbed_official 324:406fd2029f23 578 ((x) == 3 ? (0) : \
mbed_official 324:406fd2029f23 579 ((x) == 4 ? (0) : \
mbed_official 324:406fd2029f23 580 ((x) == 5 ? (0) : (-1)))))))
mbed_official 324:406fd2029f23 581 /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */
mbed_official 324:406fd2029f23 582 #define FSL_FEATURE_UART_HAS_32BIT_REGISTERS (0)
mbed_official 324:406fd2029f23 583 #elif defined(CPU_MK65FN2M0CAC18) || defined(CPU_MK65FX1M0CAC18) || defined(CPU_MK65FN2M0VMI18) || defined(CPU_MK65FX1M0VMI18) || \
mbed_official 324:406fd2029f23 584 defined(CPU_MK66FN2M0VLQ18) || defined(CPU_MK66FX1M0VLQ18) || defined(CPU_MK66FN2M0VMD18) || defined(CPU_MK66FX1M0VMD18)
mbed_official 324:406fd2029f23 585 /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */
mbed_official 324:406fd2029f23 586 #define FSL_FEATURE_UART_HAS_IRQ_EXTENDED_FUNCTIONS (1)
mbed_official 324:406fd2029f23 587 /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */
mbed_official 324:406fd2029f23 588 #define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORT (0)
mbed_official 324:406fd2029f23 589 #define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORTn(x) \
mbed_official 324:406fd2029f23 590 ((x) == 0 ? (0) : \
mbed_official 324:406fd2029f23 591 ((x) == 1 ? (0) : \
mbed_official 324:406fd2029f23 592 ((x) == 2 ? (0) : \
mbed_official 324:406fd2029f23 593 ((x) == 3 ? (0) : \
mbed_official 324:406fd2029f23 594 ((x) == 4 ? (0) : (-1))))))
mbed_official 324:406fd2029f23 595 /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */
mbed_official 324:406fd2029f23 596 #define FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1)
mbed_official 324:406fd2029f23 597 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
mbed_official 324:406fd2029f23 598 #define FSL_FEATURE_UART_HAS_FIFO (1)
mbed_official 324:406fd2029f23 599 /* @brief Hardware flow control (RTS, CTS) is supported. */
mbed_official 324:406fd2029f23 600 #define FSL_FEATURE_UART_HAS_MODEM_SUPPORT (1)
mbed_official 324:406fd2029f23 601 /* @brief Infrared (modulation) is supported. */
mbed_official 324:406fd2029f23 602 #define FSL_FEATURE_UART_HAS_IR_SUPPORT (1)
mbed_official 324:406fd2029f23 603 /* @brief 2 bits long stop bit is available. */
mbed_official 324:406fd2029f23 604 #define FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT (1)
mbed_official 324:406fd2029f23 605 /* @brief Maximal data width without parity bit. */
mbed_official 324:406fd2029f23 606 #define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORT (0)
mbed_official 324:406fd2029f23 607 #define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORTn(x) \
mbed_official 324:406fd2029f23 608 ((x) == 0 ? (0) : \
mbed_official 324:406fd2029f23 609 ((x) == 1 ? (0) : \
mbed_official 324:406fd2029f23 610 ((x) == 2 ? (0) : \
mbed_official 324:406fd2029f23 611 ((x) == 3 ? (0) : \
mbed_official 324:406fd2029f23 612 ((x) == 4 ? (0) : (-1))))))
mbed_official 324:406fd2029f23 613 /* @brief Baud rate fine adjustment is available. */
mbed_official 324:406fd2029f23 614 #define FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (1)
mbed_official 324:406fd2029f23 615 /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */
mbed_official 324:406fd2029f23 616 #define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (0)
mbed_official 324:406fd2029f23 617 #define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORTn(x) \
mbed_official 324:406fd2029f23 618 ((x) == 0 ? (0) : \
mbed_official 324:406fd2029f23 619 ((x) == 1 ? (0) : \
mbed_official 324:406fd2029f23 620 ((x) == 2 ? (0) : \
mbed_official 324:406fd2029f23 621 ((x) == 3 ? (0) : \
mbed_official 324:406fd2029f23 622 ((x) == 4 ? (0) : (-1))))))
mbed_official 324:406fd2029f23 623 /* @brief Baud rate oversampling is available. */
mbed_official 324:406fd2029f23 624 #define FSL_FEATURE_UART_HAS_RX_RESYNC_SUPPORT (0)
mbed_official 324:406fd2029f23 625 /* @brief Baud rate oversampling is available. */
mbed_official 324:406fd2029f23 626 #define FSL_FEATURE_UART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (0)
mbed_official 324:406fd2029f23 627 /* @brief Peripheral type. */
mbed_official 324:406fd2029f23 628 #define FSL_FEATURE_UART_IS_SCI (0)
mbed_official 324:406fd2029f23 629 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
mbed_official 324:406fd2029f23 630 #define FSL_FEATURE_UART_FIFO_SIZE (8)
mbed_official 324:406fd2029f23 631 #define FSL_FEATURE_UART_FIFO_SIZEn(x) \
mbed_official 324:406fd2029f23 632 ((x) == 0 ? (8) : \
mbed_official 324:406fd2029f23 633 ((x) == 1 ? (8) : \
mbed_official 324:406fd2029f23 634 ((x) == 2 ? (1) : \
mbed_official 324:406fd2029f23 635 ((x) == 3 ? (1) : \
mbed_official 324:406fd2029f23 636 ((x) == 4 ? (1) : (-1))))))
mbed_official 324:406fd2029f23 637 /* @brief Maximal data width without parity bit. */
mbed_official 324:406fd2029f23 638 #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_NO_PARITY (9)
mbed_official 324:406fd2029f23 639 #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_NO_PARITYn(x) \
mbed_official 324:406fd2029f23 640 ((x) == 0 ? (9) : \
mbed_official 324:406fd2029f23 641 ((x) == 1 ? (9) : \
mbed_official 324:406fd2029f23 642 ((x) == 2 ? (9) : \
mbed_official 324:406fd2029f23 643 ((x) == 3 ? (9) : \
mbed_official 324:406fd2029f23 644 ((x) == 4 ? (9) : (-1))))))
mbed_official 324:406fd2029f23 645 /* @brief Maximal data width with parity bit. */
mbed_official 324:406fd2029f23 646 #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_PARITY (10)
mbed_official 324:406fd2029f23 647 #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_PARITYn(x) \
mbed_official 324:406fd2029f23 648 ((x) == 0 ? (10) : \
mbed_official 324:406fd2029f23 649 ((x) == 1 ? (10) : \
mbed_official 324:406fd2029f23 650 ((x) == 2 ? (10) : \
mbed_official 324:406fd2029f23 651 ((x) == 3 ? (10) : \
mbed_official 324:406fd2029f23 652 ((x) == 4 ? (10) : (-1))))))
mbed_official 324:406fd2029f23 653 /* @brief Supports two match addresses to filter incoming frames. */
mbed_official 324:406fd2029f23 654 #define FSL_FEATURE_UART_HAS_ADDRESS_MATCHING (1)
mbed_official 324:406fd2029f23 655 #define FSL_FEATURE_UART_HAS_ADDRESS_MATCHINGn(x) \
mbed_official 324:406fd2029f23 656 ((x) == 0 ? (1) : \
mbed_official 324:406fd2029f23 657 ((x) == 1 ? (1) : \
mbed_official 324:406fd2029f23 658 ((x) == 2 ? (1) : \
mbed_official 324:406fd2029f23 659 ((x) == 3 ? (1) : \
mbed_official 324:406fd2029f23 660 ((x) == 4 ? (1) : (-1))))))
mbed_official 324:406fd2029f23 661 /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */
mbed_official 324:406fd2029f23 662 #define FSL_FEATURE_UART_HAS_DMA_ENABLE (0)
mbed_official 324:406fd2029f23 663 #define FSL_FEATURE_UART_HAS_DMA_ENABLEn(x) \
mbed_official 324:406fd2029f23 664 ((x) == 0 ? (0) : \
mbed_official 324:406fd2029f23 665 ((x) == 1 ? (0) : \
mbed_official 324:406fd2029f23 666 ((x) == 2 ? (0) : \
mbed_official 324:406fd2029f23 667 ((x) == 3 ? (0) : \
mbed_official 324:406fd2029f23 668 ((x) == 4 ? (0) : (-1))))))
mbed_official 324:406fd2029f23 669 /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */
mbed_official 324:406fd2029f23 670 #define FSL_FEATURE_UART_HAS_DMA_SELECT (1)
mbed_official 324:406fd2029f23 671 #define FSL_FEATURE_UART_HAS_DMA_SELECTn(x) \
mbed_official 324:406fd2029f23 672 ((x) == 0 ? (1) : \
mbed_official 324:406fd2029f23 673 ((x) == 1 ? (1) : \
mbed_official 324:406fd2029f23 674 ((x) == 2 ? (1) : \
mbed_official 324:406fd2029f23 675 ((x) == 3 ? (1) : \
mbed_official 324:406fd2029f23 676 ((x) == 4 ? (1) : (-1))))))
mbed_official 324:406fd2029f23 677 /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */
mbed_official 324:406fd2029f23 678 #define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECT (1)
mbed_official 324:406fd2029f23 679 #define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECTn(x) \
mbed_official 324:406fd2029f23 680 ((x) == 0 ? (1) : \
mbed_official 324:406fd2029f23 681 ((x) == 1 ? (1) : \
mbed_official 324:406fd2029f23 682 ((x) == 2 ? (1) : \
mbed_official 324:406fd2029f23 683 ((x) == 3 ? (1) : \
mbed_official 324:406fd2029f23 684 ((x) == 4 ? (1) : (-1))))))
mbed_official 324:406fd2029f23 685 /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */
mbed_official 324:406fd2029f23 686 #define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORT (1)
mbed_official 324:406fd2029f23 687 #define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORTn(x) \
mbed_official 324:406fd2029f23 688 ((x) == 0 ? (1) : \
mbed_official 324:406fd2029f23 689 ((x) == 1 ? (0) : \
mbed_official 324:406fd2029f23 690 ((x) == 2 ? (0) : \
mbed_official 324:406fd2029f23 691 ((x) == 3 ? (0) : \
mbed_official 324:406fd2029f23 692 ((x) == 4 ? (0) : (-1))))))
mbed_official 324:406fd2029f23 693 /* @brief Has improved smart card (ISO7816 protocol) support. */
mbed_official 324:406fd2029f23 694 #define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT (1)
mbed_official 324:406fd2029f23 695 #define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORTn(x) \
mbed_official 324:406fd2029f23 696 ((x) == 0 ? (1) : \
mbed_official 324:406fd2029f23 697 ((x) == 1 ? (0) : \
mbed_official 324:406fd2029f23 698 ((x) == 2 ? (0) : \
mbed_official 324:406fd2029f23 699 ((x) == 3 ? (0) : \
mbed_official 324:406fd2029f23 700 ((x) == 4 ? (0) : (-1))))))
mbed_official 324:406fd2029f23 701 /* @brief Has local operation network (CEA709.1-B protocol) support. */
mbed_official 324:406fd2029f23 702 #define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0)
mbed_official 324:406fd2029f23 703 #define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORTn(x) \
mbed_official 324:406fd2029f23 704 ((x) == 0 ? (0) : \
mbed_official 324:406fd2029f23 705 ((x) == 1 ? (0) : \
mbed_official 324:406fd2029f23 706 ((x) == 2 ? (0) : \
mbed_official 324:406fd2029f23 707 ((x) == 3 ? (0) : \
mbed_official 324:406fd2029f23 708 ((x) == 4 ? (0) : (-1))))))
mbed_official 324:406fd2029f23 709 /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */
mbed_official 324:406fd2029f23 710 #define FSL_FEATURE_UART_HAS_32BIT_REGISTERS (0)
mbed_official 324:406fd2029f23 711 #elif defined(CPU_MK70FN1M0VMF12) || defined(CPU_MK70FX512VMF12) || defined(CPU_MK70FN1M0VMF15) || defined(CPU_MK70FX512VMF15) || \
mbed_official 324:406fd2029f23 712 defined(CPU_MK70FN1M0VMJ12) || defined(CPU_MK70FX512VMJ12) || defined(CPU_MK70FN1M0VMJ15) || defined(CPU_MK70FX512VMJ15)
mbed_official 324:406fd2029f23 713 /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */
mbed_official 324:406fd2029f23 714 #define FSL_FEATURE_UART_HAS_IRQ_EXTENDED_FUNCTIONS (1)
mbed_official 324:406fd2029f23 715 /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */
mbed_official 324:406fd2029f23 716 #define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORT (0)
mbed_official 324:406fd2029f23 717 #define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORTn(x) \
mbed_official 324:406fd2029f23 718 ((x) == 0 ? (0) : \
mbed_official 324:406fd2029f23 719 ((x) == 1 ? (0) : \
mbed_official 324:406fd2029f23 720 ((x) == 2 ? (0) : \
mbed_official 324:406fd2029f23 721 ((x) == 3 ? (0) : \
mbed_official 324:406fd2029f23 722 ((x) == 4 ? (0) : \
mbed_official 324:406fd2029f23 723 ((x) == 5 ? (0) : (-1)))))))
mbed_official 324:406fd2029f23 724 /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */
mbed_official 324:406fd2029f23 725 #define FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1)
mbed_official 324:406fd2029f23 726 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
mbed_official 324:406fd2029f23 727 #define FSL_FEATURE_UART_HAS_FIFO (1)
mbed_official 324:406fd2029f23 728 /* @brief Hardware flow control (RTS, CTS) is supported. */
mbed_official 324:406fd2029f23 729 #define FSL_FEATURE_UART_HAS_MODEM_SUPPORT (1)
mbed_official 324:406fd2029f23 730 /* @brief Infrared (modulation) is supported. */
mbed_official 324:406fd2029f23 731 #define FSL_FEATURE_UART_HAS_IR_SUPPORT (1)
mbed_official 324:406fd2029f23 732 /* @brief 2 bits long stop bit is available. */
mbed_official 324:406fd2029f23 733 #define FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT (0)
mbed_official 324:406fd2029f23 734 /* @brief Maximal data width without parity bit. */
mbed_official 324:406fd2029f23 735 #define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORT (0)
mbed_official 324:406fd2029f23 736 #define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORTn(x) \
mbed_official 324:406fd2029f23 737 ((x) == 0 ? (0) : \
mbed_official 324:406fd2029f23 738 ((x) == 1 ? (0) : \
mbed_official 324:406fd2029f23 739 ((x) == 2 ? (0) : \
mbed_official 324:406fd2029f23 740 ((x) == 3 ? (0) : \
mbed_official 324:406fd2029f23 741 ((x) == 4 ? (0) : \
mbed_official 324:406fd2029f23 742 ((x) == 5 ? (0) : (-1)))))))
mbed_official 324:406fd2029f23 743 /* @brief Baud rate fine adjustment is available. */
mbed_official 324:406fd2029f23 744 #define FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (1)
mbed_official 324:406fd2029f23 745 /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */
mbed_official 324:406fd2029f23 746 #define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (0)
mbed_official 324:406fd2029f23 747 #define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORTn(x) \
mbed_official 324:406fd2029f23 748 ((x) == 0 ? (0) : \
mbed_official 324:406fd2029f23 749 ((x) == 1 ? (0) : \
mbed_official 324:406fd2029f23 750 ((x) == 2 ? (0) : \
mbed_official 324:406fd2029f23 751 ((x) == 3 ? (0) : \
mbed_official 324:406fd2029f23 752 ((x) == 4 ? (0) : \
mbed_official 324:406fd2029f23 753 ((x) == 5 ? (0) : (-1)))))))
mbed_official 324:406fd2029f23 754 /* @brief Baud rate oversampling is available. */
mbed_official 324:406fd2029f23 755 #define FSL_FEATURE_UART_HAS_RX_RESYNC_SUPPORT (0)
mbed_official 324:406fd2029f23 756 /* @brief Baud rate oversampling is available. */
mbed_official 324:406fd2029f23 757 #define FSL_FEATURE_UART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (0)
mbed_official 324:406fd2029f23 758 /* @brief Peripheral type. */
mbed_official 324:406fd2029f23 759 #define FSL_FEATURE_UART_IS_SCI (0)
mbed_official 324:406fd2029f23 760 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
mbed_official 324:406fd2029f23 761 #define FSL_FEATURE_UART_FIFO_SIZE (8)
mbed_official 324:406fd2029f23 762 #define FSL_FEATURE_UART_FIFO_SIZEn(x) \
mbed_official 324:406fd2029f23 763 ((x) == 0 ? (8) : \
mbed_official 324:406fd2029f23 764 ((x) == 1 ? (8) : \
mbed_official 324:406fd2029f23 765 ((x) == 2 ? (8) : \
mbed_official 324:406fd2029f23 766 ((x) == 3 ? (8) : \
mbed_official 324:406fd2029f23 767 ((x) == 4 ? (8) : \
mbed_official 324:406fd2029f23 768 ((x) == 5 ? (8) : (-1)))))))
mbed_official 324:406fd2029f23 769 /* @brief Maximal data width without parity bit. */
mbed_official 324:406fd2029f23 770 #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_NO_PARITY (9)
mbed_official 324:406fd2029f23 771 #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_NO_PARITYn(x) \
mbed_official 324:406fd2029f23 772 ((x) == 0 ? (9) : \
mbed_official 324:406fd2029f23 773 ((x) == 1 ? (9) : \
mbed_official 324:406fd2029f23 774 ((x) == 2 ? (9) : \
mbed_official 324:406fd2029f23 775 ((x) == 3 ? (9) : \
mbed_official 324:406fd2029f23 776 ((x) == 4 ? (9) : \
mbed_official 324:406fd2029f23 777 ((x) == 5 ? (9) : (-1)))))))
mbed_official 324:406fd2029f23 778 /* @brief Maximal data width with parity bit. */
mbed_official 324:406fd2029f23 779 #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_PARITY (10)
mbed_official 324:406fd2029f23 780 #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_PARITYn(x) \
mbed_official 324:406fd2029f23 781 ((x) == 0 ? (10) : \
mbed_official 324:406fd2029f23 782 ((x) == 1 ? (10) : \
mbed_official 324:406fd2029f23 783 ((x) == 2 ? (10) : \
mbed_official 324:406fd2029f23 784 ((x) == 3 ? (10) : \
mbed_official 324:406fd2029f23 785 ((x) == 4 ? (10) : \
mbed_official 324:406fd2029f23 786 ((x) == 5 ? (10) : (-1)))))))
mbed_official 324:406fd2029f23 787 /* @brief Supports two match addresses to filter incoming frames. */
mbed_official 324:406fd2029f23 788 #define FSL_FEATURE_UART_HAS_ADDRESS_MATCHING (1)
mbed_official 324:406fd2029f23 789 #define FSL_FEATURE_UART_HAS_ADDRESS_MATCHINGn(x) \
mbed_official 324:406fd2029f23 790 ((x) == 0 ? (1) : \
mbed_official 324:406fd2029f23 791 ((x) == 1 ? (1) : \
mbed_official 324:406fd2029f23 792 ((x) == 2 ? (1) : \
mbed_official 324:406fd2029f23 793 ((x) == 3 ? (1) : \
mbed_official 324:406fd2029f23 794 ((x) == 4 ? (1) : \
mbed_official 324:406fd2029f23 795 ((x) == 5 ? (1) : (-1)))))))
mbed_official 324:406fd2029f23 796 /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */
mbed_official 324:406fd2029f23 797 #define FSL_FEATURE_UART_HAS_DMA_ENABLE (0)
mbed_official 324:406fd2029f23 798 #define FSL_FEATURE_UART_HAS_DMA_ENABLEn(x) \
mbed_official 324:406fd2029f23 799 ((x) == 0 ? (0) : \
mbed_official 324:406fd2029f23 800 ((x) == 1 ? (0) : \
mbed_official 324:406fd2029f23 801 ((x) == 2 ? (0) : \
mbed_official 324:406fd2029f23 802 ((x) == 3 ? (0) : \
mbed_official 324:406fd2029f23 803 ((x) == 4 ? (0) : \
mbed_official 324:406fd2029f23 804 ((x) == 5 ? (0) : (-1)))))))
mbed_official 324:406fd2029f23 805 /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */
mbed_official 324:406fd2029f23 806 #define FSL_FEATURE_UART_HAS_DMA_SELECT (1)
mbed_official 324:406fd2029f23 807 #define FSL_FEATURE_UART_HAS_DMA_SELECTn(x) \
mbed_official 324:406fd2029f23 808 ((x) == 0 ? (1) : \
mbed_official 324:406fd2029f23 809 ((x) == 1 ? (1) : \
mbed_official 324:406fd2029f23 810 ((x) == 2 ? (1) : \
mbed_official 324:406fd2029f23 811 ((x) == 3 ? (1) : \
mbed_official 324:406fd2029f23 812 ((x) == 4 ? (1) : \
mbed_official 324:406fd2029f23 813 ((x) == 5 ? (1) : (-1)))))))
mbed_official 324:406fd2029f23 814 /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */
mbed_official 324:406fd2029f23 815 #define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECT (1)
mbed_official 324:406fd2029f23 816 #define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECTn(x) \
mbed_official 324:406fd2029f23 817 ((x) == 0 ? (1) : \
mbed_official 324:406fd2029f23 818 ((x) == 1 ? (1) : \
mbed_official 324:406fd2029f23 819 ((x) == 2 ? (1) : \
mbed_official 324:406fd2029f23 820 ((x) == 3 ? (1) : \
mbed_official 324:406fd2029f23 821 ((x) == 4 ? (1) : \
mbed_official 324:406fd2029f23 822 ((x) == 5 ? (1) : (-1)))))))
mbed_official 324:406fd2029f23 823 /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */
mbed_official 324:406fd2029f23 824 #define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORT (1)
mbed_official 324:406fd2029f23 825 #define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORTn(x) \
mbed_official 324:406fd2029f23 826 ((x) == 0 ? (1) : \
mbed_official 324:406fd2029f23 827 ((x) == 1 ? (1) : \
mbed_official 324:406fd2029f23 828 ((x) == 2 ? (0) : \
mbed_official 324:406fd2029f23 829 ((x) == 3 ? (0) : \
mbed_official 324:406fd2029f23 830 ((x) == 4 ? (0) : \
mbed_official 324:406fd2029f23 831 ((x) == 5 ? (0) : (-1)))))))
mbed_official 324:406fd2029f23 832 /* @brief Has improved smart card (ISO7816 protocol) support. */
mbed_official 324:406fd2029f23 833 #define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT (0)
mbed_official 324:406fd2029f23 834 #define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORTn(x) \
mbed_official 324:406fd2029f23 835 ((x) == 0 ? (0) : \
mbed_official 324:406fd2029f23 836 ((x) == 1 ? (0) : \
mbed_official 324:406fd2029f23 837 ((x) == 2 ? (0) : \
mbed_official 324:406fd2029f23 838 ((x) == 3 ? (0) : \
mbed_official 324:406fd2029f23 839 ((x) == 4 ? (0) : \
mbed_official 324:406fd2029f23 840 ((x) == 5 ? (0) : (-1)))))))
mbed_official 324:406fd2029f23 841 /* @brief Has local operation network (CEA709.1-B protocol) support. */
mbed_official 324:406fd2029f23 842 #define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (1)
mbed_official 146:f64d43ff0c18 843 #define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORTn(x) \
mbed_official 146:f64d43ff0c18 844 ((x) == 0 ? (1) : \
mbed_official 146:f64d43ff0c18 845 ((x) == 1 ? (0) : \
mbed_official 146:f64d43ff0c18 846 ((x) == 2 ? (0) : \
mbed_official 146:f64d43ff0c18 847 ((x) == 3 ? (0) : \
mbed_official 146:f64d43ff0c18 848 ((x) == 4 ? (0) : \
mbed_official 146:f64d43ff0c18 849 ((x) == 5 ? (0) : (-1)))))))
mbed_official 324:406fd2029f23 850 /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */
mbed_official 324:406fd2029f23 851 #define FSL_FEATURE_UART_HAS_32BIT_REGISTERS (0)
mbed_official 324:406fd2029f23 852 #elif defined(CPU_MKL05Z8VFK4) || defined(CPU_MKL05Z16VFK4) || defined(CPU_MKL05Z32VFK4) || defined(CPU_MKL05Z8VLC4) || \
mbed_official 324:406fd2029f23 853 defined(CPU_MKL05Z16VLC4) || defined(CPU_MKL05Z32VLC4) || defined(CPU_MKL05Z8VFM4) || defined(CPU_MKL05Z16VFM4) || \
mbed_official 324:406fd2029f23 854 defined(CPU_MKL05Z32VFM4) || defined(CPU_MKL05Z16VLF4) || defined(CPU_MKL05Z32VLF4)
mbed_official 324:406fd2029f23 855 /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */
mbed_official 324:406fd2029f23 856 #define FSL_FEATURE_UART_HAS_IRQ_EXTENDED_FUNCTIONS (1)
mbed_official 324:406fd2029f23 857 /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */
mbed_official 324:406fd2029f23 858 #define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORT (1)
mbed_official 324:406fd2029f23 859 #define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORTn(x) \
mbed_official 324:406fd2029f23 860 ((x) == 0 ? (1) : (-1))
mbed_official 324:406fd2029f23 861 /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */
mbed_official 324:406fd2029f23 862 #define FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS (0)
mbed_official 324:406fd2029f23 863 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
mbed_official 324:406fd2029f23 864 #define FSL_FEATURE_UART_HAS_FIFO (0)
mbed_official 324:406fd2029f23 865 /* @brief Hardware flow control (RTS, CTS) is supported. */
mbed_official 324:406fd2029f23 866 #define FSL_FEATURE_UART_HAS_MODEM_SUPPORT (0)
mbed_official 324:406fd2029f23 867 /* @brief Infrared (modulation) is supported. */
mbed_official 324:406fd2029f23 868 #define FSL_FEATURE_UART_HAS_IR_SUPPORT (0)
mbed_official 324:406fd2029f23 869 /* @brief 2 bits long stop bit is available. */
mbed_official 324:406fd2029f23 870 #define FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT (1)
mbed_official 324:406fd2029f23 871 /* @brief Maximal data width without parity bit. */
mbed_official 324:406fd2029f23 872 #define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORT (1)
mbed_official 324:406fd2029f23 873 #define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORTn(x) \
mbed_official 324:406fd2029f23 874 ((x) == 0 ? (1) : (-1))
mbed_official 324:406fd2029f23 875 /* @brief Baud rate fine adjustment is available. */
mbed_official 324:406fd2029f23 876 #define FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0)
mbed_official 324:406fd2029f23 877 /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */
mbed_official 324:406fd2029f23 878 #define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1)
mbed_official 324:406fd2029f23 879 #define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORTn(x) \
mbed_official 324:406fd2029f23 880 ((x) == 0 ? (1) : (-1))
mbed_official 324:406fd2029f23 881 /* @brief Baud rate oversampling is available. */
mbed_official 324:406fd2029f23 882 #define FSL_FEATURE_UART_HAS_RX_RESYNC_SUPPORT (1)
mbed_official 324:406fd2029f23 883 /* @brief Baud rate oversampling is available. */
mbed_official 324:406fd2029f23 884 #define FSL_FEATURE_UART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1)
mbed_official 324:406fd2029f23 885 /* @brief Peripheral type. */
mbed_official 324:406fd2029f23 886 #define FSL_FEATURE_UART_IS_SCI (1)
mbed_official 324:406fd2029f23 887 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
mbed_official 324:406fd2029f23 888 #define FSL_FEATURE_UART_FIFO_SIZE (0)
mbed_official 324:406fd2029f23 889 #define FSL_FEATURE_UART_FIFO_SIZEn(x) \
mbed_official 324:406fd2029f23 890 ((x) == 0 ? (0) : (-1))
mbed_official 324:406fd2029f23 891 /* @brief Maximal data width without parity bit. */
mbed_official 324:406fd2029f23 892 #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_NO_PARITY (10)
mbed_official 324:406fd2029f23 893 #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_NO_PARITYn(x) \
mbed_official 324:406fd2029f23 894 ((x) == 0 ? (10) : (-1))
mbed_official 324:406fd2029f23 895 /* @brief Maximal data width with parity bit. */
mbed_official 324:406fd2029f23 896 #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_PARITY (9)
mbed_official 324:406fd2029f23 897 #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_PARITYn(x) \
mbed_official 324:406fd2029f23 898 ((x) == 0 ? (9) : (-1))
mbed_official 324:406fd2029f23 899 /* @brief Supports two match addresses to filter incoming frames. */
mbed_official 324:406fd2029f23 900 #define FSL_FEATURE_UART_HAS_ADDRESS_MATCHING (1)
mbed_official 324:406fd2029f23 901 #define FSL_FEATURE_UART_HAS_ADDRESS_MATCHINGn(x) \
mbed_official 324:406fd2029f23 902 ((x) == 0 ? (1) : (-1))
mbed_official 324:406fd2029f23 903 /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */
mbed_official 324:406fd2029f23 904 #define FSL_FEATURE_UART_HAS_DMA_ENABLE (1)
mbed_official 324:406fd2029f23 905 #define FSL_FEATURE_UART_HAS_DMA_ENABLEn(x) \
mbed_official 324:406fd2029f23 906 ((x) == 0 ? (1) : (-1))
mbed_official 324:406fd2029f23 907 /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */
mbed_official 324:406fd2029f23 908 #define FSL_FEATURE_UART_HAS_DMA_SELECT (0)
mbed_official 324:406fd2029f23 909 #define FSL_FEATURE_UART_HAS_DMA_SELECTn(x) \
mbed_official 324:406fd2029f23 910 ((x) == 0 ? (0) : (-1))
mbed_official 324:406fd2029f23 911 /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */
mbed_official 324:406fd2029f23 912 #define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECT (1)
mbed_official 324:406fd2029f23 913 #define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECTn(x) \
mbed_official 324:406fd2029f23 914 ((x) == 0 ? (1) : (-1))
mbed_official 324:406fd2029f23 915 /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */
mbed_official 324:406fd2029f23 916 #define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORT (0)
mbed_official 324:406fd2029f23 917 #define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORTn(x) \
mbed_official 324:406fd2029f23 918 ((x) == 0 ? (0) : (-1))
mbed_official 324:406fd2029f23 919 /* @brief Has improved smart card (ISO7816 protocol) support. */
mbed_official 324:406fd2029f23 920 #define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT (0)
mbed_official 324:406fd2029f23 921 #define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORTn(x) \
mbed_official 324:406fd2029f23 922 ((x) == 0 ? (0) : (-1))
mbed_official 324:406fd2029f23 923 /* @brief Has local operation network (CEA709.1-B protocol) support. */
mbed_official 324:406fd2029f23 924 #define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0)
mbed_official 324:406fd2029f23 925 #define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORTn(x) \
mbed_official 324:406fd2029f23 926 ((x) == 0 ? (0) : (-1))
mbed_official 324:406fd2029f23 927 /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */
mbed_official 324:406fd2029f23 928 #define FSL_FEATURE_UART_HAS_32BIT_REGISTERS (0)
mbed_official 324:406fd2029f23 929 #elif defined(CPU_MKL13Z64VFM4) || defined(CPU_MKL13Z128VFM4) || defined(CPU_MKL13Z256VFM4) || defined(CPU_MKL13Z64VFT4) || \
mbed_official 324:406fd2029f23 930 defined(CPU_MKL13Z128VFT4) || defined(CPU_MKL13Z256VFT4) || defined(CPU_MKL13Z64VLH4) || defined(CPU_MKL13Z128VLH4) || \
mbed_official 324:406fd2029f23 931 defined(CPU_MKL13Z256VLH4) || defined(CPU_MKL13Z64VMP4) || defined(CPU_MKL13Z128VMP4) || defined(CPU_MKL13Z256VMP4) || \
mbed_official 324:406fd2029f23 932 defined(CPU_MKL23Z64VFM4) || defined(CPU_MKL23Z128VFM4) || defined(CPU_MKL23Z256VFM4) || defined(CPU_MKL23Z64VFT4) || \
mbed_official 324:406fd2029f23 933 defined(CPU_MKL23Z128VFT4) || defined(CPU_MKL23Z256VFT4) || defined(CPU_MKL23Z64VLH4) || defined(CPU_MKL23Z128VLH4) || \
mbed_official 324:406fd2029f23 934 defined(CPU_MKL23Z256VLH4) || defined(CPU_MKL23Z64VMP4) || defined(CPU_MKL23Z128VMP4) || defined(CPU_MKL23Z256VMP4) || \
mbed_official 324:406fd2029f23 935 defined(CPU_MKL33Z128VLH4) || defined(CPU_MKL33Z256VLH4) || defined(CPU_MKL33Z128VMP4) || defined(CPU_MKL33Z256VMP4) || \
mbed_official 324:406fd2029f23 936 defined(CPU_MKL43Z64VLH4) || defined(CPU_MKL43Z128VLH4) || defined(CPU_MKL43Z256VLH4) || defined(CPU_MKL43Z64VMP4) || \
mbed_official 324:406fd2029f23 937 defined(CPU_MKL43Z128VMP4) || defined(CPU_MKL43Z256VMP4)
mbed_official 324:406fd2029f23 938 /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */
mbed_official 324:406fd2029f23 939 #define FSL_FEATURE_UART_HAS_IRQ_EXTENDED_FUNCTIONS (1)
mbed_official 324:406fd2029f23 940 /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */
mbed_official 146:f64d43ff0c18 941 #define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORT (0)
mbed_official 324:406fd2029f23 942 #define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORTn(x) \
mbed_official 324:406fd2029f23 943 ((x) == 0 ? (0) : (-1))
mbed_official 324:406fd2029f23 944 /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */
mbed_official 146:f64d43ff0c18 945 #define FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1)
mbed_official 324:406fd2029f23 946 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
mbed_official 146:f64d43ff0c18 947 #define FSL_FEATURE_UART_HAS_FIFO (1)
mbed_official 324:406fd2029f23 948 /* @brief Hardware flow control (RTS, CTS) is supported. */
mbed_official 146:f64d43ff0c18 949 #define FSL_FEATURE_UART_HAS_MODEM_SUPPORT (1)
mbed_official 324:406fd2029f23 950 /* @brief Infrared (modulation) is supported. */
mbed_official 146:f64d43ff0c18 951 #define FSL_FEATURE_UART_HAS_IR_SUPPORT (1)
mbed_official 324:406fd2029f23 952 /* @brief 2 bits long stop bit is available. */
mbed_official 146:f64d43ff0c18 953 #define FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT (0)
mbed_official 324:406fd2029f23 954 /* @brief Maximal data width without parity bit. */
mbed_official 146:f64d43ff0c18 955 #define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORT (0)
mbed_official 324:406fd2029f23 956 #define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORTn(x) \
mbed_official 324:406fd2029f23 957 ((x) == 0 ? (0) : (-1))
mbed_official 324:406fd2029f23 958 /* @brief Baud rate fine adjustment is available. */
mbed_official 146:f64d43ff0c18 959 #define FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (1)
mbed_official 324:406fd2029f23 960 /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */
mbed_official 146:f64d43ff0c18 961 #define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (0)
mbed_official 324:406fd2029f23 962 #define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORTn(x) \
mbed_official 324:406fd2029f23 963 ((x) == 0 ? (0) : (-1))
mbed_official 324:406fd2029f23 964 /* @brief Baud rate oversampling is available. */
mbed_official 146:f64d43ff0c18 965 #define FSL_FEATURE_UART_HAS_RX_RESYNC_SUPPORT (0)
mbed_official 324:406fd2029f23 966 /* @brief Baud rate oversampling is available. */
mbed_official 146:f64d43ff0c18 967 #define FSL_FEATURE_UART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (0)
mbed_official 324:406fd2029f23 968 /* @brief Peripheral type. */
mbed_official 324:406fd2029f23 969 #define FSL_FEATURE_UART_IS_SCI (0)
mbed_official 324:406fd2029f23 970 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
mbed_official 324:406fd2029f23 971 #define FSL_FEATURE_UART_FIFO_SIZE (8)
mbed_official 146:f64d43ff0c18 972 #define FSL_FEATURE_UART_FIFO_SIZEn(x) \
mbed_official 324:406fd2029f23 973 ((x) == 0 ? (8) : (-1))
mbed_official 324:406fd2029f23 974 /* @brief Maximal data width without parity bit. */
mbed_official 146:f64d43ff0c18 975 #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_NO_PARITY (9)
mbed_official 324:406fd2029f23 976 #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_NO_PARITYn(x) \
mbed_official 324:406fd2029f23 977 ((x) == 0 ? (9) : (-1))
mbed_official 324:406fd2029f23 978 /* @brief Maximal data width with parity bit. */
mbed_official 324:406fd2029f23 979 #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_PARITY (10)
mbed_official 324:406fd2029f23 980 #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_PARITYn(x) \
mbed_official 324:406fd2029f23 981 ((x) == 0 ? (10) : (-1))
mbed_official 324:406fd2029f23 982 /* @brief Supports two match addresses to filter incoming frames. */
mbed_official 146:f64d43ff0c18 983 #define FSL_FEATURE_UART_HAS_ADDRESS_MATCHING (1)
mbed_official 324:406fd2029f23 984 #define FSL_FEATURE_UART_HAS_ADDRESS_MATCHINGn(x) \
mbed_official 324:406fd2029f23 985 ((x) == 0 ? (1) : (-1))
mbed_official 324:406fd2029f23 986 /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */
mbed_official 146:f64d43ff0c18 987 #define FSL_FEATURE_UART_HAS_DMA_ENABLE (0)
mbed_official 324:406fd2029f23 988 #define FSL_FEATURE_UART_HAS_DMA_ENABLEn(x) \
mbed_official 324:406fd2029f23 989 ((x) == 0 ? (0) : (-1))
mbed_official 324:406fd2029f23 990 /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */
mbed_official 146:f64d43ff0c18 991 #define FSL_FEATURE_UART_HAS_DMA_SELECT (1)
mbed_official 324:406fd2029f23 992 #define FSL_FEATURE_UART_HAS_DMA_SELECTn(x) \
mbed_official 324:406fd2029f23 993 ((x) == 0 ? (1) : (-1))
mbed_official 324:406fd2029f23 994 /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */
mbed_official 146:f64d43ff0c18 995 #define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECT (1)
mbed_official 324:406fd2029f23 996 #define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECTn(x) \
mbed_official 324:406fd2029f23 997 ((x) == 0 ? (1) : (-1))
mbed_official 324:406fd2029f23 998 /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */
mbed_official 324:406fd2029f23 999 #define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORT (1)
mbed_official 146:f64d43ff0c18 1000 #define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORTn(x) \
mbed_official 324:406fd2029f23 1001 ((x) == 0 ? (1) : (-1))
mbed_official 324:406fd2029f23 1002 /* @brief Has improved smart card (ISO7816 protocol) support. */
mbed_official 324:406fd2029f23 1003 #define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT (1)
mbed_official 324:406fd2029f23 1004 #define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORTn(x) \
mbed_official 324:406fd2029f23 1005 ((x) == 0 ? (1) : (-1))
mbed_official 324:406fd2029f23 1006 /* @brief Has local operation network (CEA709.1-B protocol) support. */
mbed_official 324:406fd2029f23 1007 #define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0)
mbed_official 146:f64d43ff0c18 1008 #define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORTn(x) \
mbed_official 324:406fd2029f23 1009 ((x) == 0 ? (0) : (-1))
mbed_official 324:406fd2029f23 1010 /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */
mbed_official 324:406fd2029f23 1011 #define FSL_FEATURE_UART_HAS_32BIT_REGISTERS (0)
mbed_official 324:406fd2029f23 1012 #elif defined(CPU_MKL25Z32VFM4) || defined(CPU_MKL25Z64VFM4) || defined(CPU_MKL25Z128VFM4) || defined(CPU_MKL25Z32VFT4) || \
mbed_official 324:406fd2029f23 1013 defined(CPU_MKL25Z64VFT4) || defined(CPU_MKL25Z128VFT4) || defined(CPU_MKL25Z32VLH4) || defined(CPU_MKL25Z64VLH4) || \
mbed_official 324:406fd2029f23 1014 defined(CPU_MKL25Z128VLH4) || defined(CPU_MKL25Z32VLK4) || defined(CPU_MKL25Z64VLK4) || defined(CPU_MKL25Z128VLK4) || \
mbed_official 324:406fd2029f23 1015 defined(CPU_MKL26Z256VLK4) || defined(CPU_MKL26Z128VLL4) || defined(CPU_MKL26Z256VLL4) || defined(CPU_MKL26Z128VMC4) || \
mbed_official 324:406fd2029f23 1016 defined(CPU_MKL26Z256VMC4) || defined(CPU_MKL46Z128VLH4) || defined(CPU_MKL46Z256VLH4) || defined(CPU_MKL46Z128VLL4) || \
mbed_official 324:406fd2029f23 1017 defined(CPU_MKL46Z256VLL4) || defined(CPU_MKL46Z128VMC4) || defined(CPU_MKL46Z256VMC4)
mbed_official 324:406fd2029f23 1018 /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */
mbed_official 324:406fd2029f23 1019 #define FSL_FEATURE_UART_HAS_IRQ_EXTENDED_FUNCTIONS (1)
mbed_official 324:406fd2029f23 1020 /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */
mbed_official 324:406fd2029f23 1021 #define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORT (1)
mbed_official 324:406fd2029f23 1022 #define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORTn(x) \
mbed_official 146:f64d43ff0c18 1023 ((x) == 0 ? (1) : \
mbed_official 146:f64d43ff0c18 1024 ((x) == 1 ? (0) : \
mbed_official 146:f64d43ff0c18 1025 ((x) == 2 ? (0) : (-1))))
mbed_official 324:406fd2029f23 1026 /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */
mbed_official 324:406fd2029f23 1027 #define FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS (0)
mbed_official 324:406fd2029f23 1028 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
mbed_official 324:406fd2029f23 1029 #define FSL_FEATURE_UART_HAS_FIFO (0)
mbed_official 324:406fd2029f23 1030 /* @brief Hardware flow control (RTS, CTS) is supported. */
mbed_official 324:406fd2029f23 1031 #define FSL_FEATURE_UART_HAS_MODEM_SUPPORT (0)
mbed_official 324:406fd2029f23 1032 /* @brief Infrared (modulation) is supported. */
mbed_official 324:406fd2029f23 1033 #define FSL_FEATURE_UART_HAS_IR_SUPPORT (0)
mbed_official 324:406fd2029f23 1034 /* @brief 2 bits long stop bit is available. */
mbed_official 324:406fd2029f23 1035 #define FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT (1)
mbed_official 324:406fd2029f23 1036 /* @brief Maximal data width without parity bit. */
mbed_official 324:406fd2029f23 1037 #define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORT (1)
mbed_official 324:406fd2029f23 1038 #define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORTn(x) \
mbed_official 324:406fd2029f23 1039 ((x) == 0 ? (1) : \
mbed_official 324:406fd2029f23 1040 ((x) == 1 ? (0) : \
mbed_official 324:406fd2029f23 1041 ((x) == 2 ? (0) : (-1))))
mbed_official 324:406fd2029f23 1042 /* @brief Baud rate fine adjustment is available. */
mbed_official 324:406fd2029f23 1043 #define FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0)
mbed_official 324:406fd2029f23 1044 /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */
mbed_official 324:406fd2029f23 1045 #define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1)
mbed_official 324:406fd2029f23 1046 #define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORTn(x) \
mbed_official 324:406fd2029f23 1047 ((x) == 0 ? (1) : \
mbed_official 324:406fd2029f23 1048 ((x) == 1 ? (0) : \
mbed_official 324:406fd2029f23 1049 ((x) == 2 ? (0) : (-1))))
mbed_official 324:406fd2029f23 1050 /* @brief Baud rate oversampling is available. */
mbed_official 324:406fd2029f23 1051 #define FSL_FEATURE_UART_HAS_RX_RESYNC_SUPPORT (1)
mbed_official 324:406fd2029f23 1052 /* @brief Baud rate oversampling is available. */
mbed_official 324:406fd2029f23 1053 #define FSL_FEATURE_UART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1)
mbed_official 324:406fd2029f23 1054 /* @brief Peripheral type. */
mbed_official 324:406fd2029f23 1055 #define FSL_FEATURE_UART_IS_SCI (1)
mbed_official 324:406fd2029f23 1056 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
mbed_official 324:406fd2029f23 1057 #define FSL_FEATURE_UART_FIFO_SIZE (0)
mbed_official 146:f64d43ff0c18 1058 #define FSL_FEATURE_UART_FIFO_SIZEn(x) \
mbed_official 324:406fd2029f23 1059 ((x) == 0 ? (0) : \
mbed_official 324:406fd2029f23 1060 ((x) == 1 ? (0) : \
mbed_official 324:406fd2029f23 1061 ((x) == 2 ? (0) : (-1))))
mbed_official 324:406fd2029f23 1062 /* @brief Maximal data width without parity bit. */
mbed_official 324:406fd2029f23 1063 #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_NO_PARITY (10)
mbed_official 324:406fd2029f23 1064 #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_NO_PARITYn(x) \
mbed_official 324:406fd2029f23 1065 ((x) == 0 ? (10) : \
mbed_official 324:406fd2029f23 1066 ((x) == 1 ? (9) : \
mbed_official 324:406fd2029f23 1067 ((x) == 2 ? (9) : (-1))))
mbed_official 324:406fd2029f23 1068 /* @brief Maximal data width with parity bit. */
mbed_official 146:f64d43ff0c18 1069 #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_PARITY (9)
mbed_official 324:406fd2029f23 1070 #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_PARITYn(x) \
mbed_official 324:406fd2029f23 1071 ((x) == 0 ? (9) : \
mbed_official 324:406fd2029f23 1072 ((x) == 1 ? (8) : \
mbed_official 324:406fd2029f23 1073 ((x) == 2 ? (8) : (-1))))
mbed_official 324:406fd2029f23 1074 /* @brief Supports two match addresses to filter incoming frames. */
mbed_official 146:f64d43ff0c18 1075 #define FSL_FEATURE_UART_HAS_ADDRESS_MATCHING (1)
mbed_official 324:406fd2029f23 1076 #define FSL_FEATURE_UART_HAS_ADDRESS_MATCHINGn(x) \
mbed_official 324:406fd2029f23 1077 ((x) == 0 ? (1) : \
mbed_official 324:406fd2029f23 1078 ((x) == 1 ? (0) : \
mbed_official 324:406fd2029f23 1079 ((x) == 2 ? (0) : (-1))))
mbed_official 324:406fd2029f23 1080 /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */
mbed_official 324:406fd2029f23 1081 #define FSL_FEATURE_UART_HAS_DMA_ENABLE (1)
mbed_official 324:406fd2029f23 1082 #define FSL_FEATURE_UART_HAS_DMA_ENABLEn(x) \
mbed_official 146:f64d43ff0c18 1083 ((x) == 0 ? (1) : \
mbed_official 146:f64d43ff0c18 1084 ((x) == 1 ? (0) : \
mbed_official 324:406fd2029f23 1085 ((x) == 2 ? (0) : (-1))))
mbed_official 324:406fd2029f23 1086 /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */
mbed_official 324:406fd2029f23 1087 #define FSL_FEATURE_UART_HAS_DMA_SELECT (1)
mbed_official 324:406fd2029f23 1088 #define FSL_FEATURE_UART_HAS_DMA_SELECTn(x) \
mbed_official 324:406fd2029f23 1089 ((x) == 0 ? (0) : \
mbed_official 324:406fd2029f23 1090 ((x) == 1 ? (1) : \
mbed_official 324:406fd2029f23 1091 ((x) == 2 ? (1) : (-1))))
mbed_official 324:406fd2029f23 1092 /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */
mbed_official 324:406fd2029f23 1093 #define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECT (1)
mbed_official 324:406fd2029f23 1094 #define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECTn(x) \
mbed_official 324:406fd2029f23 1095 ((x) == 0 ? (1) : \
mbed_official 324:406fd2029f23 1096 ((x) == 1 ? (0) : \
mbed_official 324:406fd2029f23 1097 ((x) == 2 ? (0) : (-1))))
mbed_official 324:406fd2029f23 1098 /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */
mbed_official 324:406fd2029f23 1099 #define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORT (0)
mbed_official 324:406fd2029f23 1100 #define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORTn(x) \
mbed_official 324:406fd2029f23 1101 ((x) == 0 ? (0) : \
mbed_official 324:406fd2029f23 1102 ((x) == 1 ? (0) : \
mbed_official 324:406fd2029f23 1103 ((x) == 2 ? (0) : (-1))))
mbed_official 324:406fd2029f23 1104 /* @brief Has improved smart card (ISO7816 protocol) support. */
mbed_official 146:f64d43ff0c18 1105 #define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT (0)
mbed_official 324:406fd2029f23 1106 #define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORTn(x) \
mbed_official 324:406fd2029f23 1107 ((x) == 0 ? (0) : \
mbed_official 324:406fd2029f23 1108 ((x) == 1 ? (0) : \
mbed_official 324:406fd2029f23 1109 ((x) == 2 ? (0) : (-1))))
mbed_official 324:406fd2029f23 1110 /* @brief Has local operation network (CEA709.1-B protocol) support. */
mbed_official 146:f64d43ff0c18 1111 #define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0)
mbed_official 324:406fd2029f23 1112 #define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORTn(x) \
mbed_official 324:406fd2029f23 1113 ((x) == 0 ? (0) : \
mbed_official 324:406fd2029f23 1114 ((x) == 1 ? (0) : \
mbed_official 324:406fd2029f23 1115 ((x) == 2 ? (0) : (-1))))
mbed_official 324:406fd2029f23 1116 /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */
mbed_official 324:406fd2029f23 1117 #define FSL_FEATURE_UART_HAS_32BIT_REGISTERS (0)
mbed_official 324:406fd2029f23 1118 #elif defined(CPU_MKV40F128VLH15) || defined(CPU_MKV40F128VLL15) || defined(CPU_MKV40F256VLH15) || defined(CPU_MKV40F256VLL15) || \
mbed_official 324:406fd2029f23 1119 defined(CPU_MKV40F64VLH15) || defined(CPU_MKV43F128VLH15) || defined(CPU_MKV43F128VLL15) || defined(CPU_MKV43F64VLH15) || \
mbed_official 324:406fd2029f23 1120 defined(CPU_MKV44F128VLH15) || defined(CPU_MKV44F128VLL15) || defined(CPU_MKV44F64VLH15) || defined(CPU_MKV45F128VLH15) || \
mbed_official 324:406fd2029f23 1121 defined(CPU_MKV45F128VLL15) || defined(CPU_MKV45F256VLH15) || defined(CPU_MKV45F256VLL15) || defined(CPU_MKV46F128VLH15) || \
mbed_official 324:406fd2029f23 1122 defined(CPU_MKV46F128VLL15) || defined(CPU_MKV46F256VLH15) || defined(CPU_MKV46F256VLL15)
mbed_official 324:406fd2029f23 1123 /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */
mbed_official 146:f64d43ff0c18 1124 #define FSL_FEATURE_UART_HAS_IRQ_EXTENDED_FUNCTIONS (1)
mbed_official 324:406fd2029f23 1125 /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */
mbed_official 146:f64d43ff0c18 1126 #define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORT (0)
mbed_official 324:406fd2029f23 1127 #define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORTn(x) \
mbed_official 324:406fd2029f23 1128 ((x) == 0 ? (0) : \
mbed_official 324:406fd2029f23 1129 ((x) == 1 ? (0) : (-1)))
mbed_official 324:406fd2029f23 1130 /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */
mbed_official 146:f64d43ff0c18 1131 #define FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1)
mbed_official 324:406fd2029f23 1132 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
mbed_official 146:f64d43ff0c18 1133 #define FSL_FEATURE_UART_HAS_FIFO (1)
mbed_official 324:406fd2029f23 1134 /* @brief Hardware flow control (RTS, CTS) is supported. */
mbed_official 146:f64d43ff0c18 1135 #define FSL_FEATURE_UART_HAS_MODEM_SUPPORT (1)
mbed_official 324:406fd2029f23 1136 /* @brief Infrared (modulation) is supported. */
mbed_official 146:f64d43ff0c18 1137 #define FSL_FEATURE_UART_HAS_IR_SUPPORT (1)
mbed_official 324:406fd2029f23 1138 /* @brief 2 bits long stop bit is available. */
mbed_official 324:406fd2029f23 1139 #define FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT (1)
mbed_official 324:406fd2029f23 1140 /* @brief Maximal data width without parity bit. */
mbed_official 146:f64d43ff0c18 1141 #define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORT (0)
mbed_official 324:406fd2029f23 1142 #define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORTn(x) \
mbed_official 324:406fd2029f23 1143 ((x) == 0 ? (0) : \
mbed_official 324:406fd2029f23 1144 ((x) == 1 ? (0) : (-1)))
mbed_official 324:406fd2029f23 1145 /* @brief Baud rate fine adjustment is available. */
mbed_official 146:f64d43ff0c18 1146 #define FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (1)
mbed_official 324:406fd2029f23 1147 /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */
mbed_official 146:f64d43ff0c18 1148 #define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (0)
mbed_official 324:406fd2029f23 1149 #define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORTn(x) \
mbed_official 324:406fd2029f23 1150 ((x) == 0 ? (0) : \
mbed_official 324:406fd2029f23 1151 ((x) == 1 ? (0) : (-1)))
mbed_official 324:406fd2029f23 1152 /* @brief Baud rate oversampling is available. */
mbed_official 146:f64d43ff0c18 1153 #define FSL_FEATURE_UART_HAS_RX_RESYNC_SUPPORT (0)
mbed_official 324:406fd2029f23 1154 /* @brief Baud rate oversampling is available. */
mbed_official 146:f64d43ff0c18 1155 #define FSL_FEATURE_UART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (0)
mbed_official 324:406fd2029f23 1156 /* @brief Peripheral type. */
mbed_official 324:406fd2029f23 1157 #define FSL_FEATURE_UART_IS_SCI (0)
mbed_official 324:406fd2029f23 1158 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
mbed_official 324:406fd2029f23 1159 #define FSL_FEATURE_UART_FIFO_SIZE (8)
mbed_official 146:f64d43ff0c18 1160 #define FSL_FEATURE_UART_FIFO_SIZEn(x) \
mbed_official 146:f64d43ff0c18 1161 ((x) == 0 ? (8) : \
mbed_official 324:406fd2029f23 1162 ((x) == 1 ? (8) : (-1)))
mbed_official 324:406fd2029f23 1163 /* @brief Maximal data width without parity bit. */
mbed_official 146:f64d43ff0c18 1164 #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_NO_PARITY (9)
mbed_official 324:406fd2029f23 1165 #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_NO_PARITYn(x) \
mbed_official 324:406fd2029f23 1166 ((x) == 0 ? (9) : \
mbed_official 324:406fd2029f23 1167 ((x) == 1 ? (9) : (-1)))
mbed_official 324:406fd2029f23 1168 /* @brief Maximal data width with parity bit. */
mbed_official 324:406fd2029f23 1169 #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_PARITY (10)
mbed_official 324:406fd2029f23 1170 #define FSL_FEATURE_UART_MAX_DATA_WIDTH_WITH_PARITYn(x) \
mbed_official 324:406fd2029f23 1171 ((x) == 0 ? (10) : \
mbed_official 324:406fd2029f23 1172 ((x) == 1 ? (10) : (-1)))
mbed_official 324:406fd2029f23 1173 /* @brief Supports two match addresses to filter incoming frames. */
mbed_official 146:f64d43ff0c18 1174 #define FSL_FEATURE_UART_HAS_ADDRESS_MATCHING (1)
mbed_official 324:406fd2029f23 1175 #define FSL_FEATURE_UART_HAS_ADDRESS_MATCHINGn(x) \
mbed_official 324:406fd2029f23 1176 ((x) == 0 ? (1) : \
mbed_official 324:406fd2029f23 1177 ((x) == 1 ? (1) : (-1)))
mbed_official 324:406fd2029f23 1178 /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */
mbed_official 146:f64d43ff0c18 1179 #define FSL_FEATURE_UART_HAS_DMA_ENABLE (0)
mbed_official 324:406fd2029f23 1180 #define FSL_FEATURE_UART_HAS_DMA_ENABLEn(x) \
mbed_official 324:406fd2029f23 1181 ((x) == 0 ? (0) : \
mbed_official 324:406fd2029f23 1182 ((x) == 1 ? (0) : (-1)))
mbed_official 324:406fd2029f23 1183 /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */
mbed_official 146:f64d43ff0c18 1184 #define FSL_FEATURE_UART_HAS_DMA_SELECT (1)
mbed_official 324:406fd2029f23 1185 #define FSL_FEATURE_UART_HAS_DMA_SELECTn(x) \
mbed_official 324:406fd2029f23 1186 ((x) == 0 ? (1) : \
mbed_official 324:406fd2029f23 1187 ((x) == 1 ? (1) : (-1)))
mbed_official 324:406fd2029f23 1188 /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */
mbed_official 146:f64d43ff0c18 1189 #define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECT (1)
mbed_official 324:406fd2029f23 1190 #define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECTn(x) \
mbed_official 324:406fd2029f23 1191 ((x) == 0 ? (1) : \
mbed_official 324:406fd2029f23 1192 ((x) == 1 ? (1) : (-1)))
mbed_official 324:406fd2029f23 1193 /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */
mbed_official 324:406fd2029f23 1194 #define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORT (0)
mbed_official 146:f64d43ff0c18 1195 #define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORTn(x) \
mbed_official 324:406fd2029f23 1196 ((x) == 0 ? (0) : \
mbed_official 324:406fd2029f23 1197 ((x) == 1 ? (0) : (-1)))
mbed_official 324:406fd2029f23 1198 /* @brief Has improved smart card (ISO7816 protocol) support. */
mbed_official 146:f64d43ff0c18 1199 #define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT (0)
mbed_official 146:f64d43ff0c18 1200 #define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORTn(x) \
mbed_official 324:406fd2029f23 1201 ((x) == 0 ? (0) : \
mbed_official 324:406fd2029f23 1202 ((x) == 1 ? (0) : (-1)))
mbed_official 324:406fd2029f23 1203 /* @brief Has local operation network (CEA709.1-B protocol) support. */
mbed_official 324:406fd2029f23 1204 #define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0)
mbed_official 146:f64d43ff0c18 1205 #define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORTn(x) \
mbed_official 324:406fd2029f23 1206 ((x) == 0 ? (0) : \
mbed_official 324:406fd2029f23 1207 ((x) == 1 ? (0) : (-1)))
mbed_official 324:406fd2029f23 1208 /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */
mbed_official 324:406fd2029f23 1209 #define FSL_FEATURE_UART_HAS_32BIT_REGISTERS (0)
mbed_official 146:f64d43ff0c18 1210 #else
mbed_official 146:f64d43ff0c18 1211 #error "No valid CPU defined!"
mbed_official 146:f64d43ff0c18 1212 #endif
mbed_official 146:f64d43ff0c18 1213
mbed_official 324:406fd2029f23 1214 #endif /* __FSL_UART_FEATURES_H__ */
mbed_official 324:406fd2029f23 1215
mbed_official 146:f64d43ff0c18 1216 /*******************************************************************************
mbed_official 146:f64d43ff0c18 1217 * EOF
mbed_official 146:f64d43ff0c18 1218 ******************************************************************************/