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Last commit 20 Feb 2019 by mbed official

vendor/NXP/LPC2368/cmsis/core_arm7.h@10:3bc89ef62ce7, 2013-06-14 (annotated)

Committer:
emilmont
Date:
Fri Jun 14 17:49:17 2013 +0100
Revision:
10:3bc89ef62ce7
Unify mbed library sources

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 10:3bc89ef62ce7 1 /* mbed Microcontroller Library
emilmont 10:3bc89ef62ce7 2 * Copyright (C) 2008-2009 ARM Limited. All rights reserved.
emilmont 10:3bc89ef62ce7 3 *
emilmont 10:3bc89ef62ce7 4 * ARM7 version of CMSIS-like functionality - not advised for use outside mbed!
emilmont 10:3bc89ef62ce7 5 * based on core_cm3.h, V1.20
emilmont 10:3bc89ef62ce7 6 */
emilmont 10:3bc89ef62ce7 7
emilmont 10:3bc89ef62ce7 8 #ifndef __ARM7_CORE_H__
emilmont 10:3bc89ef62ce7 9 #define __ARM7_CORE_H__
emilmont 10:3bc89ef62ce7 10
emilmont 10:3bc89ef62ce7 11 #ifdef __cplusplus
emilmont 10:3bc89ef62ce7 12 extern "C" {
emilmont 10:3bc89ef62ce7 13 #endif
emilmont 10:3bc89ef62ce7 14
emilmont 10:3bc89ef62ce7 15 #define __CM3_CMSIS_VERSION_MAIN (0x01) /*!< [31:16] CMSIS HAL main version */
emilmont 10:3bc89ef62ce7 16 #define __CM3_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
emilmont 10:3bc89ef62ce7 17 #define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
emilmont 10:3bc89ef62ce7 18
emilmont 10:3bc89ef62ce7 19 #define __CORTEX_M (0x03) /*!< Cortex core */
emilmont 10:3bc89ef62ce7 20
emilmont 10:3bc89ef62ce7 21 /**
emilmont 10:3bc89ef62ce7 22 * Lint configuration \n
emilmont 10:3bc89ef62ce7 23 * ----------------------- \n
emilmont 10:3bc89ef62ce7 24 *
emilmont 10:3bc89ef62ce7 25 * The following Lint messages will be suppressed and not shown: \n
emilmont 10:3bc89ef62ce7 26 * \n
emilmont 10:3bc89ef62ce7 27 * --- Error 10: --- \n
emilmont 10:3bc89ef62ce7 28 * register uint32_t __regBasePri __asm("basepri"); \n
emilmont 10:3bc89ef62ce7 29 * Error 10: Expecting ';' \n
emilmont 10:3bc89ef62ce7 30 * \n
emilmont 10:3bc89ef62ce7 31 * --- Error 530: --- \n
emilmont 10:3bc89ef62ce7 32 * return(__regBasePri); \n
emilmont 10:3bc89ef62ce7 33 * Warning 530: Symbol '__regBasePri' (line 264) not initialized \n
emilmont 10:3bc89ef62ce7 34 * \n
emilmont 10:3bc89ef62ce7 35 * --- Error 550: --- \n
emilmont 10:3bc89ef62ce7 36 * __regBasePri = (basePri & 0x1ff); \n
emilmont 10:3bc89ef62ce7 37 * } \n
emilmont 10:3bc89ef62ce7 38 * Warning 550: Symbol '__regBasePri' (line 271) not accessed \n
emilmont 10:3bc89ef62ce7 39 * \n
emilmont 10:3bc89ef62ce7 40 * --- Error 754: --- \n
emilmont 10:3bc89ef62ce7 41 * uint32_t RESERVED0[24]; \n
emilmont 10:3bc89ef62ce7 42 * Info 754: local structure member '<some, not used in the HAL>' (line 109, file ./cm3_core.h) not referenced \n
emilmont 10:3bc89ef62ce7 43 * \n
emilmont 10:3bc89ef62ce7 44 * --- Error 750: --- \n
emilmont 10:3bc89ef62ce7 45 * #define __CM3_CORE_H__ \n
emilmont 10:3bc89ef62ce7 46 * Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced \n
emilmont 10:3bc89ef62ce7 47 * \n
emilmont 10:3bc89ef62ce7 48 * --- Error 528: --- \n
emilmont 10:3bc89ef62ce7 49 * static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n
emilmont 10:3bc89ef62ce7 50 * Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced \n
emilmont 10:3bc89ef62ce7 51 * \n
emilmont 10:3bc89ef62ce7 52 * --- Error 751: --- \n
emilmont 10:3bc89ef62ce7 53 * } InterruptType_Type; \n
emilmont 10:3bc89ef62ce7 54 * Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced \n
emilmont 10:3bc89ef62ce7 55 * \n
emilmont 10:3bc89ef62ce7 56 * \n
emilmont 10:3bc89ef62ce7 57 * Note: To re-enable a Message, insert a space before 'lint' * \n
emilmont 10:3bc89ef62ce7 58 *
emilmont 10:3bc89ef62ce7 59 */
emilmont 10:3bc89ef62ce7 60
emilmont 10:3bc89ef62ce7 61 /*lint -save */
emilmont 10:3bc89ef62ce7 62 /*lint -e10 */
emilmont 10:3bc89ef62ce7 63 /*lint -e530 */
emilmont 10:3bc89ef62ce7 64 /*lint -e550 */
emilmont 10:3bc89ef62ce7 65 /*lint -e754 */
emilmont 10:3bc89ef62ce7 66 /*lint -e750 */
emilmont 10:3bc89ef62ce7 67 /*lint -e528 */
emilmont 10:3bc89ef62ce7 68 /*lint -e751 */
emilmont 10:3bc89ef62ce7 69
emilmont 10:3bc89ef62ce7 70 #include <stdint.h> /* Include standard types */
emilmont 10:3bc89ef62ce7 71
emilmont 10:3bc89ef62ce7 72 #if defined ( __CC_ARM )
emilmont 10:3bc89ef62ce7 73 /**
emilmont 10:3bc89ef62ce7 74 * @brief Return the Main Stack Pointer (current ARM7 stack)
emilmont 10:3bc89ef62ce7 75 *
emilmont 10:3bc89ef62ce7 76 * @param none
emilmont 10:3bc89ef62ce7 77 * @return uint32_t Main Stack Pointer
emilmont 10:3bc89ef62ce7 78 *
emilmont 10:3bc89ef62ce7 79 * Return the current value of the MSP (main stack pointer)
emilmont 10:3bc89ef62ce7 80 * Cortex processor register
emilmont 10:3bc89ef62ce7 81 */
emilmont 10:3bc89ef62ce7 82 extern uint32_t __get_MSP(void);
emilmont 10:3bc89ef62ce7 83 #endif
emilmont 10:3bc89ef62ce7 84
emilmont 10:3bc89ef62ce7 85
emilmont 10:3bc89ef62ce7 86 #if defined (__ICCARM__)
emilmont 10:3bc89ef62ce7 87 #include <intrinsics.h> /* IAR Intrinsics */
emilmont 10:3bc89ef62ce7 88 #endif
emilmont 10:3bc89ef62ce7 89
emilmont 10:3bc89ef62ce7 90
emilmont 10:3bc89ef62ce7 91 #ifndef __NVIC_PRIO_BITS
emilmont 10:3bc89ef62ce7 92 #define __NVIC_PRIO_BITS 4 /*!< standard definition for NVIC Priority Bits */
emilmont 10:3bc89ef62ce7 93 #endif
emilmont 10:3bc89ef62ce7 94
emilmont 10:3bc89ef62ce7 95 typedef struct
emilmont 10:3bc89ef62ce7 96 {
emilmont 10:3bc89ef62ce7 97 uint32_t IRQStatus;
emilmont 10:3bc89ef62ce7 98 uint32_t FIQStatus;
emilmont 10:3bc89ef62ce7 99 uint32_t RawIntr;
emilmont 10:3bc89ef62ce7 100 uint32_t IntSelect;
emilmont 10:3bc89ef62ce7 101 uint32_t IntEnable;
emilmont 10:3bc89ef62ce7 102 uint32_t IntEnClr;
emilmont 10:3bc89ef62ce7 103 uint32_t SoftInt;
emilmont 10:3bc89ef62ce7 104 uint32_t SoftIntClr;
emilmont 10:3bc89ef62ce7 105 uint32_t Protection;
emilmont 10:3bc89ef62ce7 106 uint32_t SWPriorityMask;
emilmont 10:3bc89ef62ce7 107 uint32_t RESERVED0[54];
emilmont 10:3bc89ef62ce7 108 uint32_t VectAddr[32];
emilmont 10:3bc89ef62ce7 109 uint32_t RESERVED1[32];
emilmont 10:3bc89ef62ce7 110 uint32_t VectPriority[32];
emilmont 10:3bc89ef62ce7 111 uint32_t RESERVED2[800];
emilmont 10:3bc89ef62ce7 112 uint32_t Address;
emilmont 10:3bc89ef62ce7 113 } NVIC_TypeDef;
emilmont 10:3bc89ef62ce7 114
emilmont 10:3bc89ef62ce7 115 #define NVIC_BASE (0xFFFFF000)
emilmont 10:3bc89ef62ce7 116 #define NVIC (( NVIC_TypeDef *) NVIC_BASE)
emilmont 10:3bc89ef62ce7 117
emilmont 10:3bc89ef62ce7 118
emilmont 10:3bc89ef62ce7 119
emilmont 10:3bc89ef62ce7 120 /**
emilmont 10:3bc89ef62ce7 121 * IO definitions
emilmont 10:3bc89ef62ce7 122 *
emilmont 10:3bc89ef62ce7 123 * define access restrictions to peripheral registers
emilmont 10:3bc89ef62ce7 124 */
emilmont 10:3bc89ef62ce7 125
emilmont 10:3bc89ef62ce7 126 #ifdef __cplusplus
emilmont 10:3bc89ef62ce7 127 #define __I volatile /*!< defines 'read only' permissions */
emilmont 10:3bc89ef62ce7 128 #else
emilmont 10:3bc89ef62ce7 129 #define __I volatile const /*!< defines 'read only' permissions */
emilmont 10:3bc89ef62ce7 130 #endif
emilmont 10:3bc89ef62ce7 131 #define __O volatile /*!< defines 'write only' permissions */
emilmont 10:3bc89ef62ce7 132 #define __IO volatile /*!< defines 'read / write' permissions */
emilmont 10:3bc89ef62ce7 133
emilmont 10:3bc89ef62ce7 134
emilmont 10:3bc89ef62ce7 135
emilmont 10:3bc89ef62ce7 136
emilmont 10:3bc89ef62ce7 137
emilmont 10:3bc89ef62ce7 138 #if defined ( __CC_ARM )
emilmont 10:3bc89ef62ce7 139 #define __ASM __asm /*!< asm keyword for ARM Compiler */
emilmont 10:3bc89ef62ce7 140 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
emilmont 10:3bc89ef62ce7 141
emilmont 10:3bc89ef62ce7 142 #elif defined ( __ICCARM__ )
emilmont 10:3bc89ef62ce7 143 #define __ASM __asm /*!< asm keyword for IAR Compiler */
emilmont 10:3bc89ef62ce7 144 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
emilmont 10:3bc89ef62ce7 145
emilmont 10:3bc89ef62ce7 146 #elif defined ( __GNUC__ )
emilmont 10:3bc89ef62ce7 147 #define __ASM __asm /*!< asm keyword for GNU Compiler */
emilmont 10:3bc89ef62ce7 148 #define __INLINE inline /*!< inline keyword for GNU Compiler */
emilmont 10:3bc89ef62ce7 149
emilmont 10:3bc89ef62ce7 150 #elif defined ( __TASKING__ )
emilmont 10:3bc89ef62ce7 151 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
emilmont 10:3bc89ef62ce7 152 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
emilmont 10:3bc89ef62ce7 153
emilmont 10:3bc89ef62ce7 154 #endif
emilmont 10:3bc89ef62ce7 155
emilmont 10:3bc89ef62ce7 156
emilmont 10:3bc89ef62ce7 157 /* ################### Compiler specific Intrinsics ########################### */
emilmont 10:3bc89ef62ce7 158
emilmont 10:3bc89ef62ce7 159 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
emilmont 10:3bc89ef62ce7 160 /* ARM armcc specific functions */
emilmont 10:3bc89ef62ce7 161
emilmont 10:3bc89ef62ce7 162 #define __enable_fault_irq __enable_fiq
emilmont 10:3bc89ef62ce7 163 #define __disable_fault_irq __disable_fiq
emilmont 10:3bc89ef62ce7 164
emilmont 10:3bc89ef62ce7 165 #define __NOP __nop
emilmont 10:3bc89ef62ce7 166 //#define __WFI __wfi
emilmont 10:3bc89ef62ce7 167 //#define __WFE __wfe
emilmont 10:3bc89ef62ce7 168 //#define __SEV __sev
emilmont 10:3bc89ef62ce7 169 //#define __ISB() __isb(0)
emilmont 10:3bc89ef62ce7 170 //#define __DSB() __dsb(0)
emilmont 10:3bc89ef62ce7 171 //#define __DMB() __dmb(0)
emilmont 10:3bc89ef62ce7 172 //#define __REV __rev
emilmont 10:3bc89ef62ce7 173 //#define __RBIT __rbit
emilmont 10:3bc89ef62ce7 174 #define __LDREXB(ptr) ((unsigned char ) __ldrex(ptr))
emilmont 10:3bc89ef62ce7 175 #define __LDREXH(ptr) ((unsigned short) __ldrex(ptr))
emilmont 10:3bc89ef62ce7 176 #define __LDREXW(ptr) ((unsigned int ) __ldrex(ptr))
emilmont 10:3bc89ef62ce7 177 #define __STREXB(value, ptr) __strex(value, ptr)
emilmont 10:3bc89ef62ce7 178 #define __STREXH(value, ptr) __strex(value, ptr)
emilmont 10:3bc89ef62ce7 179 #define __STREXW(value, ptr) __strex(value, ptr)
emilmont 10:3bc89ef62ce7 180
emilmont 10:3bc89ef62ce7 181 #define __disable_irq() unsigned tmp_IntEnable = LPC_VIC->IntEnable; \
emilmont 10:3bc89ef62ce7 182 LPC_VIC->IntEnClr = 0xffffffff
emilmont 10:3bc89ef62ce7 183
emilmont 10:3bc89ef62ce7 184 #define __enable_irq() LPC_VIC->IntEnable = tmp_IntEnable
emilmont 10:3bc89ef62ce7 185
emilmont 10:3bc89ef62ce7 186 #elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
emilmont 10:3bc89ef62ce7 187
emilmont 10:3bc89ef62ce7 188 #define __enable_irq __enable_interrupt /*!< global Interrupt enable */
emilmont 10:3bc89ef62ce7 189 #define __disable_irq __disable_interrupt /*!< global Interrupt disable */
emilmont 10:3bc89ef62ce7 190 #define __NOP __no_operation() /*!< no operation intrinsic in IAR Compiler */
emilmont 10:3bc89ef62ce7 191
emilmont 10:3bc89ef62ce7 192 #elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
emilmont 10:3bc89ef62ce7 193
emilmont 10:3bc89ef62ce7 194 static __INLINE void __enable_irq() {
emilmont 10:3bc89ef62ce7 195 unsigned long temp;
emilmont 10:3bc89ef62ce7 196 __asm__ __volatile__("mrs %0, cpsr\n"
emilmont 10:3bc89ef62ce7 197 "bic %0, %0, #0x80\n"
emilmont 10:3bc89ef62ce7 198 "msr cpsr_c, %0"
emilmont 10:3bc89ef62ce7 199 : "=r" (temp)
emilmont 10:3bc89ef62ce7 200 :
emilmont 10:3bc89ef62ce7 201 : "memory");
emilmont 10:3bc89ef62ce7 202 }
emilmont 10:3bc89ef62ce7 203
emilmont 10:3bc89ef62ce7 204 static __INLINE void __disable_irq() {
emilmont 10:3bc89ef62ce7 205 unsigned long old,temp;
emilmont 10:3bc89ef62ce7 206 __asm__ __volatile__("mrs %0, cpsr\n"
emilmont 10:3bc89ef62ce7 207 "orr %1, %0, #0xc0\n"
emilmont 10:3bc89ef62ce7 208 "msr cpsr_c, %1"
emilmont 10:3bc89ef62ce7 209 : "=r" (old), "=r" (temp)
emilmont 10:3bc89ef62ce7 210 :
emilmont 10:3bc89ef62ce7 211 : "memory");
emilmont 10:3bc89ef62ce7 212 // return (old & 0x80) == 0;
emilmont 10:3bc89ef62ce7 213 }
emilmont 10:3bc89ef62ce7 214
emilmont 10:3bc89ef62ce7 215 static __INLINE void __NOP() { __ASM volatile ("nop"); }
emilmont 10:3bc89ef62ce7 216
emilmont 10:3bc89ef62ce7 217 #elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/
emilmont 10:3bc89ef62ce7 218 /* TASKING carm specific functions */
emilmont 10:3bc89ef62ce7 219
emilmont 10:3bc89ef62ce7 220 /*
emilmont 10:3bc89ef62ce7 221 * The CMSIS functions have been implemented as intrinsics in the compiler.
emilmont 10:3bc89ef62ce7 222 * Please use "carm -?i" to get an up to date list of all instrinsics,
emilmont 10:3bc89ef62ce7 223 * Including the CMSIS ones.
emilmont 10:3bc89ef62ce7 224 */
emilmont 10:3bc89ef62ce7 225
emilmont 10:3bc89ef62ce7 226 #endif
emilmont 10:3bc89ef62ce7 227
emilmont 10:3bc89ef62ce7 228
emilmont 10:3bc89ef62ce7 229 /**
emilmont 10:3bc89ef62ce7 230 * @brief Enable Interrupt in NVIC Interrupt Controller
emilmont 10:3bc89ef62ce7 231 *
emilmont 10:3bc89ef62ce7 232 * @param IRQn_Type IRQn specifies the interrupt number
emilmont 10:3bc89ef62ce7 233 * @return none
emilmont 10:3bc89ef62ce7 234 *
emilmont 10:3bc89ef62ce7 235 * Enable a device specific interupt in the NVIC interrupt controller.
emilmont 10:3bc89ef62ce7 236 * The interrupt number cannot be a negative value.
emilmont 10:3bc89ef62ce7 237 */
emilmont 10:3bc89ef62ce7 238 static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
emilmont 10:3bc89ef62ce7 239 {
emilmont 10:3bc89ef62ce7 240 NVIC->IntEnable = 1 << (uint32_t)IRQn;
emilmont 10:3bc89ef62ce7 241 }
emilmont 10:3bc89ef62ce7 242
emilmont 10:3bc89ef62ce7 243
emilmont 10:3bc89ef62ce7 244 /**
emilmont 10:3bc89ef62ce7 245 * @brief Disable the interrupt line for external interrupt specified
emilmont 10:3bc89ef62ce7 246 *
emilmont 10:3bc89ef62ce7 247 * @param IRQn_Type IRQn is the positive number of the external interrupt
emilmont 10:3bc89ef62ce7 248 * @return none
emilmont 10:3bc89ef62ce7 249 *
emilmont 10:3bc89ef62ce7 250 * Disable a device specific interupt in the NVIC interrupt controller.
emilmont 10:3bc89ef62ce7 251 * The interrupt number cannot be a negative value.
emilmont 10:3bc89ef62ce7 252 */
emilmont 10:3bc89ef62ce7 253 static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
emilmont 10:3bc89ef62ce7 254 {
emilmont 10:3bc89ef62ce7 255 NVIC->IntEnClr = 1 << (uint32_t)IRQn;
emilmont 10:3bc89ef62ce7 256 }
emilmont 10:3bc89ef62ce7 257
emilmont 10:3bc89ef62ce7 258
emilmont 10:3bc89ef62ce7 259 #ifdef __cplusplus
emilmont 10:3bc89ef62ce7 260 }
emilmont 10:3bc89ef62ce7 261 #endif
emilmont 10:3bc89ef62ce7 262
emilmont 10:3bc89ef62ce7 263 #endif /* __ARM7_CORE_H__ */
emilmont 10:3bc89ef62ce7 264
emilmont 10:3bc89ef62ce7 265 /*lint -restore */