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Last commit 20 Feb 2019 by 
mbed official
targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_ll_fmc.c@581:39197bcd20f2, 2015-07-02 (annotated)
- Committer:
- mbed_official
- Date:
- Thu Jul 02 16:30:08 2015 +0100
- Revision:
- 581:39197bcd20f2
- Parent:
- 532:fe11edbda85c
- Child:
- 613:bc40b8d2aec4
Synchronized with git revision ae2d3cdffe70184eb8736d94f76c45c93f4b7724
Full URL: https://github.com/mbedmicro/mbed/commit/ae2d3cdffe70184eb8736d94f76c45c93f4b7724/
Make it possible to build the core mbed library with yotta
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| mbed_official | 235:685d5f11838f | 1 | /** |
| mbed_official | 235:685d5f11838f | 2 | ****************************************************************************** |
| mbed_official | 235:685d5f11838f | 3 | * @file stm32f4xx_ll_fmc.c |
| mbed_official | 235:685d5f11838f | 4 | * @author MCD Application Team |
| mbed_official | 532:fe11edbda85c | 5 | * @version V1.3.0 |
| mbed_official | 532:fe11edbda85c | 6 | * @date 09-March-2015 |
| mbed_official | 235:685d5f11838f | 7 | * @brief FMC Low Layer HAL module driver. |
| mbed_official | 235:685d5f11838f | 8 | * |
| mbed_official | 235:685d5f11838f | 9 | * This file provides firmware functions to manage the following |
| mbed_official | 235:685d5f11838f | 10 | * functionalities of the Flexible Memory Controller (FMC) peripheral memories: |
| mbed_official | 235:685d5f11838f | 11 | * + Initialization/de-initialization functions |
| mbed_official | 235:685d5f11838f | 12 | * + Peripheral Control functions |
| mbed_official | 235:685d5f11838f | 13 | * + Peripheral State functions |
| mbed_official | 235:685d5f11838f | 14 | * |
| mbed_official | 235:685d5f11838f | 15 | @verbatim |
| mbed_official | 235:685d5f11838f | 16 | ============================================================================== |
| mbed_official | 235:685d5f11838f | 17 | ##### FMC peripheral features ##### |
| mbed_official | 235:685d5f11838f | 18 | ============================================================================== |
| mbed_official | 235:685d5f11838f | 19 | [..] The Flexible memory controller (FMC) includes three memory controllers: |
| mbed_official | 235:685d5f11838f | 20 | (+) The NOR/PSRAM memory controller |
| mbed_official | 235:685d5f11838f | 21 | (+) The NAND/PC Card memory controller |
| mbed_official | 235:685d5f11838f | 22 | (+) The Synchronous DRAM (SDRAM) controller |
| mbed_official | 235:685d5f11838f | 23 | |
| mbed_official | 235:685d5f11838f | 24 | [..] The FMC functional block makes the interface with synchronous and asynchronous static |
| mbed_official | 235:685d5f11838f | 25 | memories, SDRAM memories, and 16-bit PC memory cards. Its main purposes are: |
| mbed_official | 235:685d5f11838f | 26 | (+) to translate AHB transactions into the appropriate external device protocol |
| mbed_official | 235:685d5f11838f | 27 | (+) to meet the access time requirements of the external memory devices |
| mbed_official | 235:685d5f11838f | 28 | |
| mbed_official | 235:685d5f11838f | 29 | [..] All external memories share the addresses, data and control signals with the controller. |
| mbed_official | 235:685d5f11838f | 30 | Each external device is accessed by means of a unique Chip Select. The FMC performs |
| mbed_official | 235:685d5f11838f | 31 | only one access at a time to an external device. |
| mbed_official | 235:685d5f11838f | 32 | The main features of the FMC controller are the following: |
| mbed_official | 235:685d5f11838f | 33 | (+) Interface with static-memory mapped devices including: |
| mbed_official | 235:685d5f11838f | 34 | (++) Static random access memory (SRAM) |
| mbed_official | 235:685d5f11838f | 35 | (++) Read-only memory (ROM) |
| mbed_official | 235:685d5f11838f | 36 | (++) NOR Flash memory/OneNAND Flash memory |
| mbed_official | 235:685d5f11838f | 37 | (++) PSRAM (4 memory banks) |
| mbed_official | 235:685d5f11838f | 38 | (++) 16-bit PC Card compatible devices |
| mbed_official | 235:685d5f11838f | 39 | (++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of |
| mbed_official | 235:685d5f11838f | 40 | data |
| mbed_official | 235:685d5f11838f | 41 | (+) Interface with synchronous DRAM (SDRAM) memories |
| mbed_official | 235:685d5f11838f | 42 | (+) Independent Chip Select control for each memory bank |
| mbed_official | 235:685d5f11838f | 43 | (+) Independent configuration for each memory bank |
| mbed_official | 235:685d5f11838f | 44 | |
| mbed_official | 235:685d5f11838f | 45 | @endverbatim |
| mbed_official | 235:685d5f11838f | 46 | ****************************************************************************** |
| mbed_official | 235:685d5f11838f | 47 | * @attention |
| mbed_official | 235:685d5f11838f | 48 | * |
| mbed_official | 532:fe11edbda85c | 49 | * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> |
| mbed_official | 235:685d5f11838f | 50 | * |
| mbed_official | 235:685d5f11838f | 51 | * Redistribution and use in source and binary forms, with or without modification, |
| mbed_official | 235:685d5f11838f | 52 | * are permitted provided that the following conditions are met: |
| mbed_official | 235:685d5f11838f | 53 | * 1. Redistributions of source code must retain the above copyright notice, |
| mbed_official | 235:685d5f11838f | 54 | * this list of conditions and the following disclaimer. |
| mbed_official | 235:685d5f11838f | 55 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| mbed_official | 235:685d5f11838f | 56 | * this list of conditions and the following disclaimer in the documentation |
| mbed_official | 235:685d5f11838f | 57 | * and/or other materials provided with the distribution. |
| mbed_official | 235:685d5f11838f | 58 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| mbed_official | 235:685d5f11838f | 59 | * may be used to endorse or promote products derived from this software |
| mbed_official | 235:685d5f11838f | 60 | * without specific prior written permission. |
| mbed_official | 235:685d5f11838f | 61 | * |
| mbed_official | 235:685d5f11838f | 62 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| mbed_official | 235:685d5f11838f | 63 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| mbed_official | 235:685d5f11838f | 64 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| mbed_official | 235:685d5f11838f | 65 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| mbed_official | 235:685d5f11838f | 66 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| mbed_official | 235:685d5f11838f | 67 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| mbed_official | 235:685d5f11838f | 68 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| mbed_official | 235:685d5f11838f | 69 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| mbed_official | 235:685d5f11838f | 70 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| mbed_official | 235:685d5f11838f | 71 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| mbed_official | 235:685d5f11838f | 72 | * |
| mbed_official | 235:685d5f11838f | 73 | ****************************************************************************** |
| mbed_official | 235:685d5f11838f | 74 | */ |
| mbed_official | 235:685d5f11838f | 75 | |
| mbed_official | 235:685d5f11838f | 76 | /* Includes ------------------------------------------------------------------*/ |
| mbed_official | 235:685d5f11838f | 77 | #include "stm32f4xx_hal.h" |
| mbed_official | 235:685d5f11838f | 78 | |
| mbed_official | 235:685d5f11838f | 79 | /** @addtogroup STM32F4xx_HAL_Driver |
| mbed_official | 235:685d5f11838f | 80 | * @{ |
| mbed_official | 235:685d5f11838f | 81 | */ |
| mbed_official | 235:685d5f11838f | 82 | |
| mbed_official | 532:fe11edbda85c | 83 | /** @defgroup FMC_LL FMC Low Layer |
| mbed_official | 235:685d5f11838f | 84 | * @brief FMC driver modules |
| mbed_official | 235:685d5f11838f | 85 | * @{ |
| mbed_official | 235:685d5f11838f | 86 | */ |
| mbed_official | 235:685d5f11838f | 87 | |
| mbed_official | 235:685d5f11838f | 88 | #if defined (HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) || defined(HAL_PCCARD_MODULE_ENABLED) || defined(HAL_SDRAM_MODULE_ENABLED) |
| mbed_official | 235:685d5f11838f | 89 | |
| mbed_official | 532:fe11edbda85c | 90 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) |
| mbed_official | 235:685d5f11838f | 91 | |
| mbed_official | 235:685d5f11838f | 92 | /* Private typedef -----------------------------------------------------------*/ |
| mbed_official | 235:685d5f11838f | 93 | /* Private define ------------------------------------------------------------*/ |
| mbed_official | 235:685d5f11838f | 94 | /* Private macro -------------------------------------------------------------*/ |
| mbed_official | 235:685d5f11838f | 95 | /* Private variables ---------------------------------------------------------*/ |
| mbed_official | 235:685d5f11838f | 96 | /* Private function prototypes -----------------------------------------------*/ |
| mbed_official | 235:685d5f11838f | 97 | /* Private functions ---------------------------------------------------------*/ |
| mbed_official | 532:fe11edbda85c | 98 | /** @addtogroup FMC_LL_Private_Functions |
| mbed_official | 235:685d5f11838f | 99 | * @{ |
| mbed_official | 235:685d5f11838f | 100 | */ |
| mbed_official | 235:685d5f11838f | 101 | |
| mbed_official | 532:fe11edbda85c | 102 | /** @addtogroup FMC_LL_NORSRAM |
| mbed_official | 532:fe11edbda85c | 103 | * @brief NORSRAM Controller functions |
| mbed_official | 235:685d5f11838f | 104 | * |
| mbed_official | 235:685d5f11838f | 105 | @verbatim |
| mbed_official | 235:685d5f11838f | 106 | ============================================================================== |
| mbed_official | 235:685d5f11838f | 107 | ##### How to use NORSRAM device driver ##### |
| mbed_official | 235:685d5f11838f | 108 | ============================================================================== |
| mbed_official | 235:685d5f11838f | 109 | |
| mbed_official | 235:685d5f11838f | 110 | [..] |
| mbed_official | 235:685d5f11838f | 111 | This driver contains a set of APIs to interface with the FMC NORSRAM banks in order |
| mbed_official | 235:685d5f11838f | 112 | to run the NORSRAM external devices. |
| mbed_official | 235:685d5f11838f | 113 | |
| mbed_official | 235:685d5f11838f | 114 | (+) FMC NORSRAM bank reset using the function FMC_NORSRAM_DeInit() |
| mbed_official | 235:685d5f11838f | 115 | (+) FMC NORSRAM bank control configuration using the function FMC_NORSRAM_Init() |
| mbed_official | 235:685d5f11838f | 116 | (+) FMC NORSRAM bank timing configuration using the function FMC_NORSRAM_Timing_Init() |
| mbed_official | 235:685d5f11838f | 117 | (+) FMC NORSRAM bank extended timing configuration using the function |
| mbed_official | 235:685d5f11838f | 118 | FMC_NORSRAM_Extended_Timing_Init() |
| mbed_official | 235:685d5f11838f | 119 | (+) FMC NORSRAM bank enable/disable write operation using the functions |
| mbed_official | 235:685d5f11838f | 120 | FMC_NORSRAM_WriteOperation_Enable()/FMC_NORSRAM_WriteOperation_Disable() |
| mbed_official | 235:685d5f11838f | 121 | |
| mbed_official | 235:685d5f11838f | 122 | |
| mbed_official | 235:685d5f11838f | 123 | @endverbatim |
| mbed_official | 235:685d5f11838f | 124 | * @{ |
| mbed_official | 235:685d5f11838f | 125 | */ |
| mbed_official | 235:685d5f11838f | 126 | |
| mbed_official | 532:fe11edbda85c | 127 | /** @addtogroup FMC_LL_NORSRAM_Private_Functions_Group1 |
| mbed_official | 235:685d5f11838f | 128 | * @brief Initialization and Configuration functions |
| mbed_official | 235:685d5f11838f | 129 | * |
| mbed_official | 235:685d5f11838f | 130 | @verbatim |
| mbed_official | 235:685d5f11838f | 131 | ============================================================================== |
| mbed_official | 235:685d5f11838f | 132 | ##### Initialization and de_initialization functions ##### |
| mbed_official | 235:685d5f11838f | 133 | ============================================================================== |
| mbed_official | 235:685d5f11838f | 134 | [..] |
| mbed_official | 235:685d5f11838f | 135 | This section provides functions allowing to: |
| mbed_official | 235:685d5f11838f | 136 | (+) Initialize and configure the FMC NORSRAM interface |
| mbed_official | 235:685d5f11838f | 137 | (+) De-initialize the FMC NORSRAM interface |
| mbed_official | 235:685d5f11838f | 138 | (+) Configure the FMC clock and associated GPIOs |
| mbed_official | 235:685d5f11838f | 139 | |
| mbed_official | 235:685d5f11838f | 140 | @endverbatim |
| mbed_official | 235:685d5f11838f | 141 | * @{ |
| mbed_official | 235:685d5f11838f | 142 | */ |
| mbed_official | 235:685d5f11838f | 143 | |
| mbed_official | 235:685d5f11838f | 144 | /** |
| mbed_official | 235:685d5f11838f | 145 | * @brief Initialize the FMC_NORSRAM device according to the specified |
| mbed_official | 235:685d5f11838f | 146 | * control parameters in the FMC_NORSRAM_InitTypeDef |
| mbed_official | 235:685d5f11838f | 147 | * @param Device: Pointer to NORSRAM device instance |
| mbed_official | 235:685d5f11838f | 148 | * @param Init: Pointer to NORSRAM Initialization structure |
| mbed_official | 235:685d5f11838f | 149 | * @retval HAL status |
| mbed_official | 235:685d5f11838f | 150 | */ |
| mbed_official | 235:685d5f11838f | 151 | HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef* Init) |
| mbed_official | 235:685d5f11838f | 152 | { |
| mbed_official | 235:685d5f11838f | 153 | uint32_t tmpr = 0; |
| mbed_official | 235:685d5f11838f | 154 | |
| mbed_official | 235:685d5f11838f | 155 | /* Check the parameters */ |
| mbed_official | 235:685d5f11838f | 156 | assert_param(IS_FMC_NORSRAM_DEVICE(Device)); |
| mbed_official | 235:685d5f11838f | 157 | assert_param(IS_FMC_NORSRAM_BANK(Init->NSBank)); |
| mbed_official | 235:685d5f11838f | 158 | assert_param(IS_FMC_MUX(Init->DataAddressMux)); |
| mbed_official | 235:685d5f11838f | 159 | assert_param(IS_FMC_MEMORY(Init->MemoryType)); |
| mbed_official | 235:685d5f11838f | 160 | assert_param(IS_FMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth)); |
| mbed_official | 235:685d5f11838f | 161 | assert_param(IS_FMC_BURSTMODE(Init->BurstAccessMode)); |
| mbed_official | 235:685d5f11838f | 162 | assert_param(IS_FMC_WAIT_POLARITY(Init->WaitSignalPolarity)); |
| mbed_official | 532:fe11edbda85c | 163 | #if !defined (STM32F446xx) |
| mbed_official | 235:685d5f11838f | 164 | assert_param(IS_FMC_WRAP_MODE(Init->WrapMode)); |
| mbed_official | 532:fe11edbda85c | 165 | #endif /* !defined (STM32F446xx) */ |
| mbed_official | 235:685d5f11838f | 166 | assert_param(IS_FMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive)); |
| mbed_official | 235:685d5f11838f | 167 | assert_param(IS_FMC_WRITE_OPERATION(Init->WriteOperation)); |
| mbed_official | 235:685d5f11838f | 168 | assert_param(IS_FMC_WAITE_SIGNAL(Init->WaitSignal)); |
| mbed_official | 235:685d5f11838f | 169 | assert_param(IS_FMC_EXTENDED_MODE(Init->ExtendedMode)); |
| mbed_official | 235:685d5f11838f | 170 | assert_param(IS_FMC_ASYNWAIT(Init->AsynchronousWait)); |
| mbed_official | 235:685d5f11838f | 171 | assert_param(IS_FMC_WRITE_BURST(Init->WriteBurst)); |
| mbed_official | 532:fe11edbda85c | 172 | assert_param(IS_FMC_CONTINOUS_CLOCK(Init->ContinuousClock)); |
| mbed_official | 532:fe11edbda85c | 173 | #if defined (STM32F446xx) |
| mbed_official | 532:fe11edbda85c | 174 | assert_param(IS_FMC_WRITE_FIFO(Init->WriteFifo)); |
| mbed_official | 532:fe11edbda85c | 175 | assert_param(IS_FMC_PAGESIZE(Init->PageSize)); |
| mbed_official | 532:fe11edbda85c | 176 | #endif /* defined (STM32F446xx) */ |
| mbed_official | 532:fe11edbda85c | 177 | |
| mbed_official | 532:fe11edbda85c | 178 | /* Get the BTCR register value */ |
| mbed_official | 532:fe11edbda85c | 179 | tmpr = Device->BTCR[Init->NSBank]; |
| mbed_official | 532:fe11edbda85c | 180 | |
| mbed_official | 532:fe11edbda85c | 181 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) |
| mbed_official | 532:fe11edbda85c | 182 | /* Clear MBKEN, MUXEN, MTYP, MWID, FACCEN, BURSTEN, WAITPOL, WRAPMOD, WAITCFG, WREN, |
| mbed_official | 532:fe11edbda85c | 183 | WAITEN, EXTMOD, ASYNCWAIT, CBURSTRW and CCLKEN bits */ |
| mbed_official | 532:fe11edbda85c | 184 | tmpr &= ((uint32_t)~(FMC_BCR1_MBKEN | FMC_BCR1_MUXEN | FMC_BCR1_MTYP | \ |
| mbed_official | 532:fe11edbda85c | 185 | FMC_BCR1_MWID | FMC_BCR1_FACCEN | FMC_BCR1_BURSTEN | \ |
| mbed_official | 532:fe11edbda85c | 186 | FMC_BCR1_WAITPOL | FMC_BCR1_WRAPMOD | FMC_BCR1_WAITCFG | \ |
| mbed_official | 532:fe11edbda85c | 187 | FMC_BCR1_WREN | FMC_BCR1_WAITEN | FMC_BCR1_EXTMOD | \ |
| mbed_official | 532:fe11edbda85c | 188 | FMC_BCR1_ASYNCWAIT | FMC_BCR1_CBURSTRW | FMC_BCR1_CCLKEN)); |
| mbed_official | 235:685d5f11838f | 189 | |
| mbed_official | 235:685d5f11838f | 190 | /* Set NORSRAM device control parameters */ |
| mbed_official | 532:fe11edbda85c | 191 | tmpr |= (uint32_t)(Init->DataAddressMux |\ |
| mbed_official | 235:685d5f11838f | 192 | Init->MemoryType |\ |
| mbed_official | 235:685d5f11838f | 193 | Init->MemoryDataWidth |\ |
| mbed_official | 235:685d5f11838f | 194 | Init->BurstAccessMode |\ |
| mbed_official | 235:685d5f11838f | 195 | Init->WaitSignalPolarity |\ |
| mbed_official | 235:685d5f11838f | 196 | Init->WrapMode |\ |
| mbed_official | 235:685d5f11838f | 197 | Init->WaitSignalActive |\ |
| mbed_official | 235:685d5f11838f | 198 | Init->WriteOperation |\ |
| mbed_official | 235:685d5f11838f | 199 | Init->WaitSignal |\ |
| mbed_official | 235:685d5f11838f | 200 | Init->ExtendedMode |\ |
| mbed_official | 235:685d5f11838f | 201 | Init->AsynchronousWait |\ |
| mbed_official | 235:685d5f11838f | 202 | Init->WriteBurst |\ |
| mbed_official | 532:fe11edbda85c | 203 | Init->ContinuousClock); |
| mbed_official | 532:fe11edbda85c | 204 | #else /* defined(STM32F446xx) */ |
| mbed_official | 532:fe11edbda85c | 205 | /* Clear MBKEN, MUXEN, MTYP, MWID, FACCEN, BURSTEN, WAITPOL, CPSIZE, WAITCFG, WREN, |
| mbed_official | 532:fe11edbda85c | 206 | WAITEN, EXTMOD, ASYNCWAIT, CBURSTRW, CCLKEN and WFDIS bits */ |
| mbed_official | 532:fe11edbda85c | 207 | tmpr &= ((uint32_t)~(FMC_BCR1_MBKEN | FMC_BCR1_MUXEN | FMC_BCR1_MTYP | \ |
| mbed_official | 532:fe11edbda85c | 208 | FMC_BCR1_MWID | FMC_BCR1_FACCEN | FMC_BCR1_BURSTEN | \ |
| mbed_official | 532:fe11edbda85c | 209 | FMC_BCR1_WAITPOL | FMC_BCR1_WAITCFG | FMC_BCR1_CPSIZE | \ |
| mbed_official | 532:fe11edbda85c | 210 | FMC_BCR1_WREN | FMC_BCR1_WAITEN | FMC_BCR1_EXTMOD | \ |
| mbed_official | 532:fe11edbda85c | 211 | FMC_BCR1_ASYNCWAIT | FMC_BCR1_CBURSTRW | FMC_BCR1_CCLKEN | \ |
| mbed_official | 532:fe11edbda85c | 212 | FMC_BCR1_WFDIS)); |
| mbed_official | 532:fe11edbda85c | 213 | |
| mbed_official | 532:fe11edbda85c | 214 | /* Set NORSRAM device control parameters */ |
| mbed_official | 532:fe11edbda85c | 215 | tmpr |= (uint32_t)(Init->DataAddressMux |\ |
| mbed_official | 532:fe11edbda85c | 216 | Init->MemoryType |\ |
| mbed_official | 532:fe11edbda85c | 217 | Init->MemoryDataWidth |\ |
| mbed_official | 532:fe11edbda85c | 218 | Init->BurstAccessMode |\ |
| mbed_official | 532:fe11edbda85c | 219 | Init->WaitSignalPolarity |\ |
| mbed_official | 532:fe11edbda85c | 220 | Init->WaitSignalActive |\ |
| mbed_official | 532:fe11edbda85c | 221 | Init->WriteOperation |\ |
| mbed_official | 532:fe11edbda85c | 222 | Init->WaitSignal |\ |
| mbed_official | 532:fe11edbda85c | 223 | Init->ExtendedMode |\ |
| mbed_official | 532:fe11edbda85c | 224 | Init->AsynchronousWait |\ |
| mbed_official | 532:fe11edbda85c | 225 | Init->WriteBurst |\ |
| mbed_official | 532:fe11edbda85c | 226 | Init->ContinuousClock |\ |
| mbed_official | 532:fe11edbda85c | 227 | Init->PageSize |\ |
| mbed_official | 532:fe11edbda85c | 228 | Init->WriteFifo); |
| mbed_official | 532:fe11edbda85c | 229 | #endif /* defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) */ |
| mbed_official | 235:685d5f11838f | 230 | |
| mbed_official | 235:685d5f11838f | 231 | if(Init->MemoryType == FMC_MEMORY_TYPE_NOR) |
| mbed_official | 235:685d5f11838f | 232 | { |
| mbed_official | 235:685d5f11838f | 233 | tmpr |= (uint32_t)FMC_NORSRAM_FLASH_ACCESS_ENABLE; |
| mbed_official | 235:685d5f11838f | 234 | } |
| mbed_official | 235:685d5f11838f | 235 | |
| mbed_official | 235:685d5f11838f | 236 | Device->BTCR[Init->NSBank] = tmpr; |
| mbed_official | 235:685d5f11838f | 237 | |
| mbed_official | 235:685d5f11838f | 238 | /* Configure synchronous mode when Continuous clock is enabled for bank2..4 */ |
| mbed_official | 235:685d5f11838f | 239 | if((Init->ContinuousClock == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FMC_NORSRAM_BANK1)) |
| mbed_official | 235:685d5f11838f | 240 | { |
| mbed_official | 235:685d5f11838f | 241 | Init->BurstAccessMode = FMC_BURST_ACCESS_MODE_ENABLE; |
| mbed_official | 235:685d5f11838f | 242 | Device->BTCR[FMC_NORSRAM_BANK1] |= (uint32_t)(Init->BurstAccessMode |\ |
| mbed_official | 532:fe11edbda85c | 243 | Init->ContinuousClock); |
| mbed_official | 532:fe11edbda85c | 244 | } |
| mbed_official | 532:fe11edbda85c | 245 | |
| mbed_official | 532:fe11edbda85c | 246 | #if defined(STM32F446xx) |
| mbed_official | 532:fe11edbda85c | 247 | if(Init->NSBank != FMC_NORSRAM_BANK1) |
| mbed_official | 532:fe11edbda85c | 248 | { |
| mbed_official | 532:fe11edbda85c | 249 | Device->BTCR[FMC_NORSRAM_BANK1] |= (uint32_t)(Init->WriteFifo); |
| mbed_official | 532:fe11edbda85c | 250 | } |
| mbed_official | 532:fe11edbda85c | 251 | #endif /* defined(STM32F446xx) */ |
| mbed_official | 235:685d5f11838f | 252 | |
| mbed_official | 235:685d5f11838f | 253 | return HAL_OK; |
| mbed_official | 235:685d5f11838f | 254 | } |
| mbed_official | 235:685d5f11838f | 255 | |
| mbed_official | 235:685d5f11838f | 256 | /** |
| mbed_official | 235:685d5f11838f | 257 | * @brief DeInitialize the FMC_NORSRAM peripheral |
| mbed_official | 235:685d5f11838f | 258 | * @param Device: Pointer to NORSRAM device instance |
| mbed_official | 235:685d5f11838f | 259 | * @param ExDevice: Pointer to NORSRAM extended mode device instance |
| mbed_official | 235:685d5f11838f | 260 | * @param Bank: NORSRAM bank number |
| mbed_official | 235:685d5f11838f | 261 | * @retval HAL status |
| mbed_official | 235:685d5f11838f | 262 | */ |
| mbed_official | 235:685d5f11838f | 263 | HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank) |
| mbed_official | 235:685d5f11838f | 264 | { |
| mbed_official | 235:685d5f11838f | 265 | /* Check the parameters */ |
| mbed_official | 235:685d5f11838f | 266 | assert_param(IS_FMC_NORSRAM_DEVICE(Device)); |
| mbed_official | 235:685d5f11838f | 267 | assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(ExDevice)); |
| mbed_official | 235:685d5f11838f | 268 | assert_param(IS_FMC_NORSRAM_BANK(Bank)); |
| mbed_official | 235:685d5f11838f | 269 | |
| mbed_official | 235:685d5f11838f | 270 | /* Disable the FMC_NORSRAM device */ |
| mbed_official | 235:685d5f11838f | 271 | __FMC_NORSRAM_DISABLE(Device, Bank); |
| mbed_official | 235:685d5f11838f | 272 | |
| mbed_official | 235:685d5f11838f | 273 | /* De-initialize the FMC_NORSRAM device */ |
| mbed_official | 235:685d5f11838f | 274 | /* FMC_NORSRAM_BANK1 */ |
| mbed_official | 235:685d5f11838f | 275 | if(Bank == FMC_NORSRAM_BANK1) |
| mbed_official | 235:685d5f11838f | 276 | { |
| mbed_official | 532:fe11edbda85c | 277 | Device->BTCR[Bank] = 0x000030DB; |
| mbed_official | 235:685d5f11838f | 278 | } |
| mbed_official | 235:685d5f11838f | 279 | /* FMC_NORSRAM_BANK2, FMC_NORSRAM_BANK3 or FMC_NORSRAM_BANK4 */ |
| mbed_official | 235:685d5f11838f | 280 | else |
| mbed_official | 235:685d5f11838f | 281 | { |
| mbed_official | 532:fe11edbda85c | 282 | Device->BTCR[Bank] = 0x000030D2; |
| mbed_official | 235:685d5f11838f | 283 | } |
| mbed_official | 235:685d5f11838f | 284 | |
| mbed_official | 235:685d5f11838f | 285 | Device->BTCR[Bank + 1] = 0x0FFFFFFF; |
| mbed_official | 235:685d5f11838f | 286 | ExDevice->BWTR[Bank] = 0x0FFFFFFF; |
| mbed_official | 235:685d5f11838f | 287 | |
| mbed_official | 235:685d5f11838f | 288 | return HAL_OK; |
| mbed_official | 235:685d5f11838f | 289 | } |
| mbed_official | 235:685d5f11838f | 290 | |
| mbed_official | 235:685d5f11838f | 291 | /** |
| mbed_official | 235:685d5f11838f | 292 | * @brief Initialize the FMC_NORSRAM Timing according to the specified |
| mbed_official | 235:685d5f11838f | 293 | * parameters in the FMC_NORSRAM_TimingTypeDef |
| mbed_official | 235:685d5f11838f | 294 | * @param Device: Pointer to NORSRAM device instance |
| mbed_official | 235:685d5f11838f | 295 | * @param Timing: Pointer to NORSRAM Timing structure |
| mbed_official | 235:685d5f11838f | 296 | * @param Bank: NORSRAM bank number |
| mbed_official | 235:685d5f11838f | 297 | * @retval HAL status |
| mbed_official | 235:685d5f11838f | 298 | */ |
| mbed_official | 235:685d5f11838f | 299 | HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank) |
| mbed_official | 235:685d5f11838f | 300 | { |
| mbed_official | 235:685d5f11838f | 301 | uint32_t tmpr = 0; |
| mbed_official | 235:685d5f11838f | 302 | |
| mbed_official | 235:685d5f11838f | 303 | /* Check the parameters */ |
| mbed_official | 235:685d5f11838f | 304 | assert_param(IS_FMC_NORSRAM_DEVICE(Device)); |
| mbed_official | 235:685d5f11838f | 305 | assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); |
| mbed_official | 235:685d5f11838f | 306 | assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime)); |
| mbed_official | 235:685d5f11838f | 307 | assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime)); |
| mbed_official | 235:685d5f11838f | 308 | assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration)); |
| mbed_official | 235:685d5f11838f | 309 | assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision)); |
| mbed_official | 235:685d5f11838f | 310 | assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency)); |
| mbed_official | 235:685d5f11838f | 311 | assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode)); |
| mbed_official | 235:685d5f11838f | 312 | assert_param(IS_FMC_NORSRAM_BANK(Bank)); |
| mbed_official | 235:685d5f11838f | 313 | |
| mbed_official | 532:fe11edbda85c | 314 | /* Get the BTCR register value */ |
| mbed_official | 532:fe11edbda85c | 315 | tmpr = Device->BTCR[Bank + 1]; |
| mbed_official | 532:fe11edbda85c | 316 | |
| mbed_official | 532:fe11edbda85c | 317 | /* Clear ADDSET, ADDHLD, DATAST, BUSTURN, CLKDIV, DATLAT and ACCMOD bits */ |
| mbed_official | 532:fe11edbda85c | 318 | tmpr &= ((uint32_t)~(FMC_BTR1_ADDSET | FMC_BTR1_ADDHLD | FMC_BTR1_DATAST | \ |
| mbed_official | 532:fe11edbda85c | 319 | FMC_BTR1_BUSTURN | FMC_BTR1_CLKDIV | FMC_BTR1_DATLAT | \ |
| mbed_official | 532:fe11edbda85c | 320 | FMC_BTR1_ACCMOD)); |
| mbed_official | 532:fe11edbda85c | 321 | |
| mbed_official | 235:685d5f11838f | 322 | /* Set FMC_NORSRAM device timing parameters */ |
| mbed_official | 532:fe11edbda85c | 323 | tmpr |= (uint32_t)(Timing->AddressSetupTime |\ |
| mbed_official | 532:fe11edbda85c | 324 | ((Timing->AddressHoldTime) << 4) |\ |
| mbed_official | 532:fe11edbda85c | 325 | ((Timing->DataSetupTime) << 8) |\ |
| mbed_official | 532:fe11edbda85c | 326 | ((Timing->BusTurnAroundDuration) << 16) |\ |
| mbed_official | 532:fe11edbda85c | 327 | (((Timing->CLKDivision)-1) << 20) |\ |
| mbed_official | 532:fe11edbda85c | 328 | (((Timing->DataLatency)-2) << 24) |\ |
| mbed_official | 532:fe11edbda85c | 329 | (Timing->AccessMode)); |
| mbed_official | 235:685d5f11838f | 330 | |
| mbed_official | 235:685d5f11838f | 331 | Device->BTCR[Bank + 1] = tmpr; |
| mbed_official | 235:685d5f11838f | 332 | |
| mbed_official | 235:685d5f11838f | 333 | /* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */ |
| mbed_official | 235:685d5f11838f | 334 | if(HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN)) |
| mbed_official | 235:685d5f11838f | 335 | { |
| mbed_official | 235:685d5f11838f | 336 | tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1] & ~(((uint32_t)0x0F) << 20)); |
| mbed_official | 235:685d5f11838f | 337 | tmpr |= (uint32_t)(((Timing->CLKDivision)-1) << 20); |
| mbed_official | 235:685d5f11838f | 338 | Device->BTCR[FMC_NORSRAM_BANK1 + 1] = tmpr; |
| mbed_official | 235:685d5f11838f | 339 | } |
| mbed_official | 235:685d5f11838f | 340 | |
| mbed_official | 235:685d5f11838f | 341 | return HAL_OK; |
| mbed_official | 235:685d5f11838f | 342 | } |
| mbed_official | 235:685d5f11838f | 343 | |
| mbed_official | 235:685d5f11838f | 344 | /** |
| mbed_official | 235:685d5f11838f | 345 | * @brief Initialize the FMC_NORSRAM Extended mode Timing according to the specified |
| mbed_official | 235:685d5f11838f | 346 | * parameters in the FMC_NORSRAM_TimingTypeDef |
| mbed_official | 235:685d5f11838f | 347 | * @param Device: Pointer to NORSRAM device instance |
| mbed_official | 235:685d5f11838f | 348 | * @param Timing: Pointer to NORSRAM Timing structure |
| mbed_official | 235:685d5f11838f | 349 | * @param Bank: NORSRAM bank number |
| mbed_official | 235:685d5f11838f | 350 | * @retval HAL status |
| mbed_official | 235:685d5f11838f | 351 | */ |
| mbed_official | 235:685d5f11838f | 352 | HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode) |
| mbed_official | 235:685d5f11838f | 353 | { |
| mbed_official | 532:fe11edbda85c | 354 | uint32_t tmpr = 0; |
| mbed_official | 532:fe11edbda85c | 355 | |
| mbed_official | 235:685d5f11838f | 356 | /* Check the parameters */ |
| mbed_official | 235:685d5f11838f | 357 | assert_param(IS_FMC_EXTENDED_MODE(ExtendedMode)); |
| mbed_official | 235:685d5f11838f | 358 | |
| mbed_official | 235:685d5f11838f | 359 | /* Set NORSRAM device timing register for write configuration, if extended mode is used */ |
| mbed_official | 235:685d5f11838f | 360 | if(ExtendedMode == FMC_EXTENDED_MODE_ENABLE) |
| mbed_official | 235:685d5f11838f | 361 | { |
| mbed_official | 532:fe11edbda85c | 362 | /* Check the parameters */ |
| mbed_official | 235:685d5f11838f | 363 | assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(Device)); |
| mbed_official | 235:685d5f11838f | 364 | assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); |
| mbed_official | 235:685d5f11838f | 365 | assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime)); |
| mbed_official | 235:685d5f11838f | 366 | assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime)); |
| mbed_official | 235:685d5f11838f | 367 | assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration)); |
| mbed_official | 532:fe11edbda85c | 368 | #if !defined(STM32F446xx) |
| mbed_official | 235:685d5f11838f | 369 | assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision)); |
| mbed_official | 235:685d5f11838f | 370 | assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency)); |
| mbed_official | 532:fe11edbda85c | 371 | #endif /* !defined(STM32F446xx) */ |
| mbed_official | 235:685d5f11838f | 372 | assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode)); |
| mbed_official | 235:685d5f11838f | 373 | assert_param(IS_FMC_NORSRAM_BANK(Bank)); |
| mbed_official | 235:685d5f11838f | 374 | |
| mbed_official | 532:fe11edbda85c | 375 | /* Get the BWTR register value */ |
| mbed_official | 532:fe11edbda85c | 376 | tmpr = Device->BWTR[Bank]; |
| mbed_official | 532:fe11edbda85c | 377 | |
| mbed_official | 532:fe11edbda85c | 378 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) |
| mbed_official | 532:fe11edbda85c | 379 | /* Clear ADDSET, ADDHLD, DATAST, BUSTURN, CLKDIV, DATLAT and ACCMOD bits */ |
| mbed_official | 532:fe11edbda85c | 380 | tmpr &= ((uint32_t)~(FMC_BWTR1_ADDSET | FMC_BWTR1_ADDHLD | FMC_BWTR1_DATAST | \ |
| mbed_official | 532:fe11edbda85c | 381 | FMC_BWTR1_BUSTURN | FMC_BWTR1_CLKDIV | FMC_BWTR1_DATLAT | \ |
| mbed_official | 532:fe11edbda85c | 382 | FMC_BWTR1_ACCMOD)); |
| mbed_official | 532:fe11edbda85c | 383 | |
| mbed_official | 532:fe11edbda85c | 384 | tmpr |= (uint32_t)(Timing->AddressSetupTime |\ |
| mbed_official | 532:fe11edbda85c | 385 | ((Timing->AddressHoldTime) << 4) |\ |
| mbed_official | 532:fe11edbda85c | 386 | ((Timing->DataSetupTime) << 8) |\ |
| mbed_official | 532:fe11edbda85c | 387 | ((Timing->BusTurnAroundDuration) << 16) |\ |
| mbed_official | 532:fe11edbda85c | 388 | (((Timing->CLKDivision)-1) << 20) |\ |
| mbed_official | 532:fe11edbda85c | 389 | (((Timing->DataLatency)-2) << 24) |\ |
| mbed_official | 532:fe11edbda85c | 390 | (Timing->AccessMode)); |
| mbed_official | 532:fe11edbda85c | 391 | #else /* defined(STM32F446xx) */ |
| mbed_official | 532:fe11edbda85c | 392 | /* Clear ADDSET, ADDHLD, DATAST, BUSTURN and ACCMOD bits */ |
| mbed_official | 532:fe11edbda85c | 393 | tmpr &= ((uint32_t)~(FMC_BWTR1_ADDSET | FMC_BWTR1_ADDHLD | FMC_BWTR1_DATAST | \ |
| mbed_official | 532:fe11edbda85c | 394 | FMC_BWTR1_BUSTURN | FMC_BWTR1_ACCMOD)); |
| mbed_official | 532:fe11edbda85c | 395 | |
| mbed_official | 532:fe11edbda85c | 396 | tmpr |= (uint32_t)(Timing->AddressSetupTime |\ |
| mbed_official | 532:fe11edbda85c | 397 | ((Timing->AddressHoldTime) << 4) |\ |
| mbed_official | 532:fe11edbda85c | 398 | ((Timing->DataSetupTime) << 8) |\ |
| mbed_official | 532:fe11edbda85c | 399 | ((Timing->BusTurnAroundDuration) << 16) |\ |
| mbed_official | 532:fe11edbda85c | 400 | (Timing->AccessMode)); |
| mbed_official | 532:fe11edbda85c | 401 | #endif /* defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) */ |
| mbed_official | 532:fe11edbda85c | 402 | |
| mbed_official | 532:fe11edbda85c | 403 | Device->BWTR[Bank] = tmpr; |
| mbed_official | 235:685d5f11838f | 404 | } |
| mbed_official | 532:fe11edbda85c | 405 | else |
| mbed_official | 235:685d5f11838f | 406 | { |
| mbed_official | 235:685d5f11838f | 407 | Device->BWTR[Bank] = 0x0FFFFFFF; |
| mbed_official | 235:685d5f11838f | 408 | } |
| mbed_official | 235:685d5f11838f | 409 | |
| mbed_official | 235:685d5f11838f | 410 | return HAL_OK; |
| mbed_official | 235:685d5f11838f | 411 | } |
| mbed_official | 235:685d5f11838f | 412 | /** |
| mbed_official | 235:685d5f11838f | 413 | * @} |
| mbed_official | 235:685d5f11838f | 414 | */ |
| mbed_official | 235:685d5f11838f | 415 | |
| mbed_official | 532:fe11edbda85c | 416 | /** @addtogroup FMC_LL_NORSRAM_Private_Functions_Group2 |
| mbed_official | 235:685d5f11838f | 417 | * @brief management functions |
| mbed_official | 235:685d5f11838f | 418 | * |
| mbed_official | 235:685d5f11838f | 419 | @verbatim |
| mbed_official | 235:685d5f11838f | 420 | ============================================================================== |
| mbed_official | 235:685d5f11838f | 421 | ##### FMC_NORSRAM Control functions ##### |
| mbed_official | 235:685d5f11838f | 422 | ============================================================================== |
| mbed_official | 235:685d5f11838f | 423 | [..] |
| mbed_official | 235:685d5f11838f | 424 | This subsection provides a set of functions allowing to control dynamically |
| mbed_official | 235:685d5f11838f | 425 | the FMC NORSRAM interface. |
| mbed_official | 235:685d5f11838f | 426 | |
| mbed_official | 235:685d5f11838f | 427 | @endverbatim |
| mbed_official | 235:685d5f11838f | 428 | * @{ |
| mbed_official | 235:685d5f11838f | 429 | */ |
| mbed_official | 235:685d5f11838f | 430 | /** |
| mbed_official | 235:685d5f11838f | 431 | * @brief Enables dynamically FMC_NORSRAM write operation. |
| mbed_official | 235:685d5f11838f | 432 | * @param Device: Pointer to NORSRAM device instance |
| mbed_official | 235:685d5f11838f | 433 | * @param Bank: NORSRAM bank number |
| mbed_official | 235:685d5f11838f | 434 | * @retval HAL status |
| mbed_official | 235:685d5f11838f | 435 | */ |
| mbed_official | 235:685d5f11838f | 436 | HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank) |
| mbed_official | 235:685d5f11838f | 437 | { |
| mbed_official | 235:685d5f11838f | 438 | /* Check the parameters */ |
| mbed_official | 235:685d5f11838f | 439 | assert_param(IS_FMC_NORSRAM_DEVICE(Device)); |
| mbed_official | 235:685d5f11838f | 440 | assert_param(IS_FMC_NORSRAM_BANK(Bank)); |
| mbed_official | 235:685d5f11838f | 441 | |
| mbed_official | 235:685d5f11838f | 442 | /* Enable write operation */ |
| mbed_official | 235:685d5f11838f | 443 | Device->BTCR[Bank] |= FMC_WRITE_OPERATION_ENABLE; |
| mbed_official | 235:685d5f11838f | 444 | |
| mbed_official | 235:685d5f11838f | 445 | return HAL_OK; |
| mbed_official | 235:685d5f11838f | 446 | } |
| mbed_official | 235:685d5f11838f | 447 | |
| mbed_official | 235:685d5f11838f | 448 | /** |
| mbed_official | 235:685d5f11838f | 449 | * @brief Disables dynamically FMC_NORSRAM write operation. |
| mbed_official | 235:685d5f11838f | 450 | * @param Device: Pointer to NORSRAM device instance |
| mbed_official | 235:685d5f11838f | 451 | * @param Bank: NORSRAM bank number |
| mbed_official | 235:685d5f11838f | 452 | * @retval HAL status |
| mbed_official | 235:685d5f11838f | 453 | */ |
| mbed_official | 235:685d5f11838f | 454 | HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank) |
| mbed_official | 235:685d5f11838f | 455 | { |
| mbed_official | 235:685d5f11838f | 456 | /* Check the parameters */ |
| mbed_official | 235:685d5f11838f | 457 | assert_param(IS_FMC_NORSRAM_DEVICE(Device)); |
| mbed_official | 235:685d5f11838f | 458 | assert_param(IS_FMC_NORSRAM_BANK(Bank)); |
| mbed_official | 235:685d5f11838f | 459 | |
| mbed_official | 235:685d5f11838f | 460 | /* Disable write operation */ |
| mbed_official | 235:685d5f11838f | 461 | Device->BTCR[Bank] &= ~FMC_WRITE_OPERATION_ENABLE; |
| mbed_official | 235:685d5f11838f | 462 | |
| mbed_official | 235:685d5f11838f | 463 | return HAL_OK; |
| mbed_official | 235:685d5f11838f | 464 | } |
| mbed_official | 235:685d5f11838f | 465 | |
| mbed_official | 235:685d5f11838f | 466 | /** |
| mbed_official | 235:685d5f11838f | 467 | * @} |
| mbed_official | 235:685d5f11838f | 468 | */ |
| mbed_official | 235:685d5f11838f | 469 | |
| mbed_official | 235:685d5f11838f | 470 | /** |
| mbed_official | 235:685d5f11838f | 471 | * @} |
| mbed_official | 235:685d5f11838f | 472 | */ |
| mbed_official | 532:fe11edbda85c | 473 | |
| mbed_official | 532:fe11edbda85c | 474 | /** @addtogroup FMC_LL_NAND |
| mbed_official | 532:fe11edbda85c | 475 | * @brief NAND Controller functions |
| mbed_official | 235:685d5f11838f | 476 | * |
| mbed_official | 235:685d5f11838f | 477 | @verbatim |
| mbed_official | 235:685d5f11838f | 478 | ============================================================================== |
| mbed_official | 235:685d5f11838f | 479 | ##### How to use NAND device driver ##### |
| mbed_official | 235:685d5f11838f | 480 | ============================================================================== |
| mbed_official | 235:685d5f11838f | 481 | [..] |
| mbed_official | 235:685d5f11838f | 482 | This driver contains a set of APIs to interface with the FMC NAND banks in order |
| mbed_official | 235:685d5f11838f | 483 | to run the NAND external devices. |
| mbed_official | 235:685d5f11838f | 484 | |
| mbed_official | 235:685d5f11838f | 485 | (+) FMC NAND bank reset using the function FMC_NAND_DeInit() |
| mbed_official | 235:685d5f11838f | 486 | (+) FMC NAND bank control configuration using the function FMC_NAND_Init() |
| mbed_official | 235:685d5f11838f | 487 | (+) FMC NAND bank common space timing configuration using the function |
| mbed_official | 235:685d5f11838f | 488 | FMC_NAND_CommonSpace_Timing_Init() |
| mbed_official | 235:685d5f11838f | 489 | (+) FMC NAND bank attribute space timing configuration using the function |
| mbed_official | 235:685d5f11838f | 490 | FMC_NAND_AttributeSpace_Timing_Init() |
| mbed_official | 235:685d5f11838f | 491 | (+) FMC NAND bank enable/disable ECC correction feature using the functions |
| mbed_official | 235:685d5f11838f | 492 | FMC_NAND_ECC_Enable()/FMC_NAND_ECC_Disable() |
| mbed_official | 235:685d5f11838f | 493 | (+) FMC NAND bank get ECC correction code using the function FMC_NAND_GetECC() |
| mbed_official | 235:685d5f11838f | 494 | |
| mbed_official | 235:685d5f11838f | 495 | @endverbatim |
| mbed_official | 235:685d5f11838f | 496 | * @{ |
| mbed_official | 235:685d5f11838f | 497 | */ |
| mbed_official | 532:fe11edbda85c | 498 | |
| mbed_official | 532:fe11edbda85c | 499 | #if defined(STM32F446xx) |
| mbed_official | 235:685d5f11838f | 500 | /** @defgroup HAL_FMC_NAND_Group1 Initialization/de-initialization functions |
| mbed_official | 235:685d5f11838f | 501 | * @brief Initialization and Configuration functions |
| mbed_official | 235:685d5f11838f | 502 | * |
| mbed_official | 235:685d5f11838f | 503 | @verbatim |
| mbed_official | 235:685d5f11838f | 504 | ============================================================================== |
| mbed_official | 235:685d5f11838f | 505 | ##### Initialization and de_initialization functions ##### |
| mbed_official | 235:685d5f11838f | 506 | ============================================================================== |
| mbed_official | 235:685d5f11838f | 507 | [..] |
| mbed_official | 235:685d5f11838f | 508 | This section provides functions allowing to: |
| mbed_official | 235:685d5f11838f | 509 | (+) Initialize and configure the FMC NAND interface |
| mbed_official | 235:685d5f11838f | 510 | (+) De-initialize the FMC NAND interface |
| mbed_official | 235:685d5f11838f | 511 | (+) Configure the FMC clock and associated GPIOs |
| mbed_official | 235:685d5f11838f | 512 | |
| mbed_official | 235:685d5f11838f | 513 | @endverbatim |
| mbed_official | 235:685d5f11838f | 514 | * @{ |
| mbed_official | 235:685d5f11838f | 515 | */ |
| mbed_official | 532:fe11edbda85c | 516 | |
| mbed_official | 235:685d5f11838f | 517 | /** |
| mbed_official | 235:685d5f11838f | 518 | * @brief Initializes the FMC_NAND device according to the specified |
| mbed_official | 235:685d5f11838f | 519 | * control parameters in the FMC_NAND_HandleTypeDef |
| mbed_official | 235:685d5f11838f | 520 | * @param Device: Pointer to NAND device instance |
| mbed_official | 235:685d5f11838f | 521 | * @param Init: Pointer to NAND Initialization structure |
| mbed_official | 235:685d5f11838f | 522 | * @retval HAL status |
| mbed_official | 235:685d5f11838f | 523 | */ |
| mbed_official | 235:685d5f11838f | 524 | HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init) |
| mbed_official | 235:685d5f11838f | 525 | { |
| mbed_official | 532:fe11edbda85c | 526 | uint32_t tmpr = 0; |
| mbed_official | 532:fe11edbda85c | 527 | |
| mbed_official | 532:fe11edbda85c | 528 | /* Check the parameters */ |
| mbed_official | 532:fe11edbda85c | 529 | assert_param(IS_FMC_NAND_DEVICE(Device)); |
| mbed_official | 532:fe11edbda85c | 530 | assert_param(IS_FMC_NAND_BANK(Init->NandBank)); |
| mbed_official | 532:fe11edbda85c | 531 | assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature)); |
| mbed_official | 532:fe11edbda85c | 532 | assert_param(IS_FMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth)); |
| mbed_official | 532:fe11edbda85c | 533 | assert_param(IS_FMC_ECC_STATE(Init->EccComputation)); |
| mbed_official | 532:fe11edbda85c | 534 | assert_param(IS_FMC_ECCPAGE_SIZE(Init->ECCPageSize)); |
| mbed_official | 532:fe11edbda85c | 535 | assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime)); |
| mbed_official | 532:fe11edbda85c | 536 | assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime)); |
| mbed_official | 532:fe11edbda85c | 537 | |
| mbed_official | 532:fe11edbda85c | 538 | /* Get the NAND bank register value */ |
| mbed_official | 532:fe11edbda85c | 539 | tmpr = Device->PCR; |
| mbed_official | 532:fe11edbda85c | 540 | |
| mbed_official | 532:fe11edbda85c | 541 | /* Clear PWAITEN, PBKEN, PTYP, PWID, ECCEN, TCLR, TAR and ECCPS bits */ |
| mbed_official | 532:fe11edbda85c | 542 | tmpr &= ((uint32_t)~(FMC_PCR_PWAITEN | FMC_PCR_PBKEN | FMC_PCR_PTYP | \ |
| mbed_official | 532:fe11edbda85c | 543 | FMC_PCR_PWID | FMC_PCR_ECCEN | FMC_PCR_TCLR | \ |
| mbed_official | 532:fe11edbda85c | 544 | FMC_PCR_TAR | FMC_PCR_ECCPS)); |
| mbed_official | 532:fe11edbda85c | 545 | |
| mbed_official | 532:fe11edbda85c | 546 | /* Set NAND device control parameters */ |
| mbed_official | 532:fe11edbda85c | 547 | tmpr |= (uint32_t)(Init->Waitfeature |\ |
| mbed_official | 532:fe11edbda85c | 548 | FMC_PCR_MEMORY_TYPE_NAND |\ |
| mbed_official | 532:fe11edbda85c | 549 | Init->MemoryDataWidth |\ |
| mbed_official | 532:fe11edbda85c | 550 | Init->EccComputation |\ |
| mbed_official | 532:fe11edbda85c | 551 | Init->ECCPageSize |\ |
| mbed_official | 532:fe11edbda85c | 552 | ((Init->TCLRSetupTime) << 9) |\ |
| mbed_official | 532:fe11edbda85c | 553 | ((Init->TARSetupTime) << 13)); |
| mbed_official | 532:fe11edbda85c | 554 | |
| mbed_official | 532:fe11edbda85c | 555 | /* NAND bank registers configuration */ |
| mbed_official | 532:fe11edbda85c | 556 | Device->PCR = tmpr; |
| mbed_official | 532:fe11edbda85c | 557 | |
| mbed_official | 532:fe11edbda85c | 558 | return HAL_OK; |
| mbed_official | 532:fe11edbda85c | 559 | } |
| mbed_official | 532:fe11edbda85c | 560 | |
| mbed_official | 532:fe11edbda85c | 561 | /** |
| mbed_official | 532:fe11edbda85c | 562 | * @brief Initializes the FMC_NAND Common space Timing according to the specified |
| mbed_official | 532:fe11edbda85c | 563 | * parameters in the FMC_NAND_PCC_TimingTypeDef |
| mbed_official | 532:fe11edbda85c | 564 | * @param Device: Pointer to NAND device instance |
| mbed_official | 532:fe11edbda85c | 565 | * @param Timing: Pointer to NAND timing structure |
| mbed_official | 532:fe11edbda85c | 566 | * @param Bank: NAND bank number |
| mbed_official | 532:fe11edbda85c | 567 | * @retval HAL status |
| mbed_official | 532:fe11edbda85c | 568 | */ |
| mbed_official | 532:fe11edbda85c | 569 | HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) |
| mbed_official | 532:fe11edbda85c | 570 | { |
| mbed_official | 532:fe11edbda85c | 571 | uint32_t tmpr = 0; |
| mbed_official | 532:fe11edbda85c | 572 | |
| mbed_official | 532:fe11edbda85c | 573 | /* Check the parameters */ |
| mbed_official | 532:fe11edbda85c | 574 | assert_param(IS_FMC_NAND_DEVICE(Device)); |
| mbed_official | 532:fe11edbda85c | 575 | assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime)); |
| mbed_official | 532:fe11edbda85c | 576 | assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime)); |
| mbed_official | 532:fe11edbda85c | 577 | assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime)); |
| mbed_official | 532:fe11edbda85c | 578 | assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime)); |
| mbed_official | 532:fe11edbda85c | 579 | assert_param(IS_FMC_NAND_BANK(Bank)); |
| mbed_official | 532:fe11edbda85c | 580 | |
| mbed_official | 532:fe11edbda85c | 581 | /* Get the NAND bank 2 register value */ |
| mbed_official | 532:fe11edbda85c | 582 | tmpr = Device->PMEM; |
| mbed_official | 532:fe11edbda85c | 583 | |
| mbed_official | 532:fe11edbda85c | 584 | |
| mbed_official | 532:fe11edbda85c | 585 | /* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */ |
| mbed_official | 532:fe11edbda85c | 586 | tmpr &= ((uint32_t)~(FMC_PMEM_MEMSET2 | FMC_PMEM_MEMWAIT2 | FMC_PMEM_MEMHOLD2 | \ |
| mbed_official | 532:fe11edbda85c | 587 | FMC_PMEM_MEMHIZ2)); |
| mbed_official | 532:fe11edbda85c | 588 | |
| mbed_official | 532:fe11edbda85c | 589 | /* Set FMC_NAND device timing parameters */ |
| mbed_official | 532:fe11edbda85c | 590 | tmpr |= (uint32_t)(Timing->SetupTime |\ |
| mbed_official | 532:fe11edbda85c | 591 | ((Timing->WaitSetupTime) << 8) |\ |
| mbed_official | 532:fe11edbda85c | 592 | ((Timing->HoldSetupTime) << 16) |\ |
| mbed_official | 532:fe11edbda85c | 593 | ((Timing->HiZSetupTime) << 24) |
| mbed_official | 532:fe11edbda85c | 594 | ); |
| mbed_official | 532:fe11edbda85c | 595 | |
| mbed_official | 532:fe11edbda85c | 596 | /* NAND bank registers configuration */ |
| mbed_official | 532:fe11edbda85c | 597 | Device->PMEM = tmpr; |
| mbed_official | 532:fe11edbda85c | 598 | |
| mbed_official | 532:fe11edbda85c | 599 | return HAL_OK; |
| mbed_official | 532:fe11edbda85c | 600 | } |
| mbed_official | 532:fe11edbda85c | 601 | |
| mbed_official | 532:fe11edbda85c | 602 | /** |
| mbed_official | 532:fe11edbda85c | 603 | * @brief Initializes the FMC_NAND Attribute space Timing according to the specified |
| mbed_official | 532:fe11edbda85c | 604 | * parameters in the FMC_NAND_PCC_TimingTypeDef |
| mbed_official | 532:fe11edbda85c | 605 | * @param Device: Pointer to NAND device instance |
| mbed_official | 532:fe11edbda85c | 606 | * @param Timing: Pointer to NAND timing structure |
| mbed_official | 532:fe11edbda85c | 607 | * @param Bank: NAND bank number |
| mbed_official | 532:fe11edbda85c | 608 | * @retval HAL status |
| mbed_official | 532:fe11edbda85c | 609 | */ |
| mbed_official | 532:fe11edbda85c | 610 | HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) |
| mbed_official | 532:fe11edbda85c | 611 | { |
| mbed_official | 532:fe11edbda85c | 612 | uint32_t tmpr = 0; |
| mbed_official | 532:fe11edbda85c | 613 | |
| mbed_official | 532:fe11edbda85c | 614 | /* Check the parameters */ |
| mbed_official | 532:fe11edbda85c | 615 | assert_param(IS_FMC_NAND_DEVICE(Device)); |
| mbed_official | 532:fe11edbda85c | 616 | assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime)); |
| mbed_official | 532:fe11edbda85c | 617 | assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime)); |
| mbed_official | 532:fe11edbda85c | 618 | assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime)); |
| mbed_official | 532:fe11edbda85c | 619 | assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime)); |
| mbed_official | 532:fe11edbda85c | 620 | assert_param(IS_FMC_NAND_BANK(Bank)); |
| mbed_official | 532:fe11edbda85c | 621 | |
| mbed_official | 532:fe11edbda85c | 622 | /* Get the NAND bank register value */ |
| mbed_official | 532:fe11edbda85c | 623 | tmpr = Device->PATT; |
| mbed_official | 532:fe11edbda85c | 624 | |
| mbed_official | 532:fe11edbda85c | 625 | /* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */ |
| mbed_official | 532:fe11edbda85c | 626 | tmpr &= ((uint32_t)~(FMC_PATT_ATTSET2 | FMC_PATT_ATTWAIT2 | FMC_PATT_ATTHOLD2 | \ |
| mbed_official | 532:fe11edbda85c | 627 | FMC_PATT_ATTHIZ2)); |
| mbed_official | 532:fe11edbda85c | 628 | |
| mbed_official | 532:fe11edbda85c | 629 | /* Set FMC_NAND device timing parameters */ |
| mbed_official | 532:fe11edbda85c | 630 | tmpr |= (uint32_t)(Timing->SetupTime |\ |
| mbed_official | 532:fe11edbda85c | 631 | ((Timing->WaitSetupTime) << 8) |\ |
| mbed_official | 532:fe11edbda85c | 632 | ((Timing->HoldSetupTime) << 16) |\ |
| mbed_official | 532:fe11edbda85c | 633 | ((Timing->HiZSetupTime) << 24)); |
| mbed_official | 532:fe11edbda85c | 634 | |
| mbed_official | 532:fe11edbda85c | 635 | /* NAND bank registers configuration */ |
| mbed_official | 532:fe11edbda85c | 636 | Device->PATT = tmpr; |
| mbed_official | 532:fe11edbda85c | 637 | |
| mbed_official | 532:fe11edbda85c | 638 | return HAL_OK; |
| mbed_official | 532:fe11edbda85c | 639 | } |
| mbed_official | 532:fe11edbda85c | 640 | |
| mbed_official | 532:fe11edbda85c | 641 | |
| mbed_official | 532:fe11edbda85c | 642 | /** |
| mbed_official | 532:fe11edbda85c | 643 | * @brief DeInitializes the FMC_NAND device |
| mbed_official | 532:fe11edbda85c | 644 | * @param Device: Pointer to NAND device instance |
| mbed_official | 532:fe11edbda85c | 645 | * @param Bank: NAND bank number |
| mbed_official | 532:fe11edbda85c | 646 | * @retval HAL status |
| mbed_official | 532:fe11edbda85c | 647 | */ |
| mbed_official | 532:fe11edbda85c | 648 | HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank) |
| mbed_official | 532:fe11edbda85c | 649 | { |
| mbed_official | 532:fe11edbda85c | 650 | /* Check the parameters */ |
| mbed_official | 532:fe11edbda85c | 651 | assert_param(IS_FMC_NAND_DEVICE(Device)); |
| mbed_official | 532:fe11edbda85c | 652 | assert_param(IS_FMC_NAND_BANK(Bank)); |
| mbed_official | 532:fe11edbda85c | 653 | |
| mbed_official | 532:fe11edbda85c | 654 | /* Disable the NAND Bank */ |
| mbed_official | 532:fe11edbda85c | 655 | __FMC_NAND_DISABLE(Device, Bank); |
| mbed_official | 532:fe11edbda85c | 656 | |
| mbed_official | 532:fe11edbda85c | 657 | /* De-initialize the NAND Bank */ |
| mbed_official | 532:fe11edbda85c | 658 | /* Set the FMC_NAND_BANK registers to their reset values */ |
| mbed_official | 532:fe11edbda85c | 659 | Device->PCR = 0x00000018; |
| mbed_official | 532:fe11edbda85c | 660 | Device->SR = 0x00000040; |
| mbed_official | 532:fe11edbda85c | 661 | Device->PMEM = 0xFCFCFCFC; |
| mbed_official | 532:fe11edbda85c | 662 | Device->PATT = 0xFCFCFCFC; |
| mbed_official | 532:fe11edbda85c | 663 | |
| mbed_official | 532:fe11edbda85c | 664 | return HAL_OK; |
| mbed_official | 532:fe11edbda85c | 665 | } |
| mbed_official | 532:fe11edbda85c | 666 | |
| mbed_official | 532:fe11edbda85c | 667 | /** |
| mbed_official | 532:fe11edbda85c | 668 | * @} |
| mbed_official | 532:fe11edbda85c | 669 | */ |
| mbed_official | 532:fe11edbda85c | 670 | |
| mbed_official | 532:fe11edbda85c | 671 | |
| mbed_official | 532:fe11edbda85c | 672 | /** @defgroup HAL_FMC_NAND_Group2 Control functions |
| mbed_official | 532:fe11edbda85c | 673 | * @brief management functions |
| mbed_official | 532:fe11edbda85c | 674 | * |
| mbed_official | 532:fe11edbda85c | 675 | @verbatim |
| mbed_official | 532:fe11edbda85c | 676 | ============================================================================== |
| mbed_official | 532:fe11edbda85c | 677 | ##### FMC_NAND Control functions ##### |
| mbed_official | 532:fe11edbda85c | 678 | ============================================================================== |
| mbed_official | 532:fe11edbda85c | 679 | [..] |
| mbed_official | 532:fe11edbda85c | 680 | This subsection provides a set of functions allowing to control dynamically |
| mbed_official | 532:fe11edbda85c | 681 | the FMC NAND interface. |
| mbed_official | 532:fe11edbda85c | 682 | |
| mbed_official | 532:fe11edbda85c | 683 | @endverbatim |
| mbed_official | 532:fe11edbda85c | 684 | * @{ |
| mbed_official | 532:fe11edbda85c | 685 | */ |
| mbed_official | 532:fe11edbda85c | 686 | |
| mbed_official | 532:fe11edbda85c | 687 | |
| mbed_official | 532:fe11edbda85c | 688 | /** |
| mbed_official | 532:fe11edbda85c | 689 | * @brief Enables dynamically FMC_NAND ECC feature. |
| mbed_official | 532:fe11edbda85c | 690 | * @param Device: Pointer to NAND device instance |
| mbed_official | 532:fe11edbda85c | 691 | * @param Bank: NAND bank number |
| mbed_official | 532:fe11edbda85c | 692 | * @retval HAL status |
| mbed_official | 532:fe11edbda85c | 693 | */ |
| mbed_official | 532:fe11edbda85c | 694 | HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank) |
| mbed_official | 532:fe11edbda85c | 695 | { |
| mbed_official | 532:fe11edbda85c | 696 | /* Check the parameters */ |
| mbed_official | 532:fe11edbda85c | 697 | assert_param(IS_FMC_NAND_DEVICE(Device)); |
| mbed_official | 532:fe11edbda85c | 698 | assert_param(IS_FMC_NAND_BANK(Bank)); |
| mbed_official | 532:fe11edbda85c | 699 | |
| mbed_official | 532:fe11edbda85c | 700 | /* Enable ECC feature */ |
| mbed_official | 532:fe11edbda85c | 701 | Device->PCR |= FMC_PCR_ECCEN; |
| mbed_official | 532:fe11edbda85c | 702 | |
| mbed_official | 532:fe11edbda85c | 703 | return HAL_OK; |
| mbed_official | 532:fe11edbda85c | 704 | } |
| mbed_official | 532:fe11edbda85c | 705 | |
| mbed_official | 532:fe11edbda85c | 706 | |
| mbed_official | 532:fe11edbda85c | 707 | /** |
| mbed_official | 532:fe11edbda85c | 708 | * @brief Disables dynamically FMC_NAND ECC feature. |
| mbed_official | 532:fe11edbda85c | 709 | * @param Device: Pointer to NAND device instance |
| mbed_official | 532:fe11edbda85c | 710 | * @param Bank: NAND bank number |
| mbed_official | 532:fe11edbda85c | 711 | * @retval HAL status |
| mbed_official | 532:fe11edbda85c | 712 | */ |
| mbed_official | 532:fe11edbda85c | 713 | HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank) |
| mbed_official | 532:fe11edbda85c | 714 | { |
| mbed_official | 532:fe11edbda85c | 715 | /* Check the parameters */ |
| mbed_official | 532:fe11edbda85c | 716 | assert_param(IS_FMC_NAND_DEVICE(Device)); |
| mbed_official | 532:fe11edbda85c | 717 | assert_param(IS_FMC_NAND_BANK(Bank)); |
| mbed_official | 532:fe11edbda85c | 718 | |
| mbed_official | 532:fe11edbda85c | 719 | /* Disable ECC feature */ |
| mbed_official | 532:fe11edbda85c | 720 | Device->PCR &= ~FMC_PCR_ECCEN; |
| mbed_official | 532:fe11edbda85c | 721 | |
| mbed_official | 532:fe11edbda85c | 722 | return HAL_OK; |
| mbed_official | 532:fe11edbda85c | 723 | } |
| mbed_official | 532:fe11edbda85c | 724 | |
| mbed_official | 532:fe11edbda85c | 725 | /** |
| mbed_official | 532:fe11edbda85c | 726 | * @brief Disables dynamically FMC_NAND ECC feature. |
| mbed_official | 532:fe11edbda85c | 727 | * @param Device: Pointer to NAND device instance |
| mbed_official | 532:fe11edbda85c | 728 | * @param ECCval: Pointer to ECC value |
| mbed_official | 532:fe11edbda85c | 729 | * @param Bank: NAND bank number |
| mbed_official | 532:fe11edbda85c | 730 | * @param Timeout: Timeout wait value |
| mbed_official | 532:fe11edbda85c | 731 | * @retval HAL status |
| mbed_official | 532:fe11edbda85c | 732 | */ |
| mbed_official | 532:fe11edbda85c | 733 | HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout) |
| mbed_official | 532:fe11edbda85c | 734 | { |
| mbed_official | 532:fe11edbda85c | 735 | uint32_t tickstart = 0; |
| mbed_official | 532:fe11edbda85c | 736 | |
| mbed_official | 532:fe11edbda85c | 737 | /* Check the parameters */ |
| mbed_official | 532:fe11edbda85c | 738 | assert_param(IS_FMC_NAND_DEVICE(Device)); |
| mbed_official | 532:fe11edbda85c | 739 | assert_param(IS_FMC_NAND_BANK(Bank)); |
| mbed_official | 532:fe11edbda85c | 740 | |
| mbed_official | 532:fe11edbda85c | 741 | /* Get tick */ |
| mbed_official | 532:fe11edbda85c | 742 | tickstart = HAL_GetTick(); |
| mbed_official | 532:fe11edbda85c | 743 | |
| mbed_official | 532:fe11edbda85c | 744 | /* Wait until FIFO is empty */ |
| mbed_official | 532:fe11edbda85c | 745 | while(__FMC_NAND_GET_FLAG(Device, Bank, FMC_FLAG_FEMPT) == RESET) |
| mbed_official | 532:fe11edbda85c | 746 | { |
| mbed_official | 532:fe11edbda85c | 747 | /* Check for the Timeout */ |
| mbed_official | 532:fe11edbda85c | 748 | if(Timeout != HAL_MAX_DELAY) |
| mbed_official | 532:fe11edbda85c | 749 | { |
| mbed_official | 532:fe11edbda85c | 750 | if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) |
| mbed_official | 532:fe11edbda85c | 751 | { |
| mbed_official | 532:fe11edbda85c | 752 | return HAL_TIMEOUT; |
| mbed_official | 532:fe11edbda85c | 753 | } |
| mbed_official | 532:fe11edbda85c | 754 | } |
| mbed_official | 532:fe11edbda85c | 755 | } |
| mbed_official | 532:fe11edbda85c | 756 | |
| mbed_official | 532:fe11edbda85c | 757 | /* Get the ECCR register value */ |
| mbed_official | 532:fe11edbda85c | 758 | *ECCval = (uint32_t)Device->ECCR; |
| mbed_official | 532:fe11edbda85c | 759 | |
| mbed_official | 532:fe11edbda85c | 760 | return HAL_OK; |
| mbed_official | 532:fe11edbda85c | 761 | } |
| mbed_official | 532:fe11edbda85c | 762 | |
| mbed_official | 532:fe11edbda85c | 763 | /** |
| mbed_official | 532:fe11edbda85c | 764 | * @} |
| mbed_official | 532:fe11edbda85c | 765 | */ |
| mbed_official | 532:fe11edbda85c | 766 | |
| mbed_official | 532:fe11edbda85c | 767 | #else /* defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) */ |
| mbed_official | 532:fe11edbda85c | 768 | /** @defgroup HAL_FMC_NAND_Group1 Initialization/de-initialization functions |
| mbed_official | 532:fe11edbda85c | 769 | * @brief Initialization and Configuration functions |
| mbed_official | 532:fe11edbda85c | 770 | * |
| mbed_official | 532:fe11edbda85c | 771 | @verbatim |
| mbed_official | 532:fe11edbda85c | 772 | ============================================================================== |
| mbed_official | 532:fe11edbda85c | 773 | ##### Initialization and de_initialization functions ##### |
| mbed_official | 532:fe11edbda85c | 774 | ============================================================================== |
| mbed_official | 532:fe11edbda85c | 775 | [..] |
| mbed_official | 532:fe11edbda85c | 776 | This section provides functions allowing to: |
| mbed_official | 532:fe11edbda85c | 777 | (+) Initialize and configure the FMC NAND interface |
| mbed_official | 532:fe11edbda85c | 778 | (+) De-initialize the FMC NAND interface |
| mbed_official | 532:fe11edbda85c | 779 | (+) Configure the FMC clock and associated GPIOs |
| mbed_official | 532:fe11edbda85c | 780 | |
| mbed_official | 532:fe11edbda85c | 781 | @endverbatim |
| mbed_official | 532:fe11edbda85c | 782 | * @{ |
| mbed_official | 532:fe11edbda85c | 783 | */ |
| mbed_official | 532:fe11edbda85c | 784 | /** |
| mbed_official | 532:fe11edbda85c | 785 | * @brief Initializes the FMC_NAND device according to the specified |
| mbed_official | 532:fe11edbda85c | 786 | * control parameters in the FMC_NAND_HandleTypeDef |
| mbed_official | 532:fe11edbda85c | 787 | * @param Device: Pointer to NAND device instance |
| mbed_official | 532:fe11edbda85c | 788 | * @param Init: Pointer to NAND Initialization structure |
| mbed_official | 532:fe11edbda85c | 789 | * @retval HAL status |
| mbed_official | 532:fe11edbda85c | 790 | */ |
| mbed_official | 532:fe11edbda85c | 791 | HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init) |
| mbed_official | 532:fe11edbda85c | 792 | { |
| mbed_official | 532:fe11edbda85c | 793 | uint32_t tmpr = 0; |
| mbed_official | 235:685d5f11838f | 794 | |
| mbed_official | 235:685d5f11838f | 795 | /* Check the parameters */ |
| mbed_official | 235:685d5f11838f | 796 | assert_param(IS_FMC_NAND_DEVICE(Device)); |
| mbed_official | 235:685d5f11838f | 797 | assert_param(IS_FMC_NAND_BANK(Init->NandBank)); |
| mbed_official | 235:685d5f11838f | 798 | assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature)); |
| mbed_official | 235:685d5f11838f | 799 | assert_param(IS_FMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth)); |
| mbed_official | 235:685d5f11838f | 800 | assert_param(IS_FMC_ECC_STATE(Init->EccComputation)); |
| mbed_official | 235:685d5f11838f | 801 | assert_param(IS_FMC_ECCPAGE_SIZE(Init->ECCPageSize)); |
| mbed_official | 235:685d5f11838f | 802 | assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime)); |
| mbed_official | 235:685d5f11838f | 803 | assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime)); |
| mbed_official | 235:685d5f11838f | 804 | |
| mbed_official | 532:fe11edbda85c | 805 | if(Init->NandBank == FMC_NAND_BANK2) |
| mbed_official | 532:fe11edbda85c | 806 | { |
| mbed_official | 532:fe11edbda85c | 807 | /* Get the NAND bank 2 register value */ |
| mbed_official | 532:fe11edbda85c | 808 | tmpr = Device->PCR2; |
| mbed_official | 532:fe11edbda85c | 809 | } |
| mbed_official | 532:fe11edbda85c | 810 | else |
| mbed_official | 532:fe11edbda85c | 811 | { |
| mbed_official | 532:fe11edbda85c | 812 | /* Get the NAND bank 3 register value */ |
| mbed_official | 532:fe11edbda85c | 813 | tmpr = Device->PCR3; |
| mbed_official | 532:fe11edbda85c | 814 | } |
| mbed_official | 532:fe11edbda85c | 815 | |
| mbed_official | 532:fe11edbda85c | 816 | /* Clear PWAITEN, PBKEN, PTYP, PWID, ECCEN, TCLR, TAR and ECCPS bits */ |
| mbed_official | 532:fe11edbda85c | 817 | tmpr &= ((uint32_t)~(FMC_PCR2_PWAITEN | FMC_PCR2_PBKEN | FMC_PCR2_PTYP | \ |
| mbed_official | 532:fe11edbda85c | 818 | FMC_PCR2_PWID | FMC_PCR2_ECCEN | FMC_PCR2_TCLR | \ |
| mbed_official | 532:fe11edbda85c | 819 | FMC_PCR2_TAR | FMC_PCR2_ECCPS)); |
| mbed_official | 532:fe11edbda85c | 820 | |
| mbed_official | 235:685d5f11838f | 821 | /* Set NAND device control parameters */ |
| mbed_official | 532:fe11edbda85c | 822 | tmpr |= (uint32_t)(Init->Waitfeature |\ |
| mbed_official | 532:fe11edbda85c | 823 | FMC_PCR_MEMORY_TYPE_NAND |\ |
| mbed_official | 532:fe11edbda85c | 824 | Init->MemoryDataWidth |\ |
| mbed_official | 532:fe11edbda85c | 825 | Init->EccComputation |\ |
| mbed_official | 532:fe11edbda85c | 826 | Init->ECCPageSize |\ |
| mbed_official | 532:fe11edbda85c | 827 | ((Init->TCLRSetupTime) << 9) |\ |
| mbed_official | 532:fe11edbda85c | 828 | ((Init->TARSetupTime) << 13)); |
| mbed_official | 235:685d5f11838f | 829 | |
| mbed_official | 235:685d5f11838f | 830 | if(Init->NandBank == FMC_NAND_BANK2) |
| mbed_official | 235:685d5f11838f | 831 | { |
| mbed_official | 235:685d5f11838f | 832 | /* NAND bank 2 registers configuration */ |
| mbed_official | 532:fe11edbda85c | 833 | Device->PCR2 = tmpr; |
| mbed_official | 235:685d5f11838f | 834 | } |
| mbed_official | 235:685d5f11838f | 835 | else |
| mbed_official | 235:685d5f11838f | 836 | { |
| mbed_official | 235:685d5f11838f | 837 | /* NAND bank 3 registers configuration */ |
| mbed_official | 532:fe11edbda85c | 838 | Device->PCR3 = tmpr; |
| mbed_official | 235:685d5f11838f | 839 | } |
| mbed_official | 235:685d5f11838f | 840 | |
| mbed_official | 235:685d5f11838f | 841 | return HAL_OK; |
| mbed_official | 235:685d5f11838f | 842 | |
| mbed_official | 235:685d5f11838f | 843 | } |
| mbed_official | 235:685d5f11838f | 844 | |
| mbed_official | 235:685d5f11838f | 845 | /** |
| mbed_official | 235:685d5f11838f | 846 | * @brief Initializes the FMC_NAND Common space Timing according to the specified |
| mbed_official | 235:685d5f11838f | 847 | * parameters in the FMC_NAND_PCC_TimingTypeDef |
| mbed_official | 235:685d5f11838f | 848 | * @param Device: Pointer to NAND device instance |
| mbed_official | 235:685d5f11838f | 849 | * @param Timing: Pointer to NAND timing structure |
| mbed_official | 235:685d5f11838f | 850 | * @param Bank: NAND bank number |
| mbed_official | 235:685d5f11838f | 851 | * @retval HAL status |
| mbed_official | 235:685d5f11838f | 852 | */ |
| mbed_official | 235:685d5f11838f | 853 | HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) |
| mbed_official | 235:685d5f11838f | 854 | { |
| mbed_official | 532:fe11edbda85c | 855 | uint32_t tmpr = 0; |
| mbed_official | 235:685d5f11838f | 856 | |
| mbed_official | 235:685d5f11838f | 857 | /* Check the parameters */ |
| mbed_official | 235:685d5f11838f | 858 | assert_param(IS_FMC_NAND_DEVICE(Device)); |
| mbed_official | 235:685d5f11838f | 859 | assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime)); |
| mbed_official | 235:685d5f11838f | 860 | assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime)); |
| mbed_official | 235:685d5f11838f | 861 | assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime)); |
| mbed_official | 235:685d5f11838f | 862 | assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime)); |
| mbed_official | 235:685d5f11838f | 863 | assert_param(IS_FMC_NAND_BANK(Bank)); |
| mbed_official | 235:685d5f11838f | 864 | |
| mbed_official | 532:fe11edbda85c | 865 | if(Bank == FMC_NAND_BANK2) |
| mbed_official | 532:fe11edbda85c | 866 | { |
| mbed_official | 532:fe11edbda85c | 867 | /* Get the NAND bank 2 register value */ |
| mbed_official | 532:fe11edbda85c | 868 | tmpr = Device->PMEM2; |
| mbed_official | 532:fe11edbda85c | 869 | } |
| mbed_official | 532:fe11edbda85c | 870 | else |
| mbed_official | 532:fe11edbda85c | 871 | { |
| mbed_official | 532:fe11edbda85c | 872 | /* Get the NAND bank 3 register value */ |
| mbed_official | 532:fe11edbda85c | 873 | tmpr = Device->PMEM3; |
| mbed_official | 532:fe11edbda85c | 874 | } |
| mbed_official | 532:fe11edbda85c | 875 | |
| mbed_official | 532:fe11edbda85c | 876 | /* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */ |
| mbed_official | 532:fe11edbda85c | 877 | tmpr &= ((uint32_t)~(FMC_PMEM2_MEMSET2 | FMC_PMEM2_MEMWAIT2 | FMC_PMEM2_MEMHOLD2 | \ |
| mbed_official | 532:fe11edbda85c | 878 | FMC_PMEM2_MEMHIZ2)); |
| mbed_official | 532:fe11edbda85c | 879 | |
| mbed_official | 235:685d5f11838f | 880 | /* Set FMC_NAND device timing parameters */ |
| mbed_official | 532:fe11edbda85c | 881 | tmpr |= (uint32_t)(Timing->SetupTime |\ |
| mbed_official | 235:685d5f11838f | 882 | ((Timing->WaitSetupTime) << 8) |\ |
| mbed_official | 235:685d5f11838f | 883 | ((Timing->HoldSetupTime) << 16) |\ |
| mbed_official | 235:685d5f11838f | 884 | ((Timing->HiZSetupTime) << 24) |
| mbed_official | 235:685d5f11838f | 885 | ); |
| mbed_official | 235:685d5f11838f | 886 | |
| mbed_official | 235:685d5f11838f | 887 | if(Bank == FMC_NAND_BANK2) |
| mbed_official | 235:685d5f11838f | 888 | { |
| mbed_official | 235:685d5f11838f | 889 | /* NAND bank 2 registers configuration */ |
| mbed_official | 532:fe11edbda85c | 890 | Device->PMEM2 = tmpr; |
| mbed_official | 235:685d5f11838f | 891 | } |
| mbed_official | 235:685d5f11838f | 892 | else |
| mbed_official | 235:685d5f11838f | 893 | { |
| mbed_official | 235:685d5f11838f | 894 | /* NAND bank 3 registers configuration */ |
| mbed_official | 532:fe11edbda85c | 895 | Device->PMEM3 = tmpr; |
| mbed_official | 235:685d5f11838f | 896 | } |
| mbed_official | 235:685d5f11838f | 897 | |
| mbed_official | 235:685d5f11838f | 898 | return HAL_OK; |
| mbed_official | 235:685d5f11838f | 899 | } |
| mbed_official | 235:685d5f11838f | 900 | |
| mbed_official | 235:685d5f11838f | 901 | /** |
| mbed_official | 235:685d5f11838f | 902 | * @brief Initializes the FMC_NAND Attribute space Timing according to the specified |
| mbed_official | 235:685d5f11838f | 903 | * parameters in the FMC_NAND_PCC_TimingTypeDef |
| mbed_official | 235:685d5f11838f | 904 | * @param Device: Pointer to NAND device instance |
| mbed_official | 235:685d5f11838f | 905 | * @param Timing: Pointer to NAND timing structure |
| mbed_official | 235:685d5f11838f | 906 | * @param Bank: NAND bank number |
| mbed_official | 235:685d5f11838f | 907 | * @retval HAL status |
| mbed_official | 235:685d5f11838f | 908 | */ |
| mbed_official | 235:685d5f11838f | 909 | HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) |
| mbed_official | 235:685d5f11838f | 910 | { |
| mbed_official | 532:fe11edbda85c | 911 | uint32_t tmpr = 0; |
| mbed_official | 235:685d5f11838f | 912 | |
| mbed_official | 235:685d5f11838f | 913 | /* Check the parameters */ |
| mbed_official | 235:685d5f11838f | 914 | assert_param(IS_FMC_NAND_DEVICE(Device)); |
| mbed_official | 235:685d5f11838f | 915 | assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime)); |
| mbed_official | 235:685d5f11838f | 916 | assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime)); |
| mbed_official | 235:685d5f11838f | 917 | assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime)); |
| mbed_official | 235:685d5f11838f | 918 | assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime)); |
| mbed_official | 235:685d5f11838f | 919 | assert_param(IS_FMC_NAND_BANK(Bank)); |
| mbed_official | 235:685d5f11838f | 920 | |
| mbed_official | 532:fe11edbda85c | 921 | if(Bank == FMC_NAND_BANK2) |
| mbed_official | 532:fe11edbda85c | 922 | { |
| mbed_official | 532:fe11edbda85c | 923 | /* Get the NAND bank 2 register value */ |
| mbed_official | 532:fe11edbda85c | 924 | tmpr = Device->PATT2; |
| mbed_official | 532:fe11edbda85c | 925 | } |
| mbed_official | 532:fe11edbda85c | 926 | else |
| mbed_official | 532:fe11edbda85c | 927 | { |
| mbed_official | 532:fe11edbda85c | 928 | /* Get the NAND bank 3 register value */ |
| mbed_official | 532:fe11edbda85c | 929 | tmpr = Device->PATT3; |
| mbed_official | 532:fe11edbda85c | 930 | } |
| mbed_official | 532:fe11edbda85c | 931 | |
| mbed_official | 532:fe11edbda85c | 932 | /* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */ |
| mbed_official | 532:fe11edbda85c | 933 | tmpr &= ((uint32_t)~(FMC_PATT2_ATTSET2 | FMC_PATT2_ATTWAIT2 | FMC_PATT2_ATTHOLD2 | \ |
| mbed_official | 532:fe11edbda85c | 934 | FMC_PATT2_ATTHIZ2)); |
| mbed_official | 532:fe11edbda85c | 935 | |
| mbed_official | 235:685d5f11838f | 936 | /* Set FMC_NAND device timing parameters */ |
| mbed_official | 532:fe11edbda85c | 937 | tmpr |= (uint32_t)(Timing->SetupTime |\ |
| mbed_official | 532:fe11edbda85c | 938 | ((Timing->WaitSetupTime) << 8) |\ |
| mbed_official | 532:fe11edbda85c | 939 | ((Timing->HoldSetupTime) << 16) |\ |
| mbed_official | 532:fe11edbda85c | 940 | ((Timing->HiZSetupTime) << 24)); |
| mbed_official | 235:685d5f11838f | 941 | |
| mbed_official | 235:685d5f11838f | 942 | if(Bank == FMC_NAND_BANK2) |
| mbed_official | 235:685d5f11838f | 943 | { |
| mbed_official | 235:685d5f11838f | 944 | /* NAND bank 2 registers configuration */ |
| mbed_official | 532:fe11edbda85c | 945 | Device->PATT2 = tmpr; |
| mbed_official | 235:685d5f11838f | 946 | } |
| mbed_official | 235:685d5f11838f | 947 | else |
| mbed_official | 235:685d5f11838f | 948 | { |
| mbed_official | 235:685d5f11838f | 949 | /* NAND bank 3 registers configuration */ |
| mbed_official | 532:fe11edbda85c | 950 | Device->PATT3 = tmpr; |
| mbed_official | 235:685d5f11838f | 951 | } |
| mbed_official | 235:685d5f11838f | 952 | |
| mbed_official | 235:685d5f11838f | 953 | return HAL_OK; |
| mbed_official | 235:685d5f11838f | 954 | } |
| mbed_official | 235:685d5f11838f | 955 | |
| mbed_official | 235:685d5f11838f | 956 | /** |
| mbed_official | 235:685d5f11838f | 957 | * @brief DeInitializes the FMC_NAND device |
| mbed_official | 235:685d5f11838f | 958 | * @param Device: Pointer to NAND device instance |
| mbed_official | 235:685d5f11838f | 959 | * @param Bank: NAND bank number |
| mbed_official | 235:685d5f11838f | 960 | * @retval HAL status |
| mbed_official | 235:685d5f11838f | 961 | */ |
| mbed_official | 235:685d5f11838f | 962 | HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank) |
| mbed_official | 235:685d5f11838f | 963 | { |
| mbed_official | 235:685d5f11838f | 964 | /* Check the parameters */ |
| mbed_official | 235:685d5f11838f | 965 | assert_param(IS_FMC_NAND_DEVICE(Device)); |
| mbed_official | 235:685d5f11838f | 966 | assert_param(IS_FMC_NAND_BANK(Bank)); |
| mbed_official | 235:685d5f11838f | 967 | |
| mbed_official | 235:685d5f11838f | 968 | /* Disable the NAND Bank */ |
| mbed_official | 235:685d5f11838f | 969 | __FMC_NAND_DISABLE(Device, Bank); |
| mbed_official | 235:685d5f11838f | 970 | |
| mbed_official | 235:685d5f11838f | 971 | /* De-initialize the NAND Bank */ |
| mbed_official | 235:685d5f11838f | 972 | if(Bank == FMC_NAND_BANK2) |
| mbed_official | 235:685d5f11838f | 973 | { |
| mbed_official | 235:685d5f11838f | 974 | /* Set the FMC_NAND_BANK2 registers to their reset values */ |
| mbed_official | 235:685d5f11838f | 975 | Device->PCR2 = 0x00000018; |
| mbed_official | 235:685d5f11838f | 976 | Device->SR2 = 0x00000040; |
| mbed_official | 235:685d5f11838f | 977 | Device->PMEM2 = 0xFCFCFCFC; |
| mbed_official | 235:685d5f11838f | 978 | Device->PATT2 = 0xFCFCFCFC; |
| mbed_official | 235:685d5f11838f | 979 | } |
| mbed_official | 235:685d5f11838f | 980 | /* FMC_Bank3_NAND */ |
| mbed_official | 235:685d5f11838f | 981 | else |
| mbed_official | 235:685d5f11838f | 982 | { |
| mbed_official | 235:685d5f11838f | 983 | /* Set the FMC_NAND_BANK3 registers to their reset values */ |
| mbed_official | 235:685d5f11838f | 984 | Device->PCR3 = 0x00000018; |
| mbed_official | 235:685d5f11838f | 985 | Device->SR3 = 0x00000040; |
| mbed_official | 235:685d5f11838f | 986 | Device->PMEM3 = 0xFCFCFCFC; |
| mbed_official | 235:685d5f11838f | 987 | Device->PATT3 = 0xFCFCFCFC; |
| mbed_official | 235:685d5f11838f | 988 | } |
| mbed_official | 235:685d5f11838f | 989 | |
| mbed_official | 235:685d5f11838f | 990 | return HAL_OK; |
| mbed_official | 235:685d5f11838f | 991 | } |
| mbed_official | 235:685d5f11838f | 992 | |
| mbed_official | 235:685d5f11838f | 993 | /** |
| mbed_official | 235:685d5f11838f | 994 | * @} |
| mbed_official | 235:685d5f11838f | 995 | */ |
| mbed_official | 532:fe11edbda85c | 996 | |
| mbed_official | 532:fe11edbda85c | 997 | /** @addtogroup FMC_LL_NAND_Private_Functions_Group2 |
| mbed_official | 532:fe11edbda85c | 998 | * @brief management functions |
| mbed_official | 532:fe11edbda85c | 999 | * |
| mbed_official | 235:685d5f11838f | 1000 | @verbatim |
| mbed_official | 235:685d5f11838f | 1001 | ============================================================================== |
| mbed_official | 235:685d5f11838f | 1002 | ##### FMC_NAND Control functions ##### |
| mbed_official | 235:685d5f11838f | 1003 | ============================================================================== |
| mbed_official | 235:685d5f11838f | 1004 | [..] |
| mbed_official | 235:685d5f11838f | 1005 | This subsection provides a set of functions allowing to control dynamically |
| mbed_official | 235:685d5f11838f | 1006 | the FMC NAND interface. |
| mbed_official | 235:685d5f11838f | 1007 | |
| mbed_official | 235:685d5f11838f | 1008 | @endverbatim |
| mbed_official | 235:685d5f11838f | 1009 | * @{ |
| mbed_official | 235:685d5f11838f | 1010 | */ |
| mbed_official | 235:685d5f11838f | 1011 | /** |
| mbed_official | 235:685d5f11838f | 1012 | * @brief Enables dynamically FMC_NAND ECC feature. |
| mbed_official | 235:685d5f11838f | 1013 | * @param Device: Pointer to NAND device instance |
| mbed_official | 235:685d5f11838f | 1014 | * @param Bank: NAND bank number |
| mbed_official | 235:685d5f11838f | 1015 | * @retval HAL status |
| mbed_official | 235:685d5f11838f | 1016 | */ |
| mbed_official | 235:685d5f11838f | 1017 | HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank) |
| mbed_official | 235:685d5f11838f | 1018 | { |
| mbed_official | 235:685d5f11838f | 1019 | /* Check the parameters */ |
| mbed_official | 235:685d5f11838f | 1020 | assert_param(IS_FMC_NAND_DEVICE(Device)); |
| mbed_official | 235:685d5f11838f | 1021 | assert_param(IS_FMC_NAND_BANK(Bank)); |
| mbed_official | 235:685d5f11838f | 1022 | |
| mbed_official | 235:685d5f11838f | 1023 | /* Enable ECC feature */ |
| mbed_official | 235:685d5f11838f | 1024 | if(Bank == FMC_NAND_BANK2) |
| mbed_official | 235:685d5f11838f | 1025 | { |
| mbed_official | 235:685d5f11838f | 1026 | Device->PCR2 |= FMC_PCR2_ECCEN; |
| mbed_official | 235:685d5f11838f | 1027 | } |
| mbed_official | 235:685d5f11838f | 1028 | else |
| mbed_official | 235:685d5f11838f | 1029 | { |
| mbed_official | 235:685d5f11838f | 1030 | Device->PCR3 |= FMC_PCR3_ECCEN; |
| mbed_official | 235:685d5f11838f | 1031 | } |
| mbed_official | 235:685d5f11838f | 1032 | |
| mbed_official | 235:685d5f11838f | 1033 | return HAL_OK; |
| mbed_official | 235:685d5f11838f | 1034 | } |
| mbed_official | 235:685d5f11838f | 1035 | |
| mbed_official | 235:685d5f11838f | 1036 | /** |
| mbed_official | 235:685d5f11838f | 1037 | * @brief Disables dynamically FMC_NAND ECC feature. |
| mbed_official | 235:685d5f11838f | 1038 | * @param Device: Pointer to NAND device instance |
| mbed_official | 235:685d5f11838f | 1039 | * @param Bank: NAND bank number |
| mbed_official | 235:685d5f11838f | 1040 | * @retval HAL status |
| mbed_official | 235:685d5f11838f | 1041 | */ |
| mbed_official | 235:685d5f11838f | 1042 | HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank) |
| mbed_official | 235:685d5f11838f | 1043 | { |
| mbed_official | 235:685d5f11838f | 1044 | /* Check the parameters */ |
| mbed_official | 235:685d5f11838f | 1045 | assert_param(IS_FMC_NAND_DEVICE(Device)); |
| mbed_official | 235:685d5f11838f | 1046 | assert_param(IS_FMC_NAND_BANK(Bank)); |
| mbed_official | 235:685d5f11838f | 1047 | |
| mbed_official | 235:685d5f11838f | 1048 | /* Disable ECC feature */ |
| mbed_official | 235:685d5f11838f | 1049 | if(Bank == FMC_NAND_BANK2) |
| mbed_official | 235:685d5f11838f | 1050 | { |
| mbed_official | 235:685d5f11838f | 1051 | Device->PCR2 &= ~FMC_PCR2_ECCEN; |
| mbed_official | 235:685d5f11838f | 1052 | } |
| mbed_official | 235:685d5f11838f | 1053 | else |
| mbed_official | 235:685d5f11838f | 1054 | { |
| mbed_official | 235:685d5f11838f | 1055 | Device->PCR3 &= ~FMC_PCR3_ECCEN; |
| mbed_official | 235:685d5f11838f | 1056 | } |
| mbed_official | 235:685d5f11838f | 1057 | |
| mbed_official | 235:685d5f11838f | 1058 | return HAL_OK; |
| mbed_official | 235:685d5f11838f | 1059 | } |
| mbed_official | 235:685d5f11838f | 1060 | |
| mbed_official | 235:685d5f11838f | 1061 | /** |
| mbed_official | 235:685d5f11838f | 1062 | * @brief Disables dynamically FMC_NAND ECC feature. |
| mbed_official | 235:685d5f11838f | 1063 | * @param Device: Pointer to NAND device instance |
| mbed_official | 235:685d5f11838f | 1064 | * @param ECCval: Pointer to ECC value |
| mbed_official | 235:685d5f11838f | 1065 | * @param Bank: NAND bank number |
| mbed_official | 235:685d5f11838f | 1066 | * @param Timeout: Timeout wait value |
| mbed_official | 235:685d5f11838f | 1067 | * @retval HAL status |
| mbed_official | 235:685d5f11838f | 1068 | */ |
| mbed_official | 235:685d5f11838f | 1069 | HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout) |
| mbed_official | 235:685d5f11838f | 1070 | { |
| mbed_official | 235:685d5f11838f | 1071 | uint32_t tickstart = 0; |
| mbed_official | 235:685d5f11838f | 1072 | |
| mbed_official | 235:685d5f11838f | 1073 | /* Check the parameters */ |
| mbed_official | 235:685d5f11838f | 1074 | assert_param(IS_FMC_NAND_DEVICE(Device)); |
| mbed_official | 235:685d5f11838f | 1075 | assert_param(IS_FMC_NAND_BANK(Bank)); |
| mbed_official | 235:685d5f11838f | 1076 | |
| mbed_official | 235:685d5f11838f | 1077 | /* Get tick */ |
| mbed_official | 235:685d5f11838f | 1078 | tickstart = HAL_GetTick(); |
| mbed_official | 235:685d5f11838f | 1079 | |
| mbed_official | 532:fe11edbda85c | 1080 | /* Wait until FIFO is empty */ |
| mbed_official | 532:fe11edbda85c | 1081 | while(__FMC_NAND_GET_FLAG(Device, Bank, FMC_FLAG_FEMPT) == RESET) |
| mbed_official | 235:685d5f11838f | 1082 | { |
| mbed_official | 235:685d5f11838f | 1083 | /* Check for the Timeout */ |
| mbed_official | 235:685d5f11838f | 1084 | if(Timeout != HAL_MAX_DELAY) |
| mbed_official | 235:685d5f11838f | 1085 | { |
| mbed_official | 235:685d5f11838f | 1086 | if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) |
| mbed_official | 235:685d5f11838f | 1087 | { |
| mbed_official | 235:685d5f11838f | 1088 | return HAL_TIMEOUT; |
| mbed_official | 235:685d5f11838f | 1089 | } |
| mbed_official | 235:685d5f11838f | 1090 | } |
| mbed_official | 235:685d5f11838f | 1091 | } |
| mbed_official | 235:685d5f11838f | 1092 | |
| mbed_official | 235:685d5f11838f | 1093 | if(Bank == FMC_NAND_BANK2) |
| mbed_official | 235:685d5f11838f | 1094 | { |
| mbed_official | 235:685d5f11838f | 1095 | /* Get the ECCR2 register value */ |
| mbed_official | 235:685d5f11838f | 1096 | *ECCval = (uint32_t)Device->ECCR2; |
| mbed_official | 235:685d5f11838f | 1097 | } |
| mbed_official | 235:685d5f11838f | 1098 | else |
| mbed_official | 235:685d5f11838f | 1099 | { |
| mbed_official | 235:685d5f11838f | 1100 | /* Get the ECCR3 register value */ |
| mbed_official | 235:685d5f11838f | 1101 | *ECCval = (uint32_t)Device->ECCR3; |
| mbed_official | 235:685d5f11838f | 1102 | } |
| mbed_official | 235:685d5f11838f | 1103 | |
| mbed_official | 235:685d5f11838f | 1104 | return HAL_OK; |
| mbed_official | 235:685d5f11838f | 1105 | } |
| mbed_official | 235:685d5f11838f | 1106 | |
| mbed_official | 235:685d5f11838f | 1107 | /** |
| mbed_official | 235:685d5f11838f | 1108 | * @} |
| mbed_official | 235:685d5f11838f | 1109 | */ |
| mbed_official | 532:fe11edbda85c | 1110 | |
| mbed_official | 532:fe11edbda85c | 1111 | #endif /* defined(STM32F446xx) */ |
| mbed_official | 235:685d5f11838f | 1112 | /** |
| mbed_official | 235:685d5f11838f | 1113 | * @} |
| mbed_official | 235:685d5f11838f | 1114 | */ |
| mbed_official | 532:fe11edbda85c | 1115 | |
| mbed_official | 532:fe11edbda85c | 1116 | #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) |
| mbed_official | 532:fe11edbda85c | 1117 | /** @addtogroup FMC_LL_PCCARD |
| mbed_official | 235:685d5f11838f | 1118 | * @brief PCCARD Controller functions |
| mbed_official | 235:685d5f11838f | 1119 | * |
| mbed_official | 235:685d5f11838f | 1120 | @verbatim |
| mbed_official | 235:685d5f11838f | 1121 | ============================================================================== |
| mbed_official | 235:685d5f11838f | 1122 | ##### How to use PCCARD device driver ##### |
| mbed_official | 235:685d5f11838f | 1123 | ============================================================================== |
| mbed_official | 235:685d5f11838f | 1124 | [..] |
| mbed_official | 235:685d5f11838f | 1125 | This driver contains a set of APIs to interface with the FMC PCCARD bank in order |
| mbed_official | 235:685d5f11838f | 1126 | to run the PCCARD/compact flash external devices. |
| mbed_official | 235:685d5f11838f | 1127 | |
| mbed_official | 235:685d5f11838f | 1128 | (+) FMC PCCARD bank reset using the function FMC_PCCARD_DeInit() |
| mbed_official | 235:685d5f11838f | 1129 | (+) FMC PCCARD bank control configuration using the function FMC_PCCARD_Init() |
| mbed_official | 235:685d5f11838f | 1130 | (+) FMC PCCARD bank common space timing configuration using the function |
| mbed_official | 235:685d5f11838f | 1131 | FMC_PCCARD_CommonSpace_Timing_Init() |
| mbed_official | 235:685d5f11838f | 1132 | (+) FMC PCCARD bank attribute space timing configuration using the function |
| mbed_official | 235:685d5f11838f | 1133 | FMC_PCCARD_AttributeSpace_Timing_Init() |
| mbed_official | 235:685d5f11838f | 1134 | (+) FMC PCCARD bank IO space timing configuration using the function |
| mbed_official | 235:685d5f11838f | 1135 | FMC_PCCARD_IOSpace_Timing_Init() |
| mbed_official | 235:685d5f11838f | 1136 | @endverbatim |
| mbed_official | 235:685d5f11838f | 1137 | * @{ |
| mbed_official | 235:685d5f11838f | 1138 | */ |
| mbed_official | 235:685d5f11838f | 1139 | |
| mbed_official | 532:fe11edbda85c | 1140 | /** @addtogroup FMC_LL_PCCARD_Private_Functions_Group1 |
| mbed_official | 532:fe11edbda85c | 1141 | * @brief Initialization and Configuration functions |
| mbed_official | 532:fe11edbda85c | 1142 | * |
| mbed_official | 235:685d5f11838f | 1143 | @verbatim |
| mbed_official | 235:685d5f11838f | 1144 | ============================================================================== |
| mbed_official | 235:685d5f11838f | 1145 | ##### Initialization and de_initialization functions ##### |
| mbed_official | 235:685d5f11838f | 1146 | ============================================================================== |
| mbed_official | 235:685d5f11838f | 1147 | [..] |
| mbed_official | 235:685d5f11838f | 1148 | This section provides functions allowing to: |
| mbed_official | 235:685d5f11838f | 1149 | (+) Initialize and configure the FMC PCCARD interface |
| mbed_official | 235:685d5f11838f | 1150 | (+) De-initialize the FMC PCCARD interface |
| mbed_official | 235:685d5f11838f | 1151 | (+) Configure the FMC clock and associated GPIOs |
| mbed_official | 235:685d5f11838f | 1152 | |
| mbed_official | 235:685d5f11838f | 1153 | @endverbatim |
| mbed_official | 235:685d5f11838f | 1154 | * @{ |
| mbed_official | 235:685d5f11838f | 1155 | */ |
| mbed_official | 235:685d5f11838f | 1156 | |
| mbed_official | 235:685d5f11838f | 1157 | /** |
| mbed_official | 235:685d5f11838f | 1158 | * @brief Initializes the FMC_PCCARD device according to the specified |
| mbed_official | 235:685d5f11838f | 1159 | * control parameters in the FMC_PCCARD_HandleTypeDef |
| mbed_official | 235:685d5f11838f | 1160 | * @param Device: Pointer to PCCARD device instance |
| mbed_official | 235:685d5f11838f | 1161 | * @param Init: Pointer to PCCARD Initialization structure |
| mbed_official | 235:685d5f11838f | 1162 | * @retval HAL status |
| mbed_official | 235:685d5f11838f | 1163 | */ |
| mbed_official | 235:685d5f11838f | 1164 | HAL_StatusTypeDef FMC_PCCARD_Init(FMC_PCCARD_TypeDef *Device, FMC_PCCARD_InitTypeDef *Init) |
| mbed_official | 235:685d5f11838f | 1165 | { |
| mbed_official | 532:fe11edbda85c | 1166 | uint32_t tmpr = 0; |
| mbed_official | 532:fe11edbda85c | 1167 | |
| mbed_official | 235:685d5f11838f | 1168 | /* Check the parameters */ |
| mbed_official | 235:685d5f11838f | 1169 | assert_param(IS_FMC_PCCARD_DEVICE(Device)); |
| mbed_official | 235:685d5f11838f | 1170 | assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature)); |
| mbed_official | 235:685d5f11838f | 1171 | assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime)); |
| mbed_official | 235:685d5f11838f | 1172 | assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime)); |
| mbed_official | 235:685d5f11838f | 1173 | |
| mbed_official | 532:fe11edbda85c | 1174 | /* Get PCCARD control register value */ |
| mbed_official | 532:fe11edbda85c | 1175 | tmpr = Device->PCR4; |
| mbed_official | 532:fe11edbda85c | 1176 | |
| mbed_official | 532:fe11edbda85c | 1177 | /* Clear TAR, TCLR, PWAITEN and PWID bits */ |
| mbed_official | 532:fe11edbda85c | 1178 | tmpr &= ((uint32_t)~(FMC_PCR4_TAR | FMC_PCR4_TCLR | FMC_PCR4_PWAITEN | \ |
| mbed_official | 532:fe11edbda85c | 1179 | FMC_PCR4_PWID)); |
| mbed_official | 532:fe11edbda85c | 1180 | |
| mbed_official | 235:685d5f11838f | 1181 | /* Set FMC_PCCARD device control parameters */ |
| mbed_official | 532:fe11edbda85c | 1182 | tmpr |= (uint32_t)(Init->Waitfeature |\ |
| mbed_official | 532:fe11edbda85c | 1183 | FMC_NAND_PCC_MEM_BUS_WIDTH_16 |\ |
| mbed_official | 532:fe11edbda85c | 1184 | (Init->TCLRSetupTime << 9) |\ |
| mbed_official | 532:fe11edbda85c | 1185 | (Init->TARSetupTime << 13)); |
| mbed_official | 532:fe11edbda85c | 1186 | |
| mbed_official | 532:fe11edbda85c | 1187 | Device->PCR4 = tmpr; |
| mbed_official | 235:685d5f11838f | 1188 | |
| mbed_official | 235:685d5f11838f | 1189 | return HAL_OK; |
| mbed_official | 235:685d5f11838f | 1190 | } |
| mbed_official | 235:685d5f11838f | 1191 | |
| mbed_official | 235:685d5f11838f | 1192 | /** |
| mbed_official | 235:685d5f11838f | 1193 | * @brief Initializes the FMC_PCCARD Common space Timing according to the specified |
| mbed_official | 235:685d5f11838f | 1194 | * parameters in the FMC_NAND_PCC_TimingTypeDef |
| mbed_official | 235:685d5f11838f | 1195 | * @param Device: Pointer to PCCARD device instance |
| mbed_official | 235:685d5f11838f | 1196 | * @param Timing: Pointer to PCCARD timing structure |
| mbed_official | 235:685d5f11838f | 1197 | * @retval HAL status |
| mbed_official | 235:685d5f11838f | 1198 | */ |
| mbed_official | 235:685d5f11838f | 1199 | HAL_StatusTypeDef FMC_PCCARD_CommonSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing) |
| mbed_official | 235:685d5f11838f | 1200 | { |
| mbed_official | 532:fe11edbda85c | 1201 | uint32_t tmpr = 0; |
| mbed_official | 532:fe11edbda85c | 1202 | |
| mbed_official | 235:685d5f11838f | 1203 | /* Check the parameters */ |
| mbed_official | 235:685d5f11838f | 1204 | assert_param(IS_FMC_PCCARD_DEVICE(Device)); |
| mbed_official | 235:685d5f11838f | 1205 | assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime)); |
| mbed_official | 235:685d5f11838f | 1206 | assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime)); |
| mbed_official | 235:685d5f11838f | 1207 | assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime)); |
| mbed_official | 235:685d5f11838f | 1208 | assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime)); |
| mbed_official | 235:685d5f11838f | 1209 | |
| mbed_official | 532:fe11edbda85c | 1210 | /* Get PCCARD common space timing register value */ |
| mbed_official | 532:fe11edbda85c | 1211 | tmpr = Device->PMEM4; |
| mbed_official | 532:fe11edbda85c | 1212 | |
| mbed_official | 532:fe11edbda85c | 1213 | /* Clear MEMSETx, MEMWAITx, MEMHOLDx and MEMHIZx bits */ |
| mbed_official | 532:fe11edbda85c | 1214 | tmpr &= ((uint32_t)~(FMC_PMEM4_MEMSET4 | FMC_PMEM4_MEMWAIT4 | FMC_PMEM4_MEMHOLD4 | \ |
| mbed_official | 532:fe11edbda85c | 1215 | FMC_PMEM4_MEMHIZ4)); |
| mbed_official | 235:685d5f11838f | 1216 | /* Set PCCARD timing parameters */ |
| mbed_official | 532:fe11edbda85c | 1217 | tmpr |= (uint32_t)(Timing->SetupTime |\ |
| mbed_official | 532:fe11edbda85c | 1218 | ((Timing->WaitSetupTime) << 8) |\ |
| mbed_official | 532:fe11edbda85c | 1219 | ((Timing->HoldSetupTime) << 16) |\ |
| mbed_official | 532:fe11edbda85c | 1220 | ((Timing->HiZSetupTime) << 24)); |
| mbed_official | 235:685d5f11838f | 1221 | |
| mbed_official | 532:fe11edbda85c | 1222 | Device->PMEM4 = tmpr; |
| mbed_official | 532:fe11edbda85c | 1223 | |
| mbed_official | 235:685d5f11838f | 1224 | return HAL_OK; |
| mbed_official | 235:685d5f11838f | 1225 | } |
| mbed_official | 235:685d5f11838f | 1226 | |
| mbed_official | 235:685d5f11838f | 1227 | /** |
| mbed_official | 235:685d5f11838f | 1228 | * @brief Initializes the FMC_PCCARD Attribute space Timing according to the specified |
| mbed_official | 235:685d5f11838f | 1229 | * parameters in the FMC_NAND_PCC_TimingTypeDef |
| mbed_official | 235:685d5f11838f | 1230 | * @param Device: Pointer to PCCARD device instance |
| mbed_official | 235:685d5f11838f | 1231 | * @param Timing: Pointer to PCCARD timing structure |
| mbed_official | 235:685d5f11838f | 1232 | * @retval HAL status |
| mbed_official | 235:685d5f11838f | 1233 | */ |
| mbed_official | 235:685d5f11838f | 1234 | HAL_StatusTypeDef FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing) |
| mbed_official | 235:685d5f11838f | 1235 | { |
| mbed_official | 532:fe11edbda85c | 1236 | uint32_t tmpr = 0; |
| mbed_official | 532:fe11edbda85c | 1237 | |
| mbed_official | 235:685d5f11838f | 1238 | /* Check the parameters */ |
| mbed_official | 235:685d5f11838f | 1239 | assert_param(IS_FMC_PCCARD_DEVICE(Device)); |
| mbed_official | 235:685d5f11838f | 1240 | assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime)); |
| mbed_official | 235:685d5f11838f | 1241 | assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime)); |
| mbed_official | 235:685d5f11838f | 1242 | assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime)); |
| mbed_official | 235:685d5f11838f | 1243 | assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime)); |
| mbed_official | 235:685d5f11838f | 1244 | |
| mbed_official | 532:fe11edbda85c | 1245 | /* Get PCCARD timing parameters */ |
| mbed_official | 532:fe11edbda85c | 1246 | tmpr = Device->PATT4; |
| mbed_official | 532:fe11edbda85c | 1247 | |
| mbed_official | 532:fe11edbda85c | 1248 | /* Clear ATTSETx, ATTWAITx, ATTHOLDx and ATTHIZx bits */ |
| mbed_official | 532:fe11edbda85c | 1249 | tmpr &= ((uint32_t)~(FMC_PATT4_ATTSET4 | FMC_PATT4_ATTWAIT4 | FMC_PATT4_ATTHOLD4 | \ |
| mbed_official | 532:fe11edbda85c | 1250 | FMC_PATT4_ATTHIZ4)); |
| mbed_official | 532:fe11edbda85c | 1251 | |
| mbed_official | 235:685d5f11838f | 1252 | /* Set PCCARD timing parameters */ |
| mbed_official | 532:fe11edbda85c | 1253 | tmpr |= (uint32_t)(Timing->SetupTime |\ |
| mbed_official | 532:fe11edbda85c | 1254 | ((Timing->WaitSetupTime) << 8) |\ |
| mbed_official | 532:fe11edbda85c | 1255 | ((Timing->HoldSetupTime) << 16) |\ |
| mbed_official | 532:fe11edbda85c | 1256 | ((Timing->HiZSetupTime) << 24)); |
| mbed_official | 532:fe11edbda85c | 1257 | Device->PATT4 = tmpr; |
| mbed_official | 532:fe11edbda85c | 1258 | |
| mbed_official | 235:685d5f11838f | 1259 | return HAL_OK; |
| mbed_official | 235:685d5f11838f | 1260 | } |
| mbed_official | 235:685d5f11838f | 1261 | |
| mbed_official | 235:685d5f11838f | 1262 | /** |
| mbed_official | 235:685d5f11838f | 1263 | * @brief Initializes the FMC_PCCARD IO space Timing according to the specified |
| mbed_official | 235:685d5f11838f | 1264 | * parameters in the FMC_NAND_PCC_TimingTypeDef |
| mbed_official | 235:685d5f11838f | 1265 | * @param Device: Pointer to PCCARD device instance |
| mbed_official | 235:685d5f11838f | 1266 | * @param Timing: Pointer to PCCARD timing structure |
| mbed_official | 235:685d5f11838f | 1267 | * @retval HAL status |
| mbed_official | 235:685d5f11838f | 1268 | */ |
| mbed_official | 235:685d5f11838f | 1269 | HAL_StatusTypeDef FMC_PCCARD_IOSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing) |
| mbed_official | 235:685d5f11838f | 1270 | { |
| mbed_official | 532:fe11edbda85c | 1271 | uint32_t tmpr = 0; |
| mbed_official | 532:fe11edbda85c | 1272 | |
| mbed_official | 235:685d5f11838f | 1273 | /* Check the parameters */ |
| mbed_official | 235:685d5f11838f | 1274 | assert_param(IS_FMC_PCCARD_DEVICE(Device)); |
| mbed_official | 235:685d5f11838f | 1275 | assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime)); |
| mbed_official | 235:685d5f11838f | 1276 | assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime)); |
| mbed_official | 235:685d5f11838f | 1277 | assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime)); |
| mbed_official | 235:685d5f11838f | 1278 | assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime)); |
| mbed_official | 235:685d5f11838f | 1279 | |
| mbed_official | 532:fe11edbda85c | 1280 | /* Get FMC_PCCARD device timing parameters */ |
| mbed_official | 532:fe11edbda85c | 1281 | tmpr = Device->PIO4; |
| mbed_official | 532:fe11edbda85c | 1282 | |
| mbed_official | 532:fe11edbda85c | 1283 | /* Clear IOSET4, IOWAIT4, IOHOLD4 and IOHIZ4 bits */ |
| mbed_official | 532:fe11edbda85c | 1284 | tmpr &= ((uint32_t)~(FMC_PIO4_IOSET4 | FMC_PIO4_IOWAIT4 | FMC_PIO4_IOHOLD4 | \ |
| mbed_official | 532:fe11edbda85c | 1285 | FMC_PIO4_IOHIZ4)); |
| mbed_official | 532:fe11edbda85c | 1286 | |
| mbed_official | 235:685d5f11838f | 1287 | /* Set FMC_PCCARD device timing parameters */ |
| mbed_official | 532:fe11edbda85c | 1288 | tmpr |= (uint32_t)(Timing->SetupTime |\ |
| mbed_official | 532:fe11edbda85c | 1289 | ((Timing->WaitSetupTime) << 8) |\ |
| mbed_official | 532:fe11edbda85c | 1290 | ((Timing->HoldSetupTime) << 16) |\ |
| mbed_official | 532:fe11edbda85c | 1291 | ((Timing->HiZSetupTime) << 24)); |
| mbed_official | 235:685d5f11838f | 1292 | |
| mbed_official | 532:fe11edbda85c | 1293 | Device->PIO4 = tmpr; |
| mbed_official | 532:fe11edbda85c | 1294 | |
| mbed_official | 235:685d5f11838f | 1295 | return HAL_OK; |
| mbed_official | 235:685d5f11838f | 1296 | } |
| mbed_official | 235:685d5f11838f | 1297 | |
| mbed_official | 235:685d5f11838f | 1298 | /** |
| mbed_official | 235:685d5f11838f | 1299 | * @brief DeInitializes the FMC_PCCARD device |
| mbed_official | 235:685d5f11838f | 1300 | * @param Device: Pointer to PCCARD device instance |
| mbed_official | 235:685d5f11838f | 1301 | * @retval HAL status |
| mbed_official | 235:685d5f11838f | 1302 | */ |
| mbed_official | 235:685d5f11838f | 1303 | HAL_StatusTypeDef FMC_PCCARD_DeInit(FMC_PCCARD_TypeDef *Device) |
| mbed_official | 235:685d5f11838f | 1304 | { |
| mbed_official | 235:685d5f11838f | 1305 | /* Check the parameters */ |
| mbed_official | 235:685d5f11838f | 1306 | assert_param(IS_FMC_PCCARD_DEVICE(Device)); |
| mbed_official | 235:685d5f11838f | 1307 | |
| mbed_official | 235:685d5f11838f | 1308 | /* Disable the FMC_PCCARD device */ |
| mbed_official | 235:685d5f11838f | 1309 | __FMC_PCCARD_DISABLE(Device); |
| mbed_official | 235:685d5f11838f | 1310 | |
| mbed_official | 235:685d5f11838f | 1311 | /* De-initialize the FMC_PCCARD device */ |
| mbed_official | 235:685d5f11838f | 1312 | Device->PCR4 = 0x00000018; |
| mbed_official | 235:685d5f11838f | 1313 | Device->SR4 = 0x00000000; |
| mbed_official | 235:685d5f11838f | 1314 | Device->PMEM4 = 0xFCFCFCFC; |
| mbed_official | 235:685d5f11838f | 1315 | Device->PATT4 = 0xFCFCFCFC; |
| mbed_official | 235:685d5f11838f | 1316 | Device->PIO4 = 0xFCFCFCFC; |
| mbed_official | 235:685d5f11838f | 1317 | |
| mbed_official | 235:685d5f11838f | 1318 | return HAL_OK; |
| mbed_official | 235:685d5f11838f | 1319 | } |
| mbed_official | 235:685d5f11838f | 1320 | |
| mbed_official | 235:685d5f11838f | 1321 | /** |
| mbed_official | 235:685d5f11838f | 1322 | * @} |
| mbed_official | 235:685d5f11838f | 1323 | */ |
| mbed_official | 532:fe11edbda85c | 1324 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ |
| mbed_official | 235:685d5f11838f | 1325 | |
| mbed_official | 235:685d5f11838f | 1326 | |
| mbed_official | 532:fe11edbda85c | 1327 | /** @addtogroup FMC_LL_SDRAM |
| mbed_official | 235:685d5f11838f | 1328 | * @brief SDRAM Controller functions |
| mbed_official | 235:685d5f11838f | 1329 | * |
| mbed_official | 235:685d5f11838f | 1330 | @verbatim |
| mbed_official | 235:685d5f11838f | 1331 | ============================================================================== |
| mbed_official | 235:685d5f11838f | 1332 | ##### How to use SDRAM device driver ##### |
| mbed_official | 235:685d5f11838f | 1333 | ============================================================================== |
| mbed_official | 235:685d5f11838f | 1334 | [..] |
| mbed_official | 235:685d5f11838f | 1335 | This driver contains a set of APIs to interface with the FMC SDRAM banks in order |
| mbed_official | 235:685d5f11838f | 1336 | to run the SDRAM external devices. |
| mbed_official | 235:685d5f11838f | 1337 | |
| mbed_official | 235:685d5f11838f | 1338 | (+) FMC SDRAM bank reset using the function FMC_SDRAM_DeInit() |
| mbed_official | 235:685d5f11838f | 1339 | (+) FMC SDRAM bank control configuration using the function FMC_SDRAM_Init() |
| mbed_official | 235:685d5f11838f | 1340 | (+) FMC SDRAM bank timing configuration using the function FMC_SDRAM_Timing_Init() |
| mbed_official | 235:685d5f11838f | 1341 | (+) FMC SDRAM bank enable/disable write operation using the functions |
| mbed_official | 235:685d5f11838f | 1342 | FMC_SDRAM_WriteOperation_Enable()/FMC_SDRAM_WriteOperation_Disable() |
| mbed_official | 235:685d5f11838f | 1343 | (+) FMC SDRAM bank send command using the function FMC_SDRAM_SendCommand() |
| mbed_official | 235:685d5f11838f | 1344 | |
| mbed_official | 235:685d5f11838f | 1345 | @endverbatim |
| mbed_official | 235:685d5f11838f | 1346 | * @{ |
| mbed_official | 235:685d5f11838f | 1347 | */ |
| mbed_official | 235:685d5f11838f | 1348 | |
| mbed_official | 532:fe11edbda85c | 1349 | /** @addtogroup FMC_LL_SDRAM_Private_Functions_Group1 |
| mbed_official | 532:fe11edbda85c | 1350 | * @brief Initialization and Configuration functions |
| mbed_official | 532:fe11edbda85c | 1351 | * |
| mbed_official | 235:685d5f11838f | 1352 | @verbatim |
| mbed_official | 235:685d5f11838f | 1353 | ============================================================================== |
| mbed_official | 235:685d5f11838f | 1354 | ##### Initialization and de_initialization functions ##### |
| mbed_official | 235:685d5f11838f | 1355 | ============================================================================== |
| mbed_official | 235:685d5f11838f | 1356 | [..] |
| mbed_official | 235:685d5f11838f | 1357 | This section provides functions allowing to: |
| mbed_official | 235:685d5f11838f | 1358 | (+) Initialize and configure the FMC SDRAM interface |
| mbed_official | 235:685d5f11838f | 1359 | (+) De-initialize the FMC SDRAM interface |
| mbed_official | 235:685d5f11838f | 1360 | (+) Configure the FMC clock and associated GPIOs |
| mbed_official | 235:685d5f11838f | 1361 | |
| mbed_official | 235:685d5f11838f | 1362 | @endverbatim |
| mbed_official | 235:685d5f11838f | 1363 | * @{ |
| mbed_official | 235:685d5f11838f | 1364 | */ |
| mbed_official | 235:685d5f11838f | 1365 | |
| mbed_official | 235:685d5f11838f | 1366 | /** |
| mbed_official | 235:685d5f11838f | 1367 | * @brief Initializes the FMC_SDRAM device according to the specified |
| mbed_official | 235:685d5f11838f | 1368 | * control parameters in the FMC_SDRAM_InitTypeDef |
| mbed_official | 235:685d5f11838f | 1369 | * @param Device: Pointer to SDRAM device instance |
| mbed_official | 235:685d5f11838f | 1370 | * @param Init: Pointer to SDRAM Initialization structure |
| mbed_official | 235:685d5f11838f | 1371 | * @retval HAL status |
| mbed_official | 235:685d5f11838f | 1372 | */ |
| mbed_official | 235:685d5f11838f | 1373 | HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init) |
| mbed_official | 235:685d5f11838f | 1374 | { |
| mbed_official | 235:685d5f11838f | 1375 | uint32_t tmpr1 = 0; |
| mbed_official | 235:685d5f11838f | 1376 | uint32_t tmpr2 = 0; |
| mbed_official | 235:685d5f11838f | 1377 | |
| mbed_official | 235:685d5f11838f | 1378 | /* Check the parameters */ |
| mbed_official | 235:685d5f11838f | 1379 | assert_param(IS_FMC_SDRAM_DEVICE(Device)); |
| mbed_official | 235:685d5f11838f | 1380 | assert_param(IS_FMC_SDRAM_BANK(Init->SDBank)); |
| mbed_official | 235:685d5f11838f | 1381 | assert_param(IS_FMC_COLUMNBITS_NUMBER(Init->ColumnBitsNumber)); |
| mbed_official | 235:685d5f11838f | 1382 | assert_param(IS_FMC_ROWBITS_NUMBER(Init->RowBitsNumber)); |
| mbed_official | 235:685d5f11838f | 1383 | assert_param(IS_FMC_SDMEMORY_WIDTH(Init->MemoryDataWidth)); |
| mbed_official | 235:685d5f11838f | 1384 | assert_param(IS_FMC_INTERNALBANK_NUMBER(Init->InternalBankNumber)); |
| mbed_official | 235:685d5f11838f | 1385 | assert_param(IS_FMC_CAS_LATENCY(Init->CASLatency)); |
| mbed_official | 235:685d5f11838f | 1386 | assert_param(IS_FMC_WRITE_PROTECTION(Init->WriteProtection)); |
| mbed_official | 235:685d5f11838f | 1387 | assert_param(IS_FMC_SDCLOCK_PERIOD(Init->SDClockPeriod)); |
| mbed_official | 235:685d5f11838f | 1388 | assert_param(IS_FMC_READ_BURST(Init->ReadBurst)); |
| mbed_official | 235:685d5f11838f | 1389 | assert_param(IS_FMC_READPIPE_DELAY(Init->ReadPipeDelay)); |
| mbed_official | 235:685d5f11838f | 1390 | |
| mbed_official | 235:685d5f11838f | 1391 | /* Set SDRAM bank configuration parameters */ |
| mbed_official | 235:685d5f11838f | 1392 | if (Init->SDBank != FMC_SDRAM_BANK2) |
| mbed_official | 532:fe11edbda85c | 1393 | { |
| mbed_official | 532:fe11edbda85c | 1394 | tmpr1 = Device->SDCR[FMC_SDRAM_BANK1]; |
| mbed_official | 532:fe11edbda85c | 1395 | |
| mbed_official | 532:fe11edbda85c | 1396 | /* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */ |
| mbed_official | 532:fe11edbda85c | 1397 | tmpr1 &= ((uint32_t)~(FMC_SDCR1_NC | FMC_SDCR1_NR | FMC_SDCR1_MWID | \ |
| mbed_official | 532:fe11edbda85c | 1398 | FMC_SDCR1_NB | FMC_SDCR1_CAS | FMC_SDCR1_WP | \ |
| mbed_official | 532:fe11edbda85c | 1399 | FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE)); |
| mbed_official | 532:fe11edbda85c | 1400 | |
| mbed_official | 532:fe11edbda85c | 1401 | |
| mbed_official | 532:fe11edbda85c | 1402 | tmpr1 |= (uint32_t)(Init->ColumnBitsNumber |\ |
| mbed_official | 235:685d5f11838f | 1403 | Init->RowBitsNumber |\ |
| mbed_official | 235:685d5f11838f | 1404 | Init->MemoryDataWidth |\ |
| mbed_official | 235:685d5f11838f | 1405 | Init->InternalBankNumber |\ |
| mbed_official | 235:685d5f11838f | 1406 | Init->CASLatency |\ |
| mbed_official | 235:685d5f11838f | 1407 | Init->WriteProtection |\ |
| mbed_official | 235:685d5f11838f | 1408 | Init->SDClockPeriod |\ |
| mbed_official | 235:685d5f11838f | 1409 | Init->ReadBurst |\ |
| mbed_official | 235:685d5f11838f | 1410 | Init->ReadPipeDelay |
| mbed_official | 532:fe11edbda85c | 1411 | ); |
| mbed_official | 532:fe11edbda85c | 1412 | Device->SDCR[FMC_SDRAM_BANK1] = tmpr1; |
| mbed_official | 235:685d5f11838f | 1413 | } |
| mbed_official | 235:685d5f11838f | 1414 | else /* FMC_Bank2_SDRAM */ |
| mbed_official | 235:685d5f11838f | 1415 | { |
| mbed_official | 532:fe11edbda85c | 1416 | tmpr1 = Device->SDCR[FMC_SDRAM_BANK1]; |
| mbed_official | 532:fe11edbda85c | 1417 | |
| mbed_official | 532:fe11edbda85c | 1418 | /* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */ |
| mbed_official | 532:fe11edbda85c | 1419 | tmpr1 &= ((uint32_t)~(FMC_SDCR1_NC | FMC_SDCR1_NR | FMC_SDCR1_MWID | \ |
| mbed_official | 532:fe11edbda85c | 1420 | FMC_SDCR1_NB | FMC_SDCR1_CAS | FMC_SDCR1_WP | \ |
| mbed_official | 532:fe11edbda85c | 1421 | FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE)); |
| mbed_official | 532:fe11edbda85c | 1422 | |
| mbed_official | 532:fe11edbda85c | 1423 | tmpr1 |= (uint32_t)(Init->SDClockPeriod |\ |
| mbed_official | 532:fe11edbda85c | 1424 | Init->ReadBurst |\ |
| mbed_official | 532:fe11edbda85c | 1425 | Init->ReadPipeDelay); |
| mbed_official | 532:fe11edbda85c | 1426 | |
| mbed_official | 532:fe11edbda85c | 1427 | tmpr2 = Device->SDCR[FMC_SDRAM_BANK2]; |
| mbed_official | 532:fe11edbda85c | 1428 | |
| mbed_official | 532:fe11edbda85c | 1429 | /* Clear NC, NR, MWID, NB, CAS, WP, SDCLK, RBURST, and RPIPE bits */ |
| mbed_official | 532:fe11edbda85c | 1430 | tmpr2 &= ((uint32_t)~(FMC_SDCR1_NC | FMC_SDCR1_NR | FMC_SDCR1_MWID | \ |
| mbed_official | 532:fe11edbda85c | 1431 | FMC_SDCR1_NB | FMC_SDCR1_CAS | FMC_SDCR1_WP | \ |
| mbed_official | 532:fe11edbda85c | 1432 | FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | FMC_SDCR1_RPIPE)); |
| mbed_official | 235:685d5f11838f | 1433 | |
| mbed_official | 532:fe11edbda85c | 1434 | tmpr2 |= (uint32_t)(Init->ColumnBitsNumber |\ |
| mbed_official | 235:685d5f11838f | 1435 | Init->RowBitsNumber |\ |
| mbed_official | 235:685d5f11838f | 1436 | Init->MemoryDataWidth |\ |
| mbed_official | 235:685d5f11838f | 1437 | Init->InternalBankNumber |\ |
| mbed_official | 235:685d5f11838f | 1438 | Init->CASLatency |\ |
| mbed_official | 532:fe11edbda85c | 1439 | Init->WriteProtection); |
| mbed_official | 532:fe11edbda85c | 1440 | |
| mbed_official | 235:685d5f11838f | 1441 | Device->SDCR[FMC_SDRAM_BANK1] = tmpr1; |
| mbed_official | 235:685d5f11838f | 1442 | Device->SDCR[FMC_SDRAM_BANK2] = tmpr2; |
| mbed_official | 235:685d5f11838f | 1443 | } |
| mbed_official | 235:685d5f11838f | 1444 | |
| mbed_official | 235:685d5f11838f | 1445 | return HAL_OK; |
| mbed_official | 235:685d5f11838f | 1446 | } |
| mbed_official | 235:685d5f11838f | 1447 | |
| mbed_official | 235:685d5f11838f | 1448 | /** |
| mbed_official | 235:685d5f11838f | 1449 | * @brief Initializes the FMC_SDRAM device timing according to the specified |
| mbed_official | 235:685d5f11838f | 1450 | * parameters in the FMC_SDRAM_TimingTypeDef |
| mbed_official | 235:685d5f11838f | 1451 | * @param Device: Pointer to SDRAM device instance |
| mbed_official | 235:685d5f11838f | 1452 | * @param Timing: Pointer to SDRAM Timing structure |
| mbed_official | 235:685d5f11838f | 1453 | * @param Bank: SDRAM bank number |
| mbed_official | 235:685d5f11838f | 1454 | * @retval HAL status |
| mbed_official | 235:685d5f11838f | 1455 | */ |
| mbed_official | 235:685d5f11838f | 1456 | HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank) |
| mbed_official | 235:685d5f11838f | 1457 | { |
| mbed_official | 235:685d5f11838f | 1458 | uint32_t tmpr1 = 0; |
| mbed_official | 235:685d5f11838f | 1459 | uint32_t tmpr2 = 0; |
| mbed_official | 235:685d5f11838f | 1460 | |
| mbed_official | 235:685d5f11838f | 1461 | /* Check the parameters */ |
| mbed_official | 235:685d5f11838f | 1462 | assert_param(IS_FMC_SDRAM_DEVICE(Device)); |
| mbed_official | 235:685d5f11838f | 1463 | assert_param(IS_FMC_LOADTOACTIVE_DELAY(Timing->LoadToActiveDelay)); |
| mbed_official | 235:685d5f11838f | 1464 | assert_param(IS_FMC_EXITSELFREFRESH_DELAY(Timing->ExitSelfRefreshDelay)); |
| mbed_official | 235:685d5f11838f | 1465 | assert_param(IS_FMC_SELFREFRESH_TIME(Timing->SelfRefreshTime)); |
| mbed_official | 235:685d5f11838f | 1466 | assert_param(IS_FMC_ROWCYCLE_DELAY(Timing->RowCycleDelay)); |
| mbed_official | 235:685d5f11838f | 1467 | assert_param(IS_FMC_WRITE_RECOVERY_TIME(Timing->WriteRecoveryTime)); |
| mbed_official | 235:685d5f11838f | 1468 | assert_param(IS_FMC_RP_DELAY(Timing->RPDelay)); |
| mbed_official | 235:685d5f11838f | 1469 | assert_param(IS_FMC_RCD_DELAY(Timing->RCDDelay)); |
| mbed_official | 235:685d5f11838f | 1470 | assert_param(IS_FMC_SDRAM_BANK(Bank)); |
| mbed_official | 235:685d5f11838f | 1471 | |
| mbed_official | 235:685d5f11838f | 1472 | /* Set SDRAM device timing parameters */ |
| mbed_official | 235:685d5f11838f | 1473 | if (Bank != FMC_SDRAM_BANK2) |
| mbed_official | 532:fe11edbda85c | 1474 | { |
| mbed_official | 532:fe11edbda85c | 1475 | tmpr1 = Device->SDTR[FMC_SDRAM_BANK1]; |
| mbed_official | 532:fe11edbda85c | 1476 | |
| mbed_official | 532:fe11edbda85c | 1477 | /* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */ |
| mbed_official | 532:fe11edbda85c | 1478 | tmpr1 &= ((uint32_t)~(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \ |
| mbed_official | 532:fe11edbda85c | 1479 | FMC_SDTR1_TRC | FMC_SDTR1_TWR | FMC_SDTR1_TRP | \ |
| mbed_official | 532:fe11edbda85c | 1480 | FMC_SDTR1_TRCD)); |
| mbed_official | 532:fe11edbda85c | 1481 | |
| mbed_official | 532:fe11edbda85c | 1482 | tmpr1 |= (uint32_t)(((Timing->LoadToActiveDelay)-1) |\ |
| mbed_official | 532:fe11edbda85c | 1483 | (((Timing->ExitSelfRefreshDelay)-1) << 4) |\ |
| mbed_official | 532:fe11edbda85c | 1484 | (((Timing->SelfRefreshTime)-1) << 8) |\ |
| mbed_official | 532:fe11edbda85c | 1485 | (((Timing->RowCycleDelay)-1) << 12) |\ |
| mbed_official | 532:fe11edbda85c | 1486 | (((Timing->WriteRecoveryTime)-1) <<16) |\ |
| mbed_official | 532:fe11edbda85c | 1487 | (((Timing->RPDelay)-1) << 20) |\ |
| mbed_official | 532:fe11edbda85c | 1488 | (((Timing->RCDDelay)-1) << 24)); |
| mbed_official | 532:fe11edbda85c | 1489 | Device->SDTR[FMC_SDRAM_BANK1] = tmpr1; |
| mbed_official | 235:685d5f11838f | 1490 | } |
| mbed_official | 235:685d5f11838f | 1491 | else /* FMC_Bank2_SDRAM */ |
| mbed_official | 235:685d5f11838f | 1492 | { |
| mbed_official | 532:fe11edbda85c | 1493 | tmpr1 = Device->SDTR[FMC_SDRAM_BANK2]; |
| mbed_official | 532:fe11edbda85c | 1494 | |
| mbed_official | 532:fe11edbda85c | 1495 | /* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */ |
| mbed_official | 532:fe11edbda85c | 1496 | tmpr1 &= ((uint32_t)~(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \ |
| mbed_official | 532:fe11edbda85c | 1497 | FMC_SDTR1_TRC | FMC_SDTR1_TWR | FMC_SDTR1_TRP | \ |
| mbed_official | 532:fe11edbda85c | 1498 | FMC_SDTR1_TRCD)); |
| mbed_official | 532:fe11edbda85c | 1499 | |
| mbed_official | 532:fe11edbda85c | 1500 | tmpr1 |= (uint32_t)(((Timing->LoadToActiveDelay)-1) |\ |
| mbed_official | 235:685d5f11838f | 1501 | (((Timing->ExitSelfRefreshDelay)-1) << 4) |\ |
| mbed_official | 235:685d5f11838f | 1502 | (((Timing->SelfRefreshTime)-1) << 8) |\ |
| mbed_official | 235:685d5f11838f | 1503 | (((Timing->WriteRecoveryTime)-1) <<16) |\ |
| mbed_official | 532:fe11edbda85c | 1504 | (((Timing->RCDDelay)-1) << 24)); |
| mbed_official | 532:fe11edbda85c | 1505 | |
| mbed_official | 532:fe11edbda85c | 1506 | tmpr2 = Device->SDTR[FMC_SDRAM_BANK1]; |
| mbed_official | 532:fe11edbda85c | 1507 | |
| mbed_official | 532:fe11edbda85c | 1508 | /* Clear TMRD, TXSR, TRAS, TRC, TWR, TRP and TRCD bits */ |
| mbed_official | 532:fe11edbda85c | 1509 | tmpr2 &= ((uint32_t)~(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | FMC_SDTR1_TRAS | \ |
| mbed_official | 532:fe11edbda85c | 1510 | FMC_SDTR1_TRC | FMC_SDTR1_TWR | FMC_SDTR1_TRP | \ |
| mbed_official | 532:fe11edbda85c | 1511 | FMC_SDTR1_TRCD)); |
| mbed_official | 532:fe11edbda85c | 1512 | tmpr2 |= (uint32_t)((((Timing->RowCycleDelay)-1) << 12) |\ |
| mbed_official | 532:fe11edbda85c | 1513 | (((Timing->RPDelay)-1) << 20)); |
| mbed_official | 235:685d5f11838f | 1514 | |
| mbed_official | 235:685d5f11838f | 1515 | Device->SDTR[FMC_SDRAM_BANK2] = tmpr1; |
| mbed_official | 235:685d5f11838f | 1516 | Device->SDTR[FMC_SDRAM_BANK1] = tmpr2; |
| mbed_official | 235:685d5f11838f | 1517 | } |
| mbed_official | 235:685d5f11838f | 1518 | |
| mbed_official | 235:685d5f11838f | 1519 | return HAL_OK; |
| mbed_official | 235:685d5f11838f | 1520 | } |
| mbed_official | 235:685d5f11838f | 1521 | |
| mbed_official | 235:685d5f11838f | 1522 | /** |
| mbed_official | 235:685d5f11838f | 1523 | * @brief DeInitializes the FMC_SDRAM peripheral |
| mbed_official | 235:685d5f11838f | 1524 | * @param Device: Pointer to SDRAM device instance |
| mbed_official | 235:685d5f11838f | 1525 | * @retval HAL status |
| mbed_official | 235:685d5f11838f | 1526 | */ |
| mbed_official | 235:685d5f11838f | 1527 | HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank) |
| mbed_official | 235:685d5f11838f | 1528 | { |
| mbed_official | 235:685d5f11838f | 1529 | /* Check the parameters */ |
| mbed_official | 235:685d5f11838f | 1530 | assert_param(IS_FMC_SDRAM_DEVICE(Device)); |
| mbed_official | 235:685d5f11838f | 1531 | assert_param(IS_FMC_SDRAM_BANK(Bank)); |
| mbed_official | 235:685d5f11838f | 1532 | |
| mbed_official | 235:685d5f11838f | 1533 | /* De-initialize the SDRAM device */ |
| mbed_official | 235:685d5f11838f | 1534 | Device->SDCR[Bank] = 0x000002D0; |
| mbed_official | 235:685d5f11838f | 1535 | Device->SDTR[Bank] = 0x0FFFFFFF; |
| mbed_official | 235:685d5f11838f | 1536 | Device->SDCMR = 0x00000000; |
| mbed_official | 235:685d5f11838f | 1537 | Device->SDRTR = 0x00000000; |
| mbed_official | 235:685d5f11838f | 1538 | Device->SDSR = 0x00000000; |
| mbed_official | 235:685d5f11838f | 1539 | |
| mbed_official | 235:685d5f11838f | 1540 | return HAL_OK; |
| mbed_official | 235:685d5f11838f | 1541 | } |
| mbed_official | 235:685d5f11838f | 1542 | |
| mbed_official | 235:685d5f11838f | 1543 | /** |
| mbed_official | 235:685d5f11838f | 1544 | * @} |
| mbed_official | 235:685d5f11838f | 1545 | */ |
| mbed_official | 235:685d5f11838f | 1546 | |
| mbed_official | 532:fe11edbda85c | 1547 | /** @addtogroup FMC_LL_SDRAMPrivate_Functions_Group2 |
| mbed_official | 532:fe11edbda85c | 1548 | * @brief management functions |
| mbed_official | 532:fe11edbda85c | 1549 | * |
| mbed_official | 235:685d5f11838f | 1550 | @verbatim |
| mbed_official | 235:685d5f11838f | 1551 | ============================================================================== |
| mbed_official | 235:685d5f11838f | 1552 | ##### FMC_SDRAM Control functions ##### |
| mbed_official | 235:685d5f11838f | 1553 | ============================================================================== |
| mbed_official | 235:685d5f11838f | 1554 | [..] |
| mbed_official | 235:685d5f11838f | 1555 | This subsection provides a set of functions allowing to control dynamically |
| mbed_official | 235:685d5f11838f | 1556 | the FMC SDRAM interface. |
| mbed_official | 235:685d5f11838f | 1557 | |
| mbed_official | 235:685d5f11838f | 1558 | @endverbatim |
| mbed_official | 235:685d5f11838f | 1559 | * @{ |
| mbed_official | 235:685d5f11838f | 1560 | */ |
| mbed_official | 235:685d5f11838f | 1561 | /** |
| mbed_official | 235:685d5f11838f | 1562 | * @brief Enables dynamically FMC_SDRAM write protection. |
| mbed_official | 235:685d5f11838f | 1563 | * @param Device: Pointer to SDRAM device instance |
| mbed_official | 235:685d5f11838f | 1564 | * @param Bank: SDRAM bank number |
| mbed_official | 235:685d5f11838f | 1565 | * @retval HAL status |
| mbed_official | 235:685d5f11838f | 1566 | */ |
| mbed_official | 235:685d5f11838f | 1567 | HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank) |
| mbed_official | 235:685d5f11838f | 1568 | { |
| mbed_official | 235:685d5f11838f | 1569 | /* Check the parameters */ |
| mbed_official | 235:685d5f11838f | 1570 | assert_param(IS_FMC_SDRAM_DEVICE(Device)); |
| mbed_official | 235:685d5f11838f | 1571 | assert_param(IS_FMC_SDRAM_BANK(Bank)); |
| mbed_official | 235:685d5f11838f | 1572 | |
| mbed_official | 235:685d5f11838f | 1573 | /* Enable write protection */ |
| mbed_official | 235:685d5f11838f | 1574 | Device->SDCR[Bank] |= FMC_SDRAM_WRITE_PROTECTION_ENABLE; |
| mbed_official | 235:685d5f11838f | 1575 | |
| mbed_official | 235:685d5f11838f | 1576 | return HAL_OK; |
| mbed_official | 235:685d5f11838f | 1577 | } |
| mbed_official | 235:685d5f11838f | 1578 | |
| mbed_official | 235:685d5f11838f | 1579 | /** |
| mbed_official | 235:685d5f11838f | 1580 | * @brief Disables dynamically FMC_SDRAM write protection. |
| mbed_official | 235:685d5f11838f | 1581 | * @param hsdram: FMC_SDRAM handle |
| mbed_official | 235:685d5f11838f | 1582 | * @retval HAL status |
| mbed_official | 235:685d5f11838f | 1583 | */ |
| mbed_official | 235:685d5f11838f | 1584 | HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank) |
| mbed_official | 235:685d5f11838f | 1585 | { |
| mbed_official | 235:685d5f11838f | 1586 | /* Check the parameters */ |
| mbed_official | 235:685d5f11838f | 1587 | assert_param(IS_FMC_SDRAM_DEVICE(Device)); |
| mbed_official | 235:685d5f11838f | 1588 | assert_param(IS_FMC_SDRAM_BANK(Bank)); |
| mbed_official | 235:685d5f11838f | 1589 | |
| mbed_official | 235:685d5f11838f | 1590 | /* Disable write protection */ |
| mbed_official | 235:685d5f11838f | 1591 | Device->SDCR[Bank] &= ~FMC_SDRAM_WRITE_PROTECTION_ENABLE; |
| mbed_official | 235:685d5f11838f | 1592 | |
| mbed_official | 235:685d5f11838f | 1593 | return HAL_OK; |
| mbed_official | 235:685d5f11838f | 1594 | } |
| mbed_official | 235:685d5f11838f | 1595 | |
| mbed_official | 235:685d5f11838f | 1596 | /** |
| mbed_official | 235:685d5f11838f | 1597 | * @brief Send Command to the FMC SDRAM bank |
| mbed_official | 235:685d5f11838f | 1598 | * @param Device: Pointer to SDRAM device instance |
| mbed_official | 235:685d5f11838f | 1599 | * @param Command: Pointer to SDRAM command structure |
| mbed_official | 235:685d5f11838f | 1600 | * @param Timing: Pointer to SDRAM Timing structure |
| mbed_official | 235:685d5f11838f | 1601 | * @param Timeout: Timeout wait value |
| mbed_official | 235:685d5f11838f | 1602 | * @retval HAL state |
| mbed_official | 235:685d5f11838f | 1603 | */ |
| mbed_official | 235:685d5f11838f | 1604 | HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout) |
| mbed_official | 235:685d5f11838f | 1605 | { |
| mbed_official | 235:685d5f11838f | 1606 | __IO uint32_t tmpr = 0; |
| mbed_official | 235:685d5f11838f | 1607 | uint32_t tickstart = 0; |
| mbed_official | 235:685d5f11838f | 1608 | |
| mbed_official | 235:685d5f11838f | 1609 | /* Check the parameters */ |
| mbed_official | 235:685d5f11838f | 1610 | assert_param(IS_FMC_SDRAM_DEVICE(Device)); |
| mbed_official | 235:685d5f11838f | 1611 | assert_param(IS_FMC_COMMAND_MODE(Command->CommandMode)); |
| mbed_official | 235:685d5f11838f | 1612 | assert_param(IS_FMC_COMMAND_TARGET(Command->CommandTarget)); |
| mbed_official | 235:685d5f11838f | 1613 | assert_param(IS_FMC_AUTOREFRESH_NUMBER(Command->AutoRefreshNumber)); |
| mbed_official | 235:685d5f11838f | 1614 | assert_param(IS_FMC_MODE_REGISTER(Command->ModeRegisterDefinition)); |
| mbed_official | 235:685d5f11838f | 1615 | |
| mbed_official | 235:685d5f11838f | 1616 | /* Set command register */ |
| mbed_official | 235:685d5f11838f | 1617 | tmpr = (uint32_t)((Command->CommandMode) |\ |
| mbed_official | 235:685d5f11838f | 1618 | (Command->CommandTarget) |\ |
| mbed_official | 235:685d5f11838f | 1619 | (((Command->AutoRefreshNumber)-1) << 5) |\ |
| mbed_official | 235:685d5f11838f | 1620 | ((Command->ModeRegisterDefinition) << 9) |
| mbed_official | 235:685d5f11838f | 1621 | ); |
| mbed_official | 235:685d5f11838f | 1622 | |
| mbed_official | 235:685d5f11838f | 1623 | Device->SDCMR = tmpr; |
| mbed_official | 235:685d5f11838f | 1624 | |
| mbed_official | 235:685d5f11838f | 1625 | /* Get tick */ |
| mbed_official | 235:685d5f11838f | 1626 | tickstart = HAL_GetTick(); |
| mbed_official | 235:685d5f11838f | 1627 | |
| mbed_official | 235:685d5f11838f | 1628 | /* wait until command is send */ |
| mbed_official | 235:685d5f11838f | 1629 | while(HAL_IS_BIT_SET(Device->SDSR, FMC_SDSR_BUSY)) |
| mbed_official | 235:685d5f11838f | 1630 | { |
| mbed_official | 235:685d5f11838f | 1631 | /* Check for the Timeout */ |
| mbed_official | 235:685d5f11838f | 1632 | if(Timeout != HAL_MAX_DELAY) |
| mbed_official | 235:685d5f11838f | 1633 | { |
| mbed_official | 235:685d5f11838f | 1634 | if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) |
| mbed_official | 235:685d5f11838f | 1635 | { |
| mbed_official | 235:685d5f11838f | 1636 | return HAL_TIMEOUT; |
| mbed_official | 235:685d5f11838f | 1637 | } |
| mbed_official | 235:685d5f11838f | 1638 | } |
| mbed_official | 235:685d5f11838f | 1639 | |
| mbed_official | 235:685d5f11838f | 1640 | return HAL_ERROR; |
| mbed_official | 235:685d5f11838f | 1641 | } |
| mbed_official | 235:685d5f11838f | 1642 | |
| mbed_official | 235:685d5f11838f | 1643 | return HAL_OK; |
| mbed_official | 235:685d5f11838f | 1644 | } |
| mbed_official | 235:685d5f11838f | 1645 | |
| mbed_official | 235:685d5f11838f | 1646 | /** |
| mbed_official | 235:685d5f11838f | 1647 | * @brief Program the SDRAM Memory Refresh rate. |
| mbed_official | 235:685d5f11838f | 1648 | * @param Device: Pointer to SDRAM device instance |
| mbed_official | 235:685d5f11838f | 1649 | * @param RefreshRate: The SDRAM refresh rate value. |
| mbed_official | 235:685d5f11838f | 1650 | * @retval HAL state |
| mbed_official | 235:685d5f11838f | 1651 | */ |
| mbed_official | 235:685d5f11838f | 1652 | HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate) |
| mbed_official | 235:685d5f11838f | 1653 | { |
| mbed_official | 235:685d5f11838f | 1654 | /* Check the parameters */ |
| mbed_official | 235:685d5f11838f | 1655 | assert_param(IS_FMC_SDRAM_DEVICE(Device)); |
| mbed_official | 235:685d5f11838f | 1656 | assert_param(IS_FMC_REFRESH_RATE(RefreshRate)); |
| mbed_official | 235:685d5f11838f | 1657 | |
| mbed_official | 235:685d5f11838f | 1658 | /* Set the refresh rate in command register */ |
| mbed_official | 235:685d5f11838f | 1659 | Device->SDRTR |= (RefreshRate<<1); |
| mbed_official | 235:685d5f11838f | 1660 | |
| mbed_official | 235:685d5f11838f | 1661 | return HAL_OK; |
| mbed_official | 235:685d5f11838f | 1662 | } |
| mbed_official | 235:685d5f11838f | 1663 | |
| mbed_official | 235:685d5f11838f | 1664 | /** |
| mbed_official | 235:685d5f11838f | 1665 | * @brief Set the Number of consecutive SDRAM Memory auto Refresh commands. |
| mbed_official | 235:685d5f11838f | 1666 | * @param Device: Pointer to SDRAM device instance |
| mbed_official | 235:685d5f11838f | 1667 | * @param AutoRefreshNumber: Specifies the auto Refresh number. |
| mbed_official | 235:685d5f11838f | 1668 | * @retval None |
| mbed_official | 235:685d5f11838f | 1669 | */ |
| mbed_official | 235:685d5f11838f | 1670 | HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint32_t AutoRefreshNumber) |
| mbed_official | 235:685d5f11838f | 1671 | { |
| mbed_official | 235:685d5f11838f | 1672 | /* Check the parameters */ |
| mbed_official | 235:685d5f11838f | 1673 | assert_param(IS_FMC_SDRAM_DEVICE(Device)); |
| mbed_official | 235:685d5f11838f | 1674 | assert_param(IS_FMC_AUTOREFRESH_NUMBER(AutoRefreshNumber)); |
| mbed_official | 235:685d5f11838f | 1675 | |
| mbed_official | 235:685d5f11838f | 1676 | /* Set the Auto-refresh number in command register */ |
| mbed_official | 235:685d5f11838f | 1677 | Device->SDCMR |= (AutoRefreshNumber << 5); |
| mbed_official | 235:685d5f11838f | 1678 | |
| mbed_official | 235:685d5f11838f | 1679 | return HAL_OK; |
| mbed_official | 235:685d5f11838f | 1680 | } |
| mbed_official | 235:685d5f11838f | 1681 | |
| mbed_official | 235:685d5f11838f | 1682 | /** |
| mbed_official | 235:685d5f11838f | 1683 | * @brief Returns the indicated FMC SDRAM bank mode status. |
| mbed_official | 235:685d5f11838f | 1684 | * @param Device: Pointer to SDRAM device instance |
| mbed_official | 235:685d5f11838f | 1685 | * @param Bank: Defines the FMC SDRAM bank. This parameter can be |
| mbed_official | 235:685d5f11838f | 1686 | * FMC_Bank1_SDRAM or FMC_Bank2_SDRAM. |
| mbed_official | 235:685d5f11838f | 1687 | * @retval The FMC SDRAM bank mode status, could be on of the following values: |
| mbed_official | 235:685d5f11838f | 1688 | * FMC_SDRAM_NORMAL_MODE, FMC_SDRAM_SELF_REFRESH_MODE or |
| mbed_official | 235:685d5f11838f | 1689 | * FMC_SDRAM_POWER_DOWN_MODE. |
| mbed_official | 235:685d5f11838f | 1690 | */ |
| mbed_official | 235:685d5f11838f | 1691 | uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank) |
| mbed_official | 235:685d5f11838f | 1692 | { |
| mbed_official | 235:685d5f11838f | 1693 | uint32_t tmpreg = 0; |
| mbed_official | 235:685d5f11838f | 1694 | |
| mbed_official | 235:685d5f11838f | 1695 | /* Check the parameters */ |
| mbed_official | 235:685d5f11838f | 1696 | assert_param(IS_FMC_SDRAM_DEVICE(Device)); |
| mbed_official | 235:685d5f11838f | 1697 | assert_param(IS_FMC_SDRAM_BANK(Bank)); |
| mbed_official | 235:685d5f11838f | 1698 | |
| mbed_official | 235:685d5f11838f | 1699 | /* Get the corresponding bank mode */ |
| mbed_official | 235:685d5f11838f | 1700 | if(Bank == FMC_SDRAM_BANK1) |
| mbed_official | 235:685d5f11838f | 1701 | { |
| mbed_official | 235:685d5f11838f | 1702 | tmpreg = (uint32_t)(Device->SDSR & FMC_SDSR_MODES1); |
| mbed_official | 235:685d5f11838f | 1703 | } |
| mbed_official | 235:685d5f11838f | 1704 | else |
| mbed_official | 235:685d5f11838f | 1705 | { |
| mbed_official | 235:685d5f11838f | 1706 | tmpreg = ((uint32_t)(Device->SDSR & FMC_SDSR_MODES2) >> 2); |
| mbed_official | 235:685d5f11838f | 1707 | } |
| mbed_official | 235:685d5f11838f | 1708 | |
| mbed_official | 235:685d5f11838f | 1709 | /* Return the mode status */ |
| mbed_official | 235:685d5f11838f | 1710 | return tmpreg; |
| mbed_official | 235:685d5f11838f | 1711 | } |
| mbed_official | 235:685d5f11838f | 1712 | |
| mbed_official | 235:685d5f11838f | 1713 | /** |
| mbed_official | 235:685d5f11838f | 1714 | * @} |
| mbed_official | 235:685d5f11838f | 1715 | */ |
| mbed_official | 235:685d5f11838f | 1716 | |
| mbed_official | 235:685d5f11838f | 1717 | /** |
| mbed_official | 235:685d5f11838f | 1718 | * @} |
| mbed_official | 235:685d5f11838f | 1719 | */ |
| mbed_official | 235:685d5f11838f | 1720 | |
| mbed_official | 532:fe11edbda85c | 1721 | /** |
| mbed_official | 532:fe11edbda85c | 1722 | * @} |
| mbed_official | 532:fe11edbda85c | 1723 | */ |
| mbed_official | 532:fe11edbda85c | 1724 | #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx */ |
| mbed_official | 532:fe11edbda85c | 1725 | #endif /* HAL_SRAM_MODULE_ENABLED || HAL_NOR_MODULE_ENABLED || HAL_NAND_MODULE_ENABLED || HAL_PCCARD_MODULE_ENABLED || HAL_SDRAM_MODULE_ENABLED */ |
| mbed_official | 235:685d5f11838f | 1726 | |
| mbed_official | 235:685d5f11838f | 1727 | /** |
| mbed_official | 235:685d5f11838f | 1728 | * @} |
| mbed_official | 235:685d5f11838f | 1729 | */ |
| mbed_official | 235:685d5f11838f | 1730 | |
| mbed_official | 235:685d5f11838f | 1731 | /** |
| mbed_official | 235:685d5f11838f | 1732 | * @} |
| mbed_official | 235:685d5f11838f | 1733 | */ |
| mbed_official | 235:685d5f11838f | 1734 | |
| mbed_official | 235:685d5f11838f | 1735 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
