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Last commit 20 Feb 2019 by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_tim.c@581:39197bcd20f2, 2015-07-02 (annotated)

Committer:
mbed_official
Date:
Thu Jul 02 16:30:08 2015 +0100
Revision:
581:39197bcd20f2
Parent:
532:fe11edbda85c
Child:
613:bc40b8d2aec4
Synchronized with git revision ae2d3cdffe70184eb8736d94f76c45c93f4b7724



Full URL: https://github.com/mbedmicro/mbed/commit/ae2d3cdffe70184eb8736d94f76c45c93f4b7724/



Make it possible to build the core mbed library with yotta

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UserRevisionLine numberNew contents of line
mbed_official 87:085cde657901 1 /**
mbed_official 87:085cde657901 2 ******************************************************************************
mbed_official 87:085cde657901 3 * @file stm32f4xx_hal_tim.c
mbed_official 87:085cde657901 4 * @author MCD Application Team
mbed_official 532:fe11edbda85c 5 * @version V1.3.0
mbed_official 532:fe11edbda85c 6 * @date 09-March-2015
mbed_official 87:085cde657901 7 * @brief TIM HAL module driver.
mbed_official 87:085cde657901 8 * This file provides firmware functions to manage the following
mbed_official 87:085cde657901 9 * functionalities of the Timer (TIM) peripheral:
mbed_official 87:085cde657901 10 * + Time Base Initialization
mbed_official 87:085cde657901 11 * + Time Base Start
mbed_official 87:085cde657901 12 * + Time Base Start Interruption
mbed_official 87:085cde657901 13 * + Time Base Start DMA
mbed_official 87:085cde657901 14 * + Time Output Compare/PWM Initialization
mbed_official 87:085cde657901 15 * + Time Output Compare/PWM Channel Configuration
mbed_official 87:085cde657901 16 * + Time Output Compare/PWM Start
mbed_official 87:085cde657901 17 * + Time Output Compare/PWM Start Interruption
mbed_official 87:085cde657901 18 * + Time Output Compare/PWM Start DMA
mbed_official 87:085cde657901 19 * + Time Input Capture Initialization
mbed_official 87:085cde657901 20 * + Time Input Capture Channel Configuration
mbed_official 87:085cde657901 21 * + Time Input Capture Start
mbed_official 87:085cde657901 22 * + Time Input Capture Start Interruption
mbed_official 87:085cde657901 23 * + Time Input Capture Start DMA
mbed_official 87:085cde657901 24 * + Time One Pulse Initialization
mbed_official 87:085cde657901 25 * + Time One Pulse Channel Configuration
mbed_official 87:085cde657901 26 * + Time One Pulse Start
mbed_official 87:085cde657901 27 * + Time Encoder Interface Initialization
mbed_official 87:085cde657901 28 * + Time Encoder Interface Start
mbed_official 87:085cde657901 29 * + Time Encoder Interface Start Interruption
mbed_official 87:085cde657901 30 * + Time Encoder Interface Start DMA
mbed_official 87:085cde657901 31 * + Commutation Event configuration with Interruption and DMA
mbed_official 87:085cde657901 32 * + Time OCRef clear configuration
mbed_official 87:085cde657901 33 * + Time External Clock configuration
mbed_official 87:085cde657901 34 @verbatim
mbed_official 87:085cde657901 35 ==============================================================================
mbed_official 87:085cde657901 36 ##### TIMER Generic features #####
mbed_official 87:085cde657901 37 ==============================================================================
mbed_official 87:085cde657901 38 [..] The Timer features include:
mbed_official 87:085cde657901 39 (#) 16-bit up, down, up/down auto-reload counter.
mbed_official 87:085cde657901 40 (#) 16-bit programmable prescaler allowing dividing (also on the fly) the
mbed_official 87:085cde657901 41 counter clock frequency either by any factor between 1 and 65536.
mbed_official 87:085cde657901 42 (#) Up to 4 independent channels for:
mbed_official 87:085cde657901 43 (++) Input Capture
mbed_official 87:085cde657901 44 (++) Output Compare
mbed_official 87:085cde657901 45 (++) PWM generation (Edge and Center-aligned Mode)
mbed_official 87:085cde657901 46 (++) One-pulse mode output
mbed_official 87:085cde657901 47
mbed_official 87:085cde657901 48 ##### How to use this driver #####
mbed_official 87:085cde657901 49 ==============================================================================
mbed_official 87:085cde657901 50 [..]
mbed_official 87:085cde657901 51 (#) Initialize the TIM low level resources by implementing the following functions
mbed_official 87:085cde657901 52 depending from feature used :
mbed_official 87:085cde657901 53 (++) Time Base : HAL_TIM_Base_MspInit()
mbed_official 87:085cde657901 54 (++) Input Capture : HAL_TIM_IC_MspInit()
mbed_official 87:085cde657901 55 (++) Output Compare : HAL_TIM_OC_MspInit()
mbed_official 87:085cde657901 56 (++) PWM generation : HAL_TIM_PWM_MspInit()
mbed_official 87:085cde657901 57 (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
mbed_official 87:085cde657901 58 (++) Encoder mode output : HAL_TIM_Encoder_MspInit()
mbed_official 87:085cde657901 59
mbed_official 87:085cde657901 60 (#) Initialize the TIM low level resources :
mbed_official 87:085cde657901 61 (##) Enable the TIM interface clock using __TIMx_CLK_ENABLE();
mbed_official 87:085cde657901 62 (##) TIM pins configuration
mbed_official 87:085cde657901 63 (+++) Enable the clock for the TIM GPIOs using the following function:
mbed_official 87:085cde657901 64 __GPIOx_CLK_ENABLE();
mbed_official 87:085cde657901 65 (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
mbed_official 87:085cde657901 66
mbed_official 87:085cde657901 67 (#) The external Clock can be configured, if needed (the default clock is the
mbed_official 87:085cde657901 68 internal clock from the APBx), using the following function:
mbed_official 87:085cde657901 69 HAL_TIM_ConfigClockSource, the clock configuration should be done before
mbed_official 87:085cde657901 70 any start function.
mbed_official 87:085cde657901 71
mbed_official 87:085cde657901 72 (#) Configure the TIM in the desired functioning mode using one of the
mbed_official 87:085cde657901 73 initialization function of this driver:
mbed_official 87:085cde657901 74 (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
mbed_official 87:085cde657901 75 (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
mbed_official 87:085cde657901 76 Output Compare signal.
mbed_official 87:085cde657901 77 (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
mbed_official 87:085cde657901 78 PWM signal.
mbed_official 87:085cde657901 79 (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
mbed_official 87:085cde657901 80 external signal.
mbed_official 87:085cde657901 81 (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
mbed_official 87:085cde657901 82 in One Pulse Mode.
mbed_official 87:085cde657901 83 (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
mbed_official 87:085cde657901 84
mbed_official 87:085cde657901 85 (#) Activate the TIM peripheral using one of the start functions depending from the feature used:
mbed_official 87:085cde657901 86 (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
mbed_official 87:085cde657901 87 (++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
mbed_official 87:085cde657901 88 (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
mbed_official 87:085cde657901 89 (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
mbed_official 87:085cde657901 90 (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
mbed_official 87:085cde657901 91 (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
mbed_official 87:085cde657901 92
mbed_official 87:085cde657901 93 (#) The DMA Burst is managed with the two following functions:
mbed_official 87:085cde657901 94 HAL_TIM_DMABurst_WriteStart()
mbed_official 87:085cde657901 95 HAL_TIM_DMABurst_ReadStart()
mbed_official 87:085cde657901 96
mbed_official 87:085cde657901 97 @endverbatim
mbed_official 87:085cde657901 98 ******************************************************************************
mbed_official 87:085cde657901 99 * @attention
mbed_official 87:085cde657901 100 *
mbed_official 532:fe11edbda85c 101 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
mbed_official 87:085cde657901 102 *
mbed_official 87:085cde657901 103 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 87:085cde657901 104 * are permitted provided that the following conditions are met:
mbed_official 87:085cde657901 105 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 87:085cde657901 106 * this list of conditions and the following disclaimer.
mbed_official 87:085cde657901 107 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 87:085cde657901 108 * this list of conditions and the following disclaimer in the documentation
mbed_official 87:085cde657901 109 * and/or other materials provided with the distribution.
mbed_official 87:085cde657901 110 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 87:085cde657901 111 * may be used to endorse or promote products derived from this software
mbed_official 87:085cde657901 112 * without specific prior written permission.
mbed_official 87:085cde657901 113 *
mbed_official 87:085cde657901 114 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 87:085cde657901 115 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 87:085cde657901 116 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 87:085cde657901 117 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 87:085cde657901 118 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 87:085cde657901 119 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 87:085cde657901 120 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 87:085cde657901 121 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 87:085cde657901 122 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 87:085cde657901 123 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 87:085cde657901 124 *
mbed_official 87:085cde657901 125 ******************************************************************************
mbed_official 87:085cde657901 126 */
mbed_official 87:085cde657901 127
mbed_official 87:085cde657901 128 /* Includes ------------------------------------------------------------------*/
mbed_official 87:085cde657901 129 #include "stm32f4xx_hal.h"
mbed_official 87:085cde657901 130
mbed_official 87:085cde657901 131 /** @addtogroup STM32F4xx_HAL_Driver
mbed_official 87:085cde657901 132 * @{
mbed_official 87:085cde657901 133 */
mbed_official 87:085cde657901 134
mbed_official 532:fe11edbda85c 135 /** @defgroup TIM TIM
mbed_official 87:085cde657901 136 * @brief TIM HAL module driver
mbed_official 87:085cde657901 137 * @{
mbed_official 87:085cde657901 138 */
mbed_official 87:085cde657901 139
mbed_official 87:085cde657901 140 #ifdef HAL_TIM_MODULE_ENABLED
mbed_official 87:085cde657901 141
mbed_official 87:085cde657901 142 /* Private typedef -----------------------------------------------------------*/
mbed_official 87:085cde657901 143 /* Private define ------------------------------------------------------------*/
mbed_official 87:085cde657901 144 /* Private macro -------------------------------------------------------------*/
mbed_official 87:085cde657901 145 /* Private variables ---------------------------------------------------------*/
mbed_official 532:fe11edbda85c 146 /** @addtogroup TIM_Private_Functions
mbed_official 532:fe11edbda85c 147 * @{
mbed_official 532:fe11edbda85c 148 */
mbed_official 87:085cde657901 149 /* Private function prototypes -----------------------------------------------*/
mbed_official 87:085cde657901 150 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
mbed_official 87:085cde657901 151 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
mbed_official 87:085cde657901 152 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
mbed_official 87:085cde657901 153
mbed_official 87:085cde657901 154 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
mbed_official 87:085cde657901 155 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
mbed_official 87:085cde657901 156 uint32_t TIM_ICFilter);
mbed_official 87:085cde657901 157 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
mbed_official 87:085cde657901 158 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
mbed_official 87:085cde657901 159 uint32_t TIM_ICFilter);
mbed_official 87:085cde657901 160 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
mbed_official 87:085cde657901 161 uint32_t TIM_ICFilter);
mbed_official 87:085cde657901 162
mbed_official 87:085cde657901 163 static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
mbed_official 87:085cde657901 164 uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
mbed_official 87:085cde657901 165
mbed_official 87:085cde657901 166 static void TIM_ITRx_SetConfig(TIM_TypeDef* TIMx, uint16_t TIM_ITRx);
mbed_official 87:085cde657901 167 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
mbed_official 87:085cde657901 168 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
mbed_official 532:fe11edbda85c 169 static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
mbed_official 532:fe11edbda85c 170 TIM_SlaveConfigTypeDef * sSlaveConfig);
mbed_official 532:fe11edbda85c 171 /**
mbed_official 532:fe11edbda85c 172 * @}
mbed_official 532:fe11edbda85c 173 */
mbed_official 532:fe11edbda85c 174
mbed_official 532:fe11edbda85c 175 /* Exported functions --------------------------------------------------------*/
mbed_official 532:fe11edbda85c 176 /** @defgroup TIM_Exported_Functions TIM Exported Functions
mbed_official 87:085cde657901 177 * @{
mbed_official 87:085cde657901 178 */
mbed_official 87:085cde657901 179
mbed_official 532:fe11edbda85c 180 /** @defgroup TIM_Exported_Functions_Group1 Time Base functions
mbed_official 87:085cde657901 181 * @brief Time Base functions
mbed_official 87:085cde657901 182 *
mbed_official 87:085cde657901 183 @verbatim
mbed_official 87:085cde657901 184 ==============================================================================
mbed_official 87:085cde657901 185 ##### Time Base functions #####
mbed_official 87:085cde657901 186 ==============================================================================
mbed_official 87:085cde657901 187 [..]
mbed_official 87:085cde657901 188 This section provides functions allowing to:
mbed_official 87:085cde657901 189 (+) Initialize and configure the TIM base.
mbed_official 87:085cde657901 190 (+) De-initialize the TIM base.
mbed_official 87:085cde657901 191 (+) Start the Time Base.
mbed_official 87:085cde657901 192 (+) Stop the Time Base.
mbed_official 87:085cde657901 193 (+) Start the Time Base and enable interrupt.
mbed_official 87:085cde657901 194 (+) Stop the Time Base and disable interrupt.
mbed_official 87:085cde657901 195 (+) Start the Time Base and enable DMA transfer.
mbed_official 87:085cde657901 196 (+) Stop the Time Base and disable DMA transfer.
mbed_official 87:085cde657901 197
mbed_official 87:085cde657901 198 @endverbatim
mbed_official 87:085cde657901 199 * @{
mbed_official 87:085cde657901 200 */
mbed_official 87:085cde657901 201 /**
mbed_official 87:085cde657901 202 * @brief Initializes the TIM Time base Unit according to the specified
mbed_official 87:085cde657901 203 * parameters in the TIM_HandleTypeDef and create the associated handle.
mbed_official 226:b062af740e40 204 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 205 * the configuration information for TIM module.
mbed_official 87:085cde657901 206 * @retval HAL status
mbed_official 87:085cde657901 207 */
mbed_official 87:085cde657901 208 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
mbed_official 87:085cde657901 209 {
mbed_official 87:085cde657901 210 /* Check the TIM handle allocation */
mbed_official 369:2e96f1b71984 211 if(htim == HAL_NULL)
mbed_official 87:085cde657901 212 {
mbed_official 87:085cde657901 213 return HAL_ERROR;
mbed_official 87:085cde657901 214 }
mbed_official 87:085cde657901 215
mbed_official 87:085cde657901 216 /* Check the parameters */
mbed_official 87:085cde657901 217 assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official 87:085cde657901 218 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
mbed_official 87:085cde657901 219 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
mbed_official 87:085cde657901 220
mbed_official 87:085cde657901 221 if(htim->State == HAL_TIM_STATE_RESET)
mbed_official 87:085cde657901 222 {
mbed_official 532:fe11edbda85c 223 /* Allocate lock resource and initialize it */
mbed_official 532:fe11edbda85c 224 htim->Lock = HAL_UNLOCKED;
mbed_official 87:085cde657901 225 /* Init the low level hardware : GPIO, CLOCK, NVIC */
mbed_official 87:085cde657901 226 HAL_TIM_Base_MspInit(htim);
mbed_official 87:085cde657901 227 }
mbed_official 87:085cde657901 228
mbed_official 87:085cde657901 229 /* Set the TIM state */
mbed_official 87:085cde657901 230 htim->State= HAL_TIM_STATE_BUSY;
mbed_official 87:085cde657901 231
mbed_official 87:085cde657901 232 /* Set the Time Base configuration */
mbed_official 87:085cde657901 233 TIM_Base_SetConfig(htim->Instance, &htim->Init);
mbed_official 87:085cde657901 234
mbed_official 87:085cde657901 235 /* Initialize the TIM state*/
mbed_official 87:085cde657901 236 htim->State= HAL_TIM_STATE_READY;
mbed_official 87:085cde657901 237
mbed_official 87:085cde657901 238 return HAL_OK;
mbed_official 87:085cde657901 239 }
mbed_official 87:085cde657901 240
mbed_official 87:085cde657901 241 /**
mbed_official 87:085cde657901 242 * @brief DeInitializes the TIM Base peripheral
mbed_official 226:b062af740e40 243 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 244 * the configuration information for TIM module.
mbed_official 87:085cde657901 245 * @retval HAL status
mbed_official 87:085cde657901 246 */
mbed_official 87:085cde657901 247 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
mbed_official 87:085cde657901 248 {
mbed_official 87:085cde657901 249 /* Check the parameters */
mbed_official 87:085cde657901 250 assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official 87:085cde657901 251
mbed_official 87:085cde657901 252 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 87:085cde657901 253
mbed_official 87:085cde657901 254 /* Disable the TIM Peripheral Clock */
mbed_official 87:085cde657901 255 __HAL_TIM_DISABLE(htim);
mbed_official 87:085cde657901 256
mbed_official 87:085cde657901 257 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
mbed_official 87:085cde657901 258 HAL_TIM_Base_MspDeInit(htim);
mbed_official 87:085cde657901 259
mbed_official 87:085cde657901 260 /* Change TIM state */
mbed_official 87:085cde657901 261 htim->State = HAL_TIM_STATE_RESET;
mbed_official 87:085cde657901 262
mbed_official 106:ced8cbb51063 263 /* Release Lock */
mbed_official 106:ced8cbb51063 264 __HAL_UNLOCK(htim);
mbed_official 106:ced8cbb51063 265
mbed_official 87:085cde657901 266 return HAL_OK;
mbed_official 87:085cde657901 267 }
mbed_official 87:085cde657901 268
mbed_official 87:085cde657901 269 /**
mbed_official 87:085cde657901 270 * @brief Initializes the TIM Base MSP.
mbed_official 226:b062af740e40 271 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 272 * the configuration information for TIM module.
mbed_official 87:085cde657901 273 * @retval None
mbed_official 87:085cde657901 274 */
mbed_official 87:085cde657901 275 __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
mbed_official 87:085cde657901 276 {
mbed_official 87:085cde657901 277 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 87:085cde657901 278 the HAL_TIM_Base_MspInit could be implemented in the user file
mbed_official 87:085cde657901 279 */
mbed_official 87:085cde657901 280 }
mbed_official 87:085cde657901 281
mbed_official 87:085cde657901 282 /**
mbed_official 87:085cde657901 283 * @brief DeInitializes TIM Base MSP.
mbed_official 226:b062af740e40 284 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 285 * the configuration information for TIM module.
mbed_official 87:085cde657901 286 * @retval None
mbed_official 87:085cde657901 287 */
mbed_official 87:085cde657901 288 __weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
mbed_official 87:085cde657901 289 {
mbed_official 87:085cde657901 290 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 87:085cde657901 291 the HAL_TIM_Base_MspDeInit could be implemented in the user file
mbed_official 87:085cde657901 292 */
mbed_official 87:085cde657901 293 }
mbed_official 87:085cde657901 294
mbed_official 87:085cde657901 295 /**
mbed_official 87:085cde657901 296 * @brief Starts the TIM Base generation.
mbed_official 226:b062af740e40 297 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 298 * the configuration information for TIM module.
mbed_official 87:085cde657901 299 * @retval HAL status
mbed_official 87:085cde657901 300 */
mbed_official 87:085cde657901 301 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
mbed_official 87:085cde657901 302 {
mbed_official 87:085cde657901 303 /* Check the parameters */
mbed_official 87:085cde657901 304 assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official 87:085cde657901 305
mbed_official 87:085cde657901 306 /* Set the TIM state */
mbed_official 87:085cde657901 307 htim->State= HAL_TIM_STATE_BUSY;
mbed_official 87:085cde657901 308
mbed_official 87:085cde657901 309 /* Enable the Peripheral */
mbed_official 87:085cde657901 310 __HAL_TIM_ENABLE(htim);
mbed_official 87:085cde657901 311
mbed_official 87:085cde657901 312 /* Change the TIM state*/
mbed_official 87:085cde657901 313 htim->State= HAL_TIM_STATE_READY;
mbed_official 87:085cde657901 314
mbed_official 87:085cde657901 315 /* Return function status */
mbed_official 87:085cde657901 316 return HAL_OK;
mbed_official 87:085cde657901 317 }
mbed_official 87:085cde657901 318
mbed_official 87:085cde657901 319 /**
mbed_official 87:085cde657901 320 * @brief Stops the TIM Base generation.
mbed_official 226:b062af740e40 321 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 322 * the configuration information for TIM module.
mbed_official 87:085cde657901 323 * @retval HAL status
mbed_official 87:085cde657901 324 */
mbed_official 87:085cde657901 325 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
mbed_official 87:085cde657901 326 {
mbed_official 87:085cde657901 327 /* Check the parameters */
mbed_official 87:085cde657901 328 assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official 87:085cde657901 329
mbed_official 87:085cde657901 330 /* Set the TIM state */
mbed_official 87:085cde657901 331 htim->State= HAL_TIM_STATE_BUSY;
mbed_official 87:085cde657901 332
mbed_official 87:085cde657901 333 /* Disable the Peripheral */
mbed_official 87:085cde657901 334 __HAL_TIM_DISABLE(htim);
mbed_official 87:085cde657901 335
mbed_official 87:085cde657901 336 /* Change the TIM state*/
mbed_official 87:085cde657901 337 htim->State= HAL_TIM_STATE_READY;
mbed_official 87:085cde657901 338
mbed_official 87:085cde657901 339 /* Return function status */
mbed_official 87:085cde657901 340 return HAL_OK;
mbed_official 87:085cde657901 341 }
mbed_official 87:085cde657901 342
mbed_official 87:085cde657901 343 /**
mbed_official 87:085cde657901 344 * @brief Starts the TIM Base generation in interrupt mode.
mbed_official 226:b062af740e40 345 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 346 * the configuration information for TIM module.
mbed_official 87:085cde657901 347 * @retval HAL status
mbed_official 87:085cde657901 348 */
mbed_official 87:085cde657901 349 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
mbed_official 87:085cde657901 350 {
mbed_official 87:085cde657901 351 /* Check the parameters */
mbed_official 87:085cde657901 352 assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official 87:085cde657901 353
mbed_official 87:085cde657901 354 /* Enable the TIM Update interrupt */
mbed_official 87:085cde657901 355 __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
mbed_official 87:085cde657901 356
mbed_official 87:085cde657901 357 /* Enable the Peripheral */
mbed_official 87:085cde657901 358 __HAL_TIM_ENABLE(htim);
mbed_official 87:085cde657901 359
mbed_official 87:085cde657901 360 /* Return function status */
mbed_official 87:085cde657901 361 return HAL_OK;
mbed_official 87:085cde657901 362 }
mbed_official 87:085cde657901 363
mbed_official 87:085cde657901 364 /**
mbed_official 87:085cde657901 365 * @brief Stops the TIM Base generation in interrupt mode.
mbed_official 226:b062af740e40 366 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 367 * the configuration information for TIM module.
mbed_official 87:085cde657901 368 * @retval HAL status
mbed_official 87:085cde657901 369 */
mbed_official 87:085cde657901 370 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
mbed_official 87:085cde657901 371 {
mbed_official 87:085cde657901 372 /* Check the parameters */
mbed_official 87:085cde657901 373 assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official 87:085cde657901 374 /* Disable the TIM Update interrupt */
mbed_official 87:085cde657901 375 __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
mbed_official 87:085cde657901 376
mbed_official 87:085cde657901 377 /* Disable the Peripheral */
mbed_official 87:085cde657901 378 __HAL_TIM_DISABLE(htim);
mbed_official 87:085cde657901 379
mbed_official 87:085cde657901 380 /* Return function status */
mbed_official 87:085cde657901 381 return HAL_OK;
mbed_official 87:085cde657901 382 }
mbed_official 87:085cde657901 383
mbed_official 87:085cde657901 384 /**
mbed_official 87:085cde657901 385 * @brief Starts the TIM Base generation in DMA mode.
mbed_official 226:b062af740e40 386 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 387 * the configuration information for TIM module.
mbed_official 87:085cde657901 388 * @param pData: The source Buffer address.
mbed_official 87:085cde657901 389 * @param Length: The length of data to be transferred from memory to peripheral.
mbed_official 87:085cde657901 390 * @retval HAL status
mbed_official 87:085cde657901 391 */
mbed_official 87:085cde657901 392 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
mbed_official 87:085cde657901 393 {
mbed_official 87:085cde657901 394 /* Check the parameters */
mbed_official 87:085cde657901 395 assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
mbed_official 87:085cde657901 396
mbed_official 87:085cde657901 397 if((htim->State == HAL_TIM_STATE_BUSY))
mbed_official 87:085cde657901 398 {
mbed_official 87:085cde657901 399 return HAL_BUSY;
mbed_official 87:085cde657901 400 }
mbed_official 87:085cde657901 401 else if((htim->State == HAL_TIM_STATE_READY))
mbed_official 87:085cde657901 402 {
mbed_official 87:085cde657901 403 if((pData == 0 ) && (Length > 0))
mbed_official 87:085cde657901 404 {
mbed_official 87:085cde657901 405 return HAL_ERROR;
mbed_official 87:085cde657901 406 }
mbed_official 87:085cde657901 407 else
mbed_official 87:085cde657901 408 {
mbed_official 87:085cde657901 409 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 87:085cde657901 410 }
mbed_official 87:085cde657901 411 }
mbed_official 87:085cde657901 412 /* Set the DMA Period elapsed callback */
mbed_official 87:085cde657901 413 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
mbed_official 87:085cde657901 414
mbed_official 87:085cde657901 415 /* Set the DMA error callback */
mbed_official 532:fe11edbda85c 416 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
mbed_official 87:085cde657901 417
mbed_official 87:085cde657901 418 /* Enable the DMA Stream */
mbed_official 87:085cde657901 419 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length);
mbed_official 87:085cde657901 420
mbed_official 87:085cde657901 421 /* Enable the TIM Update DMA request */
mbed_official 87:085cde657901 422 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
mbed_official 87:085cde657901 423
mbed_official 87:085cde657901 424 /* Enable the Peripheral */
mbed_official 87:085cde657901 425 __HAL_TIM_ENABLE(htim);
mbed_official 87:085cde657901 426
mbed_official 87:085cde657901 427 /* Return function status */
mbed_official 87:085cde657901 428 return HAL_OK;
mbed_official 87:085cde657901 429 }
mbed_official 87:085cde657901 430
mbed_official 87:085cde657901 431 /**
mbed_official 87:085cde657901 432 * @brief Stops the TIM Base generation in DMA mode.
mbed_official 226:b062af740e40 433 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 434 * the configuration information for TIM module.
mbed_official 87:085cde657901 435 * @retval HAL status
mbed_official 87:085cde657901 436 */
mbed_official 87:085cde657901 437 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
mbed_official 87:085cde657901 438 {
mbed_official 87:085cde657901 439 /* Check the parameters */
mbed_official 87:085cde657901 440 assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
mbed_official 87:085cde657901 441
mbed_official 87:085cde657901 442 /* Disable the TIM Update DMA request */
mbed_official 87:085cde657901 443 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
mbed_official 87:085cde657901 444
mbed_official 87:085cde657901 445 /* Disable the Peripheral */
mbed_official 87:085cde657901 446 __HAL_TIM_DISABLE(htim);
mbed_official 87:085cde657901 447
mbed_official 87:085cde657901 448 /* Change the htim state */
mbed_official 87:085cde657901 449 htim->State = HAL_TIM_STATE_READY;
mbed_official 87:085cde657901 450
mbed_official 87:085cde657901 451 /* Return function status */
mbed_official 87:085cde657901 452 return HAL_OK;
mbed_official 87:085cde657901 453 }
mbed_official 87:085cde657901 454 /**
mbed_official 87:085cde657901 455 * @}
mbed_official 87:085cde657901 456 */
mbed_official 87:085cde657901 457
mbed_official 532:fe11edbda85c 458 /** @defgroup TIM_Exported_Functions_Group2 Time Output Compare functions
mbed_official 87:085cde657901 459 * @brief Time Output Compare functions
mbed_official 87:085cde657901 460 *
mbed_official 87:085cde657901 461 @verbatim
mbed_official 87:085cde657901 462 ==============================================================================
mbed_official 87:085cde657901 463 ##### Time Output Compare functions #####
mbed_official 87:085cde657901 464 ==============================================================================
mbed_official 87:085cde657901 465 [..]
mbed_official 87:085cde657901 466 This section provides functions allowing to:
mbed_official 87:085cde657901 467 (+) Initialize and configure the TIM Output Compare.
mbed_official 87:085cde657901 468 (+) De-initialize the TIM Output Compare.
mbed_official 87:085cde657901 469 (+) Start the Time Output Compare.
mbed_official 87:085cde657901 470 (+) Stop the Time Output Compare.
mbed_official 87:085cde657901 471 (+) Start the Time Output Compare and enable interrupt.
mbed_official 87:085cde657901 472 (+) Stop the Time Output Compare and disable interrupt.
mbed_official 87:085cde657901 473 (+) Start the Time Output Compare and enable DMA transfer.
mbed_official 87:085cde657901 474 (+) Stop the Time Output Compare and disable DMA transfer.
mbed_official 87:085cde657901 475
mbed_official 87:085cde657901 476 @endverbatim
mbed_official 87:085cde657901 477 * @{
mbed_official 87:085cde657901 478 */
mbed_official 87:085cde657901 479 /**
mbed_official 87:085cde657901 480 * @brief Initializes the TIM Output Compare according to the specified
mbed_official 87:085cde657901 481 * parameters in the TIM_HandleTypeDef and create the associated handle.
mbed_official 226:b062af740e40 482 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 483 * the configuration information for TIM module.
mbed_official 87:085cde657901 484 * @retval HAL status
mbed_official 87:085cde657901 485 */
mbed_official 87:085cde657901 486 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim)
mbed_official 87:085cde657901 487 {
mbed_official 87:085cde657901 488 /* Check the TIM handle allocation */
mbed_official 369:2e96f1b71984 489 if(htim == HAL_NULL)
mbed_official 87:085cde657901 490 {
mbed_official 87:085cde657901 491 return HAL_ERROR;
mbed_official 87:085cde657901 492 }
mbed_official 87:085cde657901 493
mbed_official 87:085cde657901 494 /* Check the parameters */
mbed_official 87:085cde657901 495 assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official 87:085cde657901 496 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
mbed_official 87:085cde657901 497 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
mbed_official 87:085cde657901 498
mbed_official 87:085cde657901 499 if(htim->State == HAL_TIM_STATE_RESET)
mbed_official 532:fe11edbda85c 500 {
mbed_official 532:fe11edbda85c 501 /* Allocate lock resource and initialize it */
mbed_official 532:fe11edbda85c 502 htim->Lock = HAL_UNLOCKED;
mbed_official 87:085cde657901 503 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
mbed_official 87:085cde657901 504 HAL_TIM_OC_MspInit(htim);
mbed_official 87:085cde657901 505 }
mbed_official 87:085cde657901 506
mbed_official 87:085cde657901 507 /* Set the TIM state */
mbed_official 87:085cde657901 508 htim->State= HAL_TIM_STATE_BUSY;
mbed_official 87:085cde657901 509
mbed_official 87:085cde657901 510 /* Init the base time for the Output Compare */
mbed_official 87:085cde657901 511 TIM_Base_SetConfig(htim->Instance, &htim->Init);
mbed_official 87:085cde657901 512
mbed_official 87:085cde657901 513 /* Initialize the TIM state*/
mbed_official 87:085cde657901 514 htim->State= HAL_TIM_STATE_READY;
mbed_official 87:085cde657901 515
mbed_official 87:085cde657901 516 return HAL_OK;
mbed_official 87:085cde657901 517 }
mbed_official 87:085cde657901 518
mbed_official 87:085cde657901 519 /**
mbed_official 87:085cde657901 520 * @brief DeInitializes the TIM peripheral
mbed_official 226:b062af740e40 521 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 522 * the configuration information for TIM module.
mbed_official 87:085cde657901 523 * @retval HAL status
mbed_official 87:085cde657901 524 */
mbed_official 87:085cde657901 525 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
mbed_official 87:085cde657901 526 {
mbed_official 87:085cde657901 527 /* Check the parameters */
mbed_official 87:085cde657901 528 assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official 87:085cde657901 529
mbed_official 87:085cde657901 530 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 87:085cde657901 531
mbed_official 87:085cde657901 532 /* Disable the TIM Peripheral Clock */
mbed_official 87:085cde657901 533 __HAL_TIM_DISABLE(htim);
mbed_official 87:085cde657901 534
mbed_official 87:085cde657901 535 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
mbed_official 87:085cde657901 536 HAL_TIM_OC_MspDeInit(htim);
mbed_official 87:085cde657901 537
mbed_official 87:085cde657901 538 /* Change TIM state */
mbed_official 87:085cde657901 539 htim->State = HAL_TIM_STATE_RESET;
mbed_official 106:ced8cbb51063 540
mbed_official 106:ced8cbb51063 541 /* Release Lock */
mbed_official 106:ced8cbb51063 542 __HAL_UNLOCK(htim);
mbed_official 106:ced8cbb51063 543
mbed_official 87:085cde657901 544 return HAL_OK;
mbed_official 87:085cde657901 545 }
mbed_official 87:085cde657901 546
mbed_official 87:085cde657901 547 /**
mbed_official 87:085cde657901 548 * @brief Initializes the TIM Output Compare MSP.
mbed_official 226:b062af740e40 549 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 550 * the configuration information for TIM module.
mbed_official 87:085cde657901 551 * @retval None
mbed_official 87:085cde657901 552 */
mbed_official 87:085cde657901 553 __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
mbed_official 87:085cde657901 554 {
mbed_official 87:085cde657901 555 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 87:085cde657901 556 the HAL_TIM_OC_MspInit could be implemented in the user file
mbed_official 87:085cde657901 557 */
mbed_official 87:085cde657901 558 }
mbed_official 87:085cde657901 559
mbed_official 87:085cde657901 560 /**
mbed_official 87:085cde657901 561 * @brief DeInitializes TIM Output Compare MSP.
mbed_official 226:b062af740e40 562 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 563 * the configuration information for TIM module.
mbed_official 87:085cde657901 564 * @retval None
mbed_official 87:085cde657901 565 */
mbed_official 87:085cde657901 566 __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
mbed_official 87:085cde657901 567 {
mbed_official 87:085cde657901 568 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 87:085cde657901 569 the HAL_TIM_OC_MspDeInit could be implemented in the user file
mbed_official 87:085cde657901 570 */
mbed_official 87:085cde657901 571 }
mbed_official 87:085cde657901 572
mbed_official 87:085cde657901 573 /**
mbed_official 87:085cde657901 574 * @brief Starts the TIM Output Compare signal generation.
mbed_official 226:b062af740e40 575 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 576 * the configuration information for TIM module.
mbed_official 226:b062af740e40 577 * @param Channel: TIM Channel to be enabled.
mbed_official 87:085cde657901 578 * This parameter can be one of the following values:
mbed_official 87:085cde657901 579 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 87:085cde657901 580 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 87:085cde657901 581 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 87:085cde657901 582 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 87:085cde657901 583 * @retval HAL status
mbed_official 87:085cde657901 584 */
mbed_official 87:085cde657901 585 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 87:085cde657901 586 {
mbed_official 87:085cde657901 587 /* Check the parameters */
mbed_official 87:085cde657901 588 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official 87:085cde657901 589
mbed_official 87:085cde657901 590 /* Enable the Output compare channel */
mbed_official 87:085cde657901 591 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
mbed_official 87:085cde657901 592
mbed_official 87:085cde657901 593 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
mbed_official 87:085cde657901 594 {
mbed_official 87:085cde657901 595 /* Enable the main output */
mbed_official 87:085cde657901 596 __HAL_TIM_MOE_ENABLE(htim);
mbed_official 87:085cde657901 597 }
mbed_official 87:085cde657901 598
mbed_official 87:085cde657901 599 /* Enable the Peripheral */
mbed_official 87:085cde657901 600 __HAL_TIM_ENABLE(htim);
mbed_official 87:085cde657901 601
mbed_official 87:085cde657901 602 /* Return function status */
mbed_official 87:085cde657901 603 return HAL_OK;
mbed_official 87:085cde657901 604 }
mbed_official 87:085cde657901 605
mbed_official 87:085cde657901 606 /**
mbed_official 87:085cde657901 607 * @brief Stops the TIM Output Compare signal generation.
mbed_official 226:b062af740e40 608 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 609 * the configuration information for TIM module.
mbed_official 226:b062af740e40 610 * @param Channel: TIM Channel to be disabled.
mbed_official 87:085cde657901 611 * This parameter can be one of the following values:
mbed_official 87:085cde657901 612 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 87:085cde657901 613 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 87:085cde657901 614 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 87:085cde657901 615 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 87:085cde657901 616 * @retval HAL status
mbed_official 87:085cde657901 617 */
mbed_official 87:085cde657901 618 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 87:085cde657901 619 {
mbed_official 87:085cde657901 620 /* Check the parameters */
mbed_official 87:085cde657901 621 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official 87:085cde657901 622
mbed_official 87:085cde657901 623 /* Disable the Output compare channel */
mbed_official 87:085cde657901 624 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
mbed_official 87:085cde657901 625
mbed_official 87:085cde657901 626 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
mbed_official 87:085cde657901 627 {
mbed_official 532:fe11edbda85c 628 /* Disable the Main Output */
mbed_official 87:085cde657901 629 __HAL_TIM_MOE_DISABLE(htim);
mbed_official 87:085cde657901 630 }
mbed_official 87:085cde657901 631
mbed_official 87:085cde657901 632 /* Disable the Peripheral */
mbed_official 87:085cde657901 633 __HAL_TIM_DISABLE(htim);
mbed_official 87:085cde657901 634
mbed_official 87:085cde657901 635 /* Return function status */
mbed_official 87:085cde657901 636 return HAL_OK;
mbed_official 87:085cde657901 637 }
mbed_official 87:085cde657901 638
mbed_official 87:085cde657901 639 /**
mbed_official 87:085cde657901 640 * @brief Starts the TIM Output Compare signal generation in interrupt mode.
mbed_official 226:b062af740e40 641 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 642 * the configuration information for TIM module.
mbed_official 226:b062af740e40 643 * @param Channel: TIM Channel to be enabled.
mbed_official 87:085cde657901 644 * This parameter can be one of the following values:
mbed_official 87:085cde657901 645 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 87:085cde657901 646 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 87:085cde657901 647 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 87:085cde657901 648 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 87:085cde657901 649 * @retval HAL status
mbed_official 87:085cde657901 650 */
mbed_official 87:085cde657901 651 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 87:085cde657901 652 {
mbed_official 87:085cde657901 653 /* Check the parameters */
mbed_official 87:085cde657901 654 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official 87:085cde657901 655
mbed_official 87:085cde657901 656 switch (Channel)
mbed_official 87:085cde657901 657 {
mbed_official 87:085cde657901 658 case TIM_CHANNEL_1:
mbed_official 87:085cde657901 659 {
mbed_official 87:085cde657901 660 /* Enable the TIM Capture/Compare 1 interrupt */
mbed_official 87:085cde657901 661 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
mbed_official 87:085cde657901 662 }
mbed_official 87:085cde657901 663 break;
mbed_official 87:085cde657901 664
mbed_official 87:085cde657901 665 case TIM_CHANNEL_2:
mbed_official 87:085cde657901 666 {
mbed_official 87:085cde657901 667 /* Enable the TIM Capture/Compare 2 interrupt */
mbed_official 87:085cde657901 668 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
mbed_official 87:085cde657901 669 }
mbed_official 87:085cde657901 670 break;
mbed_official 87:085cde657901 671
mbed_official 87:085cde657901 672 case TIM_CHANNEL_3:
mbed_official 87:085cde657901 673 {
mbed_official 87:085cde657901 674 /* Enable the TIM Capture/Compare 3 interrupt */
mbed_official 87:085cde657901 675 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
mbed_official 87:085cde657901 676 }
mbed_official 87:085cde657901 677 break;
mbed_official 87:085cde657901 678
mbed_official 87:085cde657901 679 case TIM_CHANNEL_4:
mbed_official 87:085cde657901 680 {
mbed_official 87:085cde657901 681 /* Enable the TIM Capture/Compare 4 interrupt */
mbed_official 87:085cde657901 682 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
mbed_official 87:085cde657901 683 }
mbed_official 87:085cde657901 684 break;
mbed_official 87:085cde657901 685
mbed_official 87:085cde657901 686 default:
mbed_official 87:085cde657901 687 break;
mbed_official 87:085cde657901 688 }
mbed_official 87:085cde657901 689
mbed_official 87:085cde657901 690 /* Enable the Output compare channel */
mbed_official 87:085cde657901 691 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
mbed_official 87:085cde657901 692
mbed_official 87:085cde657901 693 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
mbed_official 87:085cde657901 694 {
mbed_official 87:085cde657901 695 /* Enable the main output */
mbed_official 87:085cde657901 696 __HAL_TIM_MOE_ENABLE(htim);
mbed_official 87:085cde657901 697 }
mbed_official 87:085cde657901 698
mbed_official 87:085cde657901 699 /* Enable the Peripheral */
mbed_official 87:085cde657901 700 __HAL_TIM_ENABLE(htim);
mbed_official 87:085cde657901 701
mbed_official 87:085cde657901 702 /* Return function status */
mbed_official 87:085cde657901 703 return HAL_OK;
mbed_official 87:085cde657901 704 }
mbed_official 87:085cde657901 705
mbed_official 87:085cde657901 706 /**
mbed_official 87:085cde657901 707 * @brief Stops the TIM Output Compare signal generation in interrupt mode.
mbed_official 226:b062af740e40 708 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 709 * the configuration information for TIM module.
mbed_official 226:b062af740e40 710 * @param Channel: TIM Channel to be disabled.
mbed_official 87:085cde657901 711 * This parameter can be one of the following values:
mbed_official 87:085cde657901 712 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 87:085cde657901 713 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 87:085cde657901 714 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 87:085cde657901 715 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 87:085cde657901 716 * @retval HAL status
mbed_official 87:085cde657901 717 */
mbed_official 87:085cde657901 718 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 87:085cde657901 719 {
mbed_official 87:085cde657901 720 /* Check the parameters */
mbed_official 87:085cde657901 721 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official 87:085cde657901 722
mbed_official 87:085cde657901 723 switch (Channel)
mbed_official 87:085cde657901 724 {
mbed_official 87:085cde657901 725 case TIM_CHANNEL_1:
mbed_official 87:085cde657901 726 {
mbed_official 87:085cde657901 727 /* Disable the TIM Capture/Compare 1 interrupt */
mbed_official 87:085cde657901 728 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
mbed_official 87:085cde657901 729 }
mbed_official 87:085cde657901 730 break;
mbed_official 87:085cde657901 731
mbed_official 87:085cde657901 732 case TIM_CHANNEL_2:
mbed_official 87:085cde657901 733 {
mbed_official 87:085cde657901 734 /* Disable the TIM Capture/Compare 2 interrupt */
mbed_official 87:085cde657901 735 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
mbed_official 87:085cde657901 736 }
mbed_official 87:085cde657901 737 break;
mbed_official 87:085cde657901 738
mbed_official 87:085cde657901 739 case TIM_CHANNEL_3:
mbed_official 87:085cde657901 740 {
mbed_official 87:085cde657901 741 /* Disable the TIM Capture/Compare 3 interrupt */
mbed_official 87:085cde657901 742 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
mbed_official 87:085cde657901 743 }
mbed_official 87:085cde657901 744 break;
mbed_official 87:085cde657901 745
mbed_official 87:085cde657901 746 case TIM_CHANNEL_4:
mbed_official 87:085cde657901 747 {
mbed_official 87:085cde657901 748 /* Disable the TIM Capture/Compare 4 interrupt */
mbed_official 87:085cde657901 749 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
mbed_official 87:085cde657901 750 }
mbed_official 87:085cde657901 751 break;
mbed_official 87:085cde657901 752
mbed_official 87:085cde657901 753 default:
mbed_official 87:085cde657901 754 break;
mbed_official 87:085cde657901 755 }
mbed_official 87:085cde657901 756
mbed_official 87:085cde657901 757 /* Disable the Output compare channel */
mbed_official 87:085cde657901 758 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
mbed_official 87:085cde657901 759
mbed_official 87:085cde657901 760 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
mbed_official 87:085cde657901 761 {
mbed_official 532:fe11edbda85c 762 /* Disable the Main Output */
mbed_official 87:085cde657901 763 __HAL_TIM_MOE_DISABLE(htim);
mbed_official 87:085cde657901 764 }
mbed_official 87:085cde657901 765
mbed_official 87:085cde657901 766 /* Disable the Peripheral */
mbed_official 87:085cde657901 767 __HAL_TIM_DISABLE(htim);
mbed_official 87:085cde657901 768
mbed_official 87:085cde657901 769 /* Return function status */
mbed_official 87:085cde657901 770 return HAL_OK;
mbed_official 87:085cde657901 771 }
mbed_official 87:085cde657901 772
mbed_official 87:085cde657901 773 /**
mbed_official 87:085cde657901 774 * @brief Starts the TIM Output Compare signal generation in DMA mode.
mbed_official 226:b062af740e40 775 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 776 * the configuration information for TIM module.
mbed_official 226:b062af740e40 777 * @param Channel: TIM Channel to be enabled.
mbed_official 87:085cde657901 778 * This parameter can be one of the following values:
mbed_official 87:085cde657901 779 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 87:085cde657901 780 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 87:085cde657901 781 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 87:085cde657901 782 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 87:085cde657901 783 * @param pData: The source Buffer address.
mbed_official 87:085cde657901 784 * @param Length: The length of data to be transferred from memory to TIM peripheral
mbed_official 87:085cde657901 785 * @retval HAL status
mbed_official 87:085cde657901 786 */
mbed_official 87:085cde657901 787 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
mbed_official 87:085cde657901 788 {
mbed_official 87:085cde657901 789 /* Check the parameters */
mbed_official 87:085cde657901 790 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official 87:085cde657901 791
mbed_official 87:085cde657901 792 if((htim->State == HAL_TIM_STATE_BUSY))
mbed_official 87:085cde657901 793 {
mbed_official 87:085cde657901 794 return HAL_BUSY;
mbed_official 87:085cde657901 795 }
mbed_official 87:085cde657901 796 else if((htim->State == HAL_TIM_STATE_READY))
mbed_official 87:085cde657901 797 {
mbed_official 87:085cde657901 798 if(((uint32_t)pData == 0 ) && (Length > 0))
mbed_official 87:085cde657901 799 {
mbed_official 87:085cde657901 800 return HAL_ERROR;
mbed_official 87:085cde657901 801 }
mbed_official 87:085cde657901 802 else
mbed_official 87:085cde657901 803 {
mbed_official 87:085cde657901 804 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 87:085cde657901 805 }
mbed_official 87:085cde657901 806 }
mbed_official 87:085cde657901 807 switch (Channel)
mbed_official 87:085cde657901 808 {
mbed_official 87:085cde657901 809 case TIM_CHANNEL_1:
mbed_official 87:085cde657901 810 {
mbed_official 87:085cde657901 811 /* Set the DMA Period elapsed callback */
mbed_official 532:fe11edbda85c 812 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
mbed_official 87:085cde657901 813
mbed_official 87:085cde657901 814 /* Set the DMA error callback */
mbed_official 532:fe11edbda85c 815 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
mbed_official 87:085cde657901 816
mbed_official 87:085cde657901 817 /* Enable the DMA Stream */
mbed_official 87:085cde657901 818 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
mbed_official 87:085cde657901 819
mbed_official 87:085cde657901 820 /* Enable the TIM Capture/Compare 1 DMA request */
mbed_official 87:085cde657901 821 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
mbed_official 87:085cde657901 822 }
mbed_official 87:085cde657901 823 break;
mbed_official 87:085cde657901 824
mbed_official 87:085cde657901 825 case TIM_CHANNEL_2:
mbed_official 87:085cde657901 826 {
mbed_official 87:085cde657901 827 /* Set the DMA Period elapsed callback */
mbed_official 532:fe11edbda85c 828 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
mbed_official 87:085cde657901 829
mbed_official 87:085cde657901 830 /* Set the DMA error callback */
mbed_official 532:fe11edbda85c 831 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
mbed_official 87:085cde657901 832
mbed_official 87:085cde657901 833 /* Enable the DMA Stream */
mbed_official 87:085cde657901 834 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
mbed_official 87:085cde657901 835
mbed_official 87:085cde657901 836 /* Enable the TIM Capture/Compare 2 DMA request */
mbed_official 87:085cde657901 837 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
mbed_official 87:085cde657901 838 }
mbed_official 87:085cde657901 839 break;
mbed_official 87:085cde657901 840
mbed_official 87:085cde657901 841 case TIM_CHANNEL_3:
mbed_official 87:085cde657901 842 {
mbed_official 87:085cde657901 843 /* Set the DMA Period elapsed callback */
mbed_official 532:fe11edbda85c 844 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
mbed_official 87:085cde657901 845
mbed_official 87:085cde657901 846 /* Set the DMA error callback */
mbed_official 532:fe11edbda85c 847 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
mbed_official 87:085cde657901 848
mbed_official 87:085cde657901 849 /* Enable the DMA Stream */
mbed_official 87:085cde657901 850 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
mbed_official 87:085cde657901 851
mbed_official 87:085cde657901 852 /* Enable the TIM Capture/Compare 3 DMA request */
mbed_official 87:085cde657901 853 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
mbed_official 87:085cde657901 854 }
mbed_official 87:085cde657901 855 break;
mbed_official 87:085cde657901 856
mbed_official 87:085cde657901 857 case TIM_CHANNEL_4:
mbed_official 87:085cde657901 858 {
mbed_official 87:085cde657901 859 /* Set the DMA Period elapsed callback */
mbed_official 532:fe11edbda85c 860 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
mbed_official 87:085cde657901 861
mbed_official 87:085cde657901 862 /* Set the DMA error callback */
mbed_official 532:fe11edbda85c 863 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
mbed_official 87:085cde657901 864
mbed_official 87:085cde657901 865 /* Enable the DMA Stream */
mbed_official 87:085cde657901 866 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
mbed_official 87:085cde657901 867
mbed_official 87:085cde657901 868 /* Enable the TIM Capture/Compare 4 DMA request */
mbed_official 87:085cde657901 869 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
mbed_official 87:085cde657901 870 }
mbed_official 87:085cde657901 871 break;
mbed_official 87:085cde657901 872
mbed_official 87:085cde657901 873 default:
mbed_official 87:085cde657901 874 break;
mbed_official 87:085cde657901 875 }
mbed_official 87:085cde657901 876
mbed_official 87:085cde657901 877 /* Enable the Output compare channel */
mbed_official 87:085cde657901 878 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
mbed_official 87:085cde657901 879
mbed_official 87:085cde657901 880 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
mbed_official 87:085cde657901 881 {
mbed_official 87:085cde657901 882 /* Enable the main output */
mbed_official 87:085cde657901 883 __HAL_TIM_MOE_ENABLE(htim);
mbed_official 87:085cde657901 884 }
mbed_official 87:085cde657901 885
mbed_official 87:085cde657901 886 /* Enable the Peripheral */
mbed_official 87:085cde657901 887 __HAL_TIM_ENABLE(htim);
mbed_official 87:085cde657901 888
mbed_official 87:085cde657901 889 /* Return function status */
mbed_official 87:085cde657901 890 return HAL_OK;
mbed_official 87:085cde657901 891 }
mbed_official 87:085cde657901 892
mbed_official 87:085cde657901 893 /**
mbed_official 87:085cde657901 894 * @brief Stops the TIM Output Compare signal generation in DMA mode.
mbed_official 226:b062af740e40 895 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 896 * the configuration information for TIM module.
mbed_official 226:b062af740e40 897 * @param Channel: TIM Channel to be disabled.
mbed_official 87:085cde657901 898 * This parameter can be one of the following values:
mbed_official 87:085cde657901 899 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 87:085cde657901 900 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 87:085cde657901 901 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 87:085cde657901 902 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 87:085cde657901 903 * @retval HAL status
mbed_official 87:085cde657901 904 */
mbed_official 87:085cde657901 905 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 87:085cde657901 906 {
mbed_official 87:085cde657901 907 /* Check the parameters */
mbed_official 87:085cde657901 908 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official 87:085cde657901 909
mbed_official 87:085cde657901 910 switch (Channel)
mbed_official 87:085cde657901 911 {
mbed_official 87:085cde657901 912 case TIM_CHANNEL_1:
mbed_official 87:085cde657901 913 {
mbed_official 87:085cde657901 914 /* Disable the TIM Capture/Compare 1 DMA request */
mbed_official 87:085cde657901 915 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
mbed_official 87:085cde657901 916 }
mbed_official 87:085cde657901 917 break;
mbed_official 87:085cde657901 918
mbed_official 87:085cde657901 919 case TIM_CHANNEL_2:
mbed_official 87:085cde657901 920 {
mbed_official 87:085cde657901 921 /* Disable the TIM Capture/Compare 2 DMA request */
mbed_official 87:085cde657901 922 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
mbed_official 87:085cde657901 923 }
mbed_official 87:085cde657901 924 break;
mbed_official 87:085cde657901 925
mbed_official 87:085cde657901 926 case TIM_CHANNEL_3:
mbed_official 87:085cde657901 927 {
mbed_official 87:085cde657901 928 /* Disable the TIM Capture/Compare 3 DMA request */
mbed_official 87:085cde657901 929 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
mbed_official 87:085cde657901 930 }
mbed_official 87:085cde657901 931 break;
mbed_official 87:085cde657901 932
mbed_official 87:085cde657901 933 case TIM_CHANNEL_4:
mbed_official 87:085cde657901 934 {
mbed_official 87:085cde657901 935 /* Disable the TIM Capture/Compare 4 interrupt */
mbed_official 87:085cde657901 936 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
mbed_official 87:085cde657901 937 }
mbed_official 87:085cde657901 938 break;
mbed_official 87:085cde657901 939
mbed_official 87:085cde657901 940 default:
mbed_official 87:085cde657901 941 break;
mbed_official 87:085cde657901 942 }
mbed_official 87:085cde657901 943
mbed_official 87:085cde657901 944 /* Disable the Output compare channel */
mbed_official 87:085cde657901 945 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
mbed_official 87:085cde657901 946
mbed_official 87:085cde657901 947 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
mbed_official 87:085cde657901 948 {
mbed_official 532:fe11edbda85c 949 /* Disable the Main Output */
mbed_official 87:085cde657901 950 __HAL_TIM_MOE_DISABLE(htim);
mbed_official 87:085cde657901 951 }
mbed_official 87:085cde657901 952
mbed_official 87:085cde657901 953 /* Disable the Peripheral */
mbed_official 87:085cde657901 954 __HAL_TIM_DISABLE(htim);
mbed_official 87:085cde657901 955
mbed_official 87:085cde657901 956 /* Change the htim state */
mbed_official 87:085cde657901 957 htim->State = HAL_TIM_STATE_READY;
mbed_official 87:085cde657901 958
mbed_official 87:085cde657901 959 /* Return function status */
mbed_official 87:085cde657901 960 return HAL_OK;
mbed_official 87:085cde657901 961 }
mbed_official 87:085cde657901 962 /**
mbed_official 87:085cde657901 963 * @}
mbed_official 87:085cde657901 964 */
mbed_official 87:085cde657901 965
mbed_official 532:fe11edbda85c 966 /** @defgroup TIM_Exported_Functions_Group3 Time PWM functions
mbed_official 87:085cde657901 967 * @brief Time PWM functions
mbed_official 87:085cde657901 968 *
mbed_official 87:085cde657901 969 @verbatim
mbed_official 87:085cde657901 970 ==============================================================================
mbed_official 87:085cde657901 971 ##### Time PWM functions #####
mbed_official 87:085cde657901 972 ==============================================================================
mbed_official 87:085cde657901 973 [..]
mbed_official 87:085cde657901 974 This section provides functions allowing to:
mbed_official 87:085cde657901 975 (+) Initialize and configure the TIM OPWM.
mbed_official 87:085cde657901 976 (+) De-initialize the TIM PWM.
mbed_official 87:085cde657901 977 (+) Start the Time PWM.
mbed_official 87:085cde657901 978 (+) Stop the Time PWM.
mbed_official 87:085cde657901 979 (+) Start the Time PWM and enable interrupt.
mbed_official 87:085cde657901 980 (+) Stop the Time PWM and disable interrupt.
mbed_official 87:085cde657901 981 (+) Start the Time PWM and enable DMA transfer.
mbed_official 87:085cde657901 982 (+) Stop the Time PWM and disable DMA transfer.
mbed_official 87:085cde657901 983
mbed_official 87:085cde657901 984 @endverbatim
mbed_official 87:085cde657901 985 * @{
mbed_official 87:085cde657901 986 */
mbed_official 87:085cde657901 987 /**
mbed_official 87:085cde657901 988 * @brief Initializes the TIM PWM Time Base according to the specified
mbed_official 87:085cde657901 989 * parameters in the TIM_HandleTypeDef and create the associated handle.
mbed_official 226:b062af740e40 990 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 991 * the configuration information for TIM module.
mbed_official 87:085cde657901 992 * @retval HAL status
mbed_official 87:085cde657901 993 */
mbed_official 87:085cde657901 994 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
mbed_official 87:085cde657901 995 {
mbed_official 87:085cde657901 996 /* Check the TIM handle allocation */
mbed_official 369:2e96f1b71984 997 if(htim == HAL_NULL)
mbed_official 87:085cde657901 998 {
mbed_official 87:085cde657901 999 return HAL_ERROR;
mbed_official 87:085cde657901 1000 }
mbed_official 87:085cde657901 1001
mbed_official 87:085cde657901 1002 /* Check the parameters */
mbed_official 87:085cde657901 1003 assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official 87:085cde657901 1004 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
mbed_official 87:085cde657901 1005 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
mbed_official 87:085cde657901 1006
mbed_official 87:085cde657901 1007 if(htim->State == HAL_TIM_STATE_RESET)
mbed_official 87:085cde657901 1008 {
mbed_official 532:fe11edbda85c 1009 /* Allocate lock resource and initialize it */
mbed_official 532:fe11edbda85c 1010 htim->Lock = HAL_UNLOCKED;
mbed_official 87:085cde657901 1011 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
mbed_official 87:085cde657901 1012 HAL_TIM_PWM_MspInit(htim);
mbed_official 87:085cde657901 1013 }
mbed_official 87:085cde657901 1014
mbed_official 87:085cde657901 1015 /* Set the TIM state */
mbed_official 87:085cde657901 1016 htim->State= HAL_TIM_STATE_BUSY;
mbed_official 87:085cde657901 1017
mbed_official 87:085cde657901 1018 /* Init the base time for the PWM */
mbed_official 87:085cde657901 1019 TIM_Base_SetConfig(htim->Instance, &htim->Init);
mbed_official 87:085cde657901 1020
mbed_official 87:085cde657901 1021 /* Initialize the TIM state*/
mbed_official 87:085cde657901 1022 htim->State= HAL_TIM_STATE_READY;
mbed_official 87:085cde657901 1023
mbed_official 87:085cde657901 1024 return HAL_OK;
mbed_official 87:085cde657901 1025 }
mbed_official 87:085cde657901 1026
mbed_official 87:085cde657901 1027 /**
mbed_official 87:085cde657901 1028 * @brief DeInitializes the TIM peripheral
mbed_official 226:b062af740e40 1029 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 1030 * the configuration information for TIM module.
mbed_official 87:085cde657901 1031 * @retval HAL status
mbed_official 87:085cde657901 1032 */
mbed_official 87:085cde657901 1033 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
mbed_official 87:085cde657901 1034 {
mbed_official 87:085cde657901 1035 /* Check the parameters */
mbed_official 87:085cde657901 1036 assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official 87:085cde657901 1037
mbed_official 87:085cde657901 1038 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 87:085cde657901 1039
mbed_official 87:085cde657901 1040 /* Disable the TIM Peripheral Clock */
mbed_official 87:085cde657901 1041 __HAL_TIM_DISABLE(htim);
mbed_official 87:085cde657901 1042
mbed_official 87:085cde657901 1043 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
mbed_official 87:085cde657901 1044 HAL_TIM_PWM_MspDeInit(htim);
mbed_official 87:085cde657901 1045
mbed_official 87:085cde657901 1046 /* Change TIM state */
mbed_official 87:085cde657901 1047 htim->State = HAL_TIM_STATE_RESET;
mbed_official 106:ced8cbb51063 1048
mbed_official 106:ced8cbb51063 1049 /* Release Lock */
mbed_official 106:ced8cbb51063 1050 __HAL_UNLOCK(htim);
mbed_official 106:ced8cbb51063 1051
mbed_official 87:085cde657901 1052 return HAL_OK;
mbed_official 87:085cde657901 1053 }
mbed_official 87:085cde657901 1054
mbed_official 87:085cde657901 1055 /**
mbed_official 87:085cde657901 1056 * @brief Initializes the TIM PWM MSP.
mbed_official 226:b062af740e40 1057 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 1058 * the configuration information for TIM module.
mbed_official 87:085cde657901 1059 * @retval None
mbed_official 87:085cde657901 1060 */
mbed_official 87:085cde657901 1061 __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
mbed_official 87:085cde657901 1062 {
mbed_official 87:085cde657901 1063 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 87:085cde657901 1064 the HAL_TIM_PWM_MspInit could be implemented in the user file
mbed_official 87:085cde657901 1065 */
mbed_official 87:085cde657901 1066 }
mbed_official 87:085cde657901 1067
mbed_official 87:085cde657901 1068 /**
mbed_official 87:085cde657901 1069 * @brief DeInitializes TIM PWM MSP.
mbed_official 226:b062af740e40 1070 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 1071 * the configuration information for TIM module.
mbed_official 87:085cde657901 1072 * @retval None
mbed_official 87:085cde657901 1073 */
mbed_official 87:085cde657901 1074 __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
mbed_official 87:085cde657901 1075 {
mbed_official 87:085cde657901 1076 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 87:085cde657901 1077 the HAL_TIM_PWM_MspDeInit could be implemented in the user file
mbed_official 87:085cde657901 1078 */
mbed_official 87:085cde657901 1079 }
mbed_official 87:085cde657901 1080
mbed_official 87:085cde657901 1081 /**
mbed_official 87:085cde657901 1082 * @brief Starts the PWM signal generation.
mbed_official 226:b062af740e40 1083 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 1084 * the configuration information for TIM module.
mbed_official 226:b062af740e40 1085 * @param Channel: TIM Channels to be enabled.
mbed_official 87:085cde657901 1086 * This parameter can be one of the following values:
mbed_official 87:085cde657901 1087 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 87:085cde657901 1088 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 87:085cde657901 1089 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 87:085cde657901 1090 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 87:085cde657901 1091 * @retval HAL status
mbed_official 87:085cde657901 1092 */
mbed_official 87:085cde657901 1093 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 87:085cde657901 1094 {
mbed_official 87:085cde657901 1095 /* Check the parameters */
mbed_official 87:085cde657901 1096 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official 87:085cde657901 1097
mbed_official 87:085cde657901 1098 /* Enable the Capture compare channel */
mbed_official 87:085cde657901 1099 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
mbed_official 87:085cde657901 1100
mbed_official 87:085cde657901 1101 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
mbed_official 87:085cde657901 1102 {
mbed_official 87:085cde657901 1103 /* Enable the main output */
mbed_official 87:085cde657901 1104 __HAL_TIM_MOE_ENABLE(htim);
mbed_official 87:085cde657901 1105 }
mbed_official 87:085cde657901 1106
mbed_official 87:085cde657901 1107 /* Enable the Peripheral */
mbed_official 87:085cde657901 1108 __HAL_TIM_ENABLE(htim);
mbed_official 87:085cde657901 1109
mbed_official 87:085cde657901 1110 /* Return function status */
mbed_official 87:085cde657901 1111 return HAL_OK;
mbed_official 87:085cde657901 1112 }
mbed_official 87:085cde657901 1113
mbed_official 87:085cde657901 1114 /**
mbed_official 87:085cde657901 1115 * @brief Stops the PWM signal generation.
mbed_official 226:b062af740e40 1116 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 1117 * the configuration information for TIM module.
mbed_official 226:b062af740e40 1118 * @param Channel: TIM Channels to be disabled.
mbed_official 87:085cde657901 1119 * This parameter can be one of the following values:
mbed_official 87:085cde657901 1120 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 87:085cde657901 1121 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 87:085cde657901 1122 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 87:085cde657901 1123 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 87:085cde657901 1124 * @retval HAL status
mbed_official 87:085cde657901 1125 */
mbed_official 87:085cde657901 1126 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 87:085cde657901 1127 {
mbed_official 87:085cde657901 1128 /* Check the parameters */
mbed_official 87:085cde657901 1129 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official 87:085cde657901 1130
mbed_official 87:085cde657901 1131 /* Disable the Capture compare channel */
mbed_official 87:085cde657901 1132 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
mbed_official 87:085cde657901 1133
mbed_official 87:085cde657901 1134 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
mbed_official 87:085cde657901 1135 {
mbed_official 532:fe11edbda85c 1136 /* Disable the Main Output */
mbed_official 87:085cde657901 1137 __HAL_TIM_MOE_DISABLE(htim);
mbed_official 87:085cde657901 1138 }
mbed_official 87:085cde657901 1139
mbed_official 87:085cde657901 1140 /* Disable the Peripheral */
mbed_official 87:085cde657901 1141 __HAL_TIM_DISABLE(htim);
mbed_official 87:085cde657901 1142
mbed_official 87:085cde657901 1143 /* Change the htim state */
mbed_official 87:085cde657901 1144 htim->State = HAL_TIM_STATE_READY;
mbed_official 87:085cde657901 1145
mbed_official 87:085cde657901 1146 /* Return function status */
mbed_official 87:085cde657901 1147 return HAL_OK;
mbed_official 87:085cde657901 1148 }
mbed_official 87:085cde657901 1149
mbed_official 87:085cde657901 1150 /**
mbed_official 87:085cde657901 1151 * @brief Starts the PWM signal generation in interrupt mode.
mbed_official 226:b062af740e40 1152 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 1153 * the configuration information for TIM module.
mbed_official 226:b062af740e40 1154 * @param Channel: TIM Channel to be disabled.
mbed_official 87:085cde657901 1155 * This parameter can be one of the following values:
mbed_official 87:085cde657901 1156 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 87:085cde657901 1157 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 87:085cde657901 1158 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 87:085cde657901 1159 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 87:085cde657901 1160 * @retval HAL status
mbed_official 87:085cde657901 1161 */
mbed_official 87:085cde657901 1162 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 87:085cde657901 1163 {
mbed_official 87:085cde657901 1164 /* Check the parameters */
mbed_official 87:085cde657901 1165 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official 87:085cde657901 1166
mbed_official 87:085cde657901 1167 switch (Channel)
mbed_official 87:085cde657901 1168 {
mbed_official 87:085cde657901 1169 case TIM_CHANNEL_1:
mbed_official 87:085cde657901 1170 {
mbed_official 87:085cde657901 1171 /* Enable the TIM Capture/Compare 1 interrupt */
mbed_official 87:085cde657901 1172 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
mbed_official 87:085cde657901 1173 }
mbed_official 87:085cde657901 1174 break;
mbed_official 87:085cde657901 1175
mbed_official 87:085cde657901 1176 case TIM_CHANNEL_2:
mbed_official 87:085cde657901 1177 {
mbed_official 87:085cde657901 1178 /* Enable the TIM Capture/Compare 2 interrupt */
mbed_official 87:085cde657901 1179 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
mbed_official 87:085cde657901 1180 }
mbed_official 87:085cde657901 1181 break;
mbed_official 87:085cde657901 1182
mbed_official 87:085cde657901 1183 case TIM_CHANNEL_3:
mbed_official 87:085cde657901 1184 {
mbed_official 87:085cde657901 1185 /* Enable the TIM Capture/Compare 3 interrupt */
mbed_official 87:085cde657901 1186 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
mbed_official 87:085cde657901 1187 }
mbed_official 87:085cde657901 1188 break;
mbed_official 87:085cde657901 1189
mbed_official 87:085cde657901 1190 case TIM_CHANNEL_4:
mbed_official 87:085cde657901 1191 {
mbed_official 87:085cde657901 1192 /* Enable the TIM Capture/Compare 4 interrupt */
mbed_official 87:085cde657901 1193 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
mbed_official 87:085cde657901 1194 }
mbed_official 87:085cde657901 1195 break;
mbed_official 87:085cde657901 1196
mbed_official 87:085cde657901 1197 default:
mbed_official 87:085cde657901 1198 break;
mbed_official 87:085cde657901 1199 }
mbed_official 87:085cde657901 1200
mbed_official 87:085cde657901 1201 /* Enable the Capture compare channel */
mbed_official 87:085cde657901 1202 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
mbed_official 87:085cde657901 1203
mbed_official 87:085cde657901 1204 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
mbed_official 87:085cde657901 1205 {
mbed_official 87:085cde657901 1206 /* Enable the main output */
mbed_official 87:085cde657901 1207 __HAL_TIM_MOE_ENABLE(htim);
mbed_official 87:085cde657901 1208 }
mbed_official 87:085cde657901 1209
mbed_official 87:085cde657901 1210 /* Enable the Peripheral */
mbed_official 87:085cde657901 1211 __HAL_TIM_ENABLE(htim);
mbed_official 87:085cde657901 1212
mbed_official 87:085cde657901 1213 /* Return function status */
mbed_official 87:085cde657901 1214 return HAL_OK;
mbed_official 87:085cde657901 1215 }
mbed_official 87:085cde657901 1216
mbed_official 87:085cde657901 1217 /**
mbed_official 87:085cde657901 1218 * @brief Stops the PWM signal generation in interrupt mode.
mbed_official 226:b062af740e40 1219 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 1220 * the configuration information for TIM module.
mbed_official 226:b062af740e40 1221 * @param Channel: TIM Channels to be disabled.
mbed_official 87:085cde657901 1222 * This parameter can be one of the following values:
mbed_official 87:085cde657901 1223 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 87:085cde657901 1224 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 87:085cde657901 1225 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 87:085cde657901 1226 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 87:085cde657901 1227 * @retval HAL status
mbed_official 87:085cde657901 1228 */
mbed_official 87:085cde657901 1229 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 87:085cde657901 1230 {
mbed_official 87:085cde657901 1231 /* Check the parameters */
mbed_official 87:085cde657901 1232 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official 87:085cde657901 1233
mbed_official 87:085cde657901 1234 switch (Channel)
mbed_official 87:085cde657901 1235 {
mbed_official 87:085cde657901 1236 case TIM_CHANNEL_1:
mbed_official 87:085cde657901 1237 {
mbed_official 87:085cde657901 1238 /* Disable the TIM Capture/Compare 1 interrupt */
mbed_official 87:085cde657901 1239 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
mbed_official 87:085cde657901 1240 }
mbed_official 87:085cde657901 1241 break;
mbed_official 87:085cde657901 1242
mbed_official 87:085cde657901 1243 case TIM_CHANNEL_2:
mbed_official 87:085cde657901 1244 {
mbed_official 87:085cde657901 1245 /* Disable the TIM Capture/Compare 2 interrupt */
mbed_official 87:085cde657901 1246 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
mbed_official 87:085cde657901 1247 }
mbed_official 87:085cde657901 1248 break;
mbed_official 87:085cde657901 1249
mbed_official 87:085cde657901 1250 case TIM_CHANNEL_3:
mbed_official 87:085cde657901 1251 {
mbed_official 87:085cde657901 1252 /* Disable the TIM Capture/Compare 3 interrupt */
mbed_official 87:085cde657901 1253 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
mbed_official 87:085cde657901 1254 }
mbed_official 87:085cde657901 1255 break;
mbed_official 87:085cde657901 1256
mbed_official 87:085cde657901 1257 case TIM_CHANNEL_4:
mbed_official 87:085cde657901 1258 {
mbed_official 87:085cde657901 1259 /* Disable the TIM Capture/Compare 4 interrupt */
mbed_official 87:085cde657901 1260 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
mbed_official 87:085cde657901 1261 }
mbed_official 87:085cde657901 1262 break;
mbed_official 87:085cde657901 1263
mbed_official 87:085cde657901 1264 default:
mbed_official 87:085cde657901 1265 break;
mbed_official 87:085cde657901 1266 }
mbed_official 87:085cde657901 1267
mbed_official 87:085cde657901 1268 /* Disable the Capture compare channel */
mbed_official 87:085cde657901 1269 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
mbed_official 87:085cde657901 1270
mbed_official 87:085cde657901 1271 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
mbed_official 87:085cde657901 1272 {
mbed_official 532:fe11edbda85c 1273 /* Disable the Main Output */
mbed_official 87:085cde657901 1274 __HAL_TIM_MOE_DISABLE(htim);
mbed_official 87:085cde657901 1275 }
mbed_official 87:085cde657901 1276
mbed_official 87:085cde657901 1277 /* Disable the Peripheral */
mbed_official 87:085cde657901 1278 __HAL_TIM_DISABLE(htim);
mbed_official 87:085cde657901 1279
mbed_official 87:085cde657901 1280 /* Return function status */
mbed_official 87:085cde657901 1281 return HAL_OK;
mbed_official 87:085cde657901 1282 }
mbed_official 87:085cde657901 1283
mbed_official 87:085cde657901 1284 /**
mbed_official 87:085cde657901 1285 * @brief Starts the TIM PWM signal generation in DMA mode.
mbed_official 226:b062af740e40 1286 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 1287 * the configuration information for TIM module.
mbed_official 226:b062af740e40 1288 * @param Channel: TIM Channels to be enabled.
mbed_official 87:085cde657901 1289 * This parameter can be one of the following values:
mbed_official 87:085cde657901 1290 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 87:085cde657901 1291 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 87:085cde657901 1292 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 87:085cde657901 1293 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 87:085cde657901 1294 * @param pData: The source Buffer address.
mbed_official 87:085cde657901 1295 * @param Length: The length of data to be transferred from memory to TIM peripheral
mbed_official 87:085cde657901 1296 * @retval HAL status
mbed_official 87:085cde657901 1297 */
mbed_official 87:085cde657901 1298 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
mbed_official 87:085cde657901 1299 {
mbed_official 87:085cde657901 1300 /* Check the parameters */
mbed_official 87:085cde657901 1301 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official 87:085cde657901 1302
mbed_official 87:085cde657901 1303 if((htim->State == HAL_TIM_STATE_BUSY))
mbed_official 87:085cde657901 1304 {
mbed_official 87:085cde657901 1305 return HAL_BUSY;
mbed_official 87:085cde657901 1306 }
mbed_official 87:085cde657901 1307 else if((htim->State == HAL_TIM_STATE_READY))
mbed_official 87:085cde657901 1308 {
mbed_official 87:085cde657901 1309 if(((uint32_t)pData == 0 ) && (Length > 0))
mbed_official 87:085cde657901 1310 {
mbed_official 87:085cde657901 1311 return HAL_ERROR;
mbed_official 87:085cde657901 1312 }
mbed_official 87:085cde657901 1313 else
mbed_official 87:085cde657901 1314 {
mbed_official 87:085cde657901 1315 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 87:085cde657901 1316 }
mbed_official 87:085cde657901 1317 }
mbed_official 87:085cde657901 1318 switch (Channel)
mbed_official 87:085cde657901 1319 {
mbed_official 87:085cde657901 1320 case TIM_CHANNEL_1:
mbed_official 87:085cde657901 1321 {
mbed_official 87:085cde657901 1322 /* Set the DMA Period elapsed callback */
mbed_official 532:fe11edbda85c 1323 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
mbed_official 87:085cde657901 1324
mbed_official 87:085cde657901 1325 /* Set the DMA error callback */
mbed_official 532:fe11edbda85c 1326 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
mbed_official 87:085cde657901 1327
mbed_official 87:085cde657901 1328 /* Enable the DMA Stream */
mbed_official 87:085cde657901 1329 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
mbed_official 87:085cde657901 1330
mbed_official 87:085cde657901 1331 /* Enable the TIM Capture/Compare 1 DMA request */
mbed_official 87:085cde657901 1332 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
mbed_official 87:085cde657901 1333 }
mbed_official 87:085cde657901 1334 break;
mbed_official 87:085cde657901 1335
mbed_official 87:085cde657901 1336 case TIM_CHANNEL_2:
mbed_official 87:085cde657901 1337 {
mbed_official 87:085cde657901 1338 /* Set the DMA Period elapsed callback */
mbed_official 532:fe11edbda85c 1339 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
mbed_official 87:085cde657901 1340
mbed_official 87:085cde657901 1341 /* Set the DMA error callback */
mbed_official 532:fe11edbda85c 1342 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
mbed_official 87:085cde657901 1343
mbed_official 87:085cde657901 1344 /* Enable the DMA Stream */
mbed_official 87:085cde657901 1345 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
mbed_official 87:085cde657901 1346
mbed_official 87:085cde657901 1347 /* Enable the TIM Capture/Compare 2 DMA request */
mbed_official 87:085cde657901 1348 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
mbed_official 87:085cde657901 1349 }
mbed_official 87:085cde657901 1350 break;
mbed_official 87:085cde657901 1351
mbed_official 87:085cde657901 1352 case TIM_CHANNEL_3:
mbed_official 87:085cde657901 1353 {
mbed_official 87:085cde657901 1354 /* Set the DMA Period elapsed callback */
mbed_official 532:fe11edbda85c 1355 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
mbed_official 87:085cde657901 1356
mbed_official 87:085cde657901 1357 /* Set the DMA error callback */
mbed_official 532:fe11edbda85c 1358 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
mbed_official 87:085cde657901 1359
mbed_official 87:085cde657901 1360 /* Enable the DMA Stream */
mbed_official 87:085cde657901 1361 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
mbed_official 87:085cde657901 1362
mbed_official 87:085cde657901 1363 /* Enable the TIM Output Capture/Compare 3 request */
mbed_official 87:085cde657901 1364 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
mbed_official 87:085cde657901 1365 }
mbed_official 87:085cde657901 1366 break;
mbed_official 87:085cde657901 1367
mbed_official 87:085cde657901 1368 case TIM_CHANNEL_4:
mbed_official 87:085cde657901 1369 {
mbed_official 87:085cde657901 1370 /* Set the DMA Period elapsed callback */
mbed_official 532:fe11edbda85c 1371 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
mbed_official 87:085cde657901 1372
mbed_official 87:085cde657901 1373 /* Set the DMA error callback */
mbed_official 532:fe11edbda85c 1374 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
mbed_official 87:085cde657901 1375
mbed_official 87:085cde657901 1376 /* Enable the DMA Stream */
mbed_official 87:085cde657901 1377 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
mbed_official 87:085cde657901 1378
mbed_official 87:085cde657901 1379 /* Enable the TIM Capture/Compare 4 DMA request */
mbed_official 87:085cde657901 1380 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
mbed_official 87:085cde657901 1381 }
mbed_official 87:085cde657901 1382 break;
mbed_official 87:085cde657901 1383
mbed_official 87:085cde657901 1384 default:
mbed_official 87:085cde657901 1385 break;
mbed_official 87:085cde657901 1386 }
mbed_official 87:085cde657901 1387
mbed_official 87:085cde657901 1388 /* Enable the Capture compare channel */
mbed_official 87:085cde657901 1389 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
mbed_official 87:085cde657901 1390
mbed_official 87:085cde657901 1391 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
mbed_official 87:085cde657901 1392 {
mbed_official 87:085cde657901 1393 /* Enable the main output */
mbed_official 87:085cde657901 1394 __HAL_TIM_MOE_ENABLE(htim);
mbed_official 87:085cde657901 1395 }
mbed_official 87:085cde657901 1396
mbed_official 87:085cde657901 1397 /* Enable the Peripheral */
mbed_official 87:085cde657901 1398 __HAL_TIM_ENABLE(htim);
mbed_official 87:085cde657901 1399
mbed_official 87:085cde657901 1400 /* Return function status */
mbed_official 87:085cde657901 1401 return HAL_OK;
mbed_official 87:085cde657901 1402 }
mbed_official 87:085cde657901 1403
mbed_official 87:085cde657901 1404 /**
mbed_official 87:085cde657901 1405 * @brief Stops the TIM PWM signal generation in DMA mode.
mbed_official 226:b062af740e40 1406 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 1407 * the configuration information for TIM module.
mbed_official 226:b062af740e40 1408 * @param Channel: TIM Channels to be disabled.
mbed_official 87:085cde657901 1409 * This parameter can be one of the following values:
mbed_official 87:085cde657901 1410 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 87:085cde657901 1411 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 87:085cde657901 1412 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 87:085cde657901 1413 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 87:085cde657901 1414 * @retval HAL status
mbed_official 87:085cde657901 1415 */
mbed_official 87:085cde657901 1416 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 87:085cde657901 1417 {
mbed_official 87:085cde657901 1418 /* Check the parameters */
mbed_official 87:085cde657901 1419 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official 87:085cde657901 1420
mbed_official 87:085cde657901 1421 switch (Channel)
mbed_official 87:085cde657901 1422 {
mbed_official 87:085cde657901 1423 case TIM_CHANNEL_1:
mbed_official 87:085cde657901 1424 {
mbed_official 87:085cde657901 1425 /* Disable the TIM Capture/Compare 1 DMA request */
mbed_official 87:085cde657901 1426 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
mbed_official 87:085cde657901 1427 }
mbed_official 87:085cde657901 1428 break;
mbed_official 87:085cde657901 1429
mbed_official 87:085cde657901 1430 case TIM_CHANNEL_2:
mbed_official 87:085cde657901 1431 {
mbed_official 87:085cde657901 1432 /* Disable the TIM Capture/Compare 2 DMA request */
mbed_official 87:085cde657901 1433 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
mbed_official 87:085cde657901 1434 }
mbed_official 87:085cde657901 1435 break;
mbed_official 87:085cde657901 1436
mbed_official 87:085cde657901 1437 case TIM_CHANNEL_3:
mbed_official 87:085cde657901 1438 {
mbed_official 87:085cde657901 1439 /* Disable the TIM Capture/Compare 3 DMA request */
mbed_official 87:085cde657901 1440 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
mbed_official 87:085cde657901 1441 }
mbed_official 87:085cde657901 1442 break;
mbed_official 87:085cde657901 1443
mbed_official 87:085cde657901 1444 case TIM_CHANNEL_4:
mbed_official 87:085cde657901 1445 {
mbed_official 87:085cde657901 1446 /* Disable the TIM Capture/Compare 4 interrupt */
mbed_official 87:085cde657901 1447 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
mbed_official 87:085cde657901 1448 }
mbed_official 87:085cde657901 1449 break;
mbed_official 87:085cde657901 1450
mbed_official 87:085cde657901 1451 default:
mbed_official 87:085cde657901 1452 break;
mbed_official 87:085cde657901 1453 }
mbed_official 87:085cde657901 1454
mbed_official 87:085cde657901 1455 /* Disable the Capture compare channel */
mbed_official 87:085cde657901 1456 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
mbed_official 87:085cde657901 1457
mbed_official 87:085cde657901 1458 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
mbed_official 87:085cde657901 1459 {
mbed_official 532:fe11edbda85c 1460 /* Disable the Main Output */
mbed_official 87:085cde657901 1461 __HAL_TIM_MOE_DISABLE(htim);
mbed_official 87:085cde657901 1462 }
mbed_official 87:085cde657901 1463
mbed_official 87:085cde657901 1464 /* Disable the Peripheral */
mbed_official 87:085cde657901 1465 __HAL_TIM_DISABLE(htim);
mbed_official 87:085cde657901 1466
mbed_official 87:085cde657901 1467 /* Change the htim state */
mbed_official 87:085cde657901 1468 htim->State = HAL_TIM_STATE_READY;
mbed_official 87:085cde657901 1469
mbed_official 87:085cde657901 1470 /* Return function status */
mbed_official 87:085cde657901 1471 return HAL_OK;
mbed_official 87:085cde657901 1472 }
mbed_official 87:085cde657901 1473 /**
mbed_official 87:085cde657901 1474 * @}
mbed_official 87:085cde657901 1475 */
mbed_official 87:085cde657901 1476
mbed_official 532:fe11edbda85c 1477 /** @defgroup TIM_Exported_Functions_Group4 Time Input Capture functions
mbed_official 87:085cde657901 1478 * @brief Time Input Capture functions
mbed_official 87:085cde657901 1479 *
mbed_official 87:085cde657901 1480 @verbatim
mbed_official 87:085cde657901 1481 ==============================================================================
mbed_official 87:085cde657901 1482 ##### Time Input Capture functions #####
mbed_official 87:085cde657901 1483 ==============================================================================
mbed_official 87:085cde657901 1484 [..]
mbed_official 87:085cde657901 1485 This section provides functions allowing to:
mbed_official 87:085cde657901 1486 (+) Initialize and configure the TIM Input Capture.
mbed_official 87:085cde657901 1487 (+) De-initialize the TIM Input Capture.
mbed_official 87:085cde657901 1488 (+) Start the Time Input Capture.
mbed_official 87:085cde657901 1489 (+) Stop the Time Input Capture.
mbed_official 87:085cde657901 1490 (+) Start the Time Input Capture and enable interrupt.
mbed_official 87:085cde657901 1491 (+) Stop the Time Input Capture and disable interrupt.
mbed_official 87:085cde657901 1492 (+) Start the Time Input Capture and enable DMA transfer.
mbed_official 87:085cde657901 1493 (+) Stop the Time Input Capture and disable DMA transfer.
mbed_official 87:085cde657901 1494
mbed_official 87:085cde657901 1495 @endverbatim
mbed_official 87:085cde657901 1496 * @{
mbed_official 87:085cde657901 1497 */
mbed_official 87:085cde657901 1498 /**
mbed_official 87:085cde657901 1499 * @brief Initializes the TIM Input Capture Time base according to the specified
mbed_official 87:085cde657901 1500 * parameters in the TIM_HandleTypeDef and create the associated handle.
mbed_official 226:b062af740e40 1501 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 1502 * the configuration information for TIM module.
mbed_official 87:085cde657901 1503 * @retval HAL status
mbed_official 87:085cde657901 1504 */
mbed_official 87:085cde657901 1505 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
mbed_official 87:085cde657901 1506 {
mbed_official 87:085cde657901 1507 /* Check the TIM handle allocation */
mbed_official 369:2e96f1b71984 1508 if(htim == HAL_NULL)
mbed_official 87:085cde657901 1509 {
mbed_official 87:085cde657901 1510 return HAL_ERROR;
mbed_official 87:085cde657901 1511 }
mbed_official 87:085cde657901 1512
mbed_official 87:085cde657901 1513 /* Check the parameters */
mbed_official 87:085cde657901 1514 assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official 87:085cde657901 1515 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
mbed_official 87:085cde657901 1516 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
mbed_official 87:085cde657901 1517
mbed_official 87:085cde657901 1518 if(htim->State == HAL_TIM_STATE_RESET)
mbed_official 532:fe11edbda85c 1519 {
mbed_official 532:fe11edbda85c 1520 /* Allocate lock resource and initialize it */
mbed_official 532:fe11edbda85c 1521 htim->Lock = HAL_UNLOCKED;
mbed_official 87:085cde657901 1522 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
mbed_official 87:085cde657901 1523 HAL_TIM_IC_MspInit(htim);
mbed_official 87:085cde657901 1524 }
mbed_official 87:085cde657901 1525
mbed_official 87:085cde657901 1526 /* Set the TIM state */
mbed_official 87:085cde657901 1527 htim->State= HAL_TIM_STATE_BUSY;
mbed_official 87:085cde657901 1528
mbed_official 87:085cde657901 1529 /* Init the base time for the input capture */
mbed_official 87:085cde657901 1530 TIM_Base_SetConfig(htim->Instance, &htim->Init);
mbed_official 87:085cde657901 1531
mbed_official 87:085cde657901 1532 /* Initialize the TIM state*/
mbed_official 87:085cde657901 1533 htim->State= HAL_TIM_STATE_READY;
mbed_official 87:085cde657901 1534
mbed_official 87:085cde657901 1535 return HAL_OK;
mbed_official 87:085cde657901 1536 }
mbed_official 87:085cde657901 1537
mbed_official 87:085cde657901 1538 /**
mbed_official 87:085cde657901 1539 * @brief DeInitializes the TIM peripheral
mbed_official 226:b062af740e40 1540 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 1541 * the configuration information for TIM module.
mbed_official 87:085cde657901 1542 * @retval HAL status
mbed_official 87:085cde657901 1543 */
mbed_official 87:085cde657901 1544 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
mbed_official 87:085cde657901 1545 {
mbed_official 87:085cde657901 1546 /* Check the parameters */
mbed_official 87:085cde657901 1547 assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official 87:085cde657901 1548
mbed_official 87:085cde657901 1549 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 87:085cde657901 1550
mbed_official 87:085cde657901 1551 /* Disable the TIM Peripheral Clock */
mbed_official 87:085cde657901 1552 __HAL_TIM_DISABLE(htim);
mbed_official 87:085cde657901 1553
mbed_official 87:085cde657901 1554 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
mbed_official 87:085cde657901 1555 HAL_TIM_IC_MspDeInit(htim);
mbed_official 87:085cde657901 1556
mbed_official 87:085cde657901 1557 /* Change TIM state */
mbed_official 87:085cde657901 1558 htim->State = HAL_TIM_STATE_RESET;
mbed_official 106:ced8cbb51063 1559
mbed_official 106:ced8cbb51063 1560 /* Release Lock */
mbed_official 106:ced8cbb51063 1561 __HAL_UNLOCK(htim);
mbed_official 106:ced8cbb51063 1562
mbed_official 87:085cde657901 1563 return HAL_OK;
mbed_official 87:085cde657901 1564 }
mbed_official 87:085cde657901 1565
mbed_official 87:085cde657901 1566 /**
mbed_official 87:085cde657901 1567 * @brief Initializes the TIM INput Capture MSP.
mbed_official 226:b062af740e40 1568 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 1569 * the configuration information for TIM module.
mbed_official 87:085cde657901 1570 * @retval None
mbed_official 87:085cde657901 1571 */
mbed_official 87:085cde657901 1572 __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
mbed_official 87:085cde657901 1573 {
mbed_official 87:085cde657901 1574 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 87:085cde657901 1575 the HAL_TIM_IC_MspInit could be implemented in the user file
mbed_official 87:085cde657901 1576 */
mbed_official 87:085cde657901 1577 }
mbed_official 87:085cde657901 1578
mbed_official 87:085cde657901 1579 /**
mbed_official 87:085cde657901 1580 * @brief DeInitializes TIM Input Capture MSP.
mbed_official 226:b062af740e40 1581 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 1582 * the configuration information for TIM module.
mbed_official 87:085cde657901 1583 * @retval None
mbed_official 87:085cde657901 1584 */
mbed_official 87:085cde657901 1585 __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
mbed_official 87:085cde657901 1586 {
mbed_official 87:085cde657901 1587 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 87:085cde657901 1588 the HAL_TIM_IC_MspDeInit could be implemented in the user file
mbed_official 87:085cde657901 1589 */
mbed_official 87:085cde657901 1590 }
mbed_official 87:085cde657901 1591
mbed_official 87:085cde657901 1592 /**
mbed_official 87:085cde657901 1593 * @brief Starts the TIM Input Capture measurement.
mbed_official 226:b062af740e40 1594 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 1595 * the configuration information for TIM module.
mbed_official 226:b062af740e40 1596 * @param Channel: TIM Channels to be enabled.
mbed_official 87:085cde657901 1597 * This parameter can be one of the following values:
mbed_official 87:085cde657901 1598 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 87:085cde657901 1599 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 87:085cde657901 1600 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 87:085cde657901 1601 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 87:085cde657901 1602 * @retval HAL status
mbed_official 87:085cde657901 1603 */
mbed_official 87:085cde657901 1604 HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 87:085cde657901 1605 {
mbed_official 87:085cde657901 1606 /* Check the parameters */
mbed_official 87:085cde657901 1607 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official 87:085cde657901 1608
mbed_official 87:085cde657901 1609 /* Enable the Input Capture channel */
mbed_official 87:085cde657901 1610 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
mbed_official 87:085cde657901 1611
mbed_official 87:085cde657901 1612 /* Enable the Peripheral */
mbed_official 87:085cde657901 1613 __HAL_TIM_ENABLE(htim);
mbed_official 87:085cde657901 1614
mbed_official 87:085cde657901 1615 /* Return function status */
mbed_official 87:085cde657901 1616 return HAL_OK;
mbed_official 87:085cde657901 1617 }
mbed_official 87:085cde657901 1618
mbed_official 87:085cde657901 1619 /**
mbed_official 87:085cde657901 1620 * @brief Stops the TIM Input Capture measurement.
mbed_official 226:b062af740e40 1621 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 1622 * the configuration information for TIM module.
mbed_official 226:b062af740e40 1623 * @param Channel: TIM Channels to be disabled.
mbed_official 87:085cde657901 1624 * This parameter can be one of the following values:
mbed_official 87:085cde657901 1625 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 87:085cde657901 1626 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 87:085cde657901 1627 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 87:085cde657901 1628 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 87:085cde657901 1629 * @retval HAL status
mbed_official 87:085cde657901 1630 */
mbed_official 87:085cde657901 1631 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 87:085cde657901 1632 {
mbed_official 87:085cde657901 1633 /* Check the parameters */
mbed_official 87:085cde657901 1634 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official 87:085cde657901 1635
mbed_official 87:085cde657901 1636 /* Disable the Input Capture channel */
mbed_official 87:085cde657901 1637 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
mbed_official 87:085cde657901 1638
mbed_official 87:085cde657901 1639 /* Disable the Peripheral */
mbed_official 87:085cde657901 1640 __HAL_TIM_DISABLE(htim);
mbed_official 87:085cde657901 1641
mbed_official 87:085cde657901 1642 /* Return function status */
mbed_official 87:085cde657901 1643 return HAL_OK;
mbed_official 87:085cde657901 1644 }
mbed_official 87:085cde657901 1645
mbed_official 87:085cde657901 1646 /**
mbed_official 87:085cde657901 1647 * @brief Starts the TIM Input Capture measurement in interrupt mode.
mbed_official 226:b062af740e40 1648 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 1649 * the configuration information for TIM module.
mbed_official 226:b062af740e40 1650 * @param Channel: TIM Channels to be enabled.
mbed_official 87:085cde657901 1651 * This parameter can be one of the following values:
mbed_official 87:085cde657901 1652 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 87:085cde657901 1653 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 87:085cde657901 1654 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 87:085cde657901 1655 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 87:085cde657901 1656 * @retval HAL status
mbed_official 87:085cde657901 1657 */
mbed_official 87:085cde657901 1658 HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 87:085cde657901 1659 {
mbed_official 87:085cde657901 1660 /* Check the parameters */
mbed_official 87:085cde657901 1661 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official 87:085cde657901 1662
mbed_official 87:085cde657901 1663 switch (Channel)
mbed_official 87:085cde657901 1664 {
mbed_official 87:085cde657901 1665 case TIM_CHANNEL_1:
mbed_official 87:085cde657901 1666 {
mbed_official 87:085cde657901 1667 /* Enable the TIM Capture/Compare 1 interrupt */
mbed_official 87:085cde657901 1668 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
mbed_official 87:085cde657901 1669 }
mbed_official 87:085cde657901 1670 break;
mbed_official 87:085cde657901 1671
mbed_official 87:085cde657901 1672 case TIM_CHANNEL_2:
mbed_official 87:085cde657901 1673 {
mbed_official 87:085cde657901 1674 /* Enable the TIM Capture/Compare 2 interrupt */
mbed_official 87:085cde657901 1675 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
mbed_official 87:085cde657901 1676 }
mbed_official 87:085cde657901 1677 break;
mbed_official 87:085cde657901 1678
mbed_official 87:085cde657901 1679 case TIM_CHANNEL_3:
mbed_official 87:085cde657901 1680 {
mbed_official 87:085cde657901 1681 /* Enable the TIM Capture/Compare 3 interrupt */
mbed_official 87:085cde657901 1682 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
mbed_official 87:085cde657901 1683 }
mbed_official 87:085cde657901 1684 break;
mbed_official 87:085cde657901 1685
mbed_official 87:085cde657901 1686 case TIM_CHANNEL_4:
mbed_official 87:085cde657901 1687 {
mbed_official 87:085cde657901 1688 /* Enable the TIM Capture/Compare 4 interrupt */
mbed_official 87:085cde657901 1689 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
mbed_official 87:085cde657901 1690 }
mbed_official 87:085cde657901 1691 break;
mbed_official 87:085cde657901 1692
mbed_official 87:085cde657901 1693 default:
mbed_official 87:085cde657901 1694 break;
mbed_official 87:085cde657901 1695 }
mbed_official 87:085cde657901 1696 /* Enable the Input Capture channel */
mbed_official 87:085cde657901 1697 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
mbed_official 87:085cde657901 1698
mbed_official 87:085cde657901 1699 /* Enable the Peripheral */
mbed_official 87:085cde657901 1700 __HAL_TIM_ENABLE(htim);
mbed_official 87:085cde657901 1701
mbed_official 87:085cde657901 1702 /* Return function status */
mbed_official 87:085cde657901 1703 return HAL_OK;
mbed_official 87:085cde657901 1704 }
mbed_official 87:085cde657901 1705
mbed_official 87:085cde657901 1706 /**
mbed_official 87:085cde657901 1707 * @brief Stops the TIM Input Capture measurement in interrupt mode.
mbed_official 226:b062af740e40 1708 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 1709 * the configuration information for TIM module.
mbed_official 226:b062af740e40 1710 * @param Channel: TIM Channels to be disabled.
mbed_official 87:085cde657901 1711 * This parameter can be one of the following values:
mbed_official 87:085cde657901 1712 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 87:085cde657901 1713 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 87:085cde657901 1714 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 87:085cde657901 1715 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 87:085cde657901 1716 * @retval HAL status
mbed_official 87:085cde657901 1717 */
mbed_official 87:085cde657901 1718 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 87:085cde657901 1719 {
mbed_official 87:085cde657901 1720 /* Check the parameters */
mbed_official 87:085cde657901 1721 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official 87:085cde657901 1722
mbed_official 87:085cde657901 1723 switch (Channel)
mbed_official 87:085cde657901 1724 {
mbed_official 87:085cde657901 1725 case TIM_CHANNEL_1:
mbed_official 87:085cde657901 1726 {
mbed_official 87:085cde657901 1727 /* Disable the TIM Capture/Compare 1 interrupt */
mbed_official 87:085cde657901 1728 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
mbed_official 87:085cde657901 1729 }
mbed_official 87:085cde657901 1730 break;
mbed_official 87:085cde657901 1731
mbed_official 87:085cde657901 1732 case TIM_CHANNEL_2:
mbed_official 87:085cde657901 1733 {
mbed_official 87:085cde657901 1734 /* Disable the TIM Capture/Compare 2 interrupt */
mbed_official 87:085cde657901 1735 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
mbed_official 87:085cde657901 1736 }
mbed_official 87:085cde657901 1737 break;
mbed_official 87:085cde657901 1738
mbed_official 87:085cde657901 1739 case TIM_CHANNEL_3:
mbed_official 87:085cde657901 1740 {
mbed_official 87:085cde657901 1741 /* Disable the TIM Capture/Compare 3 interrupt */
mbed_official 87:085cde657901 1742 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
mbed_official 87:085cde657901 1743 }
mbed_official 87:085cde657901 1744 break;
mbed_official 87:085cde657901 1745
mbed_official 87:085cde657901 1746 case TIM_CHANNEL_4:
mbed_official 87:085cde657901 1747 {
mbed_official 87:085cde657901 1748 /* Disable the TIM Capture/Compare 4 interrupt */
mbed_official 87:085cde657901 1749 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
mbed_official 87:085cde657901 1750 }
mbed_official 87:085cde657901 1751 break;
mbed_official 87:085cde657901 1752
mbed_official 87:085cde657901 1753 default:
mbed_official 87:085cde657901 1754 break;
mbed_official 87:085cde657901 1755 }
mbed_official 87:085cde657901 1756
mbed_official 87:085cde657901 1757 /* Disable the Input Capture channel */
mbed_official 87:085cde657901 1758 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
mbed_official 87:085cde657901 1759
mbed_official 87:085cde657901 1760 /* Disable the Peripheral */
mbed_official 87:085cde657901 1761 __HAL_TIM_DISABLE(htim);
mbed_official 87:085cde657901 1762
mbed_official 87:085cde657901 1763 /* Return function status */
mbed_official 87:085cde657901 1764 return HAL_OK;
mbed_official 87:085cde657901 1765 }
mbed_official 87:085cde657901 1766
mbed_official 87:085cde657901 1767 /**
mbed_official 87:085cde657901 1768 * @brief Starts the TIM Input Capture measurement on in DMA mode.
mbed_official 226:b062af740e40 1769 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 1770 * the configuration information for TIM module.
mbed_official 226:b062af740e40 1771 * @param Channel: TIM Channels to be enabled.
mbed_official 87:085cde657901 1772 * This parameter can be one of the following values:
mbed_official 87:085cde657901 1773 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 87:085cde657901 1774 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 87:085cde657901 1775 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 87:085cde657901 1776 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 87:085cde657901 1777 * @param pData: The destination Buffer address.
mbed_official 87:085cde657901 1778 * @param Length: The length of data to be transferred from TIM peripheral to memory.
mbed_official 87:085cde657901 1779 * @retval HAL status
mbed_official 87:085cde657901 1780 */
mbed_official 87:085cde657901 1781 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
mbed_official 87:085cde657901 1782 {
mbed_official 87:085cde657901 1783 /* Check the parameters */
mbed_official 87:085cde657901 1784 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official 87:085cde657901 1785 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
mbed_official 87:085cde657901 1786
mbed_official 87:085cde657901 1787 if((htim->State == HAL_TIM_STATE_BUSY))
mbed_official 87:085cde657901 1788 {
mbed_official 87:085cde657901 1789 return HAL_BUSY;
mbed_official 87:085cde657901 1790 }
mbed_official 87:085cde657901 1791 else if((htim->State == HAL_TIM_STATE_READY))
mbed_official 87:085cde657901 1792 {
mbed_official 87:085cde657901 1793 if((pData == 0 ) && (Length > 0))
mbed_official 87:085cde657901 1794 {
mbed_official 87:085cde657901 1795 return HAL_ERROR;
mbed_official 87:085cde657901 1796 }
mbed_official 87:085cde657901 1797 else
mbed_official 87:085cde657901 1798 {
mbed_official 87:085cde657901 1799 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 87:085cde657901 1800 }
mbed_official 87:085cde657901 1801 }
mbed_official 87:085cde657901 1802
mbed_official 87:085cde657901 1803 switch (Channel)
mbed_official 87:085cde657901 1804 {
mbed_official 87:085cde657901 1805 case TIM_CHANNEL_1:
mbed_official 87:085cde657901 1806 {
mbed_official 87:085cde657901 1807 /* Set the DMA Period elapsed callback */
mbed_official 532:fe11edbda85c 1808 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
mbed_official 87:085cde657901 1809
mbed_official 87:085cde657901 1810 /* Set the DMA error callback */
mbed_official 532:fe11edbda85c 1811 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
mbed_official 87:085cde657901 1812
mbed_official 87:085cde657901 1813 /* Enable the DMA Stream */
mbed_official 87:085cde657901 1814 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
mbed_official 87:085cde657901 1815
mbed_official 87:085cde657901 1816 /* Enable the TIM Capture/Compare 1 DMA request */
mbed_official 87:085cde657901 1817 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
mbed_official 87:085cde657901 1818 }
mbed_official 87:085cde657901 1819 break;
mbed_official 87:085cde657901 1820
mbed_official 87:085cde657901 1821 case TIM_CHANNEL_2:
mbed_official 87:085cde657901 1822 {
mbed_official 87:085cde657901 1823 /* Set the DMA Period elapsed callback */
mbed_official 532:fe11edbda85c 1824 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
mbed_official 87:085cde657901 1825
mbed_official 87:085cde657901 1826 /* Set the DMA error callback */
mbed_official 532:fe11edbda85c 1827 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
mbed_official 87:085cde657901 1828
mbed_official 87:085cde657901 1829 /* Enable the DMA Stream */
mbed_official 87:085cde657901 1830 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length);
mbed_official 87:085cde657901 1831
mbed_official 87:085cde657901 1832 /* Enable the TIM Capture/Compare 2 DMA request */
mbed_official 87:085cde657901 1833 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
mbed_official 87:085cde657901 1834 }
mbed_official 87:085cde657901 1835 break;
mbed_official 87:085cde657901 1836
mbed_official 87:085cde657901 1837 case TIM_CHANNEL_3:
mbed_official 87:085cde657901 1838 {
mbed_official 87:085cde657901 1839 /* Set the DMA Period elapsed callback */
mbed_official 532:fe11edbda85c 1840 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
mbed_official 87:085cde657901 1841
mbed_official 87:085cde657901 1842 /* Set the DMA error callback */
mbed_official 532:fe11edbda85c 1843 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
mbed_official 87:085cde657901 1844
mbed_official 87:085cde657901 1845 /* Enable the DMA Stream */
mbed_official 87:085cde657901 1846 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length);
mbed_official 87:085cde657901 1847
mbed_official 87:085cde657901 1848 /* Enable the TIM Capture/Compare 3 DMA request */
mbed_official 87:085cde657901 1849 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
mbed_official 87:085cde657901 1850 }
mbed_official 87:085cde657901 1851 break;
mbed_official 87:085cde657901 1852
mbed_official 87:085cde657901 1853 case TIM_CHANNEL_4:
mbed_official 87:085cde657901 1854 {
mbed_official 87:085cde657901 1855 /* Set the DMA Period elapsed callback */
mbed_official 532:fe11edbda85c 1856 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
mbed_official 87:085cde657901 1857
mbed_official 87:085cde657901 1858 /* Set the DMA error callback */
mbed_official 532:fe11edbda85c 1859 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
mbed_official 87:085cde657901 1860
mbed_official 87:085cde657901 1861 /* Enable the DMA Stream */
mbed_official 87:085cde657901 1862 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length);
mbed_official 87:085cde657901 1863
mbed_official 87:085cde657901 1864 /* Enable the TIM Capture/Compare 4 DMA request */
mbed_official 87:085cde657901 1865 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
mbed_official 87:085cde657901 1866 }
mbed_official 87:085cde657901 1867 break;
mbed_official 87:085cde657901 1868
mbed_official 87:085cde657901 1869 default:
mbed_official 87:085cde657901 1870 break;
mbed_official 87:085cde657901 1871 }
mbed_official 87:085cde657901 1872
mbed_official 87:085cde657901 1873 /* Enable the Input Capture channel */
mbed_official 87:085cde657901 1874 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
mbed_official 87:085cde657901 1875
mbed_official 87:085cde657901 1876 /* Enable the Peripheral */
mbed_official 87:085cde657901 1877 __HAL_TIM_ENABLE(htim);
mbed_official 87:085cde657901 1878
mbed_official 87:085cde657901 1879 /* Return function status */
mbed_official 87:085cde657901 1880 return HAL_OK;
mbed_official 87:085cde657901 1881 }
mbed_official 87:085cde657901 1882
mbed_official 87:085cde657901 1883 /**
mbed_official 87:085cde657901 1884 * @brief Stops the TIM Input Capture measurement on in DMA mode.
mbed_official 226:b062af740e40 1885 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 1886 * the configuration information for TIM module.
mbed_official 226:b062af740e40 1887 * @param Channel: TIM Channels to be disabled.
mbed_official 87:085cde657901 1888 * This parameter can be one of the following values:
mbed_official 87:085cde657901 1889 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 87:085cde657901 1890 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 87:085cde657901 1891 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 87:085cde657901 1892 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 87:085cde657901 1893 * @retval HAL status
mbed_official 87:085cde657901 1894 */
mbed_official 87:085cde657901 1895 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 87:085cde657901 1896 {
mbed_official 87:085cde657901 1897 /* Check the parameters */
mbed_official 87:085cde657901 1898 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
mbed_official 87:085cde657901 1899 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
mbed_official 87:085cde657901 1900
mbed_official 87:085cde657901 1901 switch (Channel)
mbed_official 87:085cde657901 1902 {
mbed_official 87:085cde657901 1903 case TIM_CHANNEL_1:
mbed_official 87:085cde657901 1904 {
mbed_official 87:085cde657901 1905 /* Disable the TIM Capture/Compare 1 DMA request */
mbed_official 87:085cde657901 1906 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
mbed_official 87:085cde657901 1907 }
mbed_official 87:085cde657901 1908 break;
mbed_official 87:085cde657901 1909
mbed_official 87:085cde657901 1910 case TIM_CHANNEL_2:
mbed_official 87:085cde657901 1911 {
mbed_official 87:085cde657901 1912 /* Disable the TIM Capture/Compare 2 DMA request */
mbed_official 87:085cde657901 1913 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
mbed_official 87:085cde657901 1914 }
mbed_official 87:085cde657901 1915 break;
mbed_official 87:085cde657901 1916
mbed_official 87:085cde657901 1917 case TIM_CHANNEL_3:
mbed_official 87:085cde657901 1918 {
mbed_official 87:085cde657901 1919 /* Disable the TIM Capture/Compare 3 DMA request */
mbed_official 87:085cde657901 1920 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
mbed_official 87:085cde657901 1921 }
mbed_official 87:085cde657901 1922 break;
mbed_official 87:085cde657901 1923
mbed_official 87:085cde657901 1924 case TIM_CHANNEL_4:
mbed_official 87:085cde657901 1925 {
mbed_official 87:085cde657901 1926 /* Disable the TIM Capture/Compare 4 DMA request */
mbed_official 87:085cde657901 1927 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
mbed_official 87:085cde657901 1928 }
mbed_official 87:085cde657901 1929 break;
mbed_official 87:085cde657901 1930
mbed_official 87:085cde657901 1931 default:
mbed_official 87:085cde657901 1932 break;
mbed_official 87:085cde657901 1933 }
mbed_official 87:085cde657901 1934
mbed_official 87:085cde657901 1935 /* Disable the Input Capture channel */
mbed_official 87:085cde657901 1936 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
mbed_official 87:085cde657901 1937
mbed_official 87:085cde657901 1938 /* Disable the Peripheral */
mbed_official 87:085cde657901 1939 __HAL_TIM_DISABLE(htim);
mbed_official 87:085cde657901 1940
mbed_official 87:085cde657901 1941 /* Change the htim state */
mbed_official 87:085cde657901 1942 htim->State = HAL_TIM_STATE_READY;
mbed_official 87:085cde657901 1943
mbed_official 87:085cde657901 1944 /* Return function status */
mbed_official 87:085cde657901 1945 return HAL_OK;
mbed_official 87:085cde657901 1946 }
mbed_official 87:085cde657901 1947 /**
mbed_official 87:085cde657901 1948 * @}
mbed_official 87:085cde657901 1949 */
mbed_official 87:085cde657901 1950
mbed_official 532:fe11edbda85c 1951 /** @defgroup TIM_Exported_Functions_Group5 Time One Pulse functions
mbed_official 87:085cde657901 1952 * @brief Time One Pulse functions
mbed_official 87:085cde657901 1953 *
mbed_official 87:085cde657901 1954 @verbatim
mbed_official 87:085cde657901 1955 ==============================================================================
mbed_official 87:085cde657901 1956 ##### Time One Pulse functions #####
mbed_official 87:085cde657901 1957 ==============================================================================
mbed_official 87:085cde657901 1958 [..]
mbed_official 87:085cde657901 1959 This section provides functions allowing to:
mbed_official 87:085cde657901 1960 (+) Initialize and configure the TIM One Pulse.
mbed_official 87:085cde657901 1961 (+) De-initialize the TIM One Pulse.
mbed_official 87:085cde657901 1962 (+) Start the Time One Pulse.
mbed_official 87:085cde657901 1963 (+) Stop the Time One Pulse.
mbed_official 87:085cde657901 1964 (+) Start the Time One Pulse and enable interrupt.
mbed_official 87:085cde657901 1965 (+) Stop the Time One Pulse and disable interrupt.
mbed_official 87:085cde657901 1966 (+) Start the Time One Pulse and enable DMA transfer.
mbed_official 87:085cde657901 1967 (+) Stop the Time One Pulse and disable DMA transfer.
mbed_official 87:085cde657901 1968
mbed_official 87:085cde657901 1969 @endverbatim
mbed_official 87:085cde657901 1970 * @{
mbed_official 87:085cde657901 1971 */
mbed_official 87:085cde657901 1972 /**
mbed_official 87:085cde657901 1973 * @brief Initializes the TIM One Pulse Time Base according to the specified
mbed_official 87:085cde657901 1974 * parameters in the TIM_HandleTypeDef and create the associated handle.
mbed_official 226:b062af740e40 1975 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 1976 * the configuration information for TIM module.
mbed_official 87:085cde657901 1977 * @param OnePulseMode: Select the One pulse mode.
mbed_official 87:085cde657901 1978 * This parameter can be one of the following values:
mbed_official 87:085cde657901 1979 * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
mbed_official 532:fe11edbda85c 1980 * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated.
mbed_official 87:085cde657901 1981 * @retval HAL status
mbed_official 87:085cde657901 1982 */
mbed_official 87:085cde657901 1983 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
mbed_official 87:085cde657901 1984 {
mbed_official 87:085cde657901 1985 /* Check the TIM handle allocation */
mbed_official 369:2e96f1b71984 1986 if(htim == HAL_NULL)
mbed_official 87:085cde657901 1987 {
mbed_official 87:085cde657901 1988 return HAL_ERROR;
mbed_official 87:085cde657901 1989 }
mbed_official 87:085cde657901 1990
mbed_official 87:085cde657901 1991 /* Check the parameters */
mbed_official 87:085cde657901 1992 assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official 87:085cde657901 1993 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
mbed_official 87:085cde657901 1994 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
mbed_official 87:085cde657901 1995 assert_param(IS_TIM_OPM_MODE(OnePulseMode));
mbed_official 87:085cde657901 1996
mbed_official 87:085cde657901 1997 if(htim->State == HAL_TIM_STATE_RESET)
mbed_official 532:fe11edbda85c 1998 {
mbed_official 532:fe11edbda85c 1999 /* Allocate lock resource and initialize it */
mbed_official 532:fe11edbda85c 2000 htim->Lock = HAL_UNLOCKED;
mbed_official 87:085cde657901 2001 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
mbed_official 87:085cde657901 2002 HAL_TIM_OnePulse_MspInit(htim);
mbed_official 87:085cde657901 2003 }
mbed_official 87:085cde657901 2004
mbed_official 87:085cde657901 2005 /* Set the TIM state */
mbed_official 87:085cde657901 2006 htim->State= HAL_TIM_STATE_BUSY;
mbed_official 87:085cde657901 2007
mbed_official 87:085cde657901 2008 /* Configure the Time base in the One Pulse Mode */
mbed_official 87:085cde657901 2009 TIM_Base_SetConfig(htim->Instance, &htim->Init);
mbed_official 87:085cde657901 2010
mbed_official 87:085cde657901 2011 /* Reset the OPM Bit */
mbed_official 87:085cde657901 2012 htim->Instance->CR1 &= ~TIM_CR1_OPM;
mbed_official 87:085cde657901 2013
mbed_official 87:085cde657901 2014 /* Configure the OPM Mode */
mbed_official 87:085cde657901 2015 htim->Instance->CR1 |= OnePulseMode;
mbed_official 87:085cde657901 2016
mbed_official 87:085cde657901 2017 /* Initialize the TIM state*/
mbed_official 87:085cde657901 2018 htim->State= HAL_TIM_STATE_READY;
mbed_official 87:085cde657901 2019
mbed_official 87:085cde657901 2020 return HAL_OK;
mbed_official 87:085cde657901 2021 }
mbed_official 87:085cde657901 2022
mbed_official 87:085cde657901 2023 /**
mbed_official 87:085cde657901 2024 * @brief DeInitializes the TIM One Pulse
mbed_official 226:b062af740e40 2025 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 2026 * the configuration information for TIM module.
mbed_official 87:085cde657901 2027 * @retval HAL status
mbed_official 87:085cde657901 2028 */
mbed_official 87:085cde657901 2029 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
mbed_official 87:085cde657901 2030 {
mbed_official 87:085cde657901 2031 /* Check the parameters */
mbed_official 87:085cde657901 2032 assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official 87:085cde657901 2033
mbed_official 87:085cde657901 2034 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 87:085cde657901 2035
mbed_official 87:085cde657901 2036 /* Disable the TIM Peripheral Clock */
mbed_official 87:085cde657901 2037 __HAL_TIM_DISABLE(htim);
mbed_official 87:085cde657901 2038
mbed_official 87:085cde657901 2039 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
mbed_official 87:085cde657901 2040 HAL_TIM_OnePulse_MspDeInit(htim);
mbed_official 87:085cde657901 2041
mbed_official 87:085cde657901 2042 /* Change TIM state */
mbed_official 106:ced8cbb51063 2043 htim->State = HAL_TIM_STATE_RESET;
mbed_official 106:ced8cbb51063 2044
mbed_official 106:ced8cbb51063 2045 /* Release Lock */
mbed_official 106:ced8cbb51063 2046 __HAL_UNLOCK(htim);
mbed_official 106:ced8cbb51063 2047
mbed_official 87:085cde657901 2048 return HAL_OK;
mbed_official 87:085cde657901 2049 }
mbed_official 87:085cde657901 2050
mbed_official 87:085cde657901 2051 /**
mbed_official 87:085cde657901 2052 * @brief Initializes the TIM One Pulse MSP.
mbed_official 226:b062af740e40 2053 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 2054 * the configuration information for TIM module.
mbed_official 87:085cde657901 2055 * @retval None
mbed_official 87:085cde657901 2056 */
mbed_official 87:085cde657901 2057 __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
mbed_official 87:085cde657901 2058 {
mbed_official 87:085cde657901 2059 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 87:085cde657901 2060 the HAL_TIM_OnePulse_MspInit could be implemented in the user file
mbed_official 87:085cde657901 2061 */
mbed_official 87:085cde657901 2062 }
mbed_official 87:085cde657901 2063
mbed_official 87:085cde657901 2064 /**
mbed_official 87:085cde657901 2065 * @brief DeInitializes TIM One Pulse MSP.
mbed_official 226:b062af740e40 2066 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 2067 * the configuration information for TIM module.
mbed_official 87:085cde657901 2068 * @retval None
mbed_official 87:085cde657901 2069 */
mbed_official 87:085cde657901 2070 __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
mbed_official 87:085cde657901 2071 {
mbed_official 87:085cde657901 2072 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 87:085cde657901 2073 the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
mbed_official 87:085cde657901 2074 */
mbed_official 87:085cde657901 2075 }
mbed_official 87:085cde657901 2076
mbed_official 87:085cde657901 2077 /**
mbed_official 87:085cde657901 2078 * @brief Starts the TIM One Pulse signal generation.
mbed_official 226:b062af740e40 2079 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 2080 * the configuration information for TIM module.
mbed_official 226:b062af740e40 2081 * @param OutputChannel : TIM Channels to be enabled.
mbed_official 87:085cde657901 2082 * This parameter can be one of the following values:
mbed_official 87:085cde657901 2083 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 87:085cde657901 2084 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 87:085cde657901 2085 * @retval HAL status
mbed_official 87:085cde657901 2086 */
mbed_official 87:085cde657901 2087 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
mbed_official 87:085cde657901 2088 {
mbed_official 87:085cde657901 2089 /* Enable the Capture compare and the Input Capture channels
mbed_official 87:085cde657901 2090 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
mbed_official 87:085cde657901 2091 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
mbed_official 87:085cde657901 2092 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
mbed_official 87:085cde657901 2093 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
mbed_official 87:085cde657901 2094
mbed_official 87:085cde657901 2095 No need to enable the counter, it's enabled automatically by hardware
mbed_official 87:085cde657901 2096 (the counter starts in response to a stimulus and generate a pulse */
mbed_official 87:085cde657901 2097
mbed_official 87:085cde657901 2098 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
mbed_official 87:085cde657901 2099 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
mbed_official 87:085cde657901 2100
mbed_official 87:085cde657901 2101 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
mbed_official 87:085cde657901 2102 {
mbed_official 87:085cde657901 2103 /* Enable the main output */
mbed_official 87:085cde657901 2104 __HAL_TIM_MOE_ENABLE(htim);
mbed_official 87:085cde657901 2105 }
mbed_official 87:085cde657901 2106
mbed_official 87:085cde657901 2107 /* Return function status */
mbed_official 87:085cde657901 2108 return HAL_OK;
mbed_official 87:085cde657901 2109 }
mbed_official 87:085cde657901 2110
mbed_official 87:085cde657901 2111 /**
mbed_official 87:085cde657901 2112 * @brief Stops the TIM One Pulse signal generation.
mbed_official 226:b062af740e40 2113 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 2114 * the configuration information for TIM module.
mbed_official 226:b062af740e40 2115 * @param OutputChannel : TIM Channels to be disable.
mbed_official 87:085cde657901 2116 * This parameter can be one of the following values:
mbed_official 87:085cde657901 2117 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 87:085cde657901 2118 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 87:085cde657901 2119 * @retval HAL status
mbed_official 87:085cde657901 2120 */
mbed_official 87:085cde657901 2121 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
mbed_official 87:085cde657901 2122 {
mbed_official 87:085cde657901 2123 /* Disable the Capture compare and the Input Capture channels
mbed_official 87:085cde657901 2124 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
mbed_official 87:085cde657901 2125 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
mbed_official 87:085cde657901 2126 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
mbed_official 87:085cde657901 2127 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
mbed_official 87:085cde657901 2128
mbed_official 87:085cde657901 2129 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
mbed_official 87:085cde657901 2130 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
mbed_official 87:085cde657901 2131
mbed_official 87:085cde657901 2132 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
mbed_official 87:085cde657901 2133 {
mbed_official 532:fe11edbda85c 2134 /* Disable the Main Output */
mbed_official 87:085cde657901 2135 __HAL_TIM_MOE_DISABLE(htim);
mbed_official 87:085cde657901 2136 }
mbed_official 87:085cde657901 2137
mbed_official 87:085cde657901 2138 /* Disable the Peripheral */
mbed_official 87:085cde657901 2139 __HAL_TIM_DISABLE(htim);
mbed_official 87:085cde657901 2140
mbed_official 87:085cde657901 2141 /* Return function status */
mbed_official 87:085cde657901 2142 return HAL_OK;
mbed_official 87:085cde657901 2143 }
mbed_official 87:085cde657901 2144
mbed_official 87:085cde657901 2145 /**
mbed_official 87:085cde657901 2146 * @brief Starts the TIM One Pulse signal generation in interrupt mode.
mbed_official 226:b062af740e40 2147 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 2148 * the configuration information for TIM module.
mbed_official 226:b062af740e40 2149 * @param OutputChannel : TIM Channels to be enabled.
mbed_official 87:085cde657901 2150 * This parameter can be one of the following values:
mbed_official 87:085cde657901 2151 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 87:085cde657901 2152 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 87:085cde657901 2153 * @retval HAL status
mbed_official 87:085cde657901 2154 */
mbed_official 87:085cde657901 2155 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
mbed_official 87:085cde657901 2156 {
mbed_official 87:085cde657901 2157 /* Enable the Capture compare and the Input Capture channels
mbed_official 87:085cde657901 2158 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
mbed_official 87:085cde657901 2159 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
mbed_official 87:085cde657901 2160 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
mbed_official 87:085cde657901 2161 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
mbed_official 87:085cde657901 2162
mbed_official 87:085cde657901 2163 No need to enable the counter, it's enabled automatically by hardware
mbed_official 87:085cde657901 2164 (the counter starts in response to a stimulus and generate a pulse */
mbed_official 87:085cde657901 2165
mbed_official 87:085cde657901 2166 /* Enable the TIM Capture/Compare 1 interrupt */
mbed_official 87:085cde657901 2167 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
mbed_official 87:085cde657901 2168
mbed_official 87:085cde657901 2169 /* Enable the TIM Capture/Compare 2 interrupt */
mbed_official 87:085cde657901 2170 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
mbed_official 87:085cde657901 2171
mbed_official 87:085cde657901 2172 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
mbed_official 87:085cde657901 2173 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
mbed_official 87:085cde657901 2174
mbed_official 87:085cde657901 2175 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
mbed_official 87:085cde657901 2176 {
mbed_official 87:085cde657901 2177 /* Enable the main output */
mbed_official 87:085cde657901 2178 __HAL_TIM_MOE_ENABLE(htim);
mbed_official 87:085cde657901 2179 }
mbed_official 87:085cde657901 2180
mbed_official 87:085cde657901 2181 /* Return function status */
mbed_official 87:085cde657901 2182 return HAL_OK;
mbed_official 87:085cde657901 2183 }
mbed_official 87:085cde657901 2184
mbed_official 87:085cde657901 2185 /**
mbed_official 87:085cde657901 2186 * @brief Stops the TIM One Pulse signal generation in interrupt mode.
mbed_official 226:b062af740e40 2187 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 2188 * the configuration information for TIM module.
mbed_official 226:b062af740e40 2189 * @param OutputChannel : TIM Channels to be enabled.
mbed_official 87:085cde657901 2190 * This parameter can be one of the following values:
mbed_official 87:085cde657901 2191 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 87:085cde657901 2192 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 87:085cde657901 2193 * @retval HAL status
mbed_official 87:085cde657901 2194 */
mbed_official 87:085cde657901 2195 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
mbed_official 87:085cde657901 2196 {
mbed_official 87:085cde657901 2197 /* Disable the TIM Capture/Compare 1 interrupt */
mbed_official 87:085cde657901 2198 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
mbed_official 87:085cde657901 2199
mbed_official 87:085cde657901 2200 /* Disable the TIM Capture/Compare 2 interrupt */
mbed_official 87:085cde657901 2201 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
mbed_official 87:085cde657901 2202
mbed_official 87:085cde657901 2203 /* Disable the Capture compare and the Input Capture channels
mbed_official 87:085cde657901 2204 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
mbed_official 87:085cde657901 2205 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
mbed_official 87:085cde657901 2206 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
mbed_official 87:085cde657901 2207 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
mbed_official 87:085cde657901 2208 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
mbed_official 87:085cde657901 2209 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
mbed_official 87:085cde657901 2210
mbed_official 87:085cde657901 2211 if(IS_TIM_ADVANCED_INSTANCE(htim->Instance) != RESET)
mbed_official 87:085cde657901 2212 {
mbed_official 532:fe11edbda85c 2213 /* Disable the Main Output */
mbed_official 87:085cde657901 2214 __HAL_TIM_MOE_DISABLE(htim);
mbed_official 87:085cde657901 2215 }
mbed_official 87:085cde657901 2216
mbed_official 87:085cde657901 2217 /* Disable the Peripheral */
mbed_official 87:085cde657901 2218 __HAL_TIM_DISABLE(htim);
mbed_official 87:085cde657901 2219
mbed_official 87:085cde657901 2220 /* Return function status */
mbed_official 87:085cde657901 2221 return HAL_OK;
mbed_official 87:085cde657901 2222 }
mbed_official 87:085cde657901 2223 /**
mbed_official 87:085cde657901 2224 * @}
mbed_official 87:085cde657901 2225 */
mbed_official 87:085cde657901 2226
mbed_official 532:fe11edbda85c 2227 /** @defgroup TIM_Exported_Functions_Group6 Time Encoder functions
mbed_official 87:085cde657901 2228 * @brief Time Encoder functions
mbed_official 87:085cde657901 2229 *
mbed_official 87:085cde657901 2230 @verbatim
mbed_official 87:085cde657901 2231 ==============================================================================
mbed_official 87:085cde657901 2232 ##### Time Encoder functions #####
mbed_official 87:085cde657901 2233 ==============================================================================
mbed_official 87:085cde657901 2234 [..]
mbed_official 87:085cde657901 2235 This section provides functions allowing to:
mbed_official 87:085cde657901 2236 (+) Initialize and configure the TIM Encoder.
mbed_official 87:085cde657901 2237 (+) De-initialize the TIM Encoder.
mbed_official 87:085cde657901 2238 (+) Start the Time Encoder.
mbed_official 87:085cde657901 2239 (+) Stop the Time Encoder.
mbed_official 87:085cde657901 2240 (+) Start the Time Encoder and enable interrupt.
mbed_official 87:085cde657901 2241 (+) Stop the Time Encoder and disable interrupt.
mbed_official 87:085cde657901 2242 (+) Start the Time Encoder and enable DMA transfer.
mbed_official 87:085cde657901 2243 (+) Stop the Time Encoder and disable DMA transfer.
mbed_official 87:085cde657901 2244
mbed_official 87:085cde657901 2245 @endverbatim
mbed_official 87:085cde657901 2246 * @{
mbed_official 87:085cde657901 2247 */
mbed_official 87:085cde657901 2248 /**
mbed_official 87:085cde657901 2249 * @brief Initializes the TIM Encoder Interface and create the associated handle.
mbed_official 226:b062af740e40 2250 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 2251 * the configuration information for TIM module.
mbed_official 87:085cde657901 2252 * @param sConfig: TIM Encoder Interface configuration structure
mbed_official 87:085cde657901 2253 * @retval HAL status
mbed_official 87:085cde657901 2254 */
mbed_official 87:085cde657901 2255 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig)
mbed_official 87:085cde657901 2256 {
mbed_official 87:085cde657901 2257 uint32_t tmpsmcr = 0;
mbed_official 87:085cde657901 2258 uint32_t tmpccmr1 = 0;
mbed_official 87:085cde657901 2259 uint32_t tmpccer = 0;
mbed_official 87:085cde657901 2260
mbed_official 87:085cde657901 2261 /* Check the TIM handle allocation */
mbed_official 369:2e96f1b71984 2262 if(htim == HAL_NULL)
mbed_official 87:085cde657901 2263 {
mbed_official 87:085cde657901 2264 return HAL_ERROR;
mbed_official 87:085cde657901 2265 }
mbed_official 87:085cde657901 2266
mbed_official 87:085cde657901 2267 /* Check the parameters */
mbed_official 87:085cde657901 2268 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 87:085cde657901 2269 assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
mbed_official 87:085cde657901 2270 assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
mbed_official 87:085cde657901 2271 assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
mbed_official 87:085cde657901 2272 assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
mbed_official 87:085cde657901 2273 assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity));
mbed_official 87:085cde657901 2274 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
mbed_official 87:085cde657901 2275 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
mbed_official 87:085cde657901 2276 assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
mbed_official 87:085cde657901 2277 assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
mbed_official 87:085cde657901 2278
mbed_official 87:085cde657901 2279 if(htim->State == HAL_TIM_STATE_RESET)
mbed_official 87:085cde657901 2280 {
mbed_official 532:fe11edbda85c 2281 /* Allocate lock resource and initialize it */
mbed_official 532:fe11edbda85c 2282 htim->Lock = HAL_UNLOCKED;
mbed_official 87:085cde657901 2283 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
mbed_official 87:085cde657901 2284 HAL_TIM_Encoder_MspInit(htim);
mbed_official 87:085cde657901 2285 }
mbed_official 87:085cde657901 2286
mbed_official 87:085cde657901 2287 /* Set the TIM state */
mbed_official 87:085cde657901 2288 htim->State= HAL_TIM_STATE_BUSY;
mbed_official 87:085cde657901 2289
mbed_official 87:085cde657901 2290 /* Reset the SMS bits */
mbed_official 87:085cde657901 2291 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
mbed_official 87:085cde657901 2292
mbed_official 87:085cde657901 2293 /* Configure the Time base in the Encoder Mode */
mbed_official 87:085cde657901 2294 TIM_Base_SetConfig(htim->Instance, &htim->Init);
mbed_official 87:085cde657901 2295
mbed_official 87:085cde657901 2296 /* Get the TIMx SMCR register value */
mbed_official 87:085cde657901 2297 tmpsmcr = htim->Instance->SMCR;
mbed_official 87:085cde657901 2298
mbed_official 87:085cde657901 2299 /* Get the TIMx CCMR1 register value */
mbed_official 87:085cde657901 2300 tmpccmr1 = htim->Instance->CCMR1;
mbed_official 87:085cde657901 2301
mbed_official 87:085cde657901 2302 /* Get the TIMx CCER register value */
mbed_official 87:085cde657901 2303 tmpccer = htim->Instance->CCER;
mbed_official 87:085cde657901 2304
mbed_official 87:085cde657901 2305 /* Set the encoder Mode */
mbed_official 87:085cde657901 2306 tmpsmcr |= sConfig->EncoderMode;
mbed_official 87:085cde657901 2307
mbed_official 87:085cde657901 2308 /* Select the Capture Compare 1 and the Capture Compare 2 as input */
mbed_official 87:085cde657901 2309 tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
mbed_official 87:085cde657901 2310 tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8));
mbed_official 87:085cde657901 2311
mbed_official 532:fe11edbda85c 2312 /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
mbed_official 87:085cde657901 2313 tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
mbed_official 87:085cde657901 2314 tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
mbed_official 87:085cde657901 2315 tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8);
mbed_official 87:085cde657901 2316 tmpccmr1 |= (sConfig->IC1Filter << 4) | (sConfig->IC2Filter << 12);
mbed_official 87:085cde657901 2317
mbed_official 87:085cde657901 2318 /* Set the TI1 and the TI2 Polarities */
mbed_official 87:085cde657901 2319 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
mbed_official 87:085cde657901 2320 tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
mbed_official 87:085cde657901 2321 tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4);
mbed_official 87:085cde657901 2322
mbed_official 87:085cde657901 2323 /* Write to TIMx SMCR */
mbed_official 87:085cde657901 2324 htim->Instance->SMCR = tmpsmcr;
mbed_official 87:085cde657901 2325
mbed_official 87:085cde657901 2326 /* Write to TIMx CCMR1 */
mbed_official 87:085cde657901 2327 htim->Instance->CCMR1 = tmpccmr1;
mbed_official 87:085cde657901 2328
mbed_official 87:085cde657901 2329 /* Write to TIMx CCER */
mbed_official 87:085cde657901 2330 htim->Instance->CCER = tmpccer;
mbed_official 87:085cde657901 2331
mbed_official 87:085cde657901 2332 /* Initialize the TIM state*/
mbed_official 87:085cde657901 2333 htim->State= HAL_TIM_STATE_READY;
mbed_official 87:085cde657901 2334
mbed_official 87:085cde657901 2335 return HAL_OK;
mbed_official 87:085cde657901 2336 }
mbed_official 87:085cde657901 2337
mbed_official 87:085cde657901 2338 /**
mbed_official 87:085cde657901 2339 * @brief DeInitializes the TIM Encoder interface
mbed_official 226:b062af740e40 2340 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 2341 * the configuration information for TIM module.
mbed_official 87:085cde657901 2342 * @retval HAL status
mbed_official 87:085cde657901 2343 */
mbed_official 87:085cde657901 2344 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
mbed_official 87:085cde657901 2345 {
mbed_official 87:085cde657901 2346 /* Check the parameters */
mbed_official 87:085cde657901 2347 assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official 87:085cde657901 2348
mbed_official 87:085cde657901 2349 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 87:085cde657901 2350
mbed_official 87:085cde657901 2351 /* Disable the TIM Peripheral Clock */
mbed_official 87:085cde657901 2352 __HAL_TIM_DISABLE(htim);
mbed_official 87:085cde657901 2353
mbed_official 87:085cde657901 2354 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
mbed_official 87:085cde657901 2355 HAL_TIM_Encoder_MspDeInit(htim);
mbed_official 87:085cde657901 2356
mbed_official 87:085cde657901 2357 /* Change TIM state */
mbed_official 106:ced8cbb51063 2358 htim->State = HAL_TIM_STATE_RESET;
mbed_official 106:ced8cbb51063 2359
mbed_official 106:ced8cbb51063 2360 /* Release Lock */
mbed_official 106:ced8cbb51063 2361 __HAL_UNLOCK(htim);
mbed_official 106:ced8cbb51063 2362
mbed_official 87:085cde657901 2363 return HAL_OK;
mbed_official 87:085cde657901 2364 }
mbed_official 87:085cde657901 2365
mbed_official 87:085cde657901 2366 /**
mbed_official 87:085cde657901 2367 * @brief Initializes the TIM Encoder Interface MSP.
mbed_official 226:b062af740e40 2368 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 2369 * the configuration information for TIM module.
mbed_official 87:085cde657901 2370 * @retval None
mbed_official 87:085cde657901 2371 */
mbed_official 87:085cde657901 2372 __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
mbed_official 87:085cde657901 2373 {
mbed_official 87:085cde657901 2374 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 87:085cde657901 2375 the HAL_TIM_Encoder_MspInit could be implemented in the user file
mbed_official 87:085cde657901 2376 */
mbed_official 87:085cde657901 2377 }
mbed_official 87:085cde657901 2378
mbed_official 87:085cde657901 2379 /**
mbed_official 87:085cde657901 2380 * @brief DeInitializes TIM Encoder Interface MSP.
mbed_official 226:b062af740e40 2381 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 2382 * the configuration information for TIM module.
mbed_official 87:085cde657901 2383 * @retval None
mbed_official 87:085cde657901 2384 */
mbed_official 87:085cde657901 2385 __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
mbed_official 87:085cde657901 2386 {
mbed_official 87:085cde657901 2387 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 87:085cde657901 2388 the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
mbed_official 87:085cde657901 2389 */
mbed_official 87:085cde657901 2390 }
mbed_official 87:085cde657901 2391
mbed_official 87:085cde657901 2392 /**
mbed_official 87:085cde657901 2393 * @brief Starts the TIM Encoder Interface.
mbed_official 226:b062af740e40 2394 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 2395 * the configuration information for TIM module.
mbed_official 226:b062af740e40 2396 * @param Channel: TIM Channels to be enabled.
mbed_official 87:085cde657901 2397 * This parameter can be one of the following values:
mbed_official 87:085cde657901 2398 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 87:085cde657901 2399 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 532:fe11edbda85c 2400 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
mbed_official 87:085cde657901 2401 * @retval HAL status
mbed_official 87:085cde657901 2402 */
mbed_official 87:085cde657901 2403 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 87:085cde657901 2404 {
mbed_official 87:085cde657901 2405 /* Check the parameters */
mbed_official 87:085cde657901 2406 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 87:085cde657901 2407
mbed_official 87:085cde657901 2408 /* Enable the encoder interface channels */
mbed_official 87:085cde657901 2409 switch (Channel)
mbed_official 87:085cde657901 2410 {
mbed_official 87:085cde657901 2411 case TIM_CHANNEL_1:
mbed_official 87:085cde657901 2412 {
mbed_official 87:085cde657901 2413 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
mbed_official 87:085cde657901 2414 break;
mbed_official 87:085cde657901 2415 }
mbed_official 87:085cde657901 2416 case TIM_CHANNEL_2:
mbed_official 87:085cde657901 2417 {
mbed_official 87:085cde657901 2418 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
mbed_official 87:085cde657901 2419 break;
mbed_official 87:085cde657901 2420 }
mbed_official 87:085cde657901 2421 default :
mbed_official 87:085cde657901 2422 {
mbed_official 87:085cde657901 2423 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
mbed_official 87:085cde657901 2424 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
mbed_official 87:085cde657901 2425 break;
mbed_official 87:085cde657901 2426 }
mbed_official 87:085cde657901 2427 }
mbed_official 87:085cde657901 2428 /* Enable the Peripheral */
mbed_official 87:085cde657901 2429 __HAL_TIM_ENABLE(htim);
mbed_official 87:085cde657901 2430
mbed_official 87:085cde657901 2431 /* Return function status */
mbed_official 87:085cde657901 2432 return HAL_OK;
mbed_official 87:085cde657901 2433 }
mbed_official 87:085cde657901 2434
mbed_official 87:085cde657901 2435 /**
mbed_official 87:085cde657901 2436 * @brief Stops the TIM Encoder Interface.
mbed_official 226:b062af740e40 2437 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 2438 * the configuration information for TIM module.
mbed_official 226:b062af740e40 2439 * @param Channel: TIM Channels to be disabled.
mbed_official 87:085cde657901 2440 * This parameter can be one of the following values:
mbed_official 87:085cde657901 2441 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 87:085cde657901 2442 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 532:fe11edbda85c 2443 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
mbed_official 87:085cde657901 2444 * @retval HAL status
mbed_official 87:085cde657901 2445 */
mbed_official 87:085cde657901 2446 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 87:085cde657901 2447 {
mbed_official 87:085cde657901 2448 /* Check the parameters */
mbed_official 87:085cde657901 2449 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 87:085cde657901 2450
mbed_official 87:085cde657901 2451 /* Disable the Input Capture channels 1 and 2
mbed_official 87:085cde657901 2452 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
mbed_official 87:085cde657901 2453 switch (Channel)
mbed_official 87:085cde657901 2454 {
mbed_official 87:085cde657901 2455 case TIM_CHANNEL_1:
mbed_official 87:085cde657901 2456 {
mbed_official 87:085cde657901 2457 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
mbed_official 87:085cde657901 2458 break;
mbed_official 87:085cde657901 2459 }
mbed_official 87:085cde657901 2460 case TIM_CHANNEL_2:
mbed_official 87:085cde657901 2461 {
mbed_official 87:085cde657901 2462 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
mbed_official 87:085cde657901 2463 break;
mbed_official 87:085cde657901 2464 }
mbed_official 87:085cde657901 2465 default :
mbed_official 87:085cde657901 2466 {
mbed_official 87:085cde657901 2467 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
mbed_official 87:085cde657901 2468 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
mbed_official 87:085cde657901 2469 break;
mbed_official 87:085cde657901 2470 }
mbed_official 87:085cde657901 2471 }
mbed_official 87:085cde657901 2472 /* Disable the Peripheral */
mbed_official 87:085cde657901 2473 __HAL_TIM_DISABLE(htim);
mbed_official 87:085cde657901 2474
mbed_official 87:085cde657901 2475 /* Return function status */
mbed_official 87:085cde657901 2476 return HAL_OK;
mbed_official 87:085cde657901 2477 }
mbed_official 87:085cde657901 2478
mbed_official 87:085cde657901 2479 /**
mbed_official 87:085cde657901 2480 * @brief Starts the TIM Encoder Interface in interrupt mode.
mbed_official 226:b062af740e40 2481 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 2482 * the configuration information for TIM module.
mbed_official 226:b062af740e40 2483 * @param Channel: TIM Channels to be enabled.
mbed_official 87:085cde657901 2484 * This parameter can be one of the following values:
mbed_official 87:085cde657901 2485 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 87:085cde657901 2486 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 532:fe11edbda85c 2487 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
mbed_official 87:085cde657901 2488 * @retval HAL status
mbed_official 87:085cde657901 2489 */
mbed_official 87:085cde657901 2490 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 87:085cde657901 2491 {
mbed_official 87:085cde657901 2492 /* Check the parameters */
mbed_official 87:085cde657901 2493 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 87:085cde657901 2494
mbed_official 87:085cde657901 2495 /* Enable the encoder interface channels */
mbed_official 87:085cde657901 2496 /* Enable the capture compare Interrupts 1 and/or 2 */
mbed_official 87:085cde657901 2497 switch (Channel)
mbed_official 87:085cde657901 2498 {
mbed_official 87:085cde657901 2499 case TIM_CHANNEL_1:
mbed_official 87:085cde657901 2500 {
mbed_official 87:085cde657901 2501 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
mbed_official 87:085cde657901 2502 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
mbed_official 87:085cde657901 2503 break;
mbed_official 87:085cde657901 2504 }
mbed_official 87:085cde657901 2505 case TIM_CHANNEL_2:
mbed_official 87:085cde657901 2506 {
mbed_official 87:085cde657901 2507 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
mbed_official 87:085cde657901 2508 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
mbed_official 87:085cde657901 2509 break;
mbed_official 87:085cde657901 2510 }
mbed_official 87:085cde657901 2511 default :
mbed_official 87:085cde657901 2512 {
mbed_official 87:085cde657901 2513 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
mbed_official 87:085cde657901 2514 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
mbed_official 87:085cde657901 2515 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
mbed_official 87:085cde657901 2516 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
mbed_official 87:085cde657901 2517 break;
mbed_official 87:085cde657901 2518 }
mbed_official 87:085cde657901 2519 }
mbed_official 87:085cde657901 2520
mbed_official 87:085cde657901 2521 /* Enable the Peripheral */
mbed_official 87:085cde657901 2522 __HAL_TIM_ENABLE(htim);
mbed_official 87:085cde657901 2523
mbed_official 87:085cde657901 2524 /* Return function status */
mbed_official 87:085cde657901 2525 return HAL_OK;
mbed_official 87:085cde657901 2526 }
mbed_official 87:085cde657901 2527
mbed_official 87:085cde657901 2528 /**
mbed_official 87:085cde657901 2529 * @brief Stops the TIM Encoder Interface in interrupt mode.
mbed_official 226:b062af740e40 2530 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 2531 * the configuration information for TIM module.
mbed_official 226:b062af740e40 2532 * @param Channel: TIM Channels to be disabled.
mbed_official 87:085cde657901 2533 * This parameter can be one of the following values:
mbed_official 87:085cde657901 2534 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 87:085cde657901 2535 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 532:fe11edbda85c 2536 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
mbed_official 87:085cde657901 2537 * @retval HAL status
mbed_official 87:085cde657901 2538 */
mbed_official 87:085cde657901 2539 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 87:085cde657901 2540 {
mbed_official 87:085cde657901 2541 /* Check the parameters */
mbed_official 87:085cde657901 2542 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 87:085cde657901 2543
mbed_official 87:085cde657901 2544 /* Disable the Input Capture channels 1 and 2
mbed_official 87:085cde657901 2545 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
mbed_official 87:085cde657901 2546 if(Channel == TIM_CHANNEL_1)
mbed_official 87:085cde657901 2547 {
mbed_official 87:085cde657901 2548 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
mbed_official 87:085cde657901 2549
mbed_official 87:085cde657901 2550 /* Disable the capture compare Interrupts 1 */
mbed_official 87:085cde657901 2551 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
mbed_official 87:085cde657901 2552 }
mbed_official 87:085cde657901 2553 else if(Channel == TIM_CHANNEL_2)
mbed_official 87:085cde657901 2554 {
mbed_official 87:085cde657901 2555 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
mbed_official 87:085cde657901 2556
mbed_official 87:085cde657901 2557 /* Disable the capture compare Interrupts 2 */
mbed_official 87:085cde657901 2558 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
mbed_official 87:085cde657901 2559 }
mbed_official 87:085cde657901 2560 else
mbed_official 87:085cde657901 2561 {
mbed_official 87:085cde657901 2562 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
mbed_official 87:085cde657901 2563 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
mbed_official 87:085cde657901 2564
mbed_official 87:085cde657901 2565 /* Disable the capture compare Interrupts 1 and 2 */
mbed_official 87:085cde657901 2566 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
mbed_official 87:085cde657901 2567 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
mbed_official 87:085cde657901 2568 }
mbed_official 87:085cde657901 2569
mbed_official 87:085cde657901 2570 /* Disable the Peripheral */
mbed_official 87:085cde657901 2571 __HAL_TIM_DISABLE(htim);
mbed_official 87:085cde657901 2572
mbed_official 87:085cde657901 2573 /* Change the htim state */
mbed_official 87:085cde657901 2574 htim->State = HAL_TIM_STATE_READY;
mbed_official 87:085cde657901 2575
mbed_official 87:085cde657901 2576 /* Return function status */
mbed_official 87:085cde657901 2577 return HAL_OK;
mbed_official 87:085cde657901 2578 }
mbed_official 87:085cde657901 2579
mbed_official 87:085cde657901 2580 /**
mbed_official 87:085cde657901 2581 * @brief Starts the TIM Encoder Interface in DMA mode.
mbed_official 226:b062af740e40 2582 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 2583 * the configuration information for TIM module.
mbed_official 226:b062af740e40 2584 * @param Channel: TIM Channels to be enabled.
mbed_official 87:085cde657901 2585 * This parameter can be one of the following values:
mbed_official 87:085cde657901 2586 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 87:085cde657901 2587 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 532:fe11edbda85c 2588 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
mbed_official 87:085cde657901 2589 * @param pData1: The destination Buffer address for IC1.
mbed_official 87:085cde657901 2590 * @param pData2: The destination Buffer address for IC2.
mbed_official 87:085cde657901 2591 * @param Length: The length of data to be transferred from TIM peripheral to memory.
mbed_official 87:085cde657901 2592 * @retval HAL status
mbed_official 87:085cde657901 2593 */
mbed_official 87:085cde657901 2594 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length)
mbed_official 87:085cde657901 2595 {
mbed_official 87:085cde657901 2596 /* Check the parameters */
mbed_official 87:085cde657901 2597 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
mbed_official 87:085cde657901 2598
mbed_official 87:085cde657901 2599 if((htim->State == HAL_TIM_STATE_BUSY))
mbed_official 87:085cde657901 2600 {
mbed_official 87:085cde657901 2601 return HAL_BUSY;
mbed_official 87:085cde657901 2602 }
mbed_official 87:085cde657901 2603 else if((htim->State == HAL_TIM_STATE_READY))
mbed_official 87:085cde657901 2604 {
mbed_official 87:085cde657901 2605 if((((pData1 == 0) || (pData2 == 0) )) && (Length > 0))
mbed_official 87:085cde657901 2606 {
mbed_official 87:085cde657901 2607 return HAL_ERROR;
mbed_official 87:085cde657901 2608 }
mbed_official 87:085cde657901 2609 else
mbed_official 87:085cde657901 2610 {
mbed_official 87:085cde657901 2611 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 87:085cde657901 2612 }
mbed_official 87:085cde657901 2613 }
mbed_official 87:085cde657901 2614
mbed_official 87:085cde657901 2615 switch (Channel)
mbed_official 87:085cde657901 2616 {
mbed_official 87:085cde657901 2617 case TIM_CHANNEL_1:
mbed_official 87:085cde657901 2618 {
mbed_official 87:085cde657901 2619 /* Set the DMA Period elapsed callback */
mbed_official 532:fe11edbda85c 2620 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
mbed_official 87:085cde657901 2621
mbed_official 87:085cde657901 2622 /* Set the DMA error callback */
mbed_official 532:fe11edbda85c 2623 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
mbed_official 87:085cde657901 2624
mbed_official 87:085cde657901 2625 /* Enable the DMA Stream */
mbed_official 87:085cde657901 2626 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t )pData1, Length);
mbed_official 87:085cde657901 2627
mbed_official 87:085cde657901 2628 /* Enable the TIM Input Capture DMA request */
mbed_official 87:085cde657901 2629 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
mbed_official 87:085cde657901 2630
mbed_official 87:085cde657901 2631 /* Enable the Peripheral */
mbed_official 87:085cde657901 2632 __HAL_TIM_ENABLE(htim);
mbed_official 87:085cde657901 2633
mbed_official 87:085cde657901 2634 /* Enable the Capture compare channel */
mbed_official 87:085cde657901 2635 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
mbed_official 87:085cde657901 2636 }
mbed_official 87:085cde657901 2637 break;
mbed_official 87:085cde657901 2638
mbed_official 87:085cde657901 2639 case TIM_CHANNEL_2:
mbed_official 87:085cde657901 2640 {
mbed_official 87:085cde657901 2641 /* Set the DMA Period elapsed callback */
mbed_official 532:fe11edbda85c 2642 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
mbed_official 87:085cde657901 2643
mbed_official 87:085cde657901 2644 /* Set the DMA error callback */
mbed_official 532:fe11edbda85c 2645 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
mbed_official 87:085cde657901 2646 /* Enable the DMA Stream */
mbed_official 87:085cde657901 2647 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
mbed_official 87:085cde657901 2648
mbed_official 87:085cde657901 2649 /* Enable the TIM Input Capture DMA request */
mbed_official 87:085cde657901 2650 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
mbed_official 87:085cde657901 2651
mbed_official 87:085cde657901 2652 /* Enable the Peripheral */
mbed_official 87:085cde657901 2653 __HAL_TIM_ENABLE(htim);
mbed_official 87:085cde657901 2654
mbed_official 87:085cde657901 2655 /* Enable the Capture compare channel */
mbed_official 87:085cde657901 2656 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
mbed_official 87:085cde657901 2657 }
mbed_official 87:085cde657901 2658 break;
mbed_official 87:085cde657901 2659
mbed_official 87:085cde657901 2660 case TIM_CHANNEL_ALL:
mbed_official 87:085cde657901 2661 {
mbed_official 87:085cde657901 2662 /* Set the DMA Period elapsed callback */
mbed_official 532:fe11edbda85c 2663 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
mbed_official 87:085cde657901 2664
mbed_official 87:085cde657901 2665 /* Set the DMA error callback */
mbed_official 532:fe11edbda85c 2666 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
mbed_official 87:085cde657901 2667
mbed_official 87:085cde657901 2668 /* Enable the DMA Stream */
mbed_official 87:085cde657901 2669 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length);
mbed_official 87:085cde657901 2670
mbed_official 87:085cde657901 2671 /* Set the DMA Period elapsed callback */
mbed_official 532:fe11edbda85c 2672 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
mbed_official 87:085cde657901 2673
mbed_official 87:085cde657901 2674 /* Set the DMA error callback */
mbed_official 532:fe11edbda85c 2675 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
mbed_official 87:085cde657901 2676
mbed_official 87:085cde657901 2677 /* Enable the DMA Stream */
mbed_official 87:085cde657901 2678 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
mbed_official 87:085cde657901 2679
mbed_official 87:085cde657901 2680 /* Enable the Peripheral */
mbed_official 87:085cde657901 2681 __HAL_TIM_ENABLE(htim);
mbed_official 87:085cde657901 2682
mbed_official 87:085cde657901 2683 /* Enable the Capture compare channel */
mbed_official 87:085cde657901 2684 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
mbed_official 87:085cde657901 2685 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
mbed_official 87:085cde657901 2686
mbed_official 87:085cde657901 2687 /* Enable the TIM Input Capture DMA request */
mbed_official 87:085cde657901 2688 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
mbed_official 87:085cde657901 2689 /* Enable the TIM Input Capture DMA request */
mbed_official 87:085cde657901 2690 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
mbed_official 87:085cde657901 2691 }
mbed_official 87:085cde657901 2692 break;
mbed_official 87:085cde657901 2693
mbed_official 87:085cde657901 2694 default:
mbed_official 87:085cde657901 2695 break;
mbed_official 87:085cde657901 2696 }
mbed_official 87:085cde657901 2697 /* Return function status */
mbed_official 87:085cde657901 2698 return HAL_OK;
mbed_official 87:085cde657901 2699 }
mbed_official 87:085cde657901 2700
mbed_official 87:085cde657901 2701 /**
mbed_official 87:085cde657901 2702 * @brief Stops the TIM Encoder Interface in DMA mode.
mbed_official 226:b062af740e40 2703 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 2704 * the configuration information for TIM module.
mbed_official 226:b062af740e40 2705 * @param Channel: TIM Channels to be enabled.
mbed_official 87:085cde657901 2706 * This parameter can be one of the following values:
mbed_official 87:085cde657901 2707 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 87:085cde657901 2708 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 532:fe11edbda85c 2709 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
mbed_official 87:085cde657901 2710 * @retval HAL status
mbed_official 87:085cde657901 2711 */
mbed_official 87:085cde657901 2712 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 87:085cde657901 2713 {
mbed_official 87:085cde657901 2714 /* Check the parameters */
mbed_official 87:085cde657901 2715 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
mbed_official 87:085cde657901 2716
mbed_official 87:085cde657901 2717 /* Disable the Input Capture channels 1 and 2
mbed_official 87:085cde657901 2718 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
mbed_official 87:085cde657901 2719 if(Channel == TIM_CHANNEL_1)
mbed_official 87:085cde657901 2720 {
mbed_official 87:085cde657901 2721 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
mbed_official 87:085cde657901 2722
mbed_official 87:085cde657901 2723 /* Disable the capture compare DMA Request 1 */
mbed_official 87:085cde657901 2724 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
mbed_official 87:085cde657901 2725 }
mbed_official 87:085cde657901 2726 else if(Channel == TIM_CHANNEL_2)
mbed_official 87:085cde657901 2727 {
mbed_official 87:085cde657901 2728 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
mbed_official 87:085cde657901 2729
mbed_official 87:085cde657901 2730 /* Disable the capture compare DMA Request 2 */
mbed_official 87:085cde657901 2731 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
mbed_official 87:085cde657901 2732 }
mbed_official 87:085cde657901 2733 else
mbed_official 87:085cde657901 2734 {
mbed_official 87:085cde657901 2735 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
mbed_official 87:085cde657901 2736 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
mbed_official 87:085cde657901 2737
mbed_official 87:085cde657901 2738 /* Disable the capture compare DMA Request 1 and 2 */
mbed_official 87:085cde657901 2739 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
mbed_official 87:085cde657901 2740 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
mbed_official 87:085cde657901 2741 }
mbed_official 87:085cde657901 2742
mbed_official 87:085cde657901 2743 /* Disable the Peripheral */
mbed_official 87:085cde657901 2744 __HAL_TIM_DISABLE(htim);
mbed_official 87:085cde657901 2745
mbed_official 87:085cde657901 2746 /* Change the htim state */
mbed_official 87:085cde657901 2747 htim->State = HAL_TIM_STATE_READY;
mbed_official 87:085cde657901 2748
mbed_official 87:085cde657901 2749 /* Return function status */
mbed_official 87:085cde657901 2750 return HAL_OK;
mbed_official 87:085cde657901 2751 }
mbed_official 87:085cde657901 2752 /**
mbed_official 87:085cde657901 2753 * @}
mbed_official 87:085cde657901 2754 */
mbed_official 532:fe11edbda85c 2755
mbed_official 532:fe11edbda85c 2756 /** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
mbed_official 87:085cde657901 2757 * @brief IRQ handler management
mbed_official 87:085cde657901 2758 *
mbed_official 87:085cde657901 2759 @verbatim
mbed_official 87:085cde657901 2760 ==============================================================================
mbed_official 87:085cde657901 2761 ##### IRQ handler management #####
mbed_official 87:085cde657901 2762 ==============================================================================
mbed_official 87:085cde657901 2763 [..]
mbed_official 87:085cde657901 2764 This section provides Timer IRQ handler function.
mbed_official 87:085cde657901 2765
mbed_official 87:085cde657901 2766 @endverbatim
mbed_official 87:085cde657901 2767 * @{
mbed_official 87:085cde657901 2768 */
mbed_official 87:085cde657901 2769 /**
mbed_official 87:085cde657901 2770 * @brief This function handles TIM interrupts requests.
mbed_official 226:b062af740e40 2771 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 2772 * the configuration information for TIM module.
mbed_official 87:085cde657901 2773 * @retval None
mbed_official 87:085cde657901 2774 */
mbed_official 87:085cde657901 2775 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
mbed_official 87:085cde657901 2776 {
mbed_official 87:085cde657901 2777 /* Capture compare 1 event */
mbed_official 87:085cde657901 2778 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
mbed_official 87:085cde657901 2779 {
mbed_official 532:fe11edbda85c 2780 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) !=RESET)
mbed_official 87:085cde657901 2781 {
mbed_official 87:085cde657901 2782 {
mbed_official 87:085cde657901 2783 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
mbed_official 87:085cde657901 2784 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
mbed_official 87:085cde657901 2785
mbed_official 87:085cde657901 2786 /* Input capture event */
mbed_official 87:085cde657901 2787 if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00)
mbed_official 87:085cde657901 2788 {
mbed_official 87:085cde657901 2789 HAL_TIM_IC_CaptureCallback(htim);
mbed_official 87:085cde657901 2790 }
mbed_official 87:085cde657901 2791 /* Output compare event */
mbed_official 87:085cde657901 2792 else
mbed_official 87:085cde657901 2793 {
mbed_official 87:085cde657901 2794 HAL_TIM_OC_DelayElapsedCallback(htim);
mbed_official 87:085cde657901 2795 HAL_TIM_PWM_PulseFinishedCallback(htim);
mbed_official 87:085cde657901 2796 }
mbed_official 87:085cde657901 2797 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
mbed_official 87:085cde657901 2798 }
mbed_official 87:085cde657901 2799 }
mbed_official 87:085cde657901 2800 }
mbed_official 87:085cde657901 2801 /* Capture compare 2 event */
mbed_official 87:085cde657901 2802 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
mbed_official 87:085cde657901 2803 {
mbed_official 532:fe11edbda85c 2804 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) !=RESET)
mbed_official 87:085cde657901 2805 {
mbed_official 87:085cde657901 2806 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
mbed_official 87:085cde657901 2807 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
mbed_official 87:085cde657901 2808 /* Input capture event */
mbed_official 87:085cde657901 2809 if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00)
mbed_official 87:085cde657901 2810 {
mbed_official 87:085cde657901 2811 HAL_TIM_IC_CaptureCallback(htim);
mbed_official 87:085cde657901 2812 }
mbed_official 87:085cde657901 2813 /* Output compare event */
mbed_official 87:085cde657901 2814 else
mbed_official 87:085cde657901 2815 {
mbed_official 87:085cde657901 2816 HAL_TIM_OC_DelayElapsedCallback(htim);
mbed_official 87:085cde657901 2817 HAL_TIM_PWM_PulseFinishedCallback(htim);
mbed_official 87:085cde657901 2818 }
mbed_official 87:085cde657901 2819 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
mbed_official 87:085cde657901 2820 }
mbed_official 87:085cde657901 2821 }
mbed_official 87:085cde657901 2822 /* Capture compare 3 event */
mbed_official 87:085cde657901 2823 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
mbed_official 87:085cde657901 2824 {
mbed_official 532:fe11edbda85c 2825 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) !=RESET)
mbed_official 87:085cde657901 2826 {
mbed_official 87:085cde657901 2827 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
mbed_official 87:085cde657901 2828 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
mbed_official 87:085cde657901 2829 /* Input capture event */
mbed_official 369:2e96f1b71984 2830 if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00)
mbed_official 87:085cde657901 2831 {
mbed_official 87:085cde657901 2832 HAL_TIM_IC_CaptureCallback(htim);
mbed_official 87:085cde657901 2833 }
mbed_official 87:085cde657901 2834 /* Output compare event */
mbed_official 87:085cde657901 2835 else
mbed_official 87:085cde657901 2836 {
mbed_official 87:085cde657901 2837 HAL_TIM_OC_DelayElapsedCallback(htim);
mbed_official 87:085cde657901 2838 HAL_TIM_PWM_PulseFinishedCallback(htim);
mbed_official 87:085cde657901 2839 }
mbed_official 87:085cde657901 2840 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
mbed_official 87:085cde657901 2841 }
mbed_official 87:085cde657901 2842 }
mbed_official 87:085cde657901 2843 /* Capture compare 4 event */
mbed_official 87:085cde657901 2844 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
mbed_official 87:085cde657901 2845 {
mbed_official 532:fe11edbda85c 2846 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) !=RESET)
mbed_official 87:085cde657901 2847 {
mbed_official 87:085cde657901 2848 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
mbed_official 87:085cde657901 2849 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
mbed_official 87:085cde657901 2850 /* Input capture event */
mbed_official 369:2e96f1b71984 2851 if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00)
mbed_official 87:085cde657901 2852 {
mbed_official 87:085cde657901 2853 HAL_TIM_IC_CaptureCallback(htim);
mbed_official 87:085cde657901 2854 }
mbed_official 87:085cde657901 2855 /* Output compare event */
mbed_official 87:085cde657901 2856 else
mbed_official 87:085cde657901 2857 {
mbed_official 87:085cde657901 2858 HAL_TIM_OC_DelayElapsedCallback(htim);
mbed_official 87:085cde657901 2859 HAL_TIM_PWM_PulseFinishedCallback(htim);
mbed_official 87:085cde657901 2860 }
mbed_official 87:085cde657901 2861 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
mbed_official 87:085cde657901 2862 }
mbed_official 87:085cde657901 2863 }
mbed_official 87:085cde657901 2864 /* TIM Update event */
mbed_official 87:085cde657901 2865 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
mbed_official 87:085cde657901 2866 {
mbed_official 532:fe11edbda85c 2867 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) !=RESET)
mbed_official 87:085cde657901 2868 {
mbed_official 87:085cde657901 2869 __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
mbed_official 87:085cde657901 2870 HAL_TIM_PeriodElapsedCallback(htim);
mbed_official 87:085cde657901 2871 }
mbed_official 87:085cde657901 2872 }
mbed_official 87:085cde657901 2873 /* TIM Break input event */
mbed_official 87:085cde657901 2874 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
mbed_official 87:085cde657901 2875 {
mbed_official 532:fe11edbda85c 2876 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) !=RESET)
mbed_official 87:085cde657901 2877 {
mbed_official 87:085cde657901 2878 __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
mbed_official 87:085cde657901 2879 HAL_TIMEx_BreakCallback(htim);
mbed_official 87:085cde657901 2880 }
mbed_official 87:085cde657901 2881 }
mbed_official 87:085cde657901 2882 /* TIM Trigger detection event */
mbed_official 87:085cde657901 2883 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
mbed_official 87:085cde657901 2884 {
mbed_official 532:fe11edbda85c 2885 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) !=RESET)
mbed_official 87:085cde657901 2886 {
mbed_official 87:085cde657901 2887 __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
mbed_official 87:085cde657901 2888 HAL_TIM_TriggerCallback(htim);
mbed_official 87:085cde657901 2889 }
mbed_official 87:085cde657901 2890 }
mbed_official 87:085cde657901 2891 /* TIM commutation event */
mbed_official 87:085cde657901 2892 if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
mbed_official 87:085cde657901 2893 {
mbed_official 532:fe11edbda85c 2894 if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) !=RESET)
mbed_official 87:085cde657901 2895 {
mbed_official 87:085cde657901 2896 __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
mbed_official 87:085cde657901 2897 HAL_TIMEx_CommutationCallback(htim);
mbed_official 87:085cde657901 2898 }
mbed_official 87:085cde657901 2899 }
mbed_official 87:085cde657901 2900 }
mbed_official 87:085cde657901 2901 /**
mbed_official 87:085cde657901 2902 * @}
mbed_official 87:085cde657901 2903 */
mbed_official 87:085cde657901 2904
mbed_official 532:fe11edbda85c 2905 /** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions
mbed_official 87:085cde657901 2906 * @brief Peripheral Control functions
mbed_official 87:085cde657901 2907 *
mbed_official 87:085cde657901 2908 @verbatim
mbed_official 87:085cde657901 2909 ==============================================================================
mbed_official 87:085cde657901 2910 ##### Peripheral Control functions #####
mbed_official 87:085cde657901 2911 ==============================================================================
mbed_official 87:085cde657901 2912 [..]
mbed_official 87:085cde657901 2913 This section provides functions allowing to:
mbed_official 87:085cde657901 2914 (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
mbed_official 87:085cde657901 2915 (+) Configure External Clock source.
mbed_official 87:085cde657901 2916 (+) Configure Complementary channels, break features and dead time.
mbed_official 87:085cde657901 2917 (+) Configure Master and the Slave synchronization.
mbed_official 87:085cde657901 2918 (+) Configure the DMA Burst Mode.
mbed_official 87:085cde657901 2919
mbed_official 87:085cde657901 2920 @endverbatim
mbed_official 87:085cde657901 2921 * @{
mbed_official 87:085cde657901 2922 */
mbed_official 87:085cde657901 2923
mbed_official 87:085cde657901 2924 /**
mbed_official 87:085cde657901 2925 * @brief Initializes the TIM Output Compare Channels according to the specified
mbed_official 87:085cde657901 2926 * parameters in the TIM_OC_InitTypeDef.
mbed_official 226:b062af740e40 2927 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 2928 * the configuration information for TIM module.
mbed_official 87:085cde657901 2929 * @param sConfig: TIM Output Compare configuration structure
mbed_official 226:b062af740e40 2930 * @param Channel: TIM Channels to be enabled.
mbed_official 87:085cde657901 2931 * This parameter can be one of the following values:
mbed_official 87:085cde657901 2932 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 87:085cde657901 2933 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 87:085cde657901 2934 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 87:085cde657901 2935 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 87:085cde657901 2936 * @retval HAL status
mbed_official 87:085cde657901 2937 */
mbed_official 87:085cde657901 2938 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)
mbed_official 87:085cde657901 2939 {
mbed_official 87:085cde657901 2940 /* Check the parameters */
mbed_official 87:085cde657901 2941 assert_param(IS_TIM_CHANNELS(Channel));
mbed_official 87:085cde657901 2942 assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
mbed_official 87:085cde657901 2943 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
mbed_official 87:085cde657901 2944 assert_param(IS_TIM_OCN_POLARITY(sConfig->OCNPolarity));
mbed_official 87:085cde657901 2945 assert_param(IS_TIM_OCNIDLE_STATE(sConfig->OCNIdleState));
mbed_official 87:085cde657901 2946 assert_param(IS_TIM_OCIDLE_STATE(sConfig->OCIdleState));
mbed_official 87:085cde657901 2947
mbed_official 87:085cde657901 2948 /* Check input state */
mbed_official 87:085cde657901 2949 __HAL_LOCK(htim);
mbed_official 87:085cde657901 2950
mbed_official 87:085cde657901 2951 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 87:085cde657901 2952
mbed_official 87:085cde657901 2953 switch (Channel)
mbed_official 87:085cde657901 2954 {
mbed_official 87:085cde657901 2955 case TIM_CHANNEL_1:
mbed_official 87:085cde657901 2956 {
mbed_official 87:085cde657901 2957 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
mbed_official 87:085cde657901 2958 /* Configure the TIM Channel 1 in Output Compare */
mbed_official 87:085cde657901 2959 TIM_OC1_SetConfig(htim->Instance, sConfig);
mbed_official 87:085cde657901 2960 }
mbed_official 87:085cde657901 2961 break;
mbed_official 87:085cde657901 2962
mbed_official 87:085cde657901 2963 case TIM_CHANNEL_2:
mbed_official 87:085cde657901 2964 {
mbed_official 87:085cde657901 2965 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 87:085cde657901 2966 /* Configure the TIM Channel 2 in Output Compare */
mbed_official 87:085cde657901 2967 TIM_OC2_SetConfig(htim->Instance, sConfig);
mbed_official 87:085cde657901 2968 }
mbed_official 87:085cde657901 2969 break;
mbed_official 87:085cde657901 2970
mbed_official 87:085cde657901 2971 case TIM_CHANNEL_3:
mbed_official 87:085cde657901 2972 {
mbed_official 87:085cde657901 2973 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
mbed_official 87:085cde657901 2974 /* Configure the TIM Channel 3 in Output Compare */
mbed_official 87:085cde657901 2975 TIM_OC3_SetConfig(htim->Instance, sConfig);
mbed_official 87:085cde657901 2976 }
mbed_official 87:085cde657901 2977 break;
mbed_official 87:085cde657901 2978
mbed_official 87:085cde657901 2979 case TIM_CHANNEL_4:
mbed_official 87:085cde657901 2980 {
mbed_official 87:085cde657901 2981 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
mbed_official 87:085cde657901 2982 /* Configure the TIM Channel 4 in Output Compare */
mbed_official 87:085cde657901 2983 TIM_OC4_SetConfig(htim->Instance, sConfig);
mbed_official 87:085cde657901 2984 }
mbed_official 87:085cde657901 2985 break;
mbed_official 87:085cde657901 2986
mbed_official 87:085cde657901 2987 default:
mbed_official 87:085cde657901 2988 break;
mbed_official 87:085cde657901 2989 }
mbed_official 87:085cde657901 2990 htim->State = HAL_TIM_STATE_READY;
mbed_official 87:085cde657901 2991
mbed_official 87:085cde657901 2992 __HAL_UNLOCK(htim);
mbed_official 87:085cde657901 2993
mbed_official 87:085cde657901 2994 return HAL_OK;
mbed_official 87:085cde657901 2995 }
mbed_official 87:085cde657901 2996
mbed_official 87:085cde657901 2997 /**
mbed_official 87:085cde657901 2998 * @brief Initializes the TIM Input Capture Channels according to the specified
mbed_official 87:085cde657901 2999 * parameters in the TIM_IC_InitTypeDef.
mbed_official 226:b062af740e40 3000 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 3001 * the configuration information for TIM module.
mbed_official 87:085cde657901 3002 * @param sConfig: TIM Input Capture configuration structure
mbed_official 226:b062af740e40 3003 * @param Channel: TIM Channels to be enabled.
mbed_official 87:085cde657901 3004 * This parameter can be one of the following values:
mbed_official 87:085cde657901 3005 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 87:085cde657901 3006 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 87:085cde657901 3007 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 87:085cde657901 3008 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 87:085cde657901 3009 * @retval HAL status
mbed_official 87:085cde657901 3010 */
mbed_official 87:085cde657901 3011 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel)
mbed_official 87:085cde657901 3012 {
mbed_official 87:085cde657901 3013 /* Check the parameters */
mbed_official 87:085cde657901 3014 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
mbed_official 87:085cde657901 3015 assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
mbed_official 87:085cde657901 3016 assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
mbed_official 87:085cde657901 3017 assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
mbed_official 87:085cde657901 3018 assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
mbed_official 87:085cde657901 3019
mbed_official 87:085cde657901 3020 __HAL_LOCK(htim);
mbed_official 87:085cde657901 3021
mbed_official 87:085cde657901 3022 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 87:085cde657901 3023
mbed_official 87:085cde657901 3024 if (Channel == TIM_CHANNEL_1)
mbed_official 87:085cde657901 3025 {
mbed_official 87:085cde657901 3026 /* TI1 Configuration */
mbed_official 87:085cde657901 3027 TIM_TI1_SetConfig(htim->Instance,
mbed_official 87:085cde657901 3028 sConfig->ICPolarity,
mbed_official 87:085cde657901 3029 sConfig->ICSelection,
mbed_official 87:085cde657901 3030 sConfig->ICFilter);
mbed_official 87:085cde657901 3031
mbed_official 87:085cde657901 3032 /* Reset the IC1PSC Bits */
mbed_official 87:085cde657901 3033 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
mbed_official 87:085cde657901 3034
mbed_official 87:085cde657901 3035 /* Set the IC1PSC value */
mbed_official 87:085cde657901 3036 htim->Instance->CCMR1 |= sConfig->ICPrescaler;
mbed_official 87:085cde657901 3037 }
mbed_official 87:085cde657901 3038 else if (Channel == TIM_CHANNEL_2)
mbed_official 87:085cde657901 3039 {
mbed_official 87:085cde657901 3040 /* TI2 Configuration */
mbed_official 87:085cde657901 3041 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 87:085cde657901 3042
mbed_official 87:085cde657901 3043 TIM_TI2_SetConfig(htim->Instance,
mbed_official 87:085cde657901 3044 sConfig->ICPolarity,
mbed_official 87:085cde657901 3045 sConfig->ICSelection,
mbed_official 87:085cde657901 3046 sConfig->ICFilter);
mbed_official 87:085cde657901 3047
mbed_official 87:085cde657901 3048 /* Reset the IC2PSC Bits */
mbed_official 87:085cde657901 3049 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
mbed_official 87:085cde657901 3050
mbed_official 87:085cde657901 3051 /* Set the IC2PSC value */
mbed_official 87:085cde657901 3052 htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8);
mbed_official 87:085cde657901 3053 }
mbed_official 87:085cde657901 3054 else if (Channel == TIM_CHANNEL_3)
mbed_official 87:085cde657901 3055 {
mbed_official 87:085cde657901 3056 /* TI3 Configuration */
mbed_official 87:085cde657901 3057 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
mbed_official 87:085cde657901 3058
mbed_official 87:085cde657901 3059 TIM_TI3_SetConfig(htim->Instance,
mbed_official 87:085cde657901 3060 sConfig->ICPolarity,
mbed_official 87:085cde657901 3061 sConfig->ICSelection,
mbed_official 87:085cde657901 3062 sConfig->ICFilter);
mbed_official 87:085cde657901 3063
mbed_official 87:085cde657901 3064 /* Reset the IC3PSC Bits */
mbed_official 87:085cde657901 3065 htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
mbed_official 87:085cde657901 3066
mbed_official 87:085cde657901 3067 /* Set the IC3PSC value */
mbed_official 87:085cde657901 3068 htim->Instance->CCMR2 |= sConfig->ICPrescaler;
mbed_official 87:085cde657901 3069 }
mbed_official 87:085cde657901 3070 else
mbed_official 87:085cde657901 3071 {
mbed_official 87:085cde657901 3072 /* TI4 Configuration */
mbed_official 87:085cde657901 3073 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
mbed_official 87:085cde657901 3074
mbed_official 87:085cde657901 3075 TIM_TI4_SetConfig(htim->Instance,
mbed_official 87:085cde657901 3076 sConfig->ICPolarity,
mbed_official 87:085cde657901 3077 sConfig->ICSelection,
mbed_official 87:085cde657901 3078 sConfig->ICFilter);
mbed_official 87:085cde657901 3079
mbed_official 87:085cde657901 3080 /* Reset the IC4PSC Bits */
mbed_official 87:085cde657901 3081 htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
mbed_official 87:085cde657901 3082
mbed_official 87:085cde657901 3083 /* Set the IC4PSC value */
mbed_official 87:085cde657901 3084 htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8);
mbed_official 87:085cde657901 3085 }
mbed_official 87:085cde657901 3086
mbed_official 87:085cde657901 3087 htim->State = HAL_TIM_STATE_READY;
mbed_official 87:085cde657901 3088
mbed_official 87:085cde657901 3089 __HAL_UNLOCK(htim);
mbed_official 87:085cde657901 3090
mbed_official 87:085cde657901 3091 return HAL_OK;
mbed_official 87:085cde657901 3092 }
mbed_official 87:085cde657901 3093
mbed_official 87:085cde657901 3094 /**
mbed_official 87:085cde657901 3095 * @brief Initializes the TIM PWM channels according to the specified
mbed_official 87:085cde657901 3096 * parameters in the TIM_OC_InitTypeDef.
mbed_official 226:b062af740e40 3097 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 3098 * the configuration information for TIM module.
mbed_official 87:085cde657901 3099 * @param sConfig: TIM PWM configuration structure
mbed_official 226:b062af740e40 3100 * @param Channel: TIM Channels to be enabled.
mbed_official 87:085cde657901 3101 * This parameter can be one of the following values:
mbed_official 87:085cde657901 3102 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 87:085cde657901 3103 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 87:085cde657901 3104 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 87:085cde657901 3105 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 87:085cde657901 3106 * @retval HAL status
mbed_official 87:085cde657901 3107 */
mbed_official 87:085cde657901 3108 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)
mbed_official 87:085cde657901 3109 {
mbed_official 87:085cde657901 3110 __HAL_LOCK(htim);
mbed_official 87:085cde657901 3111
mbed_official 87:085cde657901 3112 /* Check the parameters */
mbed_official 87:085cde657901 3113 assert_param(IS_TIM_CHANNELS(Channel));
mbed_official 87:085cde657901 3114 assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
mbed_official 87:085cde657901 3115 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
mbed_official 87:085cde657901 3116 assert_param(IS_TIM_OCN_POLARITY(sConfig->OCNPolarity));
mbed_official 87:085cde657901 3117 assert_param(IS_TIM_OCNIDLE_STATE(sConfig->OCNIdleState));
mbed_official 87:085cde657901 3118 assert_param(IS_TIM_OCIDLE_STATE(sConfig->OCIdleState));
mbed_official 532:fe11edbda85c 3119 assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
mbed_official 532:fe11edbda85c 3120
mbed_official 87:085cde657901 3121 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 87:085cde657901 3122
mbed_official 87:085cde657901 3123 switch (Channel)
mbed_official 87:085cde657901 3124 {
mbed_official 87:085cde657901 3125 case TIM_CHANNEL_1:
mbed_official 87:085cde657901 3126 {
mbed_official 87:085cde657901 3127 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
mbed_official 87:085cde657901 3128 /* Configure the Channel 1 in PWM mode */
mbed_official 87:085cde657901 3129 TIM_OC1_SetConfig(htim->Instance, sConfig);
mbed_official 87:085cde657901 3130
mbed_official 87:085cde657901 3131 /* Set the Preload enable bit for channel1 */
mbed_official 87:085cde657901 3132 htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
mbed_official 87:085cde657901 3133
mbed_official 87:085cde657901 3134 /* Configure the Output Fast mode */
mbed_official 87:085cde657901 3135 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
mbed_official 87:085cde657901 3136 htim->Instance->CCMR1 |= sConfig->OCFastMode;
mbed_official 87:085cde657901 3137 }
mbed_official 87:085cde657901 3138 break;
mbed_official 87:085cde657901 3139
mbed_official 87:085cde657901 3140 case TIM_CHANNEL_2:
mbed_official 87:085cde657901 3141 {
mbed_official 87:085cde657901 3142 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 87:085cde657901 3143 /* Configure the Channel 2 in PWM mode */
mbed_official 87:085cde657901 3144 TIM_OC2_SetConfig(htim->Instance, sConfig);
mbed_official 87:085cde657901 3145
mbed_official 87:085cde657901 3146 /* Set the Preload enable bit for channel2 */
mbed_official 87:085cde657901 3147 htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
mbed_official 87:085cde657901 3148
mbed_official 87:085cde657901 3149 /* Configure the Output Fast mode */
mbed_official 87:085cde657901 3150 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
mbed_official 87:085cde657901 3151 htim->Instance->CCMR1 |= sConfig->OCFastMode << 8;
mbed_official 87:085cde657901 3152 }
mbed_official 87:085cde657901 3153 break;
mbed_official 87:085cde657901 3154
mbed_official 87:085cde657901 3155 case TIM_CHANNEL_3:
mbed_official 87:085cde657901 3156 {
mbed_official 87:085cde657901 3157 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
mbed_official 87:085cde657901 3158 /* Configure the Channel 3 in PWM mode */
mbed_official 87:085cde657901 3159 TIM_OC3_SetConfig(htim->Instance, sConfig);
mbed_official 87:085cde657901 3160
mbed_official 87:085cde657901 3161 /* Set the Preload enable bit for channel3 */
mbed_official 87:085cde657901 3162 htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
mbed_official 87:085cde657901 3163
mbed_official 87:085cde657901 3164 /* Configure the Output Fast mode */
mbed_official 87:085cde657901 3165 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
mbed_official 87:085cde657901 3166 htim->Instance->CCMR2 |= sConfig->OCFastMode;
mbed_official 87:085cde657901 3167 }
mbed_official 87:085cde657901 3168 break;
mbed_official 87:085cde657901 3169
mbed_official 87:085cde657901 3170 case TIM_CHANNEL_4:
mbed_official 87:085cde657901 3171 {
mbed_official 87:085cde657901 3172 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
mbed_official 87:085cde657901 3173 /* Configure the Channel 4 in PWM mode */
mbed_official 87:085cde657901 3174 TIM_OC4_SetConfig(htim->Instance, sConfig);
mbed_official 87:085cde657901 3175
mbed_official 87:085cde657901 3176 /* Set the Preload enable bit for channel4 */
mbed_official 87:085cde657901 3177 htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
mbed_official 87:085cde657901 3178
mbed_official 87:085cde657901 3179 /* Configure the Output Fast mode */
mbed_official 87:085cde657901 3180 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
mbed_official 87:085cde657901 3181 htim->Instance->CCMR2 |= sConfig->OCFastMode << 8;
mbed_official 87:085cde657901 3182 }
mbed_official 87:085cde657901 3183 break;
mbed_official 87:085cde657901 3184
mbed_official 87:085cde657901 3185 default:
mbed_official 87:085cde657901 3186 break;
mbed_official 87:085cde657901 3187 }
mbed_official 87:085cde657901 3188
mbed_official 87:085cde657901 3189 htim->State = HAL_TIM_STATE_READY;
mbed_official 87:085cde657901 3190
mbed_official 87:085cde657901 3191 __HAL_UNLOCK(htim);
mbed_official 87:085cde657901 3192
mbed_official 87:085cde657901 3193 return HAL_OK;
mbed_official 87:085cde657901 3194 }
mbed_official 87:085cde657901 3195
mbed_official 87:085cde657901 3196 /**
mbed_official 87:085cde657901 3197 * @brief Initializes the TIM One Pulse Channels according to the specified
mbed_official 87:085cde657901 3198 * parameters in the TIM_OnePulse_InitTypeDef.
mbed_official 226:b062af740e40 3199 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 3200 * the configuration information for TIM module.
mbed_official 87:085cde657901 3201 * @param sConfig: TIM One Pulse configuration structure
mbed_official 226:b062af740e40 3202 * @param OutputChannel: TIM Channels to be enabled.
mbed_official 87:085cde657901 3203 * This parameter can be one of the following values:
mbed_official 87:085cde657901 3204 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 87:085cde657901 3205 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 226:b062af740e40 3206 * @param InputChannel: TIM Channels to be enabled.
mbed_official 87:085cde657901 3207 * This parameter can be one of the following values:
mbed_official 87:085cde657901 3208 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 87:085cde657901 3209 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 87:085cde657901 3210 * @retval HAL status
mbed_official 87:085cde657901 3211 */
mbed_official 87:085cde657901 3212 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel)
mbed_official 87:085cde657901 3213 {
mbed_official 87:085cde657901 3214 TIM_OC_InitTypeDef temp1;
mbed_official 87:085cde657901 3215
mbed_official 87:085cde657901 3216 /* Check the parameters */
mbed_official 87:085cde657901 3217 assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
mbed_official 87:085cde657901 3218 assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
mbed_official 87:085cde657901 3219
mbed_official 87:085cde657901 3220 if(OutputChannel != InputChannel)
mbed_official 87:085cde657901 3221 {
mbed_official 87:085cde657901 3222 __HAL_LOCK(htim);
mbed_official 87:085cde657901 3223
mbed_official 87:085cde657901 3224 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 87:085cde657901 3225
mbed_official 532:fe11edbda85c 3226 /* Extract the Output compare configuration from sConfig structure */
mbed_official 87:085cde657901 3227 temp1.OCMode = sConfig->OCMode;
mbed_official 87:085cde657901 3228 temp1.Pulse = sConfig->Pulse;
mbed_official 87:085cde657901 3229 temp1.OCPolarity = sConfig->OCPolarity;
mbed_official 87:085cde657901 3230 temp1.OCNPolarity = sConfig->OCNPolarity;
mbed_official 87:085cde657901 3231 temp1.OCIdleState = sConfig->OCIdleState;
mbed_official 87:085cde657901 3232 temp1.OCNIdleState = sConfig->OCNIdleState;
mbed_official 87:085cde657901 3233
mbed_official 87:085cde657901 3234 switch (OutputChannel)
mbed_official 87:085cde657901 3235 {
mbed_official 87:085cde657901 3236 case TIM_CHANNEL_1:
mbed_official 87:085cde657901 3237 {
mbed_official 87:085cde657901 3238 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
mbed_official 87:085cde657901 3239
mbed_official 87:085cde657901 3240 TIM_OC1_SetConfig(htim->Instance, &temp1);
mbed_official 87:085cde657901 3241 }
mbed_official 87:085cde657901 3242 break;
mbed_official 87:085cde657901 3243 case TIM_CHANNEL_2:
mbed_official 87:085cde657901 3244 {
mbed_official 87:085cde657901 3245 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 87:085cde657901 3246
mbed_official 87:085cde657901 3247 TIM_OC2_SetConfig(htim->Instance, &temp1);
mbed_official 87:085cde657901 3248 }
mbed_official 87:085cde657901 3249 break;
mbed_official 87:085cde657901 3250 default:
mbed_official 87:085cde657901 3251 break;
mbed_official 87:085cde657901 3252 }
mbed_official 87:085cde657901 3253 switch (InputChannel)
mbed_official 87:085cde657901 3254 {
mbed_official 87:085cde657901 3255 case TIM_CHANNEL_1:
mbed_official 87:085cde657901 3256 {
mbed_official 87:085cde657901 3257 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
mbed_official 87:085cde657901 3258
mbed_official 87:085cde657901 3259 TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
mbed_official 87:085cde657901 3260 sConfig->ICSelection, sConfig->ICFilter);
mbed_official 87:085cde657901 3261
mbed_official 87:085cde657901 3262 /* Reset the IC1PSC Bits */
mbed_official 87:085cde657901 3263 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
mbed_official 87:085cde657901 3264
mbed_official 87:085cde657901 3265 /* Select the Trigger source */
mbed_official 87:085cde657901 3266 htim->Instance->SMCR &= ~TIM_SMCR_TS;
mbed_official 87:085cde657901 3267 htim->Instance->SMCR |= TIM_TS_TI1FP1;
mbed_official 87:085cde657901 3268
mbed_official 87:085cde657901 3269 /* Select the Slave Mode */
mbed_official 87:085cde657901 3270 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
mbed_official 87:085cde657901 3271 htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
mbed_official 87:085cde657901 3272 }
mbed_official 87:085cde657901 3273 break;
mbed_official 87:085cde657901 3274 case TIM_CHANNEL_2:
mbed_official 87:085cde657901 3275 {
mbed_official 87:085cde657901 3276 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 87:085cde657901 3277
mbed_official 87:085cde657901 3278 TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
mbed_official 87:085cde657901 3279 sConfig->ICSelection, sConfig->ICFilter);
mbed_official 87:085cde657901 3280
mbed_official 87:085cde657901 3281 /* Reset the IC2PSC Bits */
mbed_official 87:085cde657901 3282 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
mbed_official 87:085cde657901 3283
mbed_official 87:085cde657901 3284 /* Select the Trigger source */
mbed_official 87:085cde657901 3285 htim->Instance->SMCR &= ~TIM_SMCR_TS;
mbed_official 87:085cde657901 3286 htim->Instance->SMCR |= TIM_TS_TI2FP2;
mbed_official 87:085cde657901 3287
mbed_official 87:085cde657901 3288 /* Select the Slave Mode */
mbed_official 87:085cde657901 3289 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
mbed_official 87:085cde657901 3290 htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
mbed_official 87:085cde657901 3291 }
mbed_official 87:085cde657901 3292 break;
mbed_official 87:085cde657901 3293
mbed_official 87:085cde657901 3294 default:
mbed_official 87:085cde657901 3295 break;
mbed_official 87:085cde657901 3296 }
mbed_official 87:085cde657901 3297
mbed_official 87:085cde657901 3298 htim->State = HAL_TIM_STATE_READY;
mbed_official 87:085cde657901 3299
mbed_official 87:085cde657901 3300 __HAL_UNLOCK(htim);
mbed_official 87:085cde657901 3301
mbed_official 87:085cde657901 3302 return HAL_OK;
mbed_official 87:085cde657901 3303 }
mbed_official 87:085cde657901 3304 else
mbed_official 87:085cde657901 3305 {
mbed_official 87:085cde657901 3306 return HAL_ERROR;
mbed_official 87:085cde657901 3307 }
mbed_official 87:085cde657901 3308 }
mbed_official 87:085cde657901 3309
mbed_official 87:085cde657901 3310 /**
mbed_official 87:085cde657901 3311 * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
mbed_official 226:b062af740e40 3312 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 3313 * the configuration information for TIM module.
mbed_official 226:b062af740e40 3314 * @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data write.
mbed_official 87:085cde657901 3315 * This parameters can be on of the following values:
mbed_official 532:fe11edbda85c 3316 * @arg TIM_DMABASE_CR1
mbed_official 532:fe11edbda85c 3317 * @arg TIM_DMABASE_CR2
mbed_official 532:fe11edbda85c 3318 * @arg TIM_DMABASE_SMCR
mbed_official 532:fe11edbda85c 3319 * @arg TIM_DMABASE_DIER
mbed_official 532:fe11edbda85c 3320 * @arg TIM_DMABASE_SR
mbed_official 532:fe11edbda85c 3321 * @arg TIM_DMABASE_EGR
mbed_official 532:fe11edbda85c 3322 * @arg TIM_DMABASE_CCMR1
mbed_official 532:fe11edbda85c 3323 * @arg TIM_DMABASE_CCMR2
mbed_official 532:fe11edbda85c 3324 * @arg TIM_DMABASE_CCER
mbed_official 532:fe11edbda85c 3325 * @arg TIM_DMABASE_CNT
mbed_official 532:fe11edbda85c 3326 * @arg TIM_DMABASE_PSC
mbed_official 532:fe11edbda85c 3327 * @arg TIM_DMABASE_ARR
mbed_official 532:fe11edbda85c 3328 * @arg TIM_DMABASE_RCR
mbed_official 532:fe11edbda85c 3329 * @arg TIM_DMABASE_CCR1
mbed_official 532:fe11edbda85c 3330 * @arg TIM_DMABASE_CCR2
mbed_official 532:fe11edbda85c 3331 * @arg TIM_DMABASE_CCR3
mbed_official 532:fe11edbda85c 3332 * @arg TIM_DMABASE_CCR4
mbed_official 532:fe11edbda85c 3333 * @arg TIM_DMABASE_BDTR
mbed_official 532:fe11edbda85c 3334 * @arg TIM_DMABASE_DCR
mbed_official 226:b062af740e40 3335 * @param BurstRequestSrc: TIM DMA Request sources.
mbed_official 87:085cde657901 3336 * This parameters can be on of the following values:
mbed_official 87:085cde657901 3337 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
mbed_official 87:085cde657901 3338 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
mbed_official 87:085cde657901 3339 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
mbed_official 87:085cde657901 3340 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
mbed_official 87:085cde657901 3341 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
mbed_official 87:085cde657901 3342 * @arg TIM_DMA_COM: TIM Commutation DMA source
mbed_official 87:085cde657901 3343 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
mbed_official 87:085cde657901 3344 * @param BurstBuffer: The Buffer address.
mbed_official 87:085cde657901 3345 * @param BurstLength: DMA Burst length. This parameter can be one value
mbed_official 532:fe11edbda85c 3346 * between TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
mbed_official 87:085cde657901 3347 * @retval HAL status
mbed_official 87:085cde657901 3348 */
mbed_official 87:085cde657901 3349 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
mbed_official 87:085cde657901 3350 uint32_t* BurstBuffer, uint32_t BurstLength)
mbed_official 87:085cde657901 3351 {
mbed_official 87:085cde657901 3352 /* Check the parameters */
mbed_official 87:085cde657901 3353 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
mbed_official 87:085cde657901 3354 assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
mbed_official 87:085cde657901 3355 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
mbed_official 87:085cde657901 3356 assert_param(IS_TIM_DMA_LENGTH(BurstLength));
mbed_official 87:085cde657901 3357
mbed_official 87:085cde657901 3358 if((htim->State == HAL_TIM_STATE_BUSY))
mbed_official 87:085cde657901 3359 {
mbed_official 87:085cde657901 3360 return HAL_BUSY;
mbed_official 87:085cde657901 3361 }
mbed_official 87:085cde657901 3362 else if((htim->State == HAL_TIM_STATE_READY))
mbed_official 87:085cde657901 3363 {
mbed_official 87:085cde657901 3364 if((BurstBuffer == 0 ) && (BurstLength > 0))
mbed_official 87:085cde657901 3365 {
mbed_official 87:085cde657901 3366 return HAL_ERROR;
mbed_official 87:085cde657901 3367 }
mbed_official 87:085cde657901 3368 else
mbed_official 87:085cde657901 3369 {
mbed_official 87:085cde657901 3370 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 87:085cde657901 3371 }
mbed_official 87:085cde657901 3372 }
mbed_official 87:085cde657901 3373 switch(BurstRequestSrc)
mbed_official 87:085cde657901 3374 {
mbed_official 87:085cde657901 3375 case TIM_DMA_UPDATE:
mbed_official 87:085cde657901 3376 {
mbed_official 87:085cde657901 3377 /* Set the DMA Period elapsed callback */
mbed_official 87:085cde657901 3378 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
mbed_official 87:085cde657901 3379
mbed_official 87:085cde657901 3380 /* Set the DMA error callback */
mbed_official 532:fe11edbda85c 3381 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
mbed_official 87:085cde657901 3382
mbed_official 87:085cde657901 3383 /* Enable the DMA Stream */
mbed_official 87:085cde657901 3384 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
mbed_official 87:085cde657901 3385 }
mbed_official 87:085cde657901 3386 break;
mbed_official 87:085cde657901 3387 case TIM_DMA_CC1:
mbed_official 87:085cde657901 3388 {
mbed_official 87:085cde657901 3389 /* Set the DMA Period elapsed callback */
mbed_official 532:fe11edbda85c 3390 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
mbed_official 87:085cde657901 3391
mbed_official 87:085cde657901 3392 /* Set the DMA error callback */
mbed_official 532:fe11edbda85c 3393 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
mbed_official 87:085cde657901 3394
mbed_official 87:085cde657901 3395 /* Enable the DMA Stream */
mbed_official 87:085cde657901 3396 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
mbed_official 87:085cde657901 3397 }
mbed_official 87:085cde657901 3398 break;
mbed_official 87:085cde657901 3399 case TIM_DMA_CC2:
mbed_official 87:085cde657901 3400 {
mbed_official 87:085cde657901 3401 /* Set the DMA Period elapsed callback */
mbed_official 532:fe11edbda85c 3402 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
mbed_official 87:085cde657901 3403
mbed_official 87:085cde657901 3404 /* Set the DMA error callback */
mbed_official 532:fe11edbda85c 3405 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
mbed_official 87:085cde657901 3406
mbed_official 87:085cde657901 3407 /* Enable the DMA Stream */
mbed_official 87:085cde657901 3408 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
mbed_official 87:085cde657901 3409 }
mbed_official 87:085cde657901 3410 break;
mbed_official 87:085cde657901 3411 case TIM_DMA_CC3:
mbed_official 87:085cde657901 3412 {
mbed_official 87:085cde657901 3413 /* Set the DMA Period elapsed callback */
mbed_official 532:fe11edbda85c 3414 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
mbed_official 87:085cde657901 3415
mbed_official 87:085cde657901 3416 /* Set the DMA error callback */
mbed_official 532:fe11edbda85c 3417 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
mbed_official 87:085cde657901 3418
mbed_official 87:085cde657901 3419 /* Enable the DMA Stream */
mbed_official 87:085cde657901 3420 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
mbed_official 87:085cde657901 3421 }
mbed_official 87:085cde657901 3422 break;
mbed_official 87:085cde657901 3423 case TIM_DMA_CC4:
mbed_official 87:085cde657901 3424 {
mbed_official 87:085cde657901 3425 /* Set the DMA Period elapsed callback */
mbed_official 532:fe11edbda85c 3426 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
mbed_official 87:085cde657901 3427
mbed_official 87:085cde657901 3428 /* Set the DMA error callback */
mbed_official 532:fe11edbda85c 3429 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
mbed_official 87:085cde657901 3430
mbed_official 87:085cde657901 3431 /* Enable the DMA Stream */
mbed_official 87:085cde657901 3432 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
mbed_official 87:085cde657901 3433 }
mbed_official 87:085cde657901 3434 break;
mbed_official 87:085cde657901 3435 case TIM_DMA_COM:
mbed_official 87:085cde657901 3436 {
mbed_official 87:085cde657901 3437 /* Set the DMA Period elapsed callback */
mbed_official 532:fe11edbda85c 3438 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
mbed_official 87:085cde657901 3439
mbed_official 87:085cde657901 3440 /* Set the DMA error callback */
mbed_official 532:fe11edbda85c 3441 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
mbed_official 87:085cde657901 3442
mbed_official 87:085cde657901 3443 /* Enable the DMA Stream */
mbed_official 87:085cde657901 3444 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
mbed_official 87:085cde657901 3445 }
mbed_official 87:085cde657901 3446 break;
mbed_official 87:085cde657901 3447 case TIM_DMA_TRIGGER:
mbed_official 87:085cde657901 3448 {
mbed_official 87:085cde657901 3449 /* Set the DMA Period elapsed callback */
mbed_official 87:085cde657901 3450 htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
mbed_official 87:085cde657901 3451
mbed_official 87:085cde657901 3452 /* Set the DMA error callback */
mbed_official 532:fe11edbda85c 3453 htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
mbed_official 87:085cde657901 3454
mbed_official 87:085cde657901 3455 /* Enable the DMA Stream */
mbed_official 87:085cde657901 3456 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
mbed_official 87:085cde657901 3457 }
mbed_official 87:085cde657901 3458 break;
mbed_official 87:085cde657901 3459 default:
mbed_official 87:085cde657901 3460 break;
mbed_official 87:085cde657901 3461 }
mbed_official 87:085cde657901 3462 /* configure the DMA Burst Mode */
mbed_official 87:085cde657901 3463 htim->Instance->DCR = BurstBaseAddress | BurstLength;
mbed_official 87:085cde657901 3464
mbed_official 87:085cde657901 3465 /* Enable the TIM DMA Request */
mbed_official 87:085cde657901 3466 __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
mbed_official 87:085cde657901 3467
mbed_official 87:085cde657901 3468 htim->State = HAL_TIM_STATE_READY;
mbed_official 87:085cde657901 3469
mbed_official 87:085cde657901 3470 /* Return function status */
mbed_official 87:085cde657901 3471 return HAL_OK;
mbed_official 87:085cde657901 3472 }
mbed_official 87:085cde657901 3473
mbed_official 87:085cde657901 3474 /**
mbed_official 87:085cde657901 3475 * @brief Stops the TIM DMA Burst mode
mbed_official 226:b062af740e40 3476 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 3477 * the configuration information for TIM module.
mbed_official 87:085cde657901 3478 * @param BurstRequestSrc: TIM DMA Request sources to disable
mbed_official 87:085cde657901 3479 * @retval HAL status
mbed_official 87:085cde657901 3480 */
mbed_official 87:085cde657901 3481 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
mbed_official 87:085cde657901 3482 {
mbed_official 87:085cde657901 3483 /* Check the parameters */
mbed_official 87:085cde657901 3484 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
mbed_official 87:085cde657901 3485
mbed_official 532:fe11edbda85c 3486 /* Abort the DMA transfer (at least disable the DMA channel) */
mbed_official 532:fe11edbda85c 3487 switch(BurstRequestSrc)
mbed_official 532:fe11edbda85c 3488 {
mbed_official 532:fe11edbda85c 3489 case TIM_DMA_UPDATE:
mbed_official 532:fe11edbda85c 3490 {
mbed_official 532:fe11edbda85c 3491 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
mbed_official 532:fe11edbda85c 3492 }
mbed_official 532:fe11edbda85c 3493 break;
mbed_official 532:fe11edbda85c 3494 case TIM_DMA_CC1:
mbed_official 532:fe11edbda85c 3495 {
mbed_official 532:fe11edbda85c 3496 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
mbed_official 532:fe11edbda85c 3497 }
mbed_official 532:fe11edbda85c 3498 break;
mbed_official 532:fe11edbda85c 3499 case TIM_DMA_CC2:
mbed_official 532:fe11edbda85c 3500 {
mbed_official 532:fe11edbda85c 3501 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
mbed_official 532:fe11edbda85c 3502 }
mbed_official 532:fe11edbda85c 3503 break;
mbed_official 532:fe11edbda85c 3504 case TIM_DMA_CC3:
mbed_official 532:fe11edbda85c 3505 {
mbed_official 532:fe11edbda85c 3506 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
mbed_official 532:fe11edbda85c 3507 }
mbed_official 532:fe11edbda85c 3508 break;
mbed_official 532:fe11edbda85c 3509 case TIM_DMA_CC4:
mbed_official 532:fe11edbda85c 3510 {
mbed_official 532:fe11edbda85c 3511 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
mbed_official 532:fe11edbda85c 3512 }
mbed_official 532:fe11edbda85c 3513 break;
mbed_official 532:fe11edbda85c 3514 case TIM_DMA_COM:
mbed_official 532:fe11edbda85c 3515 {
mbed_official 532:fe11edbda85c 3516 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
mbed_official 532:fe11edbda85c 3517 }
mbed_official 532:fe11edbda85c 3518 break;
mbed_official 532:fe11edbda85c 3519 case TIM_DMA_TRIGGER:
mbed_official 532:fe11edbda85c 3520 {
mbed_official 532:fe11edbda85c 3521 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
mbed_official 532:fe11edbda85c 3522 }
mbed_official 532:fe11edbda85c 3523 break;
mbed_official 532:fe11edbda85c 3524 default:
mbed_official 532:fe11edbda85c 3525 break;
mbed_official 532:fe11edbda85c 3526 }
mbed_official 532:fe11edbda85c 3527
mbed_official 87:085cde657901 3528 /* Disable the TIM Update DMA request */
mbed_official 87:085cde657901 3529 __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
mbed_official 87:085cde657901 3530
mbed_official 87:085cde657901 3531 /* Return function status */
mbed_official 87:085cde657901 3532 return HAL_OK;
mbed_official 87:085cde657901 3533 }
mbed_official 87:085cde657901 3534
mbed_official 87:085cde657901 3535 /**
mbed_official 87:085cde657901 3536 * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
mbed_official 226:b062af740e40 3537 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 3538 * the configuration information for TIM module.
mbed_official 226:b062af740e40 3539 * @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data read.
mbed_official 87:085cde657901 3540 * This parameters can be on of the following values:
mbed_official 532:fe11edbda85c 3541 * @arg TIM_DMABASE_CR1
mbed_official 532:fe11edbda85c 3542 * @arg TIM_DMABASE_CR2
mbed_official 532:fe11edbda85c 3543 * @arg TIM_DMABASE_SMCR
mbed_official 532:fe11edbda85c 3544 * @arg TIM_DMABASE_DIER
mbed_official 532:fe11edbda85c 3545 * @arg TIM_DMABASE_SR
mbed_official 532:fe11edbda85c 3546 * @arg TIM_DMABASE_EGR
mbed_official 532:fe11edbda85c 3547 * @arg TIM_DMABASE_CCMR1
mbed_official 532:fe11edbda85c 3548 * @arg TIM_DMABASE_CCMR2
mbed_official 532:fe11edbda85c 3549 * @arg TIM_DMABASE_CCER
mbed_official 532:fe11edbda85c 3550 * @arg TIM_DMABASE_CNT
mbed_official 532:fe11edbda85c 3551 * @arg TIM_DMABASE_PSC
mbed_official 532:fe11edbda85c 3552 * @arg TIM_DMABASE_ARR
mbed_official 532:fe11edbda85c 3553 * @arg TIM_DMABASE_RCR
mbed_official 532:fe11edbda85c 3554 * @arg TIM_DMABASE_CCR1
mbed_official 532:fe11edbda85c 3555 * @arg TIM_DMABASE_CCR2
mbed_official 532:fe11edbda85c 3556 * @arg TIM_DMABASE_CCR3
mbed_official 532:fe11edbda85c 3557 * @arg TIM_DMABASE_CCR4
mbed_official 532:fe11edbda85c 3558 * @arg TIM_DMABASE_BDTR
mbed_official 532:fe11edbda85c 3559 * @arg TIM_DMABASE_DCR
mbed_official 226:b062af740e40 3560 * @param BurstRequestSrc: TIM DMA Request sources.
mbed_official 87:085cde657901 3561 * This parameters can be on of the following values:
mbed_official 87:085cde657901 3562 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
mbed_official 87:085cde657901 3563 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
mbed_official 87:085cde657901 3564 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
mbed_official 87:085cde657901 3565 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
mbed_official 87:085cde657901 3566 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
mbed_official 87:085cde657901 3567 * @arg TIM_DMA_COM: TIM Commutation DMA source
mbed_official 87:085cde657901 3568 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
mbed_official 87:085cde657901 3569 * @param BurstBuffer: The Buffer address.
mbed_official 87:085cde657901 3570 * @param BurstLength: DMA Burst length. This parameter can be one value
mbed_official 532:fe11edbda85c 3571 * between TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
mbed_official 87:085cde657901 3572 * @retval HAL status
mbed_official 87:085cde657901 3573 */
mbed_official 87:085cde657901 3574 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
mbed_official 87:085cde657901 3575 uint32_t *BurstBuffer, uint32_t BurstLength)
mbed_official 87:085cde657901 3576 {
mbed_official 87:085cde657901 3577 /* Check the parameters */
mbed_official 87:085cde657901 3578 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
mbed_official 87:085cde657901 3579 assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
mbed_official 87:085cde657901 3580 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
mbed_official 87:085cde657901 3581 assert_param(IS_TIM_DMA_LENGTH(BurstLength));
mbed_official 87:085cde657901 3582
mbed_official 87:085cde657901 3583 if((htim->State == HAL_TIM_STATE_BUSY))
mbed_official 87:085cde657901 3584 {
mbed_official 87:085cde657901 3585 return HAL_BUSY;
mbed_official 87:085cde657901 3586 }
mbed_official 87:085cde657901 3587 else if((htim->State == HAL_TIM_STATE_READY))
mbed_official 87:085cde657901 3588 {
mbed_official 87:085cde657901 3589 if((BurstBuffer == 0 ) && (BurstLength > 0))
mbed_official 87:085cde657901 3590 {
mbed_official 87:085cde657901 3591 return HAL_ERROR;
mbed_official 87:085cde657901 3592 }
mbed_official 87:085cde657901 3593 else
mbed_official 87:085cde657901 3594 {
mbed_official 87:085cde657901 3595 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 87:085cde657901 3596 }
mbed_official 87:085cde657901 3597 }
mbed_official 87:085cde657901 3598 switch(BurstRequestSrc)
mbed_official 87:085cde657901 3599 {
mbed_official 87:085cde657901 3600 case TIM_DMA_UPDATE:
mbed_official 87:085cde657901 3601 {
mbed_official 87:085cde657901 3602 /* Set the DMA Period elapsed callback */
mbed_official 87:085cde657901 3603 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
mbed_official 87:085cde657901 3604
mbed_official 87:085cde657901 3605 /* Set the DMA error callback */
mbed_official 532:fe11edbda85c 3606 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
mbed_official 87:085cde657901 3607
mbed_official 87:085cde657901 3608 /* Enable the DMA Stream */
mbed_official 87:085cde657901 3609 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
mbed_official 87:085cde657901 3610 }
mbed_official 87:085cde657901 3611 break;
mbed_official 87:085cde657901 3612 case TIM_DMA_CC1:
mbed_official 87:085cde657901 3613 {
mbed_official 87:085cde657901 3614 /* Set the DMA Period elapsed callback */
mbed_official 532:fe11edbda85c 3615 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
mbed_official 87:085cde657901 3616
mbed_official 87:085cde657901 3617 /* Set the DMA error callback */
mbed_official 532:fe11edbda85c 3618 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
mbed_official 87:085cde657901 3619
mbed_official 87:085cde657901 3620 /* Enable the DMA Stream */
mbed_official 87:085cde657901 3621 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
mbed_official 87:085cde657901 3622 }
mbed_official 87:085cde657901 3623 break;
mbed_official 87:085cde657901 3624 case TIM_DMA_CC2:
mbed_official 87:085cde657901 3625 {
mbed_official 87:085cde657901 3626 /* Set the DMA Period elapsed callback */
mbed_official 532:fe11edbda85c 3627 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
mbed_official 87:085cde657901 3628
mbed_official 87:085cde657901 3629 /* Set the DMA error callback */
mbed_official 532:fe11edbda85c 3630 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
mbed_official 87:085cde657901 3631
mbed_official 87:085cde657901 3632 /* Enable the DMA Stream */
mbed_official 87:085cde657901 3633 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
mbed_official 87:085cde657901 3634 }
mbed_official 87:085cde657901 3635 break;
mbed_official 87:085cde657901 3636 case TIM_DMA_CC3:
mbed_official 87:085cde657901 3637 {
mbed_official 87:085cde657901 3638 /* Set the DMA Period elapsed callback */
mbed_official 532:fe11edbda85c 3639 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
mbed_official 87:085cde657901 3640
mbed_official 87:085cde657901 3641 /* Set the DMA error callback */
mbed_official 532:fe11edbda85c 3642 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
mbed_official 87:085cde657901 3643
mbed_official 87:085cde657901 3644 /* Enable the DMA Stream */
mbed_official 87:085cde657901 3645 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
mbed_official 87:085cde657901 3646 }
mbed_official 87:085cde657901 3647 break;
mbed_official 87:085cde657901 3648 case TIM_DMA_CC4:
mbed_official 87:085cde657901 3649 {
mbed_official 87:085cde657901 3650 /* Set the DMA Period elapsed callback */
mbed_official 532:fe11edbda85c 3651 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
mbed_official 87:085cde657901 3652
mbed_official 87:085cde657901 3653 /* Set the DMA error callback */
mbed_official 532:fe11edbda85c 3654 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
mbed_official 87:085cde657901 3655
mbed_official 87:085cde657901 3656 /* Enable the DMA Stream */
mbed_official 87:085cde657901 3657 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
mbed_official 87:085cde657901 3658 }
mbed_official 87:085cde657901 3659 break;
mbed_official 87:085cde657901 3660 case TIM_DMA_COM:
mbed_official 87:085cde657901 3661 {
mbed_official 87:085cde657901 3662 /* Set the DMA Period elapsed callback */
mbed_official 532:fe11edbda85c 3663 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
mbed_official 87:085cde657901 3664
mbed_official 87:085cde657901 3665 /* Set the DMA error callback */
mbed_official 532:fe11edbda85c 3666 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
mbed_official 87:085cde657901 3667
mbed_official 87:085cde657901 3668 /* Enable the DMA Stream */
mbed_official 87:085cde657901 3669 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
mbed_official 87:085cde657901 3670 }
mbed_official 87:085cde657901 3671 break;
mbed_official 87:085cde657901 3672 case TIM_DMA_TRIGGER:
mbed_official 87:085cde657901 3673 {
mbed_official 87:085cde657901 3674 /* Set the DMA Period elapsed callback */
mbed_official 87:085cde657901 3675 htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
mbed_official 87:085cde657901 3676
mbed_official 87:085cde657901 3677 /* Set the DMA error callback */
mbed_official 532:fe11edbda85c 3678 htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
mbed_official 87:085cde657901 3679
mbed_official 87:085cde657901 3680 /* Enable the DMA Stream */
mbed_official 87:085cde657901 3681 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
mbed_official 87:085cde657901 3682 }
mbed_official 87:085cde657901 3683 break;
mbed_official 87:085cde657901 3684 default:
mbed_official 87:085cde657901 3685 break;
mbed_official 87:085cde657901 3686 }
mbed_official 87:085cde657901 3687
mbed_official 87:085cde657901 3688 /* configure the DMA Burst Mode */
mbed_official 87:085cde657901 3689 htim->Instance->DCR = BurstBaseAddress | BurstLength;
mbed_official 87:085cde657901 3690
mbed_official 87:085cde657901 3691 /* Enable the TIM DMA Request */
mbed_official 87:085cde657901 3692 __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
mbed_official 87:085cde657901 3693
mbed_official 87:085cde657901 3694 htim->State = HAL_TIM_STATE_READY;
mbed_official 87:085cde657901 3695
mbed_official 87:085cde657901 3696 /* Return function status */
mbed_official 87:085cde657901 3697 return HAL_OK;
mbed_official 87:085cde657901 3698 }
mbed_official 87:085cde657901 3699
mbed_official 87:085cde657901 3700 /**
mbed_official 87:085cde657901 3701 * @brief Stop the DMA burst reading
mbed_official 226:b062af740e40 3702 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 3703 * the configuration information for TIM module.
mbed_official 87:085cde657901 3704 * @param BurstRequestSrc: TIM DMA Request sources to disable.
mbed_official 87:085cde657901 3705 * @retval HAL status
mbed_official 87:085cde657901 3706 */
mbed_official 87:085cde657901 3707 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
mbed_official 87:085cde657901 3708 {
mbed_official 87:085cde657901 3709 /* Check the parameters */
mbed_official 87:085cde657901 3710 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
mbed_official 87:085cde657901 3711
mbed_official 532:fe11edbda85c 3712 /* Abort the DMA transfer (at least disable the DMA channel) */
mbed_official 532:fe11edbda85c 3713 switch(BurstRequestSrc)
mbed_official 532:fe11edbda85c 3714 {
mbed_official 532:fe11edbda85c 3715 case TIM_DMA_UPDATE:
mbed_official 532:fe11edbda85c 3716 {
mbed_official 532:fe11edbda85c 3717 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
mbed_official 532:fe11edbda85c 3718 }
mbed_official 532:fe11edbda85c 3719 break;
mbed_official 532:fe11edbda85c 3720 case TIM_DMA_CC1:
mbed_official 532:fe11edbda85c 3721 {
mbed_official 532:fe11edbda85c 3722 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
mbed_official 532:fe11edbda85c 3723 }
mbed_official 532:fe11edbda85c 3724 break;
mbed_official 532:fe11edbda85c 3725 case TIM_DMA_CC2:
mbed_official 532:fe11edbda85c 3726 {
mbed_official 532:fe11edbda85c 3727 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
mbed_official 532:fe11edbda85c 3728 }
mbed_official 532:fe11edbda85c 3729 break;
mbed_official 532:fe11edbda85c 3730 case TIM_DMA_CC3:
mbed_official 532:fe11edbda85c 3731 {
mbed_official 532:fe11edbda85c 3732 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
mbed_official 532:fe11edbda85c 3733 }
mbed_official 532:fe11edbda85c 3734 break;
mbed_official 532:fe11edbda85c 3735 case TIM_DMA_CC4:
mbed_official 532:fe11edbda85c 3736 {
mbed_official 532:fe11edbda85c 3737 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
mbed_official 532:fe11edbda85c 3738 }
mbed_official 532:fe11edbda85c 3739 break;
mbed_official 532:fe11edbda85c 3740 case TIM_DMA_COM:
mbed_official 532:fe11edbda85c 3741 {
mbed_official 532:fe11edbda85c 3742 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_COMMUTATION]);
mbed_official 532:fe11edbda85c 3743 }
mbed_official 532:fe11edbda85c 3744 break;
mbed_official 532:fe11edbda85c 3745 case TIM_DMA_TRIGGER:
mbed_official 532:fe11edbda85c 3746 {
mbed_official 532:fe11edbda85c 3747 HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
mbed_official 532:fe11edbda85c 3748 }
mbed_official 532:fe11edbda85c 3749 break;
mbed_official 532:fe11edbda85c 3750 default:
mbed_official 532:fe11edbda85c 3751 break;
mbed_official 532:fe11edbda85c 3752 }
mbed_official 532:fe11edbda85c 3753
mbed_official 87:085cde657901 3754 /* Disable the TIM Update DMA request */
mbed_official 87:085cde657901 3755 __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
mbed_official 87:085cde657901 3756
mbed_official 87:085cde657901 3757 /* Return function status */
mbed_official 87:085cde657901 3758 return HAL_OK;
mbed_official 87:085cde657901 3759 }
mbed_official 87:085cde657901 3760
mbed_official 87:085cde657901 3761 /**
mbed_official 87:085cde657901 3762 * @brief Generate a software event
mbed_official 226:b062af740e40 3763 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 3764 * the configuration information for TIM module.
mbed_official 87:085cde657901 3765 * @param EventSource: specifies the event source.
mbed_official 87:085cde657901 3766 * This parameter can be one of the following values:
mbed_official 532:fe11edbda85c 3767 * @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source
mbed_official 532:fe11edbda85c 3768 * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
mbed_official 532:fe11edbda85c 3769 * @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
mbed_official 532:fe11edbda85c 3770 * @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
mbed_official 532:fe11edbda85c 3771 * @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
mbed_official 532:fe11edbda85c 3772 * @arg TIM_EVENTSOURCE_COM: Timer COM event source
mbed_official 532:fe11edbda85c 3773 * @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
mbed_official 532:fe11edbda85c 3774 * @arg TIM_EVENTSOURCE_BREAK: Timer Break event source
mbed_official 87:085cde657901 3775 * @note TIM6 and TIM7 can only generate an update event.
mbed_official 532:fe11edbda85c 3776 * @note TIM_EVENTSOURCE_COM and TIM_EVENTSOURCE_BREAK are used only with TIM1 and TIM8.
mbed_official 87:085cde657901 3777 * @retval HAL status
mbed_official 87:085cde657901 3778 */
mbed_official 87:085cde657901 3779
mbed_official 87:085cde657901 3780 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
mbed_official 87:085cde657901 3781 {
mbed_official 87:085cde657901 3782 /* Check the parameters */
mbed_official 87:085cde657901 3783 assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official 87:085cde657901 3784 assert_param(IS_TIM_EVENT_SOURCE(EventSource));
mbed_official 87:085cde657901 3785
mbed_official 87:085cde657901 3786 /* Process Locked */
mbed_official 87:085cde657901 3787 __HAL_LOCK(htim);
mbed_official 87:085cde657901 3788
mbed_official 87:085cde657901 3789 /* Change the TIM state */
mbed_official 87:085cde657901 3790 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 87:085cde657901 3791
mbed_official 87:085cde657901 3792 /* Set the event sources */
mbed_official 87:085cde657901 3793 htim->Instance->EGR = EventSource;
mbed_official 87:085cde657901 3794
mbed_official 87:085cde657901 3795 /* Change the TIM state */
mbed_official 87:085cde657901 3796 htim->State = HAL_TIM_STATE_READY;
mbed_official 87:085cde657901 3797
mbed_official 87:085cde657901 3798 __HAL_UNLOCK(htim);
mbed_official 87:085cde657901 3799
mbed_official 87:085cde657901 3800 /* Return function status */
mbed_official 87:085cde657901 3801 return HAL_OK;
mbed_official 87:085cde657901 3802 }
mbed_official 87:085cde657901 3803
mbed_official 87:085cde657901 3804 /**
mbed_official 87:085cde657901 3805 * @brief Configures the OCRef clear feature
mbed_official 226:b062af740e40 3806 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 3807 * the configuration information for TIM module.
mbed_official 87:085cde657901 3808 * @param sClearInputConfig: pointer to a TIM_ClearInputConfigTypeDef structure that
mbed_official 87:085cde657901 3809 * contains the OCREF clear feature and parameters for the TIM peripheral.
mbed_official 226:b062af740e40 3810 * @param Channel: specifies the TIM Channel.
mbed_official 87:085cde657901 3811 * This parameter can be one of the following values:
mbed_official 226:b062af740e40 3812 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 226:b062af740e40 3813 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 226:b062af740e40 3814 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 226:b062af740e40 3815 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 87:085cde657901 3816 * @retval HAL status
mbed_official 87:085cde657901 3817 */
mbed_official 87:085cde657901 3818 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel)
mbed_official 87:085cde657901 3819 {
mbed_official 87:085cde657901 3820 /* Check the parameters */
mbed_official 87:085cde657901 3821 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
mbed_official 87:085cde657901 3822 assert_param(IS_TIM_CHANNELS(Channel));
mbed_official 87:085cde657901 3823 assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
mbed_official 87:085cde657901 3824 assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
mbed_official 87:085cde657901 3825 assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
mbed_official 87:085cde657901 3826 assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
mbed_official 87:085cde657901 3827
mbed_official 87:085cde657901 3828 /* Process Locked */
mbed_official 87:085cde657901 3829 __HAL_LOCK(htim);
mbed_official 87:085cde657901 3830
mbed_official 87:085cde657901 3831 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 87:085cde657901 3832
mbed_official 87:085cde657901 3833 if(sClearInputConfig->ClearInputSource == TIM_CLEARINPUTSOURCE_ETR)
mbed_official 87:085cde657901 3834 {
mbed_official 87:085cde657901 3835 TIM_ETR_SetConfig(htim->Instance,
mbed_official 87:085cde657901 3836 sClearInputConfig->ClearInputPrescaler,
mbed_official 87:085cde657901 3837 sClearInputConfig->ClearInputPolarity,
mbed_official 87:085cde657901 3838 sClearInputConfig->ClearInputFilter);
mbed_official 87:085cde657901 3839 }
mbed_official 87:085cde657901 3840
mbed_official 87:085cde657901 3841 switch (Channel)
mbed_official 87:085cde657901 3842 {
mbed_official 87:085cde657901 3843 case TIM_CHANNEL_1:
mbed_official 87:085cde657901 3844 {
mbed_official 87:085cde657901 3845 if(sClearInputConfig->ClearInputState != RESET)
mbed_official 87:085cde657901 3846 {
mbed_official 87:085cde657901 3847 /* Enable the Ocref clear feature for Channel 1 */
mbed_official 87:085cde657901 3848 htim->Instance->CCMR1 |= TIM_CCMR1_OC1CE;
mbed_official 87:085cde657901 3849 }
mbed_official 87:085cde657901 3850 else
mbed_official 87:085cde657901 3851 {
mbed_official 87:085cde657901 3852 /* Disable the Ocref clear feature for Channel 1 */
mbed_official 87:085cde657901 3853 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE;
mbed_official 87:085cde657901 3854 }
mbed_official 87:085cde657901 3855 }
mbed_official 87:085cde657901 3856 break;
mbed_official 87:085cde657901 3857 case TIM_CHANNEL_2:
mbed_official 87:085cde657901 3858 {
mbed_official 87:085cde657901 3859 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 87:085cde657901 3860 if(sClearInputConfig->ClearInputState != RESET)
mbed_official 87:085cde657901 3861 {
mbed_official 87:085cde657901 3862 /* Enable the Ocref clear feature for Channel 2 */
mbed_official 87:085cde657901 3863 htim->Instance->CCMR1 |= TIM_CCMR1_OC2CE;
mbed_official 87:085cde657901 3864 }
mbed_official 87:085cde657901 3865 else
mbed_official 87:085cde657901 3866 {
mbed_official 87:085cde657901 3867 /* Disable the Ocref clear feature for Channel 2 */
mbed_official 87:085cde657901 3868 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE;
mbed_official 87:085cde657901 3869 }
mbed_official 87:085cde657901 3870 }
mbed_official 87:085cde657901 3871 break;
mbed_official 87:085cde657901 3872 case TIM_CHANNEL_3:
mbed_official 87:085cde657901 3873 {
mbed_official 87:085cde657901 3874 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
mbed_official 87:085cde657901 3875 if(sClearInputConfig->ClearInputState != RESET)
mbed_official 87:085cde657901 3876 {
mbed_official 87:085cde657901 3877 /* Enable the Ocref clear feature for Channel 3 */
mbed_official 87:085cde657901 3878 htim->Instance->CCMR2 |= TIM_CCMR2_OC3CE;
mbed_official 87:085cde657901 3879 }
mbed_official 87:085cde657901 3880 else
mbed_official 87:085cde657901 3881 {
mbed_official 87:085cde657901 3882 /* Disable the Ocref clear feature for Channel 3 */
mbed_official 87:085cde657901 3883 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE;
mbed_official 87:085cde657901 3884 }
mbed_official 87:085cde657901 3885 }
mbed_official 87:085cde657901 3886 break;
mbed_official 87:085cde657901 3887 case TIM_CHANNEL_4:
mbed_official 87:085cde657901 3888 {
mbed_official 87:085cde657901 3889 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
mbed_official 87:085cde657901 3890 if(sClearInputConfig->ClearInputState != RESET)
mbed_official 87:085cde657901 3891 {
mbed_official 87:085cde657901 3892 /* Enable the Ocref clear feature for Channel 4 */
mbed_official 87:085cde657901 3893 htim->Instance->CCMR2 |= TIM_CCMR2_OC4CE;
mbed_official 87:085cde657901 3894 }
mbed_official 87:085cde657901 3895 else
mbed_official 87:085cde657901 3896 {
mbed_official 87:085cde657901 3897 /* Disable the Ocref clear feature for Channel 4 */
mbed_official 87:085cde657901 3898 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE;
mbed_official 87:085cde657901 3899 }
mbed_official 87:085cde657901 3900 }
mbed_official 87:085cde657901 3901 break;
mbed_official 87:085cde657901 3902 default:
mbed_official 87:085cde657901 3903 break;
mbed_official 87:085cde657901 3904 }
mbed_official 87:085cde657901 3905
mbed_official 87:085cde657901 3906 htim->State = HAL_TIM_STATE_READY;
mbed_official 87:085cde657901 3907
mbed_official 87:085cde657901 3908 __HAL_UNLOCK(htim);
mbed_official 87:085cde657901 3909
mbed_official 87:085cde657901 3910 return HAL_OK;
mbed_official 87:085cde657901 3911 }
mbed_official 87:085cde657901 3912
mbed_official 87:085cde657901 3913 /**
mbed_official 87:085cde657901 3914 * @brief Configures the clock source to be used
mbed_official 226:b062af740e40 3915 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 3916 * the configuration information for TIM module.
mbed_official 87:085cde657901 3917 * @param sClockSourceConfig: pointer to a TIM_ClockConfigTypeDef structure that
mbed_official 87:085cde657901 3918 * contains the clock source information for the TIM peripheral.
mbed_official 87:085cde657901 3919 * @retval HAL status
mbed_official 87:085cde657901 3920 */
mbed_official 87:085cde657901 3921 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig)
mbed_official 87:085cde657901 3922 {
mbed_official 87:085cde657901 3923 uint32_t tmpsmcr = 0;
mbed_official 87:085cde657901 3924
mbed_official 87:085cde657901 3925 /* Process Locked */
mbed_official 87:085cde657901 3926 __HAL_LOCK(htim);
mbed_official 87:085cde657901 3927
mbed_official 87:085cde657901 3928 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 87:085cde657901 3929
mbed_official 87:085cde657901 3930 /* Check the parameters */
mbed_official 87:085cde657901 3931 assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
mbed_official 87:085cde657901 3932 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
mbed_official 87:085cde657901 3933 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
mbed_official 87:085cde657901 3934 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
mbed_official 87:085cde657901 3935
mbed_official 87:085cde657901 3936 /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
mbed_official 87:085cde657901 3937 tmpsmcr = htim->Instance->SMCR;
mbed_official 87:085cde657901 3938 tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
mbed_official 87:085cde657901 3939 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
mbed_official 87:085cde657901 3940 htim->Instance->SMCR = tmpsmcr;
mbed_official 87:085cde657901 3941
mbed_official 87:085cde657901 3942 switch (sClockSourceConfig->ClockSource)
mbed_official 87:085cde657901 3943 {
mbed_official 87:085cde657901 3944 case TIM_CLOCKSOURCE_INTERNAL:
mbed_official 87:085cde657901 3945 {
mbed_official 87:085cde657901 3946 assert_param(IS_TIM_INSTANCE(htim->Instance));
mbed_official 87:085cde657901 3947 /* Disable slave mode to clock the prescaler directly with the internal clock */
mbed_official 87:085cde657901 3948 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
mbed_official 87:085cde657901 3949 }
mbed_official 87:085cde657901 3950 break;
mbed_official 87:085cde657901 3951
mbed_official 87:085cde657901 3952 case TIM_CLOCKSOURCE_ETRMODE1:
mbed_official 87:085cde657901 3953 {
mbed_official 87:085cde657901 3954 assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));
mbed_official 87:085cde657901 3955 /* Configure the ETR Clock source */
mbed_official 87:085cde657901 3956 TIM_ETR_SetConfig(htim->Instance,
mbed_official 87:085cde657901 3957 sClockSourceConfig->ClockPrescaler,
mbed_official 87:085cde657901 3958 sClockSourceConfig->ClockPolarity,
mbed_official 87:085cde657901 3959 sClockSourceConfig->ClockFilter);
mbed_official 87:085cde657901 3960 /* Get the TIMx SMCR register value */
mbed_official 87:085cde657901 3961 tmpsmcr = htim->Instance->SMCR;
mbed_official 87:085cde657901 3962 /* Reset the SMS and TS Bits */
mbed_official 87:085cde657901 3963 tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
mbed_official 87:085cde657901 3964 /* Select the External clock mode1 and the ETRF trigger */
mbed_official 87:085cde657901 3965 tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
mbed_official 87:085cde657901 3966 /* Write to TIMx SMCR */
mbed_official 87:085cde657901 3967 htim->Instance->SMCR = tmpsmcr;
mbed_official 87:085cde657901 3968 }
mbed_official 87:085cde657901 3969 break;
mbed_official 87:085cde657901 3970
mbed_official 87:085cde657901 3971 case TIM_CLOCKSOURCE_ETRMODE2:
mbed_official 87:085cde657901 3972 {
mbed_official 87:085cde657901 3973 assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));
mbed_official 87:085cde657901 3974 /* Configure the ETR Clock source */
mbed_official 87:085cde657901 3975 TIM_ETR_SetConfig(htim->Instance,
mbed_official 87:085cde657901 3976 sClockSourceConfig->ClockPrescaler,
mbed_official 87:085cde657901 3977 sClockSourceConfig->ClockPolarity,
mbed_official 87:085cde657901 3978 sClockSourceConfig->ClockFilter);
mbed_official 87:085cde657901 3979 /* Enable the External clock mode2 */
mbed_official 87:085cde657901 3980 htim->Instance->SMCR |= TIM_SMCR_ECE;
mbed_official 87:085cde657901 3981 }
mbed_official 87:085cde657901 3982 break;
mbed_official 87:085cde657901 3983
mbed_official 87:085cde657901 3984 case TIM_CLOCKSOURCE_TI1:
mbed_official 87:085cde657901 3985 {
mbed_official 87:085cde657901 3986 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
mbed_official 87:085cde657901 3987 TIM_TI1_ConfigInputStage(htim->Instance,
mbed_official 87:085cde657901 3988 sClockSourceConfig->ClockPolarity,
mbed_official 87:085cde657901 3989 sClockSourceConfig->ClockFilter);
mbed_official 87:085cde657901 3990 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
mbed_official 87:085cde657901 3991 }
mbed_official 87:085cde657901 3992 break;
mbed_official 87:085cde657901 3993 case TIM_CLOCKSOURCE_TI2:
mbed_official 87:085cde657901 3994 {
mbed_official 87:085cde657901 3995 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 87:085cde657901 3996 TIM_TI2_ConfigInputStage(htim->Instance,
mbed_official 87:085cde657901 3997 sClockSourceConfig->ClockPolarity,
mbed_official 87:085cde657901 3998 sClockSourceConfig->ClockFilter);
mbed_official 87:085cde657901 3999 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
mbed_official 87:085cde657901 4000 }
mbed_official 87:085cde657901 4001 break;
mbed_official 87:085cde657901 4002 case TIM_CLOCKSOURCE_TI1ED:
mbed_official 87:085cde657901 4003 {
mbed_official 87:085cde657901 4004 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
mbed_official 87:085cde657901 4005 TIM_TI1_ConfigInputStage(htim->Instance,
mbed_official 87:085cde657901 4006 sClockSourceConfig->ClockPolarity,
mbed_official 87:085cde657901 4007 sClockSourceConfig->ClockFilter);
mbed_official 87:085cde657901 4008 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
mbed_official 87:085cde657901 4009 }
mbed_official 87:085cde657901 4010 break;
mbed_official 87:085cde657901 4011 case TIM_CLOCKSOURCE_ITR0:
mbed_official 87:085cde657901 4012 {
mbed_official 87:085cde657901 4013 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 87:085cde657901 4014 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR0);
mbed_official 87:085cde657901 4015 }
mbed_official 87:085cde657901 4016 break;
mbed_official 87:085cde657901 4017 case TIM_CLOCKSOURCE_ITR1:
mbed_official 87:085cde657901 4018 {
mbed_official 87:085cde657901 4019 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 87:085cde657901 4020 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR1);
mbed_official 87:085cde657901 4021 }
mbed_official 87:085cde657901 4022 break;
mbed_official 87:085cde657901 4023 case TIM_CLOCKSOURCE_ITR2:
mbed_official 87:085cde657901 4024 {
mbed_official 87:085cde657901 4025 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 87:085cde657901 4026 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR2);
mbed_official 87:085cde657901 4027 }
mbed_official 87:085cde657901 4028 break;
mbed_official 87:085cde657901 4029 case TIM_CLOCKSOURCE_ITR3:
mbed_official 87:085cde657901 4030 {
mbed_official 87:085cde657901 4031 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 87:085cde657901 4032 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR3);
mbed_official 87:085cde657901 4033 }
mbed_official 87:085cde657901 4034 break;
mbed_official 87:085cde657901 4035
mbed_official 87:085cde657901 4036 default:
mbed_official 87:085cde657901 4037 break;
mbed_official 87:085cde657901 4038 }
mbed_official 87:085cde657901 4039 htim->State = HAL_TIM_STATE_READY;
mbed_official 87:085cde657901 4040
mbed_official 87:085cde657901 4041 __HAL_UNLOCK(htim);
mbed_official 87:085cde657901 4042
mbed_official 87:085cde657901 4043 return HAL_OK;
mbed_official 87:085cde657901 4044 }
mbed_official 87:085cde657901 4045
mbed_official 87:085cde657901 4046 /**
mbed_official 87:085cde657901 4047 * @brief Selects the signal connected to the TI1 input: direct from CH1_input
mbed_official 87:085cde657901 4048 * or a XOR combination between CH1_input, CH2_input & CH3_input
mbed_official 226:b062af740e40 4049 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 532:fe11edbda85c 4050 * the configuration information for TIM module.
mbed_official 87:085cde657901 4051 * @param TI1_Selection: Indicate whether or not channel 1 is connected to the
mbed_official 87:085cde657901 4052 * output of a XOR gate.
mbed_official 87:085cde657901 4053 * This parameter can be one of the following values:
mbed_official 87:085cde657901 4054 * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
mbed_official 87:085cde657901 4055 * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
mbed_official 87:085cde657901 4056 * pins are connected to the TI1 input (XOR combination)
mbed_official 87:085cde657901 4057 * @retval HAL status
mbed_official 87:085cde657901 4058 */
mbed_official 87:085cde657901 4059 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
mbed_official 87:085cde657901 4060 {
mbed_official 87:085cde657901 4061 uint32_t tmpcr2 = 0;
mbed_official 87:085cde657901 4062
mbed_official 87:085cde657901 4063 /* Check the parameters */
mbed_official 87:085cde657901 4064 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
mbed_official 87:085cde657901 4065 assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
mbed_official 87:085cde657901 4066
mbed_official 87:085cde657901 4067 /* Get the TIMx CR2 register value */
mbed_official 87:085cde657901 4068 tmpcr2 = htim->Instance->CR2;
mbed_official 87:085cde657901 4069
mbed_official 87:085cde657901 4070 /* Reset the TI1 selection */
mbed_official 87:085cde657901 4071 tmpcr2 &= ~TIM_CR2_TI1S;
mbed_official 87:085cde657901 4072
mbed_official 532:fe11edbda85c 4073 /* Set the TI1 selection */
mbed_official 87:085cde657901 4074 tmpcr2 |= TI1_Selection;
mbed_official 87:085cde657901 4075
mbed_official 87:085cde657901 4076 /* Write to TIMxCR2 */
mbed_official 87:085cde657901 4077 htim->Instance->CR2 = tmpcr2;
mbed_official 87:085cde657901 4078
mbed_official 87:085cde657901 4079 return HAL_OK;
mbed_official 87:085cde657901 4080 }
mbed_official 87:085cde657901 4081
mbed_official 87:085cde657901 4082 /**
mbed_official 87:085cde657901 4083 * @brief Configures the TIM in Slave mode
mbed_official 226:b062af740e40 4084 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 532:fe11edbda85c 4085 * the configuration information for TIM module.
mbed_official 87:085cde657901 4086 * @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
mbed_official 87:085cde657901 4087 * contains the selected trigger (internal trigger input, filtered
mbed_official 87:085cde657901 4088 * timer input or external trigger input) and the ) and the Slave
mbed_official 87:085cde657901 4089 * mode (Disable, Reset, Gated, Trigger, External clock mode 1).
mbed_official 87:085cde657901 4090 * @retval HAL status
mbed_official 87:085cde657901 4091 */
mbed_official 87:085cde657901 4092 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig)
mbed_official 87:085cde657901 4093 {
mbed_official 87:085cde657901 4094 /* Check the parameters */
mbed_official 87:085cde657901 4095 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
mbed_official 87:085cde657901 4096 assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
mbed_official 87:085cde657901 4097 assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
mbed_official 87:085cde657901 4098
mbed_official 87:085cde657901 4099 __HAL_LOCK(htim);
mbed_official 87:085cde657901 4100
mbed_official 87:085cde657901 4101 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 87:085cde657901 4102
mbed_official 532:fe11edbda85c 4103 TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
mbed_official 532:fe11edbda85c 4104
mbed_official 532:fe11edbda85c 4105 /* Disable Trigger Interrupt */
mbed_official 532:fe11edbda85c 4106 __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
mbed_official 532:fe11edbda85c 4107
mbed_official 532:fe11edbda85c 4108 /* Disable Trigger DMA request */
mbed_official 532:fe11edbda85c 4109 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
mbed_official 532:fe11edbda85c 4110
mbed_official 532:fe11edbda85c 4111 htim->State = HAL_TIM_STATE_READY;
mbed_official 532:fe11edbda85c 4112
mbed_official 532:fe11edbda85c 4113 __HAL_UNLOCK(htim);
mbed_official 532:fe11edbda85c 4114
mbed_official 532:fe11edbda85c 4115 return HAL_OK;
mbed_official 532:fe11edbda85c 4116 }
mbed_official 532:fe11edbda85c 4117
mbed_official 532:fe11edbda85c 4118 /**
mbed_official 532:fe11edbda85c 4119 * @brief Configures the TIM in Slave mode in interrupt mode
mbed_official 532:fe11edbda85c 4120 * @param htim: TIM handle.
mbed_official 532:fe11edbda85c 4121 * @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
mbed_official 532:fe11edbda85c 4122 * contains the selected trigger (internal trigger input, filtered
mbed_official 532:fe11edbda85c 4123 * timer input or external trigger input) and the ) and the Slave
mbed_official 532:fe11edbda85c 4124 * mode (Disable, Reset, Gated, Trigger, External clock mode 1).
mbed_official 532:fe11edbda85c 4125 * @retval HAL status
mbed_official 532:fe11edbda85c 4126 */
mbed_official 532:fe11edbda85c 4127 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim,
mbed_official 532:fe11edbda85c 4128 TIM_SlaveConfigTypeDef * sSlaveConfig)
mbed_official 532:fe11edbda85c 4129 {
mbed_official 532:fe11edbda85c 4130 /* Check the parameters */
mbed_official 532:fe11edbda85c 4131 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
mbed_official 532:fe11edbda85c 4132 assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
mbed_official 532:fe11edbda85c 4133 assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
mbed_official 532:fe11edbda85c 4134
mbed_official 532:fe11edbda85c 4135 __HAL_LOCK(htim);
mbed_official 532:fe11edbda85c 4136
mbed_official 532:fe11edbda85c 4137 htim->State = HAL_TIM_STATE_BUSY;
mbed_official 532:fe11edbda85c 4138
mbed_official 532:fe11edbda85c 4139 TIM_SlaveTimer_SetConfig(htim, sSlaveConfig);
mbed_official 532:fe11edbda85c 4140
mbed_official 532:fe11edbda85c 4141 /* Enable Trigger Interrupt */
mbed_official 532:fe11edbda85c 4142 __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
mbed_official 532:fe11edbda85c 4143
mbed_official 532:fe11edbda85c 4144 /* Disable Trigger DMA request */
mbed_official 532:fe11edbda85c 4145 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
mbed_official 532:fe11edbda85c 4146
mbed_official 532:fe11edbda85c 4147 htim->State = HAL_TIM_STATE_READY;
mbed_official 532:fe11edbda85c 4148
mbed_official 532:fe11edbda85c 4149 __HAL_UNLOCK(htim);
mbed_official 532:fe11edbda85c 4150
mbed_official 532:fe11edbda85c 4151 return HAL_OK;
mbed_official 532:fe11edbda85c 4152 }
mbed_official 532:fe11edbda85c 4153
mbed_official 532:fe11edbda85c 4154 /**
mbed_official 532:fe11edbda85c 4155 * @brief Read the captured value from Capture Compare unit
mbed_official 532:fe11edbda85c 4156 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 532:fe11edbda85c 4157 * the configuration information for TIM module.
mbed_official 532:fe11edbda85c 4158 * @param Channel: TIM Channels to be enabled.
mbed_official 532:fe11edbda85c 4159 * This parameter can be one of the following values:
mbed_official 532:fe11edbda85c 4160 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official 532:fe11edbda85c 4161 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official 532:fe11edbda85c 4162 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official 532:fe11edbda85c 4163 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official 532:fe11edbda85c 4164 * @retval Captured value
mbed_official 532:fe11edbda85c 4165 */
mbed_official 532:fe11edbda85c 4166 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
mbed_official 532:fe11edbda85c 4167 {
mbed_official 532:fe11edbda85c 4168 uint32_t tmpreg = 0;
mbed_official 532:fe11edbda85c 4169
mbed_official 532:fe11edbda85c 4170 __HAL_LOCK(htim);
mbed_official 532:fe11edbda85c 4171
mbed_official 532:fe11edbda85c 4172 switch (Channel)
mbed_official 532:fe11edbda85c 4173 {
mbed_official 532:fe11edbda85c 4174 case TIM_CHANNEL_1:
mbed_official 532:fe11edbda85c 4175 {
mbed_official 532:fe11edbda85c 4176 /* Check the parameters */
mbed_official 532:fe11edbda85c 4177 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
mbed_official 532:fe11edbda85c 4178
mbed_official 532:fe11edbda85c 4179 /* Return the capture 1 value */
mbed_official 532:fe11edbda85c 4180 tmpreg = htim->Instance->CCR1;
mbed_official 532:fe11edbda85c 4181
mbed_official 532:fe11edbda85c 4182 break;
mbed_official 532:fe11edbda85c 4183 }
mbed_official 532:fe11edbda85c 4184 case TIM_CHANNEL_2:
mbed_official 532:fe11edbda85c 4185 {
mbed_official 532:fe11edbda85c 4186 /* Check the parameters */
mbed_official 532:fe11edbda85c 4187 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 532:fe11edbda85c 4188
mbed_official 532:fe11edbda85c 4189 /* Return the capture 2 value */
mbed_official 532:fe11edbda85c 4190 tmpreg = htim->Instance->CCR2;
mbed_official 532:fe11edbda85c 4191
mbed_official 532:fe11edbda85c 4192 break;
mbed_official 532:fe11edbda85c 4193 }
mbed_official 532:fe11edbda85c 4194
mbed_official 532:fe11edbda85c 4195 case TIM_CHANNEL_3:
mbed_official 532:fe11edbda85c 4196 {
mbed_official 532:fe11edbda85c 4197 /* Check the parameters */
mbed_official 532:fe11edbda85c 4198 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
mbed_official 532:fe11edbda85c 4199
mbed_official 532:fe11edbda85c 4200 /* Return the capture 3 value */
mbed_official 532:fe11edbda85c 4201 tmpreg = htim->Instance->CCR3;
mbed_official 532:fe11edbda85c 4202
mbed_official 532:fe11edbda85c 4203 break;
mbed_official 532:fe11edbda85c 4204 }
mbed_official 532:fe11edbda85c 4205
mbed_official 532:fe11edbda85c 4206 case TIM_CHANNEL_4:
mbed_official 532:fe11edbda85c 4207 {
mbed_official 532:fe11edbda85c 4208 /* Check the parameters */
mbed_official 532:fe11edbda85c 4209 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
mbed_official 532:fe11edbda85c 4210
mbed_official 532:fe11edbda85c 4211 /* Return the capture 4 value */
mbed_official 532:fe11edbda85c 4212 tmpreg = htim->Instance->CCR4;
mbed_official 532:fe11edbda85c 4213
mbed_official 532:fe11edbda85c 4214 break;
mbed_official 532:fe11edbda85c 4215 }
mbed_official 532:fe11edbda85c 4216
mbed_official 532:fe11edbda85c 4217 default:
mbed_official 532:fe11edbda85c 4218 break;
mbed_official 532:fe11edbda85c 4219 }
mbed_official 532:fe11edbda85c 4220
mbed_official 532:fe11edbda85c 4221 __HAL_UNLOCK(htim);
mbed_official 532:fe11edbda85c 4222 return tmpreg;
mbed_official 532:fe11edbda85c 4223 }
mbed_official 532:fe11edbda85c 4224 /**
mbed_official 532:fe11edbda85c 4225 * @}
mbed_official 532:fe11edbda85c 4226 */
mbed_official 532:fe11edbda85c 4227
mbed_official 532:fe11edbda85c 4228 /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
mbed_official 532:fe11edbda85c 4229 * @brief TIM Callbacks functions
mbed_official 532:fe11edbda85c 4230 *
mbed_official 532:fe11edbda85c 4231 @verbatim
mbed_official 532:fe11edbda85c 4232 ==============================================================================
mbed_official 532:fe11edbda85c 4233 ##### TIM Callbacks functions #####
mbed_official 532:fe11edbda85c 4234 ==============================================================================
mbed_official 532:fe11edbda85c 4235 [..]
mbed_official 532:fe11edbda85c 4236 This section provides TIM callback functions:
mbed_official 532:fe11edbda85c 4237 (+) Timer Period elapsed callback
mbed_official 532:fe11edbda85c 4238 (+) Timer Output Compare callback
mbed_official 532:fe11edbda85c 4239 (+) Timer Input capture callback
mbed_official 532:fe11edbda85c 4240 (+) Timer Trigger callback
mbed_official 532:fe11edbda85c 4241 (+) Timer Error callback
mbed_official 532:fe11edbda85c 4242
mbed_official 532:fe11edbda85c 4243 @endverbatim
mbed_official 532:fe11edbda85c 4244 * @{
mbed_official 532:fe11edbda85c 4245 */
mbed_official 532:fe11edbda85c 4246
mbed_official 532:fe11edbda85c 4247 /**
mbed_official 532:fe11edbda85c 4248 * @brief Period elapsed callback in non blocking mode
mbed_official 532:fe11edbda85c 4249 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 532:fe11edbda85c 4250 * the configuration information for TIM module.
mbed_official 532:fe11edbda85c 4251 * @retval None
mbed_official 532:fe11edbda85c 4252 */
mbed_official 532:fe11edbda85c 4253 __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
mbed_official 532:fe11edbda85c 4254 {
mbed_official 532:fe11edbda85c 4255 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 532:fe11edbda85c 4256 the __HAL_TIM_PeriodElapsedCallback could be implemented in the user file
mbed_official 532:fe11edbda85c 4257 */
mbed_official 532:fe11edbda85c 4258
mbed_official 532:fe11edbda85c 4259 }
mbed_official 532:fe11edbda85c 4260 /**
mbed_official 532:fe11edbda85c 4261 * @brief Output Compare callback in non blocking mode
mbed_official 532:fe11edbda85c 4262 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 532:fe11edbda85c 4263 * the configuration information for TIM module.
mbed_official 532:fe11edbda85c 4264 * @retval None
mbed_official 532:fe11edbda85c 4265 */
mbed_official 532:fe11edbda85c 4266 __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
mbed_official 532:fe11edbda85c 4267 {
mbed_official 532:fe11edbda85c 4268 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 532:fe11edbda85c 4269 the __HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
mbed_official 532:fe11edbda85c 4270 */
mbed_official 532:fe11edbda85c 4271 }
mbed_official 532:fe11edbda85c 4272 /**
mbed_official 532:fe11edbda85c 4273 * @brief Input Capture callback in non blocking mode
mbed_official 532:fe11edbda85c 4274 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 532:fe11edbda85c 4275 * the configuration information for TIM module.
mbed_official 532:fe11edbda85c 4276 * @retval None
mbed_official 532:fe11edbda85c 4277 */
mbed_official 532:fe11edbda85c 4278 __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
mbed_official 532:fe11edbda85c 4279 {
mbed_official 532:fe11edbda85c 4280 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 532:fe11edbda85c 4281 the __HAL_TIM_IC_CaptureCallback could be implemented in the user file
mbed_official 532:fe11edbda85c 4282 */
mbed_official 532:fe11edbda85c 4283 }
mbed_official 532:fe11edbda85c 4284
mbed_official 532:fe11edbda85c 4285 /**
mbed_official 532:fe11edbda85c 4286 * @brief PWM Pulse finished callback in non blocking mode
mbed_official 532:fe11edbda85c 4287 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 532:fe11edbda85c 4288 * the configuration information for TIM module.
mbed_official 532:fe11edbda85c 4289 * @retval None
mbed_official 532:fe11edbda85c 4290 */
mbed_official 532:fe11edbda85c 4291 __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
mbed_official 532:fe11edbda85c 4292 {
mbed_official 532:fe11edbda85c 4293 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 532:fe11edbda85c 4294 the __HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
mbed_official 532:fe11edbda85c 4295 */
mbed_official 532:fe11edbda85c 4296 }
mbed_official 532:fe11edbda85c 4297
mbed_official 532:fe11edbda85c 4298 /**
mbed_official 532:fe11edbda85c 4299 * @brief Hall Trigger detection callback in non blocking mode
mbed_official 532:fe11edbda85c 4300 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 532:fe11edbda85c 4301 * the configuration information for TIM module.
mbed_official 532:fe11edbda85c 4302 * @retval None
mbed_official 532:fe11edbda85c 4303 */
mbed_official 532:fe11edbda85c 4304 __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
mbed_official 532:fe11edbda85c 4305 {
mbed_official 532:fe11edbda85c 4306 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 532:fe11edbda85c 4307 the HAL_TIM_TriggerCallback could be implemented in the user file
mbed_official 532:fe11edbda85c 4308 */
mbed_official 532:fe11edbda85c 4309 }
mbed_official 532:fe11edbda85c 4310
mbed_official 532:fe11edbda85c 4311 /**
mbed_official 532:fe11edbda85c 4312 * @brief Timer error callback in non blocking mode
mbed_official 532:fe11edbda85c 4313 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 532:fe11edbda85c 4314 * the configuration information for TIM module.
mbed_official 532:fe11edbda85c 4315 * @retval None
mbed_official 532:fe11edbda85c 4316 */
mbed_official 532:fe11edbda85c 4317 __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
mbed_official 532:fe11edbda85c 4318 {
mbed_official 532:fe11edbda85c 4319 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 532:fe11edbda85c 4320 the HAL_TIM_ErrorCallback could be implemented in the user file
mbed_official 532:fe11edbda85c 4321 */
mbed_official 532:fe11edbda85c 4322 }
mbed_official 532:fe11edbda85c 4323 /**
mbed_official 532:fe11edbda85c 4324 * @}
mbed_official 532:fe11edbda85c 4325 */
mbed_official 532:fe11edbda85c 4326
mbed_official 532:fe11edbda85c 4327 /** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions
mbed_official 532:fe11edbda85c 4328 * @brief Peripheral State functions
mbed_official 532:fe11edbda85c 4329 *
mbed_official 532:fe11edbda85c 4330 @verbatim
mbed_official 532:fe11edbda85c 4331 ==============================================================================
mbed_official 532:fe11edbda85c 4332 ##### Peripheral State functions #####
mbed_official 532:fe11edbda85c 4333 ==============================================================================
mbed_official 532:fe11edbda85c 4334 [..]
mbed_official 532:fe11edbda85c 4335 This subsection permits to get in run-time the status of the peripheral
mbed_official 532:fe11edbda85c 4336 and the data flow.
mbed_official 532:fe11edbda85c 4337
mbed_official 532:fe11edbda85c 4338 @endverbatim
mbed_official 532:fe11edbda85c 4339 * @{
mbed_official 532:fe11edbda85c 4340 */
mbed_official 532:fe11edbda85c 4341
mbed_official 532:fe11edbda85c 4342 /**
mbed_official 532:fe11edbda85c 4343 * @brief Return the TIM Base state
mbed_official 532:fe11edbda85c 4344 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 532:fe11edbda85c 4345 * the configuration information for TIM module.
mbed_official 532:fe11edbda85c 4346 * @retval HAL state
mbed_official 532:fe11edbda85c 4347 */
mbed_official 532:fe11edbda85c 4348 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
mbed_official 532:fe11edbda85c 4349 {
mbed_official 532:fe11edbda85c 4350 return htim->State;
mbed_official 532:fe11edbda85c 4351 }
mbed_official 532:fe11edbda85c 4352
mbed_official 532:fe11edbda85c 4353 /**
mbed_official 532:fe11edbda85c 4354 * @brief Return the TIM OC state
mbed_official 532:fe11edbda85c 4355 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 532:fe11edbda85c 4356 * the configuration information for TIM module.
mbed_official 532:fe11edbda85c 4357 * @retval HAL state
mbed_official 532:fe11edbda85c 4358 */
mbed_official 532:fe11edbda85c 4359 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
mbed_official 532:fe11edbda85c 4360 {
mbed_official 532:fe11edbda85c 4361 return htim->State;
mbed_official 532:fe11edbda85c 4362 }
mbed_official 532:fe11edbda85c 4363
mbed_official 532:fe11edbda85c 4364 /**
mbed_official 532:fe11edbda85c 4365 * @brief Return the TIM PWM state
mbed_official 532:fe11edbda85c 4366 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 532:fe11edbda85c 4367 * the configuration information for TIM module.
mbed_official 532:fe11edbda85c 4368 * @retval HAL state
mbed_official 532:fe11edbda85c 4369 */
mbed_official 532:fe11edbda85c 4370 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
mbed_official 532:fe11edbda85c 4371 {
mbed_official 532:fe11edbda85c 4372 return htim->State;
mbed_official 532:fe11edbda85c 4373 }
mbed_official 532:fe11edbda85c 4374
mbed_official 532:fe11edbda85c 4375 /**
mbed_official 532:fe11edbda85c 4376 * @brief Return the TIM Input Capture state
mbed_official 532:fe11edbda85c 4377 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 532:fe11edbda85c 4378 * the configuration information for TIM module.
mbed_official 532:fe11edbda85c 4379 * @retval HAL state
mbed_official 532:fe11edbda85c 4380 */
mbed_official 532:fe11edbda85c 4381 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
mbed_official 532:fe11edbda85c 4382 {
mbed_official 532:fe11edbda85c 4383 return htim->State;
mbed_official 532:fe11edbda85c 4384 }
mbed_official 532:fe11edbda85c 4385
mbed_official 532:fe11edbda85c 4386 /**
mbed_official 532:fe11edbda85c 4387 * @brief Return the TIM One Pulse Mode state
mbed_official 532:fe11edbda85c 4388 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 532:fe11edbda85c 4389 * the configuration information for TIM module.
mbed_official 532:fe11edbda85c 4390 * @retval HAL state
mbed_official 532:fe11edbda85c 4391 */
mbed_official 532:fe11edbda85c 4392 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
mbed_official 532:fe11edbda85c 4393 {
mbed_official 532:fe11edbda85c 4394 return htim->State;
mbed_official 532:fe11edbda85c 4395 }
mbed_official 532:fe11edbda85c 4396
mbed_official 532:fe11edbda85c 4397 /**
mbed_official 532:fe11edbda85c 4398 * @brief Return the TIM Encoder Mode state
mbed_official 532:fe11edbda85c 4399 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 532:fe11edbda85c 4400 * the configuration information for TIM module.
mbed_official 532:fe11edbda85c 4401 * @retval HAL state
mbed_official 532:fe11edbda85c 4402 */
mbed_official 532:fe11edbda85c 4403 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
mbed_official 532:fe11edbda85c 4404 {
mbed_official 532:fe11edbda85c 4405 return htim->State;
mbed_official 532:fe11edbda85c 4406 }
mbed_official 532:fe11edbda85c 4407 /**
mbed_official 532:fe11edbda85c 4408 * @}
mbed_official 532:fe11edbda85c 4409 */
mbed_official 532:fe11edbda85c 4410
mbed_official 532:fe11edbda85c 4411 /**
mbed_official 532:fe11edbda85c 4412 * @brief Time Base configuration
mbed_official 532:fe11edbda85c 4413 * @param TIMx: TIM peripheral
mbed_official 532:fe11edbda85c 4414 * @param Structure: pointer on TIM Time Base required parameters
mbed_official 532:fe11edbda85c 4415 * @retval None
mbed_official 532:fe11edbda85c 4416 */
mbed_official 532:fe11edbda85c 4417 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
mbed_official 532:fe11edbda85c 4418 {
mbed_official 532:fe11edbda85c 4419 uint32_t tmpcr1 = 0;
mbed_official 532:fe11edbda85c 4420 tmpcr1 = TIMx->CR1;
mbed_official 532:fe11edbda85c 4421
mbed_official 532:fe11edbda85c 4422 /* Set TIM Time Base Unit parameters ---------------------------------------*/
mbed_official 532:fe11edbda85c 4423 if(IS_TIM_CC3_INSTANCE(TIMx) != RESET)
mbed_official 532:fe11edbda85c 4424 {
mbed_official 532:fe11edbda85c 4425 /* Select the Counter Mode */
mbed_official 532:fe11edbda85c 4426 tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
mbed_official 532:fe11edbda85c 4427 tmpcr1 |= Structure->CounterMode;
mbed_official 532:fe11edbda85c 4428 }
mbed_official 532:fe11edbda85c 4429
mbed_official 532:fe11edbda85c 4430 if(IS_TIM_CC1_INSTANCE(TIMx) != RESET)
mbed_official 532:fe11edbda85c 4431 {
mbed_official 532:fe11edbda85c 4432 /* Set the clock division */
mbed_official 532:fe11edbda85c 4433 tmpcr1 &= ~TIM_CR1_CKD;
mbed_official 532:fe11edbda85c 4434 tmpcr1 |= (uint32_t)Structure->ClockDivision;
mbed_official 532:fe11edbda85c 4435 }
mbed_official 532:fe11edbda85c 4436
mbed_official 532:fe11edbda85c 4437 TIMx->CR1 = tmpcr1;
mbed_official 532:fe11edbda85c 4438
mbed_official 532:fe11edbda85c 4439 /* Set the Auto-reload value */
mbed_official 532:fe11edbda85c 4440 TIMx->ARR = (uint32_t)Structure->Period ;
mbed_official 532:fe11edbda85c 4441
mbed_official 532:fe11edbda85c 4442 /* Set the Prescaler value */
mbed_official 532:fe11edbda85c 4443 TIMx->PSC = (uint32_t)Structure->Prescaler;
mbed_official 532:fe11edbda85c 4444
mbed_official 532:fe11edbda85c 4445 if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
mbed_official 532:fe11edbda85c 4446 {
mbed_official 532:fe11edbda85c 4447 /* Set the Repetition Counter value */
mbed_official 532:fe11edbda85c 4448 TIMx->RCR = Structure->RepetitionCounter;
mbed_official 532:fe11edbda85c 4449 }
mbed_official 532:fe11edbda85c 4450
mbed_official 532:fe11edbda85c 4451 /* Generate an update event to reload the Prescaler
mbed_official 532:fe11edbda85c 4452 and the repetition counter(only for TIM1 and TIM8) value immediately */
mbed_official 532:fe11edbda85c 4453 TIMx->EGR = TIM_EGR_UG;
mbed_official 532:fe11edbda85c 4454 }
mbed_official 532:fe11edbda85c 4455
mbed_official 532:fe11edbda85c 4456 /**
mbed_official 532:fe11edbda85c 4457 * @brief Configure the TI1 as Input.
mbed_official 532:fe11edbda85c 4458 * @param TIMx to select the TIM peripheral.
mbed_official 532:fe11edbda85c 4459 * @param TIM_ICPolarity : The Input Polarity.
mbed_official 532:fe11edbda85c 4460 * This parameter can be one of the following values:
mbed_official 532:fe11edbda85c 4461 * @arg TIM_ICPolarity_Rising
mbed_official 532:fe11edbda85c 4462 * @arg TIM_ICPolarity_Falling
mbed_official 532:fe11edbda85c 4463 * @arg TIM_ICPolarity_BothEdge
mbed_official 532:fe11edbda85c 4464 * @param TIM_ICSelection: specifies the input to be used.
mbed_official 532:fe11edbda85c 4465 * This parameter can be one of the following values:
mbed_official 532:fe11edbda85c 4466 * @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.
mbed_official 532:fe11edbda85c 4467 * @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.
mbed_official 532:fe11edbda85c 4468 * @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.
mbed_official 532:fe11edbda85c 4469 * @param TIM_ICFilter: Specifies the Input Capture Filter.
mbed_official 532:fe11edbda85c 4470 * This parameter must be a value between 0x00 and 0x0F.
mbed_official 532:fe11edbda85c 4471 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
mbed_official 532:fe11edbda85c 4472 * (on channel2 path) is used as the input signal. Therefore CCMR1 must be
mbed_official 532:fe11edbda85c 4473 * protected against un-initialized filter and polarity values.
mbed_official 532:fe11edbda85c 4474 * @retval None
mbed_official 532:fe11edbda85c 4475 */
mbed_official 532:fe11edbda85c 4476 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
mbed_official 532:fe11edbda85c 4477 uint32_t TIM_ICFilter)
mbed_official 532:fe11edbda85c 4478 {
mbed_official 532:fe11edbda85c 4479 uint32_t tmpccmr1 = 0;
mbed_official 532:fe11edbda85c 4480 uint32_t tmpccer = 0;
mbed_official 532:fe11edbda85c 4481
mbed_official 532:fe11edbda85c 4482 /* Disable the Channel 1: Reset the CC1E Bit */
mbed_official 532:fe11edbda85c 4483 TIMx->CCER &= ~TIM_CCER_CC1E;
mbed_official 532:fe11edbda85c 4484 tmpccmr1 = TIMx->CCMR1;
mbed_official 532:fe11edbda85c 4485 tmpccer = TIMx->CCER;
mbed_official 532:fe11edbda85c 4486
mbed_official 532:fe11edbda85c 4487 /* Select the Input */
mbed_official 532:fe11edbda85c 4488 if(IS_TIM_CC2_INSTANCE(TIMx) != RESET)
mbed_official 532:fe11edbda85c 4489 {
mbed_official 532:fe11edbda85c 4490 tmpccmr1 &= ~TIM_CCMR1_CC1S;
mbed_official 532:fe11edbda85c 4491 tmpccmr1 |= TIM_ICSelection;
mbed_official 532:fe11edbda85c 4492 }
mbed_official 532:fe11edbda85c 4493 else
mbed_official 532:fe11edbda85c 4494 {
mbed_official 532:fe11edbda85c 4495 tmpccmr1 &= ~TIM_CCMR1_CC1S;
mbed_official 532:fe11edbda85c 4496 tmpccmr1 |= TIM_CCMR1_CC1S_0;
mbed_official 532:fe11edbda85c 4497 }
mbed_official 532:fe11edbda85c 4498
mbed_official 532:fe11edbda85c 4499 /* Set the filter */
mbed_official 532:fe11edbda85c 4500 tmpccmr1 &= ~TIM_CCMR1_IC1F;
mbed_official 532:fe11edbda85c 4501 tmpccmr1 |= ((TIM_ICFilter << 4) & TIM_CCMR1_IC1F);
mbed_official 532:fe11edbda85c 4502
mbed_official 532:fe11edbda85c 4503 /* Select the Polarity and set the CC1E Bit */
mbed_official 532:fe11edbda85c 4504 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
mbed_official 532:fe11edbda85c 4505 tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));
mbed_official 532:fe11edbda85c 4506
mbed_official 532:fe11edbda85c 4507 /* Write to TIMx CCMR1 and CCER registers */
mbed_official 532:fe11edbda85c 4508 TIMx->CCMR1 = tmpccmr1;
mbed_official 532:fe11edbda85c 4509 TIMx->CCER = tmpccer;
mbed_official 532:fe11edbda85c 4510 }
mbed_official 532:fe11edbda85c 4511
mbed_official 532:fe11edbda85c 4512 /**
mbed_official 532:fe11edbda85c 4513 * @brief Time Output Compare 2 configuration
mbed_official 532:fe11edbda85c 4514 * @param TIMx to select the TIM peripheral
mbed_official 532:fe11edbda85c 4515 * @param OC_Config: The output configuration structure
mbed_official 532:fe11edbda85c 4516 * @retval None
mbed_official 532:fe11edbda85c 4517 */
mbed_official 532:fe11edbda85c 4518 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
mbed_official 532:fe11edbda85c 4519 {
mbed_official 532:fe11edbda85c 4520 uint32_t tmpccmrx = 0;
mbed_official 532:fe11edbda85c 4521 uint32_t tmpccer = 0;
mbed_official 532:fe11edbda85c 4522 uint32_t tmpcr2 = 0;
mbed_official 532:fe11edbda85c 4523
mbed_official 532:fe11edbda85c 4524 /* Disable the Channel 2: Reset the CC2E Bit */
mbed_official 532:fe11edbda85c 4525 TIMx->CCER &= ~TIM_CCER_CC2E;
mbed_official 532:fe11edbda85c 4526
mbed_official 532:fe11edbda85c 4527 /* Get the TIMx CCER register value */
mbed_official 532:fe11edbda85c 4528 tmpccer = TIMx->CCER;
mbed_official 532:fe11edbda85c 4529 /* Get the TIMx CR2 register value */
mbed_official 532:fe11edbda85c 4530 tmpcr2 = TIMx->CR2;
mbed_official 532:fe11edbda85c 4531
mbed_official 532:fe11edbda85c 4532 /* Get the TIMx CCMR1 register value */
mbed_official 532:fe11edbda85c 4533 tmpccmrx = TIMx->CCMR1;
mbed_official 532:fe11edbda85c 4534
mbed_official 532:fe11edbda85c 4535 /* Reset the Output Compare mode and Capture/Compare selection Bits */
mbed_official 532:fe11edbda85c 4536 tmpccmrx &= ~TIM_CCMR1_OC2M;
mbed_official 532:fe11edbda85c 4537 tmpccmrx &= ~TIM_CCMR1_CC2S;
mbed_official 532:fe11edbda85c 4538
mbed_official 532:fe11edbda85c 4539 /* Select the Output Compare Mode */
mbed_official 532:fe11edbda85c 4540 tmpccmrx |= (OC_Config->OCMode << 8);
mbed_official 532:fe11edbda85c 4541
mbed_official 532:fe11edbda85c 4542 /* Reset the Output Polarity level */
mbed_official 532:fe11edbda85c 4543 tmpccer &= ~TIM_CCER_CC2P;
mbed_official 532:fe11edbda85c 4544 /* Set the Output Compare Polarity */
mbed_official 532:fe11edbda85c 4545 tmpccer |= (OC_Config->OCPolarity << 4);
mbed_official 532:fe11edbda85c 4546
mbed_official 532:fe11edbda85c 4547 if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
mbed_official 532:fe11edbda85c 4548 {
mbed_official 532:fe11edbda85c 4549 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
mbed_official 532:fe11edbda85c 4550 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
mbed_official 532:fe11edbda85c 4551 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
mbed_official 532:fe11edbda85c 4552
mbed_official 532:fe11edbda85c 4553 /* Reset the Output N Polarity level */
mbed_official 532:fe11edbda85c 4554 tmpccer &= ~TIM_CCER_CC2NP;
mbed_official 532:fe11edbda85c 4555 /* Set the Output N Polarity */
mbed_official 532:fe11edbda85c 4556 tmpccer |= (OC_Config->OCNPolarity << 4);
mbed_official 532:fe11edbda85c 4557 /* Reset the Output N State */
mbed_official 532:fe11edbda85c 4558 tmpccer &= ~TIM_CCER_CC2NE;
mbed_official 532:fe11edbda85c 4559
mbed_official 532:fe11edbda85c 4560 /* Reset the Output Compare and Output Compare N IDLE State */
mbed_official 532:fe11edbda85c 4561 tmpcr2 &= ~TIM_CR2_OIS2;
mbed_official 532:fe11edbda85c 4562 tmpcr2 &= ~TIM_CR2_OIS2N;
mbed_official 532:fe11edbda85c 4563 /* Set the Output Idle state */
mbed_official 532:fe11edbda85c 4564 tmpcr2 |= (OC_Config->OCIdleState << 2);
mbed_official 532:fe11edbda85c 4565 /* Set the Output N Idle state */
mbed_official 532:fe11edbda85c 4566 tmpcr2 |= (OC_Config->OCNIdleState << 2);
mbed_official 532:fe11edbda85c 4567 }
mbed_official 532:fe11edbda85c 4568 /* Write to TIMx CR2 */
mbed_official 532:fe11edbda85c 4569 TIMx->CR2 = tmpcr2;
mbed_official 532:fe11edbda85c 4570
mbed_official 532:fe11edbda85c 4571 /* Write to TIMx CCMR1 */
mbed_official 532:fe11edbda85c 4572 TIMx->CCMR1 = tmpccmrx;
mbed_official 532:fe11edbda85c 4573
mbed_official 532:fe11edbda85c 4574 /* Set the Capture Compare Register value */
mbed_official 532:fe11edbda85c 4575 TIMx->CCR2 = OC_Config->Pulse;
mbed_official 532:fe11edbda85c 4576
mbed_official 532:fe11edbda85c 4577 /* Write to TIMx CCER */
mbed_official 532:fe11edbda85c 4578 TIMx->CCER = tmpccer;
mbed_official 532:fe11edbda85c 4579 }
mbed_official 532:fe11edbda85c 4580
mbed_official 532:fe11edbda85c 4581 /**
mbed_official 532:fe11edbda85c 4582 * @brief TIM DMA Delay Pulse complete callback.
mbed_official 532:fe11edbda85c 4583 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
mbed_official 532:fe11edbda85c 4584 * the configuration information for the specified DMA module.
mbed_official 532:fe11edbda85c 4585 * @retval None
mbed_official 532:fe11edbda85c 4586 */
mbed_official 532:fe11edbda85c 4587 void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
mbed_official 532:fe11edbda85c 4588 {
mbed_official 532:fe11edbda85c 4589 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official 532:fe11edbda85c 4590
mbed_official 532:fe11edbda85c 4591 htim->State= HAL_TIM_STATE_READY;
mbed_official 532:fe11edbda85c 4592
mbed_official 532:fe11edbda85c 4593 if(hdma == htim->hdma[TIM_DMA_ID_CC1])
mbed_official 532:fe11edbda85c 4594 {
mbed_official 532:fe11edbda85c 4595 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
mbed_official 532:fe11edbda85c 4596 }
mbed_official 532:fe11edbda85c 4597 else if(hdma == htim->hdma[TIM_DMA_ID_CC2])
mbed_official 532:fe11edbda85c 4598 {
mbed_official 532:fe11edbda85c 4599 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
mbed_official 532:fe11edbda85c 4600 }
mbed_official 532:fe11edbda85c 4601 else if(hdma == htim->hdma[TIM_DMA_ID_CC3])
mbed_official 532:fe11edbda85c 4602 {
mbed_official 532:fe11edbda85c 4603 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
mbed_official 532:fe11edbda85c 4604 }
mbed_official 532:fe11edbda85c 4605 else if(hdma == htim->hdma[TIM_DMA_ID_CC4])
mbed_official 532:fe11edbda85c 4606 {
mbed_official 532:fe11edbda85c 4607 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
mbed_official 532:fe11edbda85c 4608 }
mbed_official 532:fe11edbda85c 4609
mbed_official 532:fe11edbda85c 4610 HAL_TIM_PWM_PulseFinishedCallback(htim);
mbed_official 532:fe11edbda85c 4611
mbed_official 532:fe11edbda85c 4612 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
mbed_official 532:fe11edbda85c 4613 }
mbed_official 532:fe11edbda85c 4614
mbed_official 532:fe11edbda85c 4615 /**
mbed_official 532:fe11edbda85c 4616 * @brief TIM DMA error callback
mbed_official 532:fe11edbda85c 4617 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
mbed_official 532:fe11edbda85c 4618 * the configuration information for the specified DMA module.
mbed_official 532:fe11edbda85c 4619 * @retval None
mbed_official 532:fe11edbda85c 4620 */
mbed_official 532:fe11edbda85c 4621 void TIM_DMAError(DMA_HandleTypeDef *hdma)
mbed_official 532:fe11edbda85c 4622 {
mbed_official 532:fe11edbda85c 4623 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official 532:fe11edbda85c 4624
mbed_official 532:fe11edbda85c 4625 htim->State= HAL_TIM_STATE_READY;
mbed_official 532:fe11edbda85c 4626
mbed_official 532:fe11edbda85c 4627 HAL_TIM_ErrorCallback(htim);
mbed_official 532:fe11edbda85c 4628 }
mbed_official 532:fe11edbda85c 4629
mbed_official 532:fe11edbda85c 4630 /**
mbed_official 532:fe11edbda85c 4631 * @brief TIM DMA Capture complete callback.
mbed_official 532:fe11edbda85c 4632 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
mbed_official 532:fe11edbda85c 4633 * the configuration information for the specified DMA module.
mbed_official 532:fe11edbda85c 4634 * @retval None
mbed_official 532:fe11edbda85c 4635 */
mbed_official 532:fe11edbda85c 4636 void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
mbed_official 532:fe11edbda85c 4637 {
mbed_official 532:fe11edbda85c 4638 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official 532:fe11edbda85c 4639
mbed_official 532:fe11edbda85c 4640 htim->State= HAL_TIM_STATE_READY;
mbed_official 532:fe11edbda85c 4641
mbed_official 532:fe11edbda85c 4642 if(hdma == htim->hdma[TIM_DMA_ID_CC1])
mbed_official 532:fe11edbda85c 4643 {
mbed_official 532:fe11edbda85c 4644 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
mbed_official 532:fe11edbda85c 4645 }
mbed_official 532:fe11edbda85c 4646 else if(hdma == htim->hdma[TIM_DMA_ID_CC2])
mbed_official 532:fe11edbda85c 4647 {
mbed_official 532:fe11edbda85c 4648 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
mbed_official 532:fe11edbda85c 4649 }
mbed_official 532:fe11edbda85c 4650 else if(hdma == htim->hdma[TIM_DMA_ID_CC3])
mbed_official 532:fe11edbda85c 4651 {
mbed_official 532:fe11edbda85c 4652 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
mbed_official 532:fe11edbda85c 4653 }
mbed_official 532:fe11edbda85c 4654 else if(hdma == htim->hdma[TIM_DMA_ID_CC4])
mbed_official 532:fe11edbda85c 4655 {
mbed_official 532:fe11edbda85c 4656 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
mbed_official 532:fe11edbda85c 4657 }
mbed_official 532:fe11edbda85c 4658
mbed_official 532:fe11edbda85c 4659 HAL_TIM_IC_CaptureCallback(htim);
mbed_official 532:fe11edbda85c 4660
mbed_official 532:fe11edbda85c 4661 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
mbed_official 532:fe11edbda85c 4662 }
mbed_official 532:fe11edbda85c 4663
mbed_official 532:fe11edbda85c 4664 /**
mbed_official 532:fe11edbda85c 4665 * @brief Enables or disables the TIM Capture Compare Channel x.
mbed_official 532:fe11edbda85c 4666 * @param TIMx to select the TIM peripheral
mbed_official 532:fe11edbda85c 4667 * @param Channel: specifies the TIM Channel
mbed_official 532:fe11edbda85c 4668 * This parameter can be one of the following values:
mbed_official 532:fe11edbda85c 4669 * @arg TIM_Channel_1: TIM Channel 1
mbed_official 532:fe11edbda85c 4670 * @arg TIM_Channel_2: TIM Channel 2
mbed_official 532:fe11edbda85c 4671 * @arg TIM_Channel_3: TIM Channel 3
mbed_official 532:fe11edbda85c 4672 * @arg TIM_Channel_4: TIM Channel 4
mbed_official 532:fe11edbda85c 4673 * @param ChannelState: specifies the TIM Channel CCxE bit new state.
mbed_official 532:fe11edbda85c 4674 * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable.
mbed_official 532:fe11edbda85c 4675 * @retval None
mbed_official 532:fe11edbda85c 4676 */
mbed_official 532:fe11edbda85c 4677 void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState)
mbed_official 532:fe11edbda85c 4678 {
mbed_official 532:fe11edbda85c 4679 uint32_t tmp = 0;
mbed_official 532:fe11edbda85c 4680
mbed_official 532:fe11edbda85c 4681 /* Check the parameters */
mbed_official 532:fe11edbda85c 4682 assert_param(IS_TIM_CC1_INSTANCE(TIMx));
mbed_official 532:fe11edbda85c 4683 assert_param(IS_TIM_CHANNELS(Channel));
mbed_official 532:fe11edbda85c 4684
mbed_official 532:fe11edbda85c 4685 tmp = TIM_CCER_CC1E << Channel;
mbed_official 532:fe11edbda85c 4686
mbed_official 532:fe11edbda85c 4687 /* Reset the CCxE Bit */
mbed_official 532:fe11edbda85c 4688 TIMx->CCER &= ~tmp;
mbed_official 532:fe11edbda85c 4689
mbed_official 532:fe11edbda85c 4690 /* Set or reset the CCxE Bit */
mbed_official 532:fe11edbda85c 4691 TIMx->CCER |= (uint32_t)(ChannelState << Channel);
mbed_official 532:fe11edbda85c 4692 }
mbed_official 532:fe11edbda85c 4693
mbed_official 532:fe11edbda85c 4694 /**
mbed_official 532:fe11edbda85c 4695 * @brief TIM DMA Period Elapse complete callback.
mbed_official 532:fe11edbda85c 4696 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
mbed_official 532:fe11edbda85c 4697 * the configuration information for the specified DMA module.
mbed_official 532:fe11edbda85c 4698 * @retval None
mbed_official 532:fe11edbda85c 4699 */
mbed_official 532:fe11edbda85c 4700 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
mbed_official 532:fe11edbda85c 4701 {
mbed_official 532:fe11edbda85c 4702 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official 532:fe11edbda85c 4703
mbed_official 532:fe11edbda85c 4704 htim->State= HAL_TIM_STATE_READY;
mbed_official 532:fe11edbda85c 4705
mbed_official 532:fe11edbda85c 4706 HAL_TIM_PeriodElapsedCallback(htim);
mbed_official 532:fe11edbda85c 4707 }
mbed_official 532:fe11edbda85c 4708
mbed_official 532:fe11edbda85c 4709 /**
mbed_official 532:fe11edbda85c 4710 * @brief TIM DMA Trigger callback.
mbed_official 532:fe11edbda85c 4711 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
mbed_official 532:fe11edbda85c 4712 * the configuration information for the specified DMA module.
mbed_official 532:fe11edbda85c 4713 * @retval None
mbed_official 532:fe11edbda85c 4714 */
mbed_official 532:fe11edbda85c 4715 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
mbed_official 532:fe11edbda85c 4716 {
mbed_official 532:fe11edbda85c 4717 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official 532:fe11edbda85c 4718
mbed_official 532:fe11edbda85c 4719 htim->State= HAL_TIM_STATE_READY;
mbed_official 532:fe11edbda85c 4720
mbed_official 532:fe11edbda85c 4721 HAL_TIM_TriggerCallback(htim);
mbed_official 532:fe11edbda85c 4722 }
mbed_official 532:fe11edbda85c 4723
mbed_official 532:fe11edbda85c 4724 /**
mbed_official 532:fe11edbda85c 4725 * @brief Time Output Compare 1 configuration
mbed_official 532:fe11edbda85c 4726 * @param TIMx to select the TIM peripheral
mbed_official 532:fe11edbda85c 4727 * @param OC_Config: The output configuration structure
mbed_official 532:fe11edbda85c 4728 * @retval None
mbed_official 532:fe11edbda85c 4729 */
mbed_official 532:fe11edbda85c 4730 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
mbed_official 532:fe11edbda85c 4731 {
mbed_official 532:fe11edbda85c 4732 uint32_t tmpccmrx = 0;
mbed_official 532:fe11edbda85c 4733 uint32_t tmpccer = 0;
mbed_official 532:fe11edbda85c 4734 uint32_t tmpcr2 = 0;
mbed_official 532:fe11edbda85c 4735
mbed_official 532:fe11edbda85c 4736 /* Disable the Channel 1: Reset the CC1E Bit */
mbed_official 532:fe11edbda85c 4737 TIMx->CCER &= ~TIM_CCER_CC1E;
mbed_official 532:fe11edbda85c 4738
mbed_official 532:fe11edbda85c 4739 /* Get the TIMx CCER register value */
mbed_official 532:fe11edbda85c 4740 tmpccer = TIMx->CCER;
mbed_official 532:fe11edbda85c 4741 /* Get the TIMx CR2 register value */
mbed_official 532:fe11edbda85c 4742 tmpcr2 = TIMx->CR2;
mbed_official 532:fe11edbda85c 4743
mbed_official 532:fe11edbda85c 4744 /* Get the TIMx CCMR1 register value */
mbed_official 532:fe11edbda85c 4745 tmpccmrx = TIMx->CCMR1;
mbed_official 532:fe11edbda85c 4746
mbed_official 532:fe11edbda85c 4747 /* Reset the Output Compare Mode Bits */
mbed_official 532:fe11edbda85c 4748 tmpccmrx &= ~TIM_CCMR1_OC1M;
mbed_official 532:fe11edbda85c 4749 tmpccmrx &= ~TIM_CCMR1_CC1S;
mbed_official 532:fe11edbda85c 4750 /* Select the Output Compare Mode */
mbed_official 532:fe11edbda85c 4751 tmpccmrx |= OC_Config->OCMode;
mbed_official 532:fe11edbda85c 4752
mbed_official 532:fe11edbda85c 4753 /* Reset the Output Polarity level */
mbed_official 532:fe11edbda85c 4754 tmpccer &= ~TIM_CCER_CC1P;
mbed_official 532:fe11edbda85c 4755 /* Set the Output Compare Polarity */
mbed_official 532:fe11edbda85c 4756 tmpccer |= OC_Config->OCPolarity;
mbed_official 532:fe11edbda85c 4757
mbed_official 532:fe11edbda85c 4758
mbed_official 532:fe11edbda85c 4759 if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
mbed_official 532:fe11edbda85c 4760 {
mbed_official 532:fe11edbda85c 4761 /* Reset the Output N Polarity level */
mbed_official 532:fe11edbda85c 4762 tmpccer &= ~TIM_CCER_CC1NP;
mbed_official 532:fe11edbda85c 4763 /* Set the Output N Polarity */
mbed_official 532:fe11edbda85c 4764 tmpccer |= OC_Config->OCNPolarity;
mbed_official 532:fe11edbda85c 4765 /* Reset the Output N State */
mbed_official 532:fe11edbda85c 4766 tmpccer &= ~TIM_CCER_CC1NE;
mbed_official 532:fe11edbda85c 4767
mbed_official 532:fe11edbda85c 4768 /* Reset the Output Compare and Output Compare N IDLE State */
mbed_official 532:fe11edbda85c 4769 tmpcr2 &= ~TIM_CR2_OIS1;
mbed_official 532:fe11edbda85c 4770 tmpcr2 &= ~TIM_CR2_OIS1N;
mbed_official 532:fe11edbda85c 4771 /* Set the Output Idle state */
mbed_official 532:fe11edbda85c 4772 tmpcr2 |= OC_Config->OCIdleState;
mbed_official 532:fe11edbda85c 4773 /* Set the Output N Idle state */
mbed_official 532:fe11edbda85c 4774 tmpcr2 |= OC_Config->OCNIdleState;
mbed_official 532:fe11edbda85c 4775 }
mbed_official 532:fe11edbda85c 4776 /* Write to TIMx CR2 */
mbed_official 532:fe11edbda85c 4777 TIMx->CR2 = tmpcr2;
mbed_official 532:fe11edbda85c 4778
mbed_official 532:fe11edbda85c 4779 /* Write to TIMx CCMR1 */
mbed_official 532:fe11edbda85c 4780 TIMx->CCMR1 = tmpccmrx;
mbed_official 532:fe11edbda85c 4781
mbed_official 532:fe11edbda85c 4782 /* Set the Capture Compare Register value */
mbed_official 532:fe11edbda85c 4783 TIMx->CCR1 = OC_Config->Pulse;
mbed_official 532:fe11edbda85c 4784
mbed_official 532:fe11edbda85c 4785 /* Write to TIMx CCER */
mbed_official 532:fe11edbda85c 4786 TIMx->CCER = tmpccer;
mbed_official 532:fe11edbda85c 4787 }
mbed_official 532:fe11edbda85c 4788
mbed_official 532:fe11edbda85c 4789 /**
mbed_official 532:fe11edbda85c 4790 * @brief Time Output Compare 3 configuration
mbed_official 532:fe11edbda85c 4791 * @param TIMx to select the TIM peripheral
mbed_official 532:fe11edbda85c 4792 * @param OC_Config: The output configuration structure
mbed_official 532:fe11edbda85c 4793 * @retval None
mbed_official 532:fe11edbda85c 4794 */
mbed_official 532:fe11edbda85c 4795 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
mbed_official 532:fe11edbda85c 4796 {
mbed_official 532:fe11edbda85c 4797 uint32_t tmpccmrx = 0;
mbed_official 532:fe11edbda85c 4798 uint32_t tmpccer = 0;
mbed_official 532:fe11edbda85c 4799 uint32_t tmpcr2 = 0;
mbed_official 532:fe11edbda85c 4800
mbed_official 532:fe11edbda85c 4801 /* Disable the Channel 3: Reset the CC2E Bit */
mbed_official 532:fe11edbda85c 4802 TIMx->CCER &= ~TIM_CCER_CC3E;
mbed_official 532:fe11edbda85c 4803
mbed_official 532:fe11edbda85c 4804 /* Get the TIMx CCER register value */
mbed_official 532:fe11edbda85c 4805 tmpccer = TIMx->CCER;
mbed_official 532:fe11edbda85c 4806 /* Get the TIMx CR2 register value */
mbed_official 532:fe11edbda85c 4807 tmpcr2 = TIMx->CR2;
mbed_official 532:fe11edbda85c 4808
mbed_official 532:fe11edbda85c 4809 /* Get the TIMx CCMR2 register value */
mbed_official 532:fe11edbda85c 4810 tmpccmrx = TIMx->CCMR2;
mbed_official 532:fe11edbda85c 4811
mbed_official 532:fe11edbda85c 4812 /* Reset the Output Compare mode and Capture/Compare selection Bits */
mbed_official 532:fe11edbda85c 4813 tmpccmrx &= ~TIM_CCMR2_OC3M;
mbed_official 532:fe11edbda85c 4814 tmpccmrx &= ~TIM_CCMR2_CC3S;
mbed_official 532:fe11edbda85c 4815 /* Select the Output Compare Mode */
mbed_official 532:fe11edbda85c 4816 tmpccmrx |= OC_Config->OCMode;
mbed_official 532:fe11edbda85c 4817
mbed_official 532:fe11edbda85c 4818 /* Reset the Output Polarity level */
mbed_official 532:fe11edbda85c 4819 tmpccer &= ~TIM_CCER_CC3P;
mbed_official 532:fe11edbda85c 4820 /* Set the Output Compare Polarity */
mbed_official 532:fe11edbda85c 4821 tmpccer |= (OC_Config->OCPolarity << 8);
mbed_official 532:fe11edbda85c 4822
mbed_official 532:fe11edbda85c 4823 if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
mbed_official 532:fe11edbda85c 4824 {
mbed_official 532:fe11edbda85c 4825 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
mbed_official 532:fe11edbda85c 4826 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
mbed_official 532:fe11edbda85c 4827 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
mbed_official 532:fe11edbda85c 4828
mbed_official 532:fe11edbda85c 4829 /* Reset the Output N Polarity level */
mbed_official 532:fe11edbda85c 4830 tmpccer &= ~TIM_CCER_CC3NP;
mbed_official 532:fe11edbda85c 4831 /* Set the Output N Polarity */
mbed_official 532:fe11edbda85c 4832 tmpccer |= (OC_Config->OCNPolarity << 8);
mbed_official 532:fe11edbda85c 4833 /* Reset the Output N State */
mbed_official 532:fe11edbda85c 4834 tmpccer &= ~TIM_CCER_CC3NE;
mbed_official 532:fe11edbda85c 4835
mbed_official 532:fe11edbda85c 4836 /* Reset the Output Compare and Output Compare N IDLE State */
mbed_official 532:fe11edbda85c 4837 tmpcr2 &= ~TIM_CR2_OIS3;
mbed_official 532:fe11edbda85c 4838 tmpcr2 &= ~TIM_CR2_OIS3N;
mbed_official 532:fe11edbda85c 4839 /* Set the Output Idle state */
mbed_official 532:fe11edbda85c 4840 tmpcr2 |= (OC_Config->OCIdleState << 4);
mbed_official 532:fe11edbda85c 4841 /* Set the Output N Idle state */
mbed_official 532:fe11edbda85c 4842 tmpcr2 |= (OC_Config->OCNIdleState << 4);
mbed_official 532:fe11edbda85c 4843 }
mbed_official 532:fe11edbda85c 4844 /* Write to TIMx CR2 */
mbed_official 532:fe11edbda85c 4845 TIMx->CR2 = tmpcr2;
mbed_official 532:fe11edbda85c 4846
mbed_official 532:fe11edbda85c 4847 /* Write to TIMx CCMR2 */
mbed_official 532:fe11edbda85c 4848 TIMx->CCMR2 = tmpccmrx;
mbed_official 532:fe11edbda85c 4849
mbed_official 532:fe11edbda85c 4850 /* Set the Capture Compare Register value */
mbed_official 532:fe11edbda85c 4851 TIMx->CCR3 = OC_Config->Pulse;
mbed_official 532:fe11edbda85c 4852
mbed_official 532:fe11edbda85c 4853 /* Write to TIMx CCER */
mbed_official 532:fe11edbda85c 4854 TIMx->CCER = tmpccer;
mbed_official 532:fe11edbda85c 4855 }
mbed_official 532:fe11edbda85c 4856
mbed_official 532:fe11edbda85c 4857 /**
mbed_official 532:fe11edbda85c 4858 * @brief Time Output Compare 4 configuration
mbed_official 532:fe11edbda85c 4859 * @param TIMx to select the TIM peripheral
mbed_official 532:fe11edbda85c 4860 * @param OC_Config: The output configuration structure
mbed_official 532:fe11edbda85c 4861 * @retval None
mbed_official 532:fe11edbda85c 4862 */
mbed_official 532:fe11edbda85c 4863 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
mbed_official 532:fe11edbda85c 4864 {
mbed_official 532:fe11edbda85c 4865 uint32_t tmpccmrx = 0;
mbed_official 532:fe11edbda85c 4866 uint32_t tmpccer = 0;
mbed_official 532:fe11edbda85c 4867 uint32_t tmpcr2 = 0;
mbed_official 532:fe11edbda85c 4868
mbed_official 532:fe11edbda85c 4869 /* Disable the Channel 4: Reset the CC4E Bit */
mbed_official 532:fe11edbda85c 4870 TIMx->CCER &= ~TIM_CCER_CC4E;
mbed_official 532:fe11edbda85c 4871
mbed_official 532:fe11edbda85c 4872 /* Get the TIMx CCER register value */
mbed_official 532:fe11edbda85c 4873 tmpccer = TIMx->CCER;
mbed_official 532:fe11edbda85c 4874 /* Get the TIMx CR2 register value */
mbed_official 532:fe11edbda85c 4875 tmpcr2 = TIMx->CR2;
mbed_official 532:fe11edbda85c 4876
mbed_official 532:fe11edbda85c 4877 /* Get the TIMx CCMR2 register value */
mbed_official 532:fe11edbda85c 4878 tmpccmrx = TIMx->CCMR2;
mbed_official 532:fe11edbda85c 4879
mbed_official 532:fe11edbda85c 4880 /* Reset the Output Compare mode and Capture/Compare selection Bits */
mbed_official 532:fe11edbda85c 4881 tmpccmrx &= ~TIM_CCMR2_OC4M;
mbed_official 532:fe11edbda85c 4882 tmpccmrx &= ~TIM_CCMR2_CC4S;
mbed_official 532:fe11edbda85c 4883
mbed_official 532:fe11edbda85c 4884 /* Select the Output Compare Mode */
mbed_official 532:fe11edbda85c 4885 tmpccmrx |= (OC_Config->OCMode << 8);
mbed_official 532:fe11edbda85c 4886
mbed_official 532:fe11edbda85c 4887 /* Reset the Output Polarity level */
mbed_official 532:fe11edbda85c 4888 tmpccer &= ~TIM_CCER_CC4P;
mbed_official 532:fe11edbda85c 4889 /* Set the Output Compare Polarity */
mbed_official 532:fe11edbda85c 4890 tmpccer |= (OC_Config->OCPolarity << 12);
mbed_official 532:fe11edbda85c 4891
mbed_official 532:fe11edbda85c 4892 /*if((TIMx == TIM1) || (TIMx == TIM8))*/
mbed_official 532:fe11edbda85c 4893 if(IS_TIM_ADVANCED_INSTANCE(TIMx) != RESET)
mbed_official 532:fe11edbda85c 4894 {
mbed_official 532:fe11edbda85c 4895 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
mbed_official 532:fe11edbda85c 4896 /* Reset the Output Compare IDLE State */
mbed_official 532:fe11edbda85c 4897 tmpcr2 &= ~TIM_CR2_OIS4;
mbed_official 532:fe11edbda85c 4898 /* Set the Output Idle state */
mbed_official 532:fe11edbda85c 4899 tmpcr2 |= (OC_Config->OCIdleState << 6);
mbed_official 532:fe11edbda85c 4900 }
mbed_official 532:fe11edbda85c 4901 /* Write to TIMx CR2 */
mbed_official 532:fe11edbda85c 4902 TIMx->CR2 = tmpcr2;
mbed_official 532:fe11edbda85c 4903
mbed_official 532:fe11edbda85c 4904 /* Write to TIMx CCMR2 */
mbed_official 532:fe11edbda85c 4905 TIMx->CCMR2 = tmpccmrx;
mbed_official 532:fe11edbda85c 4906
mbed_official 532:fe11edbda85c 4907 /* Set the Capture Compare Register value */
mbed_official 532:fe11edbda85c 4908 TIMx->CCR4 = OC_Config->Pulse;
mbed_official 532:fe11edbda85c 4909
mbed_official 532:fe11edbda85c 4910 /* Write to TIMx CCER */
mbed_official 532:fe11edbda85c 4911 TIMx->CCER = tmpccer;
mbed_official 532:fe11edbda85c 4912 }
mbed_official 532:fe11edbda85c 4913
mbed_official 532:fe11edbda85c 4914 /**
mbed_official 532:fe11edbda85c 4915 * @brief Time Output Compare 4 configuration
mbed_official 532:fe11edbda85c 4916 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
mbed_official 532:fe11edbda85c 4917 * the configuration information for TIM module.
mbed_official 532:fe11edbda85c 4918 * @param sSlaveConfig: The slave configuration structure
mbed_official 532:fe11edbda85c 4919 * @retval None
mbed_official 532:fe11edbda85c 4920 */
mbed_official 532:fe11edbda85c 4921 static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
mbed_official 532:fe11edbda85c 4922 TIM_SlaveConfigTypeDef * sSlaveConfig)
mbed_official 532:fe11edbda85c 4923 {
mbed_official 532:fe11edbda85c 4924 uint32_t tmpsmcr = 0;
mbed_official 532:fe11edbda85c 4925 uint32_t tmpccmr1 = 0;
mbed_official 532:fe11edbda85c 4926 uint32_t tmpccer = 0;
mbed_official 532:fe11edbda85c 4927
mbed_official 532:fe11edbda85c 4928 /* Get the TIMx SMCR register value */
mbed_official 87:085cde657901 4929 tmpsmcr = htim->Instance->SMCR;
mbed_official 87:085cde657901 4930
mbed_official 87:085cde657901 4931 /* Reset the Trigger Selection Bits */
mbed_official 87:085cde657901 4932 tmpsmcr &= ~TIM_SMCR_TS;
mbed_official 87:085cde657901 4933 /* Set the Input Trigger source */
mbed_official 87:085cde657901 4934 tmpsmcr |= sSlaveConfig->InputTrigger;
mbed_official 87:085cde657901 4935
mbed_official 87:085cde657901 4936 /* Reset the slave mode Bits */
mbed_official 87:085cde657901 4937 tmpsmcr &= ~TIM_SMCR_SMS;
mbed_official 87:085cde657901 4938 /* Set the slave mode */
mbed_official 87:085cde657901 4939 tmpsmcr |= sSlaveConfig->SlaveMode;
mbed_official 87:085cde657901 4940
mbed_official 87:085cde657901 4941 /* Write to TIMx SMCR */
mbed_official 87:085cde657901 4942 htim->Instance->SMCR = tmpsmcr;
mbed_official 87:085cde657901 4943
mbed_official 87:085cde657901 4944 /* Configure the trigger prescaler, filter, and polarity */
mbed_official 87:085cde657901 4945 switch (sSlaveConfig->InputTrigger)
mbed_official 87:085cde657901 4946 {
mbed_official 87:085cde657901 4947 case TIM_TS_ETRF:
mbed_official 87:085cde657901 4948 {
mbed_official 87:085cde657901 4949 /* Check the parameters */
mbed_official 87:085cde657901 4950 assert_param(IS_TIM_ETR_INSTANCE(htim->Instance));
mbed_official 87:085cde657901 4951 assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
mbed_official 87:085cde657901 4952 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
mbed_official 87:085cde657901 4953 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
mbed_official 87:085cde657901 4954 /* Configure the ETR Trigger source */
mbed_official 87:085cde657901 4955 TIM_ETR_SetConfig(htim->Instance,
mbed_official 87:085cde657901 4956 sSlaveConfig->TriggerPrescaler,
mbed_official 87:085cde657901 4957 sSlaveConfig->TriggerPolarity,
mbed_official 87:085cde657901 4958 sSlaveConfig->TriggerFilter);
mbed_official 87:085cde657901 4959 }
mbed_official 87:085cde657901 4960 break;
mbed_official 87:085cde657901 4961
mbed_official 87:085cde657901 4962 case TIM_TS_TI1F_ED:
mbed_official 87:085cde657901 4963 {
mbed_official 87:085cde657901 4964 /* Check the parameters */
mbed_official 87:085cde657901 4965 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
mbed_official 87:085cde657901 4966 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
mbed_official 87:085cde657901 4967
mbed_official 87:085cde657901 4968 /* Disable the Channel 1: Reset the CC1E Bit */
mbed_official 87:085cde657901 4969 tmpccer = htim->Instance->CCER;
mbed_official 87:085cde657901 4970 htim->Instance->CCER &= ~TIM_CCER_CC1E;
mbed_official 87:085cde657901 4971 tmpccmr1 = htim->Instance->CCMR1;
mbed_official 87:085cde657901 4972
mbed_official 87:085cde657901 4973 /* Set the filter */
mbed_official 87:085cde657901 4974 tmpccmr1 &= ~TIM_CCMR1_IC1F;
mbed_official 87:085cde657901 4975 tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4);
mbed_official 87:085cde657901 4976
mbed_official 87:085cde657901 4977 /* Write to TIMx CCMR1 and CCER registers */
mbed_official 87:085cde657901 4978 htim->Instance->CCMR1 = tmpccmr1;
mbed_official 87:085cde657901 4979 htim->Instance->CCER = tmpccer;
mbed_official 87:085cde657901 4980
mbed_official 87:085cde657901 4981 }
mbed_official 87:085cde657901 4982 break;
mbed_official 87:085cde657901 4983
mbed_official 87:085cde657901 4984 case TIM_TS_TI1FP1:
mbed_official 87:085cde657901 4985 {
mbed_official 87:085cde657901 4986 /* Check the parameters */
mbed_official 87:085cde657901 4987 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
mbed_official 87:085cde657901 4988 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
mbed_official 87:085cde657901 4989 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
mbed_official 87:085cde657901 4990
mbed_official 87:085cde657901 4991 /* Configure TI1 Filter and Polarity */
mbed_official 87:085cde657901 4992 TIM_TI1_ConfigInputStage(htim->Instance,
mbed_official 87:085cde657901 4993 sSlaveConfig->TriggerPolarity,
mbed_official 87:085cde657901 4994 sSlaveConfig->TriggerFilter);
mbed_official 87:085cde657901 4995 }
mbed_official 87:085cde657901 4996 break;
mbed_official 87:085cde657901 4997
mbed_official 87:085cde657901 4998 case TIM_TS_TI2FP2:
mbed_official 87:085cde657901 4999 {
mbed_official 87:085cde657901 5000 /* Check the parameters */
mbed_official 87:085cde657901 5001 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 87:085cde657901 5002 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
mbed_official 87:085cde657901 5003 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
mbed_official 87:085cde657901 5004
mbed_official 87:085cde657901 5005 /* Configure TI2 Filter and Polarity */
mbed_official 87:085cde657901 5006 TIM_TI2_ConfigInputStage(htim->Instance,
mbed_official 87:085cde657901 5007 sSlaveConfig->TriggerPolarity,
mbed_official 87:085cde657901 5008 sSlaveConfig->TriggerFilter);
mbed_official 87:085cde657901 5009 }
mbed_official 87:085cde657901 5010 break;
mbed_official 87:085cde657901 5011
mbed_official 87:085cde657901 5012 case TIM_TS_ITR0:
mbed_official 87:085cde657901 5013 {
mbed_official 87:085cde657901 5014 /* Check the parameter */
mbed_official 87:085cde657901 5015 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 87:085cde657901 5016 }
mbed_official 87:085cde657901 5017 break;
mbed_official 87:085cde657901 5018
mbed_official 87:085cde657901 5019 case TIM_TS_ITR1:
mbed_official 87:085cde657901 5020 {
mbed_official 87:085cde657901 5021 /* Check the parameter */
mbed_official 87:085cde657901 5022 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 87:085cde657901 5023 }
mbed_official 87:085cde657901 5024 break;
mbed_official 87:085cde657901 5025
mbed_official 87:085cde657901 5026 case TIM_TS_ITR2:
mbed_official 87:085cde657901 5027 {
mbed_official 87:085cde657901 5028 /* Check the parameter */
mbed_official 87:085cde657901 5029 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 87:085cde657901 5030 }
mbed_official 87:085cde657901 5031 break;
mbed_official 87:085cde657901 5032
mbed_official 87:085cde657901 5033 case TIM_TS_ITR3:
mbed_official 87:085cde657901 5034 {
mbed_official 87:085cde657901 5035 /* Check the parameter */
mbed_official 87:085cde657901 5036 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
mbed_official 87:085cde657901 5037 }
mbed_official 87:085cde657901 5038 break;
mbed_official 87:085cde657901 5039
mbed_official 87:085cde657901 5040 default:
mbed_official 87:085cde657901 5041 break;
mbed_official 87:085cde657901 5042 }
mbed_official 87:085cde657901 5043 }
mbed_official 87:085cde657901 5044
mbed_official 87:085cde657901 5045
mbed_official 87:085cde657901 5046 /**
mbed_official 87:085cde657901 5047 * @brief Configure the Polarity and Filter for TI1.
mbed_official 87:085cde657901 5048 * @param TIMx to select the TIM peripheral.
mbed_official 87:085cde657901 5049 * @param TIM_ICPolarity : The Input Polarity.
mbed_official 87:085cde657901 5050 * This parameter can be one of the following values:
mbed_official 87:085cde657901 5051 * @arg TIM_ICPolarity_Rising
mbed_official 87:085cde657901 5052 * @arg TIM_ICPolarity_Falling
mbed_official 87:085cde657901 5053 * @arg TIM_ICPolarity_BothEdge
mbed_official 87:085cde657901 5054 * @param TIM_ICFilter: Specifies the Input Capture Filter.
mbed_official 87:085cde657901 5055 * This parameter must be a value between 0x00 and 0x0F.
mbed_official 87:085cde657901 5056 * @retval None
mbed_official 87:085cde657901 5057 */
mbed_official 87:085cde657901 5058 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
mbed_official 87:085cde657901 5059 {
mbed_official 87:085cde657901 5060 uint32_t tmpccmr1 = 0;
mbed_official 87:085cde657901 5061 uint32_t tmpccer = 0;
mbed_official 87:085cde657901 5062
mbed_official 87:085cde657901 5063 /* Disable the Channel 1: Reset the CC1E Bit */
mbed_official 87:085cde657901 5064 tmpccer = TIMx->CCER;
mbed_official 87:085cde657901 5065 TIMx->CCER &= ~TIM_CCER_CC1E;
mbed_official 87:085cde657901 5066 tmpccmr1 = TIMx->CCMR1;
mbed_official 87:085cde657901 5067
mbed_official 87:085cde657901 5068 /* Set the filter */
mbed_official 87:085cde657901 5069 tmpccmr1 &= ~TIM_CCMR1_IC1F;
mbed_official 87:085cde657901 5070 tmpccmr1 |= (TIM_ICFilter << 4);
mbed_official 87:085cde657901 5071
mbed_official 87:085cde657901 5072 /* Select the Polarity and set the CC1E Bit */
mbed_official 87:085cde657901 5073 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
mbed_official 87:085cde657901 5074 tmpccer |= TIM_ICPolarity;
mbed_official 87:085cde657901 5075
mbed_official 87:085cde657901 5076 /* Write to TIMx CCMR1 and CCER registers */
mbed_official 87:085cde657901 5077 TIMx->CCMR1 = tmpccmr1;
mbed_official 87:085cde657901 5078 TIMx->CCER = tmpccer;
mbed_official 87:085cde657901 5079 }
mbed_official 87:085cde657901 5080
mbed_official 87:085cde657901 5081 /**
mbed_official 87:085cde657901 5082 * @brief Configure the TI2 as Input.
mbed_official 87:085cde657901 5083 * @param TIMx to select the TIM peripheral
mbed_official 87:085cde657901 5084 * @param TIM_ICPolarity : The Input Polarity.
mbed_official 87:085cde657901 5085 * This parameter can be one of the following values:
mbed_official 87:085cde657901 5086 * @arg TIM_ICPolarity_Rising
mbed_official 87:085cde657901 5087 * @arg TIM_ICPolarity_Falling
mbed_official 87:085cde657901 5088 * @arg TIM_ICPolarity_BothEdge
mbed_official 87:085cde657901 5089 * @param TIM_ICSelection: specifies the input to be used.
mbed_official 87:085cde657901 5090 * This parameter can be one of the following values:
mbed_official 87:085cde657901 5091 * @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2.
mbed_official 87:085cde657901 5092 * @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1.
mbed_official 87:085cde657901 5093 * @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC.
mbed_official 87:085cde657901 5094 * @param TIM_ICFilter: Specifies the Input Capture Filter.
mbed_official 87:085cde657901 5095 * This parameter must be a value between 0x00 and 0x0F.
mbed_official 532:fe11edbda85c 5096 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2
mbed_official 532:fe11edbda85c 5097 * (on channel1 path) is used as the input signal. Therefore CCMR1 must be
mbed_official 532:fe11edbda85c 5098 * protected against un-initialized filter and polarity values.
mbed_official 87:085cde657901 5099 * @retval None
mbed_official 87:085cde657901 5100 */
mbed_official 87:085cde657901 5101 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
mbed_official 87:085cde657901 5102 uint32_t TIM_ICFilter)
mbed_official 87:085cde657901 5103 {
mbed_official 87:085cde657901 5104 uint32_t tmpccmr1 = 0;
mbed_official 87:085cde657901 5105 uint32_t tmpccer = 0;
mbed_official 87:085cde657901 5106
mbed_official 87:085cde657901 5107 /* Disable the Channel 2: Reset the CC2E Bit */
mbed_official 87:085cde657901 5108 TIMx->CCER &= ~TIM_CCER_CC2E;
mbed_official 87:085cde657901 5109 tmpccmr1 = TIMx->CCMR1;
mbed_official 87:085cde657901 5110 tmpccer = TIMx->CCER;
mbed_official 87:085cde657901 5111
mbed_official 87:085cde657901 5112 /* Select the Input */
mbed_official 87:085cde657901 5113 tmpccmr1 &= ~TIM_CCMR1_CC2S;
mbed_official 87:085cde657901 5114 tmpccmr1 |= (TIM_ICSelection << 8);
mbed_official 87:085cde657901 5115
mbed_official 87:085cde657901 5116 /* Set the filter */
mbed_official 87:085cde657901 5117 tmpccmr1 &= ~TIM_CCMR1_IC2F;
mbed_official 532:fe11edbda85c 5118 tmpccmr1 |= ((TIM_ICFilter << 12) & TIM_CCMR1_IC2F);
mbed_official 87:085cde657901 5119
mbed_official 87:085cde657901 5120 /* Select the Polarity and set the CC2E Bit */
mbed_official 87:085cde657901 5121 tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
mbed_official 532:fe11edbda85c 5122 tmpccer |= ((TIM_ICPolarity << 4) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));
mbed_official 87:085cde657901 5123
mbed_official 87:085cde657901 5124 /* Write to TIMx CCMR1 and CCER registers */
mbed_official 87:085cde657901 5125 TIMx->CCMR1 = tmpccmr1 ;
mbed_official 87:085cde657901 5126 TIMx->CCER = tmpccer;
mbed_official 87:085cde657901 5127 }
mbed_official 87:085cde657901 5128
mbed_official 87:085cde657901 5129 /**
mbed_official 87:085cde657901 5130 * @brief Configure the Polarity and Filter for TI2.
mbed_official 87:085cde657901 5131 * @param TIMx to select the TIM peripheral.
mbed_official 87:085cde657901 5132 * @param TIM_ICPolarity : The Input Polarity.
mbed_official 87:085cde657901 5133 * This parameter can be one of the following values:
mbed_official 87:085cde657901 5134 * @arg TIM_ICPolarity_Rising
mbed_official 87:085cde657901 5135 * @arg TIM_ICPolarity_Falling
mbed_official 87:085cde657901 5136 * @arg TIM_ICPolarity_BothEdge
mbed_official 87:085cde657901 5137 * @param TIM_ICFilter: Specifies the Input Capture Filter.
mbed_official 87:085cde657901 5138 * This parameter must be a value between 0x00 and 0x0F.
mbed_official 87:085cde657901 5139 * @retval None
mbed_official 87:085cde657901 5140 */
mbed_official 87:085cde657901 5141 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
mbed_official 87:085cde657901 5142 {
mbed_official 87:085cde657901 5143 uint32_t tmpccmr1 = 0;
mbed_official 87:085cde657901 5144 uint32_t tmpccer = 0;
mbed_official 87:085cde657901 5145
mbed_official 87:085cde657901 5146 /* Disable the Channel 2: Reset the CC2E Bit */
mbed_official 87:085cde657901 5147 TIMx->CCER &= ~TIM_CCER_CC2E;
mbed_official 87:085cde657901 5148 tmpccmr1 = TIMx->CCMR1;
mbed_official 87:085cde657901 5149 tmpccer = TIMx->CCER;
mbed_official 87:085cde657901 5150
mbed_official 87:085cde657901 5151 /* Set the filter */
mbed_official 87:085cde657901 5152 tmpccmr1 &= ~TIM_CCMR1_IC2F;
mbed_official 87:085cde657901 5153 tmpccmr1 |= (TIM_ICFilter << 12);
mbed_official 87:085cde657901 5154
mbed_official 87:085cde657901 5155 /* Select the Polarity and set the CC2E Bit */
mbed_official 87:085cde657901 5156 tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
mbed_official 87:085cde657901 5157 tmpccer |= (TIM_ICPolarity << 4);
mbed_official 87:085cde657901 5158
mbed_official 87:085cde657901 5159 /* Write to TIMx CCMR1 and CCER registers */
mbed_official 87:085cde657901 5160 TIMx->CCMR1 = tmpccmr1 ;
mbed_official 87:085cde657901 5161 TIMx->CCER = tmpccer;
mbed_official 87:085cde657901 5162 }
mbed_official 87:085cde657901 5163
mbed_official 87:085cde657901 5164 /**
mbed_official 87:085cde657901 5165 * @brief Configure the TI3 as Input.
mbed_official 87:085cde657901 5166 * @param TIMx to select the TIM peripheral
mbed_official 87:085cde657901 5167 * @param TIM_ICPolarity : The Input Polarity.
mbed_official 87:085cde657901 5168 * This parameter can be one of the following values:
mbed_official 87:085cde657901 5169 * @arg TIM_ICPolarity_Rising
mbed_official 87:085cde657901 5170 * @arg TIM_ICPolarity_Falling
mbed_official 87:085cde657901 5171 * @arg TIM_ICPolarity_BothEdge
mbed_official 87:085cde657901 5172 * @param TIM_ICSelection: specifies the input to be used.
mbed_official 87:085cde657901 5173 * This parameter can be one of the following values:
mbed_official 87:085cde657901 5174 * @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3.
mbed_official 87:085cde657901 5175 * @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4.
mbed_official 87:085cde657901 5176 * @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC.
mbed_official 87:085cde657901 5177 * @param TIM_ICFilter: Specifies the Input Capture Filter.
mbed_official 87:085cde657901 5178 * This parameter must be a value between 0x00 and 0x0F.
mbed_official 532:fe11edbda85c 5179 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
mbed_official 532:fe11edbda85c 5180 * (on channel4 path) is used as the input signal. Therefore CCMR2 must be
mbed_official 532:fe11edbda85c 5181 * protected against un-initialized filter and polarity values.
mbed_official 87:085cde657901 5182 * @retval None
mbed_official 87:085cde657901 5183 */
mbed_official 87:085cde657901 5184 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
mbed_official 87:085cde657901 5185 uint32_t TIM_ICFilter)
mbed_official 87:085cde657901 5186 {
mbed_official 87:085cde657901 5187 uint32_t tmpccmr2 = 0;
mbed_official 87:085cde657901 5188 uint32_t tmpccer = 0;
mbed_official 87:085cde657901 5189
mbed_official 87:085cde657901 5190 /* Disable the Channel 3: Reset the CC3E Bit */
mbed_official 87:085cde657901 5191 TIMx->CCER &= ~TIM_CCER_CC3E;
mbed_official 87:085cde657901 5192 tmpccmr2 = TIMx->CCMR2;
mbed_official 87:085cde657901 5193 tmpccer = TIMx->CCER;
mbed_official 87:085cde657901 5194
mbed_official 87:085cde657901 5195 /* Select the Input */
mbed_official 87:085cde657901 5196 tmpccmr2 &= ~TIM_CCMR2_CC3S;
mbed_official 87:085cde657901 5197 tmpccmr2 |= TIM_ICSelection;
mbed_official 87:085cde657901 5198
mbed_official 87:085cde657901 5199 /* Set the filter */
mbed_official 87:085cde657901 5200 tmpccmr2 &= ~TIM_CCMR2_IC3F;
mbed_official 532:fe11edbda85c 5201 tmpccmr2 |= ((TIM_ICFilter << 4) & TIM_CCMR2_IC3F);
mbed_official 87:085cde657901 5202
mbed_official 87:085cde657901 5203 /* Select the Polarity and set the CC3E Bit */
mbed_official 87:085cde657901 5204 tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
mbed_official 532:fe11edbda85c 5205 tmpccer |= ((TIM_ICPolarity << 8) & (TIM_CCER_CC3P | TIM_CCER_CC3NP));
mbed_official 87:085cde657901 5206
mbed_official 87:085cde657901 5207 /* Write to TIMx CCMR2 and CCER registers */
mbed_official 87:085cde657901 5208 TIMx->CCMR2 = tmpccmr2;
mbed_official 87:085cde657901 5209 TIMx->CCER = tmpccer;
mbed_official 87:085cde657901 5210 }
mbed_official 87:085cde657901 5211
mbed_official 87:085cde657901 5212 /**
mbed_official 87:085cde657901 5213 * @brief Configure the TI4 as Input.
mbed_official 87:085cde657901 5214 * @param TIMx to select the TIM peripheral
mbed_official 87:085cde657901 5215 * @param TIM_ICPolarity : The Input Polarity.
mbed_official 87:085cde657901 5216 * This parameter can be one of the following values:
mbed_official 87:085cde657901 5217 * @arg TIM_ICPolarity_Rising
mbed_official 87:085cde657901 5218 * @arg TIM_ICPolarity_Falling
mbed_official 87:085cde657901 5219 * @arg TIM_ICPolarity_BothEdge
mbed_official 87:085cde657901 5220 * @param TIM_ICSelection: specifies the input to be used.
mbed_official 87:085cde657901 5221 * This parameter can be one of the following values:
mbed_official 87:085cde657901 5222 * @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4.
mbed_official 87:085cde657901 5223 * @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3.
mbed_official 87:085cde657901 5224 * @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC.
mbed_official 87:085cde657901 5225 * @param TIM_ICFilter: Specifies the Input Capture Filter.
mbed_official 87:085cde657901 5226 * This parameter must be a value between 0x00 and 0x0F.
mbed_official 532:fe11edbda85c 5227 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
mbed_official 532:fe11edbda85c 5228 * (on channel3 path) is used as the input signal. Therefore CCMR2 must be
mbed_official 532:fe11edbda85c 5229 * protected against un-initialized filter and polarity values.
mbed_official 87:085cde657901 5230 * @retval None
mbed_official 87:085cde657901 5231 */
mbed_official 87:085cde657901 5232 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
mbed_official 87:085cde657901 5233 uint32_t TIM_ICFilter)
mbed_official 87:085cde657901 5234 {
mbed_official 87:085cde657901 5235 uint32_t tmpccmr2 = 0;
mbed_official 87:085cde657901 5236 uint32_t tmpccer = 0;
mbed_official 87:085cde657901 5237
mbed_official 87:085cde657901 5238 /* Disable the Channel 4: Reset the CC4E Bit */
mbed_official 87:085cde657901 5239 TIMx->CCER &= ~TIM_CCER_CC4E;
mbed_official 87:085cde657901 5240 tmpccmr2 = TIMx->CCMR2;
mbed_official 87:085cde657901 5241 tmpccer = TIMx->CCER;
mbed_official 87:085cde657901 5242
mbed_official 87:085cde657901 5243 /* Select the Input */
mbed_official 87:085cde657901 5244 tmpccmr2 &= ~TIM_CCMR2_CC4S;
mbed_official 87:085cde657901 5245 tmpccmr2 |= (TIM_ICSelection << 8);
mbed_official 87:085cde657901 5246
mbed_official 87:085cde657901 5247 /* Set the filter */
mbed_official 87:085cde657901 5248 tmpccmr2 &= ~TIM_CCMR2_IC4F;
mbed_official 532:fe11edbda85c 5249 tmpccmr2 |= ((TIM_ICFilter << 12) & TIM_CCMR2_IC4F);
mbed_official 87:085cde657901 5250
mbed_official 87:085cde657901 5251 /* Select the Polarity and set the CC4E Bit */
mbed_official 87:085cde657901 5252 tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
mbed_official 532:fe11edbda85c 5253 tmpccer |= ((TIM_ICPolarity << 12) & (TIM_CCER_CC4P | TIM_CCER_CC4NP));
mbed_official 87:085cde657901 5254
mbed_official 87:085cde657901 5255 /* Write to TIMx CCMR2 and CCER registers */
mbed_official 87:085cde657901 5256 TIMx->CCMR2 = tmpccmr2;
mbed_official 87:085cde657901 5257 TIMx->CCER = tmpccer ;
mbed_official 87:085cde657901 5258 }
mbed_official 87:085cde657901 5259
mbed_official 87:085cde657901 5260 /**
mbed_official 87:085cde657901 5261 * @brief Selects the Input Trigger source
mbed_official 87:085cde657901 5262 * @param TIMx to select the TIM peripheral
mbed_official 532:fe11edbda85c 5263 * @param TIM_ITRx: The Input Trigger source.
mbed_official 87:085cde657901 5264 * This parameter can be one of the following values:
mbed_official 87:085cde657901 5265 * @arg TIM_TS_ITR0: Internal Trigger 0
mbed_official 87:085cde657901 5266 * @arg TIM_TS_ITR1: Internal Trigger 1
mbed_official 87:085cde657901 5267 * @arg TIM_TS_ITR2: Internal Trigger 2
mbed_official 87:085cde657901 5268 * @arg TIM_TS_ITR3: Internal Trigger 3
mbed_official 87:085cde657901 5269 * @arg TIM_TS_TI1F_ED: TI1 Edge Detector
mbed_official 87:085cde657901 5270 * @arg TIM_TS_TI1FP1: Filtered Timer Input 1
mbed_official 87:085cde657901 5271 * @arg TIM_TS_TI2FP2: Filtered Timer Input 2
mbed_official 87:085cde657901 5272 * @arg TIM_TS_ETRF: External Trigger input
mbed_official 87:085cde657901 5273 * @retval None
mbed_official 87:085cde657901 5274 */
mbed_official 87:085cde657901 5275 static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t TIM_ITRx)
mbed_official 87:085cde657901 5276 {
mbed_official 87:085cde657901 5277 uint32_t tmpsmcr = 0;
mbed_official 87:085cde657901 5278
mbed_official 87:085cde657901 5279 /* Get the TIMx SMCR register value */
mbed_official 87:085cde657901 5280 tmpsmcr = TIMx->SMCR;
mbed_official 87:085cde657901 5281 /* Reset the TS Bits */
mbed_official 87:085cde657901 5282 tmpsmcr &= ~TIM_SMCR_TS;
mbed_official 87:085cde657901 5283 /* Set the Input Trigger source and the slave mode*/
mbed_official 87:085cde657901 5284 tmpsmcr |= TIM_ITRx | TIM_SLAVEMODE_EXTERNAL1;
mbed_official 87:085cde657901 5285 /* Write to TIMx SMCR */
mbed_official 87:085cde657901 5286 TIMx->SMCR = tmpsmcr;
mbed_official 87:085cde657901 5287 }
mbed_official 532:fe11edbda85c 5288
mbed_official 87:085cde657901 5289 /**
mbed_official 87:085cde657901 5290 * @brief Configures the TIMx External Trigger (ETR).
mbed_official 87:085cde657901 5291 * @param TIMx to select the TIM peripheral
mbed_official 87:085cde657901 5292 * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
mbed_official 87:085cde657901 5293 * This parameter can be one of the following values:
mbed_official 87:085cde657901 5294 * @arg TIM_ExtTRGPSC_DIV1: ETRP Prescaler OFF.
mbed_official 87:085cde657901 5295 * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
mbed_official 87:085cde657901 5296 * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
mbed_official 87:085cde657901 5297 * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
mbed_official 87:085cde657901 5298 * @param TIM_ExtTRGPolarity: The external Trigger Polarity.
mbed_official 87:085cde657901 5299 * This parameter can be one of the following values:
mbed_official 87:085cde657901 5300 * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
mbed_official 87:085cde657901 5301 * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
mbed_official 87:085cde657901 5302 * @param ExtTRGFilter: External Trigger Filter.
mbed_official 87:085cde657901 5303 * This parameter must be a value between 0x00 and 0x0F
mbed_official 87:085cde657901 5304 * @retval None
mbed_official 87:085cde657901 5305 */
mbed_official 87:085cde657901 5306 static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
mbed_official 87:085cde657901 5307 uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
mbed_official 87:085cde657901 5308 {
mbed_official 87:085cde657901 5309 uint32_t tmpsmcr = 0;
mbed_official 87:085cde657901 5310
mbed_official 87:085cde657901 5311 tmpsmcr = TIMx->SMCR;
mbed_official 87:085cde657901 5312
mbed_official 87:085cde657901 5313 /* Reset the ETR Bits */
mbed_official 87:085cde657901 5314 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
mbed_official 87:085cde657901 5315
mbed_official 87:085cde657901 5316 /* Set the Prescaler, the Filter value and the Polarity */
mbed_official 87:085cde657901 5317 tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8)));
mbed_official 87:085cde657901 5318
mbed_official 87:085cde657901 5319 /* Write to TIMx SMCR */
mbed_official 87:085cde657901 5320 TIMx->SMCR = tmpsmcr;
mbed_official 87:085cde657901 5321 }
mbed_official 87:085cde657901 5322
mbed_official 87:085cde657901 5323 /**
mbed_official 87:085cde657901 5324 * @}
mbed_official 87:085cde657901 5325 */
mbed_official 87:085cde657901 5326
mbed_official 87:085cde657901 5327 #endif /* HAL_TIM_MODULE_ENABLED */
mbed_official 87:085cde657901 5328 /**
mbed_official 87:085cde657901 5329 * @}
mbed_official 87:085cde657901 5330 */
mbed_official 87:085cde657901 5331
mbed_official 87:085cde657901 5332 /**
mbed_official 87:085cde657901 5333 * @}
mbed_official 87:085cde657901 5334 */
mbed_official 87:085cde657901 5335 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/