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This library was superseded by mbed-dev - https://os.mbed.com/users/mbed_official/code/mbed-dev/.

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If you are looking for a stable and tested release, please import one of the official mbed library releases:

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Last commit 20 Feb 2019 by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_spi.c@581:39197bcd20f2, 2015-07-02 (annotated)

Committer:
mbed_official
Date:
Thu Jul 02 16:30:08 2015 +0100
Revision:
581:39197bcd20f2
Parent:
532:fe11edbda85c
Child:
613:bc40b8d2aec4
Synchronized with git revision ae2d3cdffe70184eb8736d94f76c45c93f4b7724



Full URL: https://github.com/mbedmicro/mbed/commit/ae2d3cdffe70184eb8736d94f76c45c93f4b7724/



Make it possible to build the core mbed library with yotta

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 87:085cde657901 1 /**
mbed_official 87:085cde657901 2 ******************************************************************************
mbed_official 87:085cde657901 3 * @file stm32f4xx_hal_spi.c
mbed_official 87:085cde657901 4 * @author MCD Application Team
mbed_official 532:fe11edbda85c 5 * @version V1.3.0
mbed_official 532:fe11edbda85c 6 * @date 09-March-2015
mbed_official 87:085cde657901 7 * @brief SPI HAL module driver.
mbed_official 87:085cde657901 8 *
mbed_official 87:085cde657901 9 * This file provides firmware functions to manage the following
mbed_official 87:085cde657901 10 * functionalities of the Serial Peripheral Interface (SPI) peripheral:
mbed_official 87:085cde657901 11 * + Initialization and de-initialization functions
mbed_official 87:085cde657901 12 * + IO operation functions
mbed_official 87:085cde657901 13 * + Peripheral Control functions
mbed_official 87:085cde657901 14 * + Peripheral State functions
mbed_official 87:085cde657901 15 @verbatim
mbed_official 87:085cde657901 16 ==============================================================================
mbed_official 87:085cde657901 17 ##### How to use this driver #####
mbed_official 87:085cde657901 18 ==============================================================================
mbed_official 87:085cde657901 19 [..]
mbed_official 87:085cde657901 20 The SPI HAL driver can be used as follows:
mbed_official 87:085cde657901 21
mbed_official 87:085cde657901 22 (#) Declare a SPI_HandleTypeDef handle structure, for example:
mbed_official 87:085cde657901 23 SPI_HandleTypeDef hspi;
mbed_official 87:085cde657901 24
mbed_official 226:b062af740e40 25 (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit ()API:
mbed_official 87:085cde657901 26 (##) Enable the SPIx interface clock
mbed_official 87:085cde657901 27 (##) SPI pins configuration
mbed_official 87:085cde657901 28 (+++) Enable the clock for the SPI GPIOs
mbed_official 87:085cde657901 29 (+++) Configure these SPI pins as alternate function push-pull
mbed_official 87:085cde657901 30 (##) NVIC configuration if you need to use interrupt process
mbed_official 87:085cde657901 31 (+++) Configure the SPIx interrupt priority
mbed_official 87:085cde657901 32 (+++) Enable the NVIC SPI IRQ handle
mbed_official 87:085cde657901 33 (##) DMA Configuration if you need to use DMA process
mbed_official 87:085cde657901 34 (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive stream
mbed_official 87:085cde657901 35 (+++) Enable the DMAx interface clock using
mbed_official 87:085cde657901 36 (+++) Configure the DMA handle parameters
mbed_official 87:085cde657901 37 (+++) Configure the DMA Tx or Rx Stream
mbed_official 532:fe11edbda85c 38 (+++) Associate the initialized hdma_tx handle to the hspi DMA Tx or Rx handle
mbed_official 87:085cde657901 39 (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream
mbed_official 87:085cde657901 40
mbed_official 87:085cde657901 41 (#) Program the Mode, Direction , Data size, Baudrate Prescaler, NSS
mbed_official 87:085cde657901 42 management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.
mbed_official 87:085cde657901 43
mbed_official 87:085cde657901 44 (#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
mbed_official 87:085cde657901 45 (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
mbed_official 532:fe11edbda85c 46 by calling the customized HAL_SPI_MspInit() API.
mbed_official 369:2e96f1b71984 47 [..]
mbed_official 369:2e96f1b71984 48 Circular mode restriction:
mbed_official 369:2e96f1b71984 49 (#) The DMA circular mode cannot be used when the SPI is configured in these modes:
mbed_official 369:2e96f1b71984 50 (##) Master 2Lines RxOnly
mbed_official 369:2e96f1b71984 51 (##) Master 1Line Rx
mbed_official 369:2e96f1b71984 52 (#) The CRC feature is not managed when the DMA circular mode is enabled
mbed_official 369:2e96f1b71984 53 (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs
mbed_official 369:2e96f1b71984 54 the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks
mbed_official 369:2e96f1b71984 55
mbed_official 369:2e96f1b71984 56
mbed_official 87:085cde657901 57
mbed_official 87:085cde657901 58 @endverbatim
mbed_official 87:085cde657901 59 ******************************************************************************
mbed_official 87:085cde657901 60 * @attention
mbed_official 87:085cde657901 61 *
mbed_official 532:fe11edbda85c 62 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
mbed_official 87:085cde657901 63 *
mbed_official 87:085cde657901 64 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 87:085cde657901 65 * are permitted provided that the following conditions are met:
mbed_official 87:085cde657901 66 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 87:085cde657901 67 * this list of conditions and the following disclaimer.
mbed_official 87:085cde657901 68 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 87:085cde657901 69 * this list of conditions and the following disclaimer in the documentation
mbed_official 87:085cde657901 70 * and/or other materials provided with the distribution.
mbed_official 87:085cde657901 71 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 87:085cde657901 72 * may be used to endorse or promote products derived from this software
mbed_official 87:085cde657901 73 * without specific prior written permission.
mbed_official 87:085cde657901 74 *
mbed_official 87:085cde657901 75 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 87:085cde657901 76 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 87:085cde657901 77 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 87:085cde657901 78 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 87:085cde657901 79 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 87:085cde657901 80 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 87:085cde657901 81 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 87:085cde657901 82 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 87:085cde657901 83 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 87:085cde657901 84 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 87:085cde657901 85 *
mbed_official 87:085cde657901 86 ******************************************************************************
mbed_official 87:085cde657901 87 */
mbed_official 87:085cde657901 88
mbed_official 87:085cde657901 89 /* Includes ------------------------------------------------------------------*/
mbed_official 87:085cde657901 90 #include "stm32f4xx_hal.h"
mbed_official 87:085cde657901 91
mbed_official 87:085cde657901 92 /** @addtogroup STM32F4xx_HAL_Driver
mbed_official 87:085cde657901 93 * @{
mbed_official 87:085cde657901 94 */
mbed_official 87:085cde657901 95
mbed_official 532:fe11edbda85c 96 /** @defgroup SPI SPI
mbed_official 87:085cde657901 97 * @brief SPI HAL module driver
mbed_official 87:085cde657901 98 * @{
mbed_official 87:085cde657901 99 */
mbed_official 87:085cde657901 100
mbed_official 87:085cde657901 101 #ifdef HAL_SPI_MODULE_ENABLED
mbed_official 87:085cde657901 102
mbed_official 87:085cde657901 103 /* Private typedef -----------------------------------------------------------*/
mbed_official 87:085cde657901 104 /* Private define ------------------------------------------------------------*/
mbed_official 87:085cde657901 105 #define SPI_TIMEOUT_VALUE 10
mbed_official 87:085cde657901 106 /* Private macro -------------------------------------------------------------*/
mbed_official 87:085cde657901 107 /* Private variables ---------------------------------------------------------*/
mbed_official 87:085cde657901 108 /* Private function prototypes -----------------------------------------------*/
mbed_official 532:fe11edbda85c 109 /** @addtogroup SPI_Private_Functions
mbed_official 532:fe11edbda85c 110 * @{
mbed_official 532:fe11edbda85c 111 */
mbed_official 87:085cde657901 112 static void SPI_TxCloseIRQHandler(SPI_HandleTypeDef *hspi);
mbed_official 87:085cde657901 113 static void SPI_TxISR(SPI_HandleTypeDef *hspi);
mbed_official 106:ced8cbb51063 114 static void SPI_RxCloseIRQHandler(SPI_HandleTypeDef *hspi);
mbed_official 87:085cde657901 115 static void SPI_2LinesRxISR(SPI_HandleTypeDef *hspi);
mbed_official 87:085cde657901 116 static void SPI_RxISR(SPI_HandleTypeDef *hspi);
mbed_official 532:fe11edbda85c 117 static void SPI_DMAEndTransmitReceive(SPI_HandleTypeDef *hspi);
mbed_official 87:085cde657901 118 static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
mbed_official 87:085cde657901 119 static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
mbed_official 87:085cde657901 120 static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);
mbed_official 369:2e96f1b71984 121 static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma);
mbed_official 369:2e96f1b71984 122 static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma);
mbed_official 369:2e96f1b71984 123 static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma);
mbed_official 87:085cde657901 124 static void SPI_DMAError(DMA_HandleTypeDef *hdma);
mbed_official 87:085cde657901 125 static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
mbed_official 532:fe11edbda85c 126 /**
mbed_official 532:fe11edbda85c 127 * @}
mbed_official 532:fe11edbda85c 128 */
mbed_official 532:fe11edbda85c 129
mbed_official 532:fe11edbda85c 130 /* Exported functions --------------------------------------------------------*/
mbed_official 532:fe11edbda85c 131 /** @defgroup SPI_Exported_Functions SPI Exported Functions
mbed_official 87:085cde657901 132 * @{
mbed_official 87:085cde657901 133 */
mbed_official 87:085cde657901 134
mbed_official 532:fe11edbda85c 135 /** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
mbed_official 87:085cde657901 136 * @brief Initialization and Configuration functions
mbed_official 87:085cde657901 137 *
mbed_official 87:085cde657901 138 @verbatim
mbed_official 87:085cde657901 139 ===============================================================================
mbed_official 87:085cde657901 140 ##### Initialization and de-initialization functions #####
mbed_official 87:085cde657901 141 ===============================================================================
mbed_official 87:085cde657901 142 [..] This subsection provides a set of functions allowing to initialize and
mbed_official 532:fe11edbda85c 143 de-initialize the SPIx peripheral:
mbed_official 87:085cde657901 144
mbed_official 226:b062af740e40 145 (+) User must implement HAL_SPI_MspInit() function in which he configures
mbed_official 87:085cde657901 146 all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
mbed_official 87:085cde657901 147
mbed_official 87:085cde657901 148 (+) Call the function HAL_SPI_Init() to configure the selected device with
mbed_official 87:085cde657901 149 the selected configuration:
mbed_official 87:085cde657901 150 (++) Mode
mbed_official 87:085cde657901 151 (++) Direction
mbed_official 87:085cde657901 152 (++) Data Size
mbed_official 87:085cde657901 153 (++) Clock Polarity and Phase
mbed_official 87:085cde657901 154 (++) NSS Management
mbed_official 87:085cde657901 155 (++) BaudRate Prescaler
mbed_official 87:085cde657901 156 (++) FirstBit
mbed_official 87:085cde657901 157 (++) TIMode
mbed_official 87:085cde657901 158 (++) CRC Calculation
mbed_official 87:085cde657901 159 (++) CRC Polynomial if CRC enabled
mbed_official 87:085cde657901 160
mbed_official 87:085cde657901 161 (+) Call the function HAL_SPI_DeInit() to restore the default configuration
mbed_official 532:fe11edbda85c 162 of the selected SPIx peripheral.
mbed_official 87:085cde657901 163
mbed_official 87:085cde657901 164 @endverbatim
mbed_official 87:085cde657901 165 * @{
mbed_official 87:085cde657901 166 */
mbed_official 87:085cde657901 167
mbed_official 87:085cde657901 168 /**
mbed_official 87:085cde657901 169 * @brief Initializes the SPI according to the specified parameters
mbed_official 87:085cde657901 170 * in the SPI_InitTypeDef and create the associated handle.
mbed_official 226:b062af740e40 171 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 172 * the configuration information for SPI module.
mbed_official 87:085cde657901 173 * @retval HAL status
mbed_official 87:085cde657901 174 */
mbed_official 87:085cde657901 175 HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
mbed_official 87:085cde657901 176 {
mbed_official 87:085cde657901 177 /* Check the SPI handle allocation */
mbed_official 369:2e96f1b71984 178 if(hspi == HAL_NULL)
mbed_official 87:085cde657901 179 {
mbed_official 87:085cde657901 180 return HAL_ERROR;
mbed_official 87:085cde657901 181 }
mbed_official 87:085cde657901 182
mbed_official 87:085cde657901 183 /* Check the parameters */
mbed_official 87:085cde657901 184 assert_param(IS_SPI_MODE(hspi->Init.Mode));
mbed_official 87:085cde657901 185 assert_param(IS_SPI_DIRECTION_MODE(hspi->Init.Direction));
mbed_official 87:085cde657901 186 assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
mbed_official 87:085cde657901 187 assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
mbed_official 87:085cde657901 188 assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
mbed_official 87:085cde657901 189 assert_param(IS_SPI_NSS(hspi->Init.NSS));
mbed_official 87:085cde657901 190 assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
mbed_official 87:085cde657901 191 assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
mbed_official 87:085cde657901 192 assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
mbed_official 87:085cde657901 193 assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
mbed_official 87:085cde657901 194 assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
mbed_official 87:085cde657901 195
mbed_official 87:085cde657901 196 if(hspi->State == HAL_SPI_STATE_RESET)
mbed_official 87:085cde657901 197 {
mbed_official 532:fe11edbda85c 198 /* Allocate lock resource and initialize it */
mbed_official 532:fe11edbda85c 199 hspi->Lock = HAL_UNLOCKED;
mbed_official 87:085cde657901 200 /* Init the low level hardware : GPIO, CLOCK, NVIC... */
mbed_official 87:085cde657901 201 HAL_SPI_MspInit(hspi);
mbed_official 87:085cde657901 202 }
mbed_official 87:085cde657901 203
mbed_official 87:085cde657901 204 hspi->State = HAL_SPI_STATE_BUSY;
mbed_official 87:085cde657901 205
mbed_official 532:fe11edbda85c 206 /* Disable the selected SPI peripheral */
mbed_official 87:085cde657901 207 __HAL_SPI_DISABLE(hspi);
mbed_official 87:085cde657901 208
mbed_official 87:085cde657901 209 /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
mbed_official 87:085cde657901 210 /* Configure : SPI Mode, Communication Mode, Data size, Clock polarity and phase, NSS management,
mbed_official 87:085cde657901 211 Communication speed, First bit and CRC calculation state */
mbed_official 87:085cde657901 212 hspi->Instance->CR1 = (hspi->Init.Mode | hspi->Init.Direction | hspi->Init.DataSize |
mbed_official 87:085cde657901 213 hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) |
mbed_official 87:085cde657901 214 hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit | hspi->Init.CRCCalculation);
mbed_official 87:085cde657901 215
mbed_official 87:085cde657901 216 /* Configure : NSS management */
mbed_official 87:085cde657901 217 hspi->Instance->CR2 = (((hspi->Init.NSS >> 16) & SPI_CR2_SSOE) | hspi->Init.TIMode);
mbed_official 87:085cde657901 218
mbed_official 87:085cde657901 219 /*---------------------------- SPIx CRCPOLY Configuration ------------------*/
mbed_official 87:085cde657901 220 /* Configure : CRC Polynomial */
mbed_official 87:085cde657901 221 hspi->Instance->CRCPR = hspi->Init.CRCPolynomial;
mbed_official 87:085cde657901 222
mbed_official 87:085cde657901 223 /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
mbed_official 87:085cde657901 224 hspi->Instance->I2SCFGR &= (uint32_t)(~SPI_I2SCFGR_I2SMOD);
mbed_official 87:085cde657901 225
mbed_official 87:085cde657901 226 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official 87:085cde657901 227 hspi->State = HAL_SPI_STATE_READY;
mbed_official 87:085cde657901 228
mbed_official 87:085cde657901 229 return HAL_OK;
mbed_official 87:085cde657901 230 }
mbed_official 87:085cde657901 231
mbed_official 87:085cde657901 232 /**
mbed_official 87:085cde657901 233 * @brief DeInitializes the SPI peripheral
mbed_official 226:b062af740e40 234 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 235 * the configuration information for SPI module.
mbed_official 87:085cde657901 236 * @retval HAL status
mbed_official 87:085cde657901 237 */
mbed_official 87:085cde657901 238 HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
mbed_official 87:085cde657901 239 {
mbed_official 87:085cde657901 240 /* Check the SPI handle allocation */
mbed_official 369:2e96f1b71984 241 if(hspi == HAL_NULL)
mbed_official 87:085cde657901 242 {
mbed_official 87:085cde657901 243 return HAL_ERROR;
mbed_official 87:085cde657901 244 }
mbed_official 87:085cde657901 245
mbed_official 87:085cde657901 246 /* Disable the SPI Peripheral Clock */
mbed_official 87:085cde657901 247 __HAL_SPI_DISABLE(hspi);
mbed_official 87:085cde657901 248
mbed_official 87:085cde657901 249 /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
mbed_official 87:085cde657901 250 HAL_SPI_MspDeInit(hspi);
mbed_official 87:085cde657901 251
mbed_official 87:085cde657901 252 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official 87:085cde657901 253 hspi->State = HAL_SPI_STATE_RESET;
mbed_official 87:085cde657901 254
mbed_official 106:ced8cbb51063 255 /* Release Lock */
mbed_official 106:ced8cbb51063 256 __HAL_UNLOCK(hspi);
mbed_official 106:ced8cbb51063 257
mbed_official 87:085cde657901 258 return HAL_OK;
mbed_official 87:085cde657901 259 }
mbed_official 87:085cde657901 260
mbed_official 87:085cde657901 261 /**
mbed_official 87:085cde657901 262 * @brief SPI MSP Init
mbed_official 226:b062af740e40 263 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 264 * the configuration information for SPI module.
mbed_official 87:085cde657901 265 * @retval None
mbed_official 87:085cde657901 266 */
mbed_official 87:085cde657901 267 __weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
mbed_official 87:085cde657901 268 {
mbed_official 87:085cde657901 269 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 532:fe11edbda85c 270 the HAL_SPI_MspInit could be implemented in the user file
mbed_official 87:085cde657901 271 */
mbed_official 87:085cde657901 272 }
mbed_official 87:085cde657901 273
mbed_official 87:085cde657901 274 /**
mbed_official 87:085cde657901 275 * @brief SPI MSP DeInit
mbed_official 226:b062af740e40 276 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 277 * the configuration information for SPI module.
mbed_official 87:085cde657901 278 * @retval None
mbed_official 87:085cde657901 279 */
mbed_official 87:085cde657901 280 __weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
mbed_official 87:085cde657901 281 {
mbed_official 87:085cde657901 282 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 532:fe11edbda85c 283 the HAL_SPI_MspDeInit could be implemented in the user file
mbed_official 87:085cde657901 284 */
mbed_official 87:085cde657901 285 }
mbed_official 87:085cde657901 286
mbed_official 87:085cde657901 287 /**
mbed_official 87:085cde657901 288 * @}
mbed_official 87:085cde657901 289 */
mbed_official 87:085cde657901 290
mbed_official 532:fe11edbda85c 291 /** @defgroup SPI_Exported_Functions_Group2 IO operation functions
mbed_official 87:085cde657901 292 * @brief Data transfers functions
mbed_official 87:085cde657901 293 *
mbed_official 87:085cde657901 294 @verbatim
mbed_official 87:085cde657901 295 ==============================================================================
mbed_official 87:085cde657901 296 ##### IO operation functions #####
mbed_official 87:085cde657901 297 ===============================================================================
mbed_official 87:085cde657901 298 This subsection provides a set of functions allowing to manage the SPI
mbed_official 87:085cde657901 299 data transfers.
mbed_official 87:085cde657901 300
mbed_official 87:085cde657901 301 [..] The SPI supports master and slave mode :
mbed_official 87:085cde657901 302
mbed_official 226:b062af740e40 303 (#) There are two modes of transfer:
mbed_official 87:085cde657901 304 (++) Blocking mode: The communication is performed in polling mode.
mbed_official 87:085cde657901 305 The HAL status of all data processing is returned by the same function
mbed_official 87:085cde657901 306 after finishing transfer.
mbed_official 87:085cde657901 307 (++) No-Blocking mode: The communication is performed using Interrupts
mbed_official 226:b062af740e40 308 or DMA, These APIs return the HAL status.
mbed_official 87:085cde657901 309 The end of the data processing will be indicated through the
mbed_official 87:085cde657901 310 dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
mbed_official 87:085cde657901 311 using DMA mode.
mbed_official 87:085cde657901 312 The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
mbed_official 532:fe11edbda85c 313 will be executed respectively at the end of the transmit or Receive process
mbed_official 87:085cde657901 314 The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected
mbed_official 87:085cde657901 315
mbed_official 532:fe11edbda85c 316 (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA)
mbed_official 532:fe11edbda85c 317 exist for 1Line (simplex) and 2Lines (full duplex) modes.
mbed_official 87:085cde657901 318
mbed_official 87:085cde657901 319 @endverbatim
mbed_official 87:085cde657901 320 * @{
mbed_official 87:085cde657901 321 */
mbed_official 87:085cde657901 322
mbed_official 87:085cde657901 323 /**
mbed_official 87:085cde657901 324 * @brief Transmit an amount of data in blocking mode
mbed_official 226:b062af740e40 325 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 326 * the configuration information for SPI module.
mbed_official 87:085cde657901 327 * @param pData: pointer to data buffer
mbed_official 87:085cde657901 328 * @param Size: amount of data to be sent
mbed_official 87:085cde657901 329 * @param Timeout: Timeout duration
mbed_official 87:085cde657901 330 * @retval HAL status
mbed_official 87:085cde657901 331 */
mbed_official 87:085cde657901 332 HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
mbed_official 87:085cde657901 333 {
mbed_official 87:085cde657901 334
mbed_official 87:085cde657901 335 if(hspi->State == HAL_SPI_STATE_READY)
mbed_official 87:085cde657901 336 {
mbed_official 369:2e96f1b71984 337 if((pData == HAL_NULL ) || (Size == 0))
mbed_official 87:085cde657901 338 {
mbed_official 87:085cde657901 339 return HAL_ERROR;
mbed_official 87:085cde657901 340 }
mbed_official 87:085cde657901 341
mbed_official 87:085cde657901 342 /* Check the parameters */
mbed_official 87:085cde657901 343 assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
mbed_official 87:085cde657901 344
mbed_official 87:085cde657901 345 /* Process Locked */
mbed_official 87:085cde657901 346 __HAL_LOCK(hspi);
mbed_official 87:085cde657901 347
mbed_official 87:085cde657901 348 /* Configure communication */
mbed_official 87:085cde657901 349 hspi->State = HAL_SPI_STATE_BUSY_TX;
mbed_official 87:085cde657901 350 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official 87:085cde657901 351
mbed_official 87:085cde657901 352 hspi->pTxBuffPtr = pData;
mbed_official 87:085cde657901 353 hspi->TxXferSize = Size;
mbed_official 87:085cde657901 354 hspi->TxXferCount = Size;
mbed_official 87:085cde657901 355
mbed_official 87:085cde657901 356 /*Init field not used in handle to zero */
mbed_official 87:085cde657901 357 hspi->TxISR = 0;
mbed_official 87:085cde657901 358 hspi->RxISR = 0;
mbed_official 87:085cde657901 359 hspi->RxXferSize = 0;
mbed_official 87:085cde657901 360 hspi->RxXferCount = 0;
mbed_official 87:085cde657901 361
mbed_official 87:085cde657901 362 /* Reset CRC Calculation */
mbed_official 532:fe11edbda85c 363 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official 87:085cde657901 364 {
mbed_official 532:fe11edbda85c 365 SPI_RESET_CRC(hspi);
mbed_official 87:085cde657901 366 }
mbed_official 87:085cde657901 367
mbed_official 87:085cde657901 368 if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
mbed_official 87:085cde657901 369 {
mbed_official 87:085cde657901 370 /* Configure communication direction : 1Line */
mbed_official 532:fe11edbda85c 371 SPI_1LINE_TX(hspi);
mbed_official 87:085cde657901 372 }
mbed_official 87:085cde657901 373
mbed_official 87:085cde657901 374 /* Check if the SPI is already enabled */
mbed_official 87:085cde657901 375 if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official 87:085cde657901 376 {
mbed_official 87:085cde657901 377 /* Enable SPI peripheral */
mbed_official 87:085cde657901 378 __HAL_SPI_ENABLE(hspi);
mbed_official 87:085cde657901 379 }
mbed_official 87:085cde657901 380
mbed_official 87:085cde657901 381 /* Transmit data in 8 Bit mode */
mbed_official 87:085cde657901 382 if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
mbed_official 87:085cde657901 383 {
mbed_official 369:2e96f1b71984 384 if((hspi->Init.Mode == SPI_MODE_SLAVE)|| (hspi->TxXferCount == 0x01))
mbed_official 369:2e96f1b71984 385 {
mbed_official 369:2e96f1b71984 386 hspi->Instance->DR = (*hspi->pTxBuffPtr++);
mbed_official 369:2e96f1b71984 387 hspi->TxXferCount--;
mbed_official 369:2e96f1b71984 388 }
mbed_official 87:085cde657901 389 while(hspi->TxXferCount > 0)
mbed_official 87:085cde657901 390 {
mbed_official 87:085cde657901 391 /* Wait until TXE flag is set to send data */
mbed_official 87:085cde657901 392 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
mbed_official 87:085cde657901 393 {
mbed_official 87:085cde657901 394 return HAL_TIMEOUT;
mbed_official 87:085cde657901 395 }
mbed_official 87:085cde657901 396 hspi->Instance->DR = (*hspi->pTxBuffPtr++);
mbed_official 87:085cde657901 397 hspi->TxXferCount--;
mbed_official 87:085cde657901 398 }
mbed_official 87:085cde657901 399 /* Enable CRC Transmission */
mbed_official 532:fe11edbda85c 400 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official 87:085cde657901 401 {
mbed_official 87:085cde657901 402 hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
mbed_official 87:085cde657901 403 }
mbed_official 87:085cde657901 404 }
mbed_official 87:085cde657901 405 /* Transmit data in 16 Bit mode */
mbed_official 87:085cde657901 406 else
mbed_official 87:085cde657901 407 {
mbed_official 369:2e96f1b71984 408 if((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01))
mbed_official 369:2e96f1b71984 409 {
mbed_official 369:2e96f1b71984 410 hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr);
mbed_official 369:2e96f1b71984 411 hspi->pTxBuffPtr+=2;
mbed_official 369:2e96f1b71984 412 hspi->TxXferCount--;
mbed_official 369:2e96f1b71984 413 }
mbed_official 87:085cde657901 414 while(hspi->TxXferCount > 0)
mbed_official 87:085cde657901 415 {
mbed_official 87:085cde657901 416 /* Wait until TXE flag is set to send data */
mbed_official 87:085cde657901 417 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
mbed_official 87:085cde657901 418 {
mbed_official 87:085cde657901 419 return HAL_TIMEOUT;
mbed_official 87:085cde657901 420 }
mbed_official 87:085cde657901 421 hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr);
mbed_official 87:085cde657901 422 hspi->pTxBuffPtr+=2;
mbed_official 87:085cde657901 423 hspi->TxXferCount--;
mbed_official 87:085cde657901 424 }
mbed_official 87:085cde657901 425 /* Enable CRC Transmission */
mbed_official 532:fe11edbda85c 426 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official 87:085cde657901 427 {
mbed_official 87:085cde657901 428 hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
mbed_official 87:085cde657901 429 }
mbed_official 87:085cde657901 430 }
mbed_official 87:085cde657901 431
mbed_official 87:085cde657901 432 /* Wait until TXE flag is set to send data */
mbed_official 87:085cde657901 433 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
mbed_official 87:085cde657901 434 {
mbed_official 87:085cde657901 435 hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
mbed_official 87:085cde657901 436 return HAL_TIMEOUT;
mbed_official 87:085cde657901 437 }
mbed_official 87:085cde657901 438
mbed_official 87:085cde657901 439 /* Wait until Busy flag is reset before disabling SPI */
mbed_official 87:085cde657901 440 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, Timeout) != HAL_OK)
mbed_official 87:085cde657901 441 {
mbed_official 87:085cde657901 442 hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
mbed_official 87:085cde657901 443 return HAL_TIMEOUT;
mbed_official 87:085cde657901 444 }
mbed_official 87:085cde657901 445
mbed_official 532:fe11edbda85c 446 /* Clear OVERRUN flag in 2 Lines communication mode because received is not read */
mbed_official 87:085cde657901 447 if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
mbed_official 87:085cde657901 448 {
mbed_official 87:085cde657901 449 __HAL_SPI_CLEAR_OVRFLAG(hspi);
mbed_official 87:085cde657901 450 }
mbed_official 87:085cde657901 451
mbed_official 87:085cde657901 452 hspi->State = HAL_SPI_STATE_READY;
mbed_official 87:085cde657901 453
mbed_official 87:085cde657901 454 /* Process Unlocked */
mbed_official 87:085cde657901 455 __HAL_UNLOCK(hspi);
mbed_official 87:085cde657901 456
mbed_official 87:085cde657901 457 return HAL_OK;
mbed_official 87:085cde657901 458 }
mbed_official 87:085cde657901 459 else
mbed_official 87:085cde657901 460 {
mbed_official 87:085cde657901 461 return HAL_BUSY;
mbed_official 87:085cde657901 462 }
mbed_official 87:085cde657901 463 }
mbed_official 87:085cde657901 464
mbed_official 87:085cde657901 465 /**
mbed_official 87:085cde657901 466 * @brief Receive an amount of data in blocking mode
mbed_official 226:b062af740e40 467 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 468 * the configuration information for SPI module.
mbed_official 87:085cde657901 469 * @param pData: pointer to data buffer
mbed_official 87:085cde657901 470 * @param Size: amount of data to be sent
mbed_official 87:085cde657901 471 * @param Timeout: Timeout duration
mbed_official 87:085cde657901 472 * @retval HAL status
mbed_official 87:085cde657901 473 */
mbed_official 87:085cde657901 474 HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
mbed_official 87:085cde657901 475 {
mbed_official 87:085cde657901 476 __IO uint16_t tmpreg;
mbed_official 87:085cde657901 477 uint32_t tmp = 0;
mbed_official 87:085cde657901 478
mbed_official 87:085cde657901 479 if(hspi->State == HAL_SPI_STATE_READY)
mbed_official 87:085cde657901 480 {
mbed_official 369:2e96f1b71984 481 if((pData == HAL_NULL ) || (Size == 0))
mbed_official 87:085cde657901 482 {
mbed_official 87:085cde657901 483 return HAL_ERROR;
mbed_official 87:085cde657901 484 }
mbed_official 87:085cde657901 485
mbed_official 87:085cde657901 486 /* Process Locked */
mbed_official 87:085cde657901 487 __HAL_LOCK(hspi);
mbed_official 87:085cde657901 488
mbed_official 87:085cde657901 489 /* Configure communication */
mbed_official 87:085cde657901 490 hspi->State = HAL_SPI_STATE_BUSY_RX;
mbed_official 87:085cde657901 491 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official 87:085cde657901 492
mbed_official 87:085cde657901 493 hspi->pRxBuffPtr = pData;
mbed_official 87:085cde657901 494 hspi->RxXferSize = Size;
mbed_official 87:085cde657901 495 hspi->RxXferCount = Size;
mbed_official 87:085cde657901 496
mbed_official 87:085cde657901 497 /*Init field not used in handle to zero */
mbed_official 87:085cde657901 498 hspi->RxISR = 0;
mbed_official 87:085cde657901 499 hspi->TxISR = 0;
mbed_official 87:085cde657901 500 hspi->TxXferSize = 0;
mbed_official 87:085cde657901 501 hspi->TxXferCount = 0;
mbed_official 87:085cde657901 502
mbed_official 87:085cde657901 503 /* Configure communication direction : 1Line */
mbed_official 87:085cde657901 504 if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
mbed_official 87:085cde657901 505 {
mbed_official 532:fe11edbda85c 506 SPI_1LINE_RX(hspi);
mbed_official 87:085cde657901 507 }
mbed_official 87:085cde657901 508
mbed_official 87:085cde657901 509 /* Reset CRC Calculation */
mbed_official 532:fe11edbda85c 510 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official 87:085cde657901 511 {
mbed_official 532:fe11edbda85c 512 SPI_RESET_CRC(hspi);
mbed_official 87:085cde657901 513 }
mbed_official 87:085cde657901 514
mbed_official 87:085cde657901 515 if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
mbed_official 87:085cde657901 516 {
mbed_official 87:085cde657901 517 /* Process Unlocked */
mbed_official 87:085cde657901 518 __HAL_UNLOCK(hspi);
mbed_official 87:085cde657901 519
mbed_official 87:085cde657901 520 /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
mbed_official 87:085cde657901 521 return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout);
mbed_official 87:085cde657901 522 }
mbed_official 87:085cde657901 523
mbed_official 87:085cde657901 524 /* Check if the SPI is already enabled */
mbed_official 87:085cde657901 525 if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official 87:085cde657901 526 {
mbed_official 87:085cde657901 527 /* Enable SPI peripheral */
mbed_official 87:085cde657901 528 __HAL_SPI_ENABLE(hspi);
mbed_official 87:085cde657901 529 }
mbed_official 87:085cde657901 530
mbed_official 87:085cde657901 531 /* Receive data in 8 Bit mode */
mbed_official 87:085cde657901 532 if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
mbed_official 87:085cde657901 533 {
mbed_official 87:085cde657901 534 while(hspi->RxXferCount > 1)
mbed_official 87:085cde657901 535 {
mbed_official 87:085cde657901 536 /* Wait until RXNE flag is set */
mbed_official 87:085cde657901 537 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
mbed_official 87:085cde657901 538 {
mbed_official 87:085cde657901 539 return HAL_TIMEOUT;
mbed_official 87:085cde657901 540 }
mbed_official 87:085cde657901 541
mbed_official 87:085cde657901 542 (*hspi->pRxBuffPtr++) = hspi->Instance->DR;
mbed_official 87:085cde657901 543 hspi->RxXferCount--;
mbed_official 87:085cde657901 544 }
mbed_official 87:085cde657901 545 /* Enable CRC Transmission */
mbed_official 532:fe11edbda85c 546 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official 87:085cde657901 547 {
mbed_official 87:085cde657901 548 hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
mbed_official 87:085cde657901 549 }
mbed_official 87:085cde657901 550 }
mbed_official 87:085cde657901 551 /* Receive data in 16 Bit mode */
mbed_official 87:085cde657901 552 else
mbed_official 87:085cde657901 553 {
mbed_official 87:085cde657901 554 while(hspi->RxXferCount > 1)
mbed_official 87:085cde657901 555 {
mbed_official 87:085cde657901 556 /* Wait until RXNE flag is set to read data */
mbed_official 87:085cde657901 557 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
mbed_official 87:085cde657901 558 {
mbed_official 87:085cde657901 559 return HAL_TIMEOUT;
mbed_official 87:085cde657901 560 }
mbed_official 87:085cde657901 561
mbed_official 87:085cde657901 562 *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
mbed_official 87:085cde657901 563 hspi->pRxBuffPtr+=2;
mbed_official 87:085cde657901 564 hspi->RxXferCount--;
mbed_official 87:085cde657901 565 }
mbed_official 87:085cde657901 566 /* Enable CRC Transmission */
mbed_official 532:fe11edbda85c 567 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official 87:085cde657901 568 {
mbed_official 87:085cde657901 569 hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
mbed_official 87:085cde657901 570 }
mbed_official 87:085cde657901 571 }
mbed_official 87:085cde657901 572
mbed_official 87:085cde657901 573 /* Wait until RXNE flag is set */
mbed_official 87:085cde657901 574 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
mbed_official 87:085cde657901 575 {
mbed_official 87:085cde657901 576 return HAL_TIMEOUT;
mbed_official 87:085cde657901 577 }
mbed_official 87:085cde657901 578
mbed_official 87:085cde657901 579 /* Receive last data in 8 Bit mode */
mbed_official 87:085cde657901 580 if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
mbed_official 87:085cde657901 581 {
mbed_official 87:085cde657901 582 (*hspi->pRxBuffPtr++) = hspi->Instance->DR;
mbed_official 87:085cde657901 583 }
mbed_official 87:085cde657901 584 /* Receive last data in 16 Bit mode */
mbed_official 87:085cde657901 585 else
mbed_official 87:085cde657901 586 {
mbed_official 87:085cde657901 587 *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
mbed_official 87:085cde657901 588 hspi->pRxBuffPtr+=2;
mbed_official 87:085cde657901 589 }
mbed_official 87:085cde657901 590 hspi->RxXferCount--;
mbed_official 87:085cde657901 591
mbed_official 87:085cde657901 592 /* Wait until RXNE flag is set: CRC Received */
mbed_official 532:fe11edbda85c 593 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official 87:085cde657901 594 {
mbed_official 87:085cde657901 595 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
mbed_official 87:085cde657901 596 {
mbed_official 87:085cde657901 597 hspi->ErrorCode |= HAL_SPI_ERROR_CRC;
mbed_official 87:085cde657901 598 return HAL_TIMEOUT;
mbed_official 87:085cde657901 599 }
mbed_official 87:085cde657901 600
mbed_official 87:085cde657901 601 /* Read CRC to Flush RXNE flag */
mbed_official 87:085cde657901 602 tmpreg = hspi->Instance->DR;
mbed_official 532:fe11edbda85c 603 UNUSED(tmpreg);
mbed_official 87:085cde657901 604 }
mbed_official 87:085cde657901 605
mbed_official 87:085cde657901 606 if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
mbed_official 87:085cde657901 607 {
mbed_official 87:085cde657901 608 /* Disable SPI peripheral */
mbed_official 87:085cde657901 609 __HAL_SPI_DISABLE(hspi);
mbed_official 87:085cde657901 610 }
mbed_official 87:085cde657901 611
mbed_official 87:085cde657901 612 hspi->State = HAL_SPI_STATE_READY;
mbed_official 87:085cde657901 613
mbed_official 87:085cde657901 614 tmp = __HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR);
mbed_official 87:085cde657901 615 /* Check if CRC error occurred */
mbed_official 532:fe11edbda85c 616 if((hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) && (tmp != RESET))
mbed_official 87:085cde657901 617 {
mbed_official 87:085cde657901 618 hspi->ErrorCode |= HAL_SPI_ERROR_CRC;
mbed_official 87:085cde657901 619
mbed_official 87:085cde657901 620 /* Reset CRC Calculation */
mbed_official 532:fe11edbda85c 621 SPI_RESET_CRC(hspi);
mbed_official 87:085cde657901 622
mbed_official 87:085cde657901 623 /* Process Unlocked */
mbed_official 87:085cde657901 624 __HAL_UNLOCK(hspi);
mbed_official 87:085cde657901 625
mbed_official 87:085cde657901 626 return HAL_ERROR;
mbed_official 87:085cde657901 627 }
mbed_official 87:085cde657901 628
mbed_official 87:085cde657901 629 /* Process Unlocked */
mbed_official 87:085cde657901 630 __HAL_UNLOCK(hspi);
mbed_official 87:085cde657901 631
mbed_official 87:085cde657901 632 return HAL_OK;
mbed_official 87:085cde657901 633 }
mbed_official 87:085cde657901 634 else
mbed_official 87:085cde657901 635 {
mbed_official 87:085cde657901 636 return HAL_BUSY;
mbed_official 87:085cde657901 637 }
mbed_official 87:085cde657901 638 }
mbed_official 87:085cde657901 639
mbed_official 87:085cde657901 640 /**
mbed_official 87:085cde657901 641 * @brief Transmit and Receive an amount of data in blocking mode
mbed_official 226:b062af740e40 642 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 643 * the configuration information for SPI module.
mbed_official 87:085cde657901 644 * @param pTxData: pointer to transmission data buffer
mbed_official 87:085cde657901 645 * @param pRxData: pointer to reception data buffer to be
mbed_official 87:085cde657901 646 * @param Size: amount of data to be sent
mbed_official 87:085cde657901 647 * @param Timeout: Timeout duration
mbed_official 87:085cde657901 648 * @retval HAL status
mbed_official 87:085cde657901 649 */
mbed_official 87:085cde657901 650 HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
mbed_official 87:085cde657901 651 {
mbed_official 87:085cde657901 652 __IO uint16_t tmpreg;
mbed_official 369:2e96f1b71984 653 uint32_t tmpstate = 0, tmp = 0;
mbed_official 87:085cde657901 654
mbed_official 369:2e96f1b71984 655 tmpstate = hspi->State;
mbed_official 369:2e96f1b71984 656 if((tmpstate == HAL_SPI_STATE_READY) || (tmpstate == HAL_SPI_STATE_BUSY_RX))
mbed_official 87:085cde657901 657 {
mbed_official 369:2e96f1b71984 658 if((pTxData == HAL_NULL ) || (pRxData == HAL_NULL ) || (Size == 0))
mbed_official 87:085cde657901 659 {
mbed_official 87:085cde657901 660 return HAL_ERROR;
mbed_official 87:085cde657901 661 }
mbed_official 87:085cde657901 662
mbed_official 87:085cde657901 663 /* Check the parameters */
mbed_official 87:085cde657901 664 assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
mbed_official 87:085cde657901 665
mbed_official 87:085cde657901 666 /* Process Locked */
mbed_official 87:085cde657901 667 __HAL_LOCK(hspi);
mbed_official 87:085cde657901 668
mbed_official 87:085cde657901 669 /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
mbed_official 87:085cde657901 670 if(hspi->State == HAL_SPI_STATE_READY)
mbed_official 87:085cde657901 671 {
mbed_official 106:ced8cbb51063 672 hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
mbed_official 87:085cde657901 673 }
mbed_official 87:085cde657901 674
mbed_official 87:085cde657901 675 /* Configure communication */
mbed_official 87:085cde657901 676 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official 87:085cde657901 677
mbed_official 87:085cde657901 678 hspi->pRxBuffPtr = pRxData;
mbed_official 87:085cde657901 679 hspi->RxXferSize = Size;
mbed_official 87:085cde657901 680 hspi->RxXferCount = Size;
mbed_official 87:085cde657901 681
mbed_official 87:085cde657901 682 hspi->pTxBuffPtr = pTxData;
mbed_official 87:085cde657901 683 hspi->TxXferSize = Size;
mbed_official 87:085cde657901 684 hspi->TxXferCount = Size;
mbed_official 87:085cde657901 685
mbed_official 87:085cde657901 686 /*Init field not used in handle to zero */
mbed_official 87:085cde657901 687 hspi->RxISR = 0;
mbed_official 87:085cde657901 688 hspi->TxISR = 0;
mbed_official 87:085cde657901 689
mbed_official 87:085cde657901 690 /* Reset CRC Calculation */
mbed_official 532:fe11edbda85c 691 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official 87:085cde657901 692 {
mbed_official 532:fe11edbda85c 693 SPI_RESET_CRC(hspi);
mbed_official 87:085cde657901 694 }
mbed_official 87:085cde657901 695
mbed_official 87:085cde657901 696 /* Check if the SPI is already enabled */
mbed_official 87:085cde657901 697 if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official 87:085cde657901 698 {
mbed_official 87:085cde657901 699 /* Enable SPI peripheral */
mbed_official 87:085cde657901 700 __HAL_SPI_ENABLE(hspi);
mbed_official 87:085cde657901 701 }
mbed_official 87:085cde657901 702
mbed_official 87:085cde657901 703 /* Transmit and Receive data in 16 Bit mode */
mbed_official 87:085cde657901 704 if(hspi->Init.DataSize == SPI_DATASIZE_16BIT)
mbed_official 87:085cde657901 705 {
mbed_official 369:2e96f1b71984 706 if((hspi->Init.Mode == SPI_MODE_SLAVE) || ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->TxXferCount == 0x01)))
mbed_official 369:2e96f1b71984 707 {
mbed_official 369:2e96f1b71984 708 hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr);
mbed_official 369:2e96f1b71984 709 hspi->pTxBuffPtr+=2;
mbed_official 369:2e96f1b71984 710 hspi->TxXferCount--;
mbed_official 369:2e96f1b71984 711 }
mbed_official 87:085cde657901 712 if(hspi->TxXferCount == 0)
mbed_official 87:085cde657901 713 {
mbed_official 87:085cde657901 714 /* Enable CRC Transmission */
mbed_official 532:fe11edbda85c 715 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official 87:085cde657901 716 {
mbed_official 87:085cde657901 717 hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
mbed_official 87:085cde657901 718 }
mbed_official 87:085cde657901 719
mbed_official 87:085cde657901 720 /* Wait until RXNE flag is set */
mbed_official 87:085cde657901 721 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
mbed_official 87:085cde657901 722 {
mbed_official 87:085cde657901 723 return HAL_TIMEOUT;
mbed_official 87:085cde657901 724 }
mbed_official 87:085cde657901 725
mbed_official 87:085cde657901 726 *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
mbed_official 87:085cde657901 727 hspi->pRxBuffPtr+=2;
mbed_official 87:085cde657901 728 hspi->RxXferCount--;
mbed_official 87:085cde657901 729 }
mbed_official 87:085cde657901 730 else
mbed_official 87:085cde657901 731 {
mbed_official 87:085cde657901 732 while(hspi->TxXferCount > 0)
mbed_official 87:085cde657901 733 {
mbed_official 87:085cde657901 734 /* Wait until TXE flag is set to send data */
mbed_official 87:085cde657901 735 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
mbed_official 87:085cde657901 736 {
mbed_official 87:085cde657901 737 return HAL_TIMEOUT;
mbed_official 87:085cde657901 738 }
mbed_official 87:085cde657901 739
mbed_official 87:085cde657901 740 hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr);
mbed_official 87:085cde657901 741 hspi->pTxBuffPtr+=2;
mbed_official 87:085cde657901 742 hspi->TxXferCount--;
mbed_official 87:085cde657901 743
mbed_official 87:085cde657901 744 /* Enable CRC Transmission */
mbed_official 532:fe11edbda85c 745 if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
mbed_official 87:085cde657901 746 {
mbed_official 87:085cde657901 747 hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
mbed_official 87:085cde657901 748 }
mbed_official 87:085cde657901 749
mbed_official 87:085cde657901 750 /* Wait until RXNE flag is set */
mbed_official 87:085cde657901 751 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
mbed_official 87:085cde657901 752 {
mbed_official 87:085cde657901 753 return HAL_TIMEOUT;
mbed_official 87:085cde657901 754 }
mbed_official 369:2e96f1b71984 755
mbed_official 87:085cde657901 756 *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
mbed_official 87:085cde657901 757 hspi->pRxBuffPtr+=2;
mbed_official 87:085cde657901 758 hspi->RxXferCount--;
mbed_official 87:085cde657901 759 }
mbed_official 369:2e96f1b71984 760 /* Receive the last byte */
mbed_official 369:2e96f1b71984 761 if(hspi->Init.Mode == SPI_MODE_SLAVE)
mbed_official 87:085cde657901 762 {
mbed_official 369:2e96f1b71984 763 /* Wait until RXNE flag is set */
mbed_official 369:2e96f1b71984 764 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
mbed_official 369:2e96f1b71984 765 {
mbed_official 369:2e96f1b71984 766 return HAL_TIMEOUT;
mbed_official 369:2e96f1b71984 767 }
mbed_official 369:2e96f1b71984 768
mbed_official 369:2e96f1b71984 769 *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
mbed_official 369:2e96f1b71984 770 hspi->pRxBuffPtr+=2;
mbed_official 369:2e96f1b71984 771 hspi->RxXferCount--;
mbed_official 87:085cde657901 772 }
mbed_official 87:085cde657901 773 }
mbed_official 87:085cde657901 774 }
mbed_official 87:085cde657901 775 /* Transmit and Receive data in 8 Bit mode */
mbed_official 87:085cde657901 776 else
mbed_official 87:085cde657901 777 {
mbed_official 369:2e96f1b71984 778 if((hspi->Init.Mode == SPI_MODE_SLAVE) || ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->TxXferCount == 0x01)))
mbed_official 369:2e96f1b71984 779 {
mbed_official 369:2e96f1b71984 780 hspi->Instance->DR = (*hspi->pTxBuffPtr++);
mbed_official 369:2e96f1b71984 781 hspi->TxXferCount--;
mbed_official 369:2e96f1b71984 782 }
mbed_official 87:085cde657901 783 if(hspi->TxXferCount == 0)
mbed_official 87:085cde657901 784 {
mbed_official 87:085cde657901 785 /* Enable CRC Transmission */
mbed_official 532:fe11edbda85c 786 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official 87:085cde657901 787 {
mbed_official 87:085cde657901 788 hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
mbed_official 87:085cde657901 789 }
mbed_official 87:085cde657901 790
mbed_official 87:085cde657901 791 /* Wait until RXNE flag is set */
mbed_official 87:085cde657901 792 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
mbed_official 87:085cde657901 793 {
mbed_official 87:085cde657901 794 return HAL_TIMEOUT;
mbed_official 87:085cde657901 795 }
mbed_official 87:085cde657901 796
mbed_official 87:085cde657901 797 (*hspi->pRxBuffPtr) = hspi->Instance->DR;
mbed_official 87:085cde657901 798 hspi->RxXferCount--;
mbed_official 87:085cde657901 799 }
mbed_official 87:085cde657901 800 else
mbed_official 87:085cde657901 801 {
mbed_official 87:085cde657901 802 while(hspi->TxXferCount > 0)
mbed_official 87:085cde657901 803 {
mbed_official 87:085cde657901 804 /* Wait until TXE flag is set to send data */
mbed_official 87:085cde657901 805 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
mbed_official 87:085cde657901 806 {
mbed_official 87:085cde657901 807 return HAL_TIMEOUT;
mbed_official 87:085cde657901 808 }
mbed_official 87:085cde657901 809
mbed_official 87:085cde657901 810 hspi->Instance->DR = (*hspi->pTxBuffPtr++);
mbed_official 87:085cde657901 811 hspi->TxXferCount--;
mbed_official 87:085cde657901 812
mbed_official 87:085cde657901 813 /* Enable CRC Transmission */
mbed_official 532:fe11edbda85c 814 if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
mbed_official 87:085cde657901 815 {
mbed_official 87:085cde657901 816 hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
mbed_official 87:085cde657901 817 }
mbed_official 87:085cde657901 818
mbed_official 369:2e96f1b71984 819 /* Wait until RXNE flag is set */
mbed_official 369:2e96f1b71984 820 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
mbed_official 369:2e96f1b71984 821 {
mbed_official 369:2e96f1b71984 822 return HAL_TIMEOUT;
mbed_official 369:2e96f1b71984 823 }
mbed_official 369:2e96f1b71984 824
mbed_official 369:2e96f1b71984 825 (*hspi->pRxBuffPtr++) = hspi->Instance->DR;
mbed_official 369:2e96f1b71984 826 hspi->RxXferCount--;
mbed_official 369:2e96f1b71984 827 }
mbed_official 369:2e96f1b71984 828 if(hspi->Init.Mode == SPI_MODE_SLAVE)
mbed_official 369:2e96f1b71984 829 {
mbed_official 87:085cde657901 830 /* Wait until RXNE flag is set */
mbed_official 87:085cde657901 831 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
mbed_official 87:085cde657901 832 {
mbed_official 87:085cde657901 833 return HAL_TIMEOUT;
mbed_official 87:085cde657901 834 }
mbed_official 369:2e96f1b71984 835
mbed_official 87:085cde657901 836 (*hspi->pRxBuffPtr++) = hspi->Instance->DR;
mbed_official 87:085cde657901 837 hspi->RxXferCount--;
mbed_official 87:085cde657901 838 }
mbed_official 87:085cde657901 839 }
mbed_official 87:085cde657901 840 }
mbed_official 87:085cde657901 841
mbed_official 87:085cde657901 842 /* Read CRC from DR to close CRC calculation process */
mbed_official 532:fe11edbda85c 843 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official 87:085cde657901 844 {
mbed_official 87:085cde657901 845 /* Wait until RXNE flag is set */
mbed_official 87:085cde657901 846 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
mbed_official 87:085cde657901 847 {
mbed_official 87:085cde657901 848 hspi->ErrorCode |= HAL_SPI_ERROR_CRC;
mbed_official 87:085cde657901 849 return HAL_TIMEOUT;
mbed_official 87:085cde657901 850 }
mbed_official 87:085cde657901 851 /* Read CRC */
mbed_official 87:085cde657901 852 tmpreg = hspi->Instance->DR;
mbed_official 532:fe11edbda85c 853 UNUSED(tmpreg);
mbed_official 87:085cde657901 854 }
mbed_official 87:085cde657901 855
mbed_official 87:085cde657901 856 /* Wait until Busy flag is reset before disabling SPI */
mbed_official 87:085cde657901 857 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, Timeout) != HAL_OK)
mbed_official 87:085cde657901 858 {
mbed_official 87:085cde657901 859 hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
mbed_official 87:085cde657901 860 return HAL_TIMEOUT;
mbed_official 87:085cde657901 861 }
mbed_official 87:085cde657901 862
mbed_official 87:085cde657901 863 hspi->State = HAL_SPI_STATE_READY;
mbed_official 87:085cde657901 864
mbed_official 87:085cde657901 865 tmp = __HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR);
mbed_official 87:085cde657901 866 /* Check if CRC error occurred */
mbed_official 532:fe11edbda85c 867 if((hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) && (tmp != RESET))
mbed_official 87:085cde657901 868 {
mbed_official 87:085cde657901 869 hspi->ErrorCode |= HAL_SPI_ERROR_CRC;
mbed_official 87:085cde657901 870
mbed_official 87:085cde657901 871 /* Reset CRC Calculation */
mbed_official 532:fe11edbda85c 872 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official 87:085cde657901 873 {
mbed_official 532:fe11edbda85c 874 SPI_RESET_CRC(hspi);
mbed_official 87:085cde657901 875 }
mbed_official 87:085cde657901 876
mbed_official 87:085cde657901 877 /* Process Unlocked */
mbed_official 87:085cde657901 878 __HAL_UNLOCK(hspi);
mbed_official 87:085cde657901 879
mbed_official 87:085cde657901 880 return HAL_ERROR;
mbed_official 87:085cde657901 881 }
mbed_official 87:085cde657901 882
mbed_official 87:085cde657901 883 /* Process Unlocked */
mbed_official 87:085cde657901 884 __HAL_UNLOCK(hspi);
mbed_official 87:085cde657901 885
mbed_official 87:085cde657901 886 return HAL_OK;
mbed_official 87:085cde657901 887 }
mbed_official 87:085cde657901 888 else
mbed_official 87:085cde657901 889 {
mbed_official 87:085cde657901 890 return HAL_BUSY;
mbed_official 87:085cde657901 891 }
mbed_official 87:085cde657901 892 }
mbed_official 87:085cde657901 893
mbed_official 87:085cde657901 894 /**
mbed_official 87:085cde657901 895 * @brief Transmit an amount of data in no-blocking mode with Interrupt
mbed_official 226:b062af740e40 896 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 897 * the configuration information for SPI module.
mbed_official 87:085cde657901 898 * @param pData: pointer to data buffer
mbed_official 87:085cde657901 899 * @param Size: amount of data to be sent
mbed_official 87:085cde657901 900 * @retval HAL status
mbed_official 87:085cde657901 901 */
mbed_official 87:085cde657901 902 HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
mbed_official 87:085cde657901 903 {
mbed_official 87:085cde657901 904 if(hspi->State == HAL_SPI_STATE_READY)
mbed_official 87:085cde657901 905 {
mbed_official 369:2e96f1b71984 906 if((pData == HAL_NULL) || (Size == 0))
mbed_official 87:085cde657901 907 {
mbed_official 87:085cde657901 908 return HAL_ERROR;
mbed_official 87:085cde657901 909 }
mbed_official 87:085cde657901 910
mbed_official 87:085cde657901 911 /* Check the parameters */
mbed_official 87:085cde657901 912 assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
mbed_official 87:085cde657901 913
mbed_official 87:085cde657901 914 /* Process Locked */
mbed_official 87:085cde657901 915 __HAL_LOCK(hspi);
mbed_official 87:085cde657901 916
mbed_official 87:085cde657901 917 /* Configure communication */
mbed_official 87:085cde657901 918 hspi->State = HAL_SPI_STATE_BUSY_TX;
mbed_official 87:085cde657901 919 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official 87:085cde657901 920
mbed_official 87:085cde657901 921 hspi->TxISR = &SPI_TxISR;
mbed_official 87:085cde657901 922 hspi->pTxBuffPtr = pData;
mbed_official 87:085cde657901 923 hspi->TxXferSize = Size;
mbed_official 87:085cde657901 924 hspi->TxXferCount = Size;
mbed_official 87:085cde657901 925
mbed_official 87:085cde657901 926 /*Init field not used in handle to zero */
mbed_official 87:085cde657901 927 hspi->RxISR = 0;
mbed_official 87:085cde657901 928 hspi->RxXferSize = 0;
mbed_official 87:085cde657901 929 hspi->RxXferCount = 0;
mbed_official 87:085cde657901 930
mbed_official 87:085cde657901 931 /* Configure communication direction : 1Line */
mbed_official 87:085cde657901 932 if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
mbed_official 87:085cde657901 933 {
mbed_official 532:fe11edbda85c 934 SPI_1LINE_TX(hspi);
mbed_official 87:085cde657901 935 }
mbed_official 87:085cde657901 936
mbed_official 87:085cde657901 937 /* Reset CRC Calculation */
mbed_official 532:fe11edbda85c 938 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official 87:085cde657901 939 {
mbed_official 532:fe11edbda85c 940 SPI_RESET_CRC(hspi);
mbed_official 87:085cde657901 941 }
mbed_official 87:085cde657901 942
mbed_official 87:085cde657901 943 if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
mbed_official 87:085cde657901 944 {
mbed_official 87:085cde657901 945 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE));
mbed_official 87:085cde657901 946 }else
mbed_official 87:085cde657901 947 {
mbed_official 87:085cde657901 948 /* Enable TXE and ERR interrupt */
mbed_official 87:085cde657901 949 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
mbed_official 87:085cde657901 950 }
mbed_official 87:085cde657901 951 /* Process Unlocked */
mbed_official 87:085cde657901 952 __HAL_UNLOCK(hspi);
mbed_official 87:085cde657901 953
mbed_official 87:085cde657901 954 /* Check if the SPI is already enabled */
mbed_official 87:085cde657901 955 if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official 87:085cde657901 956 {
mbed_official 87:085cde657901 957 /* Enable SPI peripheral */
mbed_official 87:085cde657901 958 __HAL_SPI_ENABLE(hspi);
mbed_official 87:085cde657901 959 }
mbed_official 87:085cde657901 960
mbed_official 87:085cde657901 961 return HAL_OK;
mbed_official 87:085cde657901 962 }
mbed_official 87:085cde657901 963 else
mbed_official 87:085cde657901 964 {
mbed_official 87:085cde657901 965 return HAL_BUSY;
mbed_official 87:085cde657901 966 }
mbed_official 87:085cde657901 967 }
mbed_official 87:085cde657901 968
mbed_official 87:085cde657901 969 /**
mbed_official 87:085cde657901 970 * @brief Receive an amount of data in no-blocking mode with Interrupt
mbed_official 226:b062af740e40 971 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 972 * the configuration information for SPI module.
mbed_official 87:085cde657901 973 * @param pData: pointer to data buffer
mbed_official 87:085cde657901 974 * @param Size: amount of data to be sent
mbed_official 87:085cde657901 975 * @retval HAL status
mbed_official 87:085cde657901 976 */
mbed_official 87:085cde657901 977 HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
mbed_official 87:085cde657901 978 {
mbed_official 87:085cde657901 979 if(hspi->State == HAL_SPI_STATE_READY)
mbed_official 87:085cde657901 980 {
mbed_official 369:2e96f1b71984 981 if((pData == HAL_NULL) || (Size == 0))
mbed_official 87:085cde657901 982 {
mbed_official 87:085cde657901 983 return HAL_ERROR;
mbed_official 87:085cde657901 984 }
mbed_official 87:085cde657901 985
mbed_official 87:085cde657901 986 /* Process Locked */
mbed_official 87:085cde657901 987 __HAL_LOCK(hspi);
mbed_official 87:085cde657901 988
mbed_official 87:085cde657901 989 /* Configure communication */
mbed_official 87:085cde657901 990 hspi->State = HAL_SPI_STATE_BUSY_RX;
mbed_official 87:085cde657901 991 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official 87:085cde657901 992
mbed_official 87:085cde657901 993 hspi->RxISR = &SPI_RxISR;
mbed_official 87:085cde657901 994 hspi->pRxBuffPtr = pData;
mbed_official 87:085cde657901 995 hspi->RxXferSize = Size;
mbed_official 87:085cde657901 996 hspi->RxXferCount = Size ;
mbed_official 87:085cde657901 997
mbed_official 87:085cde657901 998 /*Init field not used in handle to zero */
mbed_official 87:085cde657901 999 hspi->TxISR = 0;
mbed_official 87:085cde657901 1000 hspi->TxXferSize = 0;
mbed_official 87:085cde657901 1001 hspi->TxXferCount = 0;
mbed_official 87:085cde657901 1002
mbed_official 87:085cde657901 1003 /* Configure communication direction : 1Line */
mbed_official 87:085cde657901 1004 if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
mbed_official 87:085cde657901 1005 {
mbed_official 532:fe11edbda85c 1006 SPI_1LINE_RX(hspi);
mbed_official 87:085cde657901 1007 }
mbed_official 87:085cde657901 1008 else if((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
mbed_official 87:085cde657901 1009 {
mbed_official 87:085cde657901 1010 /* Process Unlocked */
mbed_official 87:085cde657901 1011 __HAL_UNLOCK(hspi);
mbed_official 87:085cde657901 1012
mbed_official 87:085cde657901 1013 /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
mbed_official 87:085cde657901 1014 return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size);
mbed_official 87:085cde657901 1015 }
mbed_official 87:085cde657901 1016
mbed_official 87:085cde657901 1017 /* Reset CRC Calculation */
mbed_official 532:fe11edbda85c 1018 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official 87:085cde657901 1019 {
mbed_official 532:fe11edbda85c 1020 SPI_RESET_CRC(hspi);
mbed_official 87:085cde657901 1021 }
mbed_official 87:085cde657901 1022
mbed_official 87:085cde657901 1023 /* Enable TXE and ERR interrupt */
mbed_official 87:085cde657901 1024 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
mbed_official 87:085cde657901 1025
mbed_official 87:085cde657901 1026 /* Process Unlocked */
mbed_official 87:085cde657901 1027 __HAL_UNLOCK(hspi);
mbed_official 87:085cde657901 1028
mbed_official 87:085cde657901 1029 /* Note : The SPI must be enabled after unlocking current process
mbed_official 87:085cde657901 1030 to avoid the risk of SPI interrupt handle execution before current
mbed_official 87:085cde657901 1031 process unlock */
mbed_official 87:085cde657901 1032
mbed_official 87:085cde657901 1033 /* Check if the SPI is already enabled */
mbed_official 87:085cde657901 1034 if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official 87:085cde657901 1035 {
mbed_official 87:085cde657901 1036 /* Enable SPI peripheral */
mbed_official 87:085cde657901 1037 __HAL_SPI_ENABLE(hspi);
mbed_official 87:085cde657901 1038 }
mbed_official 87:085cde657901 1039
mbed_official 87:085cde657901 1040 return HAL_OK;
mbed_official 87:085cde657901 1041 }
mbed_official 87:085cde657901 1042 else
mbed_official 87:085cde657901 1043 {
mbed_official 87:085cde657901 1044 return HAL_BUSY;
mbed_official 87:085cde657901 1045 }
mbed_official 87:085cde657901 1046 }
mbed_official 87:085cde657901 1047
mbed_official 87:085cde657901 1048 /**
mbed_official 87:085cde657901 1049 * @brief Transmit and Receive an amount of data in no-blocking mode with Interrupt
mbed_official 226:b062af740e40 1050 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 1051 * the configuration information for SPI module.
mbed_official 87:085cde657901 1052 * @param pTxData: pointer to transmission data buffer
mbed_official 87:085cde657901 1053 * @param pRxData: pointer to reception data buffer to be
mbed_official 87:085cde657901 1054 * @param Size: amount of data to be sent
mbed_official 87:085cde657901 1055 * @retval HAL status
mbed_official 87:085cde657901 1056 */
mbed_official 87:085cde657901 1057 HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
mbed_official 87:085cde657901 1058 {
mbed_official 369:2e96f1b71984 1059 uint32_t tmpstate = 0;
mbed_official 87:085cde657901 1060
mbed_official 369:2e96f1b71984 1061 tmpstate = hspi->State;
mbed_official 369:2e96f1b71984 1062 if((tmpstate == HAL_SPI_STATE_READY) || \
mbed_official 369:2e96f1b71984 1063 ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmpstate == HAL_SPI_STATE_BUSY_RX)))
mbed_official 87:085cde657901 1064 {
mbed_official 369:2e96f1b71984 1065 if((pTxData == HAL_NULL ) || (pRxData == HAL_NULL ) || (Size == 0))
mbed_official 87:085cde657901 1066 {
mbed_official 87:085cde657901 1067 return HAL_ERROR;
mbed_official 87:085cde657901 1068 }
mbed_official 87:085cde657901 1069
mbed_official 87:085cde657901 1070 /* Check the parameters */
mbed_official 87:085cde657901 1071 assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
mbed_official 87:085cde657901 1072
mbed_official 87:085cde657901 1073 /* Process locked */
mbed_official 87:085cde657901 1074 __HAL_LOCK(hspi);
mbed_official 87:085cde657901 1075
mbed_official 87:085cde657901 1076 /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
mbed_official 369:2e96f1b71984 1077 if(hspi->State != HAL_SPI_STATE_BUSY_RX)
mbed_official 87:085cde657901 1078 {
mbed_official 106:ced8cbb51063 1079 hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
mbed_official 87:085cde657901 1080 }
mbed_official 87:085cde657901 1081
mbed_official 87:085cde657901 1082 /* Configure communication */
mbed_official 87:085cde657901 1083 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official 87:085cde657901 1084
mbed_official 87:085cde657901 1085 hspi->TxISR = &SPI_TxISR;
mbed_official 87:085cde657901 1086 hspi->pTxBuffPtr = pTxData;
mbed_official 87:085cde657901 1087 hspi->TxXferSize = Size;
mbed_official 87:085cde657901 1088 hspi->TxXferCount = Size;
mbed_official 87:085cde657901 1089
mbed_official 87:085cde657901 1090 hspi->RxISR = &SPI_2LinesRxISR;
mbed_official 87:085cde657901 1091 hspi->pRxBuffPtr = pRxData;
mbed_official 87:085cde657901 1092 hspi->RxXferSize = Size;
mbed_official 87:085cde657901 1093 hspi->RxXferCount = Size;
mbed_official 87:085cde657901 1094
mbed_official 87:085cde657901 1095 /* Reset CRC Calculation */
mbed_official 532:fe11edbda85c 1096 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official 87:085cde657901 1097 {
mbed_official 532:fe11edbda85c 1098 SPI_RESET_CRC(hspi);
mbed_official 87:085cde657901 1099 }
mbed_official 87:085cde657901 1100
mbed_official 87:085cde657901 1101 /* Enable TXE, RXNE and ERR interrupt */
mbed_official 87:085cde657901 1102 __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
mbed_official 87:085cde657901 1103
mbed_official 87:085cde657901 1104 /* Process Unlocked */
mbed_official 87:085cde657901 1105 __HAL_UNLOCK(hspi);
mbed_official 87:085cde657901 1106
mbed_official 87:085cde657901 1107 /* Check if the SPI is already enabled */
mbed_official 87:085cde657901 1108 if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official 87:085cde657901 1109 {
mbed_official 87:085cde657901 1110 /* Enable SPI peripheral */
mbed_official 87:085cde657901 1111 __HAL_SPI_ENABLE(hspi);
mbed_official 87:085cde657901 1112 }
mbed_official 87:085cde657901 1113
mbed_official 87:085cde657901 1114 return HAL_OK;
mbed_official 87:085cde657901 1115 }
mbed_official 87:085cde657901 1116 else
mbed_official 87:085cde657901 1117 {
mbed_official 87:085cde657901 1118 return HAL_BUSY;
mbed_official 87:085cde657901 1119 }
mbed_official 87:085cde657901 1120 }
mbed_official 87:085cde657901 1121
mbed_official 87:085cde657901 1122 /**
mbed_official 87:085cde657901 1123 * @brief Transmit an amount of data in no-blocking mode with DMA
mbed_official 226:b062af740e40 1124 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 1125 * the configuration information for SPI module.
mbed_official 87:085cde657901 1126 * @param pData: pointer to data buffer
mbed_official 87:085cde657901 1127 * @param Size: amount of data to be sent
mbed_official 87:085cde657901 1128 * @retval HAL status
mbed_official 87:085cde657901 1129 */
mbed_official 87:085cde657901 1130 HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
mbed_official 87:085cde657901 1131 {
mbed_official 87:085cde657901 1132 if(hspi->State == HAL_SPI_STATE_READY)
mbed_official 87:085cde657901 1133 {
mbed_official 369:2e96f1b71984 1134 if((pData == HAL_NULL) || (Size == 0))
mbed_official 87:085cde657901 1135 {
mbed_official 87:085cde657901 1136 return HAL_ERROR;
mbed_official 87:085cde657901 1137 }
mbed_official 87:085cde657901 1138
mbed_official 87:085cde657901 1139 /* Check the parameters */
mbed_official 87:085cde657901 1140 assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
mbed_official 87:085cde657901 1141
mbed_official 87:085cde657901 1142 /* Process Locked */
mbed_official 87:085cde657901 1143 __HAL_LOCK(hspi);
mbed_official 87:085cde657901 1144
mbed_official 87:085cde657901 1145 /* Configure communication */
mbed_official 87:085cde657901 1146 hspi->State = HAL_SPI_STATE_BUSY_TX;
mbed_official 87:085cde657901 1147 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official 87:085cde657901 1148
mbed_official 87:085cde657901 1149 hspi->pTxBuffPtr = pData;
mbed_official 87:085cde657901 1150 hspi->TxXferSize = Size;
mbed_official 87:085cde657901 1151 hspi->TxXferCount = Size;
mbed_official 87:085cde657901 1152
mbed_official 87:085cde657901 1153 /*Init field not used in handle to zero */
mbed_official 87:085cde657901 1154 hspi->TxISR = 0;
mbed_official 87:085cde657901 1155 hspi->RxISR = 0;
mbed_official 87:085cde657901 1156 hspi->RxXferSize = 0;
mbed_official 87:085cde657901 1157 hspi->RxXferCount = 0;
mbed_official 87:085cde657901 1158
mbed_official 87:085cde657901 1159 /* Configure communication direction : 1Line */
mbed_official 87:085cde657901 1160 if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
mbed_official 87:085cde657901 1161 {
mbed_official 532:fe11edbda85c 1162 SPI_1LINE_TX(hspi);
mbed_official 87:085cde657901 1163 }
mbed_official 87:085cde657901 1164
mbed_official 87:085cde657901 1165 /* Reset CRC Calculation */
mbed_official 532:fe11edbda85c 1166 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official 87:085cde657901 1167 {
mbed_official 532:fe11edbda85c 1168 SPI_RESET_CRC(hspi);
mbed_official 87:085cde657901 1169 }
mbed_official 87:085cde657901 1170
mbed_official 369:2e96f1b71984 1171 /* Set the SPI TxDMA Half transfer complete callback */
mbed_official 369:2e96f1b71984 1172 hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt;
mbed_official 369:2e96f1b71984 1173
mbed_official 87:085cde657901 1174 /* Set the SPI TxDMA transfer complete callback */
mbed_official 87:085cde657901 1175 hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt;
mbed_official 87:085cde657901 1176
mbed_official 87:085cde657901 1177 /* Set the DMA error callback */
mbed_official 87:085cde657901 1178 hspi->hdmatx->XferErrorCallback = SPI_DMAError;
mbed_official 87:085cde657901 1179
mbed_official 87:085cde657901 1180 /* Enable the Tx DMA Stream */
mbed_official 87:085cde657901 1181 HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
mbed_official 87:085cde657901 1182
mbed_official 87:085cde657901 1183 /* Process Unlocked */
mbed_official 87:085cde657901 1184 __HAL_UNLOCK(hspi);
mbed_official 87:085cde657901 1185
mbed_official 87:085cde657901 1186 /* Check if the SPI is already enabled */
mbed_official 87:085cde657901 1187 if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official 87:085cde657901 1188 {
mbed_official 87:085cde657901 1189 /* Enable SPI peripheral */
mbed_official 87:085cde657901 1190 __HAL_SPI_ENABLE(hspi);
mbed_official 87:085cde657901 1191 }
mbed_official 87:085cde657901 1192
mbed_official 532:fe11edbda85c 1193 /* Enable Tx DMA Request */
mbed_official 532:fe11edbda85c 1194 hspi->Instance->CR2 |= SPI_CR2_TXDMAEN;
mbed_official 532:fe11edbda85c 1195
mbed_official 87:085cde657901 1196 return HAL_OK;
mbed_official 87:085cde657901 1197 }
mbed_official 87:085cde657901 1198 else
mbed_official 87:085cde657901 1199 {
mbed_official 87:085cde657901 1200 return HAL_BUSY;
mbed_official 87:085cde657901 1201 }
mbed_official 87:085cde657901 1202 }
mbed_official 87:085cde657901 1203
mbed_official 87:085cde657901 1204 /**
mbed_official 87:085cde657901 1205 * @brief Receive an amount of data in no-blocking mode with DMA
mbed_official 226:b062af740e40 1206 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 532:fe11edbda85c 1207 * the configuration information for SPI module.
mbed_official 87:085cde657901 1208 * @param pData: pointer to data buffer
mbed_official 87:085cde657901 1209 * @note When the CRC feature is enabled the pData Length must be Size + 1.
mbed_official 87:085cde657901 1210 * @param Size: amount of data to be sent
mbed_official 87:085cde657901 1211 * @retval HAL status
mbed_official 87:085cde657901 1212 */
mbed_official 87:085cde657901 1213 HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
mbed_official 87:085cde657901 1214 {
mbed_official 87:085cde657901 1215 if(hspi->State == HAL_SPI_STATE_READY)
mbed_official 87:085cde657901 1216 {
mbed_official 369:2e96f1b71984 1217 if((pData == HAL_NULL) || (Size == 0))
mbed_official 87:085cde657901 1218 {
mbed_official 87:085cde657901 1219 return HAL_ERROR;
mbed_official 87:085cde657901 1220 }
mbed_official 87:085cde657901 1221
mbed_official 87:085cde657901 1222 /* Process Locked */
mbed_official 87:085cde657901 1223 __HAL_LOCK(hspi);
mbed_official 87:085cde657901 1224
mbed_official 87:085cde657901 1225 /* Configure communication */
mbed_official 87:085cde657901 1226 hspi->State = HAL_SPI_STATE_BUSY_RX;
mbed_official 87:085cde657901 1227 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official 87:085cde657901 1228
mbed_official 87:085cde657901 1229 hspi->pRxBuffPtr = pData;
mbed_official 87:085cde657901 1230 hspi->RxXferSize = Size;
mbed_official 87:085cde657901 1231 hspi->RxXferCount = Size;
mbed_official 87:085cde657901 1232
mbed_official 87:085cde657901 1233 /*Init field not used in handle to zero */
mbed_official 87:085cde657901 1234 hspi->RxISR = 0;
mbed_official 87:085cde657901 1235 hspi->TxISR = 0;
mbed_official 87:085cde657901 1236 hspi->TxXferSize = 0;
mbed_official 87:085cde657901 1237 hspi->TxXferCount = 0;
mbed_official 87:085cde657901 1238
mbed_official 87:085cde657901 1239 /* Configure communication direction : 1Line */
mbed_official 87:085cde657901 1240 if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
mbed_official 87:085cde657901 1241 {
mbed_official 532:fe11edbda85c 1242 SPI_1LINE_RX(hspi);
mbed_official 87:085cde657901 1243 }
mbed_official 87:085cde657901 1244 else if((hspi->Init.Direction == SPI_DIRECTION_2LINES)&&(hspi->Init.Mode == SPI_MODE_MASTER))
mbed_official 87:085cde657901 1245 {
mbed_official 87:085cde657901 1246 /* Process Unlocked */
mbed_official 87:085cde657901 1247 __HAL_UNLOCK(hspi);
mbed_official 87:085cde657901 1248
mbed_official 87:085cde657901 1249 /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
mbed_official 87:085cde657901 1250 return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size);
mbed_official 87:085cde657901 1251 }
mbed_official 87:085cde657901 1252
mbed_official 87:085cde657901 1253 /* Reset CRC Calculation */
mbed_official 532:fe11edbda85c 1254 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official 87:085cde657901 1255 {
mbed_official 532:fe11edbda85c 1256 SPI_RESET_CRC(hspi);
mbed_official 87:085cde657901 1257 }
mbed_official 87:085cde657901 1258
mbed_official 369:2e96f1b71984 1259 /* Set the SPI RxDMA Half transfer complete callback */
mbed_official 369:2e96f1b71984 1260 hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
mbed_official 369:2e96f1b71984 1261
mbed_official 87:085cde657901 1262 /* Set the SPI Rx DMA transfer complete callback */
mbed_official 87:085cde657901 1263 hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
mbed_official 87:085cde657901 1264
mbed_official 87:085cde657901 1265 /* Set the DMA error callback */
mbed_official 87:085cde657901 1266 hspi->hdmarx->XferErrorCallback = SPI_DMAError;
mbed_official 87:085cde657901 1267
mbed_official 87:085cde657901 1268 /* Enable the Rx DMA Stream */
mbed_official 87:085cde657901 1269 HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
mbed_official 87:085cde657901 1270
mbed_official 87:085cde657901 1271 /* Process Unlocked */
mbed_official 87:085cde657901 1272 __HAL_UNLOCK(hspi);
mbed_official 87:085cde657901 1273
mbed_official 87:085cde657901 1274 /* Check if the SPI is already enabled */
mbed_official 87:085cde657901 1275 if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official 87:085cde657901 1276 {
mbed_official 87:085cde657901 1277 /* Enable SPI peripheral */
mbed_official 87:085cde657901 1278 __HAL_SPI_ENABLE(hspi);
mbed_official 87:085cde657901 1279 }
mbed_official 87:085cde657901 1280
mbed_official 532:fe11edbda85c 1281 /* Enable Rx DMA Request */
mbed_official 532:fe11edbda85c 1282 hspi->Instance->CR2 |= SPI_CR2_RXDMAEN;
mbed_official 532:fe11edbda85c 1283
mbed_official 87:085cde657901 1284 return HAL_OK;
mbed_official 87:085cde657901 1285 }
mbed_official 87:085cde657901 1286 else
mbed_official 87:085cde657901 1287 {
mbed_official 87:085cde657901 1288 return HAL_BUSY;
mbed_official 87:085cde657901 1289 }
mbed_official 87:085cde657901 1290 }
mbed_official 87:085cde657901 1291
mbed_official 87:085cde657901 1292 /**
mbed_official 87:085cde657901 1293 * @brief Transmit and Receive an amount of data in no-blocking mode with DMA
mbed_official 226:b062af740e40 1294 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 1295 * the configuration information for SPI module.
mbed_official 87:085cde657901 1296 * @param pTxData: pointer to transmission data buffer
mbed_official 87:085cde657901 1297 * @param pRxData: pointer to reception data buffer
mbed_official 87:085cde657901 1298 * @note When the CRC feature is enabled the pRxData Length must be Size + 1
mbed_official 87:085cde657901 1299 * @param Size: amount of data to be sent
mbed_official 87:085cde657901 1300 * @retval HAL status
mbed_official 87:085cde657901 1301 */
mbed_official 87:085cde657901 1302 HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
mbed_official 87:085cde657901 1303 {
mbed_official 87:085cde657901 1304 uint32_t tmpstate = 0;
mbed_official 87:085cde657901 1305 tmpstate = hspi->State;
mbed_official 369:2e96f1b71984 1306 if((tmpstate == HAL_SPI_STATE_READY) || ((hspi->Init.Mode == SPI_MODE_MASTER) && \
mbed_official 369:2e96f1b71984 1307 (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmpstate == HAL_SPI_STATE_BUSY_RX)))
mbed_official 87:085cde657901 1308 {
mbed_official 369:2e96f1b71984 1309 if((pTxData == HAL_NULL ) || (pRxData == HAL_NULL ) || (Size == 0))
mbed_official 87:085cde657901 1310 {
mbed_official 87:085cde657901 1311 return HAL_ERROR;
mbed_official 87:085cde657901 1312 }
mbed_official 87:085cde657901 1313
mbed_official 87:085cde657901 1314 /* Check the parameters */
mbed_official 87:085cde657901 1315 assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
mbed_official 87:085cde657901 1316
mbed_official 87:085cde657901 1317 /* Process locked */
mbed_official 87:085cde657901 1318 __HAL_LOCK(hspi);
mbed_official 87:085cde657901 1319
mbed_official 87:085cde657901 1320 /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
mbed_official 369:2e96f1b71984 1321 if(hspi->State != HAL_SPI_STATE_BUSY_RX)
mbed_official 87:085cde657901 1322 {
mbed_official 106:ced8cbb51063 1323 hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
mbed_official 87:085cde657901 1324 }
mbed_official 87:085cde657901 1325
mbed_official 87:085cde657901 1326 /* Configure communication */
mbed_official 87:085cde657901 1327 hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official 87:085cde657901 1328
mbed_official 87:085cde657901 1329 hspi->pTxBuffPtr = (uint8_t*)pTxData;
mbed_official 87:085cde657901 1330 hspi->TxXferSize = Size;
mbed_official 87:085cde657901 1331 hspi->TxXferCount = Size;
mbed_official 87:085cde657901 1332
mbed_official 87:085cde657901 1333 hspi->pRxBuffPtr = (uint8_t*)pRxData;
mbed_official 87:085cde657901 1334 hspi->RxXferSize = Size;
mbed_official 87:085cde657901 1335 hspi->RxXferCount = Size;
mbed_official 87:085cde657901 1336
mbed_official 87:085cde657901 1337 /*Init field not used in handle to zero */
mbed_official 87:085cde657901 1338 hspi->RxISR = 0;
mbed_official 87:085cde657901 1339 hspi->TxISR = 0;
mbed_official 87:085cde657901 1340
mbed_official 87:085cde657901 1341 /* Reset CRC Calculation */
mbed_official 532:fe11edbda85c 1342 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official 87:085cde657901 1343 {
mbed_official 532:fe11edbda85c 1344 SPI_RESET_CRC(hspi);
mbed_official 87:085cde657901 1345 }
mbed_official 87:085cde657901 1346
mbed_official 106:ced8cbb51063 1347 /* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */
mbed_official 106:ced8cbb51063 1348 if(hspi->State == HAL_SPI_STATE_BUSY_RX)
mbed_official 106:ced8cbb51063 1349 {
mbed_official 369:2e96f1b71984 1350 /* Set the SPI Rx DMA Half transfer complete callback */
mbed_official 369:2e96f1b71984 1351 hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
mbed_official 369:2e96f1b71984 1352
mbed_official 106:ced8cbb51063 1353 hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
mbed_official 106:ced8cbb51063 1354 }
mbed_official 106:ced8cbb51063 1355 else
mbed_official 106:ced8cbb51063 1356 {
mbed_official 369:2e96f1b71984 1357 /* Set the SPI Tx/Rx DMA Half transfer complete callback */
mbed_official 369:2e96f1b71984 1358 hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;
mbed_official 369:2e96f1b71984 1359
mbed_official 106:ced8cbb51063 1360 hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt;
mbed_official 106:ced8cbb51063 1361 }
mbed_official 87:085cde657901 1362
mbed_official 87:085cde657901 1363 /* Set the DMA error callback */
mbed_official 87:085cde657901 1364 hspi->hdmarx->XferErrorCallback = SPI_DMAError;
mbed_official 87:085cde657901 1365
mbed_official 87:085cde657901 1366 /* Enable the Rx DMA Stream */
mbed_official 87:085cde657901 1367 HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
mbed_official 87:085cde657901 1368
mbed_official 87:085cde657901 1369 /* Enable Rx DMA Request */
mbed_official 87:085cde657901 1370 hspi->Instance->CR2 |= SPI_CR2_RXDMAEN;
mbed_official 87:085cde657901 1371
mbed_official 532:fe11edbda85c 1372 /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing
mbed_official 87:085cde657901 1373 is performed in DMA reception complete callback */
mbed_official 369:2e96f1b71984 1374 hspi->hdmatx->XferCpltCallback = HAL_NULL;
mbed_official 532:fe11edbda85c 1375
mbed_official 532:fe11edbda85c 1376 if(hspi->State == HAL_SPI_STATE_BUSY_TX_RX)
mbed_official 532:fe11edbda85c 1377 {
mbed_official 532:fe11edbda85c 1378 /* Set the DMA error callback */
mbed_official 532:fe11edbda85c 1379 hspi->hdmatx->XferErrorCallback = SPI_DMAError;
mbed_official 532:fe11edbda85c 1380 }
mbed_official 532:fe11edbda85c 1381 else
mbed_official 532:fe11edbda85c 1382 {
mbed_official 532:fe11edbda85c 1383 hspi->hdmatx->XferErrorCallback = HAL_NULL;
mbed_official 532:fe11edbda85c 1384 }
mbed_official 532:fe11edbda85c 1385
mbed_official 87:085cde657901 1386 /* Enable the Tx DMA Stream */
mbed_official 87:085cde657901 1387 HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
mbed_official 87:085cde657901 1388
mbed_official 532:fe11edbda85c 1389 /* Process Unlocked */
mbed_official 532:fe11edbda85c 1390 __HAL_UNLOCK(hspi);
mbed_official 532:fe11edbda85c 1391
mbed_official 369:2e96f1b71984 1392 /* Check if the SPI is already enabled */
mbed_official 87:085cde657901 1393 if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official 87:085cde657901 1394 {
mbed_official 87:085cde657901 1395 /* Enable SPI peripheral */
mbed_official 87:085cde657901 1396 __HAL_SPI_ENABLE(hspi);
mbed_official 87:085cde657901 1397 }
mbed_official 87:085cde657901 1398
mbed_official 369:2e96f1b71984 1399 /* Enable Tx DMA Request */
mbed_official 369:2e96f1b71984 1400 hspi->Instance->CR2 |= SPI_CR2_TXDMAEN;
mbed_official 369:2e96f1b71984 1401
mbed_official 87:085cde657901 1402 return HAL_OK;
mbed_official 87:085cde657901 1403 }
mbed_official 87:085cde657901 1404 else
mbed_official 87:085cde657901 1405 {
mbed_official 87:085cde657901 1406 return HAL_BUSY;
mbed_official 87:085cde657901 1407 }
mbed_official 87:085cde657901 1408 }
mbed_official 87:085cde657901 1409
mbed_official 369:2e96f1b71984 1410 /**
mbed_official 369:2e96f1b71984 1411 * @brief Pauses the DMA Transfer.
mbed_official 369:2e96f1b71984 1412 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 369:2e96f1b71984 1413 * the configuration information for the specified SPI module.
mbed_official 369:2e96f1b71984 1414 * @retval HAL status
mbed_official 369:2e96f1b71984 1415 */
mbed_official 369:2e96f1b71984 1416 HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi)
mbed_official 369:2e96f1b71984 1417 {
mbed_official 369:2e96f1b71984 1418 /* Process Locked */
mbed_official 369:2e96f1b71984 1419 __HAL_LOCK(hspi);
mbed_official 369:2e96f1b71984 1420
mbed_official 369:2e96f1b71984 1421 /* Disable the SPI DMA Tx & Rx requests */
mbed_official 369:2e96f1b71984 1422 hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
mbed_official 369:2e96f1b71984 1423 hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
mbed_official 369:2e96f1b71984 1424
mbed_official 369:2e96f1b71984 1425 /* Process Unlocked */
mbed_official 369:2e96f1b71984 1426 __HAL_UNLOCK(hspi);
mbed_official 369:2e96f1b71984 1427
mbed_official 369:2e96f1b71984 1428 return HAL_OK;
mbed_official 369:2e96f1b71984 1429 }
mbed_official 369:2e96f1b71984 1430
mbed_official 369:2e96f1b71984 1431 /**
mbed_official 369:2e96f1b71984 1432 * @brief Resumes the DMA Transfer.
mbed_official 369:2e96f1b71984 1433 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 369:2e96f1b71984 1434 * the configuration information for the specified SPI module.
mbed_official 369:2e96f1b71984 1435 * @retval HAL status
mbed_official 369:2e96f1b71984 1436 */
mbed_official 369:2e96f1b71984 1437 HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi)
mbed_official 369:2e96f1b71984 1438 {
mbed_official 369:2e96f1b71984 1439 /* Process Locked */
mbed_official 369:2e96f1b71984 1440 __HAL_LOCK(hspi);
mbed_official 369:2e96f1b71984 1441
mbed_official 369:2e96f1b71984 1442 /* Enable the SPI DMA Tx & Rx requests */
mbed_official 369:2e96f1b71984 1443 hspi->Instance->CR2 |= SPI_CR2_TXDMAEN;
mbed_official 369:2e96f1b71984 1444 hspi->Instance->CR2 |= SPI_CR2_RXDMAEN;
mbed_official 369:2e96f1b71984 1445
mbed_official 369:2e96f1b71984 1446 /* Process Unlocked */
mbed_official 369:2e96f1b71984 1447 __HAL_UNLOCK(hspi);
mbed_official 369:2e96f1b71984 1448
mbed_official 369:2e96f1b71984 1449 return HAL_OK;
mbed_official 369:2e96f1b71984 1450 }
mbed_official 369:2e96f1b71984 1451
mbed_official 369:2e96f1b71984 1452 /**
mbed_official 369:2e96f1b71984 1453 * @brief Stops the DMA Transfer.
mbed_official 532:fe11edbda85c 1454 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 532:fe11edbda85c 1455 * the configuration information for the specified SPI module.
mbed_official 369:2e96f1b71984 1456 * @retval HAL status
mbed_official 369:2e96f1b71984 1457 */
mbed_official 369:2e96f1b71984 1458 HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)
mbed_official 369:2e96f1b71984 1459 {
mbed_official 369:2e96f1b71984 1460 /* The Lock is not implemented on this API to allow the user application
mbed_official 369:2e96f1b71984 1461 to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback():
mbed_official 369:2e96f1b71984 1462 when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
mbed_official 369:2e96f1b71984 1463 and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback()
mbed_official 369:2e96f1b71984 1464 */
mbed_official 369:2e96f1b71984 1465
mbed_official 369:2e96f1b71984 1466 /* Abort the SPI DMA tx Stream */
mbed_official 369:2e96f1b71984 1467 if(hspi->hdmatx != HAL_NULL)
mbed_official 369:2e96f1b71984 1468 {
mbed_official 369:2e96f1b71984 1469 HAL_DMA_Abort(hspi->hdmatx);
mbed_official 369:2e96f1b71984 1470 }
mbed_official 369:2e96f1b71984 1471 /* Abort the SPI DMA rx Stream */
mbed_official 369:2e96f1b71984 1472 if(hspi->hdmarx != HAL_NULL)
mbed_official 369:2e96f1b71984 1473 {
mbed_official 369:2e96f1b71984 1474 HAL_DMA_Abort(hspi->hdmarx);
mbed_official 369:2e96f1b71984 1475 }
mbed_official 369:2e96f1b71984 1476
mbed_official 369:2e96f1b71984 1477 /* Disable the SPI DMA Tx & Rx requests */
mbed_official 369:2e96f1b71984 1478 hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
mbed_official 369:2e96f1b71984 1479 hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
mbed_official 369:2e96f1b71984 1480
mbed_official 369:2e96f1b71984 1481 hspi->State = HAL_SPI_STATE_READY;
mbed_official 369:2e96f1b71984 1482
mbed_official 369:2e96f1b71984 1483 return HAL_OK;
mbed_official 369:2e96f1b71984 1484 }
mbed_official 369:2e96f1b71984 1485
mbed_official 87:085cde657901 1486 /**
mbed_official 87:085cde657901 1487 * @brief This function handles SPI interrupt request.
mbed_official 226:b062af740e40 1488 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 1489 * the configuration information for SPI module.
mbed_official 87:085cde657901 1490 * @retval HAL status
mbed_official 87:085cde657901 1491 */
mbed_official 87:085cde657901 1492 void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
mbed_official 87:085cde657901 1493 {
mbed_official 87:085cde657901 1494 uint32_t tmp1 = 0, tmp2 = 0, tmp3 = 0;
mbed_official 87:085cde657901 1495
mbed_official 87:085cde657901 1496 tmp1 = __HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE);
mbed_official 87:085cde657901 1497 tmp2 = __HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_RXNE);
mbed_official 87:085cde657901 1498 tmp3 = __HAL_SPI_GET_FLAG(hspi, SPI_FLAG_OVR);
mbed_official 87:085cde657901 1499 /* SPI in mode Receiver and Overrun not occurred ---------------------------*/
mbed_official 87:085cde657901 1500 if((tmp1 != RESET) && (tmp2 != RESET) && (tmp3 == RESET))
mbed_official 87:085cde657901 1501 {
mbed_official 87:085cde657901 1502 hspi->RxISR(hspi);
mbed_official 87:085cde657901 1503 return;
mbed_official 87:085cde657901 1504 }
mbed_official 87:085cde657901 1505
mbed_official 87:085cde657901 1506 tmp1 = __HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE);
mbed_official 87:085cde657901 1507 tmp2 = __HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_TXE);
mbed_official 532:fe11edbda85c 1508 /* SPI in mode Transmitter ---------------------------------------------------*/
mbed_official 87:085cde657901 1509 if((tmp1 != RESET) && (tmp2 != RESET))
mbed_official 87:085cde657901 1510 {
mbed_official 87:085cde657901 1511 hspi->TxISR(hspi);
mbed_official 87:085cde657901 1512 return;
mbed_official 87:085cde657901 1513 }
mbed_official 87:085cde657901 1514
mbed_official 87:085cde657901 1515 if(__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_ERR) != RESET)
mbed_official 87:085cde657901 1516 {
mbed_official 226:b062af740e40 1517 /* SPI CRC error interrupt occurred ---------------------------------------*/
mbed_official 87:085cde657901 1518 if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
mbed_official 87:085cde657901 1519 {
mbed_official 87:085cde657901 1520 hspi->ErrorCode |= HAL_SPI_ERROR_CRC;
mbed_official 87:085cde657901 1521 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
mbed_official 87:085cde657901 1522 }
mbed_official 226:b062af740e40 1523 /* SPI Mode Fault error interrupt occurred --------------------------------*/
mbed_official 87:085cde657901 1524 if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_MODF) != RESET)
mbed_official 87:085cde657901 1525 {
mbed_official 87:085cde657901 1526 hspi->ErrorCode |= HAL_SPI_ERROR_MODF;
mbed_official 87:085cde657901 1527 __HAL_SPI_CLEAR_MODFFLAG(hspi);
mbed_official 87:085cde657901 1528 }
mbed_official 87:085cde657901 1529
mbed_official 226:b062af740e40 1530 /* SPI Overrun error interrupt occurred -----------------------------------*/
mbed_official 87:085cde657901 1531 if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_OVR) != RESET)
mbed_official 87:085cde657901 1532 {
mbed_official 87:085cde657901 1533 if(hspi->State != HAL_SPI_STATE_BUSY_TX)
mbed_official 87:085cde657901 1534 {
mbed_official 87:085cde657901 1535 hspi->ErrorCode |= HAL_SPI_ERROR_OVR;
mbed_official 87:085cde657901 1536 __HAL_SPI_CLEAR_OVRFLAG(hspi);
mbed_official 87:085cde657901 1537 }
mbed_official 87:085cde657901 1538 }
mbed_official 87:085cde657901 1539
mbed_official 226:b062af740e40 1540 /* SPI Frame error interrupt occurred -------------------------------------*/
mbed_official 87:085cde657901 1541 if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_FRE) != RESET)
mbed_official 87:085cde657901 1542 {
mbed_official 87:085cde657901 1543 hspi->ErrorCode |= HAL_SPI_ERROR_FRE;
mbed_official 87:085cde657901 1544 __HAL_SPI_CLEAR_FREFLAG(hspi);
mbed_official 87:085cde657901 1545 }
mbed_official 87:085cde657901 1546
mbed_official 87:085cde657901 1547 /* Call the Error call Back in case of Errors */
mbed_official 87:085cde657901 1548 if(hspi->ErrorCode!=HAL_SPI_ERROR_NONE)
mbed_official 87:085cde657901 1549 {
mbed_official 87:085cde657901 1550 hspi->State = HAL_SPI_STATE_READY;
mbed_official 87:085cde657901 1551 HAL_SPI_ErrorCallback(hspi);
mbed_official 87:085cde657901 1552 }
mbed_official 87:085cde657901 1553 }
mbed_official 87:085cde657901 1554 }
mbed_official 87:085cde657901 1555
mbed_official 87:085cde657901 1556 /**
mbed_official 87:085cde657901 1557 * @brief Tx Transfer completed callbacks
mbed_official 226:b062af740e40 1558 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 1559 * the configuration information for SPI module.
mbed_official 87:085cde657901 1560 * @retval None
mbed_official 87:085cde657901 1561 */
mbed_official 87:085cde657901 1562 __weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
mbed_official 87:085cde657901 1563 {
mbed_official 87:085cde657901 1564 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 532:fe11edbda85c 1565 the HAL_SPI_TxCpltCallback could be implemented in the user file
mbed_official 87:085cde657901 1566 */
mbed_official 87:085cde657901 1567 }
mbed_official 87:085cde657901 1568
mbed_official 87:085cde657901 1569 /**
mbed_official 87:085cde657901 1570 * @brief Rx Transfer completed callbacks
mbed_official 226:b062af740e40 1571 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 1572 * the configuration information for SPI module.
mbed_official 87:085cde657901 1573 * @retval None
mbed_official 87:085cde657901 1574 */
mbed_official 87:085cde657901 1575 __weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
mbed_official 87:085cde657901 1576 {
mbed_official 87:085cde657901 1577 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 532:fe11edbda85c 1578 the HAL_SPI_RxCpltCallback() could be implemented in the user file
mbed_official 87:085cde657901 1579 */
mbed_official 87:085cde657901 1580 }
mbed_official 87:085cde657901 1581
mbed_official 87:085cde657901 1582 /**
mbed_official 87:085cde657901 1583 * @brief Tx and Rx Transfer completed callbacks
mbed_official 226:b062af740e40 1584 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 1585 * the configuration information for SPI module.
mbed_official 87:085cde657901 1586 * @retval None
mbed_official 87:085cde657901 1587 */
mbed_official 87:085cde657901 1588 __weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
mbed_official 87:085cde657901 1589 {
mbed_official 87:085cde657901 1590 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 532:fe11edbda85c 1591 the HAL_SPI_TxRxCpltCallback() could be implemented in the user file
mbed_official 87:085cde657901 1592 */
mbed_official 87:085cde657901 1593 }
mbed_official 87:085cde657901 1594
mbed_official 87:085cde657901 1595 /**
mbed_official 369:2e96f1b71984 1596 * @brief Tx Half Transfer completed callbacks
mbed_official 369:2e96f1b71984 1597 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 369:2e96f1b71984 1598 * the configuration information for SPI module.
mbed_official 369:2e96f1b71984 1599 * @retval None
mbed_official 369:2e96f1b71984 1600 */
mbed_official 369:2e96f1b71984 1601 __weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)
mbed_official 369:2e96f1b71984 1602 {
mbed_official 369:2e96f1b71984 1603 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 532:fe11edbda85c 1604 the HAL_SPI_TxHalfCpltCallback could be implemented in the user file
mbed_official 369:2e96f1b71984 1605 */
mbed_official 369:2e96f1b71984 1606 }
mbed_official 369:2e96f1b71984 1607
mbed_official 369:2e96f1b71984 1608 /**
mbed_official 369:2e96f1b71984 1609 * @brief Rx Half Transfer completed callbacks
mbed_official 369:2e96f1b71984 1610 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 369:2e96f1b71984 1611 * the configuration information for SPI module.
mbed_official 369:2e96f1b71984 1612 * @retval None
mbed_official 369:2e96f1b71984 1613 */
mbed_official 369:2e96f1b71984 1614 __weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)
mbed_official 369:2e96f1b71984 1615 {
mbed_official 369:2e96f1b71984 1616 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 532:fe11edbda85c 1617 the HAL_SPI_RxHalfCpltCallback() could be implemented in the user file
mbed_official 369:2e96f1b71984 1618 */
mbed_official 369:2e96f1b71984 1619 }
mbed_official 369:2e96f1b71984 1620
mbed_official 369:2e96f1b71984 1621 /**
mbed_official 369:2e96f1b71984 1622 * @brief Tx and Rx Transfer completed callbacks
mbed_official 369:2e96f1b71984 1623 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 369:2e96f1b71984 1624 * the configuration information for SPI module.
mbed_official 369:2e96f1b71984 1625 * @retval None
mbed_official 369:2e96f1b71984 1626 */
mbed_official 369:2e96f1b71984 1627 __weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
mbed_official 369:2e96f1b71984 1628 {
mbed_official 369:2e96f1b71984 1629 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 532:fe11edbda85c 1630 the HAL_SPI_TxRxHalfCpltCallback() could be implemented in the user file
mbed_official 369:2e96f1b71984 1631 */
mbed_official 369:2e96f1b71984 1632 }
mbed_official 369:2e96f1b71984 1633
mbed_official 369:2e96f1b71984 1634 /**
mbed_official 87:085cde657901 1635 * @brief SPI error callbacks
mbed_official 226:b062af740e40 1636 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 1637 * the configuration information for SPI module.
mbed_official 87:085cde657901 1638 * @retval None
mbed_official 87:085cde657901 1639 */
mbed_official 87:085cde657901 1640 __weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
mbed_official 87:085cde657901 1641 {
mbed_official 87:085cde657901 1642 /* NOTE : - This function Should not be modified, when the callback is needed,
mbed_official 532:fe11edbda85c 1643 the HAL_SPI_ErrorCallback() could be implemented in the user file.
mbed_official 87:085cde657901 1644 - The ErrorCode parameter in the hspi handle is updated by the SPI processes
mbed_official 226:b062af740e40 1645 and user can use HAL_SPI_GetError() API to check the latest error occurred.
mbed_official 87:085cde657901 1646 */
mbed_official 87:085cde657901 1647 }
mbed_official 87:085cde657901 1648
mbed_official 87:085cde657901 1649 /**
mbed_official 87:085cde657901 1650 * @}
mbed_official 87:085cde657901 1651 */
mbed_official 87:085cde657901 1652
mbed_official 532:fe11edbda85c 1653 /** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions
mbed_official 87:085cde657901 1654 * @brief SPI control functions
mbed_official 87:085cde657901 1655 *
mbed_official 87:085cde657901 1656 @verbatim
mbed_official 87:085cde657901 1657 ===============================================================================
mbed_official 87:085cde657901 1658 ##### Peripheral State and Errors functions #####
mbed_official 87:085cde657901 1659 ===============================================================================
mbed_official 87:085cde657901 1660 [..]
mbed_official 87:085cde657901 1661 This subsection provides a set of functions allowing to control the SPI.
mbed_official 87:085cde657901 1662 (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral
mbed_official 87:085cde657901 1663 (+) HAL_SPI_GetError() check in run-time Errors occurring during communication
mbed_official 87:085cde657901 1664 @endverbatim
mbed_official 87:085cde657901 1665 * @{
mbed_official 87:085cde657901 1666 */
mbed_official 87:085cde657901 1667
mbed_official 87:085cde657901 1668 /**
mbed_official 87:085cde657901 1669 * @brief Return the SPI state
mbed_official 226:b062af740e40 1670 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 1671 * the configuration information for SPI module.
mbed_official 226:b062af740e40 1672 * @retval HAL state
mbed_official 87:085cde657901 1673 */
mbed_official 87:085cde657901 1674 HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
mbed_official 87:085cde657901 1675 {
mbed_official 87:085cde657901 1676 return hspi->State;
mbed_official 87:085cde657901 1677 }
mbed_official 87:085cde657901 1678
mbed_official 87:085cde657901 1679 /**
mbed_official 87:085cde657901 1680 * @brief Return the SPI error code
mbed_official 226:b062af740e40 1681 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 1682 * the configuration information for SPI module.
mbed_official 87:085cde657901 1683 * @retval SPI Error Code
mbed_official 87:085cde657901 1684 */
mbed_official 532:fe11edbda85c 1685 uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
mbed_official 87:085cde657901 1686 {
mbed_official 87:085cde657901 1687 return hspi->ErrorCode;
mbed_official 87:085cde657901 1688 }
mbed_official 87:085cde657901 1689
mbed_official 87:085cde657901 1690 /**
mbed_official 87:085cde657901 1691 * @}
mbed_official 87:085cde657901 1692 */
mbed_official 87:085cde657901 1693
mbed_official 87:085cde657901 1694 /**
mbed_official 87:085cde657901 1695 * @brief Interrupt Handler to close Tx transfer
mbed_official 226:b062af740e40 1696 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 1697 * the configuration information for SPI module.
mbed_official 87:085cde657901 1698 * @retval void
mbed_official 87:085cde657901 1699 */
mbed_official 87:085cde657901 1700 static void SPI_TxCloseIRQHandler(SPI_HandleTypeDef *hspi)
mbed_official 87:085cde657901 1701 {
mbed_official 106:ced8cbb51063 1702 /* Wait until TXE flag is set to send data */
mbed_official 106:ced8cbb51063 1703 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
mbed_official 87:085cde657901 1704 {
mbed_official 106:ced8cbb51063 1705 hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
mbed_official 87:085cde657901 1706 }
mbed_official 87:085cde657901 1707
mbed_official 87:085cde657901 1708 /* Disable TXE interrupt */
mbed_official 87:085cde657901 1709 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE ));
mbed_official 87:085cde657901 1710
mbed_official 87:085cde657901 1711 /* Disable ERR interrupt if Receive process is finished */
mbed_official 87:085cde657901 1712 if(__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_RXNE) == RESET)
mbed_official 87:085cde657901 1713 {
mbed_official 87:085cde657901 1714 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_ERR));
mbed_official 87:085cde657901 1715
mbed_official 87:085cde657901 1716 /* Wait until Busy flag is reset before disabling SPI */
mbed_official 87:085cde657901 1717 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
mbed_official 87:085cde657901 1718 {
mbed_official 87:085cde657901 1719 hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
mbed_official 87:085cde657901 1720 }
mbed_official 87:085cde657901 1721
mbed_official 532:fe11edbda85c 1722 /* Clear OVERRUN flag in 2 Lines communication mode because received is not read */
mbed_official 87:085cde657901 1723 if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
mbed_official 87:085cde657901 1724 {
mbed_official 87:085cde657901 1725 __HAL_SPI_CLEAR_OVRFLAG(hspi);
mbed_official 87:085cde657901 1726 }
mbed_official 87:085cde657901 1727
mbed_official 87:085cde657901 1728 /* Check if Errors has been detected during transfer */
mbed_official 87:085cde657901 1729 if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
mbed_official 87:085cde657901 1730 {
mbed_official 87:085cde657901 1731 /* Check if we are in Tx or in Rx/Tx Mode */
mbed_official 87:085cde657901 1732 if(hspi->State == HAL_SPI_STATE_BUSY_TX_RX)
mbed_official 87:085cde657901 1733 {
mbed_official 106:ced8cbb51063 1734 /* Set state to READY before run the Callback Complete */
mbed_official 106:ced8cbb51063 1735 hspi->State = HAL_SPI_STATE_READY;
mbed_official 87:085cde657901 1736 HAL_SPI_TxRxCpltCallback(hspi);
mbed_official 87:085cde657901 1737 }
mbed_official 87:085cde657901 1738 else
mbed_official 87:085cde657901 1739 {
mbed_official 106:ced8cbb51063 1740 /* Set state to READY before run the Callback Complete */
mbed_official 106:ced8cbb51063 1741 hspi->State = HAL_SPI_STATE_READY;
mbed_official 106:ced8cbb51063 1742 HAL_SPI_TxCpltCallback(hspi);
mbed_official 87:085cde657901 1743 }
mbed_official 87:085cde657901 1744 }
mbed_official 87:085cde657901 1745 else
mbed_official 87:085cde657901 1746 {
mbed_official 106:ced8cbb51063 1747 /* Set state to READY before run the Callback Complete */
mbed_official 106:ced8cbb51063 1748 hspi->State = HAL_SPI_STATE_READY;
mbed_official 87:085cde657901 1749 /* Call Error call back in case of Error */
mbed_official 87:085cde657901 1750 HAL_SPI_ErrorCallback(hspi);
mbed_official 87:085cde657901 1751 }
mbed_official 87:085cde657901 1752 }
mbed_official 87:085cde657901 1753 }
mbed_official 87:085cde657901 1754
mbed_official 87:085cde657901 1755 /**
mbed_official 87:085cde657901 1756 * @brief Interrupt Handler to transmit amount of data in no-blocking mode
mbed_official 226:b062af740e40 1757 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 1758 * the configuration information for SPI module.
mbed_official 87:085cde657901 1759 * @retval void
mbed_official 87:085cde657901 1760 */
mbed_official 87:085cde657901 1761 static void SPI_TxISR(SPI_HandleTypeDef *hspi)
mbed_official 87:085cde657901 1762 {
mbed_official 87:085cde657901 1763 /* Transmit data in 8 Bit mode */
mbed_official 87:085cde657901 1764 if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
mbed_official 87:085cde657901 1765 {
mbed_official 87:085cde657901 1766 hspi->Instance->DR = (*hspi->pTxBuffPtr++);
mbed_official 87:085cde657901 1767 }
mbed_official 87:085cde657901 1768 /* Transmit data in 16 Bit mode */
mbed_official 87:085cde657901 1769 else
mbed_official 87:085cde657901 1770 {
mbed_official 87:085cde657901 1771 hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr);
mbed_official 87:085cde657901 1772 hspi->pTxBuffPtr+=2;
mbed_official 87:085cde657901 1773 }
mbed_official 87:085cde657901 1774 hspi->TxXferCount--;
mbed_official 87:085cde657901 1775
mbed_official 87:085cde657901 1776 if(hspi->TxXferCount == 0)
mbed_official 87:085cde657901 1777 {
mbed_official 532:fe11edbda85c 1778 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official 87:085cde657901 1779 {
mbed_official 87:085cde657901 1780 /* calculate and transfer CRC on Tx line */
mbed_official 87:085cde657901 1781 hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
mbed_official 87:085cde657901 1782 }
mbed_official 87:085cde657901 1783 SPI_TxCloseIRQHandler(hspi);
mbed_official 87:085cde657901 1784 }
mbed_official 87:085cde657901 1785 }
mbed_official 87:085cde657901 1786
mbed_official 87:085cde657901 1787 /**
mbed_official 87:085cde657901 1788 * @brief Interrupt Handler to close Rx transfer
mbed_official 226:b062af740e40 1789 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 1790 * the configuration information for SPI module.
mbed_official 87:085cde657901 1791 * @retval void
mbed_official 87:085cde657901 1792 */
mbed_official 106:ced8cbb51063 1793 static void SPI_RxCloseIRQHandler(SPI_HandleTypeDef *hspi)
mbed_official 87:085cde657901 1794 {
mbed_official 87:085cde657901 1795 __IO uint16_t tmpreg;
mbed_official 87:085cde657901 1796
mbed_official 532:fe11edbda85c 1797 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official 87:085cde657901 1798 {
mbed_official 87:085cde657901 1799 /* Wait until RXNE flag is set to send data */
mbed_official 87:085cde657901 1800 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
mbed_official 87:085cde657901 1801 {
mbed_official 87:085cde657901 1802 hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
mbed_official 87:085cde657901 1803 }
mbed_official 87:085cde657901 1804
mbed_official 87:085cde657901 1805 /* Read CRC to reset RXNE flag */
mbed_official 87:085cde657901 1806 tmpreg = hspi->Instance->DR;
mbed_official 532:fe11edbda85c 1807 UNUSED(tmpreg);
mbed_official 87:085cde657901 1808
mbed_official 87:085cde657901 1809 /* Wait until RXNE flag is set to send data */
mbed_official 87:085cde657901 1810 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
mbed_official 87:085cde657901 1811 {
mbed_official 87:085cde657901 1812 hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
mbed_official 87:085cde657901 1813 }
mbed_official 87:085cde657901 1814
mbed_official 87:085cde657901 1815 /* Check if CRC error occurred */
mbed_official 87:085cde657901 1816 if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
mbed_official 87:085cde657901 1817 {
mbed_official 87:085cde657901 1818 hspi->ErrorCode |= HAL_SPI_ERROR_CRC;
mbed_official 87:085cde657901 1819
mbed_official 87:085cde657901 1820 /* Reset CRC Calculation */
mbed_official 532:fe11edbda85c 1821 SPI_RESET_CRC(hspi);
mbed_official 87:085cde657901 1822 }
mbed_official 87:085cde657901 1823 }
mbed_official 87:085cde657901 1824
mbed_official 87:085cde657901 1825 /* Disable RXNE and ERR interrupt */
mbed_official 87:085cde657901 1826 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE));
mbed_official 87:085cde657901 1827
mbed_official 87:085cde657901 1828 /* if Transmit process is finished */
mbed_official 87:085cde657901 1829 if(__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_TXE) == RESET)
mbed_official 87:085cde657901 1830 {
mbed_official 87:085cde657901 1831 /* Disable ERR interrupt */
mbed_official 87:085cde657901 1832 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_ERR));
mbed_official 87:085cde657901 1833
mbed_official 87:085cde657901 1834 if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
mbed_official 87:085cde657901 1835 {
mbed_official 87:085cde657901 1836 /* Disable SPI peripheral */
mbed_official 87:085cde657901 1837 __HAL_SPI_DISABLE(hspi);
mbed_official 87:085cde657901 1838 }
mbed_official 87:085cde657901 1839
mbed_official 87:085cde657901 1840 /* Check if Errors has been detected during transfer */
mbed_official 87:085cde657901 1841 if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
mbed_official 87:085cde657901 1842 {
mbed_official 87:085cde657901 1843 /* Check if we are in Rx or in Rx/Tx Mode */
mbed_official 87:085cde657901 1844 if(hspi->State == HAL_SPI_STATE_BUSY_TX_RX)
mbed_official 87:085cde657901 1845 {
mbed_official 106:ced8cbb51063 1846 /* Set state to READY before run the Callback Complete */
mbed_official 106:ced8cbb51063 1847 hspi->State = HAL_SPI_STATE_READY;
mbed_official 87:085cde657901 1848 HAL_SPI_TxRxCpltCallback(hspi);
mbed_official 369:2e96f1b71984 1849 }
mbed_official 369:2e96f1b71984 1850 else
mbed_official 87:085cde657901 1851 {
mbed_official 106:ced8cbb51063 1852 /* Set state to READY before run the Callback Complete */
mbed_official 106:ced8cbb51063 1853 hspi->State = HAL_SPI_STATE_READY;
mbed_official 87:085cde657901 1854 HAL_SPI_RxCpltCallback(hspi);
mbed_official 87:085cde657901 1855 }
mbed_official 87:085cde657901 1856 }
mbed_official 87:085cde657901 1857 else
mbed_official 87:085cde657901 1858 {
mbed_official 106:ced8cbb51063 1859 /* Set state to READY before run the Callback Complete */
mbed_official 106:ced8cbb51063 1860 hspi->State = HAL_SPI_STATE_READY;
mbed_official 87:085cde657901 1861 /* Call Error call back in case of Error */
mbed_official 87:085cde657901 1862 HAL_SPI_ErrorCallback(hspi);
mbed_official 87:085cde657901 1863 }
mbed_official 87:085cde657901 1864 }
mbed_official 87:085cde657901 1865 }
mbed_official 87:085cde657901 1866
mbed_official 87:085cde657901 1867 /**
mbed_official 87:085cde657901 1868 * @brief Interrupt Handler to receive amount of data in 2Lines mode
mbed_official 226:b062af740e40 1869 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 1870 * the configuration information for SPI module.
mbed_official 87:085cde657901 1871 * @retval void
mbed_official 87:085cde657901 1872 */
mbed_official 87:085cde657901 1873 static void SPI_2LinesRxISR(SPI_HandleTypeDef *hspi)
mbed_official 87:085cde657901 1874 {
mbed_official 87:085cde657901 1875 /* Receive data in 8 Bit mode */
mbed_official 87:085cde657901 1876 if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
mbed_official 87:085cde657901 1877 {
mbed_official 87:085cde657901 1878 (*hspi->pRxBuffPtr++) = hspi->Instance->DR;
mbed_official 87:085cde657901 1879 }
mbed_official 87:085cde657901 1880 /* Receive data in 16 Bit mode */
mbed_official 87:085cde657901 1881 else
mbed_official 87:085cde657901 1882 {
mbed_official 87:085cde657901 1883 *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
mbed_official 87:085cde657901 1884 hspi->pRxBuffPtr+=2;
mbed_official 87:085cde657901 1885 }
mbed_official 87:085cde657901 1886 hspi->RxXferCount--;
mbed_official 87:085cde657901 1887
mbed_official 87:085cde657901 1888 if(hspi->RxXferCount==0)
mbed_official 87:085cde657901 1889 {
mbed_official 106:ced8cbb51063 1890 SPI_RxCloseIRQHandler(hspi);
mbed_official 87:085cde657901 1891 }
mbed_official 87:085cde657901 1892 }
mbed_official 87:085cde657901 1893
mbed_official 87:085cde657901 1894 /**
mbed_official 87:085cde657901 1895 * @brief Interrupt Handler to receive amount of data in no-blocking mode
mbed_official 226:b062af740e40 1896 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 1897 * the configuration information for SPI module.
mbed_official 87:085cde657901 1898 * @retval void
mbed_official 87:085cde657901 1899 */
mbed_official 87:085cde657901 1900 static void SPI_RxISR(SPI_HandleTypeDef *hspi)
mbed_official 87:085cde657901 1901 {
mbed_official 87:085cde657901 1902 /* Receive data in 8 Bit mode */
mbed_official 87:085cde657901 1903 if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
mbed_official 87:085cde657901 1904 {
mbed_official 87:085cde657901 1905 (*hspi->pRxBuffPtr++) = hspi->Instance->DR;
mbed_official 87:085cde657901 1906 }
mbed_official 87:085cde657901 1907 /* Receive data in 16 Bit mode */
mbed_official 87:085cde657901 1908 else
mbed_official 87:085cde657901 1909 {
mbed_official 87:085cde657901 1910 *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
mbed_official 87:085cde657901 1911 hspi->pRxBuffPtr+=2;
mbed_official 87:085cde657901 1912 }
mbed_official 87:085cde657901 1913 hspi->RxXferCount--;
mbed_official 87:085cde657901 1914
mbed_official 87:085cde657901 1915 /* Enable CRC Transmission */
mbed_official 532:fe11edbda85c 1916 if((hspi->RxXferCount == 1) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
mbed_official 87:085cde657901 1917 {
mbed_official 87:085cde657901 1918 /* Set CRC Next to calculate CRC on Rx side */
mbed_official 87:085cde657901 1919 hspi->Instance->CR1 |= SPI_CR1_CRCNEXT;
mbed_official 87:085cde657901 1920 }
mbed_official 87:085cde657901 1921
mbed_official 87:085cde657901 1922 if(hspi->RxXferCount == 0)
mbed_official 87:085cde657901 1923 {
mbed_official 106:ced8cbb51063 1924 SPI_RxCloseIRQHandler(hspi);
mbed_official 87:085cde657901 1925 }
mbed_official 87:085cde657901 1926 }
mbed_official 87:085cde657901 1927
mbed_official 87:085cde657901 1928 /**
mbed_official 87:085cde657901 1929 * @brief DMA SPI transmit process complete callback
mbed_official 226:b062af740e40 1930 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 1931 * the configuration information for the specified DMA module.
mbed_official 87:085cde657901 1932 * @retval None
mbed_official 87:085cde657901 1933 */
mbed_official 87:085cde657901 1934 static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
mbed_official 87:085cde657901 1935 {
mbed_official 87:085cde657901 1936 SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official 87:085cde657901 1937
mbed_official 369:2e96f1b71984 1938 /* DMA Normal Mode */
mbed_official 369:2e96f1b71984 1939 if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
mbed_official 87:085cde657901 1940 {
mbed_official 369:2e96f1b71984 1941 /* Wait until TXE flag is set to send data */
mbed_official 369:2e96f1b71984 1942 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
mbed_official 369:2e96f1b71984 1943 {
mbed_official 369:2e96f1b71984 1944 hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
mbed_official 369:2e96f1b71984 1945 }
mbed_official 369:2e96f1b71984 1946 /* Disable Tx DMA Request */
mbed_official 369:2e96f1b71984 1947 hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
mbed_official 87:085cde657901 1948
mbed_official 369:2e96f1b71984 1949 /* Wait until Busy flag is reset before disabling SPI */
mbed_official 369:2e96f1b71984 1950 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
mbed_official 369:2e96f1b71984 1951 {
mbed_official 369:2e96f1b71984 1952 hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
mbed_official 369:2e96f1b71984 1953 }
mbed_official 369:2e96f1b71984 1954
mbed_official 369:2e96f1b71984 1955 hspi->TxXferCount = 0;
mbed_official 369:2e96f1b71984 1956
mbed_official 369:2e96f1b71984 1957 hspi->State = HAL_SPI_STATE_READY;
mbed_official 87:085cde657901 1958 }
mbed_official 87:085cde657901 1959
mbed_official 532:fe11edbda85c 1960 /* Clear OVERRUN flag in 2 Lines communication mode because received is not read */
mbed_official 87:085cde657901 1961 if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
mbed_official 87:085cde657901 1962 {
mbed_official 369:2e96f1b71984 1963 __HAL_SPI_CLEAR_OVRFLAG(hspi);
mbed_official 87:085cde657901 1964 }
mbed_official 87:085cde657901 1965
mbed_official 87:085cde657901 1966 /* Check if Errors has been detected during transfer */
mbed_official 87:085cde657901 1967 if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
mbed_official 87:085cde657901 1968 {
mbed_official 87:085cde657901 1969 HAL_SPI_ErrorCallback(hspi);
mbed_official 87:085cde657901 1970 }
mbed_official 87:085cde657901 1971 else
mbed_official 87:085cde657901 1972 {
mbed_official 87:085cde657901 1973 HAL_SPI_TxCpltCallback(hspi);
mbed_official 87:085cde657901 1974 }
mbed_official 87:085cde657901 1975 }
mbed_official 87:085cde657901 1976
mbed_official 87:085cde657901 1977 /**
mbed_official 87:085cde657901 1978 * @brief DMA SPI receive process complete callback
mbed_official 226:b062af740e40 1979 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 1980 * the configuration information for the specified DMA module.
mbed_official 87:085cde657901 1981 * @retval None
mbed_official 87:085cde657901 1982 */
mbed_official 87:085cde657901 1983 static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
mbed_official 87:085cde657901 1984 {
mbed_official 87:085cde657901 1985 __IO uint16_t tmpreg;
mbed_official 369:2e96f1b71984 1986
mbed_official 87:085cde657901 1987 SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official 369:2e96f1b71984 1988 /* DMA Normal mode */
mbed_official 369:2e96f1b71984 1989 if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
mbed_official 87:085cde657901 1990 {
mbed_official 532:fe11edbda85c 1991 if((hspi->Init.Direction == SPI_DIRECTION_2LINES)&&(hspi->Init.Mode == SPI_MODE_MASTER))
mbed_official 532:fe11edbda85c 1992 {
mbed_official 532:fe11edbda85c 1993 SPI_DMAEndTransmitReceive(hspi);
mbed_official 532:fe11edbda85c 1994 }
mbed_official 532:fe11edbda85c 1995 /* SPI_DIRECTION_1LINE or SPI_DIRECTION_2LINES_RXONLY */
mbed_official 532:fe11edbda85c 1996 else
mbed_official 87:085cde657901 1997 {
mbed_official 532:fe11edbda85c 1998 if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
mbed_official 532:fe11edbda85c 1999 {
mbed_official 532:fe11edbda85c 2000 /* Disable SPI peripheral */
mbed_official 532:fe11edbda85c 2001 __HAL_SPI_DISABLE(hspi);
mbed_official 532:fe11edbda85c 2002 }
mbed_official 532:fe11edbda85c 2003
mbed_official 532:fe11edbda85c 2004 /* Disable Rx DMA Request */
mbed_official 532:fe11edbda85c 2005 hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
mbed_official 532:fe11edbda85c 2006
mbed_official 532:fe11edbda85c 2007 hspi->RxXferCount = 0;
mbed_official 532:fe11edbda85c 2008
mbed_official 532:fe11edbda85c 2009 /* Reset CRC Calculation */
mbed_official 532:fe11edbda85c 2010 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official 532:fe11edbda85c 2011 {
mbed_official 532:fe11edbda85c 2012 /* Wait until RXNE flag is set to send data */
mbed_official 532:fe11edbda85c 2013 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
mbed_official 532:fe11edbda85c 2014 {
mbed_official 532:fe11edbda85c 2015 hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
mbed_official 532:fe11edbda85c 2016 }
mbed_official 532:fe11edbda85c 2017
mbed_official 532:fe11edbda85c 2018 /* Read CRC */
mbed_official 532:fe11edbda85c 2019 tmpreg = hspi->Instance->DR;
mbed_official 532:fe11edbda85c 2020 UNUSED(tmpreg);
mbed_official 532:fe11edbda85c 2021
mbed_official 532:fe11edbda85c 2022 /* Wait until RXNE flag is set */
mbed_official 532:fe11edbda85c 2023 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
mbed_official 532:fe11edbda85c 2024 {
mbed_official 532:fe11edbda85c 2025 hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
mbed_official 532:fe11edbda85c 2026 }
mbed_official 532:fe11edbda85c 2027
mbed_official 532:fe11edbda85c 2028 /* Check if CRC error occurred */
mbed_official 532:fe11edbda85c 2029 if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
mbed_official 532:fe11edbda85c 2030 {
mbed_official 532:fe11edbda85c 2031 hspi->ErrorCode |= HAL_SPI_ERROR_CRC;
mbed_official 532:fe11edbda85c 2032 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
mbed_official 532:fe11edbda85c 2033 }
mbed_official 532:fe11edbda85c 2034 }
mbed_official 87:085cde657901 2035 }
mbed_official 369:2e96f1b71984 2036
mbed_official 369:2e96f1b71984 2037 hspi->State = HAL_SPI_STATE_READY;
mbed_official 369:2e96f1b71984 2038
mbed_official 369:2e96f1b71984 2039 /* Check if Errors has been detected during transfer */
mbed_official 369:2e96f1b71984 2040 if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
mbed_official 369:2e96f1b71984 2041 {
mbed_official 369:2e96f1b71984 2042 HAL_SPI_ErrorCallback(hspi);
mbed_official 369:2e96f1b71984 2043 }
mbed_official 369:2e96f1b71984 2044 else
mbed_official 369:2e96f1b71984 2045 {
mbed_official 369:2e96f1b71984 2046 HAL_SPI_RxCpltCallback(hspi);
mbed_official 369:2e96f1b71984 2047 }
mbed_official 87:085cde657901 2048 }
mbed_official 87:085cde657901 2049 else
mbed_official 87:085cde657901 2050 {
mbed_official 87:085cde657901 2051 HAL_SPI_RxCpltCallback(hspi);
mbed_official 87:085cde657901 2052 }
mbed_official 87:085cde657901 2053 }
mbed_official 87:085cde657901 2054
mbed_official 87:085cde657901 2055 /**
mbed_official 532:fe11edbda85c 2056 * @brief End DMA SPI transmit receive process
mbed_official 532:fe11edbda85c 2057 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 532:fe11edbda85c 2058 * the configuration information for SPI module.
mbed_official 532:fe11edbda85c 2059 * @retval None
mbed_official 532:fe11edbda85c 2060 */
mbed_official 532:fe11edbda85c 2061 static void SPI_DMAEndTransmitReceive(SPI_HandleTypeDef *hspi)
mbed_official 532:fe11edbda85c 2062 {
mbed_official 532:fe11edbda85c 2063 __IO uint16_t tmpreg;
mbed_official 532:fe11edbda85c 2064
mbed_official 532:fe11edbda85c 2065 /* Reset CRC Calculation */
mbed_official 532:fe11edbda85c 2066 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official 532:fe11edbda85c 2067 {
mbed_official 532:fe11edbda85c 2068 /* Check if CRC is done on going (RXNE flag set) */
mbed_official 532:fe11edbda85c 2069 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) == HAL_OK)
mbed_official 532:fe11edbda85c 2070 {
mbed_official 532:fe11edbda85c 2071 /* Wait until RXNE flag is set to send data */
mbed_official 532:fe11edbda85c 2072 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
mbed_official 532:fe11edbda85c 2073 {
mbed_official 532:fe11edbda85c 2074 hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
mbed_official 532:fe11edbda85c 2075 }
mbed_official 532:fe11edbda85c 2076 }
mbed_official 532:fe11edbda85c 2077 /* Read CRC */
mbed_official 532:fe11edbda85c 2078 tmpreg = hspi->Instance->DR;
mbed_official 532:fe11edbda85c 2079 UNUSED(tmpreg);
mbed_official 532:fe11edbda85c 2080
mbed_official 532:fe11edbda85c 2081 /* Check if CRC error occurred */
mbed_official 532:fe11edbda85c 2082 if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
mbed_official 532:fe11edbda85c 2083 {
mbed_official 532:fe11edbda85c 2084 hspi->ErrorCode |= HAL_SPI_ERROR_CRC;
mbed_official 532:fe11edbda85c 2085 __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
mbed_official 532:fe11edbda85c 2086 }
mbed_official 532:fe11edbda85c 2087 }
mbed_official 532:fe11edbda85c 2088
mbed_official 532:fe11edbda85c 2089 /* Wait until TXE flag is set to send data */
mbed_official 532:fe11edbda85c 2090 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
mbed_official 532:fe11edbda85c 2091 {
mbed_official 532:fe11edbda85c 2092 hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
mbed_official 532:fe11edbda85c 2093 }
mbed_official 532:fe11edbda85c 2094 /* Disable Tx DMA Request */
mbed_official 532:fe11edbda85c 2095 hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
mbed_official 532:fe11edbda85c 2096
mbed_official 532:fe11edbda85c 2097 /* Wait until Busy flag is reset before disabling SPI */
mbed_official 532:fe11edbda85c 2098 if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
mbed_official 532:fe11edbda85c 2099 {
mbed_official 532:fe11edbda85c 2100 hspi->ErrorCode |= HAL_SPI_ERROR_FLAG;
mbed_official 532:fe11edbda85c 2101 }
mbed_official 532:fe11edbda85c 2102
mbed_official 532:fe11edbda85c 2103 /* Disable Rx DMA Request */
mbed_official 532:fe11edbda85c 2104 hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
mbed_official 532:fe11edbda85c 2105
mbed_official 532:fe11edbda85c 2106 hspi->TxXferCount = 0;
mbed_official 532:fe11edbda85c 2107 hspi->RxXferCount = 0;
mbed_official 532:fe11edbda85c 2108 }
mbed_official 532:fe11edbda85c 2109
mbed_official 532:fe11edbda85c 2110 /**
mbed_official 87:085cde657901 2111 * @brief DMA SPI transmit receive process complete callback
mbed_official 226:b062af740e40 2112 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 2113 * the configuration information for the specified DMA module.
mbed_official 87:085cde657901 2114 * @retval None
mbed_official 87:085cde657901 2115 */
mbed_official 87:085cde657901 2116 static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
mbed_official 87:085cde657901 2117 {
mbed_official 87:085cde657901 2118 __IO uint16_t tmpreg;
mbed_official 369:2e96f1b71984 2119
mbed_official 87:085cde657901 2120 SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official 369:2e96f1b71984 2121 if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0)
mbed_official 532:fe11edbda85c 2122 { /**/
mbed_official 532:fe11edbda85c 2123 SPI_DMAEndTransmitReceive(hspi);
mbed_official 369:2e96f1b71984 2124
mbed_official 532:fe11edbda85c 2125 hspi->State = HAL_SPI_STATE_READY;
mbed_official 369:2e96f1b71984 2126
mbed_official 369:2e96f1b71984 2127 /* Check if Errors has been detected during transfer */
mbed_official 369:2e96f1b71984 2128 if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
mbed_official 369:2e96f1b71984 2129 {
mbed_official 369:2e96f1b71984 2130 HAL_SPI_ErrorCallback(hspi);
mbed_official 369:2e96f1b71984 2131 }
mbed_official 369:2e96f1b71984 2132 else
mbed_official 369:2e96f1b71984 2133 {
mbed_official 369:2e96f1b71984 2134 HAL_SPI_TxRxCpltCallback(hspi);
mbed_official 369:2e96f1b71984 2135 }
mbed_official 87:085cde657901 2136 }
mbed_official 87:085cde657901 2137 else
mbed_official 87:085cde657901 2138 {
mbed_official 87:085cde657901 2139 HAL_SPI_TxRxCpltCallback(hspi);
mbed_official 87:085cde657901 2140 }
mbed_official 87:085cde657901 2141 }
mbed_official 87:085cde657901 2142
mbed_official 87:085cde657901 2143 /**
mbed_official 369:2e96f1b71984 2144 * @brief DMA SPI half transmit process complete callback
mbed_official 369:2e96f1b71984 2145 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
mbed_official 369:2e96f1b71984 2146 * the configuration information for the specified DMA module.
mbed_official 369:2e96f1b71984 2147 * @retval None
mbed_official 369:2e96f1b71984 2148 */
mbed_official 369:2e96f1b71984 2149 static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)
mbed_official 369:2e96f1b71984 2150 {
mbed_official 369:2e96f1b71984 2151 SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official 369:2e96f1b71984 2152
mbed_official 369:2e96f1b71984 2153 HAL_SPI_TxHalfCpltCallback(hspi);
mbed_official 369:2e96f1b71984 2154 }
mbed_official 369:2e96f1b71984 2155
mbed_official 369:2e96f1b71984 2156 /**
mbed_official 369:2e96f1b71984 2157 * @brief DMA SPI half receive process complete callback
mbed_official 369:2e96f1b71984 2158 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
mbed_official 369:2e96f1b71984 2159 * the configuration information for the specified DMA module.
mbed_official 369:2e96f1b71984 2160 * @retval None
mbed_official 369:2e96f1b71984 2161 */
mbed_official 369:2e96f1b71984 2162 static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)
mbed_official 369:2e96f1b71984 2163 {
mbed_official 369:2e96f1b71984 2164 SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official 369:2e96f1b71984 2165
mbed_official 369:2e96f1b71984 2166 HAL_SPI_RxHalfCpltCallback(hspi);
mbed_official 369:2e96f1b71984 2167 }
mbed_official 369:2e96f1b71984 2168
mbed_official 369:2e96f1b71984 2169 /**
mbed_official 369:2e96f1b71984 2170 * @brief DMA SPI Half transmit receive process complete callback
mbed_official 369:2e96f1b71984 2171 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
mbed_official 369:2e96f1b71984 2172 * the configuration information for the specified DMA module.
mbed_official 369:2e96f1b71984 2173 * @retval None
mbed_official 369:2e96f1b71984 2174 */
mbed_official 369:2e96f1b71984 2175 static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)
mbed_official 369:2e96f1b71984 2176 {
mbed_official 369:2e96f1b71984 2177 SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official 369:2e96f1b71984 2178
mbed_official 369:2e96f1b71984 2179 HAL_SPI_TxRxHalfCpltCallback(hspi);
mbed_official 369:2e96f1b71984 2180 }
mbed_official 369:2e96f1b71984 2181
mbed_official 369:2e96f1b71984 2182 /**
mbed_official 87:085cde657901 2183 * @brief DMA SPI communication error callback
mbed_official 226:b062af740e40 2184 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 2185 * the configuration information for the specified DMA module.
mbed_official 87:085cde657901 2186 * @retval None
mbed_official 87:085cde657901 2187 */
mbed_official 87:085cde657901 2188 static void SPI_DMAError(DMA_HandleTypeDef *hdma)
mbed_official 87:085cde657901 2189 {
mbed_official 87:085cde657901 2190 SPI_HandleTypeDef* hspi = (SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official 87:085cde657901 2191 hspi->TxXferCount = 0;
mbed_official 87:085cde657901 2192 hspi->RxXferCount = 0;
mbed_official 87:085cde657901 2193 hspi->State= HAL_SPI_STATE_READY;
mbed_official 87:085cde657901 2194 hspi->ErrorCode |= HAL_SPI_ERROR_DMA;
mbed_official 87:085cde657901 2195 HAL_SPI_ErrorCallback(hspi);
mbed_official 87:085cde657901 2196 }
mbed_official 87:085cde657901 2197
mbed_official 87:085cde657901 2198 /**
mbed_official 87:085cde657901 2199 * @brief This function handles SPI Communication Timeout.
mbed_official 226:b062af740e40 2200 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
mbed_official 226:b062af740e40 2201 * the configuration information for SPI module.
mbed_official 532:fe11edbda85c 2202 * @param Flag: SPI flag to check
mbed_official 532:fe11edbda85c 2203 * @param Status: Flag status to check: RESET or set
mbed_official 532:fe11edbda85c 2204 * @param Timeout: Timeout duration
mbed_official 87:085cde657901 2205 * @retval HAL status
mbed_official 87:085cde657901 2206 */
mbed_official 87:085cde657901 2207 static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
mbed_official 87:085cde657901 2208 {
mbed_official 369:2e96f1b71984 2209 uint32_t tickstart = 0;
mbed_official 87:085cde657901 2210
mbed_official 369:2e96f1b71984 2211 /* Get tick */
mbed_official 369:2e96f1b71984 2212 tickstart = HAL_GetTick();
mbed_official 87:085cde657901 2213
mbed_official 87:085cde657901 2214 /* Wait until flag is set */
mbed_official 87:085cde657901 2215 if(Status == RESET)
mbed_official 87:085cde657901 2216 {
mbed_official 87:085cde657901 2217 while(__HAL_SPI_GET_FLAG(hspi, Flag) == RESET)
mbed_official 87:085cde657901 2218 {
mbed_official 87:085cde657901 2219 if(Timeout != HAL_MAX_DELAY)
mbed_official 87:085cde657901 2220 {
mbed_official 369:2e96f1b71984 2221 if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
mbed_official 87:085cde657901 2222 {
mbed_official 87:085cde657901 2223 /* Disable the SPI and reset the CRC: the CRC value should be cleared
mbed_official 87:085cde657901 2224 on both master and slave sides in order to resynchronize the master
mbed_official 87:085cde657901 2225 and slave for their respective CRC calculation */
mbed_official 87:085cde657901 2226
mbed_official 87:085cde657901 2227 /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
mbed_official 87:085cde657901 2228 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
mbed_official 87:085cde657901 2229
mbed_official 87:085cde657901 2230 /* Disable SPI peripheral */
mbed_official 87:085cde657901 2231 __HAL_SPI_DISABLE(hspi);
mbed_official 87:085cde657901 2232
mbed_official 87:085cde657901 2233 /* Reset CRC Calculation */
mbed_official 532:fe11edbda85c 2234 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official 87:085cde657901 2235 {
mbed_official 532:fe11edbda85c 2236 SPI_RESET_CRC(hspi);
mbed_official 87:085cde657901 2237 }
mbed_official 87:085cde657901 2238
mbed_official 87:085cde657901 2239 hspi->State= HAL_SPI_STATE_READY;
mbed_official 87:085cde657901 2240
mbed_official 87:085cde657901 2241 /* Process Unlocked */
mbed_official 87:085cde657901 2242 __HAL_UNLOCK(hspi);
mbed_official 87:085cde657901 2243
mbed_official 87:085cde657901 2244 return HAL_TIMEOUT;
mbed_official 87:085cde657901 2245 }
mbed_official 87:085cde657901 2246 }
mbed_official 87:085cde657901 2247 }
mbed_official 87:085cde657901 2248 }
mbed_official 87:085cde657901 2249 else
mbed_official 87:085cde657901 2250 {
mbed_official 87:085cde657901 2251 while(__HAL_SPI_GET_FLAG(hspi, Flag) != RESET)
mbed_official 87:085cde657901 2252 {
mbed_official 87:085cde657901 2253 if(Timeout != HAL_MAX_DELAY)
mbed_official 87:085cde657901 2254 {
mbed_official 369:2e96f1b71984 2255 if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
mbed_official 87:085cde657901 2256 {
mbed_official 87:085cde657901 2257 /* Disable the SPI and reset the CRC: the CRC value should be cleared
mbed_official 87:085cde657901 2258 on both master and slave sides in order to resynchronize the master
mbed_official 87:085cde657901 2259 and slave for their respective CRC calculation */
mbed_official 87:085cde657901 2260
mbed_official 87:085cde657901 2261 /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
mbed_official 87:085cde657901 2262 __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
mbed_official 87:085cde657901 2263
mbed_official 87:085cde657901 2264 /* Disable SPI peripheral */
mbed_official 87:085cde657901 2265 __HAL_SPI_DISABLE(hspi);
mbed_official 87:085cde657901 2266
mbed_official 87:085cde657901 2267 /* Reset CRC Calculation */
mbed_official 532:fe11edbda85c 2268 if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
mbed_official 87:085cde657901 2269 {
mbed_official 532:fe11edbda85c 2270 SPI_RESET_CRC(hspi);
mbed_official 87:085cde657901 2271 }
mbed_official 87:085cde657901 2272
mbed_official 87:085cde657901 2273 hspi->State= HAL_SPI_STATE_READY;
mbed_official 87:085cde657901 2274
mbed_official 87:085cde657901 2275 /* Process Unlocked */
mbed_official 87:085cde657901 2276 __HAL_UNLOCK(hspi);
mbed_official 87:085cde657901 2277
mbed_official 87:085cde657901 2278 return HAL_TIMEOUT;
mbed_official 87:085cde657901 2279 }
mbed_official 87:085cde657901 2280 }
mbed_official 87:085cde657901 2281 }
mbed_official 87:085cde657901 2282 }
mbed_official 87:085cde657901 2283 return HAL_OK;
mbed_official 87:085cde657901 2284 }
mbed_official 87:085cde657901 2285
mbed_official 87:085cde657901 2286
mbed_official 87:085cde657901 2287 /**
mbed_official 87:085cde657901 2288 * @}
mbed_official 87:085cde657901 2289 */
mbed_official 87:085cde657901 2290
mbed_official 87:085cde657901 2291 #endif /* HAL_SPI_MODULE_ENABLED */
mbed_official 87:085cde657901 2292 /**
mbed_official 87:085cde657901 2293 * @}
mbed_official 87:085cde657901 2294 */
mbed_official 87:085cde657901 2295
mbed_official 87:085cde657901 2296 /**
mbed_official 87:085cde657901 2297 * @}
mbed_official 87:085cde657901 2298 */
mbed_official 87:085cde657901 2299
mbed_official 87:085cde657901 2300 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/