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targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_rcc_ex.c@581:39197bcd20f2, 2015-07-02 (annotated)

Committer:: mbed_official
Date:: Thu Jul 02 16:30:08 2015 +0100
Revision:: 581:39197bcd20f2
Parent:: 532:fe11edbda85c
Child:: 613:bc40b8d2aec4

Synchronized with git revision ae2d3cdffe70184eb8736d94f76c45c93f4b7724

Full URL: https://github.com/mbedmicro/mbed/commit/ae2d3cdffe70184eb8736d94f76c45c93f4b7724/

Make it possible to build the core mbed library with yotta

Who changed what in which revision?

User	Revision	Line number	New contents of line
mbed_official	235:685d5f11838f	1	/**
mbed_official	235:685d5f11838f	2	******************************************************************************
mbed_official	235:685d5f11838f	3	* @file stm32f4xx_hal_rcc_ex.c
mbed_official	235:685d5f11838f	4	* @author MCD Application Team
mbed_official	532:fe11edbda85c	5	* @version V1.3.0
mbed_official	532:fe11edbda85c	6	* @date 09-March-2015
mbed_official	235:685d5f11838f	7	* @brief Extension RCC HAL module driver.
mbed_official	235:685d5f11838f	8	* This file provides firmware functions to manage the following
mbed_official	235:685d5f11838f	9	* functionalities RCC extension peripheral:
mbed_official	235:685d5f11838f	10	* + Extended Peripheral Control functions
mbed_official	235:685d5f11838f	11	*
mbed_official	235:685d5f11838f	12	******************************************************************************
mbed_official	235:685d5f11838f	13	* @attention
mbed_official	235:685d5f11838f	14	*
mbed_official	532:fe11edbda85c	15	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
mbed_official	235:685d5f11838f	16	*
mbed_official	235:685d5f11838f	17	* Redistribution and use in source and binary forms, with or without modification,
mbed_official	235:685d5f11838f	18	* are permitted provided that the following conditions are met:
mbed_official	235:685d5f11838f	19	* 1. Redistributions of source code must retain the above copyright notice,
mbed_official	235:685d5f11838f	20	* this list of conditions and the following disclaimer.
mbed_official	235:685d5f11838f	21	* 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official	235:685d5f11838f	22	* this list of conditions and the following disclaimer in the documentation
mbed_official	235:685d5f11838f	23	* and/or other materials provided with the distribution.
mbed_official	235:685d5f11838f	24	* 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official	235:685d5f11838f	25	* may be used to endorse or promote products derived from this software
mbed_official	235:685d5f11838f	26	* without specific prior written permission.
mbed_official	235:685d5f11838f	27	*
mbed_official	235:685d5f11838f	28	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official	235:685d5f11838f	29	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official	235:685d5f11838f	30	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official	235:685d5f11838f	31	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official	235:685d5f11838f	32	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official	235:685d5f11838f	33	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official	235:685d5f11838f	34	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official	235:685d5f11838f	35	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official	235:685d5f11838f	36	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official	235:685d5f11838f	37	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official	235:685d5f11838f	38	*
mbed_official	235:685d5f11838f	39	******************************************************************************
mbed_official	235:685d5f11838f	40	*/
mbed_official	235:685d5f11838f	41
mbed_official	235:685d5f11838f	42	/* Includes ------------------------------------------------------------------*/
mbed_official	235:685d5f11838f	43	#include "stm32f4xx_hal.h"
mbed_official	235:685d5f11838f	44
mbed_official	235:685d5f11838f	45	/** @addtogroup STM32F4xx_HAL_Driver
mbed_official	235:685d5f11838f	46	* @{
mbed_official	235:685d5f11838f	47	*/
mbed_official	235:685d5f11838f	48
mbed_official	532:fe11edbda85c	49	/** @defgroup RCCEx RCCEx
mbed_official	532:fe11edbda85c	50	* @brief RCCEx HAL module driver
mbed_official	235:685d5f11838f	51	* @{
mbed_official	235:685d5f11838f	52	*/
mbed_official	235:685d5f11838f	53
mbed_official	235:685d5f11838f	54	#ifdef HAL_RCC_MODULE_ENABLED
mbed_official	235:685d5f11838f	55
mbed_official	235:685d5f11838f	56	/* Private typedef -----------------------------------------------------------*/
mbed_official	235:685d5f11838f	57	/* Private define ------------------------------------------------------------*/
mbed_official	532:fe11edbda85c	58	/** @addtogroup RCCEx_Private_Constants
mbed_official	532:fe11edbda85c	59	* @{
mbed_official	532:fe11edbda85c	60	*/
mbed_official	532:fe11edbda85c	61	/**
mbed_official	532:fe11edbda85c	62	* @}
mbed_official	532:fe11edbda85c	63	*/
mbed_official	235:685d5f11838f	64	/* Private macro -------------------------------------------------------------*/
mbed_official	235:685d5f11838f	65	/* Private variables ---------------------------------------------------------*/
mbed_official	235:685d5f11838f	66	/* Private function prototypes -----------------------------------------------*/
mbed_official	235:685d5f11838f	67	/* Private functions ---------------------------------------------------------*/
mbed_official	532:fe11edbda85c	68	/** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions
mbed_official	532:fe11edbda85c	69	* @{
mbed_official	235:685d5f11838f	70	*/
mbed_official	235:685d5f11838f	71
mbed_official	532:fe11edbda85c	72	/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions
mbed_official	235:685d5f11838f	73	* @brief Extended Peripheral Control functions
mbed_official	235:685d5f11838f	74	*
mbed_official	235:685d5f11838f	75	@verbatim
mbed_official	235:685d5f11838f	76	===============================================================================
mbed_official	235:685d5f11838f	77	##### Extended Peripheral Control functions #####
mbed_official	235:685d5f11838f	78	===============================================================================
mbed_official	235:685d5f11838f	79	[..]
mbed_official	235:685d5f11838f	80	This subsection provides a set of functions allowing to control the RCC Clocks
mbed_official	235:685d5f11838f	81	frequencies.
mbed_official	235:685d5f11838f	82	[..]
mbed_official	235:685d5f11838f	83	(@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
mbed_official	235:685d5f11838f	84	select the RTC clock source; in this case the Backup domain will be reset in
mbed_official	235:685d5f11838f	85	order to modify the RTC Clock source, as consequence RTC registers (including
mbed_official	235:685d5f11838f	86	the backup registers) and RCC_BDCR register are set to their reset values.
mbed_official	235:685d5f11838f	87
mbed_official	235:685d5f11838f	88	@endverbatim
mbed_official	235:685d5f11838f	89	* @{
mbed_official	235:685d5f11838f	90	*/
mbed_official	532:fe11edbda85c	91	#if defined(STM32F446xx)
mbed_official	235:685d5f11838f	92	/**
mbed_official	235:685d5f11838f	93	* @brief Initializes the RCC extended peripherals clocks according to the specified
mbed_official	235:685d5f11838f	94	* parameters in the RCC_PeriphCLKInitTypeDef.
mbed_official	235:685d5f11838f	95	* @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
mbed_official	235:685d5f11838f	96	* contains the configuration information for the Extended Peripherals
mbed_official	235:685d5f11838f	97	* clocks(I2S, SAI, LTDC RTC and TIM).
mbed_official	235:685d5f11838f	98	*
mbed_official	235:685d5f11838f	99	* @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
mbed_official	235:685d5f11838f	100	* the RTC clock source; in this case the Backup domain will be reset in
mbed_official	235:685d5f11838f	101	* order to modify the RTC Clock source, as consequence RTC registers (including
mbed_official	235:685d5f11838f	102	* the backup registers) and RCC_BDCR register are set to their reset values.
mbed_official	235:685d5f11838f	103	*
mbed_official	235:685d5f11838f	104	* @retval HAL status
mbed_official	235:685d5f11838f	105	*/
mbed_official	235:685d5f11838f	106	HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
mbed_official	235:685d5f11838f	107	{
mbed_official	235:685d5f11838f	108	uint32_t tickstart = 0;
mbed_official	532:fe11edbda85c	109	uint32_t tmpreg1 = 0;
mbed_official	532:fe11edbda85c	110	uint32_t plli2sp = 0;
mbed_official	532:fe11edbda85c	111	uint32_t plli2sq = 0;
mbed_official	532:fe11edbda85c	112	uint32_t plli2sr = 0;
mbed_official	532:fe11edbda85c	113	uint32_t pllsaip = 0;
mbed_official	532:fe11edbda85c	114	uint32_t pllsaiq = 0;
mbed_official	532:fe11edbda85c	115	uint32_t plli2sused = 0;
mbed_official	532:fe11edbda85c	116	uint32_t pllsaiused = 0;
mbed_official	532:fe11edbda85c	117
mbed_official	532:fe11edbda85c	118	/* Check the peripheral clock selection parameters */
mbed_official	532:fe11edbda85c	119	assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
mbed_official	532:fe11edbda85c	120
mbed_official	532:fe11edbda85c	121	/----------------------------------- I2S APB1 configuration ----------------------------------/
mbed_official	532:fe11edbda85c	122	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == (RCC_PERIPHCLK_I2S_APB1))
mbed_official	532:fe11edbda85c	123	{
mbed_official	532:fe11edbda85c	124	/* Check the parameters */
mbed_official	532:fe11edbda85c	125	assert_param(IS_RCC_I2SAPB1CLKSOURCE(PeriphClkInit->I2sApb1ClockSelection));
mbed_official	532:fe11edbda85c	126
mbed_official	532:fe11edbda85c	127	/* Configure I2S Clock source */
mbed_official	532:fe11edbda85c	128	__HAL_RCC_I2S_APB1_CONFIG(PeriphClkInit->I2sApb1ClockSelection);
mbed_official	532:fe11edbda85c	129	/* Enable the PLLI2S when it's used as clock source for I2S */
mbed_official	532:fe11edbda85c	130	if(PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S)
mbed_official	532:fe11edbda85c	131	{
mbed_official	532:fe11edbda85c	132	plli2sused = 1;
mbed_official	532:fe11edbda85c	133	}
mbed_official	532:fe11edbda85c	134	}
mbed_official	532:fe11edbda85c	135
mbed_official	532:fe11edbda85c	136	/----------------------------------- I2S APB2 configuration -----------------------------------/
mbed_official	532:fe11edbda85c	137	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == (RCC_PERIPHCLK_I2S_APB2))
mbed_official	532:fe11edbda85c	138	{
mbed_official	532:fe11edbda85c	139	/* Check the parameters */
mbed_official	532:fe11edbda85c	140	assert_param(IS_RCC_I2SAPB2CLKSOURCE(PeriphClkInit->I2sApb2ClockSelection));
mbed_official	532:fe11edbda85c	141
mbed_official	532:fe11edbda85c	142	/* Configure I2S Clock source */
mbed_official	532:fe11edbda85c	143	__HAL_RCC_I2S_APB2_CONFIG(PeriphClkInit->I2sApb2ClockSelection);
mbed_official	532:fe11edbda85c	144	/* Enable the PLLI2S when it's used as clock source for I2S */
mbed_official	532:fe11edbda85c	145	if(PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S)
mbed_official	532:fe11edbda85c	146	{
mbed_official	532:fe11edbda85c	147	plli2sused = 1;
mbed_official	532:fe11edbda85c	148	}
mbed_official	532:fe11edbda85c	149	}
mbed_official	532:fe11edbda85c	150
mbed_official	532:fe11edbda85c	151	/------------------------------------ SAI1 configuration --------------------------------------/
mbed_official	532:fe11edbda85c	152	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == (RCC_PERIPHCLK_SAI1))
mbed_official	532:fe11edbda85c	153	{
mbed_official	532:fe11edbda85c	154	/* Check the parameters */
mbed_official	532:fe11edbda85c	155	assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection));
mbed_official	532:fe11edbda85c	156
mbed_official	532:fe11edbda85c	157	/* Configure SAI1 Clock source */
mbed_official	532:fe11edbda85c	158	__HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
mbed_official	532:fe11edbda85c	159	/* Enable the PLLI2S when it's used as clock source for SAI */
mbed_official	532:fe11edbda85c	160	if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)
mbed_official	532:fe11edbda85c	161	{
mbed_official	532:fe11edbda85c	162	plli2sused = 1;
mbed_official	532:fe11edbda85c	163	}
mbed_official	532:fe11edbda85c	164	/* Enable the PLLSAI when it's used as clock source for SAI */
mbed_official	532:fe11edbda85c	165	if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)
mbed_official	532:fe11edbda85c	166	{
mbed_official	532:fe11edbda85c	167	pllsaiused = 1;
mbed_official	532:fe11edbda85c	168	}
mbed_official	532:fe11edbda85c	169	}
mbed_official	532:fe11edbda85c	170
mbed_official	532:fe11edbda85c	171	/------------------------------------ SAI2 configuration --------------------------------------/
mbed_official	532:fe11edbda85c	172	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == (RCC_PERIPHCLK_SAI2))
mbed_official	532:fe11edbda85c	173	{
mbed_official	532:fe11edbda85c	174	/* Check the parameters */
mbed_official	532:fe11edbda85c	175	assert_param(IS_RCC_SAI2CLKSOURCE(PeriphClkInit->Sai2ClockSelection));
mbed_official	532:fe11edbda85c	176
mbed_official	532:fe11edbda85c	177	/* Configure SAI2 Clock source */
mbed_official	532:fe11edbda85c	178	__HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection);
mbed_official	532:fe11edbda85c	179
mbed_official	532:fe11edbda85c	180	/* Enable the PLLI2S when it's used as clock source for SAI */
mbed_official	532:fe11edbda85c	181	if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)
mbed_official	532:fe11edbda85c	182	{
mbed_official	532:fe11edbda85c	183	plli2sused = 1;
mbed_official	532:fe11edbda85c	184	}
mbed_official	532:fe11edbda85c	185	/* Enable the PLLSAI when it's used as clock source for SAI */
mbed_official	532:fe11edbda85c	186	if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)
mbed_official	532:fe11edbda85c	187	{
mbed_official	532:fe11edbda85c	188	pllsaiused = 1;
mbed_official	532:fe11edbda85c	189	}
mbed_official	532:fe11edbda85c	190	}
mbed_official	532:fe11edbda85c	191
mbed_official	532:fe11edbda85c	192	/------------------------------------ RTC configuration --------------------------------------/
mbed_official	532:fe11edbda85c	193	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
mbed_official	532:fe11edbda85c	194	{
mbed_official	532:fe11edbda85c	195	/* Enable Power Clock*/
mbed_official	532:fe11edbda85c	196	__HAL_RCC_PWR_CLK_ENABLE();
mbed_official	532:fe11edbda85c	197
mbed_official	532:fe11edbda85c	198	/* Enable write access to Backup domain */
mbed_official	532:fe11edbda85c	199	PWR->CR \|= PWR_CR_DBP;
mbed_official	532:fe11edbda85c	200
mbed_official	532:fe11edbda85c	201	/* Get tick */
mbed_official	532:fe11edbda85c	202	tickstart = HAL_GetTick();
mbed_official	532:fe11edbda85c	203
mbed_official	532:fe11edbda85c	204	while((PWR->CR & PWR_CR_DBP) == RESET)
mbed_official	532:fe11edbda85c	205	{
mbed_official	532:fe11edbda85c	206	if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
mbed_official	532:fe11edbda85c	207	{
mbed_official	532:fe11edbda85c	208	return HAL_TIMEOUT;
mbed_official	532:fe11edbda85c	209	}
mbed_official	532:fe11edbda85c	210	}
mbed_official	532:fe11edbda85c	211
mbed_official	532:fe11edbda85c	212	/* Reset the Backup domain only if the RTC Clock source selction is modified */
mbed_official	532:fe11edbda85c	213	if((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))
mbed_official	532:fe11edbda85c	214	{
mbed_official	532:fe11edbda85c	215	/* Store the content of BDCR register before the reset of Backup Domain */
mbed_official	532:fe11edbda85c	216	tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
mbed_official	532:fe11edbda85c	217	/* RTC Clock selection can be changed only if the Backup Domain is reset */
mbed_official	532:fe11edbda85c	218	__HAL_RCC_BACKUPRESET_FORCE();
mbed_official	532:fe11edbda85c	219	__HAL_RCC_BACKUPRESET_RELEASE();
mbed_official	532:fe11edbda85c	220	/* Restore the Content of BDCR register */
mbed_official	532:fe11edbda85c	221	RCC->BDCR = tmpreg1;
mbed_official	532:fe11edbda85c	222	}
mbed_official	532:fe11edbda85c	223
mbed_official	532:fe11edbda85c	224	/* If LSE is selected as RTC clock source, wait for LSE reactivation */
mbed_official	532:fe11edbda85c	225	if(PeriphClkInit->RTCClockSelection == RCC_RTCCLKSOURCE_LSE)
mbed_official	532:fe11edbda85c	226	{
mbed_official	532:fe11edbda85c	227	/* Get tick */
mbed_official	532:fe11edbda85c	228	tickstart = HAL_GetTick();
mbed_official	532:fe11edbda85c	229
mbed_official	532:fe11edbda85c	230	/* Wait till LSE is ready */
mbed_official	532:fe11edbda85c	231	while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
mbed_official	532:fe11edbda85c	232	{
mbed_official	532:fe11edbda85c	233	if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
mbed_official	532:fe11edbda85c	234	{
mbed_official	532:fe11edbda85c	235	return HAL_TIMEOUT;
mbed_official	532:fe11edbda85c	236	}
mbed_official	532:fe11edbda85c	237	}
mbed_official	532:fe11edbda85c	238	}
mbed_official	532:fe11edbda85c	239	__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
mbed_official	532:fe11edbda85c	240	}
mbed_official	532:fe11edbda85c	241
mbed_official	532:fe11edbda85c	242	/------------------------------------ TIM configuration --------------------------------------/
mbed_official	532:fe11edbda85c	243	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
mbed_official	532:fe11edbda85c	244	{
mbed_official	532:fe11edbda85c	245	/* Configure Timer Prescaler */
mbed_official	532:fe11edbda85c	246	__HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
mbed_official	532:fe11edbda85c	247	}
mbed_official	532:fe11edbda85c	248
mbed_official	532:fe11edbda85c	249	/------------------------------------- FMPI2C1 Configuration ----------------------------------/
mbed_official	532:fe11edbda85c	250	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMPI2C1) == RCC_PERIPHCLK_FMPI2C1)
mbed_official	532:fe11edbda85c	251	{
mbed_official	532:fe11edbda85c	252	/* Check the parameters */
mbed_official	532:fe11edbda85c	253	assert_param(IS_RCC_FMPI2C1CLKSOURCE(PeriphClkInit->Fmpi2c1ClockSelection));
mbed_official	532:fe11edbda85c	254
mbed_official	532:fe11edbda85c	255	/* Configure the FMPI2C1 clock source */
mbed_official	532:fe11edbda85c	256	__HAL_RCC_FMPI2C1_CONFIG(PeriphClkInit->Fmpi2c1ClockSelection);
mbed_official	532:fe11edbda85c	257	}
mbed_official	532:fe11edbda85c	258
mbed_official	532:fe11edbda85c	259	/--------------------------------------- CEC Configuration -----------------------------------/
mbed_official	532:fe11edbda85c	260	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC)
mbed_official	532:fe11edbda85c	261	{
mbed_official	532:fe11edbda85c	262	/* Check the parameters */
mbed_official	532:fe11edbda85c	263	assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection));
mbed_official	532:fe11edbda85c	264
mbed_official	532:fe11edbda85c	265	/* Configure the CEC clock source */
mbed_official	532:fe11edbda85c	266	__HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection);
mbed_official	532:fe11edbda85c	267	}
mbed_official	532:fe11edbda85c	268
mbed_official	532:fe11edbda85c	269	/-------------------------------------- CK48 Configuration -----------------------------------/
mbed_official	532:fe11edbda85c	270	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CK48) == RCC_PERIPHCLK_CK48)
mbed_official	532:fe11edbda85c	271	{
mbed_official	532:fe11edbda85c	272	/* Check the parameters */
mbed_official	532:fe11edbda85c	273	assert_param(IS_RCC_CK48CLKSOURCE(PeriphClkInit->Clk48ClockSelection));
mbed_official	532:fe11edbda85c	274
mbed_official	532:fe11edbda85c	275	/* Configure the SDIO clock source */
mbed_official	532:fe11edbda85c	276	__HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection);
mbed_official	532:fe11edbda85c	277
mbed_official	532:fe11edbda85c	278	/* Enable the PLLSAI when it's used as clock source for CK48 */
mbed_official	532:fe11edbda85c	279	if(PeriphClkInit->Clk48ClockSelection == RCC_CK48CLKSOURCE_PLLSAIP)
mbed_official	532:fe11edbda85c	280	{
mbed_official	532:fe11edbda85c	281	pllsaiused = 1;
mbed_official	532:fe11edbda85c	282	}
mbed_official	532:fe11edbda85c	283	}
mbed_official	532:fe11edbda85c	284
mbed_official	532:fe11edbda85c	285	/------------------------------------- SDIO Configuration ------------------------------------/
mbed_official	532:fe11edbda85c	286	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDIO) == RCC_PERIPHCLK_SDIO)
mbed_official	532:fe11edbda85c	287	{
mbed_official	532:fe11edbda85c	288	/* Check the parameters */
mbed_official	532:fe11edbda85c	289	assert_param(IS_RCC_SDIOCLKSOURCE(PeriphClkInit->SdioClockSelection));
mbed_official	532:fe11edbda85c	290
mbed_official	532:fe11edbda85c	291	/* Configure the SDIO clock source */
mbed_official	532:fe11edbda85c	292	__HAL_RCC_SDIO_CONFIG(PeriphClkInit->SdioClockSelection);
mbed_official	532:fe11edbda85c	293	}
mbed_official	532:fe11edbda85c	294
mbed_official	532:fe11edbda85c	295	/------------------------------------- SPDIFRX Configuration --------------/
mbed_official	532:fe11edbda85c	296	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX)
mbed_official	532:fe11edbda85c	297	{
mbed_official	532:fe11edbda85c	298	/* Check the parameters */
mbed_official	532:fe11edbda85c	299	assert_param(IS_RCC_SPDIFRXCLKSOURCE(PeriphClkInit->SpdifClockSelection));
mbed_official	532:fe11edbda85c	300
mbed_official	532:fe11edbda85c	301	/* Configure the SPDIFRX clock source */
mbed_official	532:fe11edbda85c	302	__HAL_RCC_SPDIFRX_CONFIG(PeriphClkInit->SpdifClockSelection);
mbed_official	532:fe11edbda85c	303	/* Enable the PLLI2S when it's used as clock source for SPDIFRX */
mbed_official	532:fe11edbda85c	304	if(PeriphClkInit->SpdifClockSelection == RCC_SPDIFRXCLKSOURCE_PLLI2SP)
mbed_official	532:fe11edbda85c	305	{
mbed_official	532:fe11edbda85c	306	plli2sused = 1;
mbed_official	532:fe11edbda85c	307	}
mbed_official	532:fe11edbda85c	308	}
mbed_official	532:fe11edbda85c	309
mbed_official	532:fe11edbda85c	310	/-------------------------------------- PLLI2S Configuration --------------/
mbed_official	532:fe11edbda85c	311	/* PLLI2S is configured when a peripheral will use it as source clock : SAI1, SAI2, I2S on APB1,
mbed_official	532:fe11edbda85c	312	I2S on APB2 or SPDIFRX */
mbed_official	532:fe11edbda85c	313	if((plli2sused == 1) \|\| (PeriphClkInit->PeriphClockSelection == RCC_PERIPHCLK_PLLI2S))
mbed_official	532:fe11edbda85c	314	{
mbed_official	532:fe11edbda85c	315	/* Disable the PLLI2S */
mbed_official	532:fe11edbda85c	316	__HAL_RCC_PLLI2S_DISABLE();
mbed_official	532:fe11edbda85c	317	/* Get tick */
mbed_official	532:fe11edbda85c	318	tickstart = HAL_GetTick();
mbed_official	532:fe11edbda85c	319	/* Wait till PLLI2S is disabled */
mbed_official	532:fe11edbda85c	320	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
mbed_official	532:fe11edbda85c	321	{
mbed_official	532:fe11edbda85c	322	if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
mbed_official	532:fe11edbda85c	323	{
mbed_official	532:fe11edbda85c	324	/* return in case of Timeout detected */
mbed_official	532:fe11edbda85c	325	return HAL_TIMEOUT;
mbed_official	532:fe11edbda85c	326	}
mbed_official	532:fe11edbda85c	327	}
mbed_official	532:fe11edbda85c	328
mbed_official	532:fe11edbda85c	329	/* check for common PLLI2S Parameters */
mbed_official	532:fe11edbda85c	330	assert_param(IS_RCC_PLLI2SM_VALUE(PeriphClkInit->PLLI2S.PLLI2SM));
mbed_official	532:fe11edbda85c	331	assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
mbed_official	532:fe11edbda85c	332
mbed_official	532:fe11edbda85c	333	/----------------- In Case of PLLI2S is selected as source clock for I2S -------------------/
mbed_official	532:fe11edbda85c	334	if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == RCC_PERIPHCLK_I2S_APB1) && (PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S)) \|\|
mbed_official	532:fe11edbda85c	335	((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == RCC_PERIPHCLK_I2S_APB2) && (PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S)))
mbed_official	532:fe11edbda85c	336	{
mbed_official	532:fe11edbda85c	337	/* check for Parameters */
mbed_official	532:fe11edbda85c	338	assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
mbed_official	532:fe11edbda85c	339
mbed_official	532:fe11edbda85c	340	/* Read PLLI2SP/PLLI2SQ value from PLLI2SCFGR register (this value is not needed for I2S configuration) */
mbed_official	532:fe11edbda85c	341	plli2sp = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP)) + 1) << 1);
mbed_official	532:fe11edbda85c	342	plli2sq = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ));
mbed_official	532:fe11edbda85c	343	/* Configure the PLLI2S division factors */
mbed_official	532:fe11edbda85c	344	/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) × (PLLI2SN/PLLI2SM) */
mbed_official	532:fe11edbda85c	345	/* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
mbed_official	532:fe11edbda85c	346	__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , plli2sp, plli2sq, PeriphClkInit->PLLI2S.PLLI2SR);
mbed_official	532:fe11edbda85c	347	}
mbed_official	532:fe11edbda85c	348
mbed_official	532:fe11edbda85c	349	/----------------- In Case of PLLI2S is selected as source clock for SAI -------------------/
mbed_official	532:fe11edbda85c	350	if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) \|\|
mbed_official	532:fe11edbda85c	351	((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)))
mbed_official	532:fe11edbda85c	352	{
mbed_official	532:fe11edbda85c	353	/* Check for PLLI2S Parameters */
mbed_official	532:fe11edbda85c	354	assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
mbed_official	532:fe11edbda85c	355	/* Check for PLLI2S/DIVQ parameters */
mbed_official	532:fe11edbda85c	356	assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ));
mbed_official	532:fe11edbda85c	357
mbed_official	532:fe11edbda85c	358	/* Read PLLI2SP/PLLI2SR value from PLLI2SCFGR register (this value is not needed for SAI configuration) */
mbed_official	532:fe11edbda85c	359	plli2sp = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP)) + 1) << 1);
mbed_official	532:fe11edbda85c	360	plli2sr = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
mbed_official	532:fe11edbda85c	361	/* Configure the PLLI2S division factors */
mbed_official	532:fe11edbda85c	362	/* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */
mbed_official	532:fe11edbda85c	363	/* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
mbed_official	532:fe11edbda85c	364	/* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
mbed_official	532:fe11edbda85c	365	__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , plli2sp, PeriphClkInit->PLLI2S.PLLI2SQ, plli2sr);
mbed_official	532:fe11edbda85c	366
mbed_official	532:fe11edbda85c	367	/* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
mbed_official	532:fe11edbda85c	368	__HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ);
mbed_official	532:fe11edbda85c	369	}
mbed_official	532:fe11edbda85c	370
mbed_official	532:fe11edbda85c	371	/----------------- In Case of PLLI2S is selected as source clock for SPDIFRX -------------------/
mbed_official	532:fe11edbda85c	372	if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) && (PeriphClkInit->SpdifClockSelection == RCC_SPDIFRXCLKSOURCE_PLLI2SP))
mbed_official	532:fe11edbda85c	373	{
mbed_official	532:fe11edbda85c	374	/* check for Parameters */
mbed_official	532:fe11edbda85c	375	assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP));
mbed_official	532:fe11edbda85c	376	/* Read PLLI2SR value from PLLI2SCFGR register (this value is not need for SAI configuration) */
mbed_official	532:fe11edbda85c	377	plli2sq = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP)) + 1) << 1);
mbed_official	532:fe11edbda85c	378	plli2sr = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
mbed_official	532:fe11edbda85c	379	/* Configure the PLLI2S division factors */
mbed_official	532:fe11edbda85c	380	/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) × (PLLI2SN/PLLI2SM) */
mbed_official	532:fe11edbda85c	381	/* SPDIFRXCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */
mbed_official	532:fe11edbda85c	382	__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, plli2sq, plli2sr);
mbed_official	532:fe11edbda85c	383	}
mbed_official	532:fe11edbda85c	384
mbed_official	532:fe11edbda85c	385	/----------------- In Case of PLLI2S is just selected -----------------/
mbed_official	532:fe11edbda85c	386	if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)
mbed_official	532:fe11edbda85c	387	{
mbed_official	532:fe11edbda85c	388	/* Check for Parameters */
mbed_official	532:fe11edbda85c	389	assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP));
mbed_official	532:fe11edbda85c	390	assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
mbed_official	532:fe11edbda85c	391	assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
mbed_official	532:fe11edbda85c	392
mbed_official	532:fe11edbda85c	393	/* Configure the PLLI2S division factors */
mbed_official	532:fe11edbda85c	394	/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) × (PLLI2SN/PLLI2SM) */
mbed_official	532:fe11edbda85c	395	/* SPDIFRXCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */
mbed_official	532:fe11edbda85c	396	__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR);
mbed_official	532:fe11edbda85c	397	}
mbed_official	532:fe11edbda85c	398
mbed_official	532:fe11edbda85c	399	/* Enable the PLLI2S */
mbed_official	532:fe11edbda85c	400	__HAL_RCC_PLLI2S_ENABLE();
mbed_official	532:fe11edbda85c	401	/* Get tick */
mbed_official	532:fe11edbda85c	402	tickstart = HAL_GetTick();
mbed_official	532:fe11edbda85c	403	/* Wait till PLLI2S is ready */
mbed_official	532:fe11edbda85c	404	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
mbed_official	532:fe11edbda85c	405	{
mbed_official	532:fe11edbda85c	406	if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
mbed_official	532:fe11edbda85c	407	{
mbed_official	532:fe11edbda85c	408	/* return in case of Timeout detected */
mbed_official	532:fe11edbda85c	409	return HAL_TIMEOUT;
mbed_official	532:fe11edbda85c	410	}
mbed_official	532:fe11edbda85c	411	}
mbed_official	532:fe11edbda85c	412	}
mbed_official	532:fe11edbda85c	413	/-------------------------------------- PLLSAI Configuration ---------------------------------/
mbed_official	532:fe11edbda85c	414	/* PLLSAI is configured when a peripheral will use it as source clock : SAI1, SAI2, CK48 or SDIO */
mbed_official	532:fe11edbda85c	415	if(pllsaiused == 1)
mbed_official	532:fe11edbda85c	416	{
mbed_official	532:fe11edbda85c	417	/* Disable PLLSAI Clock */
mbed_official	532:fe11edbda85c	418	__HAL_RCC_PLLSAI_DISABLE();
mbed_official	532:fe11edbda85c	419	/* Get tick */
mbed_official	532:fe11edbda85c	420	tickstart = HAL_GetTick();
mbed_official	532:fe11edbda85c	421	/* Wait till PLLSAI is disabled */
mbed_official	532:fe11edbda85c	422	while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
mbed_official	532:fe11edbda85c	423	{
mbed_official	532:fe11edbda85c	424	if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
mbed_official	532:fe11edbda85c	425	{
mbed_official	532:fe11edbda85c	426	/* return in case of Timeout detected */
mbed_official	532:fe11edbda85c	427	return HAL_TIMEOUT;
mbed_official	532:fe11edbda85c	428	}
mbed_official	532:fe11edbda85c	429	}
mbed_official	532:fe11edbda85c	430
mbed_official	532:fe11edbda85c	431	/* Check the PLLSAI division factors */
mbed_official	532:fe11edbda85c	432	assert_param(IS_RCC_PLLSAIM_VALUE(PeriphClkInit->PLLSAI.PLLSAIM));
mbed_official	532:fe11edbda85c	433	assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN));
mbed_official	532:fe11edbda85c	434
mbed_official	532:fe11edbda85c	435	/----------------- In Case of PLLSAI is selected as source clock for SAI -------------------/
mbed_official	532:fe11edbda85c	436	if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) \|\|
mbed_official	532:fe11edbda85c	437	((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)))
mbed_official	532:fe11edbda85c	438	{
mbed_official	532:fe11edbda85c	439	/* check for PLLSAIQ Parameter */
mbed_official	532:fe11edbda85c	440	assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ));
mbed_official	532:fe11edbda85c	441	/* check for PLLSAI/DIVQ Parameter */
mbed_official	532:fe11edbda85c	442	assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ));
mbed_official	532:fe11edbda85c	443
mbed_official	532:fe11edbda85c	444	/* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */
mbed_official	532:fe11edbda85c	445	pllsaip = ((((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP)) + 1) << 1);
mbed_official	532:fe11edbda85c	446	/* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
mbed_official	532:fe11edbda85c	447	/* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
mbed_official	532:fe11edbda85c	448	/* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
mbed_official	532:fe11edbda85c	449	__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIM, PeriphClkInit->PLLSAI.PLLSAIN , pllsaip, PeriphClkInit->PLLSAI.PLLSAIQ, 0);
mbed_official	532:fe11edbda85c	450
mbed_official	532:fe11edbda85c	451	/* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
mbed_official	532:fe11edbda85c	452	__HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ);
mbed_official	532:fe11edbda85c	453	}
mbed_official	532:fe11edbda85c	454
mbed_official	532:fe11edbda85c	455	/----------------- In Case of PLLSAI is selected as source clock for CK48 -------------------/
mbed_official	532:fe11edbda85c	456	/* In Case of PLLI2S is selected as source clock for CK48 */
mbed_official	532:fe11edbda85c	457	if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CK48) == RCC_PERIPHCLK_CK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CK48CLKSOURCE_PLLSAIP))
mbed_official	532:fe11edbda85c	458	{
mbed_official	532:fe11edbda85c	459	/* check for Parameters */
mbed_official	532:fe11edbda85c	460	assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP));
mbed_official	532:fe11edbda85c	461	/* Read PLLSAIQ value from PLLI2SCFGR register (this value is not need for SAI configuration) */
mbed_official	532:fe11edbda85c	462	pllsaiq = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ));
mbed_official	532:fe11edbda85c	463	/* Configure the PLLSAI division factors */
mbed_official	532:fe11edbda85c	464	/* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) × (PLLI2SN/PLLSAIM) */
mbed_official	532:fe11edbda85c	465	/* 48CLK = f(PLLSAI clock output) = f(VCO clock) / PLLSAIP */
mbed_official	532:fe11edbda85c	466	__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIM, PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIP, pllsaiq, 0);
mbed_official	532:fe11edbda85c	467	}
mbed_official	532:fe11edbda85c	468
mbed_official	532:fe11edbda85c	469	/* Enable PLLSAI Clock */
mbed_official	532:fe11edbda85c	470	__HAL_RCC_PLLSAI_ENABLE();
mbed_official	532:fe11edbda85c	471	/* Get tick */
mbed_official	532:fe11edbda85c	472	tickstart = HAL_GetTick();
mbed_official	532:fe11edbda85c	473	/* Wait till PLLSAI is ready */
mbed_official	532:fe11edbda85c	474	while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
mbed_official	532:fe11edbda85c	475	{
mbed_official	532:fe11edbda85c	476	if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
mbed_official	532:fe11edbda85c	477	{
mbed_official	532:fe11edbda85c	478	/* return in case of Timeout detected */
mbed_official	532:fe11edbda85c	479	return HAL_TIMEOUT;
mbed_official	532:fe11edbda85c	480	}
mbed_official	532:fe11edbda85c	481	}
mbed_official	532:fe11edbda85c	482	}
mbed_official	532:fe11edbda85c	483	return HAL_OK;
mbed_official	532:fe11edbda85c	484	}
mbed_official	532:fe11edbda85c	485
mbed_official	532:fe11edbda85c	486	/**
mbed_official	532:fe11edbda85c	487	* @brief Get the RCC_PeriphCLKInitTypeDef according to the internal
mbed_official	532:fe11edbda85c	488	* RCC configuration registers.
mbed_official	532:fe11edbda85c	489	* @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
mbed_official	532:fe11edbda85c	490	* will be configured.
mbed_official	532:fe11edbda85c	491	* @retval None
mbed_official	532:fe11edbda85c	492	*/
mbed_official	532:fe11edbda85c	493	void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
mbed_official	532:fe11edbda85c	494	{
mbed_official	532:fe11edbda85c	495	uint32_t tempreg;
mbed_official	532:fe11edbda85c	496
mbed_official	532:fe11edbda85c	497	/* Set all possible values for the extended clock type parameter------------*/
mbed_official	532:fe11edbda85c	498	PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S_APB1 \| RCC_PERIPHCLK_I2S_APB2 \|\
mbed_official	532:fe11edbda85c	499	RCC_PERIPHCLK_SAI1 \| RCC_PERIPHCLK_SAI2 \|\
mbed_official	532:fe11edbda85c	500	RCC_PERIPHCLK_TIM \| RCC_PERIPHCLK_RTC \|\
mbed_official	532:fe11edbda85c	501	RCC_PERIPHCLK_CEC \| RCC_PERIPHCLK_FMPI2C1 \|\
mbed_official	532:fe11edbda85c	502	RCC_PERIPHCLK_CK48 \| RCC_PERIPHCLK_SDIO \|\
mbed_official	532:fe11edbda85c	503	RCC_PERIPHCLK_SPDIFRX;
mbed_official	532:fe11edbda85c	504
mbed_official	532:fe11edbda85c	505	/* Get the PLLI2S Clock configuration -----------------------------------------------*/
mbed_official	532:fe11edbda85c	506	PeriphClkInit->PLLI2S.PLLI2SM = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SM));
mbed_official	532:fe11edbda85c	507	PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN));
mbed_official	532:fe11edbda85c	508	PeriphClkInit->PLLI2S.PLLI2SP = (uint32_t)((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP)) + 1) << 1);
mbed_official	532:fe11edbda85c	509	PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ));
mbed_official	532:fe11edbda85c	510	PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
mbed_official	532:fe11edbda85c	511	/* Get the PLLSAI Clock configuration -----------------------------------------------*/
mbed_official	532:fe11edbda85c	512	PeriphClkInit->PLLSAI.PLLSAIM = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIM) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIM));
mbed_official	532:fe11edbda85c	513	PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN));
mbed_official	532:fe11edbda85c	514	PeriphClkInit->PLLSAI.PLLSAIP = (uint32_t)((((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP)) + 1) << 1);
mbed_official	532:fe11edbda85c	515	PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ));
mbed_official	532:fe11edbda85c	516	/* Get the PLLSAI/PLLI2S division factors -------------------------------------------*/
mbed_official	532:fe11edbda85c	517	PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) >> POSITION_VAL(RCC_DCKCFGR_PLLI2SDIVQ));
mbed_official	532:fe11edbda85c	518	PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVQ) >> POSITION_VAL(RCC_DCKCFGR_PLLSAIDIVQ));
mbed_official	532:fe11edbda85c	519
mbed_official	532:fe11edbda85c	520	/* Get the SAI1 clock configuration ----------------------------------------------*/
mbed_official	532:fe11edbda85c	521	PeriphClkInit->Sai1ClockSelection = __HAL_RCC_GET_SAI1_SOURCE();
mbed_official	532:fe11edbda85c	522
mbed_official	532:fe11edbda85c	523	/* Get the SAI2 clock configuration ----------------------------------------------*/
mbed_official	532:fe11edbda85c	524	PeriphClkInit->Sai2ClockSelection = __HAL_RCC_GET_SAI2_SOURCE();
mbed_official	532:fe11edbda85c	525
mbed_official	532:fe11edbda85c	526	/* Get the I2S APB1 clock configuration ------------------------------------------*/
mbed_official	532:fe11edbda85c	527	PeriphClkInit->I2sApb1ClockSelection = __HAL_RCC_GET_I2S_APB1_SOURCE();
mbed_official	532:fe11edbda85c	528
mbed_official	532:fe11edbda85c	529	/* Get the I2S APB2 clock configuration ------------------------------------------*/
mbed_official	532:fe11edbda85c	530	PeriphClkInit->I2sApb2ClockSelection = __HAL_RCC_GET_I2S_APB2_SOURCE();
mbed_official	532:fe11edbda85c	531
mbed_official	532:fe11edbda85c	532	/* Get the RTC Clock configuration -----------------------------------------------*/
mbed_official	532:fe11edbda85c	533	tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);
mbed_official	532:fe11edbda85c	534	PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) \| (RCC->BDCR & RCC_BDCR_RTCSEL));
mbed_official	532:fe11edbda85c	535
mbed_official	532:fe11edbda85c	536	/* Get the CEC clock configuration -----------------------------------------------*/
mbed_official	532:fe11edbda85c	537	PeriphClkInit->CecClockSelection = __HAL_RCC_GET_CEC_SOURCE();
mbed_official	532:fe11edbda85c	538
mbed_official	532:fe11edbda85c	539	/* Get the FMPI2C1 clock configuration -----------------------------------------------*/
mbed_official	532:fe11edbda85c	540	PeriphClkInit->Fmpi2c1ClockSelection = __HAL_RCC_GET_FMPI2C1_SOURCE();
mbed_official	532:fe11edbda85c	541
mbed_official	532:fe11edbda85c	542	/* Get the CK48 clock configuration -----------------------------------------------*/
mbed_official	532:fe11edbda85c	543	PeriphClkInit->Clk48ClockSelection = __HAL_RCC_GET_CLK48_SOURCE();
mbed_official	532:fe11edbda85c	544
mbed_official	532:fe11edbda85c	545	/* Get the SDIO clock configuration -----------------------------------------------*/
mbed_official	532:fe11edbda85c	546	PeriphClkInit->SdioClockSelection = __HAL_RCC_GET_SDIO_SOURCE();
mbed_official	532:fe11edbda85c	547
mbed_official	532:fe11edbda85c	548	/* Get the SPDIFRX clock configuration ----------------------------------------------*/
mbed_official	532:fe11edbda85c	549	PeriphClkInit->SpdifClockSelection = __HAL_RCC_GET_SPDIFRX_SOURCE();
mbed_official	532:fe11edbda85c	550
mbed_official	532:fe11edbda85c	551	/* Get the TIM Prescaler configuration --------------------------------------------*/
mbed_official	532:fe11edbda85c	552	if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET)
mbed_official	532:fe11edbda85c	553	{
mbed_official	532:fe11edbda85c	554	PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED;
mbed_official	532:fe11edbda85c	555	}
mbed_official	532:fe11edbda85c	556	else
mbed_official	532:fe11edbda85c	557	{
mbed_official	532:fe11edbda85c	558	PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;
mbed_official	532:fe11edbda85c	559	}
mbed_official	532:fe11edbda85c	560	}
mbed_official	532:fe11edbda85c	561
mbed_official	532:fe11edbda85c	562	/**
mbed_official	532:fe11edbda85c	563	* @brief Return the peripheral clock frequency for a given peripheral(SAI..)
mbed_official	532:fe11edbda85c	564	* @note Return 0 if peripheral clock identifier not managed by this API
mbed_official	532:fe11edbda85c	565	* @param PeriphClk: Peripheral clock identifier
mbed_official	532:fe11edbda85c	566	* This parameter can be one of the following values:
mbed_official	532:fe11edbda85c	567	* @arg RCC_PERIPHCLK_SAI1: SAI1 peripheral clock
mbed_official	532:fe11edbda85c	568	* @arg RCC_PERIPHCLK_SAI2: SAI2 peripheral clock
mbed_official	532:fe11edbda85c	569	* @retval Frequency in KHz
mbed_official	532:fe11edbda85c	570	*/
mbed_official	532:fe11edbda85c	571	uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
mbed_official	532:fe11edbda85c	572	{
mbed_official	532:fe11edbda85c	573	uint32_t tmpreg1 = 0;
mbed_official	532:fe11edbda85c	574	/* This variable used to store the SAI clock frequency (value in Hz) */
mbed_official	532:fe11edbda85c	575	uint32_t frequency = 0;
mbed_official	532:fe11edbda85c	576	/* This variable used to store the VCO Input (value in Hz) */
mbed_official	532:fe11edbda85c	577	uint32_t vcoinput = 0;
mbed_official	532:fe11edbda85c	578	/* This variable used to store the SAI clock source */
mbed_official	532:fe11edbda85c	579	uint32_t saiclocksource = 0;
mbed_official	532:fe11edbda85c	580	if ((PeriphClk == RCC_PERIPHCLK_SAI1) \|\| (PeriphClk == RCC_PERIPHCLK_SAI2))
mbed_official	532:fe11edbda85c	581	{
mbed_official	532:fe11edbda85c	582	saiclocksource = RCC->DCKCFGR;
mbed_official	532:fe11edbda85c	583	saiclocksource &= (RCC_DCKCFGR_SAI1SRC \| RCC_DCKCFGR_SAI2SRC);
mbed_official	532:fe11edbda85c	584	switch (saiclocksource)
mbed_official	532:fe11edbda85c	585	{
mbed_official	532:fe11edbda85c	586	case 0: /* PLLSAI is the clock source for SAI*/
mbed_official	532:fe11edbda85c	587	{
mbed_official	532:fe11edbda85c	588	/* Configure the PLLSAI division factor */
mbed_official	532:fe11edbda85c	589	/* PLLSAI_VCO Input = PLL_SOURCE/PLLSAIM */
mbed_official	532:fe11edbda85c	590	if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
mbed_official	532:fe11edbda85c	591	{
mbed_official	532:fe11edbda85c	592	/* In Case the PLL Source is HSI (Internal Clock) */
mbed_official	532:fe11edbda85c	593	vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIM));
mbed_official	532:fe11edbda85c	594	}
mbed_official	532:fe11edbda85c	595	else
mbed_official	532:fe11edbda85c	596	{
mbed_official	532:fe11edbda85c	597	/* In Case the PLL Source is HSE (External Clock) */
mbed_official	532:fe11edbda85c	598	vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIM)));
mbed_official	532:fe11edbda85c	599	}
mbed_official	532:fe11edbda85c	600	/* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
mbed_official	532:fe11edbda85c	601	/* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
mbed_official	532:fe11edbda85c	602	tmpreg1 = (RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> 24;
mbed_official	532:fe11edbda85c	603	frequency = (vcoinput * ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> 6))/(tmpreg1);
mbed_official	532:fe11edbda85c	604
mbed_official	532:fe11edbda85c	605	/* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
mbed_official	532:fe11edbda85c	606	tmpreg1 = (((RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVQ) >> 8) + 1);
mbed_official	532:fe11edbda85c	607	frequency = frequency/(tmpreg1);
mbed_official	532:fe11edbda85c	608	break;
mbed_official	532:fe11edbda85c	609	}
mbed_official	532:fe11edbda85c	610	case RCC_DCKCFGR_SAI1SRC_0: /* PLLI2S is the clock source for SAI*/
mbed_official	532:fe11edbda85c	611	case RCC_DCKCFGR_SAI2SRC_0: /* PLLI2S is the clock source for SAI*/
mbed_official	532:fe11edbda85c	612	{
mbed_official	532:fe11edbda85c	613	/* Configure the PLLI2S division factor */
mbed_official	532:fe11edbda85c	614	/* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */
mbed_official	532:fe11edbda85c	615	if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
mbed_official	532:fe11edbda85c	616	{
mbed_official	532:fe11edbda85c	617	/* In Case the PLL Source is HSI (Internal Clock) */
mbed_official	532:fe11edbda85c	618	vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
mbed_official	532:fe11edbda85c	619	}
mbed_official	532:fe11edbda85c	620	else
mbed_official	532:fe11edbda85c	621	{
mbed_official	532:fe11edbda85c	622	/* In Case the PLL Source is HSE (External Clock) */
mbed_official	532:fe11edbda85c	623	vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM)));
mbed_official	532:fe11edbda85c	624	}
mbed_official	532:fe11edbda85c	625
mbed_official	532:fe11edbda85c	626	/* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
mbed_official	532:fe11edbda85c	627	/* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
mbed_official	532:fe11edbda85c	628	tmpreg1 = (RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> 24;
mbed_official	532:fe11edbda85c	629	frequency = (vcoinput * ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6))/(tmpreg1);
mbed_official	532:fe11edbda85c	630
mbed_official	532:fe11edbda85c	631	/* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
mbed_official	532:fe11edbda85c	632	tmpreg1 = ((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) + 1);
mbed_official	532:fe11edbda85c	633	frequency = frequency/(tmpreg1);
mbed_official	532:fe11edbda85c	634	break;
mbed_official	532:fe11edbda85c	635	}
mbed_official	532:fe11edbda85c	636	case RCC_DCKCFGR_SAI1SRC_1: /* PLLR is the clock source for SAI*/
mbed_official	532:fe11edbda85c	637	case RCC_DCKCFGR_SAI2SRC_1: /* PLLR is the clock source for SAI*/
mbed_official	532:fe11edbda85c	638	{
mbed_official	532:fe11edbda85c	639	/* Configure the PLLI2S division factor */
mbed_official	532:fe11edbda85c	640	/* PLL_VCO Input = PLL_SOURCE/PLLM */
mbed_official	532:fe11edbda85c	641	if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
mbed_official	532:fe11edbda85c	642	{
mbed_official	532:fe11edbda85c	643	/* In Case the PLL Source is HSI (Internal Clock) */
mbed_official	532:fe11edbda85c	644	vcoinput = (HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
mbed_official	532:fe11edbda85c	645	}
mbed_official	532:fe11edbda85c	646	else
mbed_official	532:fe11edbda85c	647	{
mbed_official	532:fe11edbda85c	648	/* In Case the PLL Source is HSE (External Clock) */
mbed_official	532:fe11edbda85c	649	vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)));
mbed_official	532:fe11edbda85c	650	}
mbed_official	532:fe11edbda85c	651
mbed_official	532:fe11edbda85c	652	/* PLL_VCO Output = PLL_VCO Input * PLLN */
mbed_official	532:fe11edbda85c	653	/* SAI_CLK_x = PLL_VCO Output/PLLR */
mbed_official	532:fe11edbda85c	654	tmpreg1 = (RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 28;
mbed_official	532:fe11edbda85c	655	frequency = (vcoinput * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6))/(tmpreg1);
mbed_official	532:fe11edbda85c	656	break;
mbed_official	532:fe11edbda85c	657	}
mbed_official	532:fe11edbda85c	658	case RCC_DCKCFGR_SAI1SRC: /* External clock is the clock source for SAI*/
mbed_official	532:fe11edbda85c	659	{
mbed_official	532:fe11edbda85c	660	frequency = EXTERNAL_CLOCK_VALUE;
mbed_official	532:fe11edbda85c	661	break;
mbed_official	532:fe11edbda85c	662	}
mbed_official	532:fe11edbda85c	663	case RCC_DCKCFGR_SAI2SRC: /* PLLSRC(HSE or HSI) is the clock source for SAI*/
mbed_official	532:fe11edbda85c	664	{
mbed_official	532:fe11edbda85c	665	if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
mbed_official	532:fe11edbda85c	666	{
mbed_official	532:fe11edbda85c	667	/* In Case the PLL Source is HSI (Internal Clock) */
mbed_official	532:fe11edbda85c	668	frequency = (uint32_t)(HSI_VALUE);
mbed_official	532:fe11edbda85c	669	}
mbed_official	532:fe11edbda85c	670	else
mbed_official	532:fe11edbda85c	671	{
mbed_official	532:fe11edbda85c	672	/* In Case the PLL Source is HSE (External Clock) */
mbed_official	532:fe11edbda85c	673	frequency = (uint32_t)(HSE_VALUE);
mbed_official	532:fe11edbda85c	674	}
mbed_official	532:fe11edbda85c	675	break;
mbed_official	532:fe11edbda85c	676	}
mbed_official	532:fe11edbda85c	677	default :
mbed_official	532:fe11edbda85c	678	{
mbed_official	532:fe11edbda85c	679	break;
mbed_official	532:fe11edbda85c	680	}
mbed_official	532:fe11edbda85c	681	}
mbed_official	532:fe11edbda85c	682	}
mbed_official	532:fe11edbda85c	683	return frequency;
mbed_official	532:fe11edbda85c	684	}
mbed_official	532:fe11edbda85c	685
mbed_official	532:fe11edbda85c	686	#endif /* STM32F446xx */
mbed_official	532:fe11edbda85c	687
mbed_official	532:fe11edbda85c	688	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
mbed_official	532:fe11edbda85c	689	/**
mbed_official	532:fe11edbda85c	690	* @brief Initializes the RCC extended peripherals clocks according to the specified
mbed_official	532:fe11edbda85c	691	* parameters in the RCC_PeriphCLKInitTypeDef.
mbed_official	532:fe11edbda85c	692	* @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
mbed_official	532:fe11edbda85c	693	* contains the configuration information for the Extended Peripherals
mbed_official	532:fe11edbda85c	694	* clocks(I2S, SAI, LTDC RTC and TIM).
mbed_official	532:fe11edbda85c	695	*
mbed_official	532:fe11edbda85c	696	* @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
mbed_official	532:fe11edbda85c	697	* the RTC clock source; in this case the Backup domain will be reset in
mbed_official	532:fe11edbda85c	698	* order to modify the RTC Clock source, as consequence RTC registers (including
mbed_official	532:fe11edbda85c	699	* the backup registers) and RCC_BDCR register are set to their reset values.
mbed_official	532:fe11edbda85c	700	*
mbed_official	532:fe11edbda85c	701	* @retval HAL status
mbed_official	532:fe11edbda85c	702	*/
mbed_official	532:fe11edbda85c	703	HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
mbed_official	532:fe11edbda85c	704	{
mbed_official	532:fe11edbda85c	705	uint32_t tickstart = 0;
mbed_official	532:fe11edbda85c	706	uint32_t tmpreg1 = 0;
mbed_official	235:685d5f11838f	707
mbed_official	235:685d5f11838f	708	/* Check the parameters */
mbed_official	235:685d5f11838f	709	assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
mbed_official	235:685d5f11838f	710
mbed_official	235:685d5f11838f	711	/----------------------- SAI/I2S Configuration (PLLI2S) -------------------------/
mbed_official	235:685d5f11838f	712
mbed_official	235:685d5f11838f	713	/----------------------- Common configuration SAI/I2S ---------------------------/
mbed_official	235:685d5f11838f	714	/* In Case of SAI or I2S Clock Configuration through PLLI2S, PLLI2SN division
mbed_official	235:685d5f11838f	715	factor is common parameters for both peripherals */
mbed_official	235:685d5f11838f	716	if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) \|\|
mbed_official	235:685d5f11838f	717	(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == RCC_PERIPHCLK_SAI_PLLI2S))
mbed_official	235:685d5f11838f	718	{
mbed_official	235:685d5f11838f	719	/* check for Parameters */
mbed_official	235:685d5f11838f	720	assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
mbed_official	235:685d5f11838f	721
mbed_official	235:685d5f11838f	722	/* Disable the PLLI2S */
mbed_official	235:685d5f11838f	723	__HAL_RCC_PLLI2S_DISABLE();
mbed_official	235:685d5f11838f	724	/* Get tick */
mbed_official	235:685d5f11838f	725	tickstart = HAL_GetTick();
mbed_official	235:685d5f11838f	726	/* Wait till PLLI2S is disabled */
mbed_official	235:685d5f11838f	727	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
mbed_official	235:685d5f11838f	728	{
mbed_official	235:685d5f11838f	729	if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
mbed_official	235:685d5f11838f	730	{
mbed_official	235:685d5f11838f	731	/* return in case of Timeout detected */
mbed_official	235:685d5f11838f	732	return HAL_TIMEOUT;
mbed_official	235:685d5f11838f	733	}
mbed_official	235:685d5f11838f	734	}
mbed_official	235:685d5f11838f	735
mbed_official	235:685d5f11838f	736	/---------------------------- I2S configuration -------------------------------/
mbed_official	235:685d5f11838f	737	/* In Case of I2S Clock Configuration through PLLI2S, PLLI2SR must be added
mbed_official	235:685d5f11838f	738	only for I2S configuration */
mbed_official	235:685d5f11838f	739	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S))
mbed_official	235:685d5f11838f	740	{
mbed_official	235:685d5f11838f	741	/* check for Parameters */
mbed_official	235:685d5f11838f	742	assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
mbed_official	235:685d5f11838f	743	/* Configure the PLLI2S division factors */
mbed_official	235:685d5f11838f	744	/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) × (PLLI2SN/PLLM) */
mbed_official	235:685d5f11838f	745	/* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
mbed_official	235:685d5f11838f	746	__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SR);
mbed_official	235:685d5f11838f	747	}
mbed_official	235:685d5f11838f	748
mbed_official	235:685d5f11838f	749	/---------------------------- SAI configuration -------------------------------/
mbed_official	235:685d5f11838f	750	/* In Case of SAI Clock Configuration through PLLI2S, PLLI2SQ and PLLI2S_DIVQ must
mbed_official	235:685d5f11838f	751	be added only for SAI configuration */
mbed_official	235:685d5f11838f	752	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == (RCC_PERIPHCLK_SAI_PLLI2S))
mbed_official	235:685d5f11838f	753	{
mbed_official	235:685d5f11838f	754	/* Check the PLLI2S division factors */
mbed_official	235:685d5f11838f	755	assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
mbed_official	235:685d5f11838f	756	assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ));
mbed_official	235:685d5f11838f	757
mbed_official	235:685d5f11838f	758	/* Read PLLI2SR value from PLLI2SCFGR register (this value is not need for SAI configuration) */
mbed_official	532:fe11edbda85c	759	tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
mbed_official	235:685d5f11838f	760	/* Configure the PLLI2S division factors */
mbed_official	235:685d5f11838f	761	/* PLLI2S_VCO Input = PLL_SOURCE/PLLM */
mbed_official	235:685d5f11838f	762	/* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
mbed_official	235:685d5f11838f	763	/* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
mbed_official	532:fe11edbda85c	764	__HAL_RCC_PLLI2S_SAICLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SQ , tmpreg1);
mbed_official	235:685d5f11838f	765	/* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
mbed_official	235:685d5f11838f	766	__HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ);
mbed_official	235:685d5f11838f	767	}
mbed_official	235:685d5f11838f	768
mbed_official	235:685d5f11838f	769	/* Enable the PLLI2S */
mbed_official	235:685d5f11838f	770	__HAL_RCC_PLLI2S_ENABLE();
mbed_official	235:685d5f11838f	771	/* Get tick */
mbed_official	235:685d5f11838f	772	tickstart = HAL_GetTick();
mbed_official	235:685d5f11838f	773	/* Wait till PLLI2S is ready */
mbed_official	235:685d5f11838f	774	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
mbed_official	235:685d5f11838f	775	{
mbed_official	235:685d5f11838f	776	if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
mbed_official	235:685d5f11838f	777	{
mbed_official	235:685d5f11838f	778	/* return in case of Timeout detected */
mbed_official	235:685d5f11838f	779	return HAL_TIMEOUT;
mbed_official	235:685d5f11838f	780	}
mbed_official	235:685d5f11838f	781	}
mbed_official	235:685d5f11838f	782	}
mbed_official	235:685d5f11838f	783
mbed_official	235:685d5f11838f	784	/----------------------- SAI/LTDC Configuration (PLLSAI) ------------------/
mbed_official	235:685d5f11838f	785
mbed_official	235:685d5f11838f	786	/----------------------- Common configuration SAI/LTDC --------------------/
mbed_official	235:685d5f11838f	787	/* In Case of SAI or LTDC Clock Configuration through PLLSAI, PLLSAIN division
mbed_official	235:685d5f11838f	788	factor is common parameters for both peripherals */
mbed_official	235:685d5f11838f	789	if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == RCC_PERIPHCLK_SAI_PLLSAI) \|\|
mbed_official	235:685d5f11838f	790	(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC))
mbed_official	235:685d5f11838f	791	{
mbed_official	235:685d5f11838f	792	/* Check the PLLSAI division factors */
mbed_official	235:685d5f11838f	793	assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN));
mbed_official	235:685d5f11838f	794
mbed_official	235:685d5f11838f	795	/* Disable PLLSAI Clock */
mbed_official	235:685d5f11838f	796	__HAL_RCC_PLLSAI_DISABLE();
mbed_official	235:685d5f11838f	797	/* Get tick */
mbed_official	235:685d5f11838f	798	tickstart = HAL_GetTick();
mbed_official	235:685d5f11838f	799	/* Wait till PLLSAI is disabled */
mbed_official	235:685d5f11838f	800	while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
mbed_official	235:685d5f11838f	801	{
mbed_official	235:685d5f11838f	802	if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
mbed_official	235:685d5f11838f	803	{
mbed_official	235:685d5f11838f	804	/* return in case of Timeout detected */
mbed_official	235:685d5f11838f	805	return HAL_TIMEOUT;
mbed_official	235:685d5f11838f	806	}
mbed_official	235:685d5f11838f	807	}
mbed_official	235:685d5f11838f	808
mbed_official	235:685d5f11838f	809	/---------------------------- SAI configuration -------------------------/
mbed_official	235:685d5f11838f	810	/* In Case of SAI Clock Configuration through PLLSAI, PLLSAIQ and PLLSAI_DIVQ must
mbed_official	235:685d5f11838f	811	be added only for SAI configuration */
mbed_official	235:685d5f11838f	812	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == (RCC_PERIPHCLK_SAI_PLLSAI))
mbed_official	235:685d5f11838f	813	{
mbed_official	235:685d5f11838f	814	assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ));
mbed_official	235:685d5f11838f	815	assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ));
mbed_official	235:685d5f11838f	816
mbed_official	235:685d5f11838f	817	/* Read PLLSAIR value from PLLSAICFGR register (this value is not need for SAI configuration) */
mbed_official	532:fe11edbda85c	818	tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR));
mbed_official	235:685d5f11838f	819	/* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
mbed_official	235:685d5f11838f	820	/* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
mbed_official	235:685d5f11838f	821	/* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
mbed_official	532:fe11edbda85c	822	__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIQ, tmpreg1);
mbed_official	235:685d5f11838f	823	/* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
mbed_official	235:685d5f11838f	824	__HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ);
mbed_official	235:685d5f11838f	825	}
mbed_official	235:685d5f11838f	826
mbed_official	235:685d5f11838f	827	/---------------------------- LTDC configuration ------------------------/
mbed_official	235:685d5f11838f	828	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == (RCC_PERIPHCLK_LTDC))
mbed_official	235:685d5f11838f	829	{
mbed_official	235:685d5f11838f	830	assert_param(IS_RCC_PLLSAIR_VALUE(PeriphClkInit->PLLSAI.PLLSAIR));
mbed_official	235:685d5f11838f	831	assert_param(IS_RCC_PLLSAI_DIVR_VALUE(PeriphClkInit->PLLSAIDivR));
mbed_official	235:685d5f11838f	832
mbed_official	235:685d5f11838f	833	/* Read PLLSAIR value from PLLSAICFGR register (this value is not need for SAI configuration) */
mbed_official	532:fe11edbda85c	834	tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ));
mbed_official	235:685d5f11838f	835	/* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
mbed_official	235:685d5f11838f	836	/* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
mbed_official	235:685d5f11838f	837	/* LTDC_CLK(first level) = PLLSAI_VCO Output/PLLSAIR */
mbed_official	532:fe11edbda85c	838	__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg1, PeriphClkInit->PLLSAI.PLLSAIR);
mbed_official	235:685d5f11838f	839	/* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */
mbed_official	235:685d5f11838f	840	__HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLSAIDivR);
mbed_official	235:685d5f11838f	841	}
mbed_official	235:685d5f11838f	842	/* Enable PLLSAI Clock */
mbed_official	235:685d5f11838f	843	__HAL_RCC_PLLSAI_ENABLE();
mbed_official	235:685d5f11838f	844	/* Get tick */
mbed_official	235:685d5f11838f	845	tickstart = HAL_GetTick();
mbed_official	235:685d5f11838f	846	/* Wait till PLLSAI is ready */
mbed_official	235:685d5f11838f	847	while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
mbed_official	235:685d5f11838f	848	{
mbed_official	235:685d5f11838f	849	if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
mbed_official	235:685d5f11838f	850	{
mbed_official	235:685d5f11838f	851	/* return in case of Timeout detected */
mbed_official	235:685d5f11838f	852	return HAL_TIMEOUT;
mbed_official	235:685d5f11838f	853	}
mbed_official	235:685d5f11838f	854	}
mbed_official	235:685d5f11838f	855	}
mbed_official	235:685d5f11838f	856
mbed_official	235:685d5f11838f	857
mbed_official	235:685d5f11838f	858	/---------------------------- RTC configuration ---------------------------/
mbed_official	235:685d5f11838f	859	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
mbed_official	235:685d5f11838f	860	{
mbed_official	235:685d5f11838f	861	/* Enable Power Clock*/
mbed_official	532:fe11edbda85c	862	__HAL_RCC_PWR_CLK_ENABLE();
mbed_official	235:685d5f11838f	863
mbed_official	235:685d5f11838f	864	/* Enable write access to Backup domain */
mbed_official	235:685d5f11838f	865	PWR->CR \|= PWR_CR_DBP;
mbed_official	235:685d5f11838f	866
mbed_official	235:685d5f11838f	867	/* Get tick */
mbed_official	235:685d5f11838f	868	tickstart = HAL_GetTick();
mbed_official	235:685d5f11838f	869
mbed_official	235:685d5f11838f	870	while((PWR->CR & PWR_CR_DBP) == RESET)
mbed_official	235:685d5f11838f	871	{
mbed_official	532:fe11edbda85c	872	if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
mbed_official	235:685d5f11838f	873	{
mbed_official	235:685d5f11838f	874	return HAL_TIMEOUT;
mbed_official	235:685d5f11838f	875	}
mbed_official	235:685d5f11838f	876	}
mbed_official	235:685d5f11838f	877
mbed_official	532:fe11edbda85c	878	/* Reset the Backup domain only if the RTC Clock source selection is modified */
mbed_official	235:685d5f11838f	879	if((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))
mbed_official	235:685d5f11838f	880	{
mbed_official	235:685d5f11838f	881	/* Store the content of BDCR register before the reset of Backup Domain */
mbed_official	532:fe11edbda85c	882	tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
mbed_official	235:685d5f11838f	883	/* RTC Clock selection can be changed only if the Backup Domain is reset */
mbed_official	235:685d5f11838f	884	__HAL_RCC_BACKUPRESET_FORCE();
mbed_official	235:685d5f11838f	885	__HAL_RCC_BACKUPRESET_RELEASE();
mbed_official	235:685d5f11838f	886	/* Restore the Content of BDCR register */
mbed_official	532:fe11edbda85c	887	RCC->BDCR = tmpreg1;
mbed_official	235:685d5f11838f	888	}
mbed_official	235:685d5f11838f	889
mbed_official	235:685d5f11838f	890	/* If LSE is selected as RTC clock source, wait for LSE reactivation */
mbed_official	235:685d5f11838f	891	if(PeriphClkInit->RTCClockSelection == RCC_RTCCLKSOURCE_LSE)
mbed_official	235:685d5f11838f	892	{
mbed_official	235:685d5f11838f	893	/* Get tick */
mbed_official	235:685d5f11838f	894	tickstart = HAL_GetTick();
mbed_official	235:685d5f11838f	895
mbed_official	235:685d5f11838f	896	/* Wait till LSE is ready */
mbed_official	235:685d5f11838f	897	while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
mbed_official	235:685d5f11838f	898	{
mbed_official	532:fe11edbda85c	899	if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
mbed_official	235:685d5f11838f	900	{
mbed_official	235:685d5f11838f	901	return HAL_TIMEOUT;
mbed_official	235:685d5f11838f	902	}
mbed_official	235:685d5f11838f	903	}
mbed_official	235:685d5f11838f	904	}
mbed_official	235:685d5f11838f	905	__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
mbed_official	235:685d5f11838f	906	}
mbed_official	235:685d5f11838f	907
mbed_official	235:685d5f11838f	908	/---------------------------- TIM configuration ---------------------------/
mbed_official	235:685d5f11838f	909	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
mbed_official	235:685d5f11838f	910	{
mbed_official	235:685d5f11838f	911	__HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
mbed_official	235:685d5f11838f	912	}
mbed_official	235:685d5f11838f	913	return HAL_OK;
mbed_official	235:685d5f11838f	914	}
mbed_official	235:685d5f11838f	915
mbed_official	235:685d5f11838f	916	/**
mbed_official	235:685d5f11838f	917	* @brief Configures the RCC_OscInitStruct according to the internal
mbed_official	235:685d5f11838f	918	* RCC configuration registers.
mbed_official	235:685d5f11838f	919	* @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
mbed_official	235:685d5f11838f	920	* will be configured.
mbed_official	235:685d5f11838f	921	* @retval None
mbed_official	235:685d5f11838f	922	*/
mbed_official	235:685d5f11838f	923	void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
mbed_official	235:685d5f11838f	924	{
mbed_official	235:685d5f11838f	925	uint32_t tempreg;
mbed_official	235:685d5f11838f	926
mbed_official	235:685d5f11838f	927	/* Set all possible values for the extended clock type parameter------------*/
mbed_official	235:685d5f11838f	928	PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S \| RCC_PERIPHCLK_SAI_PLLSAI \| RCC_PERIPHCLK_SAI_PLLI2S \| RCC_PERIPHCLK_LTDC \| RCC_PERIPHCLK_TIM \| RCC_PERIPHCLK_RTC;
mbed_official	235:685d5f11838f	929
mbed_official	235:685d5f11838f	930	/* Get the PLLI2S Clock configuration -----------------------------------------------*/
mbed_official	235:685d5f11838f	931	PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN));
mbed_official	235:685d5f11838f	932	PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
mbed_official	235:685d5f11838f	933	PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ));
mbed_official	235:685d5f11838f	934	/* Get the PLLSAI Clock configuration -----------------------------------------------*/
mbed_official	235:685d5f11838f	935	PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN));
mbed_official	235:685d5f11838f	936	PeriphClkInit->PLLSAI.PLLSAIR = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR));
mbed_official	235:685d5f11838f	937	PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ));
mbed_official	235:685d5f11838f	938	/* Get the PLLSAI/PLLI2S division factors -----------------------------------------------*/
mbed_official	235:685d5f11838f	939	PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) >> POSITION_VAL(RCC_DCKCFGR_PLLI2SDIVQ));
mbed_official	235:685d5f11838f	940	PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVQ) >> POSITION_VAL(RCC_DCKCFGR_PLLSAIDIVQ));
mbed_official	235:685d5f11838f	941	PeriphClkInit->PLLSAIDivR = (uint32_t)(RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVR);
mbed_official	235:685d5f11838f	942	/* Get the RTC Clock configuration -----------------------------------------------*/
mbed_official	235:685d5f11838f	943	tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);
mbed_official	235:685d5f11838f	944	PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) \| (RCC->BDCR & RCC_BDCR_RTCSEL));
mbed_official	235:685d5f11838f	945
mbed_official	235:685d5f11838f	946	if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET)
mbed_official	235:685d5f11838f	947	{
mbed_official	235:685d5f11838f	948	PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED;
mbed_official	235:685d5f11838f	949	}
mbed_official	235:685d5f11838f	950	else
mbed_official	235:685d5f11838f	951	{
mbed_official	235:685d5f11838f	952	PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;
mbed_official	235:685d5f11838f	953	}
mbed_official	235:685d5f11838f	954	}
mbed_official	532:fe11edbda85c	955
mbed_official	235:685d5f11838f	956	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
mbed_official	235:685d5f11838f	957
mbed_official	235:685d5f11838f	958	#if defined(STM32F405xx) \|\| defined(STM32F415xx) \|\| defined(STM32F407xx)\|\| defined(STM32F417xx) \|\|\
mbed_official	235:685d5f11838f	959	defined(STM32F401xC) \|\| defined(STM32F401xE) \|\| defined(STM32F411xE)
mbed_official	235:685d5f11838f	960	/**
mbed_official	235:685d5f11838f	961	* @brief Initializes the RCC extended peripherals clocks according to the specified parameters in the
mbed_official	235:685d5f11838f	962	* RCC_PeriphCLKInitTypeDef.
mbed_official	235:685d5f11838f	963	* @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
mbed_official	235:685d5f11838f	964	* contains the configuration information for the Extended Peripherals clocks(I2S and RTC clocks).
mbed_official	235:685d5f11838f	965	*
mbed_official	235:685d5f11838f	966	* @note A caution to be taken when HAL_RCCEx_PeriphCLKConfig() is used to select RTC clock selection, in this case
mbed_official	235:685d5f11838f	967	* the Reset of Backup domain will be applied in order to modify the RTC Clock source as consequence all backup
mbed_official	235:685d5f11838f	968	* domain (RTC and RCC_BDCR register expect BKPSRAM) will be reset
mbed_official	235:685d5f11838f	969	*
mbed_official	235:685d5f11838f	970	* @retval HAL status
mbed_official	235:685d5f11838f	971	*/
mbed_official	235:685d5f11838f	972	HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
mbed_official	235:685d5f11838f	973	{
mbed_official	235:685d5f11838f	974	uint32_t tickstart = 0;
mbed_official	532:fe11edbda85c	975	uint32_t tmpreg1 = 0;
mbed_official	235:685d5f11838f	976
mbed_official	235:685d5f11838f	977	/* Check the parameters */
mbed_official	235:685d5f11838f	978	assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
mbed_official	235:685d5f11838f	979
mbed_official	235:685d5f11838f	980	/---------------------------- I2S configuration ---------------------------/
mbed_official	235:685d5f11838f	981	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S))
mbed_official	235:685d5f11838f	982	{
mbed_official	235:685d5f11838f	983	/* check for Parameters */
mbed_official	235:685d5f11838f	984	assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
mbed_official	235:685d5f11838f	985	assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
mbed_official	235:685d5f11838f	986	#if defined(STM32F411xE)
mbed_official	235:685d5f11838f	987	assert_param(IS_RCC_PLLI2SM_VALUE(PeriphClkInit->PLLI2S.PLLI2SM));
mbed_official	235:685d5f11838f	988	#endif /* STM32F411xE */
mbed_official	235:685d5f11838f	989	/* Disable the PLLI2S */
mbed_official	235:685d5f11838f	990	__HAL_RCC_PLLI2S_DISABLE();
mbed_official	235:685d5f11838f	991	/* Get tick */
mbed_official	235:685d5f11838f	992	tickstart = HAL_GetTick();
mbed_official	235:685d5f11838f	993	/* Wait till PLLI2S is disabled */
mbed_official	235:685d5f11838f	994	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
mbed_official	235:685d5f11838f	995	{
mbed_official	235:685d5f11838f	996	if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
mbed_official	235:685d5f11838f	997	{
mbed_official	235:685d5f11838f	998	/* return in case of Timeout detected */
mbed_official	235:685d5f11838f	999	return HAL_TIMEOUT;
mbed_official	235:685d5f11838f	1000	}
mbed_official	235:685d5f11838f	1001	}
mbed_official	235:685d5f11838f	1002
mbed_official	235:685d5f11838f	1003	#if defined(STM32F411xE)
mbed_official	235:685d5f11838f	1004	/* Configure the PLLI2S division factors */
mbed_official	235:685d5f11838f	1005	/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) × (PLLI2SN/PLLI2SM) */
mbed_official	235:685d5f11838f	1006	/* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
mbed_official	235:685d5f11838f	1007	__HAL_RCC_PLLI2S_I2SCLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SR);
mbed_official	235:685d5f11838f	1008	#else
mbed_official	235:685d5f11838f	1009	/* Configure the PLLI2S division factors */
mbed_official	235:685d5f11838f	1010	/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) × (PLLI2SN/PLLM) */
mbed_official	235:685d5f11838f	1011	/* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
mbed_official	235:685d5f11838f	1012	__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SR);
mbed_official	235:685d5f11838f	1013	#endif /* STM32F411xE */
mbed_official	235:685d5f11838f	1014
mbed_official	235:685d5f11838f	1015	/* Enable the PLLI2S */
mbed_official	235:685d5f11838f	1016	__HAL_RCC_PLLI2S_ENABLE();
mbed_official	235:685d5f11838f	1017	/* Get tick */
mbed_official	235:685d5f11838f	1018	tickstart = HAL_GetTick();
mbed_official	235:685d5f11838f	1019	/* Wait till PLLI2S is ready */
mbed_official	235:685d5f11838f	1020	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
mbed_official	235:685d5f11838f	1021	{
mbed_official	235:685d5f11838f	1022	if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
mbed_official	235:685d5f11838f	1023	{
mbed_official	235:685d5f11838f	1024	/* return in case of Timeout detected */
mbed_official	235:685d5f11838f	1025	return HAL_TIMEOUT;
mbed_official	235:685d5f11838f	1026	}
mbed_official	235:685d5f11838f	1027	}
mbed_official	235:685d5f11838f	1028	}
mbed_official	235:685d5f11838f	1029
mbed_official	235:685d5f11838f	1030	/---------------------------- RTC configuration ---------------------------/
mbed_official	235:685d5f11838f	1031	if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
mbed_official	235:685d5f11838f	1032	{
mbed_official	235:685d5f11838f	1033	/* Enable Power Clock*/
mbed_official	532:fe11edbda85c	1034	__HAL_RCC_PWR_CLK_ENABLE();
mbed_official	235:685d5f11838f	1035
mbed_official	235:685d5f11838f	1036	/* Enable write access to Backup domain */
mbed_official	235:685d5f11838f	1037	PWR->CR \|= PWR_CR_DBP;
mbed_official	235:685d5f11838f	1038
mbed_official	235:685d5f11838f	1039	/* Get tick */
mbed_official	235:685d5f11838f	1040	tickstart = HAL_GetTick();
mbed_official	235:685d5f11838f	1041
mbed_official	235:685d5f11838f	1042	while((PWR->CR & PWR_CR_DBP) == RESET)
mbed_official	235:685d5f11838f	1043	{
mbed_official	532:fe11edbda85c	1044	if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
mbed_official	235:685d5f11838f	1045	{
mbed_official	235:685d5f11838f	1046	return HAL_TIMEOUT;
mbed_official	235:685d5f11838f	1047	}
mbed_official	235:685d5f11838f	1048	}
mbed_official	235:685d5f11838f	1049
mbed_official	532:fe11edbda85c	1050	/* Reset the Backup domain only if the RTC Clock source selection is modified */
mbed_official	235:685d5f11838f	1051	if((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))
mbed_official	235:685d5f11838f	1052	{
mbed_official	235:685d5f11838f	1053	/* Store the content of BDCR register before the reset of Backup Domain */
mbed_official	532:fe11edbda85c	1054	tmpreg1 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
mbed_official	235:685d5f11838f	1055	/* RTC Clock selection can be changed only if the Backup Domain is reset */
mbed_official	235:685d5f11838f	1056	__HAL_RCC_BACKUPRESET_FORCE();
mbed_official	235:685d5f11838f	1057	__HAL_RCC_BACKUPRESET_RELEASE();
mbed_official	235:685d5f11838f	1058	/* Restore the Content of BDCR register */
mbed_official	532:fe11edbda85c	1059	RCC->BDCR = tmpreg1;
mbed_official	235:685d5f11838f	1060	}
mbed_official	235:685d5f11838f	1061
mbed_official	235:685d5f11838f	1062	/* If LSE is selected as RTC clock source, wait for LSE reactivation */
mbed_official	235:685d5f11838f	1063	if(PeriphClkInit->RTCClockSelection == RCC_RTCCLKSOURCE_LSE)
mbed_official	235:685d5f11838f	1064	{
mbed_official	235:685d5f11838f	1065	/* Get tick */
mbed_official	235:685d5f11838f	1066	tickstart = HAL_GetTick();
mbed_official	235:685d5f11838f	1067
mbed_official	235:685d5f11838f	1068	/* Wait till LSE is ready */
mbed_official	235:685d5f11838f	1069	while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
mbed_official	235:685d5f11838f	1070	{
mbed_official	532:fe11edbda85c	1071	if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
mbed_official	235:685d5f11838f	1072	{
mbed_official	235:685d5f11838f	1073	return HAL_TIMEOUT;
mbed_official	235:685d5f11838f	1074	}
mbed_official	235:685d5f11838f	1075	}
mbed_official	235:685d5f11838f	1076	}
mbed_official	235:685d5f11838f	1077	__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
mbed_official	235:685d5f11838f	1078	}
mbed_official	235:685d5f11838f	1079
mbed_official	235:685d5f11838f	1080	return HAL_OK;
mbed_official	235:685d5f11838f	1081	}
mbed_official	235:685d5f11838f	1082
mbed_official	235:685d5f11838f	1083	/**
mbed_official	235:685d5f11838f	1084	* @brief Configures the RCC_OscInitStruct according to the internal
mbed_official	235:685d5f11838f	1085	* RCC configuration registers.
mbed_official	235:685d5f11838f	1086	* @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
mbed_official	235:685d5f11838f	1087	* will be configured.
mbed_official	235:685d5f11838f	1088	* @retval None
mbed_official	235:685d5f11838f	1089	*/
mbed_official	235:685d5f11838f	1090	void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
mbed_official	235:685d5f11838f	1091	{
mbed_official	235:685d5f11838f	1092	uint32_t tempreg;
mbed_official	235:685d5f11838f	1093
mbed_official	235:685d5f11838f	1094	/* Set all possible values for the extended clock type parameter------------*/
mbed_official	235:685d5f11838f	1095	PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S \| RCC_PERIPHCLK_RTC;
mbed_official	235:685d5f11838f	1096
mbed_official	235:685d5f11838f	1097	/* Get the PLLI2S Clock configuration -----------------------------------------------*/
mbed_official	235:685d5f11838f	1098	PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN));
mbed_official	235:685d5f11838f	1099	PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
mbed_official	235:685d5f11838f	1100	#if defined(STM32F411xE)
mbed_official	235:685d5f11838f	1101	PeriphClkInit->PLLI2S.PLLI2SM = (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM);
mbed_official	235:685d5f11838f	1102	#endif /* STM32F411xE */
mbed_official	235:685d5f11838f	1103	/* Get the RTC Clock configuration -----------------------------------------------*/
mbed_official	235:685d5f11838f	1104	tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);
mbed_official	235:685d5f11838f	1105	PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) \| (RCC->BDCR & RCC_BDCR_RTCSEL));
mbed_official	235:685d5f11838f	1106
mbed_official	235:685d5f11838f	1107	}
mbed_official	235:685d5f11838f	1108	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F401xC \|\| STM32F401xE \|\| STM32F411xE */
mbed_official	235:685d5f11838f	1109
mbed_official	532:fe11edbda85c	1110	#if defined(STM32F411xE) \|\| defined(STM32F446xx)
mbed_official	235:685d5f11838f	1111	/**
mbed_official	235:685d5f11838f	1112	* @brief Select LSE mode
mbed_official	235:685d5f11838f	1113	*
mbed_official	235:685d5f11838f	1114	* @note This mode is only available for STM32F411xx devices.
mbed_official	235:685d5f11838f	1115	*
mbed_official	235:685d5f11838f	1116	* @param Mode: specifies the LSE mode.
mbed_official	235:685d5f11838f	1117	* This parameter can be one of the following values:
mbed_official	235:685d5f11838f	1118	* @arg RCC_LSE_LOWPOWER_MODE: LSE oscillator in low power mode selection
mbed_official	235:685d5f11838f	1119	* @arg RCC_LSE_HIGHDRIVE_MODE: LSE oscillator in High Drive mode selection
mbed_official	235:685d5f11838f	1120	* @retval None
mbed_official	235:685d5f11838f	1121	*/
mbed_official	235:685d5f11838f	1122	void HAL_RCCEx_SelectLSEMode(uint8_t Mode)
mbed_official	235:685d5f11838f	1123	{
mbed_official	235:685d5f11838f	1124	/* Check the parameters */
mbed_official	235:685d5f11838f	1125	assert_param(IS_RCC_LSE_MODE(Mode));
mbed_official	235:685d5f11838f	1126	if(Mode == RCC_LSE_HIGHDRIVE_MODE)
mbed_official	235:685d5f11838f	1127	{
mbed_official	235:685d5f11838f	1128	SET_BIT(RCC->BDCR, RCC_BDCR_LSEMOD);
mbed_official	235:685d5f11838f	1129	}
mbed_official	235:685d5f11838f	1130	else
mbed_official	235:685d5f11838f	1131	{
mbed_official	235:685d5f11838f	1132	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEMOD);
mbed_official	235:685d5f11838f	1133	}
mbed_official	235:685d5f11838f	1134	}
mbed_official	235:685d5f11838f	1135
mbed_official	532:fe11edbda85c	1136	#endif /* STM32F411xE \|\| STM32F446xx */
mbed_official	532:fe11edbda85c	1137
mbed_official	532:fe11edbda85c	1138	#if defined(STM32F446xx)
mbed_official	532:fe11edbda85c	1139	/**
mbed_official	532:fe11edbda85c	1140	* @brief Initializes the RCC Oscillators according to the specified parameters in the
mbed_official	532:fe11edbda85c	1141	* RCC_OscInitTypeDef.
mbed_official	532:fe11edbda85c	1142	* @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
mbed_official	532:fe11edbda85c	1143	* contains the configuration information for the RCC Oscillators.
mbed_official	532:fe11edbda85c	1144	* @note The PLL is not disabled when used as system clock.
mbed_official	532:fe11edbda85c	1145	* @note This function add the PLL/PLLR factor management during PLL configuration this feature is only available in STM32F446xx devices
mbed_official	532:fe11edbda85c	1146	* @retval HAL status
mbed_official	532:fe11edbda85c	1147	*/
mbed_official	532:fe11edbda85c	1148	HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
mbed_official	532:fe11edbda85c	1149	{
mbed_official	532:fe11edbda85c	1150	uint32_t tickstart = 0;
mbed_official	532:fe11edbda85c	1151
mbed_official	532:fe11edbda85c	1152	/* Check the parameters */
mbed_official	532:fe11edbda85c	1153	assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
mbed_official	532:fe11edbda85c	1154	/------------------------------- HSE Configuration ------------------------/
mbed_official	532:fe11edbda85c	1155	if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
mbed_official	532:fe11edbda85c	1156	{
mbed_official	532:fe11edbda85c	1157	/* Check the parameters */
mbed_official	532:fe11edbda85c	1158	assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
mbed_official	532:fe11edbda85c	1159	/* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */
mbed_official	532:fe11edbda85c	1160	if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) \|\|\
mbed_official	532:fe11edbda85c	1161	((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)) \|\|\
mbed_official	532:fe11edbda85c	1162	((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLLR) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
mbed_official	532:fe11edbda85c	1163	{
mbed_official	532:fe11edbda85c	1164	if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
mbed_official	532:fe11edbda85c	1165	{
mbed_official	532:fe11edbda85c	1166	return HAL_ERROR;
mbed_official	532:fe11edbda85c	1167	}
mbed_official	532:fe11edbda85c	1168	}
mbed_official	532:fe11edbda85c	1169	else
mbed_official	532:fe11edbda85c	1170	{
mbed_official	532:fe11edbda85c	1171	/* Reset HSEON and HSEBYP bits before configuring the HSE --------------*/
mbed_official	532:fe11edbda85c	1172	__HAL_RCC_HSE_CONFIG(RCC_HSE_OFF);
mbed_official	532:fe11edbda85c	1173
mbed_official	532:fe11edbda85c	1174	/* Get Start Tick*/
mbed_official	532:fe11edbda85c	1175	tickstart = HAL_GetTick();
mbed_official	532:fe11edbda85c	1176
mbed_official	532:fe11edbda85c	1177	/* Wait till HSE is disabled */
mbed_official	532:fe11edbda85c	1178	while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
mbed_official	532:fe11edbda85c	1179	{
mbed_official	532:fe11edbda85c	1180	if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
mbed_official	532:fe11edbda85c	1181	{
mbed_official	532:fe11edbda85c	1182	return HAL_TIMEOUT;
mbed_official	532:fe11edbda85c	1183	}
mbed_official	532:fe11edbda85c	1184	}
mbed_official	532:fe11edbda85c	1185
mbed_official	532:fe11edbda85c	1186	/* Set the new HSE configuration ---------------------------------------*/
mbed_official	532:fe11edbda85c	1187	__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
mbed_official	532:fe11edbda85c	1188
mbed_official	532:fe11edbda85c	1189	/* Check the HSE State */
mbed_official	532:fe11edbda85c	1190	if((RCC_OscInitStruct->HSEState) != RCC_HSE_OFF)
mbed_official	532:fe11edbda85c	1191	{
mbed_official	532:fe11edbda85c	1192	/* Get Start Tick*/
mbed_official	532:fe11edbda85c	1193	tickstart = HAL_GetTick();
mbed_official	532:fe11edbda85c	1194
mbed_official	532:fe11edbda85c	1195	/* Wait till HSE is ready */
mbed_official	532:fe11edbda85c	1196	while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
mbed_official	532:fe11edbda85c	1197	{
mbed_official	532:fe11edbda85c	1198	if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
mbed_official	532:fe11edbda85c	1199	{
mbed_official	532:fe11edbda85c	1200	return HAL_TIMEOUT;
mbed_official	532:fe11edbda85c	1201	}
mbed_official	532:fe11edbda85c	1202	}
mbed_official	532:fe11edbda85c	1203	}
mbed_official	532:fe11edbda85c	1204	else
mbed_official	532:fe11edbda85c	1205	{
mbed_official	532:fe11edbda85c	1206	/* Get Start Tick*/
mbed_official	532:fe11edbda85c	1207	tickstart = HAL_GetTick();
mbed_official	532:fe11edbda85c	1208
mbed_official	532:fe11edbda85c	1209	/* Wait till HSE is bypassed or disabled */
mbed_official	532:fe11edbda85c	1210	while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
mbed_official	532:fe11edbda85c	1211	{
mbed_official	532:fe11edbda85c	1212	if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
mbed_official	532:fe11edbda85c	1213	{
mbed_official	532:fe11edbda85c	1214	return HAL_TIMEOUT;
mbed_official	532:fe11edbda85c	1215	}
mbed_official	532:fe11edbda85c	1216	}
mbed_official	532:fe11edbda85c	1217	}
mbed_official	532:fe11edbda85c	1218	}
mbed_official	532:fe11edbda85c	1219	}
mbed_official	532:fe11edbda85c	1220	/----------------------------- HSI Configuration --------------------------/
mbed_official	532:fe11edbda85c	1221	if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
mbed_official	532:fe11edbda85c	1222	{
mbed_official	532:fe11edbda85c	1223	/* Check the parameters */
mbed_official	532:fe11edbda85c	1224	assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
mbed_official	532:fe11edbda85c	1225	assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
mbed_official	532:fe11edbda85c	1226
mbed_official	532:fe11edbda85c	1227	/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
mbed_official	532:fe11edbda85c	1228	if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) \|\|\
mbed_official	532:fe11edbda85c	1229	((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)) \|\|\
mbed_official	532:fe11edbda85c	1230	((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLLR) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
mbed_official	532:fe11edbda85c	1231	{
mbed_official	532:fe11edbda85c	1232	/* When HSI is used as system clock it will not disabled */
mbed_official	532:fe11edbda85c	1233	if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
mbed_official	532:fe11edbda85c	1234	{
mbed_official	532:fe11edbda85c	1235	return HAL_ERROR;
mbed_official	532:fe11edbda85c	1236	}
mbed_official	532:fe11edbda85c	1237	/* Otherwise, just the calibration is allowed */
mbed_official	532:fe11edbda85c	1238	else
mbed_official	532:fe11edbda85c	1239	{
mbed_official	532:fe11edbda85c	1240	/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
mbed_official	532:fe11edbda85c	1241	__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
mbed_official	532:fe11edbda85c	1242	}
mbed_official	532:fe11edbda85c	1243	}
mbed_official	532:fe11edbda85c	1244	else
mbed_official	532:fe11edbda85c	1245	{
mbed_official	532:fe11edbda85c	1246	/* Check the HSI State */
mbed_official	532:fe11edbda85c	1247	if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF)
mbed_official	532:fe11edbda85c	1248	{
mbed_official	532:fe11edbda85c	1249	/* Enable the Internal High Speed oscillator (HSI). */
mbed_official	532:fe11edbda85c	1250	__HAL_RCC_HSI_ENABLE();
mbed_official	532:fe11edbda85c	1251
mbed_official	532:fe11edbda85c	1252	/* Get Start Tick*/
mbed_official	532:fe11edbda85c	1253	tickstart = HAL_GetTick();
mbed_official	532:fe11edbda85c	1254
mbed_official	532:fe11edbda85c	1255	/* Wait till HSI is ready */
mbed_official	532:fe11edbda85c	1256	while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
mbed_official	532:fe11edbda85c	1257	{
mbed_official	532:fe11edbda85c	1258	if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
mbed_official	532:fe11edbda85c	1259	{
mbed_official	532:fe11edbda85c	1260	return HAL_TIMEOUT;
mbed_official	532:fe11edbda85c	1261	}
mbed_official	532:fe11edbda85c	1262	}
mbed_official	532:fe11edbda85c	1263
mbed_official	532:fe11edbda85c	1264	/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
mbed_official	532:fe11edbda85c	1265	__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
mbed_official	532:fe11edbda85c	1266	}
mbed_official	532:fe11edbda85c	1267	else
mbed_official	532:fe11edbda85c	1268	{
mbed_official	532:fe11edbda85c	1269	/* Disable the Internal High Speed oscillator (HSI). */
mbed_official	532:fe11edbda85c	1270	__HAL_RCC_HSI_DISABLE();
mbed_official	532:fe11edbda85c	1271
mbed_official	532:fe11edbda85c	1272	/* Get Start Tick*/
mbed_official	532:fe11edbda85c	1273	tickstart = HAL_GetTick();
mbed_official	532:fe11edbda85c	1274
mbed_official	532:fe11edbda85c	1275	/* Wait till HSI is ready */
mbed_official	532:fe11edbda85c	1276	while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
mbed_official	532:fe11edbda85c	1277	{
mbed_official	532:fe11edbda85c	1278	if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
mbed_official	532:fe11edbda85c	1279	{
mbed_official	532:fe11edbda85c	1280	return HAL_TIMEOUT;
mbed_official	532:fe11edbda85c	1281	}
mbed_official	532:fe11edbda85c	1282	}
mbed_official	532:fe11edbda85c	1283	}
mbed_official	532:fe11edbda85c	1284	}
mbed_official	532:fe11edbda85c	1285	}
mbed_official	532:fe11edbda85c	1286	/------------------------------ LSI Configuration -------------------------/
mbed_official	532:fe11edbda85c	1287	if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
mbed_official	532:fe11edbda85c	1288	{
mbed_official	532:fe11edbda85c	1289	/* Check the parameters */
mbed_official	532:fe11edbda85c	1290	assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
mbed_official	532:fe11edbda85c	1291
mbed_official	532:fe11edbda85c	1292	/* Check the LSI State */
mbed_official	532:fe11edbda85c	1293	if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF)
mbed_official	532:fe11edbda85c	1294	{
mbed_official	532:fe11edbda85c	1295	/* Enable the Internal Low Speed oscillator (LSI). */
mbed_official	532:fe11edbda85c	1296	__HAL_RCC_LSI_ENABLE();
mbed_official	532:fe11edbda85c	1297
mbed_official	532:fe11edbda85c	1298	/* Get Start Tick*/
mbed_official	532:fe11edbda85c	1299	tickstart = HAL_GetTick();
mbed_official	532:fe11edbda85c	1300
mbed_official	532:fe11edbda85c	1301	/* Wait till LSI is ready */
mbed_official	532:fe11edbda85c	1302	while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
mbed_official	532:fe11edbda85c	1303	{
mbed_official	532:fe11edbda85c	1304	if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
mbed_official	532:fe11edbda85c	1305	{
mbed_official	532:fe11edbda85c	1306	return HAL_TIMEOUT;
mbed_official	532:fe11edbda85c	1307	}
mbed_official	532:fe11edbda85c	1308	}
mbed_official	532:fe11edbda85c	1309	}
mbed_official	532:fe11edbda85c	1310	else
mbed_official	532:fe11edbda85c	1311	{
mbed_official	532:fe11edbda85c	1312	/* Disable the Internal Low Speed oscillator (LSI). */
mbed_official	532:fe11edbda85c	1313	__HAL_RCC_LSI_DISABLE();
mbed_official	532:fe11edbda85c	1314
mbed_official	532:fe11edbda85c	1315	/* Get Start Tick*/
mbed_official	532:fe11edbda85c	1316	tickstart = HAL_GetTick();
mbed_official	532:fe11edbda85c	1317
mbed_official	532:fe11edbda85c	1318	/* Wait till LSI is ready */
mbed_official	532:fe11edbda85c	1319	while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
mbed_official	532:fe11edbda85c	1320	{
mbed_official	532:fe11edbda85c	1321	if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
mbed_official	532:fe11edbda85c	1322	{
mbed_official	532:fe11edbda85c	1323	return HAL_TIMEOUT;
mbed_official	532:fe11edbda85c	1324	}
mbed_official	532:fe11edbda85c	1325	}
mbed_official	532:fe11edbda85c	1326	}
mbed_official	532:fe11edbda85c	1327	}
mbed_official	532:fe11edbda85c	1328	/------------------------------ LSE Configuration -------------------------/
mbed_official	532:fe11edbda85c	1329	if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
mbed_official	532:fe11edbda85c	1330	{
mbed_official	532:fe11edbda85c	1331	/* Check the parameters */
mbed_official	532:fe11edbda85c	1332	assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
mbed_official	532:fe11edbda85c	1333
mbed_official	532:fe11edbda85c	1334	/* Enable Power Clock*/
mbed_official	532:fe11edbda85c	1335	__HAL_RCC_PWR_CLK_ENABLE();
mbed_official	532:fe11edbda85c	1336
mbed_official	532:fe11edbda85c	1337	/* Enable write access to Backup domain */
mbed_official	532:fe11edbda85c	1338	PWR->CR \|= PWR_CR_DBP;
mbed_official	532:fe11edbda85c	1339
mbed_official	532:fe11edbda85c	1340	/* Wait for Backup domain Write protection disable */
mbed_official	532:fe11edbda85c	1341	tickstart = HAL_GetTick();
mbed_official	532:fe11edbda85c	1342
mbed_official	532:fe11edbda85c	1343	while((PWR->CR & PWR_CR_DBP) == RESET)
mbed_official	532:fe11edbda85c	1344	{
mbed_official	532:fe11edbda85c	1345	if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
mbed_official	532:fe11edbda85c	1346	{
mbed_official	532:fe11edbda85c	1347	return HAL_TIMEOUT;
mbed_official	532:fe11edbda85c	1348	}
mbed_official	532:fe11edbda85c	1349	}
mbed_official	532:fe11edbda85c	1350
mbed_official	532:fe11edbda85c	1351	/* Reset LSEON and LSEBYP bits before configuring the LSE ----------------*/
mbed_official	532:fe11edbda85c	1352	__HAL_RCC_LSE_CONFIG(RCC_LSE_OFF);
mbed_official	532:fe11edbda85c	1353
mbed_official	532:fe11edbda85c	1354	/* Get Start Tick*/
mbed_official	532:fe11edbda85c	1355	tickstart = HAL_GetTick();
mbed_official	532:fe11edbda85c	1356
mbed_official	532:fe11edbda85c	1357	/* Wait till LSE is ready */
mbed_official	532:fe11edbda85c	1358	while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
mbed_official	532:fe11edbda85c	1359	{
mbed_official	532:fe11edbda85c	1360	if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
mbed_official	532:fe11edbda85c	1361	{
mbed_official	532:fe11edbda85c	1362	return HAL_TIMEOUT;
mbed_official	532:fe11edbda85c	1363	}
mbed_official	532:fe11edbda85c	1364	}
mbed_official	532:fe11edbda85c	1365
mbed_official	532:fe11edbda85c	1366	/* Set the new LSE configuration -----------------------------------------*/
mbed_official	532:fe11edbda85c	1367	__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
mbed_official	532:fe11edbda85c	1368	/* Check the LSE State */
mbed_official	532:fe11edbda85c	1369	if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
mbed_official	532:fe11edbda85c	1370	{
mbed_official	532:fe11edbda85c	1371	/* Get Start Tick*/
mbed_official	532:fe11edbda85c	1372	tickstart = HAL_GetTick();
mbed_official	532:fe11edbda85c	1373
mbed_official	532:fe11edbda85c	1374	/* Wait till LSE is ready */
mbed_official	532:fe11edbda85c	1375	while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
mbed_official	532:fe11edbda85c	1376	{
mbed_official	532:fe11edbda85c	1377	if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
mbed_official	532:fe11edbda85c	1378	{
mbed_official	532:fe11edbda85c	1379	return HAL_TIMEOUT;
mbed_official	532:fe11edbda85c	1380	}
mbed_official	532:fe11edbda85c	1381	}
mbed_official	532:fe11edbda85c	1382	}
mbed_official	532:fe11edbda85c	1383	else
mbed_official	532:fe11edbda85c	1384	{
mbed_official	532:fe11edbda85c	1385	/* Get Start Tick*/
mbed_official	532:fe11edbda85c	1386	tickstart = HAL_GetTick();
mbed_official	532:fe11edbda85c	1387
mbed_official	532:fe11edbda85c	1388	/* Wait till LSE is ready */
mbed_official	532:fe11edbda85c	1389	while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
mbed_official	532:fe11edbda85c	1390	{
mbed_official	532:fe11edbda85c	1391	if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
mbed_official	532:fe11edbda85c	1392	{
mbed_official	532:fe11edbda85c	1393	return HAL_TIMEOUT;
mbed_official	532:fe11edbda85c	1394	}
mbed_official	532:fe11edbda85c	1395	}
mbed_official	532:fe11edbda85c	1396	}
mbed_official	532:fe11edbda85c	1397	}
mbed_official	532:fe11edbda85c	1398	/-------------------------------- PLL Configuration -----------------------/
mbed_official	532:fe11edbda85c	1399	/* Check the parameters */
mbed_official	532:fe11edbda85c	1400	assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
mbed_official	532:fe11edbda85c	1401	if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
mbed_official	532:fe11edbda85c	1402	{
mbed_official	532:fe11edbda85c	1403	/* Check if the PLL is used as system clock or not */
mbed_official	532:fe11edbda85c	1404	if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
mbed_official	532:fe11edbda85c	1405	{
mbed_official	532:fe11edbda85c	1406	if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
mbed_official	532:fe11edbda85c	1407	{
mbed_official	532:fe11edbda85c	1408	/* Check the parameters */
mbed_official	532:fe11edbda85c	1409	assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
mbed_official	532:fe11edbda85c	1410	assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM));
mbed_official	532:fe11edbda85c	1411	assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));
mbed_official	532:fe11edbda85c	1412	assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
mbed_official	532:fe11edbda85c	1413	assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
mbed_official	532:fe11edbda85c	1414	assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));
mbed_official	532:fe11edbda85c	1415
mbed_official	532:fe11edbda85c	1416	/* Disable the main PLL. */
mbed_official	532:fe11edbda85c	1417	__HAL_RCC_PLL_DISABLE();
mbed_official	532:fe11edbda85c	1418
mbed_official	532:fe11edbda85c	1419	/* Get Start Tick*/
mbed_official	532:fe11edbda85c	1420	tickstart = HAL_GetTick();
mbed_official	532:fe11edbda85c	1421
mbed_official	532:fe11edbda85c	1422	/* Wait till PLL is ready */
mbed_official	532:fe11edbda85c	1423	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
mbed_official	532:fe11edbda85c	1424	{
mbed_official	532:fe11edbda85c	1425	if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
mbed_official	532:fe11edbda85c	1426	{
mbed_official	532:fe11edbda85c	1427	return HAL_TIMEOUT;
mbed_official	532:fe11edbda85c	1428	}
mbed_official	532:fe11edbda85c	1429	}
mbed_official	532:fe11edbda85c	1430
mbed_official	532:fe11edbda85c	1431	/* Configure the main PLL clock source, multiplication and division factors. */
mbed_official	532:fe11edbda85c	1432	__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
mbed_official	532:fe11edbda85c	1433	RCC_OscInitStruct->PLL.PLLM,
mbed_official	532:fe11edbda85c	1434	RCC_OscInitStruct->PLL.PLLN,
mbed_official	532:fe11edbda85c	1435	RCC_OscInitStruct->PLL.PLLP,
mbed_official	532:fe11edbda85c	1436	RCC_OscInitStruct->PLL.PLLQ,
mbed_official	532:fe11edbda85c	1437	RCC_OscInitStruct->PLL.PLLR);
mbed_official	532:fe11edbda85c	1438
mbed_official	532:fe11edbda85c	1439	/* Enable the main PLL. */
mbed_official	532:fe11edbda85c	1440	__HAL_RCC_PLL_ENABLE();
mbed_official	532:fe11edbda85c	1441
mbed_official	532:fe11edbda85c	1442	/* Get Start Tick*/
mbed_official	532:fe11edbda85c	1443	tickstart = HAL_GetTick();
mbed_official	532:fe11edbda85c	1444
mbed_official	532:fe11edbda85c	1445	/* Wait till PLL is ready */
mbed_official	532:fe11edbda85c	1446	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
mbed_official	532:fe11edbda85c	1447	{
mbed_official	532:fe11edbda85c	1448	if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
mbed_official	532:fe11edbda85c	1449	{
mbed_official	532:fe11edbda85c	1450	return HAL_TIMEOUT;
mbed_official	532:fe11edbda85c	1451	}
mbed_official	532:fe11edbda85c	1452	}
mbed_official	532:fe11edbda85c	1453	}
mbed_official	532:fe11edbda85c	1454	else
mbed_official	532:fe11edbda85c	1455	{
mbed_official	532:fe11edbda85c	1456	/* Disable the main PLL. */
mbed_official	532:fe11edbda85c	1457	__HAL_RCC_PLL_DISABLE();
mbed_official	532:fe11edbda85c	1458
mbed_official	532:fe11edbda85c	1459	/* Get Start Tick*/
mbed_official	532:fe11edbda85c	1460	tickstart = HAL_GetTick();
mbed_official	532:fe11edbda85c	1461
mbed_official	532:fe11edbda85c	1462	/* Wait till PLL is ready */
mbed_official	532:fe11edbda85c	1463	while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
mbed_official	532:fe11edbda85c	1464	{
mbed_official	532:fe11edbda85c	1465	if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
mbed_official	532:fe11edbda85c	1466	{
mbed_official	532:fe11edbda85c	1467	return HAL_TIMEOUT;
mbed_official	532:fe11edbda85c	1468	}
mbed_official	532:fe11edbda85c	1469	}
mbed_official	532:fe11edbda85c	1470	}
mbed_official	532:fe11edbda85c	1471	}
mbed_official	532:fe11edbda85c	1472	else
mbed_official	532:fe11edbda85c	1473	{
mbed_official	532:fe11edbda85c	1474	return HAL_ERROR;
mbed_official	532:fe11edbda85c	1475	}
mbed_official	532:fe11edbda85c	1476	}
mbed_official	532:fe11edbda85c	1477	return HAL_OK;
mbed_official	532:fe11edbda85c	1478	}
mbed_official	532:fe11edbda85c	1479
mbed_official	532:fe11edbda85c	1480	/**
mbed_official	532:fe11edbda85c	1481	* @brief Configures the RCC_OscInitStruct according to the internal
mbed_official	532:fe11edbda85c	1482	* RCC configuration registers.
mbed_official	532:fe11edbda85c	1483	* @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that will be configured.
mbed_official	532:fe11edbda85c	1484	*
mbed_official	532:fe11edbda85c	1485	* @note This function is only available in case of STM32F446xx devices.
mbed_official	532:fe11edbda85c	1486	* @note This function add the PLL/PLLR factor management
mbed_official	532:fe11edbda85c	1487	* @retval None
mbed_official	532:fe11edbda85c	1488	*/
mbed_official	532:fe11edbda85c	1489	void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
mbed_official	532:fe11edbda85c	1490	{
mbed_official	532:fe11edbda85c	1491	/* Set all possible values for the Oscillator type parameter ---------------*/
mbed_official	532:fe11edbda85c	1492	RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE \| RCC_OSCILLATORTYPE_HSI \| RCC_OSCILLATORTYPE_LSE \| RCC_OSCILLATORTYPE_LSI;
mbed_official	532:fe11edbda85c	1493
mbed_official	532:fe11edbda85c	1494	/* Get the HSE configuration -----------------------------------------------*/
mbed_official	532:fe11edbda85c	1495	if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
mbed_official	532:fe11edbda85c	1496	{
mbed_official	532:fe11edbda85c	1497	RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
mbed_official	532:fe11edbda85c	1498	}
mbed_official	532:fe11edbda85c	1499	else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON)
mbed_official	532:fe11edbda85c	1500	{
mbed_official	532:fe11edbda85c	1501	RCC_OscInitStruct->HSEState = RCC_HSE_ON;
mbed_official	532:fe11edbda85c	1502	}
mbed_official	532:fe11edbda85c	1503	else
mbed_official	532:fe11edbda85c	1504	{
mbed_official	532:fe11edbda85c	1505	RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
mbed_official	532:fe11edbda85c	1506	}
mbed_official	532:fe11edbda85c	1507
mbed_official	532:fe11edbda85c	1508	/* Get the HSI configuration -----------------------------------------------*/
mbed_official	532:fe11edbda85c	1509	if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION)
mbed_official	532:fe11edbda85c	1510	{
mbed_official	532:fe11edbda85c	1511	RCC_OscInitStruct->HSIState = RCC_HSI_ON;
mbed_official	532:fe11edbda85c	1512	}
mbed_official	532:fe11edbda85c	1513	else
mbed_official	532:fe11edbda85c	1514	{
mbed_official	532:fe11edbda85c	1515	RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
mbed_official	532:fe11edbda85c	1516	}
mbed_official	532:fe11edbda85c	1517
mbed_official	532:fe11edbda85c	1518	RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR &RCC_CR_HSITRIM) >> POSITION_VAL(RCC_CR_HSITRIM));
mbed_official	532:fe11edbda85c	1519
mbed_official	532:fe11edbda85c	1520	/* Get the LSE configuration -----------------------------------------------*/
mbed_official	532:fe11edbda85c	1521	if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
mbed_official	532:fe11edbda85c	1522	{
mbed_official	532:fe11edbda85c	1523	RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
mbed_official	532:fe11edbda85c	1524	}
mbed_official	532:fe11edbda85c	1525	else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
mbed_official	532:fe11edbda85c	1526	{
mbed_official	532:fe11edbda85c	1527	RCC_OscInitStruct->LSEState = RCC_LSE_ON;
mbed_official	532:fe11edbda85c	1528	}
mbed_official	532:fe11edbda85c	1529	else
mbed_official	532:fe11edbda85c	1530	{
mbed_official	532:fe11edbda85c	1531	RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
mbed_official	532:fe11edbda85c	1532	}
mbed_official	532:fe11edbda85c	1533
mbed_official	532:fe11edbda85c	1534	/* Get the LSI configuration -----------------------------------------------*/
mbed_official	532:fe11edbda85c	1535	if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION)
mbed_official	532:fe11edbda85c	1536	{
mbed_official	532:fe11edbda85c	1537	RCC_OscInitStruct->LSIState = RCC_LSI_ON;
mbed_official	532:fe11edbda85c	1538	}
mbed_official	532:fe11edbda85c	1539	else
mbed_official	532:fe11edbda85c	1540	{
mbed_official	532:fe11edbda85c	1541	RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
mbed_official	532:fe11edbda85c	1542	}
mbed_official	532:fe11edbda85c	1543
mbed_official	532:fe11edbda85c	1544	/* Get the PLL configuration -----------------------------------------------*/
mbed_official	532:fe11edbda85c	1545	if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON)
mbed_official	532:fe11edbda85c	1546	{
mbed_official	532:fe11edbda85c	1547	RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
mbed_official	532:fe11edbda85c	1548	}
mbed_official	532:fe11edbda85c	1549	else
mbed_official	532:fe11edbda85c	1550	{
mbed_official	532:fe11edbda85c	1551	RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
mbed_official	532:fe11edbda85c	1552	}
mbed_official	532:fe11edbda85c	1553	RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
mbed_official	532:fe11edbda85c	1554	RCC_OscInitStruct->PLL.PLLM = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM);
mbed_official	532:fe11edbda85c	1555	RCC_OscInitStruct->PLL.PLLN = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN));
mbed_official	532:fe11edbda85c	1556	RCC_OscInitStruct->PLL.PLLP = (uint32_t)((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) + RCC_PLLCFGR_PLLP_0) << 1) >> POSITION_VAL(RCC_PLLCFGR_PLLP));
mbed_official	532:fe11edbda85c	1557	RCC_OscInitStruct->PLL.PLLQ = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLQ) >> POSITION_VAL(RCC_PLLCFGR_PLLQ));
mbed_official	532:fe11edbda85c	1558	RCC_OscInitStruct->PLL.PLLR = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> POSITION_VAL(RCC_PLLCFGR_PLLR));
mbed_official	532:fe11edbda85c	1559	}
mbed_official	532:fe11edbda85c	1560
mbed_official	532:fe11edbda85c	1561	/**
mbed_official	532:fe11edbda85c	1562	* @brief Returns the SYSCLK frequency
mbed_official	532:fe11edbda85c	1563	*
mbed_official	532:fe11edbda85c	1564	* @note This function is only available in case of STM32F446xx devices.
mbed_official	532:fe11edbda85c	1565	* @note This function add the PLL/PLLR System clock source
mbed_official	532:fe11edbda85c	1566	*
mbed_official	532:fe11edbda85c	1567	* @note The system frequency computed by this function is not the real
mbed_official	532:fe11edbda85c	1568	* frequency in the chip. It is calculated based on the predefined
mbed_official	532:fe11edbda85c	1569	* constant and the selected clock source:
mbed_official	532:fe11edbda85c	1570	* @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
mbed_official	532:fe11edbda85c	1571	* @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)
mbed_official	532:fe11edbda85c	1572	* @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**)
mbed_official	532:fe11edbda85c	1573	* or HSI_VALUE(*) multiplied/divided by the PLL factors.
mbed_official	532:fe11edbda85c	1574	* @note (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
mbed_official	532:fe11edbda85c	1575	* 16 MHz) but the real value may vary depending on the variations
mbed_official	532:fe11edbda85c	1576	* in voltage and temperature.
mbed_official	532:fe11edbda85c	1577	* @note (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
mbed_official	532:fe11edbda85c	1578	* 25 MHz), user has to ensure that HSE_VALUE is same as the real
mbed_official	532:fe11edbda85c	1579	* frequency of the crystal used. Otherwise, this function may
mbed_official	532:fe11edbda85c	1580	* have wrong result.
mbed_official	532:fe11edbda85c	1581	*
mbed_official	532:fe11edbda85c	1582	* @note The result of this function could be not correct when using fractional
mbed_official	532:fe11edbda85c	1583	* value for HSE crystal.
mbed_official	532:fe11edbda85c	1584	*
mbed_official	532:fe11edbda85c	1585	* @note This function can be used by the user application to compute the
mbed_official	532:fe11edbda85c	1586	* baudrate for the communication peripherals or configure other parameters.
mbed_official	532:fe11edbda85c	1587	*
mbed_official	532:fe11edbda85c	1588	* @note Each time SYSCLK changes, this function must be called to update the
mbed_official	532:fe11edbda85c	1589	* right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
mbed_official	532:fe11edbda85c	1590	*
mbed_official	532:fe11edbda85c	1591	*
mbed_official	532:fe11edbda85c	1592	* @retval SYSCLK frequency
mbed_official	532:fe11edbda85c	1593	*/
mbed_official	532:fe11edbda85c	1594	uint32_t HAL_RCC_GetSysClockFreq(void)
mbed_official	532:fe11edbda85c	1595	{
mbed_official	532:fe11edbda85c	1596	uint32_t pllm = 0;
mbed_official	532:fe11edbda85c	1597	uint32_t pllvco = 0;
mbed_official	532:fe11edbda85c	1598	uint32_t pllp = 0;
mbed_official	532:fe11edbda85c	1599	uint32_t pllr = 0;
mbed_official	532:fe11edbda85c	1600	uint32_t sysclockfreq = 0;
mbed_official	532:fe11edbda85c	1601
mbed_official	532:fe11edbda85c	1602	/* Get SYSCLK source -------------------------------------------------------*/
mbed_official	532:fe11edbda85c	1603	switch (RCC->CFGR & RCC_CFGR_SWS)
mbed_official	532:fe11edbda85c	1604	{
mbed_official	532:fe11edbda85c	1605	case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */
mbed_official	532:fe11edbda85c	1606	{
mbed_official	532:fe11edbda85c	1607	sysclockfreq = HSI_VALUE;
mbed_official	532:fe11edbda85c	1608	break;
mbed_official	532:fe11edbda85c	1609	}
mbed_official	532:fe11edbda85c	1610	case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */
mbed_official	532:fe11edbda85c	1611	{
mbed_official	532:fe11edbda85c	1612	sysclockfreq = HSE_VALUE;
mbed_official	532:fe11edbda85c	1613	break;
mbed_official	532:fe11edbda85c	1614	}
mbed_official	532:fe11edbda85c	1615	case RCC_CFGR_SWS_PLL: /* PLL/PLLP used as system clock source */
mbed_official	532:fe11edbda85c	1616	{
mbed_official	532:fe11edbda85c	1617	/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
mbed_official	532:fe11edbda85c	1618	SYSCLK = PLL_VCO / PLLP */
mbed_official	532:fe11edbda85c	1619	pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
mbed_official	532:fe11edbda85c	1620	if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)
mbed_official	532:fe11edbda85c	1621	{
mbed_official	532:fe11edbda85c	1622	/* HSE used as PLL clock source */
mbed_official	532:fe11edbda85c	1623	pllvco = ((HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));
mbed_official	532:fe11edbda85c	1624	}
mbed_official	532:fe11edbda85c	1625	else
mbed_official	532:fe11edbda85c	1626	{
mbed_official	532:fe11edbda85c	1627	/* HSI used as PLL clock source */
mbed_official	532:fe11edbda85c	1628	pllvco = ((HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));
mbed_official	532:fe11edbda85c	1629	}
mbed_official	532:fe11edbda85c	1630	pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> POSITION_VAL(RCC_PLLCFGR_PLLP)) + 1 ) *2);
mbed_official	532:fe11edbda85c	1631
mbed_official	532:fe11edbda85c	1632	sysclockfreq = pllvco/pllp;
mbed_official	532:fe11edbda85c	1633	break;
mbed_official	532:fe11edbda85c	1634	}
mbed_official	532:fe11edbda85c	1635	case RCC_CFGR_SWS_PLLR: /* PLL/PLLR used as system clock source */
mbed_official	532:fe11edbda85c	1636	{
mbed_official	532:fe11edbda85c	1637	/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
mbed_official	532:fe11edbda85c	1638	SYSCLK = PLL_VCO / PLLR */
mbed_official	532:fe11edbda85c	1639	pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
mbed_official	532:fe11edbda85c	1640	if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)
mbed_official	532:fe11edbda85c	1641	{
mbed_official	532:fe11edbda85c	1642	/* HSE used as PLL clock source */
mbed_official	532:fe11edbda85c	1643	pllvco = ((HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));
mbed_official	532:fe11edbda85c	1644	}
mbed_official	532:fe11edbda85c	1645	else
mbed_official	532:fe11edbda85c	1646	{
mbed_official	532:fe11edbda85c	1647	/* HSI used as PLL clock source */
mbed_official	532:fe11edbda85c	1648	pllvco = ((HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));
mbed_official	532:fe11edbda85c	1649	}
mbed_official	532:fe11edbda85c	1650	pllr = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> POSITION_VAL(RCC_PLLCFGR_PLLR));
mbed_official	532:fe11edbda85c	1651
mbed_official	532:fe11edbda85c	1652	sysclockfreq = pllvco/pllr;
mbed_official	532:fe11edbda85c	1653	break;
mbed_official	532:fe11edbda85c	1654	}
mbed_official	532:fe11edbda85c	1655	default:
mbed_official	532:fe11edbda85c	1656	{
mbed_official	532:fe11edbda85c	1657	sysclockfreq = HSI_VALUE;
mbed_official	532:fe11edbda85c	1658	break;
mbed_official	532:fe11edbda85c	1659	}
mbed_official	532:fe11edbda85c	1660	}
mbed_official	532:fe11edbda85c	1661	return sysclockfreq;
mbed_official	532:fe11edbda85c	1662	}
mbed_official	532:fe11edbda85c	1663	#endif /* STM32F446xx */
mbed_official	235:685d5f11838f	1664
mbed_official	235:685d5f11838f	1665	/**
mbed_official	235:685d5f11838f	1666	* @}
mbed_official	235:685d5f11838f	1667	*/
mbed_official	235:685d5f11838f	1668
mbed_official	235:685d5f11838f	1669	/**
mbed_official	235:685d5f11838f	1670	* @}
mbed_official	235:685d5f11838f	1671	*/
mbed_official	235:685d5f11838f	1672
mbed_official	235:685d5f11838f	1673	#endif /* HAL_RCC_MODULE_ENABLED */
mbed_official	235:685d5f11838f	1674	/**
mbed_official	235:685d5f11838f	1675	* @}
mbed_official	235:685d5f11838f	1676	*/
mbed_official	235:685d5f11838f	1677
mbed_official	235:685d5f11838f	1678	/**
mbed_official	235:685d5f11838f	1679	* @}
mbed_official	235:685d5f11838f	1680	*/
mbed_official	235:685d5f11838f	1681
mbed_official	235:685d5f11838f	1682	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/