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Superseded

This library was superseded by mbed-dev - https://os.mbed.com/users/mbed_official/code/mbed-dev/.

Development branch of the mbed library sources. This library is kept in synch with the latest changes from the mbed SDK and it is not guaranteed to work.

If you are looking for a stable and tested release, please import one of the official mbed library releases:

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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Last commit 20 Feb 2019 by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_eth.h@581:39197bcd20f2, 2015-07-02 (annotated)

Committer:
mbed_official
Date:
Thu Jul 02 16:30:08 2015 +0100
Revision:
581:39197bcd20f2
Parent:
532:fe11edbda85c
Child:
613:bc40b8d2aec4
Synchronized with git revision ae2d3cdffe70184eb8736d94f76c45c93f4b7724



Full URL: https://github.com/mbedmicro/mbed/commit/ae2d3cdffe70184eb8736d94f76c45c93f4b7724/



Make it possible to build the core mbed library with yotta

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 87:085cde657901 1 /**
mbed_official 87:085cde657901 2 ******************************************************************************
mbed_official 87:085cde657901 3 * @file stm32f4xx_hal_eth.h
mbed_official 87:085cde657901 4 * @author MCD Application Team
mbed_official 532:fe11edbda85c 5 * @version V1.3.0
mbed_official 532:fe11edbda85c 6 * @date 09-March-2015
mbed_official 87:085cde657901 7 * @brief Header file of ETH HAL module.
mbed_official 87:085cde657901 8 ******************************************************************************
mbed_official 87:085cde657901 9 * @attention
mbed_official 87:085cde657901 10 *
mbed_official 532:fe11edbda85c 11 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
mbed_official 87:085cde657901 12 *
mbed_official 87:085cde657901 13 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 87:085cde657901 14 * are permitted provided that the following conditions are met:
mbed_official 87:085cde657901 15 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 87:085cde657901 16 * this list of conditions and the following disclaimer.
mbed_official 87:085cde657901 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 87:085cde657901 18 * this list of conditions and the following disclaimer in the documentation
mbed_official 87:085cde657901 19 * and/or other materials provided with the distribution.
mbed_official 87:085cde657901 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 87:085cde657901 21 * may be used to endorse or promote products derived from this software
mbed_official 87:085cde657901 22 * without specific prior written permission.
mbed_official 87:085cde657901 23 *
mbed_official 87:085cde657901 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 87:085cde657901 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 87:085cde657901 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 87:085cde657901 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 87:085cde657901 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 87:085cde657901 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 87:085cde657901 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 87:085cde657901 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 87:085cde657901 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 87:085cde657901 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 87:085cde657901 34 *
mbed_official 87:085cde657901 35 ******************************************************************************
mbed_official 87:085cde657901 36 */
mbed_official 87:085cde657901 37
mbed_official 87:085cde657901 38 /* Define to prevent recursive inclusion -------------------------------------*/
mbed_official 87:085cde657901 39 #ifndef __STM32F4xx_HAL_ETH_H
mbed_official 87:085cde657901 40 #define __STM32F4xx_HAL_ETH_H
mbed_official 87:085cde657901 41
mbed_official 87:085cde657901 42 #ifdef __cplusplus
mbed_official 87:085cde657901 43 extern "C" {
mbed_official 87:085cde657901 44 #endif
mbed_official 87:085cde657901 45
mbed_official 87:085cde657901 46 #if defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
mbed_official 87:085cde657901 47 /* Includes ------------------------------------------------------------------*/
mbed_official 87:085cde657901 48 #include "stm32f4xx_hal_def.h"
mbed_official 87:085cde657901 49
mbed_official 87:085cde657901 50 /** @addtogroup STM32F4xx_HAL_Driver
mbed_official 87:085cde657901 51 * @{
mbed_official 87:085cde657901 52 */
mbed_official 87:085cde657901 53
mbed_official 87:085cde657901 54 /** @addtogroup ETH
mbed_official 87:085cde657901 55 * @{
mbed_official 87:085cde657901 56 */
mbed_official 532:fe11edbda85c 57
mbed_official 532:fe11edbda85c 58 /** @addtogroup ETH_Private_Macros
mbed_official 532:fe11edbda85c 59 * @{
mbed_official 532:fe11edbda85c 60 */
mbed_official 532:fe11edbda85c 61 #define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20)
mbed_official 532:fe11edbda85c 62 #define IS_ETH_AUTONEGOTIATION(CMD) (((CMD) == ETH_AUTONEGOTIATION_ENABLE) || \
mbed_official 532:fe11edbda85c 63 ((CMD) == ETH_AUTONEGOTIATION_DISABLE))
mbed_official 532:fe11edbda85c 64 #define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_SPEED_10M) || \
mbed_official 532:fe11edbda85c 65 ((SPEED) == ETH_SPEED_100M))
mbed_official 532:fe11edbda85c 66 #define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_MODE_FULLDUPLEX) || \
mbed_official 532:fe11edbda85c 67 ((MODE) == ETH_MODE_HALFDUPLEX))
mbed_official 532:fe11edbda85c 68 #define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_MODE_FULLDUPLEX) || \
mbed_official 532:fe11edbda85c 69 ((MODE) == ETH_MODE_HALFDUPLEX))
mbed_official 532:fe11edbda85c 70 #define IS_ETH_RX_MODE(MODE) (((MODE) == ETH_RXPOLLING_MODE) || \
mbed_official 532:fe11edbda85c 71 ((MODE) == ETH_RXINTERRUPT_MODE))
mbed_official 532:fe11edbda85c 72 #define IS_ETH_RX_MODE(MODE) (((MODE) == ETH_RXPOLLING_MODE) || \
mbed_official 532:fe11edbda85c 73 ((MODE) == ETH_RXINTERRUPT_MODE))
mbed_official 532:fe11edbda85c 74 #define IS_ETH_RX_MODE(MODE) (((MODE) == ETH_RXPOLLING_MODE) || \
mbed_official 532:fe11edbda85c 75 ((MODE) == ETH_RXINTERRUPT_MODE))
mbed_official 532:fe11edbda85c 76 #define IS_ETH_CHECKSUM_MODE(MODE) (((MODE) == ETH_CHECKSUM_BY_HARDWARE) || \
mbed_official 532:fe11edbda85c 77 ((MODE) == ETH_CHECKSUM_BY_SOFTWARE))
mbed_official 532:fe11edbda85c 78 #define IS_ETH_MEDIA_INTERFACE(MODE) (((MODE) == ETH_MEDIA_INTERFACE_MII) || \
mbed_official 532:fe11edbda85c 79 ((MODE) == ETH_MEDIA_INTERFACE_RMII))
mbed_official 532:fe11edbda85c 80 #define IS_ETH_WATCHDOG(CMD) (((CMD) == ETH_WATCHDOG_ENABLE) || \
mbed_official 532:fe11edbda85c 81 ((CMD) == ETH_WATCHDOG_DISABLE))
mbed_official 532:fe11edbda85c 82 #define IS_ETH_JABBER(CMD) (((CMD) == ETH_JABBER_ENABLE) || \
mbed_official 532:fe11edbda85c 83 ((CMD) == ETH_JABBER_DISABLE))
mbed_official 532:fe11edbda85c 84 #define IS_ETH_INTER_FRAME_GAP(GAP) (((GAP) == ETH_INTERFRAMEGAP_96BIT) || \
mbed_official 532:fe11edbda85c 85 ((GAP) == ETH_INTERFRAMEGAP_88BIT) || \
mbed_official 532:fe11edbda85c 86 ((GAP) == ETH_INTERFRAMEGAP_80BIT) || \
mbed_official 532:fe11edbda85c 87 ((GAP) == ETH_INTERFRAMEGAP_72BIT) || \
mbed_official 532:fe11edbda85c 88 ((GAP) == ETH_INTERFRAMEGAP_64BIT) || \
mbed_official 532:fe11edbda85c 89 ((GAP) == ETH_INTERFRAMEGAP_56BIT) || \
mbed_official 532:fe11edbda85c 90 ((GAP) == ETH_INTERFRAMEGAP_48BIT) || \
mbed_official 532:fe11edbda85c 91 ((GAP) == ETH_INTERFRAMEGAP_40BIT))
mbed_official 532:fe11edbda85c 92 #define IS_ETH_CARRIER_SENSE(CMD) (((CMD) == ETH_CARRIERSENCE_ENABLE) || \
mbed_official 532:fe11edbda85c 93 ((CMD) == ETH_CARRIERSENCE_DISABLE))
mbed_official 532:fe11edbda85c 94 #define IS_ETH_RECEIVE_OWN(CMD) (((CMD) == ETH_RECEIVEOWN_ENABLE) || \
mbed_official 532:fe11edbda85c 95 ((CMD) == ETH_RECEIVEOWN_DISABLE))
mbed_official 532:fe11edbda85c 96 #define IS_ETH_LOOPBACK_MODE(CMD) (((CMD) == ETH_LOOPBACKMODE_ENABLE) || \
mbed_official 532:fe11edbda85c 97 ((CMD) == ETH_LOOPBACKMODE_DISABLE))
mbed_official 532:fe11edbda85c 98 #define IS_ETH_CHECKSUM_OFFLOAD(CMD) (((CMD) == ETH_CHECKSUMOFFLAOD_ENABLE) || \
mbed_official 532:fe11edbda85c 99 ((CMD) == ETH_CHECKSUMOFFLAOD_DISABLE))
mbed_official 532:fe11edbda85c 100 #define IS_ETH_RETRY_TRANSMISSION(CMD) (((CMD) == ETH_RETRYTRANSMISSION_ENABLE) || \
mbed_official 532:fe11edbda85c 101 ((CMD) == ETH_RETRYTRANSMISSION_DISABLE))
mbed_official 532:fe11edbda85c 102 #define IS_ETH_AUTOMATIC_PADCRC_STRIP(CMD) (((CMD) == ETH_AUTOMATICPADCRCSTRIP_ENABLE) || \
mbed_official 532:fe11edbda85c 103 ((CMD) == ETH_AUTOMATICPADCRCSTRIP_DISABLE))
mbed_official 532:fe11edbda85c 104 #define IS_ETH_BACKOFF_LIMIT(LIMIT) (((LIMIT) == ETH_BACKOFFLIMIT_10) || \
mbed_official 532:fe11edbda85c 105 ((LIMIT) == ETH_BACKOFFLIMIT_8) || \
mbed_official 532:fe11edbda85c 106 ((LIMIT) == ETH_BACKOFFLIMIT_4) || \
mbed_official 532:fe11edbda85c 107 ((LIMIT) == ETH_BACKOFFLIMIT_1))
mbed_official 532:fe11edbda85c 108 #define IS_ETH_DEFERRAL_CHECK(CMD) (((CMD) == ETH_DEFFERRALCHECK_ENABLE) || \
mbed_official 532:fe11edbda85c 109 ((CMD) == ETH_DEFFERRALCHECK_DISABLE))
mbed_official 532:fe11edbda85c 110 #define IS_ETH_RECEIVE_ALL(CMD) (((CMD) == ETH_RECEIVEALL_ENABLE) || \
mbed_official 532:fe11edbda85c 111 ((CMD) == ETH_RECEIVEAll_DISABLE))
mbed_official 532:fe11edbda85c 112 #define IS_ETH_SOURCE_ADDR_FILTER(CMD) (((CMD) == ETH_SOURCEADDRFILTER_NORMAL_ENABLE) || \
mbed_official 532:fe11edbda85c 113 ((CMD) == ETH_SOURCEADDRFILTER_INVERSE_ENABLE) || \
mbed_official 532:fe11edbda85c 114 ((CMD) == ETH_SOURCEADDRFILTER_DISABLE))
mbed_official 532:fe11edbda85c 115 #define IS_ETH_CONTROL_FRAMES(PASS) (((PASS) == ETH_PASSCONTROLFRAMES_BLOCKALL) || \
mbed_official 532:fe11edbda85c 116 ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDALL) || \
mbed_official 532:fe11edbda85c 117 ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER))
mbed_official 532:fe11edbda85c 118 #define IS_ETH_BROADCAST_FRAMES_RECEPTION(CMD) (((CMD) == ETH_BROADCASTFRAMESRECEPTION_ENABLE) || \
mbed_official 532:fe11edbda85c 119 ((CMD) == ETH_BROADCASTFRAMESRECEPTION_DISABLE))
mbed_official 532:fe11edbda85c 120 #define IS_ETH_DESTINATION_ADDR_FILTER(FILTER) (((FILTER) == ETH_DESTINATIONADDRFILTER_NORMAL) || \
mbed_official 532:fe11edbda85c 121 ((FILTER) == ETH_DESTINATIONADDRFILTER_INVERSE))
mbed_official 532:fe11edbda85c 122 #define IS_ETH_PROMISCUOUS_MODE(CMD) (((CMD) == ETH_PROMISCUOUS_MODE_ENABLE) || \
mbed_official 532:fe11edbda85c 123 ((CMD) == ETH_PROMISCUOUS_MODE_DISABLE))
mbed_official 532:fe11edbda85c 124 #define IS_ETH_MULTICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE) || \
mbed_official 532:fe11edbda85c 125 ((FILTER) == ETH_MULTICASTFRAMESFILTER_HASHTABLE) || \
mbed_official 532:fe11edbda85c 126 ((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECT) || \
mbed_official 532:fe11edbda85c 127 ((FILTER) == ETH_MULTICASTFRAMESFILTER_NONE))
mbed_official 532:fe11edbda85c 128 #define IS_ETH_UNICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE) || \
mbed_official 532:fe11edbda85c 129 ((FILTER) == ETH_UNICASTFRAMESFILTER_HASHTABLE) || \
mbed_official 532:fe11edbda85c 130 ((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECT))
mbed_official 532:fe11edbda85c 131 #define IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFF)
mbed_official 532:fe11edbda85c 132 #define IS_ETH_ZEROQUANTA_PAUSE(CMD) (((CMD) == ETH_ZEROQUANTAPAUSE_ENABLE) || \
mbed_official 532:fe11edbda85c 133 ((CMD) == ETH_ZEROQUANTAPAUSE_DISABLE))
mbed_official 532:fe11edbda85c 134 #define IS_ETH_PAUSE_LOW_THRESHOLD(THRESHOLD) (((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS4) || \
mbed_official 532:fe11edbda85c 135 ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS28) || \
mbed_official 532:fe11edbda85c 136 ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS144) || \
mbed_official 532:fe11edbda85c 137 ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS256))
mbed_official 532:fe11edbda85c 138 #define IS_ETH_UNICAST_PAUSE_FRAME_DETECT(CMD) (((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_ENABLE) || \
mbed_official 532:fe11edbda85c 139 ((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_DISABLE))
mbed_official 532:fe11edbda85c 140 #define IS_ETH_RECEIVE_FLOWCONTROL(CMD) (((CMD) == ETH_RECEIVEFLOWCONTROL_ENABLE) || \
mbed_official 532:fe11edbda85c 141 ((CMD) == ETH_RECEIVEFLOWCONTROL_DISABLE))
mbed_official 532:fe11edbda85c 142 #define IS_ETH_TRANSMIT_FLOWCONTROL(CMD) (((CMD) == ETH_TRANSMITFLOWCONTROL_ENABLE) || \
mbed_official 532:fe11edbda85c 143 ((CMD) == ETH_TRANSMITFLOWCONTROL_DISABLE))
mbed_official 532:fe11edbda85c 144 #define IS_ETH_VLAN_TAG_COMPARISON(COMPARISON) (((COMPARISON) == ETH_VLANTAGCOMPARISON_12BIT) || \
mbed_official 532:fe11edbda85c 145 ((COMPARISON) == ETH_VLANTAGCOMPARISON_16BIT))
mbed_official 532:fe11edbda85c 146 #define IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFF)
mbed_official 532:fe11edbda85c 147 #define IS_ETH_MAC_ADDRESS0123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS0) || \
mbed_official 532:fe11edbda85c 148 ((ADDRESS) == ETH_MAC_ADDRESS1) || \
mbed_official 532:fe11edbda85c 149 ((ADDRESS) == ETH_MAC_ADDRESS2) || \
mbed_official 532:fe11edbda85c 150 ((ADDRESS) == ETH_MAC_ADDRESS3))
mbed_official 532:fe11edbda85c 151 #define IS_ETH_MAC_ADDRESS123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS1) || \
mbed_official 532:fe11edbda85c 152 ((ADDRESS) == ETH_MAC_ADDRESS2) || \
mbed_official 532:fe11edbda85c 153 ((ADDRESS) == ETH_MAC_ADDRESS3))
mbed_official 532:fe11edbda85c 154 #define IS_ETH_MAC_ADDRESS_FILTER(FILTER) (((FILTER) == ETH_MAC_ADDRESSFILTER_SA) || \
mbed_official 532:fe11edbda85c 155 ((FILTER) == ETH_MAC_ADDRESSFILTER_DA))
mbed_official 532:fe11edbda85c 156 #define IS_ETH_MAC_ADDRESS_MASK(MASK) (((MASK) == ETH_MAC_ADDRESSMASK_BYTE6) || \
mbed_official 532:fe11edbda85c 157 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE5) || \
mbed_official 532:fe11edbda85c 158 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE4) || \
mbed_official 532:fe11edbda85c 159 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE3) || \
mbed_official 532:fe11edbda85c 160 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE2) || \
mbed_official 532:fe11edbda85c 161 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE1))
mbed_official 532:fe11edbda85c 162 #define IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(CMD) (((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE) || \
mbed_official 532:fe11edbda85c 163 ((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE))
mbed_official 532:fe11edbda85c 164 #define IS_ETH_RECEIVE_STORE_FORWARD(CMD) (((CMD) == ETH_RECEIVESTOREFORWARD_ENABLE) || \
mbed_official 532:fe11edbda85c 165 ((CMD) == ETH_RECEIVESTOREFORWARD_DISABLE))
mbed_official 532:fe11edbda85c 166 #define IS_ETH_FLUSH_RECEIVE_FRAME(CMD) (((CMD) == ETH_FLUSHRECEIVEDFRAME_ENABLE) || \
mbed_official 532:fe11edbda85c 167 ((CMD) == ETH_FLUSHRECEIVEDFRAME_DISABLE))
mbed_official 532:fe11edbda85c 168 #define IS_ETH_TRANSMIT_STORE_FORWARD(CMD) (((CMD) == ETH_TRANSMITSTOREFORWARD_ENABLE) || \
mbed_official 532:fe11edbda85c 169 ((CMD) == ETH_TRANSMITSTOREFORWARD_DISABLE))
mbed_official 532:fe11edbda85c 170 #define IS_ETH_TRANSMIT_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_64BYTES) || \
mbed_official 532:fe11edbda85c 171 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_128BYTES) || \
mbed_official 532:fe11edbda85c 172 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_192BYTES) || \
mbed_official 532:fe11edbda85c 173 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_256BYTES) || \
mbed_official 532:fe11edbda85c 174 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_40BYTES) || \
mbed_official 532:fe11edbda85c 175 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_32BYTES) || \
mbed_official 532:fe11edbda85c 176 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_24BYTES) || \
mbed_official 532:fe11edbda85c 177 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_16BYTES))
mbed_official 532:fe11edbda85c 178 #define IS_ETH_FORWARD_ERROR_FRAMES(CMD) (((CMD) == ETH_FORWARDERRORFRAMES_ENABLE) || \
mbed_official 532:fe11edbda85c 179 ((CMD) == ETH_FORWARDERRORFRAMES_DISABLE))
mbed_official 532:fe11edbda85c 180 #define IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(CMD) (((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE) || \
mbed_official 532:fe11edbda85c 181 ((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE))
mbed_official 532:fe11edbda85c 182 #define IS_ETH_RECEIVE_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES) || \
mbed_official 532:fe11edbda85c 183 ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES) || \
mbed_official 532:fe11edbda85c 184 ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES) || \
mbed_official 532:fe11edbda85c 185 ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES))
mbed_official 532:fe11edbda85c 186 #define IS_ETH_SECOND_FRAME_OPERATE(CMD) (((CMD) == ETH_SECONDFRAMEOPERARTE_ENABLE) || \
mbed_official 532:fe11edbda85c 187 ((CMD) == ETH_SECONDFRAMEOPERARTE_DISABLE))
mbed_official 532:fe11edbda85c 188 #define IS_ETH_ADDRESS_ALIGNED_BEATS(CMD) (((CMD) == ETH_ADDRESSALIGNEDBEATS_ENABLE) || \
mbed_official 532:fe11edbda85c 189 ((CMD) == ETH_ADDRESSALIGNEDBEATS_DISABLE))
mbed_official 532:fe11edbda85c 190 #define IS_ETH_FIXED_BURST(CMD) (((CMD) == ETH_FIXEDBURST_ENABLE) || \
mbed_official 532:fe11edbda85c 191 ((CMD) == ETH_FIXEDBURST_DISABLE))
mbed_official 532:fe11edbda85c 192 #define IS_ETH_RXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_RXDMABURSTLENGTH_1BEAT) || \
mbed_official 532:fe11edbda85c 193 ((LENGTH) == ETH_RXDMABURSTLENGTH_2BEAT) || \
mbed_official 532:fe11edbda85c 194 ((LENGTH) == ETH_RXDMABURSTLENGTH_4BEAT) || \
mbed_official 532:fe11edbda85c 195 ((LENGTH) == ETH_RXDMABURSTLENGTH_8BEAT) || \
mbed_official 532:fe11edbda85c 196 ((LENGTH) == ETH_RXDMABURSTLENGTH_16BEAT) || \
mbed_official 532:fe11edbda85c 197 ((LENGTH) == ETH_RXDMABURSTLENGTH_32BEAT) || \
mbed_official 532:fe11edbda85c 198 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_4BEAT) || \
mbed_official 532:fe11edbda85c 199 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_8BEAT) || \
mbed_official 532:fe11edbda85c 200 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_16BEAT) || \
mbed_official 532:fe11edbda85c 201 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_32BEAT) || \
mbed_official 532:fe11edbda85c 202 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_64BEAT) || \
mbed_official 532:fe11edbda85c 203 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_128BEAT))
mbed_official 532:fe11edbda85c 204 #define IS_ETH_TXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_TXDMABURSTLENGTH_1BEAT) || \
mbed_official 532:fe11edbda85c 205 ((LENGTH) == ETH_TXDMABURSTLENGTH_2BEAT) || \
mbed_official 532:fe11edbda85c 206 ((LENGTH) == ETH_TXDMABURSTLENGTH_4BEAT) || \
mbed_official 532:fe11edbda85c 207 ((LENGTH) == ETH_TXDMABURSTLENGTH_8BEAT) || \
mbed_official 532:fe11edbda85c 208 ((LENGTH) == ETH_TXDMABURSTLENGTH_16BEAT) || \
mbed_official 532:fe11edbda85c 209 ((LENGTH) == ETH_TXDMABURSTLENGTH_32BEAT) || \
mbed_official 532:fe11edbda85c 210 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_4BEAT) || \
mbed_official 532:fe11edbda85c 211 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_8BEAT) || \
mbed_official 532:fe11edbda85c 212 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_16BEAT) || \
mbed_official 532:fe11edbda85c 213 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_32BEAT) || \
mbed_official 532:fe11edbda85c 214 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_64BEAT) || \
mbed_official 532:fe11edbda85c 215 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_128BEAT))
mbed_official 532:fe11edbda85c 216 #define IS_ETH_DMA_DESC_SKIP_LENGTH(LENGTH) ((LENGTH) <= 0x1F)
mbed_official 532:fe11edbda85c 217 #define IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(RATIO) (((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1) || \
mbed_official 532:fe11edbda85c 218 ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1) || \
mbed_official 532:fe11edbda85c 219 ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1) || \
mbed_official 532:fe11edbda85c 220 ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1) || \
mbed_official 532:fe11edbda85c 221 ((RATIO) == ETH_DMAARBITRATION_RXPRIORTX))
mbed_official 532:fe11edbda85c 222 #define IS_ETH_DMATXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMATXDESC_OWN) || \
mbed_official 532:fe11edbda85c 223 ((FLAG) == ETH_DMATXDESC_IC) || \
mbed_official 532:fe11edbda85c 224 ((FLAG) == ETH_DMATXDESC_LS) || \
mbed_official 532:fe11edbda85c 225 ((FLAG) == ETH_DMATXDESC_FS) || \
mbed_official 532:fe11edbda85c 226 ((FLAG) == ETH_DMATXDESC_DC) || \
mbed_official 532:fe11edbda85c 227 ((FLAG) == ETH_DMATXDESC_DP) || \
mbed_official 532:fe11edbda85c 228 ((FLAG) == ETH_DMATXDESC_TTSE) || \
mbed_official 532:fe11edbda85c 229 ((FLAG) == ETH_DMATXDESC_TER) || \
mbed_official 532:fe11edbda85c 230 ((FLAG) == ETH_DMATXDESC_TCH) || \
mbed_official 532:fe11edbda85c 231 ((FLAG) == ETH_DMATXDESC_TTSS) || \
mbed_official 532:fe11edbda85c 232 ((FLAG) == ETH_DMATXDESC_IHE) || \
mbed_official 532:fe11edbda85c 233 ((FLAG) == ETH_DMATXDESC_ES) || \
mbed_official 532:fe11edbda85c 234 ((FLAG) == ETH_DMATXDESC_JT) || \
mbed_official 532:fe11edbda85c 235 ((FLAG) == ETH_DMATXDESC_FF) || \
mbed_official 532:fe11edbda85c 236 ((FLAG) == ETH_DMATXDESC_PCE) || \
mbed_official 532:fe11edbda85c 237 ((FLAG) == ETH_DMATXDESC_LCA) || \
mbed_official 532:fe11edbda85c 238 ((FLAG) == ETH_DMATXDESC_NC) || \
mbed_official 532:fe11edbda85c 239 ((FLAG) == ETH_DMATXDESC_LCO) || \
mbed_official 532:fe11edbda85c 240 ((FLAG) == ETH_DMATXDESC_EC) || \
mbed_official 532:fe11edbda85c 241 ((FLAG) == ETH_DMATXDESC_VF) || \
mbed_official 532:fe11edbda85c 242 ((FLAG) == ETH_DMATXDESC_CC) || \
mbed_official 532:fe11edbda85c 243 ((FLAG) == ETH_DMATXDESC_ED) || \
mbed_official 532:fe11edbda85c 244 ((FLAG) == ETH_DMATXDESC_UF) || \
mbed_official 532:fe11edbda85c 245 ((FLAG) == ETH_DMATXDESC_DB))
mbed_official 532:fe11edbda85c 246 #define IS_ETH_DMA_TXDESC_SEGMENT(SEGMENT) (((SEGMENT) == ETH_DMATXDESC_LASTSEGMENTS) || \
mbed_official 532:fe11edbda85c 247 ((SEGMENT) == ETH_DMATXDESC_FIRSTSEGMENT))
mbed_official 532:fe11edbda85c 248 #define IS_ETH_DMA_TXDESC_CHECKSUM(CHECKSUM) (((CHECKSUM) == ETH_DMATXDESC_CHECKSUMBYPASS) || \
mbed_official 532:fe11edbda85c 249 ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMIPV4HEADER) || \
mbed_official 532:fe11edbda85c 250 ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT) || \
mbed_official 532:fe11edbda85c 251 ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL))
mbed_official 532:fe11edbda85c 252 #define IS_ETH_DMATXDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFF)
mbed_official 532:fe11edbda85c 253 #define IS_ETH_DMARXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMARXDESC_OWN) || \
mbed_official 532:fe11edbda85c 254 ((FLAG) == ETH_DMARXDESC_AFM) || \
mbed_official 532:fe11edbda85c 255 ((FLAG) == ETH_DMARXDESC_ES) || \
mbed_official 532:fe11edbda85c 256 ((FLAG) == ETH_DMARXDESC_DE) || \
mbed_official 532:fe11edbda85c 257 ((FLAG) == ETH_DMARXDESC_SAF) || \
mbed_official 532:fe11edbda85c 258 ((FLAG) == ETH_DMARXDESC_LE) || \
mbed_official 532:fe11edbda85c 259 ((FLAG) == ETH_DMARXDESC_OE) || \
mbed_official 532:fe11edbda85c 260 ((FLAG) == ETH_DMARXDESC_VLAN) || \
mbed_official 532:fe11edbda85c 261 ((FLAG) == ETH_DMARXDESC_FS) || \
mbed_official 532:fe11edbda85c 262 ((FLAG) == ETH_DMARXDESC_LS) || \
mbed_official 532:fe11edbda85c 263 ((FLAG) == ETH_DMARXDESC_IPV4HCE) || \
mbed_official 532:fe11edbda85c 264 ((FLAG) == ETH_DMARXDESC_LC) || \
mbed_official 532:fe11edbda85c 265 ((FLAG) == ETH_DMARXDESC_FT) || \
mbed_official 532:fe11edbda85c 266 ((FLAG) == ETH_DMARXDESC_RWT) || \
mbed_official 532:fe11edbda85c 267 ((FLAG) == ETH_DMARXDESC_RE) || \
mbed_official 532:fe11edbda85c 268 ((FLAG) == ETH_DMARXDESC_DBE) || \
mbed_official 532:fe11edbda85c 269 ((FLAG) == ETH_DMARXDESC_CE) || \
mbed_official 532:fe11edbda85c 270 ((FLAG) == ETH_DMARXDESC_MAMPCE))
mbed_official 532:fe11edbda85c 271 #define IS_ETH_DMA_RXDESC_BUFFER(BUFFER) (((BUFFER) == ETH_DMARXDESC_BUFFER1) || \
mbed_official 532:fe11edbda85c 272 ((BUFFER) == ETH_DMARXDESC_BUFFER2))
mbed_official 532:fe11edbda85c 273 #define IS_ETH_PMT_GET_FLAG(FLAG) (((FLAG) == ETH_PMT_FLAG_WUFR) || \
mbed_official 532:fe11edbda85c 274 ((FLAG) == ETH_PMT_FLAG_MPR))
mbed_official 532:fe11edbda85c 275 #define IS_ETH_DMA_FLAG(FLAG) ((((FLAG) & (uint32_t)0xC7FE1800) == 0x00) && ((FLAG) != 0x00))
mbed_official 532:fe11edbda85c 276 #define IS_ETH_DMA_GET_FLAG(FLAG) (((FLAG) == ETH_DMA_FLAG_TST) || ((FLAG) == ETH_DMA_FLAG_PMT) || \
mbed_official 532:fe11edbda85c 277 ((FLAG) == ETH_DMA_FLAG_MMC) || ((FLAG) == ETH_DMA_FLAG_DATATRANSFERERROR) || \
mbed_official 532:fe11edbda85c 278 ((FLAG) == ETH_DMA_FLAG_READWRITEERROR) || ((FLAG) == ETH_DMA_FLAG_ACCESSERROR) || \
mbed_official 532:fe11edbda85c 279 ((FLAG) == ETH_DMA_FLAG_NIS) || ((FLAG) == ETH_DMA_FLAG_AIS) || \
mbed_official 532:fe11edbda85c 280 ((FLAG) == ETH_DMA_FLAG_ER) || ((FLAG) == ETH_DMA_FLAG_FBE) || \
mbed_official 532:fe11edbda85c 281 ((FLAG) == ETH_DMA_FLAG_ET) || ((FLAG) == ETH_DMA_FLAG_RWT) || \
mbed_official 532:fe11edbda85c 282 ((FLAG) == ETH_DMA_FLAG_RPS) || ((FLAG) == ETH_DMA_FLAG_RBU) || \
mbed_official 532:fe11edbda85c 283 ((FLAG) == ETH_DMA_FLAG_R) || ((FLAG) == ETH_DMA_FLAG_TU) || \
mbed_official 532:fe11edbda85c 284 ((FLAG) == ETH_DMA_FLAG_RO) || ((FLAG) == ETH_DMA_FLAG_TJT) || \
mbed_official 532:fe11edbda85c 285 ((FLAG) == ETH_DMA_FLAG_TBU) || ((FLAG) == ETH_DMA_FLAG_TPS) || \
mbed_official 532:fe11edbda85c 286 ((FLAG) == ETH_DMA_FLAG_T))
mbed_official 532:fe11edbda85c 287 #define IS_ETH_MAC_IT(IT) ((((IT) & (uint32_t)0xFFFFFDF1) == 0x00) && ((IT) != 0x00))
mbed_official 532:fe11edbda85c 288 #define IS_ETH_MAC_GET_IT(IT) (((IT) == ETH_MAC_IT_TST) || ((IT) == ETH_MAC_IT_MMCT) || \
mbed_official 532:fe11edbda85c 289 ((IT) == ETH_MAC_IT_MMCR) || ((IT) == ETH_MAC_IT_MMC) || \
mbed_official 532:fe11edbda85c 290 ((IT) == ETH_MAC_IT_PMT))
mbed_official 532:fe11edbda85c 291 #define IS_ETH_MAC_GET_FLAG(FLAG) (((FLAG) == ETH_MAC_FLAG_TST) || ((FLAG) == ETH_MAC_FLAG_MMCT) || \
mbed_official 532:fe11edbda85c 292 ((FLAG) == ETH_MAC_FLAG_MMCR) || ((FLAG) == ETH_MAC_FLAG_MMC) || \
mbed_official 532:fe11edbda85c 293 ((FLAG) == ETH_MAC_FLAG_PMT))
mbed_official 532:fe11edbda85c 294 #define IS_ETH_DMA_IT(IT) ((((IT) & (uint32_t)0xC7FE1800) == 0x00) && ((IT) != 0x00))
mbed_official 532:fe11edbda85c 295 #define IS_ETH_DMA_GET_IT(IT) (((IT) == ETH_DMA_IT_TST) || ((IT) == ETH_DMA_IT_PMT) || \
mbed_official 532:fe11edbda85c 296 ((IT) == ETH_DMA_IT_MMC) || ((IT) == ETH_DMA_IT_NIS) || \
mbed_official 532:fe11edbda85c 297 ((IT) == ETH_DMA_IT_AIS) || ((IT) == ETH_DMA_IT_ER) || \
mbed_official 532:fe11edbda85c 298 ((IT) == ETH_DMA_IT_FBE) || ((IT) == ETH_DMA_IT_ET) || \
mbed_official 532:fe11edbda85c 299 ((IT) == ETH_DMA_IT_RWT) || ((IT) == ETH_DMA_IT_RPS) || \
mbed_official 532:fe11edbda85c 300 ((IT) == ETH_DMA_IT_RBU) || ((IT) == ETH_DMA_IT_R) || \
mbed_official 532:fe11edbda85c 301 ((IT) == ETH_DMA_IT_TU) || ((IT) == ETH_DMA_IT_RO) || \
mbed_official 532:fe11edbda85c 302 ((IT) == ETH_DMA_IT_TJT) || ((IT) == ETH_DMA_IT_TBU) || \
mbed_official 532:fe11edbda85c 303 ((IT) == ETH_DMA_IT_TPS) || ((IT) == ETH_DMA_IT_T))
mbed_official 532:fe11edbda85c 304 #define IS_ETH_DMA_GET_OVERFLOW(OVERFLOW) (((OVERFLOW) == ETH_DMA_OVERFLOW_RXFIFOCOUNTER) || \
mbed_official 532:fe11edbda85c 305 ((OVERFLOW) == ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER))
mbed_official 532:fe11edbda85c 306 #define IS_ETH_MMC_IT(IT) (((((IT) & (uint32_t)0xFFDF3FFF) == 0x00) || (((IT) & (uint32_t)0xEFFDFF9F) == 0x00)) && \
mbed_official 532:fe11edbda85c 307 ((IT) != 0x00))
mbed_official 532:fe11edbda85c 308 #define IS_ETH_MMC_GET_IT(IT) (((IT) == ETH_MMC_IT_TGF) || ((IT) == ETH_MMC_IT_TGFMSC) || \
mbed_official 532:fe11edbda85c 309 ((IT) == ETH_MMC_IT_TGFSC) || ((IT) == ETH_MMC_IT_RGUF) || \
mbed_official 532:fe11edbda85c 310 ((IT) == ETH_MMC_IT_RFAE) || ((IT) == ETH_MMC_IT_RFCE))
mbed_official 532:fe11edbda85c 311 #define IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(CMD) (((CMD) == ETH_DMAENHANCEDDESCRIPTOR_ENABLE) || \
mbed_official 532:fe11edbda85c 312 ((CMD) == ETH_DMAENHANCEDDESCRIPTOR_DISABLE))
mbed_official 532:fe11edbda85c 313
mbed_official 532:fe11edbda85c 314
mbed_official 532:fe11edbda85c 315 /**
mbed_official 532:fe11edbda85c 316 * @}
mbed_official 532:fe11edbda85c 317 */
mbed_official 532:fe11edbda85c 318
mbed_official 532:fe11edbda85c 319 /** @addtogroup ETH_Private_Defines
mbed_official 532:fe11edbda85c 320 * @{
mbed_official 532:fe11edbda85c 321 */
mbed_official 532:fe11edbda85c 322 /* Delay to wait when writing to some Ethernet registers */
mbed_official 532:fe11edbda85c 323 #define ETH_REG_WRITE_DELAY ((uint32_t)0x00000001)
mbed_official 532:fe11edbda85c 324
mbed_official 532:fe11edbda85c 325 /* ETHERNET Errors */
mbed_official 532:fe11edbda85c 326 #define ETH_SUCCESS ((uint32_t)0)
mbed_official 532:fe11edbda85c 327 #define ETH_ERROR ((uint32_t)1)
mbed_official 532:fe11edbda85c 328
mbed_official 532:fe11edbda85c 329 /* ETHERNET DMA Tx descriptors Collision Count Shift */
mbed_official 532:fe11edbda85c 330 #define ETH_DMATXDESC_COLLISION_COUNTSHIFT ((uint32_t)3)
mbed_official 532:fe11edbda85c 331
mbed_official 532:fe11edbda85c 332 /* ETHERNET DMA Tx descriptors Buffer2 Size Shift */
mbed_official 532:fe11edbda85c 333 #define ETH_DMATXDESC_BUFFER2_SIZESHIFT ((uint32_t)16)
mbed_official 532:fe11edbda85c 334
mbed_official 532:fe11edbda85c 335 /* ETHERNET DMA Rx descriptors Frame Length Shift */
mbed_official 532:fe11edbda85c 336 #define ETH_DMARXDESC_FRAME_LENGTHSHIFT ((uint32_t)16)
mbed_official 532:fe11edbda85c 337
mbed_official 532:fe11edbda85c 338 /* ETHERNET DMA Rx descriptors Buffer2 Size Shift */
mbed_official 532:fe11edbda85c 339 #define ETH_DMARXDESC_BUFFER2_SIZESHIFT ((uint32_t)16)
mbed_official 532:fe11edbda85c 340
mbed_official 532:fe11edbda85c 341 /* ETHERNET DMA Rx descriptors Frame length Shift */
mbed_official 532:fe11edbda85c 342 #define ETH_DMARXDESC_FRAMELENGTHSHIFT ((uint32_t)16)
mbed_official 532:fe11edbda85c 343
mbed_official 532:fe11edbda85c 344 /* ETHERNET MAC address offsets */
mbed_official 532:fe11edbda85c 345 #define ETH_MAC_ADDR_HBASE (uint32_t)(ETH_MAC_BASE + (uint32_t)0x40) /* ETHERNET MAC address high offset */
mbed_official 532:fe11edbda85c 346 #define ETH_MAC_ADDR_LBASE (uint32_t)(ETH_MAC_BASE + (uint32_t)0x44) /* ETHERNET MAC address low offset */
mbed_official 532:fe11edbda85c 347
mbed_official 532:fe11edbda85c 348 /* ETHERNET MACMIIAR register Mask */
mbed_official 532:fe11edbda85c 349 #define ETH_MACMIIAR_CR_MASK ((uint32_t)0xFFFFFFE3)
mbed_official 532:fe11edbda85c 350
mbed_official 532:fe11edbda85c 351 /* ETHERNET MACCR register Mask */
mbed_official 532:fe11edbda85c 352 #define ETH_MACCR_CLEAR_MASK ((uint32_t)0xFF20810F)
mbed_official 532:fe11edbda85c 353
mbed_official 532:fe11edbda85c 354 /* ETHERNET MACFCR register Mask */
mbed_official 532:fe11edbda85c 355 #define ETH_MACFCR_CLEAR_MASK ((uint32_t)0x0000FF41)
mbed_official 532:fe11edbda85c 356
mbed_official 532:fe11edbda85c 357 /* ETHERNET DMAOMR register Mask */
mbed_official 532:fe11edbda85c 358 #define ETH_DMAOMR_CLEAR_MASK ((uint32_t)0xF8DE3F23)
mbed_official 532:fe11edbda85c 359
mbed_official 532:fe11edbda85c 360 /* ETHERNET Remote Wake-up frame register length */
mbed_official 532:fe11edbda85c 361 #define ETH_WAKEUP_REGISTER_LENGTH 8
mbed_official 532:fe11edbda85c 362
mbed_official 532:fe11edbda85c 363 /* ETHERNET Missed frames counter Shift */
mbed_official 532:fe11edbda85c 364 #define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT 17
mbed_official 532:fe11edbda85c 365 /**
mbed_official 532:fe11edbda85c 366 * @}
mbed_official 532:fe11edbda85c 367 */
mbed_official 87:085cde657901 368
mbed_official 87:085cde657901 369 /* Exported types ------------------------------------------------------------*/
mbed_official 532:fe11edbda85c 370 /** @defgroup ETH_Exported_Types ETH Exported Types
mbed_official 532:fe11edbda85c 371 * @{
mbed_official 532:fe11edbda85c 372 */
mbed_official 87:085cde657901 373
mbed_official 87:085cde657901 374 /**
mbed_official 87:085cde657901 375 * @brief HAL State structures definition
mbed_official 87:085cde657901 376 */
mbed_official 87:085cde657901 377 typedef enum
mbed_official 87:085cde657901 378 {
mbed_official 87:085cde657901 379 HAL_ETH_STATE_RESET = 0x00, /*!< Peripheral not yet Initialized or disabled */
mbed_official 87:085cde657901 380 HAL_ETH_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
mbed_official 87:085cde657901 381 HAL_ETH_STATE_BUSY = 0x02, /*!< an internal process is ongoing */
mbed_official 87:085cde657901 382 HAL_ETH_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */
mbed_official 87:085cde657901 383 HAL_ETH_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */
mbed_official 87:085cde657901 384 HAL_ETH_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */
mbed_official 87:085cde657901 385 HAL_ETH_STATE_BUSY_WR = 0x42, /*!< Write process is ongoing */
mbed_official 87:085cde657901 386 HAL_ETH_STATE_BUSY_RD = 0x82, /*!< Read process is ongoing */
mbed_official 87:085cde657901 387 HAL_ETH_STATE_TIMEOUT = 0x03, /*!< Timeout state */
mbed_official 87:085cde657901 388 HAL_ETH_STATE_ERROR = 0x04 /*!< Reception process is ongoing */
mbed_official 87:085cde657901 389 }HAL_ETH_StateTypeDef;
mbed_official 87:085cde657901 390
mbed_official 87:085cde657901 391 /**
mbed_official 87:085cde657901 392 * @brief ETH Init Structure definition
mbed_official 87:085cde657901 393 */
mbed_official 87:085cde657901 394
mbed_official 87:085cde657901 395 typedef struct
mbed_official 87:085cde657901 396 {
mbed_official 87:085cde657901 397 uint32_t AutoNegotiation; /*!< Selects or not the AutoNegotiation mode for the external PHY
mbed_official 87:085cde657901 398 The AutoNegotiation allows an automatic setting of the Speed (10/100Mbps)
mbed_official 87:085cde657901 399 and the mode (half/full-duplex).
mbed_official 87:085cde657901 400 This parameter can be a value of @ref ETH_AutoNegotiation */
mbed_official 87:085cde657901 401
mbed_official 226:b062af740e40 402 uint32_t Speed; /*!< Sets the Ethernet speed: 10/100 Mbps.
mbed_official 87:085cde657901 403 This parameter can be a value of @ref ETH_Speed */
mbed_official 87:085cde657901 404
mbed_official 87:085cde657901 405 uint32_t DuplexMode; /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode
mbed_official 87:085cde657901 406 This parameter can be a value of @ref ETH_Duplex_Mode */
mbed_official 87:085cde657901 407
mbed_official 226:b062af740e40 408 uint16_t PhyAddress; /*!< Ethernet PHY address.
mbed_official 87:085cde657901 409 This parameter must be a number between Min_Data = 0 and Max_Data = 32 */
mbed_official 87:085cde657901 410
mbed_official 87:085cde657901 411 uint8_t *MACAddr; /*!< MAC Address of used Hardware: must be pointer on an array of 6 bytes */
mbed_official 87:085cde657901 412
mbed_official 226:b062af740e40 413 uint32_t RxMode; /*!< Selects the Ethernet Rx mode: Polling mode, Interrupt mode.
mbed_official 87:085cde657901 414 This parameter can be a value of @ref ETH_Rx_Mode */
mbed_official 87:085cde657901 415
mbed_official 226:b062af740e40 416 uint32_t ChecksumMode; /*!< Selects if the checksum is check by hardware or by software.
mbed_official 87:085cde657901 417 This parameter can be a value of @ref ETH_Checksum_Mode */
mbed_official 87:085cde657901 418
mbed_official 226:b062af740e40 419 uint32_t MediaInterface ; /*!< Selects the media-independent interface or the reduced media-independent interface.
mbed_official 87:085cde657901 420 This parameter can be a value of @ref ETH_Media_Interface */
mbed_official 87:085cde657901 421
mbed_official 87:085cde657901 422 } ETH_InitTypeDef;
mbed_official 87:085cde657901 423
mbed_official 87:085cde657901 424
mbed_official 87:085cde657901 425 /**
mbed_official 87:085cde657901 426 * @brief ETH MAC Configuration Structure definition
mbed_official 87:085cde657901 427 */
mbed_official 87:085cde657901 428
mbed_official 87:085cde657901 429 typedef struct
mbed_official 87:085cde657901 430 {
mbed_official 87:085cde657901 431 uint32_t Watchdog; /*!< Selects or not the Watchdog timer
mbed_official 87:085cde657901 432 When enabled, the MAC allows no more then 2048 bytes to be received.
mbed_official 87:085cde657901 433 When disabled, the MAC can receive up to 16384 bytes.
mbed_official 532:fe11edbda85c 434 This parameter can be a value of @ref ETH_Watchdog */
mbed_official 87:085cde657901 435
mbed_official 87:085cde657901 436 uint32_t Jabber; /*!< Selects or not Jabber timer
mbed_official 87:085cde657901 437 When enabled, the MAC allows no more then 2048 bytes to be sent.
mbed_official 87:085cde657901 438 When disabled, the MAC can send up to 16384 bytes.
mbed_official 87:085cde657901 439 This parameter can be a value of @ref ETH_Jabber */
mbed_official 87:085cde657901 440
mbed_official 226:b062af740e40 441 uint32_t InterFrameGap; /*!< Selects the minimum IFG between frames during transmission.
mbed_official 87:085cde657901 442 This parameter can be a value of @ref ETH_Inter_Frame_Gap */
mbed_official 87:085cde657901 443
mbed_official 226:b062af740e40 444 uint32_t CarrierSense; /*!< Selects or not the Carrier Sense.
mbed_official 87:085cde657901 445 This parameter can be a value of @ref ETH_Carrier_Sense */
mbed_official 87:085cde657901 446
mbed_official 226:b062af740e40 447 uint32_t ReceiveOwn; /*!< Selects or not the ReceiveOwn,
mbed_official 87:085cde657901 448 ReceiveOwn allows the reception of frames when the TX_EN signal is asserted
mbed_official 226:b062af740e40 449 in Half-Duplex mode.
mbed_official 87:085cde657901 450 This parameter can be a value of @ref ETH_Receive_Own */
mbed_official 87:085cde657901 451
mbed_official 226:b062af740e40 452 uint32_t LoopbackMode; /*!< Selects or not the internal MAC MII Loopback mode.
mbed_official 87:085cde657901 453 This parameter can be a value of @ref ETH_Loop_Back_Mode */
mbed_official 87:085cde657901 454
mbed_official 87:085cde657901 455 uint32_t ChecksumOffload; /*!< Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers.
mbed_official 87:085cde657901 456 This parameter can be a value of @ref ETH_Checksum_Offload */
mbed_official 87:085cde657901 457
mbed_official 87:085cde657901 458 uint32_t RetryTransmission; /*!< Selects or not the MAC attempt retries transmission, based on the settings of BL,
mbed_official 226:b062af740e40 459 when a collision occurs (Half-Duplex mode).
mbed_official 87:085cde657901 460 This parameter can be a value of @ref ETH_Retry_Transmission */
mbed_official 87:085cde657901 461
mbed_official 226:b062af740e40 462 uint32_t AutomaticPadCRCStrip; /*!< Selects or not the Automatic MAC Pad/CRC Stripping.
mbed_official 87:085cde657901 463 This parameter can be a value of @ref ETH_Automatic_Pad_CRC_Strip */
mbed_official 87:085cde657901 464
mbed_official 226:b062af740e40 465 uint32_t BackOffLimit; /*!< Selects the BackOff limit value.
mbed_official 87:085cde657901 466 This parameter can be a value of @ref ETH_Back_Off_Limit */
mbed_official 87:085cde657901 467
mbed_official 226:b062af740e40 468 uint32_t DeferralCheck; /*!< Selects or not the deferral check function (Half-Duplex mode).
mbed_official 87:085cde657901 469 This parameter can be a value of @ref ETH_Deferral_Check */
mbed_official 87:085cde657901 470
mbed_official 226:b062af740e40 471 uint32_t ReceiveAll; /*!< Selects or not all frames reception by the MAC (No filtering).
mbed_official 87:085cde657901 472 This parameter can be a value of @ref ETH_Receive_All */
mbed_official 87:085cde657901 473
mbed_official 226:b062af740e40 474 uint32_t SourceAddrFilter; /*!< Selects the Source Address Filter mode.
mbed_official 87:085cde657901 475 This parameter can be a value of @ref ETH_Source_Addr_Filter */
mbed_official 87:085cde657901 476
mbed_official 87:085cde657901 477 uint32_t PassControlFrames; /*!< Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames)
mbed_official 87:085cde657901 478 This parameter can be a value of @ref ETH_Pass_Control_Frames */
mbed_official 87:085cde657901 479
mbed_official 226:b062af740e40 480 uint32_t BroadcastFramesReception; /*!< Selects or not the reception of Broadcast Frames.
mbed_official 87:085cde657901 481 This parameter can be a value of @ref ETH_Broadcast_Frames_Reception */
mbed_official 87:085cde657901 482
mbed_official 226:b062af740e40 483 uint32_t DestinationAddrFilter; /*!< Sets the destination filter mode for both unicast and multicast frames.
mbed_official 87:085cde657901 484 This parameter can be a value of @ref ETH_Destination_Addr_Filter */
mbed_official 87:085cde657901 485
mbed_official 87:085cde657901 486 uint32_t PromiscuousMode; /*!< Selects or not the Promiscuous Mode
mbed_official 87:085cde657901 487 This parameter can be a value of @ref ETH_Promiscuous_Mode */
mbed_official 87:085cde657901 488
mbed_official 226:b062af740e40 489 uint32_t MulticastFramesFilter; /*!< Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter.
mbed_official 87:085cde657901 490 This parameter can be a value of @ref ETH_Multicast_Frames_Filter */
mbed_official 87:085cde657901 491
mbed_official 226:b062af740e40 492 uint32_t UnicastFramesFilter; /*!< Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter.
mbed_official 87:085cde657901 493 This parameter can be a value of @ref ETH_Unicast_Frames_Filter */
mbed_official 87:085cde657901 494
mbed_official 226:b062af740e40 495 uint32_t HashTableHigh; /*!< This field holds the higher 32 bits of Hash table.
mbed_official 87:085cde657901 496 This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */
mbed_official 87:085cde657901 497
mbed_official 226:b062af740e40 498 uint32_t HashTableLow; /*!< This field holds the lower 32 bits of Hash table.
mbed_official 87:085cde657901 499 This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */
mbed_official 87:085cde657901 500
mbed_official 226:b062af740e40 501 uint32_t PauseTime; /*!< This field holds the value to be used in the Pause Time field in the transmit control frame.
mbed_official 87:085cde657901 502 This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFF */
mbed_official 87:085cde657901 503
mbed_official 226:b062af740e40 504 uint32_t ZeroQuantaPause; /*!< Selects or not the automatic generation of Zero-Quanta Pause Control frames.
mbed_official 87:085cde657901 505 This parameter can be a value of @ref ETH_Zero_Quanta_Pause */
mbed_official 87:085cde657901 506
mbed_official 87:085cde657901 507 uint32_t PauseLowThreshold; /*!< This field configures the threshold of the PAUSE to be checked for
mbed_official 226:b062af740e40 508 automatic retransmission of PAUSE Frame.
mbed_official 87:085cde657901 509 This parameter can be a value of @ref ETH_Pause_Low_Threshold */
mbed_official 87:085cde657901 510
mbed_official 87:085cde657901 511 uint32_t UnicastPauseFrameDetect; /*!< Selects or not the MAC detection of the Pause frames (with MAC Address0
mbed_official 226:b062af740e40 512 unicast address and unique multicast address).
mbed_official 87:085cde657901 513 This parameter can be a value of @ref ETH_Unicast_Pause_Frame_Detect */
mbed_official 87:085cde657901 514
mbed_official 87:085cde657901 515 uint32_t ReceiveFlowControl; /*!< Enables or disables the MAC to decode the received Pause frame and
mbed_official 87:085cde657901 516 disable its transmitter for a specified time (Pause Time)
mbed_official 87:085cde657901 517 This parameter can be a value of @ref ETH_Receive_Flow_Control */
mbed_official 87:085cde657901 518
mbed_official 87:085cde657901 519 uint32_t TransmitFlowControl; /*!< Enables or disables the MAC to transmit Pause frames (Full-Duplex mode)
mbed_official 87:085cde657901 520 or the MAC back-pressure operation (Half-Duplex mode)
mbed_official 87:085cde657901 521 This parameter can be a value of @ref ETH_Transmit_Flow_Control */
mbed_official 87:085cde657901 522
mbed_official 87:085cde657901 523 uint32_t VLANTagComparison; /*!< Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for
mbed_official 226:b062af740e40 524 comparison and filtering.
mbed_official 87:085cde657901 525 This parameter can be a value of @ref ETH_VLAN_Tag_Comparison */
mbed_official 87:085cde657901 526
mbed_official 87:085cde657901 527 uint32_t VLANTagIdentifier; /*!< Holds the VLAN tag identifier for receive frames */
mbed_official 87:085cde657901 528
mbed_official 87:085cde657901 529 } ETH_MACInitTypeDef;
mbed_official 87:085cde657901 530
mbed_official 87:085cde657901 531
mbed_official 87:085cde657901 532 /**
mbed_official 87:085cde657901 533 * @brief ETH DMA Configuration Structure definition
mbed_official 87:085cde657901 534 */
mbed_official 87:085cde657901 535
mbed_official 87:085cde657901 536 typedef struct
mbed_official 87:085cde657901 537 {
mbed_official 226:b062af740e40 538 uint32_t DropTCPIPChecksumErrorFrame; /*!< Selects or not the Dropping of TCP/IP Checksum Error Frames.
mbed_official 87:085cde657901 539 This parameter can be a value of @ref ETH_Drop_TCP_IP_Checksum_Error_Frame */
mbed_official 87:085cde657901 540
mbed_official 226:b062af740e40 541 uint32_t ReceiveStoreForward; /*!< Enables or disables the Receive store and forward mode.
mbed_official 87:085cde657901 542 This parameter can be a value of @ref ETH_Receive_Store_Forward */
mbed_official 87:085cde657901 543
mbed_official 226:b062af740e40 544 uint32_t FlushReceivedFrame; /*!< Enables or disables the flushing of received frames.
mbed_official 87:085cde657901 545 This parameter can be a value of @ref ETH_Flush_Received_Frame */
mbed_official 87:085cde657901 546
mbed_official 226:b062af740e40 547 uint32_t TransmitStoreForward; /*!< Enables or disables Transmit store and forward mode.
mbed_official 87:085cde657901 548 This parameter can be a value of @ref ETH_Transmit_Store_Forward */
mbed_official 87:085cde657901 549
mbed_official 226:b062af740e40 550 uint32_t TransmitThresholdControl; /*!< Selects or not the Transmit Threshold Control.
mbed_official 87:085cde657901 551 This parameter can be a value of @ref ETH_Transmit_Threshold_Control */
mbed_official 87:085cde657901 552
mbed_official 226:b062af740e40 553 uint32_t ForwardErrorFrames; /*!< Selects or not the forward to the DMA of erroneous frames.
mbed_official 87:085cde657901 554 This parameter can be a value of @ref ETH_Forward_Error_Frames */
mbed_official 87:085cde657901 555
mbed_official 87:085cde657901 556 uint32_t ForwardUndersizedGoodFrames; /*!< Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error
mbed_official 87:085cde657901 557 and length less than 64 bytes) including pad-bytes and CRC)
mbed_official 87:085cde657901 558 This parameter can be a value of @ref ETH_Forward_Undersized_Good_Frames */
mbed_official 87:085cde657901 559
mbed_official 226:b062af740e40 560 uint32_t ReceiveThresholdControl; /*!< Selects the threshold level of the Receive FIFO.
mbed_official 87:085cde657901 561 This parameter can be a value of @ref ETH_Receive_Threshold_Control */
mbed_official 87:085cde657901 562
mbed_official 87:085cde657901 563 uint32_t SecondFrameOperate; /*!< Selects or not the Operate on second frame mode, which allows the DMA to process a second
mbed_official 87:085cde657901 564 frame of Transmit data even before obtaining the status for the first frame.
mbed_official 87:085cde657901 565 This parameter can be a value of @ref ETH_Second_Frame_Operate */
mbed_official 87:085cde657901 566
mbed_official 226:b062af740e40 567 uint32_t AddressAlignedBeats; /*!< Enables or disables the Address Aligned Beats.
mbed_official 87:085cde657901 568 This parameter can be a value of @ref ETH_Address_Aligned_Beats */
mbed_official 87:085cde657901 569
mbed_official 226:b062af740e40 570 uint32_t FixedBurst; /*!< Enables or disables the AHB Master interface fixed burst transfers.
mbed_official 87:085cde657901 571 This parameter can be a value of @ref ETH_Fixed_Burst */
mbed_official 87:085cde657901 572
mbed_official 226:b062af740e40 573 uint32_t RxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction.
mbed_official 87:085cde657901 574 This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */
mbed_official 87:085cde657901 575
mbed_official 226:b062af740e40 576 uint32_t TxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Tx DMA transaction.
mbed_official 87:085cde657901 577 This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */
mbed_official 87:085cde657901 578
mbed_official 226:b062af740e40 579 uint32_t EnhancedDescriptorFormat; /*!< Enables the enhanced descriptor format.
mbed_official 87:085cde657901 580 This parameter can be a value of @ref ETH_DMA_Enhanced_descriptor_format */
mbed_official 87:085cde657901 581
mbed_official 87:085cde657901 582 uint32_t DescriptorSkipLength; /*!< Specifies the number of word to skip between two unchained descriptors (Ring mode)
mbed_official 87:085cde657901 583 This parameter must be a number between Min_Data = 0 and Max_Data = 32 */
mbed_official 87:085cde657901 584
mbed_official 226:b062af740e40 585 uint32_t DMAArbitration; /*!< Selects the DMA Tx/Rx arbitration.
mbed_official 87:085cde657901 586 This parameter can be a value of @ref ETH_DMA_Arbitration */
mbed_official 87:085cde657901 587 } ETH_DMAInitTypeDef;
mbed_official 87:085cde657901 588
mbed_official 87:085cde657901 589
mbed_official 87:085cde657901 590 /**
mbed_official 87:085cde657901 591 * @brief ETH DMA Descriptors data structure definition
mbed_official 87:085cde657901 592 */
mbed_official 87:085cde657901 593
mbed_official 87:085cde657901 594 typedef struct
mbed_official 87:085cde657901 595 {
mbed_official 87:085cde657901 596 __IO uint32_t Status; /*!< Status */
mbed_official 87:085cde657901 597
mbed_official 87:085cde657901 598 uint32_t ControlBufferSize; /*!< Control and Buffer1, Buffer2 lengths */
mbed_official 87:085cde657901 599
mbed_official 87:085cde657901 600 uint32_t Buffer1Addr; /*!< Buffer1 address pointer */
mbed_official 87:085cde657901 601
mbed_official 87:085cde657901 602 uint32_t Buffer2NextDescAddr; /*!< Buffer2 or next descriptor address pointer */
mbed_official 87:085cde657901 603
mbed_official 87:085cde657901 604 /*!< Enhanced ETHERNET DMA PTP Descriptors */
mbed_official 87:085cde657901 605 uint32_t ExtendedStatus; /*!< Extended status for PTP receive descriptor */
mbed_official 87:085cde657901 606
mbed_official 87:085cde657901 607 uint32_t Reserved1; /*!< Reserved */
mbed_official 87:085cde657901 608
mbed_official 87:085cde657901 609 uint32_t TimeStampLow; /*!< Time Stamp Low value for transmit and receive */
mbed_official 87:085cde657901 610
mbed_official 87:085cde657901 611 uint32_t TimeStampHigh; /*!< Time Stamp High value for transmit and receive */
mbed_official 87:085cde657901 612
mbed_official 87:085cde657901 613 } ETH_DMADescTypeDef;
mbed_official 87:085cde657901 614
mbed_official 87:085cde657901 615
mbed_official 87:085cde657901 616 /**
mbed_official 87:085cde657901 617 * @brief Received Frame Informations structure definition
mbed_official 87:085cde657901 618 */
mbed_official 87:085cde657901 619 typedef struct
mbed_official 87:085cde657901 620 {
mbed_official 87:085cde657901 621 ETH_DMADescTypeDef *FSRxDesc; /*!< First Segment Rx Desc */
mbed_official 87:085cde657901 622
mbed_official 87:085cde657901 623 ETH_DMADescTypeDef *LSRxDesc; /*!< Last Segment Rx Desc */
mbed_official 87:085cde657901 624
mbed_official 87:085cde657901 625 uint32_t SegCount; /*!< Segment count */
mbed_official 87:085cde657901 626
mbed_official 87:085cde657901 627 uint32_t length; /*!< Frame length */
mbed_official 87:085cde657901 628
mbed_official 87:085cde657901 629 uint32_t buffer; /*!< Frame buffer */
mbed_official 87:085cde657901 630
mbed_official 87:085cde657901 631 } ETH_DMARxFrameInfos;
mbed_official 87:085cde657901 632
mbed_official 87:085cde657901 633
mbed_official 87:085cde657901 634 /**
mbed_official 87:085cde657901 635 * @brief ETH Handle Structure definition
mbed_official 87:085cde657901 636 */
mbed_official 87:085cde657901 637
mbed_official 87:085cde657901 638 typedef struct
mbed_official 87:085cde657901 639 {
mbed_official 87:085cde657901 640 ETH_TypeDef *Instance; /*!< Register base address */
mbed_official 87:085cde657901 641
mbed_official 87:085cde657901 642 ETH_InitTypeDef Init; /*!< Ethernet Init Configuration */
mbed_official 87:085cde657901 643
mbed_official 87:085cde657901 644 uint32_t LinkStatus; /*!< Ethernet link status */
mbed_official 87:085cde657901 645
mbed_official 87:085cde657901 646 ETH_DMADescTypeDef *RxDesc; /*!< Rx descriptor to Get */
mbed_official 87:085cde657901 647
mbed_official 87:085cde657901 648 ETH_DMADescTypeDef *TxDesc; /*!< Tx descriptor to Set */
mbed_official 87:085cde657901 649
mbed_official 87:085cde657901 650 ETH_DMARxFrameInfos RxFrameInfos; /*!< last Rx frame infos */
mbed_official 87:085cde657901 651
mbed_official 87:085cde657901 652 __IO HAL_ETH_StateTypeDef State; /*!< ETH communication state */
mbed_official 87:085cde657901 653
mbed_official 87:085cde657901 654 HAL_LockTypeDef Lock; /*!< ETH Lock */
mbed_official 87:085cde657901 655
mbed_official 87:085cde657901 656 } ETH_HandleTypeDef;
mbed_official 87:085cde657901 657
mbed_official 532:fe11edbda85c 658 /**
mbed_official 532:fe11edbda85c 659 * @}
mbed_official 532:fe11edbda85c 660 */
mbed_official 87:085cde657901 661
mbed_official 532:fe11edbda85c 662 /* Exported constants --------------------------------------------------------*/
mbed_official 532:fe11edbda85c 663 /** @defgroup ETH_Exported_Constants ETH Exported Constants
mbed_official 532:fe11edbda85c 664 * @{
mbed_official 532:fe11edbda85c 665 */
mbed_official 87:085cde657901 666
mbed_official 532:fe11edbda85c 667 /** @defgroup ETH_Buffers_setting ETH Buffers setting
mbed_official 87:085cde657901 668 * @{
mbed_official 87:085cde657901 669 */
mbed_official 532:fe11edbda85c 670 #define ETH_MAX_PACKET_SIZE ((uint32_t)1524) /*!< ETH_HEADER + ETH_EXTRA + ETH_VLAN_TAG + ETH_MAX_ETH_PAYLOAD + ETH_CRC */
mbed_official 87:085cde657901 671 #define ETH_HEADER ((uint32_t)14) /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */
mbed_official 87:085cde657901 672 #define ETH_CRC ((uint32_t)4) /*!< Ethernet CRC */
mbed_official 87:085cde657901 673 #define ETH_EXTRA ((uint32_t)2) /*!< Extra bytes in some cases */
mbed_official 532:fe11edbda85c 674 #define ETH_VLAN_TAG ((uint32_t)4) /*!< optional 802.1q VLAN Tag */
mbed_official 532:fe11edbda85c 675 #define ETH_MIN_ETH_PAYLOAD ((uint32_t)46) /*!< Minimum Ethernet payload size */
mbed_official 532:fe11edbda85c 676 #define ETH_MAX_ETH_PAYLOAD ((uint32_t)1500) /*!< Maximum Ethernet payload size */
mbed_official 532:fe11edbda85c 677 #define ETH_JUMBO_FRAME_PAYLOAD ((uint32_t)9000) /*!< Jumbo frame payload size */
mbed_official 87:085cde657901 678
mbed_official 87:085cde657901 679 /* Ethernet driver receive buffers are organized in a chained linked-list, when
mbed_official 87:085cde657901 680 an ethernet packet is received, the Rx-DMA will transfer the packet from RxFIFO
mbed_official 87:085cde657901 681 to the driver receive buffers memory.
mbed_official 87:085cde657901 682
mbed_official 87:085cde657901 683 Depending on the size of the received ethernet packet and the size of
mbed_official 87:085cde657901 684 each ethernet driver receive buffer, the received packet can take one or more
mbed_official 87:085cde657901 685 ethernet driver receive buffer.
mbed_official 87:085cde657901 686
mbed_official 87:085cde657901 687 In below are defined the size of one ethernet driver receive buffer ETH_RX_BUF_SIZE
mbed_official 87:085cde657901 688 and the total count of the driver receive buffers ETH_RXBUFNB.
mbed_official 87:085cde657901 689
mbed_official 87:085cde657901 690 The configured value for ETH_RX_BUF_SIZE and ETH_RXBUFNB are only provided as
mbed_official 87:085cde657901 691 example, they can be reconfigured in the application layer to fit the application
mbed_official 87:085cde657901 692 needs */
mbed_official 87:085cde657901 693
mbed_official 87:085cde657901 694 /* Here we configure each Ethernet driver receive buffer to fit the Max size Ethernet
mbed_official 87:085cde657901 695 packet */
mbed_official 87:085cde657901 696 #ifndef ETH_RX_BUF_SIZE
mbed_official 87:085cde657901 697 #define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE
mbed_official 87:085cde657901 698 #endif
mbed_official 87:085cde657901 699
mbed_official 87:085cde657901 700 /* 5 Ethernet driver receive buffers are used (in a chained linked list)*/
mbed_official 87:085cde657901 701 #ifndef ETH_RXBUFNB
mbed_official 87:085cde657901 702 #define ETH_RXBUFNB ((uint32_t)5 /* 5 Rx buffers of size ETH_RX_BUF_SIZE */
mbed_official 87:085cde657901 703 #endif
mbed_official 87:085cde657901 704
mbed_official 87:085cde657901 705
mbed_official 87:085cde657901 706 /* Ethernet driver transmit buffers are organized in a chained linked-list, when
mbed_official 87:085cde657901 707 an ethernet packet is transmitted, Tx-DMA will transfer the packet from the
mbed_official 87:085cde657901 708 driver transmit buffers memory to the TxFIFO.
mbed_official 87:085cde657901 709
mbed_official 87:085cde657901 710 Depending on the size of the Ethernet packet to be transmitted and the size of
mbed_official 87:085cde657901 711 each ethernet driver transmit buffer, the packet to be transmitted can take
mbed_official 87:085cde657901 712 one or more ethernet driver transmit buffer.
mbed_official 87:085cde657901 713
mbed_official 87:085cde657901 714 In below are defined the size of one ethernet driver transmit buffer ETH_TX_BUF_SIZE
mbed_official 87:085cde657901 715 and the total count of the driver transmit buffers ETH_TXBUFNB.
mbed_official 87:085cde657901 716
mbed_official 87:085cde657901 717 The configured value for ETH_TX_BUF_SIZE and ETH_TXBUFNB are only provided as
mbed_official 87:085cde657901 718 example, they can be reconfigured in the application layer to fit the application
mbed_official 87:085cde657901 719 needs */
mbed_official 87:085cde657901 720
mbed_official 87:085cde657901 721 /* Here we configure each Ethernet driver transmit buffer to fit the Max size Ethernet
mbed_official 87:085cde657901 722 packet */
mbed_official 87:085cde657901 723 #ifndef ETH_TX_BUF_SIZE
mbed_official 87:085cde657901 724 #define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE
mbed_official 87:085cde657901 725 #endif
mbed_official 87:085cde657901 726
mbed_official 87:085cde657901 727 /* 5 ethernet driver transmit buffers are used (in a chained linked list)*/
mbed_official 87:085cde657901 728 #ifndef ETH_TXBUFNB
mbed_official 87:085cde657901 729 #define ETH_TXBUFNB ((uint32_t)5 /* 5 Tx buffers of size ETH_TX_BUF_SIZE */
mbed_official 87:085cde657901 730 #endif
mbed_official 87:085cde657901 731
mbed_official 532:fe11edbda85c 732 /**
mbed_official 532:fe11edbda85c 733 * @}
mbed_official 532:fe11edbda85c 734 */
mbed_official 532:fe11edbda85c 735
mbed_official 532:fe11edbda85c 736 /** @defgroup ETH_DMA_TX_Descriptor ETH DMA TX Descriptor
mbed_official 532:fe11edbda85c 737 * @{
mbed_official 532:fe11edbda85c 738 */
mbed_official 87:085cde657901 739
mbed_official 87:085cde657901 740 /*
mbed_official 532:fe11edbda85c 741 DMA Tx Descriptor
mbed_official 87:085cde657901 742 -----------------------------------------------------------------------------------------------
mbed_official 87:085cde657901 743 TDES0 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] |
mbed_official 87:085cde657901 744 -----------------------------------------------------------------------------------------------
mbed_official 87:085cde657901 745 TDES1 | Reserved[31:29] | Buffer2 ByteCount[28:16] | Reserved[15:13] | Buffer1 ByteCount[12:0] |
mbed_official 87:085cde657901 746 -----------------------------------------------------------------------------------------------
mbed_official 87:085cde657901 747 TDES2 | Buffer1 Address [31:0] |
mbed_official 87:085cde657901 748 -----------------------------------------------------------------------------------------------
mbed_official 87:085cde657901 749 TDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] |
mbed_official 87:085cde657901 750 -----------------------------------------------------------------------------------------------
mbed_official 87:085cde657901 751 */
mbed_official 87:085cde657901 752
mbed_official 87:085cde657901 753 /**
mbed_official 87:085cde657901 754 * @brief Bit definition of TDES0 register: DMA Tx descriptor status register
mbed_official 87:085cde657901 755 */
mbed_official 87:085cde657901 756 #define ETH_DMATXDESC_OWN ((uint32_t)0x80000000) /*!< OWN bit: descriptor is owned by DMA engine */
mbed_official 87:085cde657901 757 #define ETH_DMATXDESC_IC ((uint32_t)0x40000000) /*!< Interrupt on Completion */
mbed_official 87:085cde657901 758 #define ETH_DMATXDESC_LS ((uint32_t)0x20000000) /*!< Last Segment */
mbed_official 87:085cde657901 759 #define ETH_DMATXDESC_FS ((uint32_t)0x10000000) /*!< First Segment */
mbed_official 87:085cde657901 760 #define ETH_DMATXDESC_DC ((uint32_t)0x08000000) /*!< Disable CRC */
mbed_official 87:085cde657901 761 #define ETH_DMATXDESC_DP ((uint32_t)0x04000000) /*!< Disable Padding */
mbed_official 87:085cde657901 762 #define ETH_DMATXDESC_TTSE ((uint32_t)0x02000000) /*!< Transmit Time Stamp Enable */
mbed_official 87:085cde657901 763 #define ETH_DMATXDESC_CIC ((uint32_t)0x00C00000) /*!< Checksum Insertion Control: 4 cases */
mbed_official 87:085cde657901 764 #define ETH_DMATXDESC_CIC_BYPASS ((uint32_t)0x00000000) /*!< Do Nothing: Checksum Engine is bypassed */
mbed_official 87:085cde657901 765 #define ETH_DMATXDESC_CIC_IPV4HEADER ((uint32_t)0x00400000) /*!< IPV4 header Checksum Insertion */
mbed_official 87:085cde657901 766 #define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT ((uint32_t)0x00800000) /*!< TCP/UDP/ICMP Checksum Insertion calculated over segment only */
mbed_official 87:085cde657901 767 #define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL ((uint32_t)0x00C00000) /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */
mbed_official 87:085cde657901 768 #define ETH_DMATXDESC_TER ((uint32_t)0x00200000) /*!< Transmit End of Ring */
mbed_official 87:085cde657901 769 #define ETH_DMATXDESC_TCH ((uint32_t)0x00100000) /*!< Second Address Chained */
mbed_official 87:085cde657901 770 #define ETH_DMATXDESC_TTSS ((uint32_t)0x00020000) /*!< Tx Time Stamp Status */
mbed_official 87:085cde657901 771 #define ETH_DMATXDESC_IHE ((uint32_t)0x00010000) /*!< IP Header Error */
mbed_official 87:085cde657901 772 #define ETH_DMATXDESC_ES ((uint32_t)0x00008000) /*!< Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT */
mbed_official 87:085cde657901 773 #define ETH_DMATXDESC_JT ((uint32_t)0x00004000) /*!< Jabber Timeout */
mbed_official 87:085cde657901 774 #define ETH_DMATXDESC_FF ((uint32_t)0x00002000) /*!< Frame Flushed: DMA/MTL flushed the frame due to SW flush */
mbed_official 87:085cde657901 775 #define ETH_DMATXDESC_PCE ((uint32_t)0x00001000) /*!< Payload Checksum Error */
mbed_official 87:085cde657901 776 #define ETH_DMATXDESC_LCA ((uint32_t)0x00000800) /*!< Loss of Carrier: carrier lost during transmission */
mbed_official 87:085cde657901 777 #define ETH_DMATXDESC_NC ((uint32_t)0x00000400) /*!< No Carrier: no carrier signal from the transceiver */
mbed_official 87:085cde657901 778 #define ETH_DMATXDESC_LCO ((uint32_t)0x00000200) /*!< Late Collision: transmission aborted due to collision */
mbed_official 87:085cde657901 779 #define ETH_DMATXDESC_EC ((uint32_t)0x00000100) /*!< Excessive Collision: transmission aborted after 16 collisions */
mbed_official 87:085cde657901 780 #define ETH_DMATXDESC_VF ((uint32_t)0x00000080) /*!< VLAN Frame */
mbed_official 87:085cde657901 781 #define ETH_DMATXDESC_CC ((uint32_t)0x00000078) /*!< Collision Count */
mbed_official 87:085cde657901 782 #define ETH_DMATXDESC_ED ((uint32_t)0x00000004) /*!< Excessive Deferral */
mbed_official 87:085cde657901 783 #define ETH_DMATXDESC_UF ((uint32_t)0x00000002) /*!< Underflow Error: late data arrival from the memory */
mbed_official 87:085cde657901 784 #define ETH_DMATXDESC_DB ((uint32_t)0x00000001) /*!< Deferred Bit */
mbed_official 87:085cde657901 785
mbed_official 87:085cde657901 786 /**
mbed_official 87:085cde657901 787 * @brief Bit definition of TDES1 register
mbed_official 87:085cde657901 788 */
mbed_official 87:085cde657901 789 #define ETH_DMATXDESC_TBS2 ((uint32_t)0x1FFF0000) /*!< Transmit Buffer2 Size */
mbed_official 87:085cde657901 790 #define ETH_DMATXDESC_TBS1 ((uint32_t)0x00001FFF) /*!< Transmit Buffer1 Size */
mbed_official 87:085cde657901 791
mbed_official 87:085cde657901 792 /**
mbed_official 87:085cde657901 793 * @brief Bit definition of TDES2 register
mbed_official 87:085cde657901 794 */
mbed_official 87:085cde657901 795 #define ETH_DMATXDESC_B1AP ((uint32_t)0xFFFFFFFF) /*!< Buffer1 Address Pointer */
mbed_official 87:085cde657901 796
mbed_official 87:085cde657901 797 /**
mbed_official 87:085cde657901 798 * @brief Bit definition of TDES3 register
mbed_official 87:085cde657901 799 */
mbed_official 87:085cde657901 800 #define ETH_DMATXDESC_B2AP ((uint32_t)0xFFFFFFFF) /*!< Buffer2 Address Pointer */
mbed_official 87:085cde657901 801
mbed_official 87:085cde657901 802 /*---------------------------------------------------------------------------------------------
mbed_official 87:085cde657901 803 TDES6 | Transmit Time Stamp Low [31:0] |
mbed_official 87:085cde657901 804 -----------------------------------------------------------------------------------------------
mbed_official 87:085cde657901 805 TDES7 | Transmit Time Stamp High [31:0] |
mbed_official 87:085cde657901 806 ----------------------------------------------------------------------------------------------*/
mbed_official 87:085cde657901 807
mbed_official 87:085cde657901 808 /* Bit definition of TDES6 register */
mbed_official 87:085cde657901 809 #define ETH_DMAPTPTXDESC_TTSL ((uint32_t)0xFFFFFFFF) /* Transmit Time Stamp Low */
mbed_official 87:085cde657901 810
mbed_official 87:085cde657901 811 /* Bit definition of TDES7 register */
mbed_official 87:085cde657901 812 #define ETH_DMAPTPTXDESC_TTSH ((uint32_t)0xFFFFFFFF) /* Transmit Time Stamp High */
mbed_official 87:085cde657901 813
mbed_official 87:085cde657901 814 /**
mbed_official 87:085cde657901 815 * @}
mbed_official 87:085cde657901 816 */
mbed_official 532:fe11edbda85c 817 /** @defgroup ETH_DMA_RX_Descriptor ETH DMA RX Descriptor
mbed_official 87:085cde657901 818 * @{
mbed_official 87:085cde657901 819 */
mbed_official 87:085cde657901 820
mbed_official 87:085cde657901 821 /*
mbed_official 87:085cde657901 822 DMA Rx Descriptor
mbed_official 87:085cde657901 823 --------------------------------------------------------------------------------------------------------------------
mbed_official 87:085cde657901 824 RDES0 | OWN(31) | Status [30:0] |
mbed_official 87:085cde657901 825 ---------------------------------------------------------------------------------------------------------------------
mbed_official 87:085cde657901 826 RDES1 | CTRL(31) | Reserved[30:29] | Buffer2 ByteCount[28:16] | CTRL[15:14] | Reserved(13) | Buffer1 ByteCount[12:0] |
mbed_official 87:085cde657901 827 ---------------------------------------------------------------------------------------------------------------------
mbed_official 87:085cde657901 828 RDES2 | Buffer1 Address [31:0] |
mbed_official 87:085cde657901 829 ---------------------------------------------------------------------------------------------------------------------
mbed_official 87:085cde657901 830 RDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] |
mbed_official 87:085cde657901 831 ---------------------------------------------------------------------------------------------------------------------
mbed_official 87:085cde657901 832 */
mbed_official 87:085cde657901 833
mbed_official 87:085cde657901 834 /**
mbed_official 87:085cde657901 835 * @brief Bit definition of RDES0 register: DMA Rx descriptor status register
mbed_official 87:085cde657901 836 */
mbed_official 87:085cde657901 837 #define ETH_DMARXDESC_OWN ((uint32_t)0x80000000) /*!< OWN bit: descriptor is owned by DMA engine */
mbed_official 87:085cde657901 838 #define ETH_DMARXDESC_AFM ((uint32_t)0x40000000) /*!< DA Filter Fail for the rx frame */
mbed_official 87:085cde657901 839 #define ETH_DMARXDESC_FL ((uint32_t)0x3FFF0000) /*!< Receive descriptor frame length */
mbed_official 87:085cde657901 840 #define ETH_DMARXDESC_ES ((uint32_t)0x00008000) /*!< Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */
mbed_official 87:085cde657901 841 #define ETH_DMARXDESC_DE ((uint32_t)0x00004000) /*!< Descriptor error: no more descriptors for receive frame */
mbed_official 87:085cde657901 842 #define ETH_DMARXDESC_SAF ((uint32_t)0x00002000) /*!< SA Filter Fail for the received frame */
mbed_official 87:085cde657901 843 #define ETH_DMARXDESC_LE ((uint32_t)0x00001000) /*!< Frame size not matching with length field */
mbed_official 87:085cde657901 844 #define ETH_DMARXDESC_OE ((uint32_t)0x00000800) /*!< Overflow Error: Frame was damaged due to buffer overflow */
mbed_official 87:085cde657901 845 #define ETH_DMARXDESC_VLAN ((uint32_t)0x00000400) /*!< VLAN Tag: received frame is a VLAN frame */
mbed_official 87:085cde657901 846 #define ETH_DMARXDESC_FS ((uint32_t)0x00000200) /*!< First descriptor of the frame */
mbed_official 87:085cde657901 847 #define ETH_DMARXDESC_LS ((uint32_t)0x00000100) /*!< Last descriptor of the frame */
mbed_official 87:085cde657901 848 #define ETH_DMARXDESC_IPV4HCE ((uint32_t)0x00000080) /*!< IPC Checksum Error: Rx Ipv4 header checksum error */
mbed_official 87:085cde657901 849 #define ETH_DMARXDESC_LC ((uint32_t)0x00000040) /*!< Late collision occurred during reception */
mbed_official 87:085cde657901 850 #define ETH_DMARXDESC_FT ((uint32_t)0x00000020) /*!< Frame type - Ethernet, otherwise 802.3 */
mbed_official 87:085cde657901 851 #define ETH_DMARXDESC_RWT ((uint32_t)0x00000010) /*!< Receive Watchdog Timeout: watchdog timer expired during reception */
mbed_official 87:085cde657901 852 #define ETH_DMARXDESC_RE ((uint32_t)0x00000008) /*!< Receive error: error reported by MII interface */
mbed_official 87:085cde657901 853 #define ETH_DMARXDESC_DBE ((uint32_t)0x00000004) /*!< Dribble bit error: frame contains non int multiple of 8 bits */
mbed_official 87:085cde657901 854 #define ETH_DMARXDESC_CE ((uint32_t)0x00000002) /*!< CRC error */
mbed_official 87:085cde657901 855 #define ETH_DMARXDESC_MAMPCE ((uint32_t)0x00000001) /*!< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */
mbed_official 87:085cde657901 856
mbed_official 87:085cde657901 857 /**
mbed_official 87:085cde657901 858 * @brief Bit definition of RDES1 register
mbed_official 87:085cde657901 859 */
mbed_official 87:085cde657901 860 #define ETH_DMARXDESC_DIC ((uint32_t)0x80000000) /*!< Disable Interrupt on Completion */
mbed_official 87:085cde657901 861 #define ETH_DMARXDESC_RBS2 ((uint32_t)0x1FFF0000) /*!< Receive Buffer2 Size */
mbed_official 87:085cde657901 862 #define ETH_DMARXDESC_RER ((uint32_t)0x00008000) /*!< Receive End of Ring */
mbed_official 87:085cde657901 863 #define ETH_DMARXDESC_RCH ((uint32_t)0x00004000) /*!< Second Address Chained */
mbed_official 87:085cde657901 864 #define ETH_DMARXDESC_RBS1 ((uint32_t)0x00001FFF) /*!< Receive Buffer1 Size */
mbed_official 87:085cde657901 865
mbed_official 87:085cde657901 866 /**
mbed_official 87:085cde657901 867 * @brief Bit definition of RDES2 register
mbed_official 87:085cde657901 868 */
mbed_official 87:085cde657901 869 #define ETH_DMARXDESC_B1AP ((uint32_t)0xFFFFFFFF) /*!< Buffer1 Address Pointer */
mbed_official 87:085cde657901 870
mbed_official 87:085cde657901 871 /**
mbed_official 87:085cde657901 872 * @brief Bit definition of RDES3 register
mbed_official 87:085cde657901 873 */
mbed_official 87:085cde657901 874 #define ETH_DMARXDESC_B2AP ((uint32_t)0xFFFFFFFF) /*!< Buffer2 Address Pointer */
mbed_official 87:085cde657901 875
mbed_official 87:085cde657901 876 /*---------------------------------------------------------------------------------------------------------------------
mbed_official 87:085cde657901 877 RDES4 | Reserved[31:15] | Extended Status [14:0] |
mbed_official 87:085cde657901 878 ---------------------------------------------------------------------------------------------------------------------
mbed_official 87:085cde657901 879 RDES5 | Reserved[31:0] |
mbed_official 87:085cde657901 880 ---------------------------------------------------------------------------------------------------------------------
mbed_official 87:085cde657901 881 RDES6 | Receive Time Stamp Low [31:0] |
mbed_official 87:085cde657901 882 ---------------------------------------------------------------------------------------------------------------------
mbed_official 87:085cde657901 883 RDES7 | Receive Time Stamp High [31:0] |
mbed_official 87:085cde657901 884 --------------------------------------------------------------------------------------------------------------------*/
mbed_official 87:085cde657901 885
mbed_official 87:085cde657901 886 /* Bit definition of RDES4 register */
mbed_official 87:085cde657901 887 #define ETH_DMAPTPRXDESC_PTPV ((uint32_t)0x00002000) /* PTP Version */
mbed_official 87:085cde657901 888 #define ETH_DMAPTPRXDESC_PTPFT ((uint32_t)0x00001000) /* PTP Frame Type */
mbed_official 87:085cde657901 889 #define ETH_DMAPTPRXDESC_PTPMT ((uint32_t)0x00000F00) /* PTP Message Type */
mbed_official 87:085cde657901 890 #define ETH_DMAPTPRXDESC_PTPMT_SYNC ((uint32_t)0x00000100) /* SYNC message (all clock types) */
mbed_official 87:085cde657901 891 #define ETH_DMAPTPRXDESC_PTPMT_FOLLOWUP ((uint32_t)0x00000200) /* FollowUp message (all clock types) */
mbed_official 87:085cde657901 892 #define ETH_DMAPTPRXDESC_PTPMT_DELAYREQ ((uint32_t)0x00000300) /* DelayReq message (all clock types) */
mbed_official 87:085cde657901 893 #define ETH_DMAPTPRXDESC_PTPMT_DELAYRESP ((uint32_t)0x00000400) /* DelayResp message (all clock types) */
mbed_official 87:085cde657901 894 #define ETH_DMAPTPRXDESC_PTPMT_PDELAYREQ_ANNOUNCE ((uint32_t)0x00000500) /* PdelayReq message (peer-to-peer transparent clock) or Announce message (Ordinary or Boundary clock) */
mbed_official 87:085cde657901 895 #define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESP_MANAG ((uint32_t)0x00000600) /* PdelayResp message (peer-to-peer transparent clock) or Management message (Ordinary or Boundary clock) */
mbed_official 87:085cde657901 896 #define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESPFOLLOWUP_SIGNAL ((uint32_t)0x00000700) /* PdelayRespFollowUp message (peer-to-peer transparent clock) or Signaling message (Ordinary or Boundary clock) */
mbed_official 87:085cde657901 897 #define ETH_DMAPTPRXDESC_IPV6PR ((uint32_t)0x00000080) /* IPv6 Packet Received */
mbed_official 87:085cde657901 898 #define ETH_DMAPTPRXDESC_IPV4PR ((uint32_t)0x00000040) /* IPv4 Packet Received */
mbed_official 87:085cde657901 899 #define ETH_DMAPTPRXDESC_IPCB ((uint32_t)0x00000020) /* IP Checksum Bypassed */
mbed_official 87:085cde657901 900 #define ETH_DMAPTPRXDESC_IPPE ((uint32_t)0x00000010) /* IP Payload Error */
mbed_official 87:085cde657901 901 #define ETH_DMAPTPRXDESC_IPHE ((uint32_t)0x00000008) /* IP Header Error */
mbed_official 87:085cde657901 902 #define ETH_DMAPTPRXDESC_IPPT ((uint32_t)0x00000007) /* IP Payload Type */
mbed_official 87:085cde657901 903 #define ETH_DMAPTPRXDESC_IPPT_UDP ((uint32_t)0x00000001) /* UDP payload encapsulated in the IP datagram */
mbed_official 87:085cde657901 904 #define ETH_DMAPTPRXDESC_IPPT_TCP ((uint32_t)0x00000002) /* TCP payload encapsulated in the IP datagram */
mbed_official 87:085cde657901 905 #define ETH_DMAPTPRXDESC_IPPT_ICMP ((uint32_t)0x00000003) /* ICMP payload encapsulated in the IP datagram */
mbed_official 87:085cde657901 906
mbed_official 87:085cde657901 907 /* Bit definition of RDES6 register */
mbed_official 87:085cde657901 908 #define ETH_DMAPTPRXDESC_RTSL ((uint32_t)0xFFFFFFFF) /* Receive Time Stamp Low */
mbed_official 87:085cde657901 909
mbed_official 87:085cde657901 910 /* Bit definition of RDES7 register */
mbed_official 87:085cde657901 911 #define ETH_DMAPTPRXDESC_RTSH ((uint32_t)0xFFFFFFFF) /* Receive Time Stamp High */
mbed_official 532:fe11edbda85c 912 /**
mbed_official 532:fe11edbda85c 913 * @}
mbed_official 532:fe11edbda85c 914 */
mbed_official 532:fe11edbda85c 915 /** @defgroup ETH_AutoNegotiation ETH AutoNegotiation
mbed_official 87:085cde657901 916 * @{
mbed_official 87:085cde657901 917 */
mbed_official 87:085cde657901 918 #define ETH_AUTONEGOTIATION_ENABLE ((uint32_t)0x00000001)
mbed_official 87:085cde657901 919 #define ETH_AUTONEGOTIATION_DISABLE ((uint32_t)0x00000000)
mbed_official 532:fe11edbda85c 920
mbed_official 87:085cde657901 921 /**
mbed_official 87:085cde657901 922 * @}
mbed_official 87:085cde657901 923 */
mbed_official 532:fe11edbda85c 924 /** @defgroup ETH_Speed ETH Speed
mbed_official 87:085cde657901 925 * @{
mbed_official 87:085cde657901 926 */
mbed_official 87:085cde657901 927 #define ETH_SPEED_10M ((uint32_t)0x00000000)
mbed_official 87:085cde657901 928 #define ETH_SPEED_100M ((uint32_t)0x00004000)
mbed_official 532:fe11edbda85c 929
mbed_official 87:085cde657901 930 /**
mbed_official 87:085cde657901 931 * @}
mbed_official 87:085cde657901 932 */
mbed_official 532:fe11edbda85c 933 /** @defgroup ETH_Duplex_Mode ETH Duplex Mode
mbed_official 87:085cde657901 934 * @{
mbed_official 87:085cde657901 935 */
mbed_official 87:085cde657901 936 #define ETH_MODE_FULLDUPLEX ((uint32_t)0x00000800)
mbed_official 87:085cde657901 937 #define ETH_MODE_HALFDUPLEX ((uint32_t)0x00000000)
mbed_official 87:085cde657901 938 /**
mbed_official 87:085cde657901 939 * @}
mbed_official 87:085cde657901 940 */
mbed_official 532:fe11edbda85c 941 /** @defgroup ETH_Rx_Mode ETH Rx Mode
mbed_official 87:085cde657901 942 * @{
mbed_official 87:085cde657901 943 */
mbed_official 87:085cde657901 944 #define ETH_RXPOLLING_MODE ((uint32_t)0x00000000)
mbed_official 87:085cde657901 945 #define ETH_RXINTERRUPT_MODE ((uint32_t)0x00000001)
mbed_official 87:085cde657901 946 /**
mbed_official 87:085cde657901 947 * @}
mbed_official 87:085cde657901 948 */
mbed_official 87:085cde657901 949
mbed_official 532:fe11edbda85c 950 /** @defgroup ETH_Checksum_Mode ETH Checksum Mode
mbed_official 87:085cde657901 951 * @{
mbed_official 87:085cde657901 952 */
mbed_official 87:085cde657901 953 #define ETH_CHECKSUM_BY_HARDWARE ((uint32_t)0x00000000)
mbed_official 87:085cde657901 954 #define ETH_CHECKSUM_BY_SOFTWARE ((uint32_t)0x00000001)
mbed_official 87:085cde657901 955 /**
mbed_official 87:085cde657901 956 * @}
mbed_official 87:085cde657901 957 */
mbed_official 87:085cde657901 958
mbed_official 532:fe11edbda85c 959 /** @defgroup ETH_Media_Interface ETH Media Interface
mbed_official 87:085cde657901 960 * @{
mbed_official 87:085cde657901 961 */
mbed_official 87:085cde657901 962 #define ETH_MEDIA_INTERFACE_MII ((uint32_t)0x00000000)
mbed_official 87:085cde657901 963 #define ETH_MEDIA_INTERFACE_RMII ((uint32_t)SYSCFG_PMC_MII_RMII_SEL)
mbed_official 87:085cde657901 964 /**
mbed_official 87:085cde657901 965 * @}
mbed_official 87:085cde657901 966 */
mbed_official 87:085cde657901 967
mbed_official 532:fe11edbda85c 968 /** @defgroup ETH_Watchdog ETH Watchdog
mbed_official 87:085cde657901 969 * @{
mbed_official 87:085cde657901 970 */
mbed_official 87:085cde657901 971 #define ETH_WATCHDOG_ENABLE ((uint32_t)0x00000000)
mbed_official 87:085cde657901 972 #define ETH_WATCHDOG_DISABLE ((uint32_t)0x00800000)
mbed_official 87:085cde657901 973 /**
mbed_official 87:085cde657901 974 * @}
mbed_official 87:085cde657901 975 */
mbed_official 87:085cde657901 976
mbed_official 532:fe11edbda85c 977 /** @defgroup ETH_Jabber ETH Jabber
mbed_official 87:085cde657901 978 * @{
mbed_official 87:085cde657901 979 */
mbed_official 87:085cde657901 980 #define ETH_JABBER_ENABLE ((uint32_t)0x00000000)
mbed_official 87:085cde657901 981 #define ETH_JABBER_DISABLE ((uint32_t)0x00400000)
mbed_official 87:085cde657901 982 /**
mbed_official 87:085cde657901 983 * @}
mbed_official 87:085cde657901 984 */
mbed_official 87:085cde657901 985
mbed_official 532:fe11edbda85c 986 /** @defgroup ETH_Inter_Frame_Gap ETH Inter Frame Gap
mbed_official 87:085cde657901 987 * @{
mbed_official 87:085cde657901 988 */
mbed_official 87:085cde657901 989 #define ETH_INTERFRAMEGAP_96BIT ((uint32_t)0x00000000) /*!< minimum IFG between frames during transmission is 96Bit */
mbed_official 87:085cde657901 990 #define ETH_INTERFRAMEGAP_88BIT ((uint32_t)0x00020000) /*!< minimum IFG between frames during transmission is 88Bit */
mbed_official 87:085cde657901 991 #define ETH_INTERFRAMEGAP_80BIT ((uint32_t)0x00040000) /*!< minimum IFG between frames during transmission is 80Bit */
mbed_official 87:085cde657901 992 #define ETH_INTERFRAMEGAP_72BIT ((uint32_t)0x00060000) /*!< minimum IFG between frames during transmission is 72Bit */
mbed_official 87:085cde657901 993 #define ETH_INTERFRAMEGAP_64BIT ((uint32_t)0x00080000) /*!< minimum IFG between frames during transmission is 64Bit */
mbed_official 87:085cde657901 994 #define ETH_INTERFRAMEGAP_56BIT ((uint32_t)0x000A0000) /*!< minimum IFG between frames during transmission is 56Bit */
mbed_official 87:085cde657901 995 #define ETH_INTERFRAMEGAP_48BIT ((uint32_t)0x000C0000) /*!< minimum IFG between frames during transmission is 48Bit */
mbed_official 87:085cde657901 996 #define ETH_INTERFRAMEGAP_40BIT ((uint32_t)0x000E0000) /*!< minimum IFG between frames during transmission is 40Bit */
mbed_official 87:085cde657901 997 /**
mbed_official 87:085cde657901 998 * @}
mbed_official 87:085cde657901 999 */
mbed_official 87:085cde657901 1000
mbed_official 532:fe11edbda85c 1001 /** @defgroup ETH_Carrier_Sense ETH Carrier Sense
mbed_official 87:085cde657901 1002 * @{
mbed_official 87:085cde657901 1003 */
mbed_official 87:085cde657901 1004 #define ETH_CARRIERSENCE_ENABLE ((uint32_t)0x00000000)
mbed_official 532:fe11edbda85c 1005 #define ETH_CARRIERSENCE_DISABLE ((uint32_t)0x00010000)
mbed_official 87:085cde657901 1006 /**
mbed_official 87:085cde657901 1007 * @}
mbed_official 87:085cde657901 1008 */
mbed_official 87:085cde657901 1009
mbed_official 532:fe11edbda85c 1010 /** @defgroup ETH_Receive_Own ETH Receive Own
mbed_official 87:085cde657901 1011 * @{
mbed_official 87:085cde657901 1012 */
mbed_official 87:085cde657901 1013 #define ETH_RECEIVEOWN_ENABLE ((uint32_t)0x00000000)
mbed_official 532:fe11edbda85c 1014 #define ETH_RECEIVEOWN_DISABLE ((uint32_t)0x00002000)
mbed_official 87:085cde657901 1015 /**
mbed_official 87:085cde657901 1016 * @}
mbed_official 87:085cde657901 1017 */
mbed_official 87:085cde657901 1018
mbed_official 532:fe11edbda85c 1019 /** @defgroup ETH_Loop_Back_Mode ETH Loop Back Mode
mbed_official 87:085cde657901 1020 * @{
mbed_official 87:085cde657901 1021 */
mbed_official 87:085cde657901 1022 #define ETH_LOOPBACKMODE_ENABLE ((uint32_t)0x00001000)
mbed_official 87:085cde657901 1023 #define ETH_LOOPBACKMODE_DISABLE ((uint32_t)0x00000000)
mbed_official 87:085cde657901 1024 /**
mbed_official 87:085cde657901 1025 * @}
mbed_official 87:085cde657901 1026 */
mbed_official 87:085cde657901 1027
mbed_official 532:fe11edbda85c 1028 /** @defgroup ETH_Checksum_Offload ETH Checksum Offload
mbed_official 87:085cde657901 1029 * @{
mbed_official 87:085cde657901 1030 */
mbed_official 87:085cde657901 1031 #define ETH_CHECKSUMOFFLAOD_ENABLE ((uint32_t)0x00000400)
mbed_official 87:085cde657901 1032 #define ETH_CHECKSUMOFFLAOD_DISABLE ((uint32_t)0x00000000)
mbed_official 87:085cde657901 1033 /**
mbed_official 87:085cde657901 1034 * @}
mbed_official 87:085cde657901 1035 */
mbed_official 87:085cde657901 1036
mbed_official 532:fe11edbda85c 1037 /** @defgroup ETH_Retry_Transmission ETH Retry Transmission
mbed_official 87:085cde657901 1038 * @{
mbed_official 87:085cde657901 1039 */
mbed_official 87:085cde657901 1040 #define ETH_RETRYTRANSMISSION_ENABLE ((uint32_t)0x00000000)
mbed_official 87:085cde657901 1041 #define ETH_RETRYTRANSMISSION_DISABLE ((uint32_t)0x00000200)
mbed_official 87:085cde657901 1042 /**
mbed_official 87:085cde657901 1043 * @}
mbed_official 87:085cde657901 1044 */
mbed_official 87:085cde657901 1045
mbed_official 532:fe11edbda85c 1046 /** @defgroup ETH_Automatic_Pad_CRC_Strip ETH Automatic Pad CRC Strip
mbed_official 87:085cde657901 1047 * @{
mbed_official 87:085cde657901 1048 */
mbed_official 87:085cde657901 1049 #define ETH_AUTOMATICPADCRCSTRIP_ENABLE ((uint32_t)0x00000080)
mbed_official 87:085cde657901 1050 #define ETH_AUTOMATICPADCRCSTRIP_DISABLE ((uint32_t)0x00000000)
mbed_official 87:085cde657901 1051 /**
mbed_official 87:085cde657901 1052 * @}
mbed_official 87:085cde657901 1053 */
mbed_official 87:085cde657901 1054
mbed_official 532:fe11edbda85c 1055 /** @defgroup ETH_Back_Off_Limit ETH Back Off Limit
mbed_official 87:085cde657901 1056 * @{
mbed_official 87:085cde657901 1057 */
mbed_official 87:085cde657901 1058 #define ETH_BACKOFFLIMIT_10 ((uint32_t)0x00000000)
mbed_official 87:085cde657901 1059 #define ETH_BACKOFFLIMIT_8 ((uint32_t)0x00000020)
mbed_official 87:085cde657901 1060 #define ETH_BACKOFFLIMIT_4 ((uint32_t)0x00000040)
mbed_official 87:085cde657901 1061 #define ETH_BACKOFFLIMIT_1 ((uint32_t)0x00000060)
mbed_official 87:085cde657901 1062 /**
mbed_official 87:085cde657901 1063 * @}
mbed_official 87:085cde657901 1064 */
mbed_official 87:085cde657901 1065
mbed_official 532:fe11edbda85c 1066 /** @defgroup ETH_Deferral_Check ETH Deferral Check
mbed_official 87:085cde657901 1067 * @{
mbed_official 87:085cde657901 1068 */
mbed_official 87:085cde657901 1069 #define ETH_DEFFERRALCHECK_ENABLE ((uint32_t)0x00000010)
mbed_official 87:085cde657901 1070 #define ETH_DEFFERRALCHECK_DISABLE ((uint32_t)0x00000000)
mbed_official 87:085cde657901 1071 /**
mbed_official 87:085cde657901 1072 * @}
mbed_official 87:085cde657901 1073 */
mbed_official 87:085cde657901 1074
mbed_official 532:fe11edbda85c 1075 /** @defgroup ETH_Receive_All ETH Receive All
mbed_official 87:085cde657901 1076 * @{
mbed_official 87:085cde657901 1077 */
mbed_official 87:085cde657901 1078 #define ETH_RECEIVEALL_ENABLE ((uint32_t)0x80000000)
mbed_official 87:085cde657901 1079 #define ETH_RECEIVEAll_DISABLE ((uint32_t)0x00000000)
mbed_official 87:085cde657901 1080 /**
mbed_official 87:085cde657901 1081 * @}
mbed_official 87:085cde657901 1082 */
mbed_official 87:085cde657901 1083
mbed_official 532:fe11edbda85c 1084 /** @defgroup ETH_Source_Addr_Filter ETH Source Addr Filter
mbed_official 87:085cde657901 1085 * @{
mbed_official 87:085cde657901 1086 */
mbed_official 87:085cde657901 1087 #define ETH_SOURCEADDRFILTER_NORMAL_ENABLE ((uint32_t)0x00000200)
mbed_official 87:085cde657901 1088 #define ETH_SOURCEADDRFILTER_INVERSE_ENABLE ((uint32_t)0x00000300)
mbed_official 87:085cde657901 1089 #define ETH_SOURCEADDRFILTER_DISABLE ((uint32_t)0x00000000)
mbed_official 87:085cde657901 1090 /**
mbed_official 87:085cde657901 1091 * @}
mbed_official 87:085cde657901 1092 */
mbed_official 87:085cde657901 1093
mbed_official 532:fe11edbda85c 1094 /** @defgroup ETH_Pass_Control_Frames ETH Pass Control Frames
mbed_official 87:085cde657901 1095 * @{
mbed_official 87:085cde657901 1096 */
mbed_official 87:085cde657901 1097 #define ETH_PASSCONTROLFRAMES_BLOCKALL ((uint32_t)0x00000040) /*!< MAC filters all control frames from reaching the application */
mbed_official 87:085cde657901 1098 #define ETH_PASSCONTROLFRAMES_FORWARDALL ((uint32_t)0x00000080) /*!< MAC forwards all control frames to application even if they fail the Address Filter */
mbed_official 87:085cde657901 1099 #define ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER ((uint32_t)0x000000C0) /*!< MAC forwards control frames that pass the Address Filter. */
mbed_official 87:085cde657901 1100 /**
mbed_official 87:085cde657901 1101 * @}
mbed_official 87:085cde657901 1102 */
mbed_official 87:085cde657901 1103
mbed_official 532:fe11edbda85c 1104 /** @defgroup ETH_Broadcast_Frames_Reception ETH Broadcast Frames Reception
mbed_official 87:085cde657901 1105 * @{
mbed_official 87:085cde657901 1106 */
mbed_official 87:085cde657901 1107 #define ETH_BROADCASTFRAMESRECEPTION_ENABLE ((uint32_t)0x00000000)
mbed_official 87:085cde657901 1108 #define ETH_BROADCASTFRAMESRECEPTION_DISABLE ((uint32_t)0x00000020)
mbed_official 87:085cde657901 1109 /**
mbed_official 87:085cde657901 1110 * @}
mbed_official 87:085cde657901 1111 */
mbed_official 87:085cde657901 1112
mbed_official 532:fe11edbda85c 1113 /** @defgroup ETH_Destination_Addr_Filter ETH Destination Addr Filter
mbed_official 87:085cde657901 1114 * @{
mbed_official 87:085cde657901 1115 */
mbed_official 87:085cde657901 1116 #define ETH_DESTINATIONADDRFILTER_NORMAL ((uint32_t)0x00000000)
mbed_official 87:085cde657901 1117 #define ETH_DESTINATIONADDRFILTER_INVERSE ((uint32_t)0x00000008)
mbed_official 87:085cde657901 1118 /**
mbed_official 87:085cde657901 1119 * @}
mbed_official 87:085cde657901 1120 */
mbed_official 87:085cde657901 1121
mbed_official 532:fe11edbda85c 1122 /** @defgroup ETH_Promiscuous_Mode ETH Promiscuous Mode
mbed_official 87:085cde657901 1123 * @{
mbed_official 87:085cde657901 1124 */
mbed_official 532:fe11edbda85c 1125 #define ETH_PROMISCUOUS_MODE_ENABLE ((uint32_t)0x00000001)
mbed_official 532:fe11edbda85c 1126 #define ETH_PROMISCUOUS_MODE_DISABLE ((uint32_t)0x00000000)
mbed_official 87:085cde657901 1127 /**
mbed_official 87:085cde657901 1128 * @}
mbed_official 87:085cde657901 1129 */
mbed_official 87:085cde657901 1130
mbed_official 532:fe11edbda85c 1131 /** @defgroup ETH_Multicast_Frames_Filter ETH Multicast Frames Filter
mbed_official 87:085cde657901 1132 * @{
mbed_official 87:085cde657901 1133 */
mbed_official 87:085cde657901 1134 #define ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE ((uint32_t)0x00000404)
mbed_official 87:085cde657901 1135 #define ETH_MULTICASTFRAMESFILTER_HASHTABLE ((uint32_t)0x00000004)
mbed_official 87:085cde657901 1136 #define ETH_MULTICASTFRAMESFILTER_PERFECT ((uint32_t)0x00000000)
mbed_official 87:085cde657901 1137 #define ETH_MULTICASTFRAMESFILTER_NONE ((uint32_t)0x00000010)
mbed_official 87:085cde657901 1138 /**
mbed_official 87:085cde657901 1139 * @}
mbed_official 87:085cde657901 1140 */
mbed_official 87:085cde657901 1141
mbed_official 532:fe11edbda85c 1142 /** @defgroup ETH_Unicast_Frames_Filter ETH Unicast Frames Filter
mbed_official 87:085cde657901 1143 * @{
mbed_official 87:085cde657901 1144 */
mbed_official 87:085cde657901 1145 #define ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE ((uint32_t)0x00000402)
mbed_official 87:085cde657901 1146 #define ETH_UNICASTFRAMESFILTER_HASHTABLE ((uint32_t)0x00000002)
mbed_official 87:085cde657901 1147 #define ETH_UNICASTFRAMESFILTER_PERFECT ((uint32_t)0x00000000)
mbed_official 87:085cde657901 1148 /**
mbed_official 87:085cde657901 1149 * @}
mbed_official 87:085cde657901 1150 */
mbed_official 87:085cde657901 1151
mbed_official 532:fe11edbda85c 1152 /** @defgroup ETH_Zero_Quanta_Pause ETH Zero Quanta Pause
mbed_official 87:085cde657901 1153 * @{
mbed_official 87:085cde657901 1154 */
mbed_official 532:fe11edbda85c 1155 #define ETH_ZEROQUANTAPAUSE_ENABLE ((uint32_t)0x00000000)
mbed_official 532:fe11edbda85c 1156 #define ETH_ZEROQUANTAPAUSE_DISABLE ((uint32_t)0x00000080)
mbed_official 87:085cde657901 1157 /**
mbed_official 87:085cde657901 1158 * @}
mbed_official 87:085cde657901 1159 */
mbed_official 87:085cde657901 1160
mbed_official 532:fe11edbda85c 1161 /** @defgroup ETH_Pause_Low_Threshold ETH Pause Low Threshold
mbed_official 87:085cde657901 1162 * @{
mbed_official 87:085cde657901 1163 */
mbed_official 87:085cde657901 1164 #define ETH_PAUSELOWTHRESHOLD_MINUS4 ((uint32_t)0x00000000) /*!< Pause time minus 4 slot times */
mbed_official 87:085cde657901 1165 #define ETH_PAUSELOWTHRESHOLD_MINUS28 ((uint32_t)0x00000010) /*!< Pause time minus 28 slot times */
mbed_official 87:085cde657901 1166 #define ETH_PAUSELOWTHRESHOLD_MINUS144 ((uint32_t)0x00000020) /*!< Pause time minus 144 slot times */
mbed_official 87:085cde657901 1167 #define ETH_PAUSELOWTHRESHOLD_MINUS256 ((uint32_t)0x00000030) /*!< Pause time minus 256 slot times */
mbed_official 87:085cde657901 1168 /**
mbed_official 87:085cde657901 1169 * @}
mbed_official 87:085cde657901 1170 */
mbed_official 87:085cde657901 1171
mbed_official 532:fe11edbda85c 1172 /** @defgroup ETH_Unicast_Pause_Frame_Detect ETH Unicast Pause Frame Detect
mbed_official 87:085cde657901 1173 * @{
mbed_official 87:085cde657901 1174 */
mbed_official 87:085cde657901 1175 #define ETH_UNICASTPAUSEFRAMEDETECT_ENABLE ((uint32_t)0x00000008)
mbed_official 87:085cde657901 1176 #define ETH_UNICASTPAUSEFRAMEDETECT_DISABLE ((uint32_t)0x00000000)
mbed_official 87:085cde657901 1177 /**
mbed_official 87:085cde657901 1178 * @}
mbed_official 87:085cde657901 1179 */
mbed_official 87:085cde657901 1180
mbed_official 532:fe11edbda85c 1181 /** @defgroup ETH_Receive_Flow_Control ETH Receive Flow Control
mbed_official 87:085cde657901 1182 * @{
mbed_official 87:085cde657901 1183 */
mbed_official 87:085cde657901 1184 #define ETH_RECEIVEFLOWCONTROL_ENABLE ((uint32_t)0x00000004)
mbed_official 87:085cde657901 1185 #define ETH_RECEIVEFLOWCONTROL_DISABLE ((uint32_t)0x00000000)
mbed_official 87:085cde657901 1186 /**
mbed_official 87:085cde657901 1187 * @}
mbed_official 87:085cde657901 1188 */
mbed_official 87:085cde657901 1189
mbed_official 532:fe11edbda85c 1190 /** @defgroup ETH_Transmit_Flow_Control ETH Transmit Flow Control
mbed_official 87:085cde657901 1191 * @{
mbed_official 87:085cde657901 1192 */
mbed_official 87:085cde657901 1193 #define ETH_TRANSMITFLOWCONTROL_ENABLE ((uint32_t)0x00000002)
mbed_official 87:085cde657901 1194 #define ETH_TRANSMITFLOWCONTROL_DISABLE ((uint32_t)0x00000000)
mbed_official 87:085cde657901 1195 /**
mbed_official 87:085cde657901 1196 * @}
mbed_official 87:085cde657901 1197 */
mbed_official 87:085cde657901 1198
mbed_official 532:fe11edbda85c 1199 /** @defgroup ETH_VLAN_Tag_Comparison ETH VLAN Tag Comparison
mbed_official 87:085cde657901 1200 * @{
mbed_official 87:085cde657901 1201 */
mbed_official 87:085cde657901 1202 #define ETH_VLANTAGCOMPARISON_12BIT ((uint32_t)0x00010000)
mbed_official 87:085cde657901 1203 #define ETH_VLANTAGCOMPARISON_16BIT ((uint32_t)0x00000000)
mbed_official 87:085cde657901 1204 /**
mbed_official 87:085cde657901 1205 * @}
mbed_official 87:085cde657901 1206 */
mbed_official 87:085cde657901 1207
mbed_official 532:fe11edbda85c 1208 /** @defgroup ETH_MAC_addresses ETH MAC addresses
mbed_official 87:085cde657901 1209 * @{
mbed_official 87:085cde657901 1210 */
mbed_official 87:085cde657901 1211 #define ETH_MAC_ADDRESS0 ((uint32_t)0x00000000)
mbed_official 87:085cde657901 1212 #define ETH_MAC_ADDRESS1 ((uint32_t)0x00000008)
mbed_official 87:085cde657901 1213 #define ETH_MAC_ADDRESS2 ((uint32_t)0x00000010)
mbed_official 87:085cde657901 1214 #define ETH_MAC_ADDRESS3 ((uint32_t)0x00000018)
mbed_official 87:085cde657901 1215 /**
mbed_official 87:085cde657901 1216 * @}
mbed_official 87:085cde657901 1217 */
mbed_official 87:085cde657901 1218
mbed_official 532:fe11edbda85c 1219 /** @defgroup ETH_MAC_addresses_filter_SA_DA ETH MAC addresses filter SA DA
mbed_official 87:085cde657901 1220 * @{
mbed_official 87:085cde657901 1221 */
mbed_official 87:085cde657901 1222 #define ETH_MAC_ADDRESSFILTER_SA ((uint32_t)0x00000000)
mbed_official 87:085cde657901 1223 #define ETH_MAC_ADDRESSFILTER_DA ((uint32_t)0x00000008)
mbed_official 87:085cde657901 1224 /**
mbed_official 87:085cde657901 1225 * @}
mbed_official 87:085cde657901 1226 */
mbed_official 87:085cde657901 1227
mbed_official 532:fe11edbda85c 1228 /** @defgroup ETH_MAC_addresses_filter_Mask_bytes ETH MAC addresses filter Mask bytes
mbed_official 87:085cde657901 1229 * @{
mbed_official 87:085cde657901 1230 */
mbed_official 87:085cde657901 1231 #define ETH_MAC_ADDRESSMASK_BYTE6 ((uint32_t)0x20000000) /*!< Mask MAC Address high reg bits [15:8] */
mbed_official 87:085cde657901 1232 #define ETH_MAC_ADDRESSMASK_BYTE5 ((uint32_t)0x10000000) /*!< Mask MAC Address high reg bits [7:0] */
mbed_official 87:085cde657901 1233 #define ETH_MAC_ADDRESSMASK_BYTE4 ((uint32_t)0x08000000) /*!< Mask MAC Address low reg bits [31:24] */
mbed_official 87:085cde657901 1234 #define ETH_MAC_ADDRESSMASK_BYTE3 ((uint32_t)0x04000000) /*!< Mask MAC Address low reg bits [23:16] */
mbed_official 87:085cde657901 1235 #define ETH_MAC_ADDRESSMASK_BYTE2 ((uint32_t)0x02000000) /*!< Mask MAC Address low reg bits [15:8] */
mbed_official 87:085cde657901 1236 #define ETH_MAC_ADDRESSMASK_BYTE1 ((uint32_t)0x01000000) /*!< Mask MAC Address low reg bits [70] */
mbed_official 87:085cde657901 1237 /**
mbed_official 87:085cde657901 1238 * @}
mbed_official 87:085cde657901 1239 */
mbed_official 87:085cde657901 1240
mbed_official 532:fe11edbda85c 1241 /** @defgroup ETH_MAC_Debug_flags ETH MAC Debug flags
mbed_official 87:085cde657901 1242 * @{
mbed_official 87:085cde657901 1243 */
mbed_official 87:085cde657901 1244 #define ETH_MAC_TXFIFO_FULL ((uint32_t)0x02000000) /* Tx FIFO full */
mbed_official 87:085cde657901 1245 #define ETH_MAC_TXFIFONOT_EMPTY ((uint32_t)0x01000000) /* Tx FIFO not empty */
mbed_official 87:085cde657901 1246 #define ETH_MAC_TXFIFO_WRITE_ACTIVE ((uint32_t)0x00400000) /* Tx FIFO write active */
mbed_official 87:085cde657901 1247 #define ETH_MAC_TXFIFO_IDLE ((uint32_t)0x00000000) /* Tx FIFO read status: Idle */
mbed_official 87:085cde657901 1248 #define ETH_MAC_TXFIFO_READ ((uint32_t)0x00100000) /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
mbed_official 87:085cde657901 1249 #define ETH_MAC_TXFIFO_WAITING ((uint32_t)0x00200000) /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
mbed_official 87:085cde657901 1250 #define ETH_MAC_TXFIFO_WRITING ((uint32_t)0x00300000) /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
mbed_official 87:085cde657901 1251 #define ETH_MAC_TRANSMISSION_PAUSE ((uint32_t)0x00080000) /* MAC transmitter in pause */
mbed_official 87:085cde657901 1252 #define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE ((uint32_t)0x00000000) /* MAC transmit frame controller: Idle */
mbed_official 87:085cde657901 1253 #define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING ((uint32_t)0x00020000) /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
mbed_official 87:085cde657901 1254 #define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF ((uint32_t)0x00040000) /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
mbed_official 87:085cde657901 1255 #define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING ((uint32_t)0x00060000) /* MAC transmit frame controller: Transferring input frame for transmission */
mbed_official 87:085cde657901 1256 #define ETH_MAC_MII_TRANSMIT_ACTIVE ((uint32_t)0x00010000) /* MAC MII transmit engine active */
mbed_official 87:085cde657901 1257 #define ETH_MAC_RXFIFO_EMPTY ((uint32_t)0x00000000) /* Rx FIFO fill level: empty */
mbed_official 87:085cde657901 1258 #define ETH_MAC_RXFIFO_BELOW_THRESHOLD ((uint32_t)0x00000100) /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
mbed_official 87:085cde657901 1259 #define ETH_MAC_RXFIFO_ABOVE_THRESHOLD ((uint32_t)0x00000200) /* Rx FIFO fill level: fill-level above flow-control activate threshold */
mbed_official 87:085cde657901 1260 #define ETH_MAC_RXFIFO_FULL ((uint32_t)0x00000300) /* Rx FIFO fill level: full */
mbed_official 87:085cde657901 1261 #define ETH_MAC_READCONTROLLER_IDLE ((uint32_t)0x00000060) /* Rx FIFO read controller IDLE state */
mbed_official 87:085cde657901 1262 #define ETH_MAC_READCONTROLLER_READING_DATA ((uint32_t)0x00000060) /* Rx FIFO read controller Reading frame data */
mbed_official 87:085cde657901 1263 #define ETH_MAC_READCONTROLLER_READING_STATUS ((uint32_t)0x00000060) /* Rx FIFO read controller Reading frame status (or time-stamp) */
mbed_official 87:085cde657901 1264 #define ETH_MAC_READCONTROLLER_ FLUSHING ((uint32_t)0x00000060) /* Rx FIFO read controller Flushing the frame data and status */
mbed_official 87:085cde657901 1265 #define ETH_MAC_RXFIFO_WRITE_ACTIVE ((uint32_t)0x00000010) /* Rx FIFO write controller active */
mbed_official 87:085cde657901 1266 #define ETH_MAC_SMALL_FIFO_NOTACTIVE ((uint32_t)0x00000000) /* MAC small FIFO read / write controllers not active */
mbed_official 87:085cde657901 1267 #define ETH_MAC_SMALL_FIFO_READ_ACTIVE ((uint32_t)0x00000002) /* MAC small FIFO read controller active */
mbed_official 87:085cde657901 1268 #define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE ((uint32_t)0x00000004) /* MAC small FIFO write controller active */
mbed_official 87:085cde657901 1269 #define ETH_MAC_SMALL_FIFO_RW_ACTIVE ((uint32_t)0x00000006) /* MAC small FIFO read / write controllers active */
mbed_official 532:fe11edbda85c 1270 #define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE ((uint32_t)0x00000001) /* MAC MII receive protocol engine active */
mbed_official 87:085cde657901 1271 /**
mbed_official 87:085cde657901 1272 * @}
mbed_official 87:085cde657901 1273 */
mbed_official 87:085cde657901 1274
mbed_official 532:fe11edbda85c 1275 /** @defgroup ETH_Drop_TCP_IP_Checksum_Error_Frame ETH Drop TCP IP Checksum Error Frame
mbed_official 87:085cde657901 1276 * @{
mbed_official 87:085cde657901 1277 */
mbed_official 87:085cde657901 1278 #define ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE ((uint32_t)0x00000000)
mbed_official 87:085cde657901 1279 #define ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE ((uint32_t)0x04000000)
mbed_official 87:085cde657901 1280 /**
mbed_official 87:085cde657901 1281 * @}
mbed_official 87:085cde657901 1282 */
mbed_official 87:085cde657901 1283
mbed_official 532:fe11edbda85c 1284 /** @defgroup ETH_Receive_Store_Forward ETH Receive Store Forward
mbed_official 87:085cde657901 1285 * @{
mbed_official 87:085cde657901 1286 */
mbed_official 87:085cde657901 1287 #define ETH_RECEIVESTOREFORWARD_ENABLE ((uint32_t)0x02000000)
mbed_official 87:085cde657901 1288 #define ETH_RECEIVESTOREFORWARD_DISABLE ((uint32_t)0x00000000)
mbed_official 87:085cde657901 1289 /**
mbed_official 87:085cde657901 1290 * @}
mbed_official 87:085cde657901 1291 */
mbed_official 87:085cde657901 1292
mbed_official 532:fe11edbda85c 1293 /** @defgroup ETH_Flush_Received_Frame ETH Flush Received Frame
mbed_official 87:085cde657901 1294 * @{
mbed_official 87:085cde657901 1295 */
mbed_official 87:085cde657901 1296 #define ETH_FLUSHRECEIVEDFRAME_ENABLE ((uint32_t)0x00000000)
mbed_official 87:085cde657901 1297 #define ETH_FLUSHRECEIVEDFRAME_DISABLE ((uint32_t)0x01000000)
mbed_official 87:085cde657901 1298 /**
mbed_official 87:085cde657901 1299 * @}
mbed_official 87:085cde657901 1300 */
mbed_official 87:085cde657901 1301
mbed_official 532:fe11edbda85c 1302 /** @defgroup ETH_Transmit_Store_Forward ETH Transmit Store Forward
mbed_official 87:085cde657901 1303 * @{
mbed_official 87:085cde657901 1304 */
mbed_official 87:085cde657901 1305 #define ETH_TRANSMITSTOREFORWARD_ENABLE ((uint32_t)0x00200000)
mbed_official 87:085cde657901 1306 #define ETH_TRANSMITSTOREFORWARD_DISABLE ((uint32_t)0x00000000)
mbed_official 87:085cde657901 1307 /**
mbed_official 87:085cde657901 1308 * @}
mbed_official 87:085cde657901 1309 */
mbed_official 87:085cde657901 1310
mbed_official 532:fe11edbda85c 1311 /** @defgroup ETH_Transmit_Threshold_Control ETH Transmit Threshold Control
mbed_official 87:085cde657901 1312 * @{
mbed_official 87:085cde657901 1313 */
mbed_official 87:085cde657901 1314 #define ETH_TRANSMITTHRESHOLDCONTROL_64BYTES ((uint32_t)0x00000000) /*!< threshold level of the MTL Transmit FIFO is 64 Bytes */
mbed_official 87:085cde657901 1315 #define ETH_TRANSMITTHRESHOLDCONTROL_128BYTES ((uint32_t)0x00004000) /*!< threshold level of the MTL Transmit FIFO is 128 Bytes */
mbed_official 87:085cde657901 1316 #define ETH_TRANSMITTHRESHOLDCONTROL_192BYTES ((uint32_t)0x00008000) /*!< threshold level of the MTL Transmit FIFO is 192 Bytes */
mbed_official 87:085cde657901 1317 #define ETH_TRANSMITTHRESHOLDCONTROL_256BYTES ((uint32_t)0x0000C000) /*!< threshold level of the MTL Transmit FIFO is 256 Bytes */
mbed_official 87:085cde657901 1318 #define ETH_TRANSMITTHRESHOLDCONTROL_40BYTES ((uint32_t)0x00010000) /*!< threshold level of the MTL Transmit FIFO is 40 Bytes */
mbed_official 87:085cde657901 1319 #define ETH_TRANSMITTHRESHOLDCONTROL_32BYTES ((uint32_t)0x00014000) /*!< threshold level of the MTL Transmit FIFO is 32 Bytes */
mbed_official 87:085cde657901 1320 #define ETH_TRANSMITTHRESHOLDCONTROL_24BYTES ((uint32_t)0x00018000) /*!< threshold level of the MTL Transmit FIFO is 24 Bytes */
mbed_official 87:085cde657901 1321 #define ETH_TRANSMITTHRESHOLDCONTROL_16BYTES ((uint32_t)0x0001C000) /*!< threshold level of the MTL Transmit FIFO is 16 Bytes */
mbed_official 87:085cde657901 1322 /**
mbed_official 87:085cde657901 1323 * @}
mbed_official 87:085cde657901 1324 */
mbed_official 87:085cde657901 1325
mbed_official 532:fe11edbda85c 1326 /** @defgroup ETH_Forward_Error_Frames ETH Forward Error Frames
mbed_official 87:085cde657901 1327 * @{
mbed_official 87:085cde657901 1328 */
mbed_official 87:085cde657901 1329 #define ETH_FORWARDERRORFRAMES_ENABLE ((uint32_t)0x00000080)
mbed_official 87:085cde657901 1330 #define ETH_FORWARDERRORFRAMES_DISABLE ((uint32_t)0x00000000)
mbed_official 87:085cde657901 1331 /**
mbed_official 87:085cde657901 1332 * @}
mbed_official 87:085cde657901 1333 */
mbed_official 87:085cde657901 1334
mbed_official 532:fe11edbda85c 1335 /** @defgroup ETH_Forward_Undersized_Good_Frames ETH Forward Undersized Good Frames
mbed_official 87:085cde657901 1336 * @{
mbed_official 87:085cde657901 1337 */
mbed_official 87:085cde657901 1338 #define ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE ((uint32_t)0x00000040)
mbed_official 87:085cde657901 1339 #define ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE ((uint32_t)0x00000000)
mbed_official 87:085cde657901 1340 /**
mbed_official 87:085cde657901 1341 * @}
mbed_official 87:085cde657901 1342 */
mbed_official 87:085cde657901 1343
mbed_official 532:fe11edbda85c 1344 /** @defgroup ETH_Receive_Threshold_Control ETH Receive Threshold Control
mbed_official 87:085cde657901 1345 * @{
mbed_official 87:085cde657901 1346 */
mbed_official 87:085cde657901 1347 #define ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES ((uint32_t)0x00000000) /*!< threshold level of the MTL Receive FIFO is 64 Bytes */
mbed_official 87:085cde657901 1348 #define ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES ((uint32_t)0x00000008) /*!< threshold level of the MTL Receive FIFO is 32 Bytes */
mbed_official 87:085cde657901 1349 #define ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES ((uint32_t)0x00000010) /*!< threshold level of the MTL Receive FIFO is 96 Bytes */
mbed_official 87:085cde657901 1350 #define ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES ((uint32_t)0x00000018) /*!< threshold level of the MTL Receive FIFO is 128 Bytes */
mbed_official 87:085cde657901 1351 /**
mbed_official 87:085cde657901 1352 * @}
mbed_official 87:085cde657901 1353 */
mbed_official 87:085cde657901 1354
mbed_official 532:fe11edbda85c 1355 /** @defgroup ETH_Second_Frame_Operate ETH Second Frame Operate
mbed_official 87:085cde657901 1356 * @{
mbed_official 87:085cde657901 1357 */
mbed_official 87:085cde657901 1358 #define ETH_SECONDFRAMEOPERARTE_ENABLE ((uint32_t)0x00000004)
mbed_official 87:085cde657901 1359 #define ETH_SECONDFRAMEOPERARTE_DISABLE ((uint32_t)0x00000000)
mbed_official 87:085cde657901 1360 /**
mbed_official 87:085cde657901 1361 * @}
mbed_official 87:085cde657901 1362 */
mbed_official 87:085cde657901 1363
mbed_official 532:fe11edbda85c 1364 /** @defgroup ETH_Address_Aligned_Beats ETH Address Aligned Beats
mbed_official 87:085cde657901 1365 * @{
mbed_official 87:085cde657901 1366 */
mbed_official 87:085cde657901 1367 #define ETH_ADDRESSALIGNEDBEATS_ENABLE ((uint32_t)0x02000000)
mbed_official 87:085cde657901 1368 #define ETH_ADDRESSALIGNEDBEATS_DISABLE ((uint32_t)0x00000000)
mbed_official 87:085cde657901 1369 /**
mbed_official 87:085cde657901 1370 * @}
mbed_official 87:085cde657901 1371 */
mbed_official 87:085cde657901 1372
mbed_official 532:fe11edbda85c 1373 /** @defgroup ETH_Fixed_Burst ETH Fixed Burst
mbed_official 87:085cde657901 1374 * @{
mbed_official 87:085cde657901 1375 */
mbed_official 87:085cde657901 1376 #define ETH_FIXEDBURST_ENABLE ((uint32_t)0x00010000)
mbed_official 87:085cde657901 1377 #define ETH_FIXEDBURST_DISABLE ((uint32_t)0x00000000)
mbed_official 87:085cde657901 1378 /**
mbed_official 87:085cde657901 1379 * @}
mbed_official 87:085cde657901 1380 */
mbed_official 87:085cde657901 1381
mbed_official 532:fe11edbda85c 1382 /** @defgroup ETH_Rx_DMA_Burst_Length ETH Rx DMA Burst Length
mbed_official 87:085cde657901 1383 * @{
mbed_official 87:085cde657901 1384 */
mbed_official 87:085cde657901 1385 #define ETH_RXDMABURSTLENGTH_1BEAT ((uint32_t)0x00020000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 1 */
mbed_official 87:085cde657901 1386 #define ETH_RXDMABURSTLENGTH_2BEAT ((uint32_t)0x00040000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 2 */
mbed_official 87:085cde657901 1387 #define ETH_RXDMABURSTLENGTH_4BEAT ((uint32_t)0x00080000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */
mbed_official 87:085cde657901 1388 #define ETH_RXDMABURSTLENGTH_8BEAT ((uint32_t)0x00100000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */
mbed_official 87:085cde657901 1389 #define ETH_RXDMABURSTLENGTH_16BEAT ((uint32_t)0x00200000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */
mbed_official 87:085cde657901 1390 #define ETH_RXDMABURSTLENGTH_32BEAT ((uint32_t)0x00400000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */
mbed_official 87:085cde657901 1391 #define ETH_RXDMABURSTLENGTH_4XPBL_4BEAT ((uint32_t)0x01020000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */
mbed_official 87:085cde657901 1392 #define ETH_RXDMABURSTLENGTH_4XPBL_8BEAT ((uint32_t)0x01040000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */
mbed_official 87:085cde657901 1393 #define ETH_RXDMABURSTLENGTH_4XPBL_16BEAT ((uint32_t)0x01080000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */
mbed_official 87:085cde657901 1394 #define ETH_RXDMABURSTLENGTH_4XPBL_32BEAT ((uint32_t)0x01100000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */
mbed_official 87:085cde657901 1395 #define ETH_RXDMABURSTLENGTH_4XPBL_64BEAT ((uint32_t)0x01200000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 64 */
mbed_official 87:085cde657901 1396 #define ETH_RXDMABURSTLENGTH_4XPBL_128BEAT ((uint32_t)0x01400000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 128 */
mbed_official 87:085cde657901 1397 /**
mbed_official 87:085cde657901 1398 * @}
mbed_official 87:085cde657901 1399 */
mbed_official 87:085cde657901 1400
mbed_official 532:fe11edbda85c 1401 /** @defgroup ETH_Tx_DMA_Burst_Length ETH Tx DMA Burst Length
mbed_official 87:085cde657901 1402 * @{
mbed_official 87:085cde657901 1403 */
mbed_official 87:085cde657901 1404 #define ETH_TXDMABURSTLENGTH_1BEAT ((uint32_t)0x00000100) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
mbed_official 87:085cde657901 1405 #define ETH_TXDMABURSTLENGTH_2BEAT ((uint32_t)0x00000200) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
mbed_official 87:085cde657901 1406 #define ETH_TXDMABURSTLENGTH_4BEAT ((uint32_t)0x00000400) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
mbed_official 87:085cde657901 1407 #define ETH_TXDMABURSTLENGTH_8BEAT ((uint32_t)0x00000800) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
mbed_official 87:085cde657901 1408 #define ETH_TXDMABURSTLENGTH_16BEAT ((uint32_t)0x00001000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
mbed_official 87:085cde657901 1409 #define ETH_TXDMABURSTLENGTH_32BEAT ((uint32_t)0x00002000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
mbed_official 87:085cde657901 1410 #define ETH_TXDMABURSTLENGTH_4XPBL_4BEAT ((uint32_t)0x01000100) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
mbed_official 87:085cde657901 1411 #define ETH_TXDMABURSTLENGTH_4XPBL_8BEAT ((uint32_t)0x01000200) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
mbed_official 87:085cde657901 1412 #define ETH_TXDMABURSTLENGTH_4XPBL_16BEAT ((uint32_t)0x01000400) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
mbed_official 87:085cde657901 1413 #define ETH_TXDMABURSTLENGTH_4XPBL_32BEAT ((uint32_t)0x01000800) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
mbed_official 87:085cde657901 1414 #define ETH_TXDMABURSTLENGTH_4XPBL_64BEAT ((uint32_t)0x01001000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
mbed_official 87:085cde657901 1415 #define ETH_TXDMABURSTLENGTH_4XPBL_128BEAT ((uint32_t)0x01002000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
mbed_official 532:fe11edbda85c 1416 /**
mbed_official 532:fe11edbda85c 1417 * @}
mbed_official 532:fe11edbda85c 1418 */
mbed_official 87:085cde657901 1419
mbed_official 532:fe11edbda85c 1420 /** @defgroup ETH_DMA_Enhanced_descriptor_format ETH DMA Enhanced descriptor format
mbed_official 226:b062af740e40 1421 * @{
mbed_official 226:b062af740e40 1422 */
mbed_official 87:085cde657901 1423 #define ETH_DMAENHANCEDDESCRIPTOR_ENABLE ((uint32_t)0x00000080)
mbed_official 87:085cde657901 1424 #define ETH_DMAENHANCEDDESCRIPTOR_DISABLE ((uint32_t)0x00000000)
mbed_official 87:085cde657901 1425 /**
mbed_official 87:085cde657901 1426 * @}
mbed_official 87:085cde657901 1427 */
mbed_official 87:085cde657901 1428
mbed_official 532:fe11edbda85c 1429 /** @defgroup ETH_DMA_Arbitration ETH DMA Arbitration
mbed_official 87:085cde657901 1430 * @{
mbed_official 87:085cde657901 1431 */
mbed_official 87:085cde657901 1432 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1 ((uint32_t)0x00000000)
mbed_official 87:085cde657901 1433 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1 ((uint32_t)0x00004000)
mbed_official 87:085cde657901 1434 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1 ((uint32_t)0x00008000)
mbed_official 87:085cde657901 1435 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1 ((uint32_t)0x0000C000)
mbed_official 87:085cde657901 1436 #define ETH_DMAARBITRATION_RXPRIORTX ((uint32_t)0x00000002)
mbed_official 87:085cde657901 1437 /**
mbed_official 87:085cde657901 1438 * @}
mbed_official 87:085cde657901 1439 */
mbed_official 87:085cde657901 1440
mbed_official 532:fe11edbda85c 1441 /** @defgroup ETH_DMA_Tx_descriptor_segment ETH DMA Tx descriptor segment
mbed_official 87:085cde657901 1442 * @{
mbed_official 87:085cde657901 1443 */
mbed_official 532:fe11edbda85c 1444 #define ETH_DMATXDESC_LASTSEGMENTS ((uint32_t)0x40000000) /*!< Last Segment */
mbed_official 532:fe11edbda85c 1445 #define ETH_DMATXDESC_FIRSTSEGMENT ((uint32_t)0x20000000) /*!< First Segment */
mbed_official 87:085cde657901 1446 /**
mbed_official 87:085cde657901 1447 * @}
mbed_official 87:085cde657901 1448 */
mbed_official 87:085cde657901 1449
mbed_official 532:fe11edbda85c 1450 /** @defgroup ETH_DMA_Tx_descriptor_Checksum_Insertion_Control ETH DMA Tx descriptor Checksum Insertion Control
mbed_official 87:085cde657901 1451 * @{
mbed_official 87:085cde657901 1452 */
mbed_official 87:085cde657901 1453 #define ETH_DMATXDESC_CHECKSUMBYPASS ((uint32_t)0x00000000) /*!< Checksum engine bypass */
mbed_official 87:085cde657901 1454 #define ETH_DMATXDESC_CHECKSUMIPV4HEADER ((uint32_t)0x00400000) /*!< IPv4 header checksum insertion */
mbed_official 87:085cde657901 1455 #define ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT ((uint32_t)0x00800000) /*!< TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present */
mbed_official 87:085cde657901 1456 #define ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL ((uint32_t)0x00C00000) /*!< TCP/UDP/ICMP checksum fully in hardware including pseudo header */
mbed_official 87:085cde657901 1457 /**
mbed_official 87:085cde657901 1458 * @}
mbed_official 87:085cde657901 1459 */
mbed_official 87:085cde657901 1460
mbed_official 532:fe11edbda85c 1461 /** @defgroup ETH_DMA_Rx_descriptor_buffers ETH DMA Rx descriptor buffers
mbed_official 87:085cde657901 1462 * @{
mbed_official 87:085cde657901 1463 */
mbed_official 532:fe11edbda85c 1464 #define ETH_DMARXDESC_BUFFER1 ((uint32_t)0x00000000) /*!< DMA Rx Desc Buffer1 */
mbed_official 532:fe11edbda85c 1465 #define ETH_DMARXDESC_BUFFER2 ((uint32_t)0x00000001) /*!< DMA Rx Desc Buffer2 */
mbed_official 87:085cde657901 1466 /**
mbed_official 87:085cde657901 1467 * @}
mbed_official 87:085cde657901 1468 */
mbed_official 87:085cde657901 1469
mbed_official 532:fe11edbda85c 1470 /** @defgroup ETH_PMT_Flags ETH PMT Flags
mbed_official 87:085cde657901 1471 * @{
mbed_official 87:085cde657901 1472 */
mbed_official 87:085cde657901 1473 #define ETH_PMT_FLAG_WUFFRPR ((uint32_t)0x80000000) /*!< Wake-Up Frame Filter Register Pointer Reset */
mbed_official 87:085cde657901 1474 #define ETH_PMT_FLAG_WUFR ((uint32_t)0x00000040) /*!< Wake-Up Frame Received */
mbed_official 87:085cde657901 1475 #define ETH_PMT_FLAG_MPR ((uint32_t)0x00000020) /*!< Magic Packet Received */
mbed_official 87:085cde657901 1476 /**
mbed_official 87:085cde657901 1477 * @}
mbed_official 87:085cde657901 1478 */
mbed_official 87:085cde657901 1479
mbed_official 532:fe11edbda85c 1480 /** @defgroup ETH_MMC_Tx_Interrupts ETH MMC Tx Interrupts
mbed_official 87:085cde657901 1481 * @{
mbed_official 87:085cde657901 1482 */
mbed_official 87:085cde657901 1483 #define ETH_MMC_IT_TGF ((uint32_t)0x00200000) /*!< When Tx good frame counter reaches half the maximum value */
mbed_official 87:085cde657901 1484 #define ETH_MMC_IT_TGFMSC ((uint32_t)0x00008000) /*!< When Tx good multi col counter reaches half the maximum value */
mbed_official 87:085cde657901 1485 #define ETH_MMC_IT_TGFSC ((uint32_t)0x00004000) /*!< When Tx good single col counter reaches half the maximum value */
mbed_official 87:085cde657901 1486 /**
mbed_official 87:085cde657901 1487 * @}
mbed_official 87:085cde657901 1488 */
mbed_official 87:085cde657901 1489
mbed_official 532:fe11edbda85c 1490 /** @defgroup ETH_MMC_Rx_Interrupts ETH MMC Rx Interrupts
mbed_official 87:085cde657901 1491 * @{
mbed_official 87:085cde657901 1492 */
mbed_official 87:085cde657901 1493 #define ETH_MMC_IT_RGUF ((uint32_t)0x10020000) /*!< When Rx good unicast frames counter reaches half the maximum value */
mbed_official 87:085cde657901 1494 #define ETH_MMC_IT_RFAE ((uint32_t)0x10000040) /*!< When Rx alignment error counter reaches half the maximum value */
mbed_official 87:085cde657901 1495 #define ETH_MMC_IT_RFCE ((uint32_t)0x10000020) /*!< When Rx crc error counter reaches half the maximum value */
mbed_official 87:085cde657901 1496 /**
mbed_official 87:085cde657901 1497 * @}
mbed_official 87:085cde657901 1498 */
mbed_official 87:085cde657901 1499
mbed_official 532:fe11edbda85c 1500 /** @defgroup ETH_MAC_Flags ETH MAC Flags
mbed_official 87:085cde657901 1501 * @{
mbed_official 87:085cde657901 1502 */
mbed_official 87:085cde657901 1503 #define ETH_MAC_FLAG_TST ((uint32_t)0x00000200) /*!< Time stamp trigger flag (on MAC) */
mbed_official 87:085cde657901 1504 #define ETH_MAC_FLAG_MMCT ((uint32_t)0x00000040) /*!< MMC transmit flag */
mbed_official 87:085cde657901 1505 #define ETH_MAC_FLAG_MMCR ((uint32_t)0x00000020) /*!< MMC receive flag */
mbed_official 87:085cde657901 1506 #define ETH_MAC_FLAG_MMC ((uint32_t)0x00000010) /*!< MMC flag (on MAC) */
mbed_official 87:085cde657901 1507 #define ETH_MAC_FLAG_PMT ((uint32_t)0x00000008) /*!< PMT flag (on MAC) */
mbed_official 87:085cde657901 1508 /**
mbed_official 87:085cde657901 1509 * @}
mbed_official 87:085cde657901 1510 */
mbed_official 87:085cde657901 1511
mbed_official 532:fe11edbda85c 1512 /** @defgroup ETH_DMA_Flags ETH DMA Flags
mbed_official 87:085cde657901 1513 * @{
mbed_official 87:085cde657901 1514 */
mbed_official 87:085cde657901 1515 #define ETH_DMA_FLAG_TST ((uint32_t)0x20000000) /*!< Time-stamp trigger interrupt (on DMA) */
mbed_official 87:085cde657901 1516 #define ETH_DMA_FLAG_PMT ((uint32_t)0x10000000) /*!< PMT interrupt (on DMA) */
mbed_official 87:085cde657901 1517 #define ETH_DMA_FLAG_MMC ((uint32_t)0x08000000) /*!< MMC interrupt (on DMA) */
mbed_official 87:085cde657901 1518 #define ETH_DMA_FLAG_DATATRANSFERERROR ((uint32_t)0x00800000) /*!< Error bits 0-Rx DMA, 1-Tx DMA */
mbed_official 532:fe11edbda85c 1519 #define ETH_DMA_FLAG_READWRITEERROR ((uint32_t)0x01000000) /*!< Error bits 0-write transfer, 1-read transfer */
mbed_official 87:085cde657901 1520 #define ETH_DMA_FLAG_ACCESSERROR ((uint32_t)0x02000000) /*!< Error bits 0-data buffer, 1-desc. access */
mbed_official 87:085cde657901 1521 #define ETH_DMA_FLAG_NIS ((uint32_t)0x00010000) /*!< Normal interrupt summary flag */
mbed_official 87:085cde657901 1522 #define ETH_DMA_FLAG_AIS ((uint32_t)0x00008000) /*!< Abnormal interrupt summary flag */
mbed_official 87:085cde657901 1523 #define ETH_DMA_FLAG_ER ((uint32_t)0x00004000) /*!< Early receive flag */
mbed_official 87:085cde657901 1524 #define ETH_DMA_FLAG_FBE ((uint32_t)0x00002000) /*!< Fatal bus error flag */
mbed_official 87:085cde657901 1525 #define ETH_DMA_FLAG_ET ((uint32_t)0x00000400) /*!< Early transmit flag */
mbed_official 87:085cde657901 1526 #define ETH_DMA_FLAG_RWT ((uint32_t)0x00000200) /*!< Receive watchdog timeout flag */
mbed_official 87:085cde657901 1527 #define ETH_DMA_FLAG_RPS ((uint32_t)0x00000100) /*!< Receive process stopped flag */
mbed_official 87:085cde657901 1528 #define ETH_DMA_FLAG_RBU ((uint32_t)0x00000080) /*!< Receive buffer unavailable flag */
mbed_official 87:085cde657901 1529 #define ETH_DMA_FLAG_R ((uint32_t)0x00000040) /*!< Receive flag */
mbed_official 87:085cde657901 1530 #define ETH_DMA_FLAG_TU ((uint32_t)0x00000020) /*!< Underflow flag */
mbed_official 87:085cde657901 1531 #define ETH_DMA_FLAG_RO ((uint32_t)0x00000010) /*!< Overflow flag */
mbed_official 87:085cde657901 1532 #define ETH_DMA_FLAG_TJT ((uint32_t)0x00000008) /*!< Transmit jabber timeout flag */
mbed_official 87:085cde657901 1533 #define ETH_DMA_FLAG_TBU ((uint32_t)0x00000004) /*!< Transmit buffer unavailable flag */
mbed_official 87:085cde657901 1534 #define ETH_DMA_FLAG_TPS ((uint32_t)0x00000002) /*!< Transmit process stopped flag */
mbed_official 87:085cde657901 1535 #define ETH_DMA_FLAG_T ((uint32_t)0x00000001) /*!< Transmit flag */
mbed_official 87:085cde657901 1536 /**
mbed_official 87:085cde657901 1537 * @}
mbed_official 87:085cde657901 1538 */
mbed_official 87:085cde657901 1539
mbed_official 532:fe11edbda85c 1540 /** @defgroup ETH_MAC_Interrupts ETH MAC Interrupts
mbed_official 87:085cde657901 1541 * @{
mbed_official 87:085cde657901 1542 */
mbed_official 87:085cde657901 1543 #define ETH_MAC_IT_TST ((uint32_t)0x00000200) /*!< Time stamp trigger interrupt (on MAC) */
mbed_official 87:085cde657901 1544 #define ETH_MAC_IT_MMCT ((uint32_t)0x00000040) /*!< MMC transmit interrupt */
mbed_official 87:085cde657901 1545 #define ETH_MAC_IT_MMCR ((uint32_t)0x00000020) /*!< MMC receive interrupt */
mbed_official 87:085cde657901 1546 #define ETH_MAC_IT_MMC ((uint32_t)0x00000010) /*!< MMC interrupt (on MAC) */
mbed_official 87:085cde657901 1547 #define ETH_MAC_IT_PMT ((uint32_t)0x00000008) /*!< PMT interrupt (on MAC) */
mbed_official 87:085cde657901 1548 /**
mbed_official 87:085cde657901 1549 * @}
mbed_official 87:085cde657901 1550 */
mbed_official 87:085cde657901 1551
mbed_official 532:fe11edbda85c 1552 /** @defgroup ETH_DMA_Interrupts ETH DMA Interrupts
mbed_official 87:085cde657901 1553 * @{
mbed_official 87:085cde657901 1554 */
mbed_official 87:085cde657901 1555 #define ETH_DMA_IT_TST ((uint32_t)0x20000000) /*!< Time-stamp trigger interrupt (on DMA) */
mbed_official 87:085cde657901 1556 #define ETH_DMA_IT_PMT ((uint32_t)0x10000000) /*!< PMT interrupt (on DMA) */
mbed_official 87:085cde657901 1557 #define ETH_DMA_IT_MMC ((uint32_t)0x08000000) /*!< MMC interrupt (on DMA) */
mbed_official 87:085cde657901 1558 #define ETH_DMA_IT_NIS ((uint32_t)0x00010000) /*!< Normal interrupt summary */
mbed_official 87:085cde657901 1559 #define ETH_DMA_IT_AIS ((uint32_t)0x00008000) /*!< Abnormal interrupt summary */
mbed_official 87:085cde657901 1560 #define ETH_DMA_IT_ER ((uint32_t)0x00004000) /*!< Early receive interrupt */
mbed_official 87:085cde657901 1561 #define ETH_DMA_IT_FBE ((uint32_t)0x00002000) /*!< Fatal bus error interrupt */
mbed_official 87:085cde657901 1562 #define ETH_DMA_IT_ET ((uint32_t)0x00000400) /*!< Early transmit interrupt */
mbed_official 87:085cde657901 1563 #define ETH_DMA_IT_RWT ((uint32_t)0x00000200) /*!< Receive watchdog timeout interrupt */
mbed_official 87:085cde657901 1564 #define ETH_DMA_IT_RPS ((uint32_t)0x00000100) /*!< Receive process stopped interrupt */
mbed_official 87:085cde657901 1565 #define ETH_DMA_IT_RBU ((uint32_t)0x00000080) /*!< Receive buffer unavailable interrupt */
mbed_official 87:085cde657901 1566 #define ETH_DMA_IT_R ((uint32_t)0x00000040) /*!< Receive interrupt */
mbed_official 87:085cde657901 1567 #define ETH_DMA_IT_TU ((uint32_t)0x00000020) /*!< Underflow interrupt */
mbed_official 87:085cde657901 1568 #define ETH_DMA_IT_RO ((uint32_t)0x00000010) /*!< Overflow interrupt */
mbed_official 87:085cde657901 1569 #define ETH_DMA_IT_TJT ((uint32_t)0x00000008) /*!< Transmit jabber timeout interrupt */
mbed_official 87:085cde657901 1570 #define ETH_DMA_IT_TBU ((uint32_t)0x00000004) /*!< Transmit buffer unavailable interrupt */
mbed_official 87:085cde657901 1571 #define ETH_DMA_IT_TPS ((uint32_t)0x00000002) /*!< Transmit process stopped interrupt */
mbed_official 87:085cde657901 1572 #define ETH_DMA_IT_T ((uint32_t)0x00000001) /*!< Transmit interrupt */
mbed_official 87:085cde657901 1573 /**
mbed_official 87:085cde657901 1574 * @}
mbed_official 87:085cde657901 1575 */
mbed_official 87:085cde657901 1576
mbed_official 532:fe11edbda85c 1577 /** @defgroup ETH_DMA_transmit_process_state ETH DMA transmit process state
mbed_official 87:085cde657901 1578 * @{
mbed_official 87:085cde657901 1579 */
mbed_official 87:085cde657901 1580 #define ETH_DMA_TRANSMITPROCESS_STOPPED ((uint32_t)0x00000000) /*!< Stopped - Reset or Stop Tx Command issued */
mbed_official 87:085cde657901 1581 #define ETH_DMA_TRANSMITPROCESS_FETCHING ((uint32_t)0x00100000) /*!< Running - fetching the Tx descriptor */
mbed_official 87:085cde657901 1582 #define ETH_DMA_TRANSMITPROCESS_WAITING ((uint32_t)0x00200000) /*!< Running - waiting for status */
mbed_official 87:085cde657901 1583 #define ETH_DMA_TRANSMITPROCESS_READING ((uint32_t)0x00300000) /*!< Running - reading the data from host memory */
mbed_official 87:085cde657901 1584 #define ETH_DMA_TRANSMITPROCESS_SUSPENDED ((uint32_t)0x00600000) /*!< Suspended - Tx Descriptor unavailable */
mbed_official 87:085cde657901 1585 #define ETH_DMA_TRANSMITPROCESS_CLOSING ((uint32_t)0x00700000) /*!< Running - closing Rx descriptor */
mbed_official 87:085cde657901 1586
mbed_official 87:085cde657901 1587 /**
mbed_official 87:085cde657901 1588 * @}
mbed_official 87:085cde657901 1589 */
mbed_official 87:085cde657901 1590
mbed_official 87:085cde657901 1591
mbed_official 532:fe11edbda85c 1592 /** @defgroup ETH_DMA_receive_process_state ETH DMA receive process state
mbed_official 87:085cde657901 1593 * @{
mbed_official 87:085cde657901 1594 */
mbed_official 87:085cde657901 1595 #define ETH_DMA_RECEIVEPROCESS_STOPPED ((uint32_t)0x00000000) /*!< Stopped - Reset or Stop Rx Command issued */
mbed_official 87:085cde657901 1596 #define ETH_DMA_RECEIVEPROCESS_FETCHING ((uint32_t)0x00020000) /*!< Running - fetching the Rx descriptor */
mbed_official 87:085cde657901 1597 #define ETH_DMA_RECEIVEPROCESS_WAITING ((uint32_t)0x00060000) /*!< Running - waiting for packet */
mbed_official 87:085cde657901 1598 #define ETH_DMA_RECEIVEPROCESS_SUSPENDED ((uint32_t)0x00080000) /*!< Suspended - Rx Descriptor unavailable */
mbed_official 87:085cde657901 1599 #define ETH_DMA_RECEIVEPROCESS_CLOSING ((uint32_t)0x000A0000) /*!< Running - closing descriptor */
mbed_official 87:085cde657901 1600 #define ETH_DMA_RECEIVEPROCESS_QUEUING ((uint32_t)0x000E0000) /*!< Running - queuing the receive frame into host memory */
mbed_official 87:085cde657901 1601
mbed_official 87:085cde657901 1602 /**
mbed_official 87:085cde657901 1603 * @}
mbed_official 87:085cde657901 1604 */
mbed_official 87:085cde657901 1605
mbed_official 532:fe11edbda85c 1606 /** @defgroup ETH_DMA_overflow ETH DMA overflow
mbed_official 87:085cde657901 1607 * @{
mbed_official 87:085cde657901 1608 */
mbed_official 87:085cde657901 1609 #define ETH_DMA_OVERFLOW_RXFIFOCOUNTER ((uint32_t)0x10000000) /*!< Overflow bit for FIFO overflow counter */
mbed_official 87:085cde657901 1610 #define ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER ((uint32_t)0x00010000) /*!< Overflow bit for missed frame counter */
mbed_official 87:085cde657901 1611 /**
mbed_official 87:085cde657901 1612 * @}
mbed_official 87:085cde657901 1613 */
mbed_official 87:085cde657901 1614
mbed_official 532:fe11edbda85c 1615 /** @defgroup ETH_EXTI_LINE_WAKEUP ETH EXTI LINE WAKEUP
mbed_official 532:fe11edbda85c 1616 * @{
mbed_official 532:fe11edbda85c 1617 */
mbed_official 532:fe11edbda85c 1618 #define ETH_EXTI_LINE_WAKEUP ((uint32_t)0x00080000) /*!< External interrupt line 19 Connected to the ETH EXTI Line */
mbed_official 87:085cde657901 1619
mbed_official 532:fe11edbda85c 1620 /**
mbed_official 532:fe11edbda85c 1621 * @}
mbed_official 532:fe11edbda85c 1622 */
mbed_official 87:085cde657901 1623
mbed_official 87:085cde657901 1624 /**
mbed_official 87:085cde657901 1625 * @}
mbed_official 87:085cde657901 1626 */
mbed_official 87:085cde657901 1627
mbed_official 87:085cde657901 1628 /* Exported macro ------------------------------------------------------------*/
mbed_official 532:fe11edbda85c 1629 /** @defgroup ETH_Exported_Macros ETH Exported Macros
mbed_official 532:fe11edbda85c 1630 * @brief macros to handle interrupts and specific clock configurations
mbed_official 532:fe11edbda85c 1631 * @{
mbed_official 532:fe11edbda85c 1632 */
mbed_official 532:fe11edbda85c 1633
mbed_official 226:b062af740e40 1634 /** @brief Reset ETH handle state
mbed_official 226:b062af740e40 1635 * @param __HANDLE__: specifies the ETH handle.
mbed_official 226:b062af740e40 1636 * @retval None
mbed_official 226:b062af740e40 1637 */
mbed_official 226:b062af740e40 1638 #define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ETH_STATE_RESET)
mbed_official 226:b062af740e40 1639
mbed_official 87:085cde657901 1640 /**
mbed_official 87:085cde657901 1641 * @brief Checks whether the specified ETHERNET DMA Tx Desc flag is set or not.
mbed_official 87:085cde657901 1642 * @param __HANDLE__: ETH Handle
mbed_official 532:fe11edbda85c 1643 * @param __FLAG__: specifies the flag of TDES0 to check.
mbed_official 87:085cde657901 1644 * @retval the ETH_DMATxDescFlag (SET or RESET).
mbed_official 87:085cde657901 1645 */
mbed_official 87:085cde657901 1646 #define __HAL_ETH_DMATXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->TxDesc->Status & (__FLAG__) == (__FLAG__))
mbed_official 87:085cde657901 1647
mbed_official 87:085cde657901 1648 /**
mbed_official 87:085cde657901 1649 * @brief Checks whether the specified ETHERNET DMA Rx Desc flag is set or not.
mbed_official 87:085cde657901 1650 * @param __HANDLE__: ETH Handle
mbed_official 532:fe11edbda85c 1651 * @param __FLAG__: specifies the flag of RDES0 to check.
mbed_official 87:085cde657901 1652 * @retval the ETH_DMATxDescFlag (SET or RESET).
mbed_official 87:085cde657901 1653 */
mbed_official 87:085cde657901 1654 #define __HAL_ETH_DMARXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->RxDesc->Status & (__FLAG__) == (__FLAG__))
mbed_official 87:085cde657901 1655
mbed_official 87:085cde657901 1656 /**
mbed_official 87:085cde657901 1657 * @brief Enables the specified DMA Rx Desc receive interrupt.
mbed_official 87:085cde657901 1658 * @param __HANDLE__: ETH Handle
mbed_official 87:085cde657901 1659 * @retval None
mbed_official 87:085cde657901 1660 */
mbed_official 87:085cde657901 1661 #define __HAL_ETH_DMARXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARXDESC_DIC))
mbed_official 87:085cde657901 1662
mbed_official 87:085cde657901 1663 /**
mbed_official 87:085cde657901 1664 * @brief Disables the specified DMA Rx Desc receive interrupt.
mbed_official 87:085cde657901 1665 * @param __HANDLE__: ETH Handle
mbed_official 87:085cde657901 1666 * @retval None
mbed_official 87:085cde657901 1667 */
mbed_official 87:085cde657901 1668 #define __HAL_ETH_DMARXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize |= ETH_DMARXDESC_DIC)
mbed_official 87:085cde657901 1669
mbed_official 87:085cde657901 1670 /**
mbed_official 87:085cde657901 1671 * @brief Set the specified DMA Rx Desc Own bit.
mbed_official 87:085cde657901 1672 * @param __HANDLE__: ETH Handle
mbed_official 87:085cde657901 1673 * @retval None
mbed_official 87:085cde657901 1674 */
mbed_official 87:085cde657901 1675 #define __HAL_ETH_DMARXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->RxDesc->Status |= ETH_DMARXDESC_OWN)
mbed_official 87:085cde657901 1676
mbed_official 87:085cde657901 1677 /**
mbed_official 87:085cde657901 1678 * @brief Returns the specified ETHERNET DMA Tx Desc collision count.
mbed_official 87:085cde657901 1679 * @param __HANDLE__: ETH Handle
mbed_official 87:085cde657901 1680 * @retval The Transmit descriptor collision counter value.
mbed_official 87:085cde657901 1681 */
mbed_official 87:085cde657901 1682 #define __HAL_ETH_DMATXDESC_GET_COLLISION_COUNT(__HANDLE__) (((__HANDLE__)->TxDesc->Status & ETH_DMATXDESC_CC) >> ETH_DMATXDESC_COLLISION_COUNTSHIFT)
mbed_official 87:085cde657901 1683
mbed_official 87:085cde657901 1684 /**
mbed_official 87:085cde657901 1685 * @brief Set the specified DMA Tx Desc Own bit.
mbed_official 87:085cde657901 1686 * @param __HANDLE__: ETH Handle
mbed_official 87:085cde657901 1687 * @retval None
mbed_official 87:085cde657901 1688 */
mbed_official 87:085cde657901 1689 #define __HAL_ETH_DMATXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_OWN)
mbed_official 87:085cde657901 1690
mbed_official 87:085cde657901 1691 /**
mbed_official 87:085cde657901 1692 * @brief Enables the specified DMA Tx Desc Transmit interrupt.
mbed_official 87:085cde657901 1693 * @param __HANDLE__: ETH Handle
mbed_official 87:085cde657901 1694 * @retval None
mbed_official 87:085cde657901 1695 */
mbed_official 87:085cde657901 1696 #define __HAL_ETH_DMATXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_IC)
mbed_official 87:085cde657901 1697
mbed_official 87:085cde657901 1698 /**
mbed_official 87:085cde657901 1699 * @brief Disables the specified DMA Tx Desc Transmit interrupt.
mbed_official 87:085cde657901 1700 * @param __HANDLE__: ETH Handle
mbed_official 87:085cde657901 1701 * @retval None
mbed_official 87:085cde657901 1702 */
mbed_official 87:085cde657901 1703 #define __HAL_ETH_DMATXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_IC)
mbed_official 87:085cde657901 1704
mbed_official 87:085cde657901 1705 /**
mbed_official 87:085cde657901 1706 * @brief Selects the specified ETHERNET DMA Tx Desc Checksum Insertion.
mbed_official 87:085cde657901 1707 * @param __HANDLE__: ETH Handle
mbed_official 87:085cde657901 1708 * @param __CHECKSUM__: specifies is the DMA Tx desc checksum insertion.
mbed_official 87:085cde657901 1709 * This parameter can be one of the following values:
mbed_official 87:085cde657901 1710 * @arg ETH_DMATXDESC_CHECKSUMBYPASS : Checksum bypass
mbed_official 87:085cde657901 1711 * @arg ETH_DMATXDESC_CHECKSUMIPV4HEADER : IPv4 header checksum
mbed_official 87:085cde657901 1712 * @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT : TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present
mbed_official 87:085cde657901 1713 * @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL : TCP/UDP/ICMP checksum fully in hardware including pseudo header
mbed_official 87:085cde657901 1714 * @retval None
mbed_official 87:085cde657901 1715 */
mbed_official 87:085cde657901 1716 #define __HAL_ETH_DMATXDESC_CHECKSUM_INSERTION(__HANDLE__, __CHECKSUM__) ((__HANDLE__)->TxDesc->Status |= (__CHECKSUM__))
mbed_official 87:085cde657901 1717
mbed_official 87:085cde657901 1718 /**
mbed_official 87:085cde657901 1719 * @brief Enables the DMA Tx Desc CRC.
mbed_official 87:085cde657901 1720 * @param __HANDLE__: ETH Handle
mbed_official 87:085cde657901 1721 * @retval None
mbed_official 87:085cde657901 1722 */
mbed_official 87:085cde657901 1723 #define __HAL_ETH_DMATXDESC_CRC_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DC)
mbed_official 87:085cde657901 1724
mbed_official 87:085cde657901 1725 /**
mbed_official 87:085cde657901 1726 * @brief Disables the DMA Tx Desc CRC.
mbed_official 87:085cde657901 1727 * @param __HANDLE__: ETH Handle
mbed_official 87:085cde657901 1728 * @retval None
mbed_official 87:085cde657901 1729 */
mbed_official 87:085cde657901 1730 #define __HAL_ETH_DMATXDESC_CRC_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DC)
mbed_official 87:085cde657901 1731
mbed_official 87:085cde657901 1732 /**
mbed_official 87:085cde657901 1733 * @brief Enables the DMA Tx Desc padding for frame shorter than 64 bytes.
mbed_official 87:085cde657901 1734 * @param __HANDLE__: ETH Handle
mbed_official 87:085cde657901 1735 * @retval None
mbed_official 87:085cde657901 1736 */
mbed_official 87:085cde657901 1737 #define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DP)
mbed_official 87:085cde657901 1738
mbed_official 87:085cde657901 1739 /**
mbed_official 87:085cde657901 1740 * @brief Disables the DMA Tx Desc padding for frame shorter than 64 bytes.
mbed_official 87:085cde657901 1741 * @param __HANDLE__: ETH Handle
mbed_official 87:085cde657901 1742 * @retval None
mbed_official 87:085cde657901 1743 */
mbed_official 87:085cde657901 1744 #define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DP)
mbed_official 87:085cde657901 1745
mbed_official 87:085cde657901 1746 /**
mbed_official 87:085cde657901 1747 * @brief Enables the specified ETHERNET MAC interrupts.
mbed_official 87:085cde657901 1748 * @param __HANDLE__ : ETH Handle
mbed_official 87:085cde657901 1749 * @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be
mbed_official 87:085cde657901 1750 * enabled or disabled.
mbed_official 87:085cde657901 1751 * This parameter can be any combination of the following values:
mbed_official 87:085cde657901 1752 * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt
mbed_official 87:085cde657901 1753 * @arg ETH_MAC_IT_PMT : PMT interrupt
mbed_official 87:085cde657901 1754 * @retval None
mbed_official 87:085cde657901 1755 */
mbed_official 87:085cde657901 1756 #define __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR |= (__INTERRUPT__))
mbed_official 87:085cde657901 1757
mbed_official 87:085cde657901 1758 /**
mbed_official 87:085cde657901 1759 * @brief Disables the specified ETHERNET MAC interrupts.
mbed_official 87:085cde657901 1760 * @param __HANDLE__ : ETH Handle
mbed_official 87:085cde657901 1761 * @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be
mbed_official 87:085cde657901 1762 * enabled or disabled.
mbed_official 87:085cde657901 1763 * This parameter can be any combination of the following values:
mbed_official 87:085cde657901 1764 * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt
mbed_official 87:085cde657901 1765 * @arg ETH_MAC_IT_PMT : PMT interrupt
mbed_official 87:085cde657901 1766 * @retval None
mbed_official 87:085cde657901 1767 */
mbed_official 87:085cde657901 1768 #define __HAL_ETH_MAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR &= ~(__INTERRUPT__))
mbed_official 87:085cde657901 1769
mbed_official 87:085cde657901 1770 /**
mbed_official 87:085cde657901 1771 * @brief Initiate a Pause Control Frame (Full-duplex only).
mbed_official 87:085cde657901 1772 * @param __HANDLE__: ETH Handle
mbed_official 87:085cde657901 1773 * @retval None
mbed_official 87:085cde657901 1774 */
mbed_official 87:085cde657901 1775 #define __HAL_ETH_INITIATE_PAUSE_CONTROL_FRAME(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA)
mbed_official 87:085cde657901 1776
mbed_official 87:085cde657901 1777 /**
mbed_official 87:085cde657901 1778 * @brief Checks whether the ETHERNET flow control busy bit is set or not.
mbed_official 87:085cde657901 1779 * @param __HANDLE__: ETH Handle
mbed_official 87:085cde657901 1780 * @retval The new state of flow control busy status bit (SET or RESET).
mbed_official 87:085cde657901 1781 */
mbed_official 87:085cde657901 1782 #define __HAL_ETH_GET_FLOW_CONTROL_BUSY_STATUS(__HANDLE__) (((__HANDLE__)->Instance->MACFCR & ETH_MACFCR_FCBBPA) == ETH_MACFCR_FCBBPA)
mbed_official 87:085cde657901 1783
mbed_official 87:085cde657901 1784 /**
mbed_official 87:085cde657901 1785 * @brief Enables the MAC Back Pressure operation activation (Half-duplex only).
mbed_official 87:085cde657901 1786 * @param __HANDLE__: ETH Handle
mbed_official 87:085cde657901 1787 * @retval None
mbed_official 87:085cde657901 1788 */
mbed_official 87:085cde657901 1789 #define __HAL_ETH_BACK_PRESSURE_ACTIVATION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA)
mbed_official 87:085cde657901 1790
mbed_official 87:085cde657901 1791 /**
mbed_official 87:085cde657901 1792 * @brief Disables the MAC BackPressure operation activation (Half-duplex only).
mbed_official 87:085cde657901 1793 * @param __HANDLE__: ETH Handle
mbed_official 87:085cde657901 1794 * @retval None
mbed_official 87:085cde657901 1795 */
mbed_official 87:085cde657901 1796 #define __HAL_ETH_BACK_PRESSURE_ACTIVATION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR &= ~ETH_MACFCR_FCBBPA)
mbed_official 87:085cde657901 1797
mbed_official 87:085cde657901 1798 /**
mbed_official 87:085cde657901 1799 * @brief Checks whether the specified ETHERNET MAC flag is set or not.
mbed_official 87:085cde657901 1800 * @param __HANDLE__: ETH Handle
mbed_official 87:085cde657901 1801 * @param __FLAG__: specifies the flag to check.
mbed_official 87:085cde657901 1802 * This parameter can be one of the following values:
mbed_official 87:085cde657901 1803 * @arg ETH_MAC_FLAG_TST : Time stamp trigger flag
mbed_official 87:085cde657901 1804 * @arg ETH_MAC_FLAG_MMCT : MMC transmit flag
mbed_official 87:085cde657901 1805 * @arg ETH_MAC_FLAG_MMCR : MMC receive flag
mbed_official 87:085cde657901 1806 * @arg ETH_MAC_FLAG_MMC : MMC flag
mbed_official 87:085cde657901 1807 * @arg ETH_MAC_FLAG_PMT : PMT flag
mbed_official 87:085cde657901 1808 * @retval The state of ETHERNET MAC flag.
mbed_official 87:085cde657901 1809 */
mbed_official 87:085cde657901 1810 #define __HAL_ETH_MAC_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACSR &( __FLAG__)) == ( __FLAG__))
mbed_official 87:085cde657901 1811
mbed_official 87:085cde657901 1812 /**
mbed_official 87:085cde657901 1813 * @brief Enables the specified ETHERNET DMA interrupts.
mbed_official 87:085cde657901 1814 * @param __HANDLE__ : ETH Handle
mbed_official 87:085cde657901 1815 * @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be
mbed_official 532:fe11edbda85c 1816 * enabled @ref ETH_DMA_Interrupts
mbed_official 87:085cde657901 1817 * @retval None
mbed_official 87:085cde657901 1818 */
mbed_official 87:085cde657901 1819 #define __HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER |= (__INTERRUPT__))
mbed_official 87:085cde657901 1820
mbed_official 87:085cde657901 1821 /**
mbed_official 87:085cde657901 1822 * @brief Disables the specified ETHERNET DMA interrupts.
mbed_official 87:085cde657901 1823 * @param __HANDLE__ : ETH Handle
mbed_official 87:085cde657901 1824 * @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be
mbed_official 532:fe11edbda85c 1825 * disabled. @ref ETH_DMA_Interrupts
mbed_official 87:085cde657901 1826 * @retval None
mbed_official 87:085cde657901 1827 */
mbed_official 87:085cde657901 1828 #define __HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER &= ~(__INTERRUPT__))
mbed_official 87:085cde657901 1829
mbed_official 87:085cde657901 1830 /**
mbed_official 87:085cde657901 1831 * @brief Clears the ETHERNET DMA IT pending bit.
mbed_official 87:085cde657901 1832 * @param __HANDLE__ : ETH Handle
mbed_official 532:fe11edbda85c 1833 * @param __INTERRUPT__: specifies the interrupt pending bit to clear. @ref ETH_DMA_Interrupts
mbed_official 87:085cde657901 1834 * @retval None
mbed_official 87:085cde657901 1835 */
mbed_official 106:ced8cbb51063 1836 #define __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMASR =(__INTERRUPT__))
mbed_official 87:085cde657901 1837
mbed_official 87:085cde657901 1838 /**
mbed_official 87:085cde657901 1839 * @brief Checks whether the specified ETHERNET DMA flag is set or not.
mbed_official 87:085cde657901 1840 * @param __HANDLE__: ETH Handle
mbed_official 532:fe11edbda85c 1841 * @param __FLAG__: specifies the flag to check. @ref ETH_DMA_Flags
mbed_official 87:085cde657901 1842 * @retval The new state of ETH_DMA_FLAG (SET or RESET).
mbed_official 87:085cde657901 1843 */
mbed_official 87:085cde657901 1844 #define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->DMASR &( __FLAG__)) == ( __FLAG__))
mbed_official 87:085cde657901 1845
mbed_official 87:085cde657901 1846 /**
mbed_official 87:085cde657901 1847 * @brief Checks whether the specified ETHERNET DMA flag is set or not.
mbed_official 87:085cde657901 1848 * @param __HANDLE__: ETH Handle
mbed_official 532:fe11edbda85c 1849 * @param __FLAG__: specifies the flag to clear. @ref ETH_DMA_Flags
mbed_official 87:085cde657901 1850 * @retval The new state of ETH_DMA_FLAG (SET or RESET).
mbed_official 87:085cde657901 1851 */
mbed_official 369:2e96f1b71984 1852 #define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->DMASR = (__FLAG__))
mbed_official 87:085cde657901 1853
mbed_official 87:085cde657901 1854 /**
mbed_official 87:085cde657901 1855 * @brief Checks whether the specified ETHERNET DMA overflow flag is set or not.
mbed_official 87:085cde657901 1856 * @param __HANDLE__: ETH Handle
mbed_official 87:085cde657901 1857 * @param __OVERFLOW__: specifies the DMA overflow flag to check.
mbed_official 87:085cde657901 1858 * This parameter can be one of the following values:
mbed_official 87:085cde657901 1859 * @arg ETH_DMA_OVERFLOW_RXFIFOCOUNTER : Overflow for FIFO Overflows Counter
mbed_official 87:085cde657901 1860 * @arg ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER : Overflow for Buffer Unavailable Missed Frame Counter
mbed_official 87:085cde657901 1861 * @retval The state of ETHERNET DMA overflow Flag (SET or RESET).
mbed_official 87:085cde657901 1862 */
mbed_official 87:085cde657901 1863 #define __HAL_ETH_GET_DMA_OVERFLOW_STATUS(__HANDLE__, __OVERFLOW__) (((__HANDLE__)->Instance->DMAMFBOCR & (__OVERFLOW__)) == (__OVERFLOW__))
mbed_official 87:085cde657901 1864
mbed_official 87:085cde657901 1865 /**
mbed_official 87:085cde657901 1866 * @brief Set the DMA Receive status watchdog timer register value
mbed_official 87:085cde657901 1867 * @param __HANDLE__: ETH Handle
mbed_official 87:085cde657901 1868 * @param __VALUE__: DMA Receive status watchdog timer register value
mbed_official 87:085cde657901 1869 * @retval None
mbed_official 87:085cde657901 1870 */
mbed_official 87:085cde657901 1871 #define __HAL_ETH_SET_RECEIVE_WATCHDOG_TIMER(__HANDLE__, __VALUE__) ((__HANDLE__)->Instance->DMARSWTR = (__VALUE__))
mbed_official 87:085cde657901 1872
mbed_official 87:085cde657901 1873 /**
mbed_official 87:085cde657901 1874 * @brief Enables any unicast packet filtered by the MAC address
mbed_official 87:085cde657901 1875 * recognition to be a wake-up frame.
mbed_official 87:085cde657901 1876 * @param __HANDLE__: ETH Handle.
mbed_official 87:085cde657901 1877 * @retval None
mbed_official 87:085cde657901 1878 */
mbed_official 87:085cde657901 1879 #define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_GU)
mbed_official 87:085cde657901 1880
mbed_official 87:085cde657901 1881 /**
mbed_official 87:085cde657901 1882 * @brief Disables any unicast packet filtered by the MAC address
mbed_official 87:085cde657901 1883 * recognition to be a wake-up frame.
mbed_official 87:085cde657901 1884 * @param __HANDLE__: ETH Handle.
mbed_official 87:085cde657901 1885 * @retval None
mbed_official 87:085cde657901 1886 */
mbed_official 87:085cde657901 1887 #define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_GU)
mbed_official 87:085cde657901 1888
mbed_official 87:085cde657901 1889 /**
mbed_official 87:085cde657901 1890 * @brief Enables the MAC Wake-Up Frame Detection.
mbed_official 87:085cde657901 1891 * @param __HANDLE__: ETH Handle.
mbed_official 87:085cde657901 1892 * @retval None
mbed_official 87:085cde657901 1893 */
mbed_official 87:085cde657901 1894 #define __HAL_ETH_WAKEUP_FRAME_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_WFE)
mbed_official 87:085cde657901 1895
mbed_official 87:085cde657901 1896 /**
mbed_official 87:085cde657901 1897 * @brief Disables the MAC Wake-Up Frame Detection.
mbed_official 87:085cde657901 1898 * @param __HANDLE__: ETH Handle.
mbed_official 87:085cde657901 1899 * @retval None
mbed_official 87:085cde657901 1900 */
mbed_official 87:085cde657901 1901 #define __HAL_ETH_WAKEUP_FRAME_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)
mbed_official 87:085cde657901 1902
mbed_official 87:085cde657901 1903 /**
mbed_official 87:085cde657901 1904 * @brief Enables the MAC Magic Packet Detection.
mbed_official 87:085cde657901 1905 * @param __HANDLE__: ETH Handle.
mbed_official 87:085cde657901 1906 * @retval None
mbed_official 87:085cde657901 1907 */
mbed_official 87:085cde657901 1908 #define __HAL_ETH_MAGIC_PACKET_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_MPE)
mbed_official 87:085cde657901 1909
mbed_official 87:085cde657901 1910 /**
mbed_official 87:085cde657901 1911 * @brief Disables the MAC Magic Packet Detection.
mbed_official 87:085cde657901 1912 * @param __HANDLE__: ETH Handle.
mbed_official 87:085cde657901 1913 * @retval None
mbed_official 87:085cde657901 1914 */
mbed_official 87:085cde657901 1915 #define __HAL_ETH_MAGIC_PACKET_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)
mbed_official 87:085cde657901 1916
mbed_official 87:085cde657901 1917 /**
mbed_official 87:085cde657901 1918 * @brief Enables the MAC Power Down.
mbed_official 87:085cde657901 1919 * @param __HANDLE__: ETH Handle
mbed_official 87:085cde657901 1920 * @retval None
mbed_official 87:085cde657901 1921 */
mbed_official 87:085cde657901 1922 #define __HAL_ETH_POWER_DOWN_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_PD)
mbed_official 87:085cde657901 1923
mbed_official 87:085cde657901 1924 /**
mbed_official 87:085cde657901 1925 * @brief Disables the MAC Power Down.
mbed_official 87:085cde657901 1926 * @param __HANDLE__: ETH Handle
mbed_official 87:085cde657901 1927 * @retval None
mbed_official 87:085cde657901 1928 */
mbed_official 87:085cde657901 1929 #define __HAL_ETH_POWER_DOWN_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_PD)
mbed_official 87:085cde657901 1930
mbed_official 87:085cde657901 1931 /**
mbed_official 87:085cde657901 1932 * @brief Checks whether the specified ETHERNET PMT flag is set or not.
mbed_official 87:085cde657901 1933 * @param __HANDLE__: ETH Handle.
mbed_official 87:085cde657901 1934 * @param __FLAG__: specifies the flag to check.
mbed_official 87:085cde657901 1935 * This parameter can be one of the following values:
mbed_official 87:085cde657901 1936 * @arg ETH_PMT_FLAG_WUFFRPR : Wake-Up Frame Filter Register Pointer Reset
mbed_official 87:085cde657901 1937 * @arg ETH_PMT_FLAG_WUFR : Wake-Up Frame Received
mbed_official 87:085cde657901 1938 * @arg ETH_PMT_FLAG_MPR : Magic Packet Received
mbed_official 87:085cde657901 1939 * @retval The new state of ETHERNET PMT Flag (SET or RESET).
mbed_official 87:085cde657901 1940 */
mbed_official 87:085cde657901 1941 #define __HAL_ETH_GET_PMT_FLAG_STATUS(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACPMTCSR &( __FLAG__)) == ( __FLAG__))
mbed_official 87:085cde657901 1942
mbed_official 87:085cde657901 1943 /**
mbed_official 87:085cde657901 1944 * @brief Preset and Initialize the MMC counters to almost-full value: 0xFFFF_FFF0 (full - 16)
mbed_official 87:085cde657901 1945 * @param __HANDLE__: ETH Handle.
mbed_official 87:085cde657901 1946 * @retval None
mbed_official 87:085cde657901 1947 */
mbed_official 87:085cde657901 1948 #define __HAL_ETH_MMC_COUNTER_FULL_PRESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= (ETH_MMCCR_MCFHP | ETH_MMCCR_MCP))
mbed_official 87:085cde657901 1949
mbed_official 87:085cde657901 1950 /**
mbed_official 87:085cde657901 1951 * @brief Preset and Initialize the MMC counters to almost-half value: 0x7FFF_FFF0 (half - 16)
mbed_official 87:085cde657901 1952 * @param __HANDLE__: ETH Handle.
mbed_official 87:085cde657901 1953 * @retval None
mbed_official 87:085cde657901 1954 */
mbed_official 87:085cde657901 1955 #define __HAL_ETH_MMC_COUNTER_HALF_PRESET(__HANDLE__) do{(__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCFHP;\
mbed_official 87:085cde657901 1956 (__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCP;} while (0)
mbed_official 87:085cde657901 1957
mbed_official 87:085cde657901 1958 /**
mbed_official 87:085cde657901 1959 * @brief Enables the MMC Counter Freeze.
mbed_official 87:085cde657901 1960 * @param __HANDLE__: ETH Handle.
mbed_official 87:085cde657901 1961 * @retval None
mbed_official 87:085cde657901 1962 */
mbed_official 87:085cde657901 1963 #define __HAL_ETH_MMC_COUNTER_FREEZE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCF)
mbed_official 87:085cde657901 1964
mbed_official 87:085cde657901 1965 /**
mbed_official 87:085cde657901 1966 * @brief Disables the MMC Counter Freeze.
mbed_official 87:085cde657901 1967 * @param __HANDLE__: ETH Handle.
mbed_official 87:085cde657901 1968 * @retval None
mbed_official 87:085cde657901 1969 */
mbed_official 87:085cde657901 1970 #define __HAL_ETH_MMC_COUNTER_FREEZE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCF)
mbed_official 87:085cde657901 1971
mbed_official 87:085cde657901 1972 /**
mbed_official 87:085cde657901 1973 * @brief Enables the MMC Reset On Read.
mbed_official 87:085cde657901 1974 * @param __HANDLE__: ETH Handle.
mbed_official 87:085cde657901 1975 * @retval None
mbed_official 87:085cde657901 1976 */
mbed_official 87:085cde657901 1977 #define __HAL_ETH_ETH_MMC_RESET_ONREAD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_ROR)
mbed_official 87:085cde657901 1978
mbed_official 87:085cde657901 1979 /**
mbed_official 87:085cde657901 1980 * @brief Disables the MMC Reset On Read.
mbed_official 87:085cde657901 1981 * @param __HANDLE__: ETH Handle.
mbed_official 87:085cde657901 1982 * @retval None
mbed_official 87:085cde657901 1983 */
mbed_official 87:085cde657901 1984 #define __HAL_ETH_ETH_MMC_RESET_ONREAD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_ROR)
mbed_official 87:085cde657901 1985
mbed_official 87:085cde657901 1986 /**
mbed_official 87:085cde657901 1987 * @brief Enables the MMC Counter Stop Rollover.
mbed_official 87:085cde657901 1988 * @param __HANDLE__: ETH Handle.
mbed_official 87:085cde657901 1989 * @retval None
mbed_official 87:085cde657901 1990 */
mbed_official 87:085cde657901 1991 #define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_CSR)
mbed_official 87:085cde657901 1992
mbed_official 87:085cde657901 1993 /**
mbed_official 87:085cde657901 1994 * @brief Disables the MMC Counter Stop Rollover.
mbed_official 87:085cde657901 1995 * @param __HANDLE__: ETH Handle.
mbed_official 87:085cde657901 1996 * @retval None
mbed_official 87:085cde657901 1997 */
mbed_official 87:085cde657901 1998 #define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CSR)
mbed_official 87:085cde657901 1999
mbed_official 87:085cde657901 2000 /**
mbed_official 87:085cde657901 2001 * @brief Resets the MMC Counters.
mbed_official 87:085cde657901 2002 * @param __HANDLE__: ETH Handle.
mbed_official 87:085cde657901 2003 * @retval None
mbed_official 87:085cde657901 2004 */
mbed_official 87:085cde657901 2005 #define __HAL_ETH_MMC_COUNTERS_RESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CR)
mbed_official 87:085cde657901 2006
mbed_official 87:085cde657901 2007 /**
mbed_official 87:085cde657901 2008 * @brief Enables the specified ETHERNET MMC Rx interrupts.
mbed_official 87:085cde657901 2009 * @param __HANDLE__: ETH Handle.
mbed_official 87:085cde657901 2010 * @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
mbed_official 87:085cde657901 2011 * This parameter can be one of the following values:
mbed_official 87:085cde657901 2012 * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value
mbed_official 87:085cde657901 2013 * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value
mbed_official 87:085cde657901 2014 * @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value
mbed_official 87:085cde657901 2015 * @retval None
mbed_official 87:085cde657901 2016 */
mbed_official 87:085cde657901 2017 #define __HAL_ETH_MMC_RX_IT_ENABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR &= ~((__INTERRUPT__) & 0xEFFFFFFF)
mbed_official 87:085cde657901 2018 /**
mbed_official 87:085cde657901 2019 * @brief Disables the specified ETHERNET MMC Rx interrupts.
mbed_official 87:085cde657901 2020 * @param __HANDLE__: ETH Handle.
mbed_official 87:085cde657901 2021 * @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
mbed_official 87:085cde657901 2022 * This parameter can be one of the following values:
mbed_official 87:085cde657901 2023 * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value
mbed_official 87:085cde657901 2024 * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value
mbed_official 87:085cde657901 2025 * @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value
mbed_official 87:085cde657901 2026 * @retval None
mbed_official 87:085cde657901 2027 */
mbed_official 87:085cde657901 2028 #define __HAL_ETH_MMC_RX_IT_DISABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR |= ((__INTERRUPT__) & 0xEFFFFFFF)
mbed_official 87:085cde657901 2029 /**
mbed_official 87:085cde657901 2030 * @brief Enables the specified ETHERNET MMC Tx interrupts.
mbed_official 87:085cde657901 2031 * @param __HANDLE__: ETH Handle.
mbed_official 87:085cde657901 2032 * @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
mbed_official 87:085cde657901 2033 * This parameter can be one of the following values:
mbed_official 87:085cde657901 2034 * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value
mbed_official 87:085cde657901 2035 * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value
mbed_official 87:085cde657901 2036 * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value
mbed_official 87:085cde657901 2037 * @retval None
mbed_official 87:085cde657901 2038 */
mbed_official 87:085cde657901 2039 #define __HAL_ETH_MMC_TX_IT_ENABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR &= ~ (__INTERRUPT__))
mbed_official 87:085cde657901 2040
mbed_official 87:085cde657901 2041 /**
mbed_official 87:085cde657901 2042 * @brief Disables the specified ETHERNET MMC Tx interrupts.
mbed_official 87:085cde657901 2043 * @param __HANDLE__: ETH Handle.
mbed_official 87:085cde657901 2044 * @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
mbed_official 87:085cde657901 2045 * This parameter can be one of the following values:
mbed_official 87:085cde657901 2046 * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value
mbed_official 87:085cde657901 2047 * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value
mbed_official 87:085cde657901 2048 * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value
mbed_official 87:085cde657901 2049 * @retval None
mbed_official 87:085cde657901 2050 */
mbed_official 532:fe11edbda85c 2051 #define __HAL_ETH_MMC_TX_IT_DISABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR |= (__INTERRUPT__))
mbed_official 532:fe11edbda85c 2052
mbed_official 532:fe11edbda85c 2053 /**
mbed_official 532:fe11edbda85c 2054 * @brief Enables the ETH External interrupt line.
mbed_official 532:fe11edbda85c 2055 * @retval None
mbed_official 532:fe11edbda85c 2056 */
mbed_official 532:fe11edbda85c 2057 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= (ETH_EXTI_LINE_WAKEUP)
mbed_official 532:fe11edbda85c 2058
mbed_official 532:fe11edbda85c 2059 /**
mbed_official 532:fe11edbda85c 2060 * @brief Disables the ETH External interrupt line.
mbed_official 532:fe11edbda85c 2061 * @retval None
mbed_official 532:fe11edbda85c 2062 */
mbed_official 532:fe11edbda85c 2063 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(ETH_EXTI_LINE_WAKEUP)
mbed_official 532:fe11edbda85c 2064
mbed_official 532:fe11edbda85c 2065 /**
mbed_official 532:fe11edbda85c 2066 * @brief Enable event on ETH External event line.
mbed_official 532:fe11edbda85c 2067 * @retval None.
mbed_official 532:fe11edbda85c 2068 */
mbed_official 532:fe11edbda85c 2069 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_EVENT() EXTI->EMR |= (ETH_EXTI_LINE_WAKEUP)
mbed_official 532:fe11edbda85c 2070
mbed_official 532:fe11edbda85c 2071 /**
mbed_official 532:fe11edbda85c 2072 * @brief Disable event on ETH External event line
mbed_official 532:fe11edbda85c 2073 * @retval None.
mbed_official 532:fe11edbda85c 2074 */
mbed_official 532:fe11edbda85c 2075 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_EVENT() EXTI->EMR &= ~(ETH_EXTI_LINE_WAKEUP)
mbed_official 532:fe11edbda85c 2076
mbed_official 532:fe11edbda85c 2077 /**
mbed_official 532:fe11edbda85c 2078 * @brief Get flag of the ETH External interrupt line.
mbed_official 532:fe11edbda85c 2079 * @retval None
mbed_official 532:fe11edbda85c 2080 */
mbed_official 532:fe11edbda85c 2081 #define __HAL_ETH_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (ETH_EXTI_LINE_WAKEUP)
mbed_official 532:fe11edbda85c 2082
mbed_official 532:fe11edbda85c 2083 /**
mbed_official 532:fe11edbda85c 2084 * @brief Clear flag of the ETH External interrupt line.
mbed_official 532:fe11edbda85c 2085 * @retval None
mbed_official 532:fe11edbda85c 2086 */
mbed_official 532:fe11edbda85c 2087 #define __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = (ETH_EXTI_LINE_WAKEUP)
mbed_official 87:085cde657901 2088
mbed_official 532:fe11edbda85c 2089 /**
mbed_official 532:fe11edbda85c 2090 * @brief Enables rising edge trigger to the ETH External interrupt line.
mbed_official 532:fe11edbda85c 2091 * @retval None
mbed_official 532:fe11edbda85c 2092 */
mbed_official 532:fe11edbda85c 2093 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER() EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP
mbed_official 532:fe11edbda85c 2094
mbed_official 532:fe11edbda85c 2095 /**
mbed_official 532:fe11edbda85c 2096 * @brief Disables the rising edge trigger to the ETH External interrupt line.
mbed_official 532:fe11edbda85c 2097 * @retval None
mbed_official 532:fe11edbda85c 2098 */
mbed_official 532:fe11edbda85c 2099 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_RISING_EDGE_TRIGGER() EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP)
mbed_official 532:fe11edbda85c 2100
mbed_official 532:fe11edbda85c 2101 /**
mbed_official 532:fe11edbda85c 2102 * @brief Enables falling edge trigger to the ETH External interrupt line.
mbed_official 532:fe11edbda85c 2103 * @retval None
mbed_official 532:fe11edbda85c 2104 */
mbed_official 532:fe11edbda85c 2105 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR |= (ETH_EXTI_LINE_WAKEUP)
mbed_official 532:fe11edbda85c 2106
mbed_official 532:fe11edbda85c 2107 /**
mbed_official 532:fe11edbda85c 2108 * @brief Disables falling edge trigger to the ETH External interrupt line.
mbed_official 532:fe11edbda85c 2109 * @retval None
mbed_official 532:fe11edbda85c 2110 */
mbed_official 532:fe11edbda85c 2111 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP)
mbed_official 532:fe11edbda85c 2112
mbed_official 532:fe11edbda85c 2113 /**
mbed_official 532:fe11edbda85c 2114 * @brief Enables rising/falling edge trigger to the ETH External interrupt line.
mbed_official 532:fe11edbda85c 2115 * @retval None
mbed_official 532:fe11edbda85c 2116 */
mbed_official 532:fe11edbda85c 2117 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER() EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP;\
mbed_official 532:fe11edbda85c 2118 EXTI->FTSR |= ETH_EXTI_LINE_WAKEUP
mbed_official 532:fe11edbda85c 2119
mbed_official 532:fe11edbda85c 2120 /**
mbed_official 532:fe11edbda85c 2121 * @brief Disables rising/falling edge trigger to the ETH External interrupt line.
mbed_official 532:fe11edbda85c 2122 * @retval None
mbed_official 532:fe11edbda85c 2123 */
mbed_official 532:fe11edbda85c 2124 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLINGRISING_TRIGGER() EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP);\
mbed_official 532:fe11edbda85c 2125 EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP)
mbed_official 532:fe11edbda85c 2126
mbed_official 532:fe11edbda85c 2127 /**
mbed_official 532:fe11edbda85c 2128 * @brief Generate a Software interrupt on selected EXTI line.
mbed_official 532:fe11edbda85c 2129 * @retval None.
mbed_official 532:fe11edbda85c 2130 */
mbed_official 532:fe11edbda85c 2131 #define __HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT() EXTI->SWIER|= ETH_EXTI_LINE_WAKEUP
mbed_official 87:085cde657901 2132
mbed_official 369:2e96f1b71984 2133 /**
mbed_official 369:2e96f1b71984 2134 * @}
mbed_official 369:2e96f1b71984 2135 */
mbed_official 87:085cde657901 2136 /* Exported functions --------------------------------------------------------*/
mbed_official 87:085cde657901 2137
mbed_official 532:fe11edbda85c 2138 /** @addtogroup ETH_Exported_Functions
mbed_official 532:fe11edbda85c 2139 * @{
mbed_official 532:fe11edbda85c 2140 */
mbed_official 532:fe11edbda85c 2141
mbed_official 87:085cde657901 2142 /* Initialization and de-initialization functions ****************************/
mbed_official 532:fe11edbda85c 2143
mbed_official 532:fe11edbda85c 2144 /** @addtogroup ETH_Exported_Functions_Group1
mbed_official 532:fe11edbda85c 2145 * @{
mbed_official 532:fe11edbda85c 2146 */
mbed_official 87:085cde657901 2147 HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth);
mbed_official 87:085cde657901 2148 HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth);
mbed_official 106:ced8cbb51063 2149 void HAL_ETH_MspInit(ETH_HandleTypeDef *heth);
mbed_official 106:ced8cbb51063 2150 void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth);
mbed_official 87:085cde657901 2151 HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount);
mbed_official 87:085cde657901 2152 HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount);
mbed_official 87:085cde657901 2153
mbed_official 532:fe11edbda85c 2154 /**
mbed_official 532:fe11edbda85c 2155 * @}
mbed_official 532:fe11edbda85c 2156 */
mbed_official 87:085cde657901 2157 /* IO operation functions ****************************************************/
mbed_official 532:fe11edbda85c 2158
mbed_official 532:fe11edbda85c 2159 /** @addtogroup ETH_Exported_Functions_Group2
mbed_official 532:fe11edbda85c 2160 * @{
mbed_official 532:fe11edbda85c 2161 */
mbed_official 87:085cde657901 2162 HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength);
mbed_official 87:085cde657901 2163 HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth);
mbed_official 532:fe11edbda85c 2164 /* Communication with PHY functions*/
mbed_official 532:fe11edbda85c 2165 HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue);
mbed_official 532:fe11edbda85c 2166 HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue);
mbed_official 532:fe11edbda85c 2167 /* Non-Blocking mode: Interrupt */
mbed_official 87:085cde657901 2168 HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth);
mbed_official 87:085cde657901 2169 void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth);
mbed_official 532:fe11edbda85c 2170 /* Callback in non blocking modes (Interrupt) */
mbed_official 106:ced8cbb51063 2171 void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth);
mbed_official 106:ced8cbb51063 2172 void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth);
mbed_official 106:ced8cbb51063 2173 void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth);
mbed_official 532:fe11edbda85c 2174 /**
mbed_official 532:fe11edbda85c 2175 * @}
mbed_official 532:fe11edbda85c 2176 */
mbed_official 87:085cde657901 2177
mbed_official 87:085cde657901 2178 /* Peripheral Control functions **********************************************/
mbed_official 532:fe11edbda85c 2179
mbed_official 532:fe11edbda85c 2180 /** @addtogroup ETH_Exported_Functions_Group3
mbed_official 532:fe11edbda85c 2181 * @{
mbed_official 532:fe11edbda85c 2182 */
mbed_official 532:fe11edbda85c 2183
mbed_official 87:085cde657901 2184 HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth);
mbed_official 87:085cde657901 2185 HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth);
mbed_official 87:085cde657901 2186 HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf);
mbed_official 87:085cde657901 2187 HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf);
mbed_official 87:085cde657901 2188 /**
mbed_official 87:085cde657901 2189 * @}
mbed_official 87:085cde657901 2190 */
mbed_official 87:085cde657901 2191
mbed_official 532:fe11edbda85c 2192 /* Peripheral State functions ************************************************/
mbed_official 532:fe11edbda85c 2193
mbed_official 532:fe11edbda85c 2194 /** @addtogroup ETH_Exported_Functions_Group4
mbed_official 532:fe11edbda85c 2195 * @{
mbed_official 532:fe11edbda85c 2196 */
mbed_official 532:fe11edbda85c 2197 HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth);
mbed_official 532:fe11edbda85c 2198 /**
mbed_official 532:fe11edbda85c 2199 * @}
mbed_official 532:fe11edbda85c 2200 */
mbed_official 532:fe11edbda85c 2201
mbed_official 87:085cde657901 2202 /**
mbed_official 87:085cde657901 2203 * @}
mbed_official 532:fe11edbda85c 2204 */
mbed_official 532:fe11edbda85c 2205
mbed_official 532:fe11edbda85c 2206 /**
mbed_official 532:fe11edbda85c 2207 * @}
mbed_official 532:fe11edbda85c 2208 */
mbed_official 532:fe11edbda85c 2209
mbed_official 532:fe11edbda85c 2210 /**
mbed_official 532:fe11edbda85c 2211 * @}
mbed_official 532:fe11edbda85c 2212 */
mbed_official 532:fe11edbda85c 2213
mbed_official 532:fe11edbda85c 2214 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
mbed_official 87:085cde657901 2215
mbed_official 87:085cde657901 2216 #ifdef __cplusplus
mbed_official 87:085cde657901 2217 }
mbed_official 87:085cde657901 2218 #endif
mbed_official 87:085cde657901 2219
mbed_official 87:085cde657901 2220 #endif /* __STM32F4xx_HAL_ETH_H */
mbed_official 87:085cde657901 2221
mbed_official 87:085cde657901 2222
mbed_official 87:085cde657901 2223 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/