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This library was superseded by mbed-dev - https://os.mbed.com/users/mbed_official/code/mbed-dev/.

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Last commit 20 Feb 2019 by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F4/stm32f4xx_hal_eth.c@581:39197bcd20f2, 2015-07-02 (annotated)

Committer:
mbed_official
Date:
Thu Jul 02 16:30:08 2015 +0100
Revision:
581:39197bcd20f2
Parent:
532:fe11edbda85c
Child:
613:bc40b8d2aec4
Synchronized with git revision ae2d3cdffe70184eb8736d94f76c45c93f4b7724



Full URL: https://github.com/mbedmicro/mbed/commit/ae2d3cdffe70184eb8736d94f76c45c93f4b7724/



Make it possible to build the core mbed library with yotta

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 235:685d5f11838f 1 /**
mbed_official 235:685d5f11838f 2 ******************************************************************************
mbed_official 235:685d5f11838f 3 * @file stm32f4xx_hal_eth.c
mbed_official 235:685d5f11838f 4 * @author MCD Application Team
mbed_official 532:fe11edbda85c 5 * @version V1.3.0
mbed_official 532:fe11edbda85c 6 * @date 09-March-2015
mbed_official 235:685d5f11838f 7 * @brief ETH HAL module driver.
mbed_official 235:685d5f11838f 8 * This file provides firmware functions to manage the following
mbed_official 235:685d5f11838f 9 * functionalities of the Ethernet (ETH) peripheral:
mbed_official 235:685d5f11838f 10 * + Initialization and de-initialization functions
mbed_official 235:685d5f11838f 11 * + IO operation functions
mbed_official 235:685d5f11838f 12 * + Peripheral Control functions
mbed_official 235:685d5f11838f 13 * + Peripheral State and Errors functions
mbed_official 235:685d5f11838f 14 *
mbed_official 235:685d5f11838f 15 @verbatim
mbed_official 235:685d5f11838f 16 ==============================================================================
mbed_official 235:685d5f11838f 17 ##### How to use this driver #####
mbed_official 235:685d5f11838f 18 ==============================================================================
mbed_official 235:685d5f11838f 19 [..]
mbed_official 235:685d5f11838f 20 (#)Declare a ETH_HandleTypeDef handle structure, for example:
mbed_official 235:685d5f11838f 21 ETH_HandleTypeDef heth;
mbed_official 235:685d5f11838f 22
mbed_official 235:685d5f11838f 23 (#)Fill parameters of Init structure in heth handle
mbed_official 235:685d5f11838f 24
mbed_official 235:685d5f11838f 25 (#)Call HAL_ETH_Init() API to initialize the Ethernet peripheral (MAC, DMA, ...)
mbed_official 235:685d5f11838f 26
mbed_official 235:685d5f11838f 27 (#)Initialize the ETH low level resources through the HAL_ETH_MspInit() API:
mbed_official 235:685d5f11838f 28 (##) Enable the Ethernet interface clock using
mbed_official 532:fe11edbda85c 29 (+++) __HAL_RCC_ETHMAC_CLK_ENABLE();
mbed_official 532:fe11edbda85c 30 (+++) __HAL_RCC_ETHMACTX_CLK_ENABLE();
mbed_official 532:fe11edbda85c 31 (+++) __HAL_RCC_ETHMACRX_CLK_ENABLE();
mbed_official 235:685d5f11838f 32
mbed_official 235:685d5f11838f 33 (##) Initialize the related GPIO clocks
mbed_official 235:685d5f11838f 34 (##) Configure Ethernet pin-out
mbed_official 235:685d5f11838f 35 (##) Configure Ethernet NVIC interrupt (IT mode)
mbed_official 235:685d5f11838f 36
mbed_official 235:685d5f11838f 37 (#)Initialize Ethernet DMA Descriptors in chain mode and point to allocated buffers:
mbed_official 235:685d5f11838f 38 (##) HAL_ETH_DMATxDescListInit(); for Transmission process
mbed_official 235:685d5f11838f 39 (##) HAL_ETH_DMARxDescListInit(); for Reception process
mbed_official 235:685d5f11838f 40
mbed_official 235:685d5f11838f 41 (#)Enable MAC and DMA transmission and reception:
mbed_official 235:685d5f11838f 42 (##) HAL_ETH_Start();
mbed_official 235:685d5f11838f 43
mbed_official 235:685d5f11838f 44 (#)Prepare ETH DMA TX Descriptors and give the hand to ETH DMA to transfer
mbed_official 235:685d5f11838f 45 the frame to MAC TX FIFO:
mbed_official 235:685d5f11838f 46 (##) HAL_ETH_TransmitFrame();
mbed_official 235:685d5f11838f 47
mbed_official 235:685d5f11838f 48 (#)Poll for a received frame in ETH RX DMA Descriptors and get received
mbed_official 235:685d5f11838f 49 frame parameters
mbed_official 235:685d5f11838f 50 (##) HAL_ETH_GetReceivedFrame(); (should be called into an infinite loop)
mbed_official 235:685d5f11838f 51
mbed_official 235:685d5f11838f 52 (#) Get a received frame when an ETH RX interrupt occurs:
mbed_official 235:685d5f11838f 53 (##) HAL_ETH_GetReceivedFrame_IT(); (called in IT mode only)
mbed_official 235:685d5f11838f 54
mbed_official 235:685d5f11838f 55 (#) Communicate with external PHY device:
mbed_official 235:685d5f11838f 56 (##) Read a specific register from the PHY
mbed_official 235:685d5f11838f 57 HAL_ETH_ReadPHYRegister();
mbed_official 235:685d5f11838f 58 (##) Write data to a specific RHY register:
mbed_official 235:685d5f11838f 59 HAL_ETH_WritePHYRegister();
mbed_official 235:685d5f11838f 60
mbed_official 235:685d5f11838f 61 (#) Configure the Ethernet MAC after ETH peripheral initialization
mbed_official 235:685d5f11838f 62 HAL_ETH_ConfigMAC(); all MAC parameters should be filled.
mbed_official 235:685d5f11838f 63
mbed_official 235:685d5f11838f 64 (#) Configure the Ethernet DMA after ETH peripheral initialization
mbed_official 235:685d5f11838f 65 HAL_ETH_ConfigDMA(); all DMA parameters should be filled.
mbed_official 532:fe11edbda85c 66
mbed_official 532:fe11edbda85c 67 -@- The PTP protocol and the DMA descriptors ring mode are not supported
mbed_official 532:fe11edbda85c 68 in this driver
mbed_official 235:685d5f11838f 69
mbed_official 235:685d5f11838f 70 @endverbatim
mbed_official 235:685d5f11838f 71 ******************************************************************************
mbed_official 235:685d5f11838f 72 * @attention
mbed_official 235:685d5f11838f 73 *
mbed_official 532:fe11edbda85c 74 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
mbed_official 235:685d5f11838f 75 *
mbed_official 235:685d5f11838f 76 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 235:685d5f11838f 77 * are permitted provided that the following conditions are met:
mbed_official 235:685d5f11838f 78 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 235:685d5f11838f 79 * this list of conditions and the following disclaimer.
mbed_official 235:685d5f11838f 80 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 235:685d5f11838f 81 * this list of conditions and the following disclaimer in the documentation
mbed_official 235:685d5f11838f 82 * and/or other materials provided with the distribution.
mbed_official 235:685d5f11838f 83 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 235:685d5f11838f 84 * may be used to endorse or promote products derived from this software
mbed_official 235:685d5f11838f 85 * without specific prior written permission.
mbed_official 235:685d5f11838f 86 *
mbed_official 235:685d5f11838f 87 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 235:685d5f11838f 88 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 235:685d5f11838f 89 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 235:685d5f11838f 90 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 235:685d5f11838f 91 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 235:685d5f11838f 92 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 235:685d5f11838f 93 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 235:685d5f11838f 94 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 235:685d5f11838f 95 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 235:685d5f11838f 96 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 235:685d5f11838f 97 *
mbed_official 235:685d5f11838f 98 ******************************************************************************
mbed_official 235:685d5f11838f 99 */
mbed_official 235:685d5f11838f 100
mbed_official 235:685d5f11838f 101 /* Includes ------------------------------------------------------------------*/
mbed_official 235:685d5f11838f 102 #include "stm32f4xx_hal.h"
mbed_official 235:685d5f11838f 103
mbed_official 235:685d5f11838f 104 /** @addtogroup STM32F4xx_HAL_Driver
mbed_official 235:685d5f11838f 105 * @{
mbed_official 235:685d5f11838f 106 */
mbed_official 235:685d5f11838f 107
mbed_official 532:fe11edbda85c 108 /** @defgroup ETH ETH
mbed_official 235:685d5f11838f 109 * @brief ETH HAL module driver
mbed_official 235:685d5f11838f 110 * @{
mbed_official 235:685d5f11838f 111 */
mbed_official 235:685d5f11838f 112
mbed_official 235:685d5f11838f 113 #ifdef HAL_ETH_MODULE_ENABLED
mbed_official 235:685d5f11838f 114
mbed_official 235:685d5f11838f 115 #if defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
mbed_official 235:685d5f11838f 116
mbed_official 235:685d5f11838f 117 /* Private typedef -----------------------------------------------------------*/
mbed_official 235:685d5f11838f 118 /* Private define ------------------------------------------------------------*/
mbed_official 532:fe11edbda85c 119 /** @defgroup ETH_Private_Constants ETH Private Constants
mbed_official 532:fe11edbda85c 120 * @{
mbed_official 532:fe11edbda85c 121 */
mbed_official 235:685d5f11838f 122 #define LINKED_STATE_TIMEOUT_VALUE ((uint32_t)2000) /* 2000 ms */
mbed_official 235:685d5f11838f 123 #define AUTONEGO_COMPLETED_TIMEOUT_VALUE ((uint32_t)1000) /* 1000 ms */
mbed_official 235:685d5f11838f 124
mbed_official 532:fe11edbda85c 125 /**
mbed_official 532:fe11edbda85c 126 * @}
mbed_official 532:fe11edbda85c 127 */
mbed_official 235:685d5f11838f 128 /* Private macro -------------------------------------------------------------*/
mbed_official 235:685d5f11838f 129 /* Private variables ---------------------------------------------------------*/
mbed_official 235:685d5f11838f 130 /* Private function prototypes -----------------------------------------------*/
mbed_official 532:fe11edbda85c 131 /** @defgroup ETH_Private_Functions ETH Private Functions
mbed_official 532:fe11edbda85c 132 * @{
mbed_official 532:fe11edbda85c 133 */
mbed_official 235:685d5f11838f 134 static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err);
mbed_official 235:685d5f11838f 135 static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr);
mbed_official 235:685d5f11838f 136 static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth);
mbed_official 235:685d5f11838f 137 static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth);
mbed_official 235:685d5f11838f 138 static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth);
mbed_official 235:685d5f11838f 139 static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth);
mbed_official 235:685d5f11838f 140 static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth);
mbed_official 235:685d5f11838f 141 static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth);
mbed_official 235:685d5f11838f 142 static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth);
mbed_official 235:685d5f11838f 143 static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth);
mbed_official 235:685d5f11838f 144 static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth);
mbed_official 235:685d5f11838f 145
mbed_official 532:fe11edbda85c 146 /**
mbed_official 532:fe11edbda85c 147 * @}
mbed_official 532:fe11edbda85c 148 */
mbed_official 235:685d5f11838f 149 /* Private functions ---------------------------------------------------------*/
mbed_official 235:685d5f11838f 150
mbed_official 532:fe11edbda85c 151 /** @defgroup ETH_Exported_Functions ETH Exported Functions
mbed_official 235:685d5f11838f 152 * @{
mbed_official 235:685d5f11838f 153 */
mbed_official 235:685d5f11838f 154
mbed_official 532:fe11edbda85c 155 /** @defgroup ETH_Exported_Functions_Group1 Initialization and de-initialization functions
mbed_official 532:fe11edbda85c 156 * @brief Initialization and Configuration functions
mbed_official 235:685d5f11838f 157 *
mbed_official 235:685d5f11838f 158 @verbatim
mbed_official 235:685d5f11838f 159 ===============================================================================
mbed_official 235:685d5f11838f 160 ##### Initialization and de-initialization functions #####
mbed_official 235:685d5f11838f 161 ===============================================================================
mbed_official 235:685d5f11838f 162 [..] This section provides functions allowing to:
mbed_official 235:685d5f11838f 163 (+) Initialize and configure the Ethernet peripheral
mbed_official 235:685d5f11838f 164 (+) De-initialize the Ethernet peripheral
mbed_official 235:685d5f11838f 165
mbed_official 235:685d5f11838f 166 @endverbatim
mbed_official 235:685d5f11838f 167 * @{
mbed_official 235:685d5f11838f 168 */
mbed_official 235:685d5f11838f 169
mbed_official 235:685d5f11838f 170 /**
mbed_official 235:685d5f11838f 171 * @brief Initializes the Ethernet MAC and DMA according to default
mbed_official 235:685d5f11838f 172 * parameters.
mbed_official 235:685d5f11838f 173 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 235:685d5f11838f 174 * the configuration information for ETHERNET module
mbed_official 235:685d5f11838f 175 * @retval HAL status
mbed_official 235:685d5f11838f 176 */
mbed_official 235:685d5f11838f 177 HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
mbed_official 235:685d5f11838f 178 {
mbed_official 532:fe11edbda85c 179 uint32_t tmpreg1 = 0, phyreg = 0;
mbed_official 235:685d5f11838f 180 uint32_t hclk = 60000000;
mbed_official 235:685d5f11838f 181 uint32_t tickstart = 0;
mbed_official 235:685d5f11838f 182 uint32_t err = ETH_SUCCESS;
mbed_official 235:685d5f11838f 183
mbed_official 235:685d5f11838f 184 /* Check the ETH peripheral state */
mbed_official 384:ef87175507f1 185 if(heth == HAL_NULL)
mbed_official 235:685d5f11838f 186 {
mbed_official 235:685d5f11838f 187 return HAL_ERROR;
mbed_official 235:685d5f11838f 188 }
mbed_official 235:685d5f11838f 189
mbed_official 235:685d5f11838f 190 /* Check parameters */
mbed_official 235:685d5f11838f 191 assert_param(IS_ETH_AUTONEGOTIATION(heth->Init.AutoNegotiation));
mbed_official 235:685d5f11838f 192 assert_param(IS_ETH_RX_MODE(heth->Init.RxMode));
mbed_official 235:685d5f11838f 193 assert_param(IS_ETH_CHECKSUM_MODE(heth->Init.ChecksumMode));
mbed_official 235:685d5f11838f 194 assert_param(IS_ETH_MEDIA_INTERFACE(heth->Init.MediaInterface));
mbed_official 235:685d5f11838f 195
mbed_official 235:685d5f11838f 196 if(heth->State == HAL_ETH_STATE_RESET)
mbed_official 235:685d5f11838f 197 {
mbed_official 532:fe11edbda85c 198 /* Allocate lock resource and initialize it */
mbed_official 532:fe11edbda85c 199 heth->Lock = HAL_UNLOCKED;
mbed_official 235:685d5f11838f 200 /* Init the low level hardware : GPIO, CLOCK, NVIC. */
mbed_official 235:685d5f11838f 201 HAL_ETH_MspInit(heth);
mbed_official 235:685d5f11838f 202 }
mbed_official 235:685d5f11838f 203
mbed_official 235:685d5f11838f 204 /* Enable SYSCFG Clock */
mbed_official 532:fe11edbda85c 205 __HAL_RCC_SYSCFG_CLK_ENABLE();
mbed_official 235:685d5f11838f 206
mbed_official 235:685d5f11838f 207 /* Select MII or RMII Mode*/
mbed_official 235:685d5f11838f 208 SYSCFG->PMC &= ~(SYSCFG_PMC_MII_RMII_SEL);
mbed_official 235:685d5f11838f 209 SYSCFG->PMC |= (uint32_t)heth->Init.MediaInterface;
mbed_official 235:685d5f11838f 210
mbed_official 235:685d5f11838f 211 /* Ethernet Software reset */
mbed_official 235:685d5f11838f 212 /* Set the SWR bit: resets all MAC subsystem internal registers and logic */
mbed_official 235:685d5f11838f 213 /* After reset all the registers holds their respective reset values */
mbed_official 235:685d5f11838f 214 (heth->Instance)->DMABMR |= ETH_DMABMR_SR;
mbed_official 235:685d5f11838f 215
mbed_official 235:685d5f11838f 216 /* Wait for software reset */
mbed_official 235:685d5f11838f 217 while (((heth->Instance)->DMABMR & ETH_DMABMR_SR) != (uint32_t)RESET)
mbed_official 235:685d5f11838f 218 {
mbed_official 235:685d5f11838f 219 }
mbed_official 235:685d5f11838f 220
mbed_official 235:685d5f11838f 221 /*-------------------------------- MAC Initialization ----------------------*/
mbed_official 235:685d5f11838f 222 /* Get the ETHERNET MACMIIAR value */
mbed_official 532:fe11edbda85c 223 tmpreg1 = (heth->Instance)->MACMIIAR;
mbed_official 235:685d5f11838f 224 /* Clear CSR Clock Range CR[2:0] bits */
mbed_official 532:fe11edbda85c 225 tmpreg1 &= ETH_MACMIIAR_CR_MASK;
mbed_official 235:685d5f11838f 226
mbed_official 235:685d5f11838f 227 /* Get hclk frequency value */
mbed_official 235:685d5f11838f 228 hclk = HAL_RCC_GetHCLKFreq();
mbed_official 235:685d5f11838f 229
mbed_official 235:685d5f11838f 230 /* Set CR bits depending on hclk value */
mbed_official 235:685d5f11838f 231 if((hclk >= 20000000)&&(hclk < 35000000))
mbed_official 235:685d5f11838f 232 {
mbed_official 235:685d5f11838f 233 /* CSR Clock Range between 20-35 MHz */
mbed_official 532:fe11edbda85c 234 tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div16;
mbed_official 235:685d5f11838f 235 }
mbed_official 235:685d5f11838f 236 else if((hclk >= 35000000)&&(hclk < 60000000))
mbed_official 235:685d5f11838f 237 {
mbed_official 235:685d5f11838f 238 /* CSR Clock Range between 35-60 MHz */
mbed_official 532:fe11edbda85c 239 tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div26;
mbed_official 235:685d5f11838f 240 }
mbed_official 235:685d5f11838f 241 else if((hclk >= 60000000)&&(hclk < 100000000))
mbed_official 235:685d5f11838f 242 {
mbed_official 235:685d5f11838f 243 /* CSR Clock Range between 60-100 MHz */
mbed_official 532:fe11edbda85c 244 tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div42;
mbed_official 235:685d5f11838f 245 }
mbed_official 235:685d5f11838f 246 else if((hclk >= 100000000)&&(hclk < 150000000))
mbed_official 235:685d5f11838f 247 {
mbed_official 235:685d5f11838f 248 /* CSR Clock Range between 100-150 MHz */
mbed_official 532:fe11edbda85c 249 tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div62;
mbed_official 235:685d5f11838f 250 }
mbed_official 235:685d5f11838f 251 else /* ((hclk >= 150000000)&&(hclk <= 168000000)) */
mbed_official 235:685d5f11838f 252 {
mbed_official 235:685d5f11838f 253 /* CSR Clock Range between 150-168 MHz */
mbed_official 532:fe11edbda85c 254 tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div102;
mbed_official 235:685d5f11838f 255 }
mbed_official 235:685d5f11838f 256
mbed_official 235:685d5f11838f 257 /* Write to ETHERNET MAC MIIAR: Configure the ETHERNET CSR Clock Range */
mbed_official 532:fe11edbda85c 258 (heth->Instance)->MACMIIAR = (uint32_t)tmpreg1;
mbed_official 235:685d5f11838f 259
mbed_official 235:685d5f11838f 260 /*-------------------- PHY initialization and configuration ----------------*/
mbed_official 235:685d5f11838f 261 /* Put the PHY in reset mode */
mbed_official 235:685d5f11838f 262 if((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_RESET)) != HAL_OK)
mbed_official 235:685d5f11838f 263 {
mbed_official 235:685d5f11838f 264 /* In case of write timeout */
mbed_official 235:685d5f11838f 265 err = ETH_ERROR;
mbed_official 235:685d5f11838f 266
mbed_official 235:685d5f11838f 267 /* Config MAC and DMA */
mbed_official 235:685d5f11838f 268 ETH_MACDMAConfig(heth, err);
mbed_official 235:685d5f11838f 269
mbed_official 235:685d5f11838f 270 /* Set the ETH peripheral state to READY */
mbed_official 235:685d5f11838f 271 heth->State = HAL_ETH_STATE_READY;
mbed_official 235:685d5f11838f 272
mbed_official 235:685d5f11838f 273 /* Return HAL_ERROR */
mbed_official 235:685d5f11838f 274 return HAL_ERROR;
mbed_official 235:685d5f11838f 275 }
mbed_official 235:685d5f11838f 276
mbed_official 235:685d5f11838f 277 /* Delay to assure PHY reset */
mbed_official 235:685d5f11838f 278 HAL_Delay(PHY_RESET_DELAY);
mbed_official 235:685d5f11838f 279
mbed_official 235:685d5f11838f 280 if((heth->Init).AutoNegotiation != ETH_AUTONEGOTIATION_DISABLE)
mbed_official 235:685d5f11838f 281 {
mbed_official 235:685d5f11838f 282 /* Get tick */
mbed_official 235:685d5f11838f 283 tickstart = HAL_GetTick();
mbed_official 235:685d5f11838f 284
mbed_official 235:685d5f11838f 285 /* We wait for linked status */
mbed_official 235:685d5f11838f 286 do
mbed_official 235:685d5f11838f 287 {
mbed_official 235:685d5f11838f 288 HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg);
mbed_official 235:685d5f11838f 289
mbed_official 235:685d5f11838f 290 /* Check for the Timeout */
mbed_official 235:685d5f11838f 291 if((HAL_GetTick() - tickstart ) > LINKED_STATE_TIMEOUT_VALUE)
mbed_official 235:685d5f11838f 292 {
mbed_official 235:685d5f11838f 293 /* In case of write timeout */
mbed_official 235:685d5f11838f 294 err = ETH_ERROR;
mbed_official 235:685d5f11838f 295
mbed_official 235:685d5f11838f 296 /* Config MAC and DMA */
mbed_official 235:685d5f11838f 297 ETH_MACDMAConfig(heth, err);
mbed_official 235:685d5f11838f 298
mbed_official 235:685d5f11838f 299 heth->State= HAL_ETH_STATE_READY;
mbed_official 235:685d5f11838f 300
mbed_official 235:685d5f11838f 301 /* Process Unlocked */
mbed_official 235:685d5f11838f 302 __HAL_UNLOCK(heth);
mbed_official 235:685d5f11838f 303
mbed_official 235:685d5f11838f 304 return HAL_TIMEOUT;
mbed_official 235:685d5f11838f 305 }
mbed_official 235:685d5f11838f 306 } while (((phyreg & PHY_LINKED_STATUS) != PHY_LINKED_STATUS));
mbed_official 235:685d5f11838f 307
mbed_official 235:685d5f11838f 308
mbed_official 235:685d5f11838f 309 /* Enable Auto-Negotiation */
mbed_official 235:685d5f11838f 310 if((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_AUTONEGOTIATION)) != HAL_OK)
mbed_official 235:685d5f11838f 311 {
mbed_official 235:685d5f11838f 312 /* In case of write timeout */
mbed_official 235:685d5f11838f 313 err = ETH_ERROR;
mbed_official 235:685d5f11838f 314
mbed_official 235:685d5f11838f 315 /* Config MAC and DMA */
mbed_official 235:685d5f11838f 316 ETH_MACDMAConfig(heth, err);
mbed_official 235:685d5f11838f 317
mbed_official 235:685d5f11838f 318 /* Set the ETH peripheral state to READY */
mbed_official 235:685d5f11838f 319 heth->State = HAL_ETH_STATE_READY;
mbed_official 235:685d5f11838f 320
mbed_official 235:685d5f11838f 321 /* Return HAL_ERROR */
mbed_official 235:685d5f11838f 322 return HAL_ERROR;
mbed_official 235:685d5f11838f 323 }
mbed_official 235:685d5f11838f 324
mbed_official 235:685d5f11838f 325 /* Get tick */
mbed_official 235:685d5f11838f 326 tickstart = HAL_GetTick();
mbed_official 235:685d5f11838f 327
mbed_official 235:685d5f11838f 328 /* Wait until the auto-negotiation will be completed */
mbed_official 235:685d5f11838f 329 do
mbed_official 235:685d5f11838f 330 {
mbed_official 235:685d5f11838f 331 HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg);
mbed_official 235:685d5f11838f 332
mbed_official 235:685d5f11838f 333 /* Check for the Timeout */
mbed_official 235:685d5f11838f 334 if((HAL_GetTick() - tickstart ) > AUTONEGO_COMPLETED_TIMEOUT_VALUE)
mbed_official 235:685d5f11838f 335 {
mbed_official 235:685d5f11838f 336 /* In case of write timeout */
mbed_official 235:685d5f11838f 337 err = ETH_ERROR;
mbed_official 235:685d5f11838f 338
mbed_official 235:685d5f11838f 339 /* Config MAC and DMA */
mbed_official 235:685d5f11838f 340 ETH_MACDMAConfig(heth, err);
mbed_official 235:685d5f11838f 341
mbed_official 235:685d5f11838f 342 heth->State= HAL_ETH_STATE_READY;
mbed_official 235:685d5f11838f 343
mbed_official 235:685d5f11838f 344 /* Process Unlocked */
mbed_official 235:685d5f11838f 345 __HAL_UNLOCK(heth);
mbed_official 235:685d5f11838f 346
mbed_official 235:685d5f11838f 347 return HAL_TIMEOUT;
mbed_official 235:685d5f11838f 348 }
mbed_official 235:685d5f11838f 349
mbed_official 235:685d5f11838f 350 } while (((phyreg & PHY_AUTONEGO_COMPLETE) != PHY_AUTONEGO_COMPLETE));
mbed_official 235:685d5f11838f 351
mbed_official 235:685d5f11838f 352 /* Read the result of the auto-negotiation */
mbed_official 235:685d5f11838f 353 if((HAL_ETH_ReadPHYRegister(heth, PHY_SR, &phyreg)) != HAL_OK)
mbed_official 235:685d5f11838f 354 {
mbed_official 235:685d5f11838f 355 /* In case of write timeout */
mbed_official 235:685d5f11838f 356 err = ETH_ERROR;
mbed_official 235:685d5f11838f 357
mbed_official 235:685d5f11838f 358 /* Config MAC and DMA */
mbed_official 235:685d5f11838f 359 ETH_MACDMAConfig(heth, err);
mbed_official 235:685d5f11838f 360
mbed_official 235:685d5f11838f 361 /* Set the ETH peripheral state to READY */
mbed_official 235:685d5f11838f 362 heth->State = HAL_ETH_STATE_READY;
mbed_official 235:685d5f11838f 363
mbed_official 235:685d5f11838f 364 /* Return HAL_ERROR */
mbed_official 235:685d5f11838f 365 return HAL_ERROR;
mbed_official 235:685d5f11838f 366 }
mbed_official 235:685d5f11838f 367
mbed_official 235:685d5f11838f 368 /* Configure the MAC with the Duplex Mode fixed by the auto-negotiation process */
mbed_official 235:685d5f11838f 369 if((phyreg & PHY_DUPLEX_STATUS) != (uint32_t)RESET)
mbed_official 235:685d5f11838f 370 {
mbed_official 235:685d5f11838f 371 /* Set Ethernet duplex mode to Full-duplex following the auto-negotiation */
mbed_official 235:685d5f11838f 372 (heth->Init).DuplexMode = ETH_MODE_FULLDUPLEX;
mbed_official 235:685d5f11838f 373 }
mbed_official 235:685d5f11838f 374 else
mbed_official 235:685d5f11838f 375 {
mbed_official 235:685d5f11838f 376 /* Set Ethernet duplex mode to Half-duplex following the auto-negotiation */
mbed_official 235:685d5f11838f 377 (heth->Init).DuplexMode = ETH_MODE_HALFDUPLEX;
mbed_official 235:685d5f11838f 378 }
mbed_official 235:685d5f11838f 379 /* Configure the MAC with the speed fixed by the auto-negotiation process */
mbed_official 235:685d5f11838f 380 if((phyreg & PHY_SPEED_STATUS) == PHY_SPEED_STATUS)
mbed_official 235:685d5f11838f 381 {
mbed_official 235:685d5f11838f 382 /* Set Ethernet speed to 10M following the auto-negotiation */
mbed_official 235:685d5f11838f 383 (heth->Init).Speed = ETH_SPEED_10M;
mbed_official 235:685d5f11838f 384 }
mbed_official 235:685d5f11838f 385 else
mbed_official 235:685d5f11838f 386 {
mbed_official 235:685d5f11838f 387 /* Set Ethernet speed to 100M following the auto-negotiation */
mbed_official 235:685d5f11838f 388 (heth->Init).Speed = ETH_SPEED_100M;
mbed_official 235:685d5f11838f 389 }
mbed_official 235:685d5f11838f 390 }
mbed_official 235:685d5f11838f 391 else /* AutoNegotiation Disable */
mbed_official 235:685d5f11838f 392 {
mbed_official 235:685d5f11838f 393 /* Check parameters */
mbed_official 235:685d5f11838f 394 assert_param(IS_ETH_SPEED(heth->Init.Speed));
mbed_official 235:685d5f11838f 395 assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode));
mbed_official 235:685d5f11838f 396
mbed_official 235:685d5f11838f 397 /* Set MAC Speed and Duplex Mode */
mbed_official 235:685d5f11838f 398 if(HAL_ETH_WritePHYRegister(heth, PHY_BCR, ((uint16_t)((heth->Init).DuplexMode >> 3) |
mbed_official 235:685d5f11838f 399 (uint16_t)((heth->Init).Speed >> 1))) != HAL_OK)
mbed_official 235:685d5f11838f 400 {
mbed_official 235:685d5f11838f 401 /* In case of write timeout */
mbed_official 235:685d5f11838f 402 err = ETH_ERROR;
mbed_official 235:685d5f11838f 403
mbed_official 235:685d5f11838f 404 /* Config MAC and DMA */
mbed_official 235:685d5f11838f 405 ETH_MACDMAConfig(heth, err);
mbed_official 235:685d5f11838f 406
mbed_official 235:685d5f11838f 407 /* Set the ETH peripheral state to READY */
mbed_official 235:685d5f11838f 408 heth->State = HAL_ETH_STATE_READY;
mbed_official 235:685d5f11838f 409
mbed_official 235:685d5f11838f 410 /* Return HAL_ERROR */
mbed_official 235:685d5f11838f 411 return HAL_ERROR;
mbed_official 235:685d5f11838f 412 }
mbed_official 235:685d5f11838f 413
mbed_official 235:685d5f11838f 414 /* Delay to assure PHY configuration */
mbed_official 235:685d5f11838f 415 HAL_Delay(PHY_CONFIG_DELAY);
mbed_official 235:685d5f11838f 416 }
mbed_official 235:685d5f11838f 417
mbed_official 235:685d5f11838f 418 /* Config MAC and DMA */
mbed_official 235:685d5f11838f 419 ETH_MACDMAConfig(heth, err);
mbed_official 235:685d5f11838f 420
mbed_official 235:685d5f11838f 421 /* Set ETH HAL State to Ready */
mbed_official 235:685d5f11838f 422 heth->State= HAL_ETH_STATE_READY;
mbed_official 235:685d5f11838f 423
mbed_official 235:685d5f11838f 424 /* Return function status */
mbed_official 235:685d5f11838f 425 return HAL_OK;
mbed_official 235:685d5f11838f 426 }
mbed_official 235:685d5f11838f 427
mbed_official 235:685d5f11838f 428 /**
mbed_official 235:685d5f11838f 429 * @brief De-Initializes the ETH peripheral.
mbed_official 235:685d5f11838f 430 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 235:685d5f11838f 431 * the configuration information for ETHERNET module
mbed_official 235:685d5f11838f 432 * @retval HAL status
mbed_official 235:685d5f11838f 433 */
mbed_official 235:685d5f11838f 434 HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth)
mbed_official 235:685d5f11838f 435 {
mbed_official 235:685d5f11838f 436 /* Set the ETH peripheral state to BUSY */
mbed_official 235:685d5f11838f 437 heth->State = HAL_ETH_STATE_BUSY;
mbed_official 235:685d5f11838f 438
mbed_official 235:685d5f11838f 439 /* De-Init the low level hardware : GPIO, CLOCK, NVIC. */
mbed_official 235:685d5f11838f 440 HAL_ETH_MspDeInit(heth);
mbed_official 235:685d5f11838f 441
mbed_official 235:685d5f11838f 442 /* Set ETH HAL state to Disabled */
mbed_official 235:685d5f11838f 443 heth->State= HAL_ETH_STATE_RESET;
mbed_official 235:685d5f11838f 444
mbed_official 235:685d5f11838f 445 /* Release Lock */
mbed_official 235:685d5f11838f 446 __HAL_UNLOCK(heth);
mbed_official 235:685d5f11838f 447
mbed_official 235:685d5f11838f 448 /* Return function status */
mbed_official 235:685d5f11838f 449 return HAL_OK;
mbed_official 235:685d5f11838f 450 }
mbed_official 235:685d5f11838f 451
mbed_official 235:685d5f11838f 452 /**
mbed_official 235:685d5f11838f 453 * @brief Initializes the DMA Tx descriptors in chain mode.
mbed_official 235:685d5f11838f 454 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 235:685d5f11838f 455 * the configuration information for ETHERNET module
mbed_official 235:685d5f11838f 456 * @param DMATxDescTab: Pointer to the first Tx desc list
mbed_official 235:685d5f11838f 457 * @param TxBuff: Pointer to the first TxBuffer list
mbed_official 235:685d5f11838f 458 * @param TxBuffCount: Number of the used Tx desc in the list
mbed_official 235:685d5f11838f 459 * @retval HAL status
mbed_official 235:685d5f11838f 460 */
mbed_official 235:685d5f11838f 461 HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t *TxBuff, uint32_t TxBuffCount)
mbed_official 235:685d5f11838f 462 {
mbed_official 235:685d5f11838f 463 uint32_t i = 0;
mbed_official 235:685d5f11838f 464 ETH_DMADescTypeDef *dmatxdesc;
mbed_official 235:685d5f11838f 465
mbed_official 235:685d5f11838f 466 /* Process Locked */
mbed_official 235:685d5f11838f 467 __HAL_LOCK(heth);
mbed_official 235:685d5f11838f 468
mbed_official 235:685d5f11838f 469 /* Set the ETH peripheral state to BUSY */
mbed_official 235:685d5f11838f 470 heth->State = HAL_ETH_STATE_BUSY;
mbed_official 235:685d5f11838f 471
mbed_official 235:685d5f11838f 472 /* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */
mbed_official 235:685d5f11838f 473 heth->TxDesc = DMATxDescTab;
mbed_official 235:685d5f11838f 474
mbed_official 235:685d5f11838f 475 /* Fill each DMATxDesc descriptor with the right values */
mbed_official 235:685d5f11838f 476 for(i=0; i < TxBuffCount; i++)
mbed_official 235:685d5f11838f 477 {
mbed_official 235:685d5f11838f 478 /* Get the pointer on the ith member of the Tx Desc list */
mbed_official 235:685d5f11838f 479 dmatxdesc = DMATxDescTab + i;
mbed_official 235:685d5f11838f 480
mbed_official 235:685d5f11838f 481 /* Set Second Address Chained bit */
mbed_official 235:685d5f11838f 482 dmatxdesc->Status = ETH_DMATXDESC_TCH;
mbed_official 235:685d5f11838f 483
mbed_official 235:685d5f11838f 484 /* Set Buffer1 address pointer */
mbed_official 235:685d5f11838f 485 dmatxdesc->Buffer1Addr = (uint32_t)(&TxBuff[i*ETH_TX_BUF_SIZE]);
mbed_official 235:685d5f11838f 486
mbed_official 235:685d5f11838f 487 if ((heth->Init).ChecksumMode == ETH_CHECKSUM_BY_HARDWARE)
mbed_official 235:685d5f11838f 488 {
mbed_official 235:685d5f11838f 489 /* Set the DMA Tx descriptors checksum insertion */
mbed_official 235:685d5f11838f 490 dmatxdesc->Status |= ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL;
mbed_official 235:685d5f11838f 491 }
mbed_official 235:685d5f11838f 492
mbed_official 235:685d5f11838f 493 /* Initialize the next descriptor with the Next Descriptor Polling Enable */
mbed_official 235:685d5f11838f 494 if(i < (TxBuffCount-1))
mbed_official 235:685d5f11838f 495 {
mbed_official 235:685d5f11838f 496 /* Set next descriptor address register with next descriptor base address */
mbed_official 235:685d5f11838f 497 dmatxdesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab+i+1);
mbed_official 235:685d5f11838f 498 }
mbed_official 235:685d5f11838f 499 else
mbed_official 235:685d5f11838f 500 {
mbed_official 235:685d5f11838f 501 /* For last descriptor, set next descriptor address register equal to the first descriptor base address */
mbed_official 235:685d5f11838f 502 dmatxdesc->Buffer2NextDescAddr = (uint32_t) DMATxDescTab;
mbed_official 235:685d5f11838f 503 }
mbed_official 235:685d5f11838f 504 }
mbed_official 235:685d5f11838f 505
mbed_official 235:685d5f11838f 506 /* Set Transmit Descriptor List Address Register */
mbed_official 235:685d5f11838f 507 (heth->Instance)->DMATDLAR = (uint32_t) DMATxDescTab;
mbed_official 235:685d5f11838f 508
mbed_official 235:685d5f11838f 509 /* Set ETH HAL State to Ready */
mbed_official 235:685d5f11838f 510 heth->State= HAL_ETH_STATE_READY;
mbed_official 235:685d5f11838f 511
mbed_official 235:685d5f11838f 512 /* Process Unlocked */
mbed_official 235:685d5f11838f 513 __HAL_UNLOCK(heth);
mbed_official 235:685d5f11838f 514
mbed_official 235:685d5f11838f 515 /* Return function status */
mbed_official 235:685d5f11838f 516 return HAL_OK;
mbed_official 235:685d5f11838f 517 }
mbed_official 235:685d5f11838f 518
mbed_official 235:685d5f11838f 519 /**
mbed_official 235:685d5f11838f 520 * @brief Initializes the DMA Rx descriptors in chain mode.
mbed_official 235:685d5f11838f 521 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 235:685d5f11838f 522 * the configuration information for ETHERNET module
mbed_official 235:685d5f11838f 523 * @param DMARxDescTab: Pointer to the first Rx desc list
mbed_official 235:685d5f11838f 524 * @param RxBuff: Pointer to the first RxBuffer list
mbed_official 235:685d5f11838f 525 * @param RxBuffCount: Number of the used Rx desc in the list
mbed_official 235:685d5f11838f 526 * @retval HAL status
mbed_official 235:685d5f11838f 527 */
mbed_official 235:685d5f11838f 528 HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount)
mbed_official 235:685d5f11838f 529 {
mbed_official 235:685d5f11838f 530 uint32_t i = 0;
mbed_official 235:685d5f11838f 531 ETH_DMADescTypeDef *DMARxDesc;
mbed_official 235:685d5f11838f 532
mbed_official 235:685d5f11838f 533 /* Process Locked */
mbed_official 235:685d5f11838f 534 __HAL_LOCK(heth);
mbed_official 235:685d5f11838f 535
mbed_official 235:685d5f11838f 536 /* Set the ETH peripheral state to BUSY */
mbed_official 235:685d5f11838f 537 heth->State = HAL_ETH_STATE_BUSY;
mbed_official 235:685d5f11838f 538
mbed_official 235:685d5f11838f 539 /* Set the Ethernet RxDesc pointer with the first one of the DMARxDescTab list */
mbed_official 235:685d5f11838f 540 heth->RxDesc = DMARxDescTab;
mbed_official 235:685d5f11838f 541
mbed_official 235:685d5f11838f 542 /* Fill each DMARxDesc descriptor with the right values */
mbed_official 235:685d5f11838f 543 for(i=0; i < RxBuffCount; i++)
mbed_official 235:685d5f11838f 544 {
mbed_official 235:685d5f11838f 545 /* Get the pointer on the ith member of the Rx Desc list */
mbed_official 235:685d5f11838f 546 DMARxDesc = DMARxDescTab+i;
mbed_official 235:685d5f11838f 547
mbed_official 235:685d5f11838f 548 /* Set Own bit of the Rx descriptor Status */
mbed_official 235:685d5f11838f 549 DMARxDesc->Status = ETH_DMARXDESC_OWN;
mbed_official 235:685d5f11838f 550
mbed_official 235:685d5f11838f 551 /* Set Buffer1 size and Second Address Chained bit */
mbed_official 235:685d5f11838f 552 DMARxDesc->ControlBufferSize = ETH_DMARXDESC_RCH | ETH_RX_BUF_SIZE;
mbed_official 235:685d5f11838f 553
mbed_official 235:685d5f11838f 554 /* Set Buffer1 address pointer */
mbed_official 235:685d5f11838f 555 DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff[i*ETH_RX_BUF_SIZE]);
mbed_official 235:685d5f11838f 556
mbed_official 235:685d5f11838f 557 if((heth->Init).RxMode == ETH_RXINTERRUPT_MODE)
mbed_official 235:685d5f11838f 558 {
mbed_official 235:685d5f11838f 559 /* Enable Ethernet DMA Rx Descriptor interrupt */
mbed_official 235:685d5f11838f 560 DMARxDesc->ControlBufferSize &= ~ETH_DMARXDESC_DIC;
mbed_official 235:685d5f11838f 561 }
mbed_official 235:685d5f11838f 562
mbed_official 235:685d5f11838f 563 /* Initialize the next descriptor with the Next Descriptor Polling Enable */
mbed_official 235:685d5f11838f 564 if(i < (RxBuffCount-1))
mbed_official 235:685d5f11838f 565 {
mbed_official 235:685d5f11838f 566 /* Set next descriptor address register with next descriptor base address */
mbed_official 235:685d5f11838f 567 DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab+i+1);
mbed_official 235:685d5f11838f 568 }
mbed_official 235:685d5f11838f 569 else
mbed_official 235:685d5f11838f 570 {
mbed_official 235:685d5f11838f 571 /* For last descriptor, set next descriptor address register equal to the first descriptor base address */
mbed_official 235:685d5f11838f 572 DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab);
mbed_official 235:685d5f11838f 573 }
mbed_official 235:685d5f11838f 574 }
mbed_official 235:685d5f11838f 575
mbed_official 235:685d5f11838f 576 /* Set Receive Descriptor List Address Register */
mbed_official 235:685d5f11838f 577 (heth->Instance)->DMARDLAR = (uint32_t) DMARxDescTab;
mbed_official 235:685d5f11838f 578
mbed_official 235:685d5f11838f 579 /* Set ETH HAL State to Ready */
mbed_official 235:685d5f11838f 580 heth->State= HAL_ETH_STATE_READY;
mbed_official 235:685d5f11838f 581
mbed_official 235:685d5f11838f 582 /* Process Unlocked */
mbed_official 235:685d5f11838f 583 __HAL_UNLOCK(heth);
mbed_official 235:685d5f11838f 584
mbed_official 235:685d5f11838f 585 /* Return function status */
mbed_official 235:685d5f11838f 586 return HAL_OK;
mbed_official 235:685d5f11838f 587 }
mbed_official 235:685d5f11838f 588
mbed_official 235:685d5f11838f 589 /**
mbed_official 235:685d5f11838f 590 * @brief Initializes the ETH MSP.
mbed_official 235:685d5f11838f 591 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 235:685d5f11838f 592 * the configuration information for ETHERNET module
mbed_official 235:685d5f11838f 593 * @retval None
mbed_official 235:685d5f11838f 594 */
mbed_official 235:685d5f11838f 595 __weak void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
mbed_official 235:685d5f11838f 596 {
mbed_official 235:685d5f11838f 597 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 235:685d5f11838f 598 the HAL_ETH_MspInit could be implemented in the user file
mbed_official 235:685d5f11838f 599 */
mbed_official 235:685d5f11838f 600 }
mbed_official 235:685d5f11838f 601
mbed_official 235:685d5f11838f 602 /**
mbed_official 235:685d5f11838f 603 * @brief DeInitializes ETH MSP.
mbed_official 235:685d5f11838f 604 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 235:685d5f11838f 605 * the configuration information for ETHERNET module
mbed_official 235:685d5f11838f 606 * @retval None
mbed_official 235:685d5f11838f 607 */
mbed_official 235:685d5f11838f 608 __weak void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
mbed_official 235:685d5f11838f 609 {
mbed_official 235:685d5f11838f 610 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 235:685d5f11838f 611 the HAL_ETH_MspDeInit could be implemented in the user file
mbed_official 235:685d5f11838f 612 */
mbed_official 235:685d5f11838f 613 }
mbed_official 235:685d5f11838f 614
mbed_official 235:685d5f11838f 615 /**
mbed_official 235:685d5f11838f 616 * @}
mbed_official 235:685d5f11838f 617 */
mbed_official 235:685d5f11838f 618
mbed_official 532:fe11edbda85c 619 /** @defgroup ETH_Exported_Functions_Group2 IO operation functions
mbed_official 235:685d5f11838f 620 * @brief Data transfers functions
mbed_official 235:685d5f11838f 621 *
mbed_official 235:685d5f11838f 622 @verbatim
mbed_official 235:685d5f11838f 623 ==============================================================================
mbed_official 235:685d5f11838f 624 ##### IO operation functions #####
mbed_official 235:685d5f11838f 625 ==============================================================================
mbed_official 235:685d5f11838f 626 [..] This section provides functions allowing to:
mbed_official 235:685d5f11838f 627 (+) Transmit a frame
mbed_official 235:685d5f11838f 628 HAL_ETH_TransmitFrame();
mbed_official 235:685d5f11838f 629 (+) Receive a frame
mbed_official 235:685d5f11838f 630 HAL_ETH_GetReceivedFrame();
mbed_official 235:685d5f11838f 631 HAL_ETH_GetReceivedFrame_IT();
mbed_official 235:685d5f11838f 632 (+) Read from an External PHY register
mbed_official 235:685d5f11838f 633 HAL_ETH_ReadPHYRegister();
mbed_official 235:685d5f11838f 634 (+) Write to an External PHY register
mbed_official 235:685d5f11838f 635 HAL_ETH_WritePHYRegister();
mbed_official 235:685d5f11838f 636
mbed_official 235:685d5f11838f 637 @endverbatim
mbed_official 235:685d5f11838f 638
mbed_official 235:685d5f11838f 639 * @{
mbed_official 235:685d5f11838f 640 */
mbed_official 235:685d5f11838f 641
mbed_official 235:685d5f11838f 642 /**
mbed_official 235:685d5f11838f 643 * @brief Sends an Ethernet frame.
mbed_official 235:685d5f11838f 644 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 235:685d5f11838f 645 * the configuration information for ETHERNET module
mbed_official 235:685d5f11838f 646 * @param FrameLength: Amount of data to be sent
mbed_official 235:685d5f11838f 647 * @retval HAL status
mbed_official 235:685d5f11838f 648 */
mbed_official 235:685d5f11838f 649 HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength)
mbed_official 235:685d5f11838f 650 {
mbed_official 235:685d5f11838f 651 uint32_t bufcount = 0, size = 0, i = 0;
mbed_official 235:685d5f11838f 652
mbed_official 235:685d5f11838f 653 /* Process Locked */
mbed_official 235:685d5f11838f 654 __HAL_LOCK(heth);
mbed_official 235:685d5f11838f 655
mbed_official 235:685d5f11838f 656 /* Set the ETH peripheral state to BUSY */
mbed_official 235:685d5f11838f 657 heth->State = HAL_ETH_STATE_BUSY;
mbed_official 235:685d5f11838f 658
mbed_official 235:685d5f11838f 659 if (FrameLength == 0)
mbed_official 235:685d5f11838f 660 {
mbed_official 235:685d5f11838f 661 /* Set ETH HAL state to READY */
mbed_official 235:685d5f11838f 662 heth->State = HAL_ETH_STATE_READY;
mbed_official 235:685d5f11838f 663
mbed_official 235:685d5f11838f 664 /* Process Unlocked */
mbed_official 235:685d5f11838f 665 __HAL_UNLOCK(heth);
mbed_official 235:685d5f11838f 666
mbed_official 235:685d5f11838f 667 return HAL_ERROR;
mbed_official 235:685d5f11838f 668 }
mbed_official 235:685d5f11838f 669
mbed_official 235:685d5f11838f 670 /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */
mbed_official 235:685d5f11838f 671 if(((heth->TxDesc)->Status & ETH_DMATXDESC_OWN) != (uint32_t)RESET)
mbed_official 235:685d5f11838f 672 {
mbed_official 235:685d5f11838f 673 /* OWN bit set */
mbed_official 235:685d5f11838f 674 heth->State = HAL_ETH_STATE_BUSY_TX;
mbed_official 235:685d5f11838f 675
mbed_official 235:685d5f11838f 676 /* Process Unlocked */
mbed_official 235:685d5f11838f 677 __HAL_UNLOCK(heth);
mbed_official 235:685d5f11838f 678
mbed_official 235:685d5f11838f 679 return HAL_ERROR;
mbed_official 235:685d5f11838f 680 }
mbed_official 235:685d5f11838f 681
mbed_official 235:685d5f11838f 682 /* Get the number of needed Tx buffers for the current frame */
mbed_official 235:685d5f11838f 683 if (FrameLength > ETH_TX_BUF_SIZE)
mbed_official 235:685d5f11838f 684 {
mbed_official 235:685d5f11838f 685 bufcount = FrameLength/ETH_TX_BUF_SIZE;
mbed_official 235:685d5f11838f 686 if (FrameLength % ETH_TX_BUF_SIZE)
mbed_official 235:685d5f11838f 687 {
mbed_official 235:685d5f11838f 688 bufcount++;
mbed_official 235:685d5f11838f 689 }
mbed_official 235:685d5f11838f 690 }
mbed_official 235:685d5f11838f 691 else
mbed_official 235:685d5f11838f 692 {
mbed_official 235:685d5f11838f 693 bufcount = 1;
mbed_official 235:685d5f11838f 694 }
mbed_official 235:685d5f11838f 695 if (bufcount == 1)
mbed_official 235:685d5f11838f 696 {
mbed_official 235:685d5f11838f 697 /* Set LAST and FIRST segment */
mbed_official 235:685d5f11838f 698 heth->TxDesc->Status |=ETH_DMATXDESC_FS|ETH_DMATXDESC_LS;
mbed_official 235:685d5f11838f 699 /* Set frame size */
mbed_official 235:685d5f11838f 700 heth->TxDesc->ControlBufferSize = (FrameLength & ETH_DMATXDESC_TBS1);
mbed_official 235:685d5f11838f 701 /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
mbed_official 235:685d5f11838f 702 heth->TxDesc->Status |= ETH_DMATXDESC_OWN;
mbed_official 235:685d5f11838f 703 /* Point to next descriptor */
mbed_official 235:685d5f11838f 704 heth->TxDesc= (ETH_DMADescTypeDef *)(heth->TxDesc->Buffer2NextDescAddr);
mbed_official 235:685d5f11838f 705 }
mbed_official 235:685d5f11838f 706 else
mbed_official 235:685d5f11838f 707 {
mbed_official 235:685d5f11838f 708 for (i=0; i< bufcount; i++)
mbed_official 235:685d5f11838f 709 {
mbed_official 235:685d5f11838f 710 /* Clear FIRST and LAST segment bits */
mbed_official 235:685d5f11838f 711 heth->TxDesc->Status &= ~(ETH_DMATXDESC_FS | ETH_DMATXDESC_LS);
mbed_official 235:685d5f11838f 712
mbed_official 235:685d5f11838f 713 if (i == 0)
mbed_official 235:685d5f11838f 714 {
mbed_official 235:685d5f11838f 715 /* Setting the first segment bit */
mbed_official 235:685d5f11838f 716 heth->TxDesc->Status |= ETH_DMATXDESC_FS;
mbed_official 235:685d5f11838f 717 }
mbed_official 235:685d5f11838f 718
mbed_official 235:685d5f11838f 719 /* Program size */
mbed_official 235:685d5f11838f 720 heth->TxDesc->ControlBufferSize = (ETH_TX_BUF_SIZE & ETH_DMATXDESC_TBS1);
mbed_official 235:685d5f11838f 721
mbed_official 235:685d5f11838f 722 if (i == (bufcount-1))
mbed_official 235:685d5f11838f 723 {
mbed_official 235:685d5f11838f 724 /* Setting the last segment bit */
mbed_official 235:685d5f11838f 725 heth->TxDesc->Status |= ETH_DMATXDESC_LS;
mbed_official 235:685d5f11838f 726 size = FrameLength - (bufcount-1)*ETH_TX_BUF_SIZE;
mbed_official 235:685d5f11838f 727 heth->TxDesc->ControlBufferSize = (size & ETH_DMATXDESC_TBS1);
mbed_official 235:685d5f11838f 728 }
mbed_official 235:685d5f11838f 729
mbed_official 235:685d5f11838f 730 /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
mbed_official 235:685d5f11838f 731 heth->TxDesc->Status |= ETH_DMATXDESC_OWN;
mbed_official 235:685d5f11838f 732 /* point to next descriptor */
mbed_official 235:685d5f11838f 733 heth->TxDesc = (ETH_DMADescTypeDef *)(heth->TxDesc->Buffer2NextDescAddr);
mbed_official 235:685d5f11838f 734 }
mbed_official 235:685d5f11838f 735 }
mbed_official 235:685d5f11838f 736
mbed_official 235:685d5f11838f 737 /* When Tx Buffer unavailable flag is set: clear it and resume transmission */
mbed_official 235:685d5f11838f 738 if (((heth->Instance)->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET)
mbed_official 235:685d5f11838f 739 {
mbed_official 235:685d5f11838f 740 /* Clear TBUS ETHERNET DMA flag */
mbed_official 235:685d5f11838f 741 (heth->Instance)->DMASR = ETH_DMASR_TBUS;
mbed_official 235:685d5f11838f 742 /* Resume DMA transmission*/
mbed_official 235:685d5f11838f 743 (heth->Instance)->DMATPDR = 0;
mbed_official 235:685d5f11838f 744 }
mbed_official 235:685d5f11838f 745
mbed_official 235:685d5f11838f 746 /* Set ETH HAL State to Ready */
mbed_official 235:685d5f11838f 747 heth->State = HAL_ETH_STATE_READY;
mbed_official 235:685d5f11838f 748
mbed_official 235:685d5f11838f 749 /* Process Unlocked */
mbed_official 235:685d5f11838f 750 __HAL_UNLOCK(heth);
mbed_official 235:685d5f11838f 751
mbed_official 235:685d5f11838f 752 /* Return function status */
mbed_official 235:685d5f11838f 753 return HAL_OK;
mbed_official 235:685d5f11838f 754 }
mbed_official 235:685d5f11838f 755
mbed_official 235:685d5f11838f 756 /**
mbed_official 235:685d5f11838f 757 * @brief Checks for received frames.
mbed_official 235:685d5f11838f 758 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 235:685d5f11838f 759 * the configuration information for ETHERNET module
mbed_official 235:685d5f11838f 760 * @retval HAL status
mbed_official 235:685d5f11838f 761 */
mbed_official 235:685d5f11838f 762 HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth)
mbed_official 235:685d5f11838f 763 {
mbed_official 235:685d5f11838f 764 uint32_t framelength = 0;
mbed_official 235:685d5f11838f 765
mbed_official 235:685d5f11838f 766 /* Process Locked */
mbed_official 235:685d5f11838f 767 __HAL_LOCK(heth);
mbed_official 235:685d5f11838f 768
mbed_official 235:685d5f11838f 769 /* Check the ETH state to BUSY */
mbed_official 235:685d5f11838f 770 heth->State = HAL_ETH_STATE_BUSY;
mbed_official 235:685d5f11838f 771
mbed_official 235:685d5f11838f 772 /* Check if segment is not owned by DMA */
mbed_official 235:685d5f11838f 773 /* (((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && ((heth->RxDesc->Status & ETH_DMARXDESC_LS) != (uint32_t)RESET)) */
mbed_official 235:685d5f11838f 774 if(((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET))
mbed_official 235:685d5f11838f 775 {
mbed_official 235:685d5f11838f 776 /* Check if last segment */
mbed_official 235:685d5f11838f 777 if(((heth->RxDesc->Status & ETH_DMARXDESC_LS) != (uint32_t)RESET))
mbed_official 235:685d5f11838f 778 {
mbed_official 235:685d5f11838f 779 /* increment segment count */
mbed_official 235:685d5f11838f 780 (heth->RxFrameInfos).SegCount++;
mbed_official 235:685d5f11838f 781
mbed_official 235:685d5f11838f 782 /* Check if last segment is first segment: one segment contains the frame */
mbed_official 235:685d5f11838f 783 if ((heth->RxFrameInfos).SegCount == 1)
mbed_official 235:685d5f11838f 784 {
mbed_official 235:685d5f11838f 785 (heth->RxFrameInfos).FSRxDesc =heth->RxDesc;
mbed_official 235:685d5f11838f 786 }
mbed_official 235:685d5f11838f 787
mbed_official 235:685d5f11838f 788 heth->RxFrameInfos.LSRxDesc = heth->RxDesc;
mbed_official 235:685d5f11838f 789
mbed_official 235:685d5f11838f 790 /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
mbed_official 235:685d5f11838f 791 framelength = (((heth->RxDesc)->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4;
mbed_official 235:685d5f11838f 792 heth->RxFrameInfos.length = framelength;
mbed_official 235:685d5f11838f 793
mbed_official 235:685d5f11838f 794 /* Get the address of the buffer start address */
mbed_official 235:685d5f11838f 795 heth->RxFrameInfos.buffer = ((heth->RxFrameInfos).FSRxDesc)->Buffer1Addr;
mbed_official 235:685d5f11838f 796 /* point to next descriptor */
mbed_official 235:685d5f11838f 797 heth->RxDesc = (ETH_DMADescTypeDef*) ((heth->RxDesc)->Buffer2NextDescAddr);
mbed_official 235:685d5f11838f 798
mbed_official 235:685d5f11838f 799 /* Set HAL State to Ready */
mbed_official 235:685d5f11838f 800 heth->State = HAL_ETH_STATE_READY;
mbed_official 235:685d5f11838f 801
mbed_official 235:685d5f11838f 802 /* Process Unlocked */
mbed_official 235:685d5f11838f 803 __HAL_UNLOCK(heth);
mbed_official 235:685d5f11838f 804
mbed_official 235:685d5f11838f 805 /* Return function status */
mbed_official 235:685d5f11838f 806 return HAL_OK;
mbed_official 235:685d5f11838f 807 }
mbed_official 235:685d5f11838f 808 /* Check if first segment */
mbed_official 235:685d5f11838f 809 else if((heth->RxDesc->Status & ETH_DMARXDESC_FS) != (uint32_t)RESET)
mbed_official 235:685d5f11838f 810 {
mbed_official 235:685d5f11838f 811 (heth->RxFrameInfos).FSRxDesc = heth->RxDesc;
mbed_official 384:ef87175507f1 812 (heth->RxFrameInfos).LSRxDesc = HAL_NULL;
mbed_official 235:685d5f11838f 813 (heth->RxFrameInfos).SegCount = 1;
mbed_official 235:685d5f11838f 814 /* Point to next descriptor */
mbed_official 235:685d5f11838f 815 heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
mbed_official 235:685d5f11838f 816 }
mbed_official 235:685d5f11838f 817 /* Check if intermediate segment */
mbed_official 235:685d5f11838f 818 else
mbed_official 235:685d5f11838f 819 {
mbed_official 235:685d5f11838f 820 (heth->RxFrameInfos).SegCount++;
mbed_official 235:685d5f11838f 821 /* Point to next descriptor */
mbed_official 235:685d5f11838f 822 heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
mbed_official 235:685d5f11838f 823 }
mbed_official 235:685d5f11838f 824 }
mbed_official 235:685d5f11838f 825
mbed_official 235:685d5f11838f 826 /* Set ETH HAL State to Ready */
mbed_official 235:685d5f11838f 827 heth->State = HAL_ETH_STATE_READY;
mbed_official 235:685d5f11838f 828
mbed_official 235:685d5f11838f 829 /* Process Unlocked */
mbed_official 235:685d5f11838f 830 __HAL_UNLOCK(heth);
mbed_official 235:685d5f11838f 831
mbed_official 235:685d5f11838f 832 /* Return function status */
mbed_official 235:685d5f11838f 833 return HAL_ERROR;
mbed_official 235:685d5f11838f 834 }
mbed_official 235:685d5f11838f 835
mbed_official 235:685d5f11838f 836 /**
mbed_official 235:685d5f11838f 837 * @brief Gets the Received frame in interrupt mode.
mbed_official 235:685d5f11838f 838 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 235:685d5f11838f 839 * the configuration information for ETHERNET module
mbed_official 235:685d5f11838f 840 * @retval HAL status
mbed_official 235:685d5f11838f 841 */
mbed_official 235:685d5f11838f 842 HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth)
mbed_official 235:685d5f11838f 843 {
mbed_official 235:685d5f11838f 844 uint32_t descriptorscancounter = 0;
mbed_official 235:685d5f11838f 845
mbed_official 235:685d5f11838f 846 /* Process Locked */
mbed_official 235:685d5f11838f 847 __HAL_LOCK(heth);
mbed_official 235:685d5f11838f 848
mbed_official 235:685d5f11838f 849 /* Set ETH HAL State to BUSY */
mbed_official 235:685d5f11838f 850 heth->State = HAL_ETH_STATE_BUSY;
mbed_official 235:685d5f11838f 851
mbed_official 235:685d5f11838f 852 /* Scan descriptors owned by CPU */
mbed_official 235:685d5f11838f 853 while (((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && (descriptorscancounter < ETH_RXBUFNB))
mbed_official 235:685d5f11838f 854 {
mbed_official 235:685d5f11838f 855 /* Just for security */
mbed_official 235:685d5f11838f 856 descriptorscancounter++;
mbed_official 235:685d5f11838f 857
mbed_official 235:685d5f11838f 858 /* Check if first segment in frame */
mbed_official 235:685d5f11838f 859 /* ((heth->RxDesc->Status & ETH_DMARXDESC_FS) != (uint32_t)RESET) && ((heth->RxDesc->Status & ETH_DMARXDESC_LS) == (uint32_t)RESET)) */
mbed_official 235:685d5f11838f 860 if((heth->RxDesc->Status & (ETH_DMARXDESC_FS | ETH_DMARXDESC_LS)) == (uint32_t)ETH_DMARXDESC_FS)
mbed_official 235:685d5f11838f 861 {
mbed_official 235:685d5f11838f 862 heth->RxFrameInfos.FSRxDesc = heth->RxDesc;
mbed_official 235:685d5f11838f 863 heth->RxFrameInfos.SegCount = 1;
mbed_official 235:685d5f11838f 864 /* Point to next descriptor */
mbed_official 235:685d5f11838f 865 heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
mbed_official 235:685d5f11838f 866 }
mbed_official 235:685d5f11838f 867 /* Check if intermediate segment */
mbed_official 235:685d5f11838f 868 /* ((heth->RxDesc->Status & ETH_DMARXDESC_LS) == (uint32_t)RESET)&& ((heth->RxDesc->Status & ETH_DMARXDESC_FS) == (uint32_t)RESET)) */
mbed_official 235:685d5f11838f 869 else if ((heth->RxDesc->Status & (ETH_DMARXDESC_LS | ETH_DMARXDESC_FS)) == (uint32_t)RESET)
mbed_official 235:685d5f11838f 870 {
mbed_official 235:685d5f11838f 871 /* Increment segment count */
mbed_official 235:685d5f11838f 872 (heth->RxFrameInfos.SegCount)++;
mbed_official 235:685d5f11838f 873 /* Point to next descriptor */
mbed_official 235:685d5f11838f 874 heth->RxDesc = (ETH_DMADescTypeDef*)(heth->RxDesc->Buffer2NextDescAddr);
mbed_official 235:685d5f11838f 875 }
mbed_official 235:685d5f11838f 876 /* Should be last segment */
mbed_official 235:685d5f11838f 877 else
mbed_official 235:685d5f11838f 878 {
mbed_official 235:685d5f11838f 879 /* Last segment */
mbed_official 235:685d5f11838f 880 heth->RxFrameInfos.LSRxDesc = heth->RxDesc;
mbed_official 235:685d5f11838f 881
mbed_official 235:685d5f11838f 882 /* Increment segment count */
mbed_official 235:685d5f11838f 883 (heth->RxFrameInfos.SegCount)++;
mbed_official 235:685d5f11838f 884
mbed_official 235:685d5f11838f 885 /* Check if last segment is first segment: one segment contains the frame */
mbed_official 235:685d5f11838f 886 if ((heth->RxFrameInfos.SegCount) == 1)
mbed_official 235:685d5f11838f 887 {
mbed_official 235:685d5f11838f 888 heth->RxFrameInfos.FSRxDesc = heth->RxDesc;
mbed_official 235:685d5f11838f 889 }
mbed_official 235:685d5f11838f 890
mbed_official 235:685d5f11838f 891 /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
mbed_official 235:685d5f11838f 892 heth->RxFrameInfos.length = (((heth->RxDesc)->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4;
mbed_official 235:685d5f11838f 893
mbed_official 235:685d5f11838f 894 /* Get the address of the buffer start address */
mbed_official 235:685d5f11838f 895 heth->RxFrameInfos.buffer =((heth->RxFrameInfos).FSRxDesc)->Buffer1Addr;
mbed_official 235:685d5f11838f 896
mbed_official 235:685d5f11838f 897 /* Point to next descriptor */
mbed_official 235:685d5f11838f 898 heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
mbed_official 235:685d5f11838f 899
mbed_official 235:685d5f11838f 900 /* Set HAL State to Ready */
mbed_official 235:685d5f11838f 901 heth->State = HAL_ETH_STATE_READY;
mbed_official 235:685d5f11838f 902
mbed_official 235:685d5f11838f 903 /* Process Unlocked */
mbed_official 235:685d5f11838f 904 __HAL_UNLOCK(heth);
mbed_official 235:685d5f11838f 905
mbed_official 235:685d5f11838f 906 /* Return function status */
mbed_official 235:685d5f11838f 907 return HAL_OK;
mbed_official 235:685d5f11838f 908 }
mbed_official 235:685d5f11838f 909 }
mbed_official 235:685d5f11838f 910
mbed_official 235:685d5f11838f 911 /* Set HAL State to Ready */
mbed_official 235:685d5f11838f 912 heth->State = HAL_ETH_STATE_READY;
mbed_official 235:685d5f11838f 913
mbed_official 235:685d5f11838f 914 /* Process Unlocked */
mbed_official 235:685d5f11838f 915 __HAL_UNLOCK(heth);
mbed_official 235:685d5f11838f 916
mbed_official 235:685d5f11838f 917 /* Return function status */
mbed_official 235:685d5f11838f 918 return HAL_ERROR;
mbed_official 235:685d5f11838f 919 }
mbed_official 235:685d5f11838f 920
mbed_official 235:685d5f11838f 921 /**
mbed_official 235:685d5f11838f 922 * @brief This function handles ETH interrupt request.
mbed_official 235:685d5f11838f 923 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 235:685d5f11838f 924 * the configuration information for ETHERNET module
mbed_official 235:685d5f11838f 925 * @retval HAL status
mbed_official 235:685d5f11838f 926 */
mbed_official 235:685d5f11838f 927 void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth)
mbed_official 235:685d5f11838f 928 {
mbed_official 235:685d5f11838f 929 /* Frame received */
mbed_official 235:685d5f11838f 930 if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_R))
mbed_official 235:685d5f11838f 931 {
mbed_official 235:685d5f11838f 932 /* Receive complete callback */
mbed_official 235:685d5f11838f 933 HAL_ETH_RxCpltCallback(heth);
mbed_official 235:685d5f11838f 934
mbed_official 235:685d5f11838f 935 /* Clear the Eth DMA Rx IT pending bits */
mbed_official 235:685d5f11838f 936 __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_R);
mbed_official 235:685d5f11838f 937
mbed_official 235:685d5f11838f 938 /* Set HAL State to Ready */
mbed_official 235:685d5f11838f 939 heth->State = HAL_ETH_STATE_READY;
mbed_official 235:685d5f11838f 940
mbed_official 235:685d5f11838f 941 /* Process Unlocked */
mbed_official 235:685d5f11838f 942 __HAL_UNLOCK(heth);
mbed_official 235:685d5f11838f 943
mbed_official 235:685d5f11838f 944 }
mbed_official 235:685d5f11838f 945 /* Frame transmitted */
mbed_official 235:685d5f11838f 946 else if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_T))
mbed_official 235:685d5f11838f 947 {
mbed_official 235:685d5f11838f 948 /* Transfer complete callback */
mbed_official 235:685d5f11838f 949 HAL_ETH_TxCpltCallback(heth);
mbed_official 235:685d5f11838f 950
mbed_official 235:685d5f11838f 951 /* Clear the Eth DMA Tx IT pending bits */
mbed_official 235:685d5f11838f 952 __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_T);
mbed_official 235:685d5f11838f 953
mbed_official 235:685d5f11838f 954 /* Set HAL State to Ready */
mbed_official 235:685d5f11838f 955 heth->State = HAL_ETH_STATE_READY;
mbed_official 235:685d5f11838f 956
mbed_official 235:685d5f11838f 957 /* Process Unlocked */
mbed_official 235:685d5f11838f 958 __HAL_UNLOCK(heth);
mbed_official 235:685d5f11838f 959 }
mbed_official 235:685d5f11838f 960
mbed_official 235:685d5f11838f 961 /* Clear the interrupt flags */
mbed_official 235:685d5f11838f 962 __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_NIS);
mbed_official 235:685d5f11838f 963
mbed_official 235:685d5f11838f 964 /* ETH DMA Error */
mbed_official 235:685d5f11838f 965 if(__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_AIS))
mbed_official 235:685d5f11838f 966 {
mbed_official 235:685d5f11838f 967 /* Ethernet Error callback */
mbed_official 235:685d5f11838f 968 HAL_ETH_ErrorCallback(heth);
mbed_official 235:685d5f11838f 969
mbed_official 235:685d5f11838f 970 /* Clear the interrupt flags */
mbed_official 235:685d5f11838f 971 __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_FLAG_AIS);
mbed_official 235:685d5f11838f 972
mbed_official 235:685d5f11838f 973 /* Set HAL State to Ready */
mbed_official 235:685d5f11838f 974 heth->State = HAL_ETH_STATE_READY;
mbed_official 235:685d5f11838f 975
mbed_official 235:685d5f11838f 976 /* Process Unlocked */
mbed_official 235:685d5f11838f 977 __HAL_UNLOCK(heth);
mbed_official 235:685d5f11838f 978 }
mbed_official 235:685d5f11838f 979 }
mbed_official 235:685d5f11838f 980
mbed_official 235:685d5f11838f 981 /**
mbed_official 235:685d5f11838f 982 * @brief Tx Transfer completed callbacks.
mbed_official 235:685d5f11838f 983 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 235:685d5f11838f 984 * the configuration information for ETHERNET module
mbed_official 235:685d5f11838f 985 * @retval None
mbed_official 235:685d5f11838f 986 */
mbed_official 235:685d5f11838f 987 __weak void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth)
mbed_official 235:685d5f11838f 988 {
mbed_official 235:685d5f11838f 989 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 235:685d5f11838f 990 the HAL_ETH_TxCpltCallback could be implemented in the user file
mbed_official 235:685d5f11838f 991 */
mbed_official 235:685d5f11838f 992 }
mbed_official 235:685d5f11838f 993
mbed_official 235:685d5f11838f 994 /**
mbed_official 235:685d5f11838f 995 * @brief Rx Transfer completed callbacks.
mbed_official 235:685d5f11838f 996 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 235:685d5f11838f 997 * the configuration information for ETHERNET module
mbed_official 235:685d5f11838f 998 * @retval None
mbed_official 235:685d5f11838f 999 */
mbed_official 235:685d5f11838f 1000 __weak void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth)
mbed_official 235:685d5f11838f 1001 {
mbed_official 235:685d5f11838f 1002 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 235:685d5f11838f 1003 the HAL_ETH_TxCpltCallback could be implemented in the user file
mbed_official 235:685d5f11838f 1004 */
mbed_official 235:685d5f11838f 1005 }
mbed_official 235:685d5f11838f 1006
mbed_official 235:685d5f11838f 1007 /**
mbed_official 235:685d5f11838f 1008 * @brief Ethernet transfer error callbacks
mbed_official 235:685d5f11838f 1009 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 235:685d5f11838f 1010 * the configuration information for ETHERNET module
mbed_official 235:685d5f11838f 1011 * @retval None
mbed_official 235:685d5f11838f 1012 */
mbed_official 235:685d5f11838f 1013 __weak void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth)
mbed_official 235:685d5f11838f 1014 {
mbed_official 235:685d5f11838f 1015 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 235:685d5f11838f 1016 the HAL_ETH_TxCpltCallback could be implemented in the user file
mbed_official 235:685d5f11838f 1017 */
mbed_official 235:685d5f11838f 1018 }
mbed_official 235:685d5f11838f 1019
mbed_official 235:685d5f11838f 1020 /**
mbed_official 235:685d5f11838f 1021 * @brief Reads a PHY register
mbed_official 235:685d5f11838f 1022 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 235:685d5f11838f 1023 * the configuration information for ETHERNET module
mbed_official 235:685d5f11838f 1024 * @param PHYReg: PHY register address, is the index of one of the 32 PHY register.
mbed_official 235:685d5f11838f 1025 * This parameter can be one of the following values:
mbed_official 235:685d5f11838f 1026 * PHY_BCR: Transceiver Basic Control Register,
mbed_official 235:685d5f11838f 1027 * PHY_BSR: Transceiver Basic Status Register.
mbed_official 235:685d5f11838f 1028 * More PHY register could be read depending on the used PHY
mbed_official 235:685d5f11838f 1029 * @param RegValue: PHY register value
mbed_official 235:685d5f11838f 1030 * @retval HAL status
mbed_official 235:685d5f11838f 1031 */
mbed_official 235:685d5f11838f 1032 HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue)
mbed_official 235:685d5f11838f 1033 {
mbed_official 532:fe11edbda85c 1034 uint32_t tmpreg1 = 0;
mbed_official 235:685d5f11838f 1035 uint32_t tickstart = 0;
mbed_official 235:685d5f11838f 1036
mbed_official 235:685d5f11838f 1037 /* Check parameters */
mbed_official 235:685d5f11838f 1038 assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress));
mbed_official 235:685d5f11838f 1039
mbed_official 235:685d5f11838f 1040 /* Check the ETH peripheral state */
mbed_official 235:685d5f11838f 1041 if(heth->State == HAL_ETH_STATE_BUSY_RD)
mbed_official 235:685d5f11838f 1042 {
mbed_official 235:685d5f11838f 1043 return HAL_BUSY;
mbed_official 235:685d5f11838f 1044 }
mbed_official 235:685d5f11838f 1045 /* Set ETH HAL State to BUSY_RD */
mbed_official 235:685d5f11838f 1046 heth->State = HAL_ETH_STATE_BUSY_RD;
mbed_official 235:685d5f11838f 1047
mbed_official 235:685d5f11838f 1048 /* Get the ETHERNET MACMIIAR value */
mbed_official 532:fe11edbda85c 1049 tmpreg1 = heth->Instance->MACMIIAR;
mbed_official 235:685d5f11838f 1050
mbed_official 235:685d5f11838f 1051 /* Keep only the CSR Clock Range CR[2:0] bits value */
mbed_official 532:fe11edbda85c 1052 tmpreg1 &= ~ETH_MACMIIAR_CR_MASK;
mbed_official 235:685d5f11838f 1053
mbed_official 235:685d5f11838f 1054 /* Prepare the MII address register value */
mbed_official 532:fe11edbda85c 1055 tmpreg1 |=(((uint32_t)heth->Init.PhyAddress << 11) & ETH_MACMIIAR_PA); /* Set the PHY device address */
mbed_official 532:fe11edbda85c 1056 tmpreg1 |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR); /* Set the PHY register address */
mbed_official 532:fe11edbda85c 1057 tmpreg1 &= ~ETH_MACMIIAR_MW; /* Set the read mode */
mbed_official 532:fe11edbda85c 1058 tmpreg1 |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */
mbed_official 235:685d5f11838f 1059
mbed_official 235:685d5f11838f 1060 /* Write the result value into the MII Address register */
mbed_official 532:fe11edbda85c 1061 heth->Instance->MACMIIAR = tmpreg1;
mbed_official 235:685d5f11838f 1062
mbed_official 235:685d5f11838f 1063 /* Get tick */
mbed_official 235:685d5f11838f 1064 tickstart = HAL_GetTick();
mbed_official 235:685d5f11838f 1065
mbed_official 235:685d5f11838f 1066 /* Check for the Busy flag */
mbed_official 532:fe11edbda85c 1067 while((tmpreg1 & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB)
mbed_official 235:685d5f11838f 1068 {
mbed_official 235:685d5f11838f 1069 /* Check for the Timeout */
mbed_official 235:685d5f11838f 1070 if((HAL_GetTick() - tickstart ) > PHY_READ_TO)
mbed_official 235:685d5f11838f 1071 {
mbed_official 235:685d5f11838f 1072 heth->State= HAL_ETH_STATE_READY;
mbed_official 235:685d5f11838f 1073
mbed_official 235:685d5f11838f 1074 /* Process Unlocked */
mbed_official 235:685d5f11838f 1075 __HAL_UNLOCK(heth);
mbed_official 235:685d5f11838f 1076
mbed_official 235:685d5f11838f 1077 return HAL_TIMEOUT;
mbed_official 235:685d5f11838f 1078 }
mbed_official 235:685d5f11838f 1079
mbed_official 532:fe11edbda85c 1080 tmpreg1 = heth->Instance->MACMIIAR;
mbed_official 235:685d5f11838f 1081 }
mbed_official 235:685d5f11838f 1082
mbed_official 235:685d5f11838f 1083 /* Get MACMIIDR value */
mbed_official 235:685d5f11838f 1084 *RegValue = (uint16_t)(heth->Instance->MACMIIDR);
mbed_official 235:685d5f11838f 1085
mbed_official 235:685d5f11838f 1086 /* Set ETH HAL State to READY */
mbed_official 235:685d5f11838f 1087 heth->State = HAL_ETH_STATE_READY;
mbed_official 235:685d5f11838f 1088
mbed_official 235:685d5f11838f 1089 /* Return function status */
mbed_official 235:685d5f11838f 1090 return HAL_OK;
mbed_official 235:685d5f11838f 1091 }
mbed_official 235:685d5f11838f 1092
mbed_official 235:685d5f11838f 1093 /**
mbed_official 235:685d5f11838f 1094 * @brief Writes to a PHY register.
mbed_official 235:685d5f11838f 1095 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 235:685d5f11838f 1096 * the configuration information for ETHERNET module
mbed_official 235:685d5f11838f 1097 * @param PHYReg: PHY register address, is the index of one of the 32 PHY register.
mbed_official 235:685d5f11838f 1098 * This parameter can be one of the following values:
mbed_official 235:685d5f11838f 1099 * PHY_BCR: Transceiver Control Register.
mbed_official 235:685d5f11838f 1100 * More PHY register could be written depending on the used PHY
mbed_official 235:685d5f11838f 1101 * @param RegValue: the value to write
mbed_official 235:685d5f11838f 1102 * @retval HAL status
mbed_official 235:685d5f11838f 1103 */
mbed_official 235:685d5f11838f 1104 HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue)
mbed_official 235:685d5f11838f 1105 {
mbed_official 532:fe11edbda85c 1106 uint32_t tmpreg1 = 0;
mbed_official 235:685d5f11838f 1107 uint32_t tickstart = 0;
mbed_official 235:685d5f11838f 1108
mbed_official 235:685d5f11838f 1109 /* Check parameters */
mbed_official 235:685d5f11838f 1110 assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress));
mbed_official 235:685d5f11838f 1111
mbed_official 235:685d5f11838f 1112 /* Check the ETH peripheral state */
mbed_official 235:685d5f11838f 1113 if(heth->State == HAL_ETH_STATE_BUSY_WR)
mbed_official 235:685d5f11838f 1114 {
mbed_official 235:685d5f11838f 1115 return HAL_BUSY;
mbed_official 235:685d5f11838f 1116 }
mbed_official 235:685d5f11838f 1117 /* Set ETH HAL State to BUSY_WR */
mbed_official 235:685d5f11838f 1118 heth->State = HAL_ETH_STATE_BUSY_WR;
mbed_official 235:685d5f11838f 1119
mbed_official 235:685d5f11838f 1120 /* Get the ETHERNET MACMIIAR value */
mbed_official 532:fe11edbda85c 1121 tmpreg1 = heth->Instance->MACMIIAR;
mbed_official 235:685d5f11838f 1122
mbed_official 235:685d5f11838f 1123 /* Keep only the CSR Clock Range CR[2:0] bits value */
mbed_official 532:fe11edbda85c 1124 tmpreg1 &= ~ETH_MACMIIAR_CR_MASK;
mbed_official 235:685d5f11838f 1125
mbed_official 235:685d5f11838f 1126 /* Prepare the MII register address value */
mbed_official 532:fe11edbda85c 1127 tmpreg1 |=(((uint32_t)heth->Init.PhyAddress<<11) & ETH_MACMIIAR_PA); /* Set the PHY device address */
mbed_official 532:fe11edbda85c 1128 tmpreg1 |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR); /* Set the PHY register address */
mbed_official 532:fe11edbda85c 1129 tmpreg1 |= ETH_MACMIIAR_MW; /* Set the write mode */
mbed_official 532:fe11edbda85c 1130 tmpreg1 |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */
mbed_official 235:685d5f11838f 1131
mbed_official 235:685d5f11838f 1132 /* Give the value to the MII data register */
mbed_official 235:685d5f11838f 1133 heth->Instance->MACMIIDR = (uint16_t)RegValue;
mbed_official 235:685d5f11838f 1134
mbed_official 235:685d5f11838f 1135 /* Write the result value into the MII Address register */
mbed_official 532:fe11edbda85c 1136 heth->Instance->MACMIIAR = tmpreg1;
mbed_official 235:685d5f11838f 1137
mbed_official 235:685d5f11838f 1138 /* Get tick */
mbed_official 235:685d5f11838f 1139 tickstart = HAL_GetTick();
mbed_official 235:685d5f11838f 1140
mbed_official 235:685d5f11838f 1141 /* Check for the Busy flag */
mbed_official 532:fe11edbda85c 1142 while((tmpreg1 & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB)
mbed_official 235:685d5f11838f 1143 {
mbed_official 235:685d5f11838f 1144 /* Check for the Timeout */
mbed_official 235:685d5f11838f 1145 if((HAL_GetTick() - tickstart ) > PHY_WRITE_TO)
mbed_official 235:685d5f11838f 1146 {
mbed_official 235:685d5f11838f 1147 heth->State= HAL_ETH_STATE_READY;
mbed_official 235:685d5f11838f 1148
mbed_official 235:685d5f11838f 1149 /* Process Unlocked */
mbed_official 235:685d5f11838f 1150 __HAL_UNLOCK(heth);
mbed_official 235:685d5f11838f 1151
mbed_official 235:685d5f11838f 1152 return HAL_TIMEOUT;
mbed_official 235:685d5f11838f 1153 }
mbed_official 235:685d5f11838f 1154
mbed_official 532:fe11edbda85c 1155 tmpreg1 = heth->Instance->MACMIIAR;
mbed_official 235:685d5f11838f 1156 }
mbed_official 235:685d5f11838f 1157
mbed_official 235:685d5f11838f 1158 /* Set ETH HAL State to READY */
mbed_official 235:685d5f11838f 1159 heth->State = HAL_ETH_STATE_READY;
mbed_official 235:685d5f11838f 1160
mbed_official 235:685d5f11838f 1161 /* Return function status */
mbed_official 235:685d5f11838f 1162 return HAL_OK;
mbed_official 235:685d5f11838f 1163 }
mbed_official 235:685d5f11838f 1164
mbed_official 235:685d5f11838f 1165 /**
mbed_official 235:685d5f11838f 1166 * @}
mbed_official 235:685d5f11838f 1167 */
mbed_official 235:685d5f11838f 1168
mbed_official 532:fe11edbda85c 1169 /** @defgroup ETH_Exported_Functions_Group3 Peripheral Control functions
mbed_official 235:685d5f11838f 1170 * @brief Peripheral Control functions
mbed_official 235:685d5f11838f 1171 *
mbed_official 235:685d5f11838f 1172 @verbatim
mbed_official 235:685d5f11838f 1173 ===============================================================================
mbed_official 235:685d5f11838f 1174 ##### Peripheral Control functions #####
mbed_official 235:685d5f11838f 1175 ===============================================================================
mbed_official 235:685d5f11838f 1176 [..] This section provides functions allowing to:
mbed_official 235:685d5f11838f 1177 (+) Enable MAC and DMA transmission and reception.
mbed_official 235:685d5f11838f 1178 HAL_ETH_Start();
mbed_official 235:685d5f11838f 1179 (+) Disable MAC and DMA transmission and reception.
mbed_official 235:685d5f11838f 1180 HAL_ETH_Stop();
mbed_official 235:685d5f11838f 1181 (+) Set the MAC configuration in runtime mode
mbed_official 235:685d5f11838f 1182 HAL_ETH_ConfigMAC();
mbed_official 235:685d5f11838f 1183 (+) Set the DMA configuration in runtime mode
mbed_official 235:685d5f11838f 1184 HAL_ETH_ConfigDMA();
mbed_official 235:685d5f11838f 1185
mbed_official 235:685d5f11838f 1186 @endverbatim
mbed_official 235:685d5f11838f 1187 * @{
mbed_official 235:685d5f11838f 1188 */
mbed_official 235:685d5f11838f 1189
mbed_official 235:685d5f11838f 1190 /**
mbed_official 235:685d5f11838f 1191 * @brief Enables Ethernet MAC and DMA reception/transmission
mbed_official 235:685d5f11838f 1192 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 235:685d5f11838f 1193 * the configuration information for ETHERNET module
mbed_official 235:685d5f11838f 1194 * @retval HAL status
mbed_official 235:685d5f11838f 1195 */
mbed_official 235:685d5f11838f 1196 HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth)
mbed_official 235:685d5f11838f 1197 {
mbed_official 235:685d5f11838f 1198 /* Process Locked */
mbed_official 235:685d5f11838f 1199 __HAL_LOCK(heth);
mbed_official 235:685d5f11838f 1200
mbed_official 235:685d5f11838f 1201 /* Set the ETH peripheral state to BUSY */
mbed_official 235:685d5f11838f 1202 heth->State = HAL_ETH_STATE_BUSY;
mbed_official 235:685d5f11838f 1203
mbed_official 235:685d5f11838f 1204 /* Enable transmit state machine of the MAC for transmission on the MII */
mbed_official 235:685d5f11838f 1205 ETH_MACTransmissionEnable(heth);
mbed_official 235:685d5f11838f 1206
mbed_official 235:685d5f11838f 1207 /* Enable receive state machine of the MAC for reception from the MII */
mbed_official 235:685d5f11838f 1208 ETH_MACReceptionEnable(heth);
mbed_official 235:685d5f11838f 1209
mbed_official 235:685d5f11838f 1210 /* Flush Transmit FIFO */
mbed_official 235:685d5f11838f 1211 ETH_FlushTransmitFIFO(heth);
mbed_official 235:685d5f11838f 1212
mbed_official 235:685d5f11838f 1213 /* Start DMA transmission */
mbed_official 235:685d5f11838f 1214 ETH_DMATransmissionEnable(heth);
mbed_official 235:685d5f11838f 1215
mbed_official 235:685d5f11838f 1216 /* Start DMA reception */
mbed_official 235:685d5f11838f 1217 ETH_DMAReceptionEnable(heth);
mbed_official 235:685d5f11838f 1218
mbed_official 235:685d5f11838f 1219 /* Set the ETH state to READY*/
mbed_official 235:685d5f11838f 1220 heth->State= HAL_ETH_STATE_READY;
mbed_official 235:685d5f11838f 1221
mbed_official 235:685d5f11838f 1222 /* Process Unlocked */
mbed_official 235:685d5f11838f 1223 __HAL_UNLOCK(heth);
mbed_official 235:685d5f11838f 1224
mbed_official 235:685d5f11838f 1225 /* Return function status */
mbed_official 235:685d5f11838f 1226 return HAL_OK;
mbed_official 235:685d5f11838f 1227 }
mbed_official 235:685d5f11838f 1228
mbed_official 235:685d5f11838f 1229 /**
mbed_official 235:685d5f11838f 1230 * @brief Stop Ethernet MAC and DMA reception/transmission
mbed_official 235:685d5f11838f 1231 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 235:685d5f11838f 1232 * the configuration information for ETHERNET module
mbed_official 235:685d5f11838f 1233 * @retval HAL status
mbed_official 235:685d5f11838f 1234 */
mbed_official 235:685d5f11838f 1235 HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth)
mbed_official 235:685d5f11838f 1236 {
mbed_official 235:685d5f11838f 1237 /* Process Locked */
mbed_official 235:685d5f11838f 1238 __HAL_LOCK(heth);
mbed_official 235:685d5f11838f 1239
mbed_official 235:685d5f11838f 1240 /* Set the ETH peripheral state to BUSY */
mbed_official 235:685d5f11838f 1241 heth->State = HAL_ETH_STATE_BUSY;
mbed_official 235:685d5f11838f 1242
mbed_official 235:685d5f11838f 1243 /* Stop DMA transmission */
mbed_official 235:685d5f11838f 1244 ETH_DMATransmissionDisable(heth);
mbed_official 235:685d5f11838f 1245
mbed_official 235:685d5f11838f 1246 /* Stop DMA reception */
mbed_official 235:685d5f11838f 1247 ETH_DMAReceptionDisable(heth);
mbed_official 235:685d5f11838f 1248
mbed_official 235:685d5f11838f 1249 /* Disable receive state machine of the MAC for reception from the MII */
mbed_official 235:685d5f11838f 1250 ETH_MACReceptionDisable(heth);
mbed_official 235:685d5f11838f 1251
mbed_official 235:685d5f11838f 1252 /* Flush Transmit FIFO */
mbed_official 235:685d5f11838f 1253 ETH_FlushTransmitFIFO(heth);
mbed_official 235:685d5f11838f 1254
mbed_official 235:685d5f11838f 1255 /* Disable transmit state machine of the MAC for transmission on the MII */
mbed_official 235:685d5f11838f 1256 ETH_MACTransmissionDisable(heth);
mbed_official 235:685d5f11838f 1257
mbed_official 235:685d5f11838f 1258 /* Set the ETH state*/
mbed_official 235:685d5f11838f 1259 heth->State = HAL_ETH_STATE_READY;
mbed_official 235:685d5f11838f 1260
mbed_official 235:685d5f11838f 1261 /* Process Unlocked */
mbed_official 235:685d5f11838f 1262 __HAL_UNLOCK(heth);
mbed_official 235:685d5f11838f 1263
mbed_official 235:685d5f11838f 1264 /* Return function status */
mbed_official 235:685d5f11838f 1265 return HAL_OK;
mbed_official 235:685d5f11838f 1266 }
mbed_official 235:685d5f11838f 1267
mbed_official 235:685d5f11838f 1268 /**
mbed_official 235:685d5f11838f 1269 * @brief Set ETH MAC Configuration.
mbed_official 235:685d5f11838f 1270 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 235:685d5f11838f 1271 * the configuration information for ETHERNET module
mbed_official 235:685d5f11838f 1272 * @param macconf: MAC Configuration structure
mbed_official 235:685d5f11838f 1273 * @retval HAL status
mbed_official 235:685d5f11838f 1274 */
mbed_official 235:685d5f11838f 1275 HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf)
mbed_official 235:685d5f11838f 1276 {
mbed_official 532:fe11edbda85c 1277 uint32_t tmpreg1 = 0;
mbed_official 235:685d5f11838f 1278
mbed_official 235:685d5f11838f 1279 /* Process Locked */
mbed_official 235:685d5f11838f 1280 __HAL_LOCK(heth);
mbed_official 235:685d5f11838f 1281
mbed_official 235:685d5f11838f 1282 /* Set the ETH peripheral state to BUSY */
mbed_official 235:685d5f11838f 1283 heth->State= HAL_ETH_STATE_BUSY;
mbed_official 235:685d5f11838f 1284
mbed_official 235:685d5f11838f 1285 assert_param(IS_ETH_SPEED(heth->Init.Speed));
mbed_official 235:685d5f11838f 1286 assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode));
mbed_official 235:685d5f11838f 1287
mbed_official 384:ef87175507f1 1288 if (macconf != HAL_NULL)
mbed_official 235:685d5f11838f 1289 {
mbed_official 235:685d5f11838f 1290 /* Check the parameters */
mbed_official 235:685d5f11838f 1291 assert_param(IS_ETH_WATCHDOG(macconf->Watchdog));
mbed_official 235:685d5f11838f 1292 assert_param(IS_ETH_JABBER(macconf->Jabber));
mbed_official 235:685d5f11838f 1293 assert_param(IS_ETH_INTER_FRAME_GAP(macconf->InterFrameGap));
mbed_official 235:685d5f11838f 1294 assert_param(IS_ETH_CARRIER_SENSE(macconf->CarrierSense));
mbed_official 235:685d5f11838f 1295 assert_param(IS_ETH_RECEIVE_OWN(macconf->ReceiveOwn));
mbed_official 235:685d5f11838f 1296 assert_param(IS_ETH_LOOPBACK_MODE(macconf->LoopbackMode));
mbed_official 235:685d5f11838f 1297 assert_param(IS_ETH_CHECKSUM_OFFLOAD(macconf->ChecksumOffload));
mbed_official 235:685d5f11838f 1298 assert_param(IS_ETH_RETRY_TRANSMISSION(macconf->RetryTransmission));
mbed_official 235:685d5f11838f 1299 assert_param(IS_ETH_AUTOMATIC_PADCRC_STRIP(macconf->AutomaticPadCRCStrip));
mbed_official 235:685d5f11838f 1300 assert_param(IS_ETH_BACKOFF_LIMIT(macconf->BackOffLimit));
mbed_official 235:685d5f11838f 1301 assert_param(IS_ETH_DEFERRAL_CHECK(macconf->DeferralCheck));
mbed_official 235:685d5f11838f 1302 assert_param(IS_ETH_RECEIVE_ALL(macconf->ReceiveAll));
mbed_official 235:685d5f11838f 1303 assert_param(IS_ETH_SOURCE_ADDR_FILTER(macconf->SourceAddrFilter));
mbed_official 235:685d5f11838f 1304 assert_param(IS_ETH_CONTROL_FRAMES(macconf->PassControlFrames));
mbed_official 235:685d5f11838f 1305 assert_param(IS_ETH_BROADCAST_FRAMES_RECEPTION(macconf->BroadcastFramesReception));
mbed_official 235:685d5f11838f 1306 assert_param(IS_ETH_DESTINATION_ADDR_FILTER(macconf->DestinationAddrFilter));
mbed_official 532:fe11edbda85c 1307 assert_param(IS_ETH_PROMISCUOUS_MODE(macconf->PromiscuousMode));
mbed_official 235:685d5f11838f 1308 assert_param(IS_ETH_MULTICAST_FRAMES_FILTER(macconf->MulticastFramesFilter));
mbed_official 235:685d5f11838f 1309 assert_param(IS_ETH_UNICAST_FRAMES_FILTER(macconf->UnicastFramesFilter));
mbed_official 235:685d5f11838f 1310 assert_param(IS_ETH_PAUSE_TIME(macconf->PauseTime));
mbed_official 235:685d5f11838f 1311 assert_param(IS_ETH_ZEROQUANTA_PAUSE(macconf->ZeroQuantaPause));
mbed_official 235:685d5f11838f 1312 assert_param(IS_ETH_PAUSE_LOW_THRESHOLD(macconf->PauseLowThreshold));
mbed_official 235:685d5f11838f 1313 assert_param(IS_ETH_UNICAST_PAUSE_FRAME_DETECT(macconf->UnicastPauseFrameDetect));
mbed_official 235:685d5f11838f 1314 assert_param(IS_ETH_RECEIVE_FLOWCONTROL(macconf->ReceiveFlowControl));
mbed_official 235:685d5f11838f 1315 assert_param(IS_ETH_TRANSMIT_FLOWCONTROL(macconf->TransmitFlowControl));
mbed_official 235:685d5f11838f 1316 assert_param(IS_ETH_VLAN_TAG_COMPARISON(macconf->VLANTagComparison));
mbed_official 235:685d5f11838f 1317 assert_param(IS_ETH_VLAN_TAG_IDENTIFIER(macconf->VLANTagIdentifier));
mbed_official 235:685d5f11838f 1318
mbed_official 235:685d5f11838f 1319 /*------------------------ ETHERNET MACCR Configuration --------------------*/
mbed_official 235:685d5f11838f 1320 /* Get the ETHERNET MACCR value */
mbed_official 532:fe11edbda85c 1321 tmpreg1 = (heth->Instance)->MACCR;
mbed_official 235:685d5f11838f 1322 /* Clear WD, PCE, PS, TE and RE bits */
mbed_official 532:fe11edbda85c 1323 tmpreg1 &= ETH_MACCR_CLEAR_MASK;
mbed_official 235:685d5f11838f 1324
mbed_official 532:fe11edbda85c 1325 tmpreg1 |= (uint32_t)(macconf->Watchdog |
mbed_official 235:685d5f11838f 1326 macconf->Jabber |
mbed_official 235:685d5f11838f 1327 macconf->InterFrameGap |
mbed_official 235:685d5f11838f 1328 macconf->CarrierSense |
mbed_official 235:685d5f11838f 1329 (heth->Init).Speed |
mbed_official 235:685d5f11838f 1330 macconf->ReceiveOwn |
mbed_official 235:685d5f11838f 1331 macconf->LoopbackMode |
mbed_official 235:685d5f11838f 1332 (heth->Init).DuplexMode |
mbed_official 235:685d5f11838f 1333 macconf->ChecksumOffload |
mbed_official 235:685d5f11838f 1334 macconf->RetryTransmission |
mbed_official 235:685d5f11838f 1335 macconf->AutomaticPadCRCStrip |
mbed_official 235:685d5f11838f 1336 macconf->BackOffLimit |
mbed_official 235:685d5f11838f 1337 macconf->DeferralCheck);
mbed_official 235:685d5f11838f 1338
mbed_official 235:685d5f11838f 1339 /* Write to ETHERNET MACCR */
mbed_official 532:fe11edbda85c 1340 (heth->Instance)->MACCR = (uint32_t)tmpreg1;
mbed_official 235:685d5f11838f 1341
mbed_official 235:685d5f11838f 1342 /* Wait until the write operation will be taken into account :
mbed_official 235:685d5f11838f 1343 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 532:fe11edbda85c 1344 tmpreg1 = (heth->Instance)->MACCR;
mbed_official 235:685d5f11838f 1345 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 532:fe11edbda85c 1346 (heth->Instance)->MACCR = tmpreg1;
mbed_official 235:685d5f11838f 1347
mbed_official 235:685d5f11838f 1348 /*----------------------- ETHERNET MACFFR Configuration --------------------*/
mbed_official 235:685d5f11838f 1349 /* Write to ETHERNET MACFFR */
mbed_official 235:685d5f11838f 1350 (heth->Instance)->MACFFR = (uint32_t)(macconf->ReceiveAll |
mbed_official 235:685d5f11838f 1351 macconf->SourceAddrFilter |
mbed_official 235:685d5f11838f 1352 macconf->PassControlFrames |
mbed_official 235:685d5f11838f 1353 macconf->BroadcastFramesReception |
mbed_official 235:685d5f11838f 1354 macconf->DestinationAddrFilter |
mbed_official 235:685d5f11838f 1355 macconf->PromiscuousMode |
mbed_official 235:685d5f11838f 1356 macconf->MulticastFramesFilter |
mbed_official 235:685d5f11838f 1357 macconf->UnicastFramesFilter);
mbed_official 235:685d5f11838f 1358
mbed_official 235:685d5f11838f 1359 /* Wait until the write operation will be taken into account :
mbed_official 235:685d5f11838f 1360 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 532:fe11edbda85c 1361 tmpreg1 = (heth->Instance)->MACFFR;
mbed_official 235:685d5f11838f 1362 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 532:fe11edbda85c 1363 (heth->Instance)->MACFFR = tmpreg1;
mbed_official 235:685d5f11838f 1364
mbed_official 235:685d5f11838f 1365 /*--------------- ETHERNET MACHTHR and MACHTLR Configuration ---------------*/
mbed_official 235:685d5f11838f 1366 /* Write to ETHERNET MACHTHR */
mbed_official 235:685d5f11838f 1367 (heth->Instance)->MACHTHR = (uint32_t)macconf->HashTableHigh;
mbed_official 235:685d5f11838f 1368
mbed_official 235:685d5f11838f 1369 /* Write to ETHERNET MACHTLR */
mbed_official 235:685d5f11838f 1370 (heth->Instance)->MACHTLR = (uint32_t)macconf->HashTableLow;
mbed_official 235:685d5f11838f 1371 /*----------------------- ETHERNET MACFCR Configuration --------------------*/
mbed_official 235:685d5f11838f 1372
mbed_official 235:685d5f11838f 1373 /* Get the ETHERNET MACFCR value */
mbed_official 532:fe11edbda85c 1374 tmpreg1 = (heth->Instance)->MACFCR;
mbed_official 235:685d5f11838f 1375 /* Clear xx bits */
mbed_official 532:fe11edbda85c 1376 tmpreg1 &= ETH_MACFCR_CLEAR_MASK;
mbed_official 235:685d5f11838f 1377
mbed_official 532:fe11edbda85c 1378 tmpreg1 |= (uint32_t)((macconf->PauseTime << 16) |
mbed_official 235:685d5f11838f 1379 macconf->ZeroQuantaPause |
mbed_official 235:685d5f11838f 1380 macconf->PauseLowThreshold |
mbed_official 235:685d5f11838f 1381 macconf->UnicastPauseFrameDetect |
mbed_official 235:685d5f11838f 1382 macconf->ReceiveFlowControl |
mbed_official 235:685d5f11838f 1383 macconf->TransmitFlowControl);
mbed_official 235:685d5f11838f 1384
mbed_official 235:685d5f11838f 1385 /* Write to ETHERNET MACFCR */
mbed_official 532:fe11edbda85c 1386 (heth->Instance)->MACFCR = (uint32_t)tmpreg1;
mbed_official 235:685d5f11838f 1387
mbed_official 235:685d5f11838f 1388 /* Wait until the write operation will be taken into account :
mbed_official 235:685d5f11838f 1389 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 532:fe11edbda85c 1390 tmpreg1 = (heth->Instance)->MACFCR;
mbed_official 235:685d5f11838f 1391 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 532:fe11edbda85c 1392 (heth->Instance)->MACFCR = tmpreg1;
mbed_official 235:685d5f11838f 1393
mbed_official 235:685d5f11838f 1394 /*----------------------- ETHERNET MACVLANTR Configuration -----------------*/
mbed_official 235:685d5f11838f 1395 (heth->Instance)->MACVLANTR = (uint32_t)(macconf->VLANTagComparison |
mbed_official 235:685d5f11838f 1396 macconf->VLANTagIdentifier);
mbed_official 235:685d5f11838f 1397
mbed_official 235:685d5f11838f 1398 /* Wait until the write operation will be taken into account :
mbed_official 235:685d5f11838f 1399 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 532:fe11edbda85c 1400 tmpreg1 = (heth->Instance)->MACVLANTR;
mbed_official 235:685d5f11838f 1401 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 532:fe11edbda85c 1402 (heth->Instance)->MACVLANTR = tmpreg1;
mbed_official 235:685d5f11838f 1403 }
mbed_official 235:685d5f11838f 1404 else /* macconf == NULL : here we just configure Speed and Duplex mode */
mbed_official 235:685d5f11838f 1405 {
mbed_official 235:685d5f11838f 1406 /*------------------------ ETHERNET MACCR Configuration --------------------*/
mbed_official 235:685d5f11838f 1407 /* Get the ETHERNET MACCR value */
mbed_official 532:fe11edbda85c 1408 tmpreg1 = (heth->Instance)->MACCR;
mbed_official 235:685d5f11838f 1409
mbed_official 235:685d5f11838f 1410 /* Clear FES and DM bits */
mbed_official 532:fe11edbda85c 1411 tmpreg1 &= ~((uint32_t)0x00004800);
mbed_official 235:685d5f11838f 1412
mbed_official 532:fe11edbda85c 1413 tmpreg1 |= (uint32_t)(heth->Init.Speed | heth->Init.DuplexMode);
mbed_official 235:685d5f11838f 1414
mbed_official 235:685d5f11838f 1415 /* Write to ETHERNET MACCR */
mbed_official 532:fe11edbda85c 1416 (heth->Instance)->MACCR = (uint32_t)tmpreg1;
mbed_official 235:685d5f11838f 1417
mbed_official 235:685d5f11838f 1418 /* Wait until the write operation will be taken into account:
mbed_official 235:685d5f11838f 1419 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 532:fe11edbda85c 1420 tmpreg1 = (heth->Instance)->MACCR;
mbed_official 235:685d5f11838f 1421 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 532:fe11edbda85c 1422 (heth->Instance)->MACCR = tmpreg1;
mbed_official 235:685d5f11838f 1423 }
mbed_official 235:685d5f11838f 1424
mbed_official 235:685d5f11838f 1425 /* Set the ETH state to Ready */
mbed_official 235:685d5f11838f 1426 heth->State= HAL_ETH_STATE_READY;
mbed_official 235:685d5f11838f 1427
mbed_official 235:685d5f11838f 1428 /* Process Unlocked */
mbed_official 235:685d5f11838f 1429 __HAL_UNLOCK(heth);
mbed_official 235:685d5f11838f 1430
mbed_official 235:685d5f11838f 1431 /* Return function status */
mbed_official 235:685d5f11838f 1432 return HAL_OK;
mbed_official 235:685d5f11838f 1433 }
mbed_official 235:685d5f11838f 1434
mbed_official 235:685d5f11838f 1435 /**
mbed_official 235:685d5f11838f 1436 * @brief Sets ETH DMA Configuration.
mbed_official 235:685d5f11838f 1437 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 235:685d5f11838f 1438 * the configuration information for ETHERNET module
mbed_official 235:685d5f11838f 1439 * @param dmaconf: DMA Configuration structure
mbed_official 235:685d5f11838f 1440 * @retval HAL status
mbed_official 235:685d5f11838f 1441 */
mbed_official 235:685d5f11838f 1442 HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf)
mbed_official 235:685d5f11838f 1443 {
mbed_official 532:fe11edbda85c 1444 uint32_t tmpreg1 = 0;
mbed_official 235:685d5f11838f 1445
mbed_official 235:685d5f11838f 1446 /* Process Locked */
mbed_official 235:685d5f11838f 1447 __HAL_LOCK(heth);
mbed_official 235:685d5f11838f 1448
mbed_official 235:685d5f11838f 1449 /* Set the ETH peripheral state to BUSY */
mbed_official 235:685d5f11838f 1450 heth->State= HAL_ETH_STATE_BUSY;
mbed_official 235:685d5f11838f 1451
mbed_official 235:685d5f11838f 1452 /* Check parameters */
mbed_official 235:685d5f11838f 1453 assert_param(IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(dmaconf->DropTCPIPChecksumErrorFrame));
mbed_official 235:685d5f11838f 1454 assert_param(IS_ETH_RECEIVE_STORE_FORWARD(dmaconf->ReceiveStoreForward));
mbed_official 235:685d5f11838f 1455 assert_param(IS_ETH_FLUSH_RECEIVE_FRAME(dmaconf->FlushReceivedFrame));
mbed_official 235:685d5f11838f 1456 assert_param(IS_ETH_TRANSMIT_STORE_FORWARD(dmaconf->TransmitStoreForward));
mbed_official 235:685d5f11838f 1457 assert_param(IS_ETH_TRANSMIT_THRESHOLD_CONTROL(dmaconf->TransmitThresholdControl));
mbed_official 235:685d5f11838f 1458 assert_param(IS_ETH_FORWARD_ERROR_FRAMES(dmaconf->ForwardErrorFrames));
mbed_official 235:685d5f11838f 1459 assert_param(IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(dmaconf->ForwardUndersizedGoodFrames));
mbed_official 235:685d5f11838f 1460 assert_param(IS_ETH_RECEIVE_THRESHOLD_CONTROL(dmaconf->ReceiveThresholdControl));
mbed_official 235:685d5f11838f 1461 assert_param(IS_ETH_SECOND_FRAME_OPERATE(dmaconf->SecondFrameOperate));
mbed_official 235:685d5f11838f 1462 assert_param(IS_ETH_ADDRESS_ALIGNED_BEATS(dmaconf->AddressAlignedBeats));
mbed_official 235:685d5f11838f 1463 assert_param(IS_ETH_FIXED_BURST(dmaconf->FixedBurst));
mbed_official 235:685d5f11838f 1464 assert_param(IS_ETH_RXDMA_BURST_LENGTH(dmaconf->RxDMABurstLength));
mbed_official 235:685d5f11838f 1465 assert_param(IS_ETH_TXDMA_BURST_LENGTH(dmaconf->TxDMABurstLength));
mbed_official 235:685d5f11838f 1466 assert_param(IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(dmaconf->EnhancedDescriptorFormat));
mbed_official 235:685d5f11838f 1467 assert_param(IS_ETH_DMA_DESC_SKIP_LENGTH(dmaconf->DescriptorSkipLength));
mbed_official 235:685d5f11838f 1468 assert_param(IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(dmaconf->DMAArbitration));
mbed_official 235:685d5f11838f 1469
mbed_official 235:685d5f11838f 1470 /*----------------------- ETHERNET DMAOMR Configuration --------------------*/
mbed_official 235:685d5f11838f 1471 /* Get the ETHERNET DMAOMR value */
mbed_official 532:fe11edbda85c 1472 tmpreg1 = (heth->Instance)->DMAOMR;
mbed_official 235:685d5f11838f 1473 /* Clear xx bits */
mbed_official 532:fe11edbda85c 1474 tmpreg1 &= ETH_DMAOMR_CLEAR_MASK;
mbed_official 235:685d5f11838f 1475
mbed_official 532:fe11edbda85c 1476 tmpreg1 |= (uint32_t)(dmaconf->DropTCPIPChecksumErrorFrame |
mbed_official 235:685d5f11838f 1477 dmaconf->ReceiveStoreForward |
mbed_official 235:685d5f11838f 1478 dmaconf->FlushReceivedFrame |
mbed_official 235:685d5f11838f 1479 dmaconf->TransmitStoreForward |
mbed_official 235:685d5f11838f 1480 dmaconf->TransmitThresholdControl |
mbed_official 235:685d5f11838f 1481 dmaconf->ForwardErrorFrames |
mbed_official 235:685d5f11838f 1482 dmaconf->ForwardUndersizedGoodFrames |
mbed_official 235:685d5f11838f 1483 dmaconf->ReceiveThresholdControl |
mbed_official 235:685d5f11838f 1484 dmaconf->SecondFrameOperate);
mbed_official 235:685d5f11838f 1485
mbed_official 235:685d5f11838f 1486 /* Write to ETHERNET DMAOMR */
mbed_official 532:fe11edbda85c 1487 (heth->Instance)->DMAOMR = (uint32_t)tmpreg1;
mbed_official 235:685d5f11838f 1488
mbed_official 235:685d5f11838f 1489 /* Wait until the write operation will be taken into account:
mbed_official 235:685d5f11838f 1490 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 532:fe11edbda85c 1491 tmpreg1 = (heth->Instance)->DMAOMR;
mbed_official 235:685d5f11838f 1492 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 532:fe11edbda85c 1493 (heth->Instance)->DMAOMR = tmpreg1;
mbed_official 235:685d5f11838f 1494
mbed_official 235:685d5f11838f 1495 /*----------------------- ETHERNET DMABMR Configuration --------------------*/
mbed_official 235:685d5f11838f 1496 (heth->Instance)->DMABMR = (uint32_t)(dmaconf->AddressAlignedBeats |
mbed_official 235:685d5f11838f 1497 dmaconf->FixedBurst |
mbed_official 235:685d5f11838f 1498 dmaconf->RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */
mbed_official 235:685d5f11838f 1499 dmaconf->TxDMABurstLength |
mbed_official 235:685d5f11838f 1500 dmaconf->EnhancedDescriptorFormat |
mbed_official 235:685d5f11838f 1501 (dmaconf->DescriptorSkipLength << 2) |
mbed_official 235:685d5f11838f 1502 dmaconf->DMAArbitration |
mbed_official 235:685d5f11838f 1503 ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */
mbed_official 235:685d5f11838f 1504
mbed_official 235:685d5f11838f 1505 /* Wait until the write operation will be taken into account:
mbed_official 235:685d5f11838f 1506 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 532:fe11edbda85c 1507 tmpreg1 = (heth->Instance)->DMABMR;
mbed_official 235:685d5f11838f 1508 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 532:fe11edbda85c 1509 (heth->Instance)->DMABMR = tmpreg1;
mbed_official 235:685d5f11838f 1510
mbed_official 235:685d5f11838f 1511 /* Set the ETH state to Ready */
mbed_official 235:685d5f11838f 1512 heth->State= HAL_ETH_STATE_READY;
mbed_official 235:685d5f11838f 1513
mbed_official 235:685d5f11838f 1514 /* Process Unlocked */
mbed_official 235:685d5f11838f 1515 __HAL_UNLOCK(heth);
mbed_official 235:685d5f11838f 1516
mbed_official 235:685d5f11838f 1517 /* Return function status */
mbed_official 235:685d5f11838f 1518 return HAL_OK;
mbed_official 235:685d5f11838f 1519 }
mbed_official 235:685d5f11838f 1520
mbed_official 235:685d5f11838f 1521 /**
mbed_official 235:685d5f11838f 1522 * @}
mbed_official 235:685d5f11838f 1523 */
mbed_official 235:685d5f11838f 1524
mbed_official 532:fe11edbda85c 1525 /** @defgroup ETH_Exported_Functions_Group4 Peripheral State functions
mbed_official 235:685d5f11838f 1526 * @brief Peripheral State functions
mbed_official 235:685d5f11838f 1527 *
mbed_official 235:685d5f11838f 1528 @verbatim
mbed_official 235:685d5f11838f 1529 ===============================================================================
mbed_official 235:685d5f11838f 1530 ##### Peripheral State functions #####
mbed_official 235:685d5f11838f 1531 ===============================================================================
mbed_official 235:685d5f11838f 1532 [..]
mbed_official 235:685d5f11838f 1533 This subsection permits to get in run-time the status of the peripheral
mbed_official 235:685d5f11838f 1534 and the data flow.
mbed_official 235:685d5f11838f 1535 (+) Get the ETH handle state:
mbed_official 235:685d5f11838f 1536 HAL_ETH_GetState();
mbed_official 235:685d5f11838f 1537
mbed_official 235:685d5f11838f 1538
mbed_official 235:685d5f11838f 1539 @endverbatim
mbed_official 235:685d5f11838f 1540 * @{
mbed_official 235:685d5f11838f 1541 */
mbed_official 235:685d5f11838f 1542
mbed_official 235:685d5f11838f 1543 /**
mbed_official 235:685d5f11838f 1544 * @brief Return the ETH HAL state
mbed_official 235:685d5f11838f 1545 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 235:685d5f11838f 1546 * the configuration information for ETHERNET module
mbed_official 235:685d5f11838f 1547 * @retval HAL state
mbed_official 235:685d5f11838f 1548 */
mbed_official 235:685d5f11838f 1549 HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth)
mbed_official 235:685d5f11838f 1550 {
mbed_official 235:685d5f11838f 1551 /* Return ETH state */
mbed_official 235:685d5f11838f 1552 return heth->State;
mbed_official 235:685d5f11838f 1553 }
mbed_official 235:685d5f11838f 1554
mbed_official 235:685d5f11838f 1555 /**
mbed_official 235:685d5f11838f 1556 * @}
mbed_official 235:685d5f11838f 1557 */
mbed_official 532:fe11edbda85c 1558
mbed_official 532:fe11edbda85c 1559 /**
mbed_official 532:fe11edbda85c 1560 * @}
mbed_official 532:fe11edbda85c 1561 */
mbed_official 532:fe11edbda85c 1562
mbed_official 532:fe11edbda85c 1563 /** @addtogroup ETH_Private_Functions
mbed_official 532:fe11edbda85c 1564 * @{
mbed_official 532:fe11edbda85c 1565 */
mbed_official 235:685d5f11838f 1566
mbed_official 235:685d5f11838f 1567 /**
mbed_official 235:685d5f11838f 1568 * @brief Configures Ethernet MAC and DMA with default parameters.
mbed_official 235:685d5f11838f 1569 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 235:685d5f11838f 1570 * the configuration information for ETHERNET module
mbed_official 235:685d5f11838f 1571 * @param err: Ethernet Init error
mbed_official 235:685d5f11838f 1572 * @retval HAL status
mbed_official 235:685d5f11838f 1573 */
mbed_official 235:685d5f11838f 1574 static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err)
mbed_official 235:685d5f11838f 1575 {
mbed_official 235:685d5f11838f 1576 ETH_MACInitTypeDef macinit;
mbed_official 235:685d5f11838f 1577 ETH_DMAInitTypeDef dmainit;
mbed_official 532:fe11edbda85c 1578 uint32_t tmpreg1 = 0;
mbed_official 235:685d5f11838f 1579
mbed_official 235:685d5f11838f 1580 if (err != ETH_SUCCESS) /* Auto-negotiation failed */
mbed_official 235:685d5f11838f 1581 {
mbed_official 235:685d5f11838f 1582 /* Set Ethernet duplex mode to Full-duplex */
mbed_official 235:685d5f11838f 1583 (heth->Init).DuplexMode = ETH_MODE_FULLDUPLEX;
mbed_official 235:685d5f11838f 1584
mbed_official 235:685d5f11838f 1585 /* Set Ethernet speed to 100M */
mbed_official 235:685d5f11838f 1586 (heth->Init).Speed = ETH_SPEED_100M;
mbed_official 235:685d5f11838f 1587 }
mbed_official 235:685d5f11838f 1588
mbed_official 235:685d5f11838f 1589 /* Ethernet MAC default initialization **************************************/
mbed_official 235:685d5f11838f 1590 macinit.Watchdog = ETH_WATCHDOG_ENABLE;
mbed_official 235:685d5f11838f 1591 macinit.Jabber = ETH_JABBER_ENABLE;
mbed_official 235:685d5f11838f 1592 macinit.InterFrameGap = ETH_INTERFRAMEGAP_96BIT;
mbed_official 235:685d5f11838f 1593 macinit.CarrierSense = ETH_CARRIERSENCE_ENABLE;
mbed_official 235:685d5f11838f 1594 macinit.ReceiveOwn = ETH_RECEIVEOWN_ENABLE;
mbed_official 235:685d5f11838f 1595 macinit.LoopbackMode = ETH_LOOPBACKMODE_DISABLE;
mbed_official 235:685d5f11838f 1596 if(heth->Init.ChecksumMode == ETH_CHECKSUM_BY_HARDWARE)
mbed_official 235:685d5f11838f 1597 {
mbed_official 235:685d5f11838f 1598 macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_ENABLE;
mbed_official 235:685d5f11838f 1599 }
mbed_official 235:685d5f11838f 1600 else
mbed_official 235:685d5f11838f 1601 {
mbed_official 235:685d5f11838f 1602 macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_DISABLE;
mbed_official 235:685d5f11838f 1603 }
mbed_official 235:685d5f11838f 1604 macinit.RetryTransmission = ETH_RETRYTRANSMISSION_DISABLE;
mbed_official 235:685d5f11838f 1605 macinit.AutomaticPadCRCStrip = ETH_AUTOMATICPADCRCSTRIP_DISABLE;
mbed_official 235:685d5f11838f 1606 macinit.BackOffLimit = ETH_BACKOFFLIMIT_10;
mbed_official 235:685d5f11838f 1607 macinit.DeferralCheck = ETH_DEFFERRALCHECK_DISABLE;
mbed_official 235:685d5f11838f 1608 macinit.ReceiveAll = ETH_RECEIVEAll_DISABLE;
mbed_official 235:685d5f11838f 1609 macinit.SourceAddrFilter = ETH_SOURCEADDRFILTER_DISABLE;
mbed_official 235:685d5f11838f 1610 macinit.PassControlFrames = ETH_PASSCONTROLFRAMES_BLOCKALL;
mbed_official 235:685d5f11838f 1611 macinit.BroadcastFramesReception = ETH_BROADCASTFRAMESRECEPTION_ENABLE;
mbed_official 235:685d5f11838f 1612 macinit.DestinationAddrFilter = ETH_DESTINATIONADDRFILTER_NORMAL;
mbed_official 532:fe11edbda85c 1613 macinit.PromiscuousMode = ETH_PROMISCUOUS_MODE_DISABLE;
mbed_official 235:685d5f11838f 1614 macinit.MulticastFramesFilter = ETH_MULTICASTFRAMESFILTER_PERFECT;
mbed_official 235:685d5f11838f 1615 macinit.UnicastFramesFilter = ETH_UNICASTFRAMESFILTER_PERFECT;
mbed_official 235:685d5f11838f 1616 macinit.HashTableHigh = 0x0;
mbed_official 235:685d5f11838f 1617 macinit.HashTableLow = 0x0;
mbed_official 235:685d5f11838f 1618 macinit.PauseTime = 0x0;
mbed_official 235:685d5f11838f 1619 macinit.ZeroQuantaPause = ETH_ZEROQUANTAPAUSE_DISABLE;
mbed_official 235:685d5f11838f 1620 macinit.PauseLowThreshold = ETH_PAUSELOWTHRESHOLD_MINUS4;
mbed_official 235:685d5f11838f 1621 macinit.UnicastPauseFrameDetect = ETH_UNICASTPAUSEFRAMEDETECT_DISABLE;
mbed_official 235:685d5f11838f 1622 macinit.ReceiveFlowControl = ETH_RECEIVEFLOWCONTROL_DISABLE;
mbed_official 235:685d5f11838f 1623 macinit.TransmitFlowControl = ETH_TRANSMITFLOWCONTROL_DISABLE;
mbed_official 235:685d5f11838f 1624 macinit.VLANTagComparison = ETH_VLANTAGCOMPARISON_16BIT;
mbed_official 235:685d5f11838f 1625 macinit.VLANTagIdentifier = 0x0;
mbed_official 235:685d5f11838f 1626
mbed_official 235:685d5f11838f 1627 /*------------------------ ETHERNET MACCR Configuration --------------------*/
mbed_official 235:685d5f11838f 1628 /* Get the ETHERNET MACCR value */
mbed_official 532:fe11edbda85c 1629 tmpreg1 = (heth->Instance)->MACCR;
mbed_official 235:685d5f11838f 1630 /* Clear WD, PCE, PS, TE and RE bits */
mbed_official 532:fe11edbda85c 1631 tmpreg1 &= ETH_MACCR_CLEAR_MASK;
mbed_official 235:685d5f11838f 1632 /* Set the WD bit according to ETH Watchdog value */
mbed_official 235:685d5f11838f 1633 /* Set the JD: bit according to ETH Jabber value */
mbed_official 235:685d5f11838f 1634 /* Set the IFG bit according to ETH InterFrameGap value */
mbed_official 235:685d5f11838f 1635 /* Set the DCRS bit according to ETH CarrierSense value */
mbed_official 235:685d5f11838f 1636 /* Set the FES bit according to ETH Speed value */
mbed_official 235:685d5f11838f 1637 /* Set the DO bit according to ETH ReceiveOwn value */
mbed_official 235:685d5f11838f 1638 /* Set the LM bit according to ETH LoopbackMode value */
mbed_official 235:685d5f11838f 1639 /* Set the DM bit according to ETH Mode value */
mbed_official 235:685d5f11838f 1640 /* Set the IPCO bit according to ETH ChecksumOffload value */
mbed_official 235:685d5f11838f 1641 /* Set the DR bit according to ETH RetryTransmission value */
mbed_official 235:685d5f11838f 1642 /* Set the ACS bit according to ETH AutomaticPadCRCStrip value */
mbed_official 235:685d5f11838f 1643 /* Set the BL bit according to ETH BackOffLimit value */
mbed_official 235:685d5f11838f 1644 /* Set the DC bit according to ETH DeferralCheck value */
mbed_official 532:fe11edbda85c 1645 tmpreg1 |= (uint32_t)(macinit.Watchdog |
mbed_official 235:685d5f11838f 1646 macinit.Jabber |
mbed_official 235:685d5f11838f 1647 macinit.InterFrameGap |
mbed_official 235:685d5f11838f 1648 macinit.CarrierSense |
mbed_official 235:685d5f11838f 1649 (heth->Init).Speed |
mbed_official 235:685d5f11838f 1650 macinit.ReceiveOwn |
mbed_official 235:685d5f11838f 1651 macinit.LoopbackMode |
mbed_official 235:685d5f11838f 1652 (heth->Init).DuplexMode |
mbed_official 235:685d5f11838f 1653 macinit.ChecksumOffload |
mbed_official 235:685d5f11838f 1654 macinit.RetryTransmission |
mbed_official 235:685d5f11838f 1655 macinit.AutomaticPadCRCStrip |
mbed_official 235:685d5f11838f 1656 macinit.BackOffLimit |
mbed_official 235:685d5f11838f 1657 macinit.DeferralCheck);
mbed_official 235:685d5f11838f 1658
mbed_official 235:685d5f11838f 1659 /* Write to ETHERNET MACCR */
mbed_official 532:fe11edbda85c 1660 (heth->Instance)->MACCR = (uint32_t)tmpreg1;
mbed_official 235:685d5f11838f 1661
mbed_official 235:685d5f11838f 1662 /* Wait until the write operation will be taken into account:
mbed_official 235:685d5f11838f 1663 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 532:fe11edbda85c 1664 tmpreg1 = (heth->Instance)->MACCR;
mbed_official 235:685d5f11838f 1665 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 532:fe11edbda85c 1666 (heth->Instance)->MACCR = tmpreg1;
mbed_official 235:685d5f11838f 1667
mbed_official 235:685d5f11838f 1668 /*----------------------- ETHERNET MACFFR Configuration --------------------*/
mbed_official 235:685d5f11838f 1669 /* Set the RA bit according to ETH ReceiveAll value */
mbed_official 235:685d5f11838f 1670 /* Set the SAF and SAIF bits according to ETH SourceAddrFilter value */
mbed_official 235:685d5f11838f 1671 /* Set the PCF bit according to ETH PassControlFrames value */
mbed_official 235:685d5f11838f 1672 /* Set the DBF bit according to ETH BroadcastFramesReception value */
mbed_official 235:685d5f11838f 1673 /* Set the DAIF bit according to ETH DestinationAddrFilter value */
mbed_official 235:685d5f11838f 1674 /* Set the PR bit according to ETH PromiscuousMode value */
mbed_official 235:685d5f11838f 1675 /* Set the PM, HMC and HPF bits according to ETH MulticastFramesFilter value */
mbed_official 235:685d5f11838f 1676 /* Set the HUC and HPF bits according to ETH UnicastFramesFilter value */
mbed_official 235:685d5f11838f 1677 /* Write to ETHERNET MACFFR */
mbed_official 235:685d5f11838f 1678 (heth->Instance)->MACFFR = (uint32_t)(macinit.ReceiveAll |
mbed_official 235:685d5f11838f 1679 macinit.SourceAddrFilter |
mbed_official 235:685d5f11838f 1680 macinit.PassControlFrames |
mbed_official 235:685d5f11838f 1681 macinit.BroadcastFramesReception |
mbed_official 235:685d5f11838f 1682 macinit.DestinationAddrFilter |
mbed_official 235:685d5f11838f 1683 macinit.PromiscuousMode |
mbed_official 235:685d5f11838f 1684 macinit.MulticastFramesFilter |
mbed_official 235:685d5f11838f 1685 macinit.UnicastFramesFilter);
mbed_official 235:685d5f11838f 1686
mbed_official 235:685d5f11838f 1687 /* Wait until the write operation will be taken into account:
mbed_official 235:685d5f11838f 1688 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 532:fe11edbda85c 1689 tmpreg1 = (heth->Instance)->MACFFR;
mbed_official 235:685d5f11838f 1690 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 532:fe11edbda85c 1691 (heth->Instance)->MACFFR = tmpreg1;
mbed_official 235:685d5f11838f 1692
mbed_official 235:685d5f11838f 1693 /*--------------- ETHERNET MACHTHR and MACHTLR Configuration --------------*/
mbed_official 235:685d5f11838f 1694 /* Write to ETHERNET MACHTHR */
mbed_official 235:685d5f11838f 1695 (heth->Instance)->MACHTHR = (uint32_t)macinit.HashTableHigh;
mbed_official 235:685d5f11838f 1696
mbed_official 235:685d5f11838f 1697 /* Write to ETHERNET MACHTLR */
mbed_official 235:685d5f11838f 1698 (heth->Instance)->MACHTLR = (uint32_t)macinit.HashTableLow;
mbed_official 235:685d5f11838f 1699 /*----------------------- ETHERNET MACFCR Configuration -------------------*/
mbed_official 235:685d5f11838f 1700
mbed_official 235:685d5f11838f 1701 /* Get the ETHERNET MACFCR value */
mbed_official 532:fe11edbda85c 1702 tmpreg1 = (heth->Instance)->MACFCR;
mbed_official 235:685d5f11838f 1703 /* Clear xx bits */
mbed_official 532:fe11edbda85c 1704 tmpreg1 &= ETH_MACFCR_CLEAR_MASK;
mbed_official 235:685d5f11838f 1705
mbed_official 235:685d5f11838f 1706 /* Set the PT bit according to ETH PauseTime value */
mbed_official 235:685d5f11838f 1707 /* Set the DZPQ bit according to ETH ZeroQuantaPause value */
mbed_official 235:685d5f11838f 1708 /* Set the PLT bit according to ETH PauseLowThreshold value */
mbed_official 235:685d5f11838f 1709 /* Set the UP bit according to ETH UnicastPauseFrameDetect value */
mbed_official 235:685d5f11838f 1710 /* Set the RFE bit according to ETH ReceiveFlowControl value */
mbed_official 235:685d5f11838f 1711 /* Set the TFE bit according to ETH TransmitFlowControl value */
mbed_official 532:fe11edbda85c 1712 tmpreg1 |= (uint32_t)((macinit.PauseTime << 16) |
mbed_official 235:685d5f11838f 1713 macinit.ZeroQuantaPause |
mbed_official 235:685d5f11838f 1714 macinit.PauseLowThreshold |
mbed_official 235:685d5f11838f 1715 macinit.UnicastPauseFrameDetect |
mbed_official 235:685d5f11838f 1716 macinit.ReceiveFlowControl |
mbed_official 235:685d5f11838f 1717 macinit.TransmitFlowControl);
mbed_official 235:685d5f11838f 1718
mbed_official 235:685d5f11838f 1719 /* Write to ETHERNET MACFCR */
mbed_official 532:fe11edbda85c 1720 (heth->Instance)->MACFCR = (uint32_t)tmpreg1;
mbed_official 235:685d5f11838f 1721
mbed_official 235:685d5f11838f 1722 /* Wait until the write operation will be taken into account:
mbed_official 235:685d5f11838f 1723 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 532:fe11edbda85c 1724 tmpreg1 = (heth->Instance)->MACFCR;
mbed_official 235:685d5f11838f 1725 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 532:fe11edbda85c 1726 (heth->Instance)->MACFCR = tmpreg1;
mbed_official 235:685d5f11838f 1727
mbed_official 235:685d5f11838f 1728 /*----------------------- ETHERNET MACVLANTR Configuration ----------------*/
mbed_official 235:685d5f11838f 1729 /* Set the ETV bit according to ETH VLANTagComparison value */
mbed_official 235:685d5f11838f 1730 /* Set the VL bit according to ETH VLANTagIdentifier value */
mbed_official 235:685d5f11838f 1731 (heth->Instance)->MACVLANTR = (uint32_t)(macinit.VLANTagComparison |
mbed_official 235:685d5f11838f 1732 macinit.VLANTagIdentifier);
mbed_official 235:685d5f11838f 1733
mbed_official 235:685d5f11838f 1734 /* Wait until the write operation will be taken into account:
mbed_official 235:685d5f11838f 1735 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 532:fe11edbda85c 1736 tmpreg1 = (heth->Instance)->MACVLANTR;
mbed_official 235:685d5f11838f 1737 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 532:fe11edbda85c 1738 (heth->Instance)->MACVLANTR = tmpreg1;
mbed_official 235:685d5f11838f 1739
mbed_official 235:685d5f11838f 1740 /* Ethernet DMA default initialization ************************************/
mbed_official 235:685d5f11838f 1741 dmainit.DropTCPIPChecksumErrorFrame = ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE;
mbed_official 235:685d5f11838f 1742 dmainit.ReceiveStoreForward = ETH_RECEIVESTOREFORWARD_ENABLE;
mbed_official 235:685d5f11838f 1743 dmainit.FlushReceivedFrame = ETH_FLUSHRECEIVEDFRAME_ENABLE;
mbed_official 235:685d5f11838f 1744 dmainit.TransmitStoreForward = ETH_TRANSMITSTOREFORWARD_ENABLE;
mbed_official 235:685d5f11838f 1745 dmainit.TransmitThresholdControl = ETH_TRANSMITTHRESHOLDCONTROL_64BYTES;
mbed_official 235:685d5f11838f 1746 dmainit.ForwardErrorFrames = ETH_FORWARDERRORFRAMES_DISABLE;
mbed_official 235:685d5f11838f 1747 dmainit.ForwardUndersizedGoodFrames = ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE;
mbed_official 235:685d5f11838f 1748 dmainit.ReceiveThresholdControl = ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES;
mbed_official 235:685d5f11838f 1749 dmainit.SecondFrameOperate = ETH_SECONDFRAMEOPERARTE_ENABLE;
mbed_official 235:685d5f11838f 1750 dmainit.AddressAlignedBeats = ETH_ADDRESSALIGNEDBEATS_ENABLE;
mbed_official 235:685d5f11838f 1751 dmainit.FixedBurst = ETH_FIXEDBURST_ENABLE;
mbed_official 235:685d5f11838f 1752 dmainit.RxDMABurstLength = ETH_RXDMABURSTLENGTH_32BEAT;
mbed_official 235:685d5f11838f 1753 dmainit.TxDMABurstLength = ETH_TXDMABURSTLENGTH_32BEAT;
mbed_official 235:685d5f11838f 1754 dmainit.EnhancedDescriptorFormat = ETH_DMAENHANCEDDESCRIPTOR_ENABLE;
mbed_official 235:685d5f11838f 1755 dmainit.DescriptorSkipLength = 0x0;
mbed_official 235:685d5f11838f 1756 dmainit.DMAArbitration = ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1;
mbed_official 235:685d5f11838f 1757
mbed_official 235:685d5f11838f 1758 /* Get the ETHERNET DMAOMR value */
mbed_official 532:fe11edbda85c 1759 tmpreg1 = (heth->Instance)->DMAOMR;
mbed_official 235:685d5f11838f 1760 /* Clear xx bits */
mbed_official 532:fe11edbda85c 1761 tmpreg1 &= ETH_DMAOMR_CLEAR_MASK;
mbed_official 235:685d5f11838f 1762
mbed_official 235:685d5f11838f 1763 /* Set the DT bit according to ETH DropTCPIPChecksumErrorFrame value */
mbed_official 235:685d5f11838f 1764 /* Set the RSF bit according to ETH ReceiveStoreForward value */
mbed_official 235:685d5f11838f 1765 /* Set the DFF bit according to ETH FlushReceivedFrame value */
mbed_official 235:685d5f11838f 1766 /* Set the TSF bit according to ETH TransmitStoreForward value */
mbed_official 235:685d5f11838f 1767 /* Set the TTC bit according to ETH TransmitThresholdControl value */
mbed_official 235:685d5f11838f 1768 /* Set the FEF bit according to ETH ForwardErrorFrames value */
mbed_official 235:685d5f11838f 1769 /* Set the FUF bit according to ETH ForwardUndersizedGoodFrames value */
mbed_official 235:685d5f11838f 1770 /* Set the RTC bit according to ETH ReceiveThresholdControl value */
mbed_official 235:685d5f11838f 1771 /* Set the OSF bit according to ETH SecondFrameOperate value */
mbed_official 532:fe11edbda85c 1772 tmpreg1 |= (uint32_t)(dmainit.DropTCPIPChecksumErrorFrame |
mbed_official 235:685d5f11838f 1773 dmainit.ReceiveStoreForward |
mbed_official 235:685d5f11838f 1774 dmainit.FlushReceivedFrame |
mbed_official 235:685d5f11838f 1775 dmainit.TransmitStoreForward |
mbed_official 235:685d5f11838f 1776 dmainit.TransmitThresholdControl |
mbed_official 235:685d5f11838f 1777 dmainit.ForwardErrorFrames |
mbed_official 235:685d5f11838f 1778 dmainit.ForwardUndersizedGoodFrames |
mbed_official 235:685d5f11838f 1779 dmainit.ReceiveThresholdControl |
mbed_official 235:685d5f11838f 1780 dmainit.SecondFrameOperate);
mbed_official 235:685d5f11838f 1781
mbed_official 235:685d5f11838f 1782 /* Write to ETHERNET DMAOMR */
mbed_official 532:fe11edbda85c 1783 (heth->Instance)->DMAOMR = (uint32_t)tmpreg1;
mbed_official 235:685d5f11838f 1784
mbed_official 235:685d5f11838f 1785 /* Wait until the write operation will be taken into account:
mbed_official 235:685d5f11838f 1786 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 532:fe11edbda85c 1787 tmpreg1 = (heth->Instance)->DMAOMR;
mbed_official 235:685d5f11838f 1788 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 532:fe11edbda85c 1789 (heth->Instance)->DMAOMR = tmpreg1;
mbed_official 235:685d5f11838f 1790
mbed_official 235:685d5f11838f 1791 /*----------------------- ETHERNET DMABMR Configuration ------------------*/
mbed_official 235:685d5f11838f 1792 /* Set the AAL bit according to ETH AddressAlignedBeats value */
mbed_official 235:685d5f11838f 1793 /* Set the FB bit according to ETH FixedBurst value */
mbed_official 235:685d5f11838f 1794 /* Set the RPBL and 4*PBL bits according to ETH RxDMABurstLength value */
mbed_official 235:685d5f11838f 1795 /* Set the PBL and 4*PBL bits according to ETH TxDMABurstLength value */
mbed_official 235:685d5f11838f 1796 /* Set the Enhanced DMA descriptors bit according to ETH EnhancedDescriptorFormat value*/
mbed_official 235:685d5f11838f 1797 /* Set the DSL bit according to ETH DesciptorSkipLength value */
mbed_official 235:685d5f11838f 1798 /* Set the PR and DA bits according to ETH DMAArbitration value */
mbed_official 235:685d5f11838f 1799 (heth->Instance)->DMABMR = (uint32_t)(dmainit.AddressAlignedBeats |
mbed_official 235:685d5f11838f 1800 dmainit.FixedBurst |
mbed_official 235:685d5f11838f 1801 dmainit.RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */
mbed_official 235:685d5f11838f 1802 dmainit.TxDMABurstLength |
mbed_official 235:685d5f11838f 1803 dmainit.EnhancedDescriptorFormat |
mbed_official 235:685d5f11838f 1804 (dmainit.DescriptorSkipLength << 2) |
mbed_official 235:685d5f11838f 1805 dmainit.DMAArbitration |
mbed_official 235:685d5f11838f 1806 ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */
mbed_official 235:685d5f11838f 1807
mbed_official 235:685d5f11838f 1808 /* Wait until the write operation will be taken into account:
mbed_official 235:685d5f11838f 1809 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 532:fe11edbda85c 1810 tmpreg1 = (heth->Instance)->DMABMR;
mbed_official 235:685d5f11838f 1811 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 532:fe11edbda85c 1812 (heth->Instance)->DMABMR = tmpreg1;
mbed_official 235:685d5f11838f 1813
mbed_official 235:685d5f11838f 1814 if((heth->Init).RxMode == ETH_RXINTERRUPT_MODE)
mbed_official 235:685d5f11838f 1815 {
mbed_official 235:685d5f11838f 1816 /* Enable the Ethernet Rx Interrupt */
mbed_official 235:685d5f11838f 1817 __HAL_ETH_DMA_ENABLE_IT((heth), ETH_DMA_IT_NIS | ETH_DMA_IT_R);
mbed_official 235:685d5f11838f 1818 }
mbed_official 235:685d5f11838f 1819
mbed_official 235:685d5f11838f 1820 /* Initialize MAC address in ethernet MAC */
mbed_official 235:685d5f11838f 1821 ETH_MACAddressConfig(heth, ETH_MAC_ADDRESS0, heth->Init.MACAddr);
mbed_official 235:685d5f11838f 1822 }
mbed_official 235:685d5f11838f 1823
mbed_official 235:685d5f11838f 1824 /**
mbed_official 235:685d5f11838f 1825 * @brief Configures the selected MAC address.
mbed_official 235:685d5f11838f 1826 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 235:685d5f11838f 1827 * the configuration information for ETHERNET module
mbed_official 235:685d5f11838f 1828 * @param MacAddr: The MAC address to configure
mbed_official 235:685d5f11838f 1829 * This parameter can be one of the following values:
mbed_official 235:685d5f11838f 1830 * @arg ETH_MAC_Address0: MAC Address0
mbed_official 235:685d5f11838f 1831 * @arg ETH_MAC_Address1: MAC Address1
mbed_official 235:685d5f11838f 1832 * @arg ETH_MAC_Address2: MAC Address2
mbed_official 235:685d5f11838f 1833 * @arg ETH_MAC_Address3: MAC Address3
mbed_official 235:685d5f11838f 1834 * @param Addr: Pointer to MAC address buffer data (6 bytes)
mbed_official 235:685d5f11838f 1835 * @retval HAL status
mbed_official 235:685d5f11838f 1836 */
mbed_official 235:685d5f11838f 1837 static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr)
mbed_official 235:685d5f11838f 1838 {
mbed_official 532:fe11edbda85c 1839 uint32_t tmpreg1;
mbed_official 235:685d5f11838f 1840
mbed_official 235:685d5f11838f 1841 /* Check the parameters */
mbed_official 235:685d5f11838f 1842 assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr));
mbed_official 235:685d5f11838f 1843
mbed_official 235:685d5f11838f 1844 /* Calculate the selected MAC address high register */
mbed_official 532:fe11edbda85c 1845 tmpreg1 = ((uint32_t)Addr[5] << 8) | (uint32_t)Addr[4];
mbed_official 235:685d5f11838f 1846 /* Load the selected MAC address high register */
mbed_official 532:fe11edbda85c 1847 (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_HBASE + MacAddr))) = tmpreg1;
mbed_official 235:685d5f11838f 1848 /* Calculate the selected MAC address low register */
mbed_official 532:fe11edbda85c 1849 tmpreg1 = ((uint32_t)Addr[3] << 24) | ((uint32_t)Addr[2] << 16) | ((uint32_t)Addr[1] << 8) | Addr[0];
mbed_official 235:685d5f11838f 1850
mbed_official 235:685d5f11838f 1851 /* Load the selected MAC address low register */
mbed_official 532:fe11edbda85c 1852 (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_LBASE + MacAddr))) = tmpreg1;
mbed_official 235:685d5f11838f 1853 }
mbed_official 235:685d5f11838f 1854
mbed_official 235:685d5f11838f 1855 /**
mbed_official 235:685d5f11838f 1856 * @brief Enables the MAC transmission.
mbed_official 235:685d5f11838f 1857 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 235:685d5f11838f 1858 * the configuration information for ETHERNET module
mbed_official 235:685d5f11838f 1859 * @retval None
mbed_official 235:685d5f11838f 1860 */
mbed_official 235:685d5f11838f 1861 static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth)
mbed_official 235:685d5f11838f 1862 {
mbed_official 532:fe11edbda85c 1863 __IO uint32_t tmpreg1 = 0;
mbed_official 235:685d5f11838f 1864
mbed_official 235:685d5f11838f 1865 /* Enable the MAC transmission */
mbed_official 235:685d5f11838f 1866 (heth->Instance)->MACCR |= ETH_MACCR_TE;
mbed_official 235:685d5f11838f 1867
mbed_official 235:685d5f11838f 1868 /* Wait until the write operation will be taken into account:
mbed_official 235:685d5f11838f 1869 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 532:fe11edbda85c 1870 tmpreg1 = (heth->Instance)->MACCR;
mbed_official 235:685d5f11838f 1871 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 532:fe11edbda85c 1872 (heth->Instance)->MACCR = tmpreg1;
mbed_official 235:685d5f11838f 1873 }
mbed_official 235:685d5f11838f 1874
mbed_official 235:685d5f11838f 1875 /**
mbed_official 235:685d5f11838f 1876 * @brief Disables the MAC transmission.
mbed_official 235:685d5f11838f 1877 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 235:685d5f11838f 1878 * the configuration information for ETHERNET module
mbed_official 235:685d5f11838f 1879 * @retval None
mbed_official 235:685d5f11838f 1880 */
mbed_official 235:685d5f11838f 1881 static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth)
mbed_official 235:685d5f11838f 1882 {
mbed_official 532:fe11edbda85c 1883 __IO uint32_t tmpreg1 = 0;
mbed_official 235:685d5f11838f 1884
mbed_official 235:685d5f11838f 1885 /* Disable the MAC transmission */
mbed_official 235:685d5f11838f 1886 (heth->Instance)->MACCR &= ~ETH_MACCR_TE;
mbed_official 235:685d5f11838f 1887
mbed_official 235:685d5f11838f 1888 /* Wait until the write operation will be taken into account:
mbed_official 235:685d5f11838f 1889 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 532:fe11edbda85c 1890 tmpreg1 = (heth->Instance)->MACCR;
mbed_official 235:685d5f11838f 1891 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 532:fe11edbda85c 1892 (heth->Instance)->MACCR = tmpreg1;
mbed_official 235:685d5f11838f 1893 }
mbed_official 235:685d5f11838f 1894
mbed_official 235:685d5f11838f 1895 /**
mbed_official 235:685d5f11838f 1896 * @brief Enables the MAC reception.
mbed_official 235:685d5f11838f 1897 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 235:685d5f11838f 1898 * the configuration information for ETHERNET module
mbed_official 235:685d5f11838f 1899 * @retval None
mbed_official 235:685d5f11838f 1900 */
mbed_official 235:685d5f11838f 1901 static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth)
mbed_official 235:685d5f11838f 1902 {
mbed_official 532:fe11edbda85c 1903 __IO uint32_t tmpreg1 = 0;
mbed_official 235:685d5f11838f 1904
mbed_official 235:685d5f11838f 1905 /* Enable the MAC reception */
mbed_official 235:685d5f11838f 1906 (heth->Instance)->MACCR |= ETH_MACCR_RE;
mbed_official 235:685d5f11838f 1907
mbed_official 235:685d5f11838f 1908 /* Wait until the write operation will be taken into account:
mbed_official 235:685d5f11838f 1909 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 532:fe11edbda85c 1910 tmpreg1 = (heth->Instance)->MACCR;
mbed_official 235:685d5f11838f 1911 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 532:fe11edbda85c 1912 (heth->Instance)->MACCR = tmpreg1;
mbed_official 235:685d5f11838f 1913 }
mbed_official 235:685d5f11838f 1914
mbed_official 235:685d5f11838f 1915 /**
mbed_official 235:685d5f11838f 1916 * @brief Disables the MAC reception.
mbed_official 235:685d5f11838f 1917 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 235:685d5f11838f 1918 * the configuration information for ETHERNET module
mbed_official 235:685d5f11838f 1919 * @retval None
mbed_official 235:685d5f11838f 1920 */
mbed_official 235:685d5f11838f 1921 static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth)
mbed_official 235:685d5f11838f 1922 {
mbed_official 532:fe11edbda85c 1923 __IO uint32_t tmpreg1 = 0;
mbed_official 235:685d5f11838f 1924
mbed_official 235:685d5f11838f 1925 /* Disable the MAC reception */
mbed_official 235:685d5f11838f 1926 (heth->Instance)->MACCR &= ~ETH_MACCR_RE;
mbed_official 235:685d5f11838f 1927
mbed_official 235:685d5f11838f 1928 /* Wait until the write operation will be taken into account:
mbed_official 235:685d5f11838f 1929 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 532:fe11edbda85c 1930 tmpreg1 = (heth->Instance)->MACCR;
mbed_official 235:685d5f11838f 1931 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 532:fe11edbda85c 1932 (heth->Instance)->MACCR = tmpreg1;
mbed_official 235:685d5f11838f 1933 }
mbed_official 235:685d5f11838f 1934
mbed_official 235:685d5f11838f 1935 /**
mbed_official 235:685d5f11838f 1936 * @brief Enables the DMA transmission.
mbed_official 235:685d5f11838f 1937 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 235:685d5f11838f 1938 * the configuration information for ETHERNET module
mbed_official 235:685d5f11838f 1939 * @retval None
mbed_official 235:685d5f11838f 1940 */
mbed_official 235:685d5f11838f 1941 static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth)
mbed_official 235:685d5f11838f 1942 {
mbed_official 235:685d5f11838f 1943 /* Enable the DMA transmission */
mbed_official 235:685d5f11838f 1944 (heth->Instance)->DMAOMR |= ETH_DMAOMR_ST;
mbed_official 235:685d5f11838f 1945 }
mbed_official 235:685d5f11838f 1946
mbed_official 235:685d5f11838f 1947 /**
mbed_official 235:685d5f11838f 1948 * @brief Disables the DMA transmission.
mbed_official 235:685d5f11838f 1949 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 235:685d5f11838f 1950 * the configuration information for ETHERNET module
mbed_official 235:685d5f11838f 1951 * @retval None
mbed_official 235:685d5f11838f 1952 */
mbed_official 235:685d5f11838f 1953 static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth)
mbed_official 235:685d5f11838f 1954 {
mbed_official 235:685d5f11838f 1955 /* Disable the DMA transmission */
mbed_official 235:685d5f11838f 1956 (heth->Instance)->DMAOMR &= ~ETH_DMAOMR_ST;
mbed_official 235:685d5f11838f 1957 }
mbed_official 235:685d5f11838f 1958
mbed_official 235:685d5f11838f 1959 /**
mbed_official 235:685d5f11838f 1960 * @brief Enables the DMA reception.
mbed_official 235:685d5f11838f 1961 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 235:685d5f11838f 1962 * the configuration information for ETHERNET module
mbed_official 235:685d5f11838f 1963 * @retval None
mbed_official 235:685d5f11838f 1964 */
mbed_official 235:685d5f11838f 1965 static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth)
mbed_official 235:685d5f11838f 1966 {
mbed_official 235:685d5f11838f 1967 /* Enable the DMA reception */
mbed_official 235:685d5f11838f 1968 (heth->Instance)->DMAOMR |= ETH_DMAOMR_SR;
mbed_official 235:685d5f11838f 1969 }
mbed_official 235:685d5f11838f 1970
mbed_official 235:685d5f11838f 1971 /**
mbed_official 235:685d5f11838f 1972 * @brief Disables the DMA reception.
mbed_official 235:685d5f11838f 1973 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 235:685d5f11838f 1974 * the configuration information for ETHERNET module
mbed_official 235:685d5f11838f 1975 * @retval None
mbed_official 235:685d5f11838f 1976 */
mbed_official 235:685d5f11838f 1977 static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth)
mbed_official 235:685d5f11838f 1978 {
mbed_official 235:685d5f11838f 1979 /* Disable the DMA reception */
mbed_official 235:685d5f11838f 1980 (heth->Instance)->DMAOMR &= ~ETH_DMAOMR_SR;
mbed_official 235:685d5f11838f 1981 }
mbed_official 235:685d5f11838f 1982
mbed_official 235:685d5f11838f 1983 /**
mbed_official 235:685d5f11838f 1984 * @brief Clears the ETHERNET transmit FIFO.
mbed_official 235:685d5f11838f 1985 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 235:685d5f11838f 1986 * the configuration information for ETHERNET module
mbed_official 235:685d5f11838f 1987 * @retval None
mbed_official 235:685d5f11838f 1988 */
mbed_official 235:685d5f11838f 1989 static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth)
mbed_official 235:685d5f11838f 1990 {
mbed_official 532:fe11edbda85c 1991 __IO uint32_t tmpreg1 = 0;
mbed_official 235:685d5f11838f 1992
mbed_official 235:685d5f11838f 1993 /* Set the Flush Transmit FIFO bit */
mbed_official 235:685d5f11838f 1994 (heth->Instance)->DMAOMR |= ETH_DMAOMR_FTF;
mbed_official 235:685d5f11838f 1995
mbed_official 235:685d5f11838f 1996 /* Wait until the write operation will be taken into account:
mbed_official 235:685d5f11838f 1997 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 532:fe11edbda85c 1998 tmpreg1 = (heth->Instance)->DMAOMR;
mbed_official 235:685d5f11838f 1999 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 532:fe11edbda85c 2000 (heth->Instance)->DMAOMR = tmpreg1;
mbed_official 235:685d5f11838f 2001 }
mbed_official 235:685d5f11838f 2002
mbed_official 235:685d5f11838f 2003 /**
mbed_official 235:685d5f11838f 2004 * @}
mbed_official 235:685d5f11838f 2005 */
mbed_official 235:685d5f11838f 2006
mbed_official 235:685d5f11838f 2007 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
mbed_official 235:685d5f11838f 2008 #endif /* HAL_ETH_MODULE_ENABLED */
mbed_official 235:685d5f11838f 2009 /**
mbed_official 235:685d5f11838f 2010 * @}
mbed_official 235:685d5f11838f 2011 */
mbed_official 235:685d5f11838f 2012
mbed_official 235:685d5f11838f 2013 /**
mbed_official 235:685d5f11838f 2014 * @}
mbed_official 235:685d5f11838f 2015 */
mbed_official 235:685d5f11838f 2016
mbed_official 235:685d5f11838f 2017 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/