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Last commit 20 Feb 2019 by 
mbed official
targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_ll_fsmc.c@581:39197bcd20f2, 2015-07-02 (annotated)
- Committer:
- mbed_official
- Date:
- Thu Jul 02 16:30:08 2015 +0100
- Revision:
- 581:39197bcd20f2
- Parent:
- 489:119543c9f674
Synchronized with git revision ae2d3cdffe70184eb8736d94f76c45c93f4b7724
Full URL: https://github.com/mbedmicro/mbed/commit/ae2d3cdffe70184eb8736d94f76c45c93f4b7724/
Make it possible to build the core mbed library with yotta
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| mbed_official | 489:119543c9f674 | 1 | /** |
| mbed_official | 489:119543c9f674 | 2 | ****************************************************************************** |
| mbed_official | 489:119543c9f674 | 3 | * @file stm32f1xx_ll_fsmc.c |
| mbed_official | 489:119543c9f674 | 4 | * @author MCD Application Team |
| mbed_official | 489:119543c9f674 | 5 | * @version V1.0.0 |
| mbed_official | 489:119543c9f674 | 6 | * @date 15-December-2014 |
| mbed_official | 489:119543c9f674 | 7 | * @brief FSMC Low Layer HAL module driver. |
| mbed_official | 489:119543c9f674 | 8 | * |
| mbed_official | 489:119543c9f674 | 9 | * This file provides firmware functions to manage the following |
| mbed_official | 489:119543c9f674 | 10 | * functionalities of the Flexible Static Memory Controller (FSMC) peripheral memories: |
| mbed_official | 489:119543c9f674 | 11 | * + Initialization/de-initialization functions |
| mbed_official | 489:119543c9f674 | 12 | * + Peripheral Control functions |
| mbed_official | 489:119543c9f674 | 13 | * + Peripheral State functions |
| mbed_official | 489:119543c9f674 | 14 | * |
| mbed_official | 489:119543c9f674 | 15 | @verbatim |
| mbed_official | 489:119543c9f674 | 16 | ============================================================================= |
| mbed_official | 489:119543c9f674 | 17 | ##### FSMC peripheral features ##### |
| mbed_official | 489:119543c9f674 | 18 | ============================================================================= |
| mbed_official | 489:119543c9f674 | 19 | [..] The Flexible static memory controller (FSMC) includes following memory controllers: |
| mbed_official | 489:119543c9f674 | 20 | (+) The NOR/PSRAM memory controller |
| mbed_official | 489:119543c9f674 | 21 | (+) The NAND/PC Card memory controller (except STM32F100xE devices) |
| mbed_official | 489:119543c9f674 | 22 | |
| mbed_official | 489:119543c9f674 | 23 | [..] The FSMC functional block makes the interface with synchronous and asynchronous static |
| mbed_official | 489:119543c9f674 | 24 | memories and 16-bit PC memory cards. Its main purposes are: |
| mbed_official | 489:119543c9f674 | 25 | (+) to translate AHB transactions into the appropriate external device protocol. |
| mbed_official | 489:119543c9f674 | 26 | (+) to meet the access time requirements of the external memory devices. |
| mbed_official | 489:119543c9f674 | 27 | |
| mbed_official | 489:119543c9f674 | 28 | [..] All external memories share the addresses, data and control signals with the controller. |
| mbed_official | 489:119543c9f674 | 29 | Each external device is accessed by means of a unique Chip Select. The FSMC performs |
| mbed_official | 489:119543c9f674 | 30 | only one access at a time to an external device. |
| mbed_official | 489:119543c9f674 | 31 | The main features of the FSMC controller are the following: |
| mbed_official | 489:119543c9f674 | 32 | (+) Interface with static-memory mapped devices including: |
| mbed_official | 489:119543c9f674 | 33 | (++) Static random access memory (SRAM). |
| mbed_official | 489:119543c9f674 | 34 | (++) NOR Flash memory. |
| mbed_official | 489:119543c9f674 | 35 | (++) PSRAM (4 memory banks). |
| mbed_official | 489:119543c9f674 | 36 | (++) 16-bit PC Card compatible devices |
| mbed_official | 489:119543c9f674 | 37 | (++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of |
| mbed_official | 489:119543c9f674 | 38 | data |
| mbed_official | 489:119543c9f674 | 39 | (+) Independent Chip Select control for each memory bank |
| mbed_official | 489:119543c9f674 | 40 | (+) Independent configuration for each memory bank |
| mbed_official | 489:119543c9f674 | 41 | |
| mbed_official | 489:119543c9f674 | 42 | @endverbatim |
| mbed_official | 489:119543c9f674 | 43 | ****************************************************************************** |
| mbed_official | 489:119543c9f674 | 44 | * @attention |
| mbed_official | 489:119543c9f674 | 45 | * |
| mbed_official | 489:119543c9f674 | 46 | * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> |
| mbed_official | 489:119543c9f674 | 47 | * |
| mbed_official | 489:119543c9f674 | 48 | * Redistribution and use in source and binary forms, with or without modification, |
| mbed_official | 489:119543c9f674 | 49 | * are permitted provided that the following conditions are met: |
| mbed_official | 489:119543c9f674 | 50 | * 1. Redistributions of source code must retain the above copyright notice, |
| mbed_official | 489:119543c9f674 | 51 | * this list of conditions and the following disclaimer. |
| mbed_official | 489:119543c9f674 | 52 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| mbed_official | 489:119543c9f674 | 53 | * this list of conditions and the following disclaimer in the documentation |
| mbed_official | 489:119543c9f674 | 54 | * and/or other materials provided with the distribution. |
| mbed_official | 489:119543c9f674 | 55 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| mbed_official | 489:119543c9f674 | 56 | * may be used to endorse or promote products derived from this software |
| mbed_official | 489:119543c9f674 | 57 | * without specific prior written permission. |
| mbed_official | 489:119543c9f674 | 58 | * |
| mbed_official | 489:119543c9f674 | 59 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| mbed_official | 489:119543c9f674 | 60 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| mbed_official | 489:119543c9f674 | 61 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| mbed_official | 489:119543c9f674 | 62 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| mbed_official | 489:119543c9f674 | 63 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| mbed_official | 489:119543c9f674 | 64 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| mbed_official | 489:119543c9f674 | 65 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| mbed_official | 489:119543c9f674 | 66 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| mbed_official | 489:119543c9f674 | 67 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| mbed_official | 489:119543c9f674 | 68 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| mbed_official | 489:119543c9f674 | 69 | * |
| mbed_official | 489:119543c9f674 | 70 | ****************************************************************************** |
| mbed_official | 489:119543c9f674 | 71 | */ |
| mbed_official | 489:119543c9f674 | 72 | |
| mbed_official | 489:119543c9f674 | 73 | /* Includes ------------------------------------------------------------------*/ |
| mbed_official | 489:119543c9f674 | 74 | #include "stm32f1xx_hal.h" |
| mbed_official | 489:119543c9f674 | 75 | |
| mbed_official | 489:119543c9f674 | 76 | /** @addtogroup STM32F1xx_HAL_Driver |
| mbed_official | 489:119543c9f674 | 77 | * @{ |
| mbed_official | 489:119543c9f674 | 78 | */ |
| mbed_official | 489:119543c9f674 | 79 | |
| mbed_official | 489:119543c9f674 | 80 | #if defined (HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_PCCARD_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) |
| mbed_official | 489:119543c9f674 | 81 | |
| mbed_official | 489:119543c9f674 | 82 | #if defined (STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) || defined(STM32F100xE) |
| mbed_official | 489:119543c9f674 | 83 | |
| mbed_official | 489:119543c9f674 | 84 | /** @defgroup FSMC_LL FSMC_LL |
| mbed_official | 489:119543c9f674 | 85 | * @brief FSMC driver modules |
| mbed_official | 489:119543c9f674 | 86 | * @{ |
| mbed_official | 489:119543c9f674 | 87 | */ |
| mbed_official | 489:119543c9f674 | 88 | |
| mbed_official | 489:119543c9f674 | 89 | /* Private typedef -----------------------------------------------------------*/ |
| mbed_official | 489:119543c9f674 | 90 | /* Private define ------------------------------------------------------------*/ |
| mbed_official | 489:119543c9f674 | 91 | /** @defgroup FSMC_LL_Private_Constants FSMC Low Layer Private Constants |
| mbed_official | 489:119543c9f674 | 92 | * @{ |
| mbed_official | 489:119543c9f674 | 93 | */ |
| mbed_official | 489:119543c9f674 | 94 | |
| mbed_official | 489:119543c9f674 | 95 | /* ----------------------- FMC registers bit mask --------------------------- */ |
| mbed_official | 489:119543c9f674 | 96 | /* --- PCR Register ---*/ |
| mbed_official | 489:119543c9f674 | 97 | /* PCR register clear mask */ |
| mbed_official | 489:119543c9f674 | 98 | #define PCR_CLEAR_MASK ((uint32_t)(FSMC_PCRx_PWAITEN | FSMC_PCRx_PTYP | FSMC_PCRx_PWID | \ |
| mbed_official | 489:119543c9f674 | 99 | FSMC_PCRx_ECCEN | FSMC_PCRx_TCLR | \ |
| mbed_official | 489:119543c9f674 | 100 | FSMC_PCRx_TAR | FSMC_PCRx_ECCPS)) |
| mbed_official | 489:119543c9f674 | 101 | |
| mbed_official | 489:119543c9f674 | 102 | /* --- SR Register ---*/ |
| mbed_official | 489:119543c9f674 | 103 | /* SR register clear mask */ |
| mbed_official | 489:119543c9f674 | 104 | #define SR_CLEAR_MASK ((uint32_t)(FSMC_SRx_IRS | FSMC_SRx_ILS | FSMC_SRx_IFS | \ |
| mbed_official | 489:119543c9f674 | 105 | FSMC_SRx_IREN | FSMC_SRx_ILEN | FSMC_SRx_IFEN)) |
| mbed_official | 489:119543c9f674 | 106 | |
| mbed_official | 489:119543c9f674 | 107 | /* --- PMEM Register ---*/ |
| mbed_official | 489:119543c9f674 | 108 | /* PMEM register clear mask */ |
| mbed_official | 489:119543c9f674 | 109 | #define PMEM_CLEAR_MASK ((uint32_t)(FSMC_PMEMx_MEMSETx | FSMC_PMEMx_MEMWAITx |\ |
| mbed_official | 489:119543c9f674 | 110 | FSMC_PMEMx_MEMHOLDx | FSMC_PMEMx_MEMHIZx)) |
| mbed_official | 489:119543c9f674 | 111 | |
| mbed_official | 489:119543c9f674 | 112 | /* --- PATT Register ---*/ |
| mbed_official | 489:119543c9f674 | 113 | /* PATT register clear mask */ |
| mbed_official | 489:119543c9f674 | 114 | #define PATT_CLEAR_MASK ((uint32_t)(FSMC_PATTx_ATTSETx | FSMC_PATTx_ATTWAITx |\ |
| mbed_official | 489:119543c9f674 | 115 | FSMC_PATTx_ATTHOLDx | FSMC_PATTx_ATTHIZx)) |
| mbed_official | 489:119543c9f674 | 116 | |
| mbed_official | 489:119543c9f674 | 117 | /* --- PIO4 Register ---*/ |
| mbed_official | 489:119543c9f674 | 118 | /* PIO4 register clear mask */ |
| mbed_official | 489:119543c9f674 | 119 | #define PIO4_CLEAR_MASK ((uint32_t)(FSMC_PIO4_IOSET4 | FSMC_PIO4_IOWAIT4 | \ |
| mbed_official | 489:119543c9f674 | 120 | FSMC_PIO4_IOHOLD4 | FSMC_PIO4_IOHIZ4)) |
| mbed_official | 489:119543c9f674 | 121 | /** |
| mbed_official | 489:119543c9f674 | 122 | * @} |
| mbed_official | 489:119543c9f674 | 123 | */ |
| mbed_official | 489:119543c9f674 | 124 | |
| mbed_official | 489:119543c9f674 | 125 | /* Private macro -------------------------------------------------------------*/ |
| mbed_official | 489:119543c9f674 | 126 | /** @defgroup FSMC_LL_Private_Macros FSMC Low Layer Private Macros |
| mbed_official | 489:119543c9f674 | 127 | * @{ |
| mbed_official | 489:119543c9f674 | 128 | */ |
| mbed_official | 489:119543c9f674 | 129 | |
| mbed_official | 489:119543c9f674 | 130 | /** |
| mbed_official | 489:119543c9f674 | 131 | * @} |
| mbed_official | 489:119543c9f674 | 132 | */ |
| mbed_official | 489:119543c9f674 | 133 | |
| mbed_official | 489:119543c9f674 | 134 | /* Private variables ---------------------------------------------------------*/ |
| mbed_official | 489:119543c9f674 | 135 | /* Private function prototypes -----------------------------------------------*/ |
| mbed_official | 489:119543c9f674 | 136 | /* Exported functions --------------------------------------------------------*/ |
| mbed_official | 489:119543c9f674 | 137 | |
| mbed_official | 489:119543c9f674 | 138 | /** @defgroup FSMC_LL_Exported_Functions FSMC Low Layer Exported Functions |
| mbed_official | 489:119543c9f674 | 139 | * @{ |
| mbed_official | 489:119543c9f674 | 140 | */ |
| mbed_official | 489:119543c9f674 | 141 | |
| mbed_official | 489:119543c9f674 | 142 | /** @defgroup FSMC_NORSRAM FSMC NORSRAM Controller functions |
| mbed_official | 489:119543c9f674 | 143 | * @brief NORSRAM Controller functions |
| mbed_official | 489:119543c9f674 | 144 | * |
| mbed_official | 489:119543c9f674 | 145 | @verbatim |
| mbed_official | 489:119543c9f674 | 146 | ============================================================================== |
| mbed_official | 489:119543c9f674 | 147 | ##### How to use NORSRAM device driver ##### |
| mbed_official | 489:119543c9f674 | 148 | ============================================================================== |
| mbed_official | 489:119543c9f674 | 149 | |
| mbed_official | 489:119543c9f674 | 150 | [..] |
| mbed_official | 489:119543c9f674 | 151 | This driver contains a set of APIs to interface with the FSMC NORSRAM banks in order |
| mbed_official | 489:119543c9f674 | 152 | to run the NORSRAM external devices. |
| mbed_official | 489:119543c9f674 | 153 | |
| mbed_official | 489:119543c9f674 | 154 | (+) FSMC NORSRAM bank reset using the function FSMC_NORSRAM_DeInit() |
| mbed_official | 489:119543c9f674 | 155 | (+) FSMC NORSRAM bank control configuration using the function FSMC_NORSRAM_Init() |
| mbed_official | 489:119543c9f674 | 156 | (+) FSMC NORSRAM bank timing configuration using the function FSMC_NORSRAM_Timing_Init() |
| mbed_official | 489:119543c9f674 | 157 | (+) FSMC NORSRAM bank extended timing configuration using the function |
| mbed_official | 489:119543c9f674 | 158 | FSMC_NORSRAM_Extended_Timing_Init() |
| mbed_official | 489:119543c9f674 | 159 | (+) FSMC NORSRAM bank enable/disable write operation using the functions |
| mbed_official | 489:119543c9f674 | 160 | FSMC_NORSRAM_WriteOperation_Enable()/FSMC_NORSRAM_WriteOperation_Disable() |
| mbed_official | 489:119543c9f674 | 161 | |
| mbed_official | 489:119543c9f674 | 162 | |
| mbed_official | 489:119543c9f674 | 163 | @endverbatim |
| mbed_official | 489:119543c9f674 | 164 | * @{ |
| mbed_official | 489:119543c9f674 | 165 | */ |
| mbed_official | 489:119543c9f674 | 166 | |
| mbed_official | 489:119543c9f674 | 167 | /** @defgroup FSMC_NORSRAM_Group1 Initialization/de-initialization functions |
| mbed_official | 489:119543c9f674 | 168 | * @brief Initialization and Configuration functions |
| mbed_official | 489:119543c9f674 | 169 | * |
| mbed_official | 489:119543c9f674 | 170 | @verbatim |
| mbed_official | 489:119543c9f674 | 171 | ============================================================================== |
| mbed_official | 489:119543c9f674 | 172 | ##### Initialization and de_initialization functions ##### |
| mbed_official | 489:119543c9f674 | 173 | ============================================================================== |
| mbed_official | 489:119543c9f674 | 174 | [..] |
| mbed_official | 489:119543c9f674 | 175 | This section provides functions allowing to: |
| mbed_official | 489:119543c9f674 | 176 | (+) Initialize and configure the FSMC NORSRAM interface |
| mbed_official | 489:119543c9f674 | 177 | (+) De-initialize the FSMC NORSRAM interface |
| mbed_official | 489:119543c9f674 | 178 | (+) Configure the FSMC clock and associated GPIOs |
| mbed_official | 489:119543c9f674 | 179 | |
| mbed_official | 489:119543c9f674 | 180 | @endverbatim |
| mbed_official | 489:119543c9f674 | 181 | * @{ |
| mbed_official | 489:119543c9f674 | 182 | */ |
| mbed_official | 489:119543c9f674 | 183 | |
| mbed_official | 489:119543c9f674 | 184 | /** |
| mbed_official | 489:119543c9f674 | 185 | * @brief Initialize the FSMC_NORSRAM device according to the specified |
| mbed_official | 489:119543c9f674 | 186 | * control parameters in the FSMC_NORSRAM_InitTypeDef |
| mbed_official | 489:119543c9f674 | 187 | * @param Device: Pointer to NORSRAM device instance |
| mbed_official | 489:119543c9f674 | 188 | * @param Init: Pointer to NORSRAM Initialization structure |
| mbed_official | 489:119543c9f674 | 189 | * @retval HAL status |
| mbed_official | 489:119543c9f674 | 190 | */ |
| mbed_official | 489:119543c9f674 | 191 | HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_InitTypeDef* Init) |
| mbed_official | 489:119543c9f674 | 192 | { |
| mbed_official | 489:119543c9f674 | 193 | /* Check the parameters */ |
| mbed_official | 489:119543c9f674 | 194 | assert_param(IS_FSMC_NORSRAM_DEVICE(Device)); |
| mbed_official | 489:119543c9f674 | 195 | assert_param(IS_FSMC_NORSRAM_BANK(Init->NSBank)); |
| mbed_official | 489:119543c9f674 | 196 | assert_param(IS_FSMC_MUX(Init->DataAddressMux)); |
| mbed_official | 489:119543c9f674 | 197 | assert_param(IS_FSMC_MEMORY(Init->MemoryType)); |
| mbed_official | 489:119543c9f674 | 198 | assert_param(IS_FSMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth)); |
| mbed_official | 489:119543c9f674 | 199 | assert_param(IS_FSMC_BURSTMODE(Init->BurstAccessMode)); |
| mbed_official | 489:119543c9f674 | 200 | assert_param(IS_FSMC_WAIT_POLARITY(Init->WaitSignalPolarity)); |
| mbed_official | 489:119543c9f674 | 201 | assert_param(IS_FSMC_WRAP_MODE(Init->WrapMode)); |
| mbed_official | 489:119543c9f674 | 202 | assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive)); |
| mbed_official | 489:119543c9f674 | 203 | assert_param(IS_FSMC_WRITE_OPERATION(Init->WriteOperation)); |
| mbed_official | 489:119543c9f674 | 204 | assert_param(IS_FSMC_WAITE_SIGNAL(Init->WaitSignal)); |
| mbed_official | 489:119543c9f674 | 205 | assert_param(IS_FSMC_EXTENDED_MODE(Init->ExtendedMode)); |
| mbed_official | 489:119543c9f674 | 206 | assert_param(IS_FSMC_ASYNWAIT(Init->AsynchronousWait)); |
| mbed_official | 489:119543c9f674 | 207 | assert_param(IS_FSMC_WRITE_BURST(Init->WriteBurst)); |
| mbed_official | 489:119543c9f674 | 208 | |
| mbed_official | 489:119543c9f674 | 209 | /* Disable NORSRAM Device */ |
| mbed_official | 489:119543c9f674 | 210 | __FSMC_NORSRAM_DISABLE(Device, Init->NSBank); |
| mbed_official | 489:119543c9f674 | 211 | |
| mbed_official | 489:119543c9f674 | 212 | /* Set NORSRAM device control parameters */ |
| mbed_official | 489:119543c9f674 | 213 | if(Init->MemoryType == FSMC_MEMORY_TYPE_NOR) |
| mbed_official | 489:119543c9f674 | 214 | { |
| mbed_official | 489:119543c9f674 | 215 | MODIFY_REG(Device->BTCR[Init->NSBank], \ |
| mbed_official | 489:119543c9f674 | 216 | (FSMC_BCRx_FACCEN | FSMC_BCRx_MUXEN | FSMC_BCRx_MTYP | \ |
| mbed_official | 489:119543c9f674 | 217 | FSMC_BCRx_MWID | FSMC_BCRx_BURSTEN | FSMC_BCRx_WAITPOL | FSMC_BCRx_WRAPMOD | FSMC_BCRx_WAITCFG | \ |
| mbed_official | 489:119543c9f674 | 218 | FSMC_BCRx_WREN | FSMC_BCRx_WAITEN | FSMC_BCRx_EXTMOD | FSMC_BCRx_ASYNCWAIT | FSMC_BCRx_CBURSTRW), \ |
| mbed_official | 489:119543c9f674 | 219 | (FSMC_NORSRAM_FLASH_ACCESS_ENABLE | Init->DataAddressMux | Init->MemoryType | \ |
| mbed_official | 489:119543c9f674 | 220 | Init->MemoryDataWidth | Init->BurstAccessMode | Init->WaitSignalPolarity | Init->WrapMode | Init->WaitSignalActive |\ |
| mbed_official | 489:119543c9f674 | 221 | Init->WriteOperation | Init->WaitSignal | Init->ExtendedMode | Init->AsynchronousWait | Init->WriteBurst ) \ |
| mbed_official | 489:119543c9f674 | 222 | ); |
| mbed_official | 489:119543c9f674 | 223 | } |
| mbed_official | 489:119543c9f674 | 224 | else |
| mbed_official | 489:119543c9f674 | 225 | { |
| mbed_official | 489:119543c9f674 | 226 | MODIFY_REG(Device->BTCR[Init->NSBank], \ |
| mbed_official | 489:119543c9f674 | 227 | (FSMC_BCRx_FACCEN | FSMC_BCRx_MUXEN | FSMC_BCRx_MTYP | \ |
| mbed_official | 489:119543c9f674 | 228 | FSMC_BCRx_MWID | FSMC_BCRx_BURSTEN | FSMC_BCRx_WAITPOL | FSMC_BCRx_WRAPMOD | FSMC_BCRx_WAITCFG | \ |
| mbed_official | 489:119543c9f674 | 229 | FSMC_BCRx_WREN | FSMC_BCRx_WAITEN | FSMC_BCRx_EXTMOD | FSMC_BCRx_ASYNCWAIT | FSMC_BCRx_CBURSTRW), \ |
| mbed_official | 489:119543c9f674 | 230 | (FSMC_NORSRAM_FLASH_ACCESS_DISABLE | Init->DataAddressMux | Init->MemoryType | \ |
| mbed_official | 489:119543c9f674 | 231 | Init->MemoryDataWidth | Init->BurstAccessMode | Init->WaitSignalPolarity | Init->WrapMode | Init->WaitSignalActive |\ |
| mbed_official | 489:119543c9f674 | 232 | Init->WriteOperation | Init->WaitSignal | Init->ExtendedMode | Init->AsynchronousWait | Init->WriteBurst ) \ |
| mbed_official | 489:119543c9f674 | 233 | ); |
| mbed_official | 489:119543c9f674 | 234 | } |
| mbed_official | 489:119543c9f674 | 235 | |
| mbed_official | 489:119543c9f674 | 236 | return HAL_OK; |
| mbed_official | 489:119543c9f674 | 237 | } |
| mbed_official | 489:119543c9f674 | 238 | |
| mbed_official | 489:119543c9f674 | 239 | |
| mbed_official | 489:119543c9f674 | 240 | /** |
| mbed_official | 489:119543c9f674 | 241 | * @brief DeInitialize the FSMC_NORSRAM peripheral |
| mbed_official | 489:119543c9f674 | 242 | * @param Device: Pointer to NORSRAM device instance |
| mbed_official | 489:119543c9f674 | 243 | * @param ExDevice: Pointer to NORSRAM extended mode device instance |
| mbed_official | 489:119543c9f674 | 244 | * @param Bank: NORSRAM bank number |
| mbed_official | 489:119543c9f674 | 245 | * @retval HAL status |
| mbed_official | 489:119543c9f674 | 246 | */ |
| mbed_official | 489:119543c9f674 | 247 | HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank) |
| mbed_official | 489:119543c9f674 | 248 | { |
| mbed_official | 489:119543c9f674 | 249 | /* Check the parameters */ |
| mbed_official | 489:119543c9f674 | 250 | assert_param(IS_FSMC_NORSRAM_DEVICE(Device)); |
| mbed_official | 489:119543c9f674 | 251 | assert_param(IS_FSMC_NORSRAM_EXTENDED_DEVICE(ExDevice)); |
| mbed_official | 489:119543c9f674 | 252 | assert_param(IS_FSMC_NORSRAM_BANK(Bank)); |
| mbed_official | 489:119543c9f674 | 253 | |
| mbed_official | 489:119543c9f674 | 254 | /* Disable the FSMC_NORSRAM device */ |
| mbed_official | 489:119543c9f674 | 255 | __FSMC_NORSRAM_DISABLE(Device, Bank); |
| mbed_official | 489:119543c9f674 | 256 | |
| mbed_official | 489:119543c9f674 | 257 | /* De-initialize the FSMC_NORSRAM device */ |
| mbed_official | 489:119543c9f674 | 258 | /* FSMC_NORSRAM_BANK1 */ |
| mbed_official | 489:119543c9f674 | 259 | if(Bank == FSMC_NORSRAM_BANK1) |
| mbed_official | 489:119543c9f674 | 260 | { |
| mbed_official | 489:119543c9f674 | 261 | Device->BTCR[Bank] = 0x000030DB; |
| mbed_official | 489:119543c9f674 | 262 | } |
| mbed_official | 489:119543c9f674 | 263 | /* FSMC_NORSRAM_BANK2, FSMC_NORSRAM_BANK3 or FSMC_NORSRAM_BANK4 */ |
| mbed_official | 489:119543c9f674 | 264 | else |
| mbed_official | 489:119543c9f674 | 265 | { |
| mbed_official | 489:119543c9f674 | 266 | Device->BTCR[Bank] = 0x000030D2; |
| mbed_official | 489:119543c9f674 | 267 | } |
| mbed_official | 489:119543c9f674 | 268 | |
| mbed_official | 489:119543c9f674 | 269 | Device->BTCR[Bank + 1] = 0x0FFFFFFF; |
| mbed_official | 489:119543c9f674 | 270 | ExDevice->BWTR[Bank] = 0x0FFFFFFF; |
| mbed_official | 489:119543c9f674 | 271 | |
| mbed_official | 489:119543c9f674 | 272 | return HAL_OK; |
| mbed_official | 489:119543c9f674 | 273 | } |
| mbed_official | 489:119543c9f674 | 274 | |
| mbed_official | 489:119543c9f674 | 275 | |
| mbed_official | 489:119543c9f674 | 276 | /** |
| mbed_official | 489:119543c9f674 | 277 | * @brief Initialize the FSMC_NORSRAM Timing according to the specified |
| mbed_official | 489:119543c9f674 | 278 | * parameters in the FSMC_NORSRAM_TimingTypeDef |
| mbed_official | 489:119543c9f674 | 279 | * @param Device: Pointer to NORSRAM device instance |
| mbed_official | 489:119543c9f674 | 280 | * @param Timing: Pointer to NORSRAM Timing structure |
| mbed_official | 489:119543c9f674 | 281 | * @param Bank: NORSRAM bank number |
| mbed_official | 489:119543c9f674 | 282 | * @retval HAL status |
| mbed_official | 489:119543c9f674 | 283 | */ |
| mbed_official | 489:119543c9f674 | 284 | HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank) |
| mbed_official | 489:119543c9f674 | 285 | { |
| mbed_official | 489:119543c9f674 | 286 | /* Check the parameters */ |
| mbed_official | 489:119543c9f674 | 287 | assert_param(IS_FSMC_NORSRAM_DEVICE(Device)); |
| mbed_official | 489:119543c9f674 | 288 | assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); |
| mbed_official | 489:119543c9f674 | 289 | assert_param(IS_FSMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime)); |
| mbed_official | 489:119543c9f674 | 290 | assert_param(IS_FSMC_DATASETUP_TIME(Timing->DataSetupTime)); |
| mbed_official | 489:119543c9f674 | 291 | assert_param(IS_FSMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration)); |
| mbed_official | 489:119543c9f674 | 292 | assert_param(IS_FSMC_CLK_DIV(Timing->CLKDivision)); |
| mbed_official | 489:119543c9f674 | 293 | assert_param(IS_FSMC_DATA_LATENCY(Timing->DataLatency)); |
| mbed_official | 489:119543c9f674 | 294 | assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode)); |
| mbed_official | 489:119543c9f674 | 295 | assert_param(IS_FSMC_NORSRAM_BANK(Bank)); |
| mbed_official | 489:119543c9f674 | 296 | |
| mbed_official | 489:119543c9f674 | 297 | /* Set FSMC_NORSRAM device timing parameters */ |
| mbed_official | 489:119543c9f674 | 298 | MODIFY_REG(Device->BTCR[Bank + 1], \ |
| mbed_official | 489:119543c9f674 | 299 | (FSMC_BTRx_ADDSET | FSMC_BTRx_ADDHLD | FSMC_BTRx_DATAST | FSMC_BTRx_BUSTURN | \ |
| mbed_official | 489:119543c9f674 | 300 | FSMC_BTRx_CLKDIV | FSMC_BTRx_DATLAT | FSMC_BTRx_ACCMOD), \ |
| mbed_official | 489:119543c9f674 | 301 | ( Timing->AddressSetupTime | \ |
| mbed_official | 489:119543c9f674 | 302 | ((Timing->AddressHoldTime) << POSITION_VAL(FSMC_BTRx_ADDHLD)) | \ |
| mbed_official | 489:119543c9f674 | 303 | ((Timing->DataSetupTime) << POSITION_VAL(FSMC_BTRx_DATAST)) | \ |
| mbed_official | 489:119543c9f674 | 304 | ((Timing->BusTurnAroundDuration) << POSITION_VAL(FSMC_BTRx_BUSTURN)) | \ |
| mbed_official | 489:119543c9f674 | 305 | (((Timing->CLKDivision)-1) << POSITION_VAL(FSMC_BTRx_CLKDIV)) | \ |
| mbed_official | 489:119543c9f674 | 306 | (((Timing->DataLatency)-2) << POSITION_VAL(FSMC_BTRx_DATLAT)) | \ |
| mbed_official | 489:119543c9f674 | 307 | (Timing->AccessMode))); |
| mbed_official | 489:119543c9f674 | 308 | |
| mbed_official | 489:119543c9f674 | 309 | return HAL_OK; |
| mbed_official | 489:119543c9f674 | 310 | } |
| mbed_official | 489:119543c9f674 | 311 | |
| mbed_official | 489:119543c9f674 | 312 | /** |
| mbed_official | 489:119543c9f674 | 313 | * @brief Initialize the FSMC_NORSRAM Extended mode Timing according to the specified |
| mbed_official | 489:119543c9f674 | 314 | * parameters in the FSMC_NORSRAM_TimingTypeDef |
| mbed_official | 489:119543c9f674 | 315 | * @param Device: Pointer to NORSRAM device instance |
| mbed_official | 489:119543c9f674 | 316 | * @param Timing: Pointer to NORSRAM Timing structure |
| mbed_official | 489:119543c9f674 | 317 | * @param Bank: NORSRAM bank number |
| mbed_official | 489:119543c9f674 | 318 | * @param ExtendedMode: FSMC Extended Mode |
| mbed_official | 489:119543c9f674 | 319 | * This parameter can be one of the following values: |
| mbed_official | 489:119543c9f674 | 320 | * @arg FSMC_EXTENDED_MODE_DISABLE |
| mbed_official | 489:119543c9f674 | 321 | * @arg FSMC_EXTENDED_MODE_ENABLE |
| mbed_official | 489:119543c9f674 | 322 | * @retval HAL status |
| mbed_official | 489:119543c9f674 | 323 | */ |
| mbed_official | 489:119543c9f674 | 324 | HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode) |
| mbed_official | 489:119543c9f674 | 325 | { |
| mbed_official | 489:119543c9f674 | 326 | /* Check the parameters */ |
| mbed_official | 489:119543c9f674 | 327 | assert_param(IS_FSMC_EXTENDED_MODE(ExtendedMode)); |
| mbed_official | 489:119543c9f674 | 328 | |
| mbed_official | 489:119543c9f674 | 329 | /* Set NORSRAM device timing register for write configuration, if extended mode is used */ |
| mbed_official | 489:119543c9f674 | 330 | if(ExtendedMode == FSMC_EXTENDED_MODE_ENABLE) |
| mbed_official | 489:119543c9f674 | 331 | { |
| mbed_official | 489:119543c9f674 | 332 | /* Check the parameters */ |
| mbed_official | 489:119543c9f674 | 333 | assert_param(IS_FSMC_NORSRAM_EXTENDED_DEVICE(Device)); |
| mbed_official | 489:119543c9f674 | 334 | assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); |
| mbed_official | 489:119543c9f674 | 335 | assert_param(IS_FSMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime)); |
| mbed_official | 489:119543c9f674 | 336 | assert_param(IS_FSMC_DATASETUP_TIME(Timing->DataSetupTime)); |
| mbed_official | 489:119543c9f674 | 337 | #if defined (STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) |
| mbed_official | 489:119543c9f674 | 338 | assert_param(IS_FSMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration)); |
| mbed_official | 489:119543c9f674 | 339 | #else |
| mbed_official | 489:119543c9f674 | 340 | assert_param(IS_FSMC_CLK_DIV(Timing->CLKDivision)); |
| mbed_official | 489:119543c9f674 | 341 | assert_param(IS_FSMC_DATA_LATENCY(Timing->DataLatency)); |
| mbed_official | 489:119543c9f674 | 342 | #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */ |
| mbed_official | 489:119543c9f674 | 343 | assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode)); |
| mbed_official | 489:119543c9f674 | 344 | assert_param(IS_FSMC_NORSRAM_BANK(Bank)); |
| mbed_official | 489:119543c9f674 | 345 | |
| mbed_official | 489:119543c9f674 | 346 | #if defined (STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) |
| mbed_official | 489:119543c9f674 | 347 | MODIFY_REG(Device->BWTR[Bank], \ |
| mbed_official | 489:119543c9f674 | 348 | (FSMC_BWTRx_ADDSET | FSMC_BWTRx_ADDHLD | FSMC_BWTRx_DATAST | FSMC_BWTRx_ACCMOD | FSMC_BWTRx_BUSTURN), \ |
| mbed_official | 489:119543c9f674 | 349 | (Timing->AddressSetupTime | \ |
| mbed_official | 489:119543c9f674 | 350 | ((Timing->AddressHoldTime) << POSITION_VAL(FSMC_BWTRx_ADDHLD)) | \ |
| mbed_official | 489:119543c9f674 | 351 | ((Timing->DataSetupTime) << POSITION_VAL(FSMC_BWTRx_DATAST)) | \ |
| mbed_official | 489:119543c9f674 | 352 | Timing->AccessMode | \ |
| mbed_official | 489:119543c9f674 | 353 | ((Timing->BusTurnAroundDuration) << POSITION_VAL(FSMC_BWTRx_BUSTURN)))); |
| mbed_official | 489:119543c9f674 | 354 | #else |
| mbed_official | 489:119543c9f674 | 355 | MODIFY_REG(Device->BWTR[Bank], \ |
| mbed_official | 489:119543c9f674 | 356 | (FSMC_BWTRx_ADDSET | FSMC_BWTRx_ADDHLD | FSMC_BWTRx_DATAST | FSMC_BWTRx_ACCMOD | FSMC_BWTRx_CLKDIV | FSMC_BWTRx_DATLAT), \ |
| mbed_official | 489:119543c9f674 | 357 | (Timing->AddressSetupTime | \ |
| mbed_official | 489:119543c9f674 | 358 | ((Timing->AddressHoldTime) << POSITION_VAL(FSMC_BWTRx_ADDHLD)) | \ |
| mbed_official | 489:119543c9f674 | 359 | ((Timing->DataSetupTime) << POSITION_VAL(FSMC_BWTRx_DATAST)) | \ |
| mbed_official | 489:119543c9f674 | 360 | Timing->AccessMode | \ |
| mbed_official | 489:119543c9f674 | 361 | (((Timing->CLKDivision)-1) << POSITION_VAL(FSMC_BTRx_CLKDIV)) | \ |
| mbed_official | 489:119543c9f674 | 362 | (((Timing->DataLatency)-2) << POSITION_VAL(FSMC_BWTRx_DATLAT)))); |
| mbed_official | 489:119543c9f674 | 363 | #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */ |
| mbed_official | 489:119543c9f674 | 364 | } |
| mbed_official | 489:119543c9f674 | 365 | else |
| mbed_official | 489:119543c9f674 | 366 | { |
| mbed_official | 489:119543c9f674 | 367 | Device->BWTR[Bank] = 0x0FFFFFFF; |
| mbed_official | 489:119543c9f674 | 368 | } |
| mbed_official | 489:119543c9f674 | 369 | |
| mbed_official | 489:119543c9f674 | 370 | return HAL_OK; |
| mbed_official | 489:119543c9f674 | 371 | } |
| mbed_official | 489:119543c9f674 | 372 | |
| mbed_official | 489:119543c9f674 | 373 | |
| mbed_official | 489:119543c9f674 | 374 | /** |
| mbed_official | 489:119543c9f674 | 375 | * @} |
| mbed_official | 489:119543c9f674 | 376 | */ |
| mbed_official | 489:119543c9f674 | 377 | |
| mbed_official | 489:119543c9f674 | 378 | |
| mbed_official | 489:119543c9f674 | 379 | /** @defgroup FSMC_NORSRAM_Group2 Control functions |
| mbed_official | 489:119543c9f674 | 380 | * @brief management functions |
| mbed_official | 489:119543c9f674 | 381 | * |
| mbed_official | 489:119543c9f674 | 382 | @verbatim |
| mbed_official | 489:119543c9f674 | 383 | ============================================================================== |
| mbed_official | 489:119543c9f674 | 384 | ##### FSMC_NORSRAM Control functions ##### |
| mbed_official | 489:119543c9f674 | 385 | ============================================================================== |
| mbed_official | 489:119543c9f674 | 386 | [..] |
| mbed_official | 489:119543c9f674 | 387 | This subsection provides a set of functions allowing to control dynamically |
| mbed_official | 489:119543c9f674 | 388 | the FSMC NORSRAM interface. |
| mbed_official | 489:119543c9f674 | 389 | |
| mbed_official | 489:119543c9f674 | 390 | @endverbatim |
| mbed_official | 489:119543c9f674 | 391 | * @{ |
| mbed_official | 489:119543c9f674 | 392 | */ |
| mbed_official | 489:119543c9f674 | 393 | |
| mbed_official | 489:119543c9f674 | 394 | /** |
| mbed_official | 489:119543c9f674 | 395 | * @brief Enables dynamically FSMC_NORSRAM write operation. |
| mbed_official | 489:119543c9f674 | 396 | * @param Device: Pointer to NORSRAM device instance |
| mbed_official | 489:119543c9f674 | 397 | * @param Bank: NORSRAM bank number |
| mbed_official | 489:119543c9f674 | 398 | * @retval HAL status |
| mbed_official | 489:119543c9f674 | 399 | */ |
| mbed_official | 489:119543c9f674 | 400 | HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank) |
| mbed_official | 489:119543c9f674 | 401 | { |
| mbed_official | 489:119543c9f674 | 402 | /* Check the parameters */ |
| mbed_official | 489:119543c9f674 | 403 | assert_param(IS_FSMC_NORSRAM_DEVICE(Device)); |
| mbed_official | 489:119543c9f674 | 404 | assert_param(IS_FSMC_NORSRAM_BANK(Bank)); |
| mbed_official | 489:119543c9f674 | 405 | |
| mbed_official | 489:119543c9f674 | 406 | /* Enable write operation */ |
| mbed_official | 489:119543c9f674 | 407 | SET_BIT(Device->BTCR[Bank], FSMC_WRITE_OPERATION_ENABLE); |
| mbed_official | 489:119543c9f674 | 408 | |
| mbed_official | 489:119543c9f674 | 409 | return HAL_OK; |
| mbed_official | 489:119543c9f674 | 410 | } |
| mbed_official | 489:119543c9f674 | 411 | |
| mbed_official | 489:119543c9f674 | 412 | /** |
| mbed_official | 489:119543c9f674 | 413 | * @brief Disables dynamically FSMC_NORSRAM write operation. |
| mbed_official | 489:119543c9f674 | 414 | * @param Device: Pointer to NORSRAM device instance |
| mbed_official | 489:119543c9f674 | 415 | * @param Bank: NORSRAM bank number |
| mbed_official | 489:119543c9f674 | 416 | * @retval HAL status |
| mbed_official | 489:119543c9f674 | 417 | */ |
| mbed_official | 489:119543c9f674 | 418 | HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank) |
| mbed_official | 489:119543c9f674 | 419 | { |
| mbed_official | 489:119543c9f674 | 420 | /* Check the parameters */ |
| mbed_official | 489:119543c9f674 | 421 | assert_param(IS_FSMC_NORSRAM_DEVICE(Device)); |
| mbed_official | 489:119543c9f674 | 422 | assert_param(IS_FSMC_NORSRAM_BANK(Bank)); |
| mbed_official | 489:119543c9f674 | 423 | |
| mbed_official | 489:119543c9f674 | 424 | /* Disable write operation */ |
| mbed_official | 489:119543c9f674 | 425 | CLEAR_BIT(Device->BTCR[Bank], FSMC_WRITE_OPERATION_ENABLE); |
| mbed_official | 489:119543c9f674 | 426 | |
| mbed_official | 489:119543c9f674 | 427 | return HAL_OK; |
| mbed_official | 489:119543c9f674 | 428 | } |
| mbed_official | 489:119543c9f674 | 429 | |
| mbed_official | 489:119543c9f674 | 430 | /** |
| mbed_official | 489:119543c9f674 | 431 | * @} |
| mbed_official | 489:119543c9f674 | 432 | */ |
| mbed_official | 489:119543c9f674 | 433 | |
| mbed_official | 489:119543c9f674 | 434 | /** |
| mbed_official | 489:119543c9f674 | 435 | * @} |
| mbed_official | 489:119543c9f674 | 436 | */ |
| mbed_official | 489:119543c9f674 | 437 | #if defined (STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) |
| mbed_official | 489:119543c9f674 | 438 | /** @defgroup FSMC_NAND FSMC NAND Controller functions |
| mbed_official | 489:119543c9f674 | 439 | * @brief NAND Controller functions |
| mbed_official | 489:119543c9f674 | 440 | * |
| mbed_official | 489:119543c9f674 | 441 | @verbatim |
| mbed_official | 489:119543c9f674 | 442 | ============================================================================== |
| mbed_official | 489:119543c9f674 | 443 | ##### How to use NAND device driver ##### |
| mbed_official | 489:119543c9f674 | 444 | ============================================================================== |
| mbed_official | 489:119543c9f674 | 445 | [..] |
| mbed_official | 489:119543c9f674 | 446 | This driver contains a set of APIs to interface with the FSMC NAND banks in order |
| mbed_official | 489:119543c9f674 | 447 | to run the NAND external devices. |
| mbed_official | 489:119543c9f674 | 448 | |
| mbed_official | 489:119543c9f674 | 449 | (+) FSMC NAND bank reset using the function FSMC_NAND_DeInit() |
| mbed_official | 489:119543c9f674 | 450 | (+) FSMC NAND bank control configuration using the function FSMC_NAND_Init() |
| mbed_official | 489:119543c9f674 | 451 | (+) FSMC NAND bank common space timing configuration using the function |
| mbed_official | 489:119543c9f674 | 452 | FSMC_NAND_CommonSpace_Timing_Init() |
| mbed_official | 489:119543c9f674 | 453 | (+) FSMC NAND bank attribute space timing configuration using the function |
| mbed_official | 489:119543c9f674 | 454 | FSMC_NAND_AttributeSpace_Timing_Init() |
| mbed_official | 489:119543c9f674 | 455 | (+) FSMC NAND bank enable/disable ECC correction feature using the functions |
| mbed_official | 489:119543c9f674 | 456 | FSMC_NAND_ECC_Enable()/FSMC_NAND_ECC_Disable() |
| mbed_official | 489:119543c9f674 | 457 | (+) FSMC NAND bank get ECC correction code using the function FSMC_NAND_GetECC() |
| mbed_official | 489:119543c9f674 | 458 | |
| mbed_official | 489:119543c9f674 | 459 | @endverbatim |
| mbed_official | 489:119543c9f674 | 460 | * @{ |
| mbed_official | 489:119543c9f674 | 461 | */ |
| mbed_official | 489:119543c9f674 | 462 | |
| mbed_official | 489:119543c9f674 | 463 | /** @defgroup FSMC_NAND_Exported_Functions_Group1 Initialization and de-initialization functions |
| mbed_official | 489:119543c9f674 | 464 | * @brief Initialization and Configuration functions |
| mbed_official | 489:119543c9f674 | 465 | * |
| mbed_official | 489:119543c9f674 | 466 | @verbatim |
| mbed_official | 489:119543c9f674 | 467 | ============================================================================== |
| mbed_official | 489:119543c9f674 | 468 | ##### Initialization and de_initialization functions ##### |
| mbed_official | 489:119543c9f674 | 469 | ============================================================================== |
| mbed_official | 489:119543c9f674 | 470 | [..] |
| mbed_official | 489:119543c9f674 | 471 | This section provides functions allowing to: |
| mbed_official | 489:119543c9f674 | 472 | (+) Initialize and configure the FSMC NAND interface |
| mbed_official | 489:119543c9f674 | 473 | (+) De-initialize the FSMC NAND interface |
| mbed_official | 489:119543c9f674 | 474 | (+) Configure the FSMC clock and associated GPIOs |
| mbed_official | 489:119543c9f674 | 475 | |
| mbed_official | 489:119543c9f674 | 476 | @endverbatim |
| mbed_official | 489:119543c9f674 | 477 | * @{ |
| mbed_official | 489:119543c9f674 | 478 | */ |
| mbed_official | 489:119543c9f674 | 479 | |
| mbed_official | 489:119543c9f674 | 480 | /** |
| mbed_official | 489:119543c9f674 | 481 | * @brief Initializes the FSMC_NAND device according to the specified |
| mbed_official | 489:119543c9f674 | 482 | * control parameters in the FSMC_NAND_HandleTypeDef |
| mbed_official | 489:119543c9f674 | 483 | * @param Device: Pointer to NAND device instance |
| mbed_official | 489:119543c9f674 | 484 | * @param Init: Pointer to NAND Initialization structure |
| mbed_official | 489:119543c9f674 | 485 | * @retval HAL status |
| mbed_official | 489:119543c9f674 | 486 | */ |
| mbed_official | 489:119543c9f674 | 487 | HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDef *Init) |
| mbed_official | 489:119543c9f674 | 488 | { |
| mbed_official | 489:119543c9f674 | 489 | /* Check the parameters */ |
| mbed_official | 489:119543c9f674 | 490 | assert_param(IS_FSMC_NAND_DEVICE(Device)); |
| mbed_official | 489:119543c9f674 | 491 | assert_param(IS_FSMC_NAND_BANK(Init->NandBank)); |
| mbed_official | 489:119543c9f674 | 492 | assert_param(IS_FSMC_WAIT_FEATURE(Init->Waitfeature)); |
| mbed_official | 489:119543c9f674 | 493 | assert_param(IS_FSMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth)); |
| mbed_official | 489:119543c9f674 | 494 | assert_param(IS_FSMC_ECC_STATE(Init->EccComputation)); |
| mbed_official | 489:119543c9f674 | 495 | assert_param(IS_FSMC_ECCPAGE_SIZE(Init->ECCPageSize)); |
| mbed_official | 489:119543c9f674 | 496 | assert_param(IS_FSMC_TCLR_TIME(Init->TCLRSetupTime)); |
| mbed_official | 489:119543c9f674 | 497 | assert_param(IS_FSMC_TAR_TIME(Init->TARSetupTime)); |
| mbed_official | 489:119543c9f674 | 498 | |
| mbed_official | 489:119543c9f674 | 499 | if(Init->NandBank == FSMC_NAND_BANK2) |
| mbed_official | 489:119543c9f674 | 500 | { |
| mbed_official | 489:119543c9f674 | 501 | /* NAND bank 2 registers configuration */ |
| mbed_official | 489:119543c9f674 | 502 | MODIFY_REG(Device->PCR2, PCR_CLEAR_MASK, (Init->Waitfeature |\ |
| mbed_official | 489:119543c9f674 | 503 | FSMC_PCR_MEMORY_TYPE_NAND |\ |
| mbed_official | 489:119543c9f674 | 504 | Init->MemoryDataWidth |\ |
| mbed_official | 489:119543c9f674 | 505 | Init->EccComputation |\ |
| mbed_official | 489:119543c9f674 | 506 | Init->ECCPageSize |\ |
| mbed_official | 489:119543c9f674 | 507 | ((Init->TCLRSetupTime) << POSITION_VAL(FSMC_PCRx_TCLR)) |\ |
| mbed_official | 489:119543c9f674 | 508 | ((Init->TARSetupTime) << POSITION_VAL(FSMC_PCRx_TAR)))); |
| mbed_official | 489:119543c9f674 | 509 | } |
| mbed_official | 489:119543c9f674 | 510 | else |
| mbed_official | 489:119543c9f674 | 511 | { |
| mbed_official | 489:119543c9f674 | 512 | /* NAND bank 3 registers configuration */ |
| mbed_official | 489:119543c9f674 | 513 | MODIFY_REG(Device->PCR3, PCR_CLEAR_MASK, (Init->Waitfeature |\ |
| mbed_official | 489:119543c9f674 | 514 | FSMC_PCR_MEMORY_TYPE_NAND |\ |
| mbed_official | 489:119543c9f674 | 515 | Init->MemoryDataWidth |\ |
| mbed_official | 489:119543c9f674 | 516 | Init->EccComputation |\ |
| mbed_official | 489:119543c9f674 | 517 | Init->ECCPageSize |\ |
| mbed_official | 489:119543c9f674 | 518 | ((Init->TCLRSetupTime) << POSITION_VAL(FSMC_PCRx_TCLR)) |\ |
| mbed_official | 489:119543c9f674 | 519 | ((Init->TARSetupTime) << POSITION_VAL(FSMC_PCRx_TAR)))); |
| mbed_official | 489:119543c9f674 | 520 | } |
| mbed_official | 489:119543c9f674 | 521 | |
| mbed_official | 489:119543c9f674 | 522 | return HAL_OK; |
| mbed_official | 489:119543c9f674 | 523 | |
| mbed_official | 489:119543c9f674 | 524 | } |
| mbed_official | 489:119543c9f674 | 525 | |
| mbed_official | 489:119543c9f674 | 526 | /** |
| mbed_official | 489:119543c9f674 | 527 | * @brief Initializes the FSMC_NAND Common space Timing according to the specified |
| mbed_official | 489:119543c9f674 | 528 | * parameters in the FSMC_NAND_PCC_TimingTypeDef |
| mbed_official | 489:119543c9f674 | 529 | * @param Device: Pointer to NAND device instance |
| mbed_official | 489:119543c9f674 | 530 | * @param Timing: Pointer to NAND timing structure |
| mbed_official | 489:119543c9f674 | 531 | * @param Bank: NAND bank number |
| mbed_official | 489:119543c9f674 | 532 | * @retval HAL status |
| mbed_official | 489:119543c9f674 | 533 | */ |
| mbed_official | 489:119543c9f674 | 534 | HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) |
| mbed_official | 489:119543c9f674 | 535 | { |
| mbed_official | 489:119543c9f674 | 536 | /* Check the parameters */ |
| mbed_official | 489:119543c9f674 | 537 | assert_param(IS_FSMC_NAND_DEVICE(Device)); |
| mbed_official | 489:119543c9f674 | 538 | assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime)); |
| mbed_official | 489:119543c9f674 | 539 | assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime)); |
| mbed_official | 489:119543c9f674 | 540 | assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime)); |
| mbed_official | 489:119543c9f674 | 541 | assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime)); |
| mbed_official | 489:119543c9f674 | 542 | assert_param(IS_FSMC_NAND_BANK(Bank)); |
| mbed_official | 489:119543c9f674 | 543 | |
| mbed_official | 489:119543c9f674 | 544 | if(Bank == FSMC_NAND_BANK2) |
| mbed_official | 489:119543c9f674 | 545 | { |
| mbed_official | 489:119543c9f674 | 546 | /* NAND bank 2 registers configuration */ |
| mbed_official | 489:119543c9f674 | 547 | MODIFY_REG(Device->PMEM2, PMEM_CLEAR_MASK, (Timing->SetupTime |\ |
| mbed_official | 489:119543c9f674 | 548 | ((Timing->WaitSetupTime) << POSITION_VAL(FSMC_PMEMx_MEMWAITx)) |\ |
| mbed_official | 489:119543c9f674 | 549 | ((Timing->HoldSetupTime) << POSITION_VAL(FSMC_PMEMx_MEMHOLDx)) |\ |
| mbed_official | 489:119543c9f674 | 550 | ((Timing->HiZSetupTime) << POSITION_VAL(FSMC_PMEMx_MEMHIZx)))); |
| mbed_official | 489:119543c9f674 | 551 | |
| mbed_official | 489:119543c9f674 | 552 | } |
| mbed_official | 489:119543c9f674 | 553 | else |
| mbed_official | 489:119543c9f674 | 554 | { |
| mbed_official | 489:119543c9f674 | 555 | /* NAND bank 3 registers configuration */ |
| mbed_official | 489:119543c9f674 | 556 | MODIFY_REG(Device->PMEM3, PMEM_CLEAR_MASK, (Timing->SetupTime |\ |
| mbed_official | 489:119543c9f674 | 557 | ((Timing->WaitSetupTime) << POSITION_VAL(FSMC_PMEMx_MEMWAITx)) |\ |
| mbed_official | 489:119543c9f674 | 558 | ((Timing->HoldSetupTime) << POSITION_VAL(FSMC_PMEMx_MEMHOLDx)) |\ |
| mbed_official | 489:119543c9f674 | 559 | ((Timing->HiZSetupTime) << POSITION_VAL(FSMC_PMEMx_MEMHIZx)))); |
| mbed_official | 489:119543c9f674 | 560 | } |
| mbed_official | 489:119543c9f674 | 561 | |
| mbed_official | 489:119543c9f674 | 562 | return HAL_OK; |
| mbed_official | 489:119543c9f674 | 563 | } |
| mbed_official | 489:119543c9f674 | 564 | |
| mbed_official | 489:119543c9f674 | 565 | /** |
| mbed_official | 489:119543c9f674 | 566 | * @brief Initializes the FSMC_NAND Attribute space Timing according to the specified |
| mbed_official | 489:119543c9f674 | 567 | * parameters in the FSMC_NAND_PCC_TimingTypeDef |
| mbed_official | 489:119543c9f674 | 568 | * @param Device: Pointer to NAND device instance |
| mbed_official | 489:119543c9f674 | 569 | * @param Timing: Pointer to NAND timing structure |
| mbed_official | 489:119543c9f674 | 570 | * @param Bank: NAND bank number |
| mbed_official | 489:119543c9f674 | 571 | * @retval HAL status |
| mbed_official | 489:119543c9f674 | 572 | */ |
| mbed_official | 489:119543c9f674 | 573 | HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) |
| mbed_official | 489:119543c9f674 | 574 | { |
| mbed_official | 489:119543c9f674 | 575 | /* Check the parameters */ |
| mbed_official | 489:119543c9f674 | 576 | assert_param(IS_FSMC_NAND_DEVICE(Device)); |
| mbed_official | 489:119543c9f674 | 577 | assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime)); |
| mbed_official | 489:119543c9f674 | 578 | assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime)); |
| mbed_official | 489:119543c9f674 | 579 | assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime)); |
| mbed_official | 489:119543c9f674 | 580 | assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime)); |
| mbed_official | 489:119543c9f674 | 581 | assert_param(IS_FSMC_NAND_BANK(Bank)); |
| mbed_official | 489:119543c9f674 | 582 | |
| mbed_official | 489:119543c9f674 | 583 | if(Bank == FSMC_NAND_BANK2) |
| mbed_official | 489:119543c9f674 | 584 | { |
| mbed_official | 489:119543c9f674 | 585 | /* NAND bank 2 registers configuration */ |
| mbed_official | 489:119543c9f674 | 586 | MODIFY_REG(Device->PATT2, PATT_CLEAR_MASK, (Timing->SetupTime |\ |
| mbed_official | 489:119543c9f674 | 587 | ((Timing->WaitSetupTime) << POSITION_VAL(FSMC_PATTx_ATTWAITx)) |\ |
| mbed_official | 489:119543c9f674 | 588 | ((Timing->HoldSetupTime) << POSITION_VAL(FSMC_PATTx_ATTHOLDx)) |\ |
| mbed_official | 489:119543c9f674 | 589 | ((Timing->HiZSetupTime) << POSITION_VAL(FSMC_PATTx_ATTHIZx)))); |
| mbed_official | 489:119543c9f674 | 590 | } |
| mbed_official | 489:119543c9f674 | 591 | else |
| mbed_official | 489:119543c9f674 | 592 | { |
| mbed_official | 489:119543c9f674 | 593 | /* NAND bank 3 registers configuration */ |
| mbed_official | 489:119543c9f674 | 594 | MODIFY_REG(Device->PATT3, PATT_CLEAR_MASK, (Timing->SetupTime |\ |
| mbed_official | 489:119543c9f674 | 595 | ((Timing->WaitSetupTime) << POSITION_VAL(FSMC_PATTx_ATTWAITx)) |\ |
| mbed_official | 489:119543c9f674 | 596 | ((Timing->HoldSetupTime) << POSITION_VAL(FSMC_PATTx_ATTHOLDx)) |\ |
| mbed_official | 489:119543c9f674 | 597 | ((Timing->HiZSetupTime) << POSITION_VAL(FSMC_PATTx_ATTHIZx)))); |
| mbed_official | 489:119543c9f674 | 598 | } |
| mbed_official | 489:119543c9f674 | 599 | |
| mbed_official | 489:119543c9f674 | 600 | return HAL_OK; |
| mbed_official | 489:119543c9f674 | 601 | } |
| mbed_official | 489:119543c9f674 | 602 | |
| mbed_official | 489:119543c9f674 | 603 | |
| mbed_official | 489:119543c9f674 | 604 | /** |
| mbed_official | 489:119543c9f674 | 605 | * @brief DeInitializes the FSMC_NAND device |
| mbed_official | 489:119543c9f674 | 606 | * @param Device: Pointer to NAND device instance |
| mbed_official | 489:119543c9f674 | 607 | * @param Bank: NAND bank number |
| mbed_official | 489:119543c9f674 | 608 | * @retval HAL status |
| mbed_official | 489:119543c9f674 | 609 | */ |
| mbed_official | 489:119543c9f674 | 610 | HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank) |
| mbed_official | 489:119543c9f674 | 611 | { |
| mbed_official | 489:119543c9f674 | 612 | /* Check the parameters */ |
| mbed_official | 489:119543c9f674 | 613 | assert_param(IS_FSMC_NAND_DEVICE(Device)); |
| mbed_official | 489:119543c9f674 | 614 | assert_param(IS_FSMC_NAND_BANK(Bank)); |
| mbed_official | 489:119543c9f674 | 615 | |
| mbed_official | 489:119543c9f674 | 616 | /* Disable the NAND Bank */ |
| mbed_official | 489:119543c9f674 | 617 | __FSMC_NAND_DISABLE(Device, Bank); |
| mbed_official | 489:119543c9f674 | 618 | |
| mbed_official | 489:119543c9f674 | 619 | /* De-initialize the NAND Bank */ |
| mbed_official | 489:119543c9f674 | 620 | if(Bank == FSMC_NAND_BANK2) |
| mbed_official | 489:119543c9f674 | 621 | { |
| mbed_official | 489:119543c9f674 | 622 | /* Set the FSMC_NAND_BANK2 registers to their reset values */ |
| mbed_official | 489:119543c9f674 | 623 | WRITE_REG(Device->PCR2, 0x00000018); |
| mbed_official | 489:119543c9f674 | 624 | WRITE_REG(Device->SR2, 0x00000040); |
| mbed_official | 489:119543c9f674 | 625 | WRITE_REG(Device->PMEM2, 0xFCFCFCFC); |
| mbed_official | 489:119543c9f674 | 626 | WRITE_REG(Device->PATT2, 0xFCFCFCFC); |
| mbed_official | 489:119543c9f674 | 627 | } |
| mbed_official | 489:119543c9f674 | 628 | /* FSMC_Bank3_NAND */ |
| mbed_official | 489:119543c9f674 | 629 | else |
| mbed_official | 489:119543c9f674 | 630 | { |
| mbed_official | 489:119543c9f674 | 631 | /* Set the FSMC_NAND_BANK3 registers to their reset values */ |
| mbed_official | 489:119543c9f674 | 632 | WRITE_REG(Device->PCR3, 0x00000018); |
| mbed_official | 489:119543c9f674 | 633 | WRITE_REG(Device->SR3, 0x00000040); |
| mbed_official | 489:119543c9f674 | 634 | WRITE_REG(Device->PMEM3, 0xFCFCFCFC); |
| mbed_official | 489:119543c9f674 | 635 | WRITE_REG(Device->PATT3, 0xFCFCFCFC); |
| mbed_official | 489:119543c9f674 | 636 | } |
| mbed_official | 489:119543c9f674 | 637 | |
| mbed_official | 489:119543c9f674 | 638 | return HAL_OK; |
| mbed_official | 489:119543c9f674 | 639 | } |
| mbed_official | 489:119543c9f674 | 640 | |
| mbed_official | 489:119543c9f674 | 641 | /** |
| mbed_official | 489:119543c9f674 | 642 | * @} |
| mbed_official | 489:119543c9f674 | 643 | */ |
| mbed_official | 489:119543c9f674 | 644 | |
| mbed_official | 489:119543c9f674 | 645 | |
| mbed_official | 489:119543c9f674 | 646 | /** @defgroup FSMC_NAND_Exported_Functions_Group2 Peripheral Control functions |
| mbed_official | 489:119543c9f674 | 647 | * @brief management functions |
| mbed_official | 489:119543c9f674 | 648 | * |
| mbed_official | 489:119543c9f674 | 649 | @verbatim |
| mbed_official | 489:119543c9f674 | 650 | ============================================================================== |
| mbed_official | 489:119543c9f674 | 651 | ##### FSMC_NAND Control functions ##### |
| mbed_official | 489:119543c9f674 | 652 | ============================================================================== |
| mbed_official | 489:119543c9f674 | 653 | [..] |
| mbed_official | 489:119543c9f674 | 654 | This subsection provides a set of functions allowing to control dynamically |
| mbed_official | 489:119543c9f674 | 655 | the FSMC NAND interface. |
| mbed_official | 489:119543c9f674 | 656 | |
| mbed_official | 489:119543c9f674 | 657 | @endverbatim |
| mbed_official | 489:119543c9f674 | 658 | * @{ |
| mbed_official | 489:119543c9f674 | 659 | */ |
| mbed_official | 489:119543c9f674 | 660 | |
| mbed_official | 489:119543c9f674 | 661 | |
| mbed_official | 489:119543c9f674 | 662 | /** |
| mbed_official | 489:119543c9f674 | 663 | * @brief Enables dynamically FSMC_NAND ECC feature. |
| mbed_official | 489:119543c9f674 | 664 | * @param Device: Pointer to NAND device instance |
| mbed_official | 489:119543c9f674 | 665 | * @param Bank: NAND bank number |
| mbed_official | 489:119543c9f674 | 666 | * @retval HAL status |
| mbed_official | 489:119543c9f674 | 667 | */ |
| mbed_official | 489:119543c9f674 | 668 | HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank) |
| mbed_official | 489:119543c9f674 | 669 | { |
| mbed_official | 489:119543c9f674 | 670 | /* Check the parameters */ |
| mbed_official | 489:119543c9f674 | 671 | assert_param(IS_FSMC_NAND_DEVICE(Device)); |
| mbed_official | 489:119543c9f674 | 672 | assert_param(IS_FSMC_NAND_BANK(Bank)); |
| mbed_official | 489:119543c9f674 | 673 | |
| mbed_official | 489:119543c9f674 | 674 | /* Enable ECC feature */ |
| mbed_official | 489:119543c9f674 | 675 | if(Bank == FSMC_NAND_BANK2) |
| mbed_official | 489:119543c9f674 | 676 | { |
| mbed_official | 489:119543c9f674 | 677 | SET_BIT(Device->PCR2, FSMC_PCRx_ECCEN); |
| mbed_official | 489:119543c9f674 | 678 | } |
| mbed_official | 489:119543c9f674 | 679 | else |
| mbed_official | 489:119543c9f674 | 680 | { |
| mbed_official | 489:119543c9f674 | 681 | SET_BIT(Device->PCR3, FSMC_PCRx_ECCEN); |
| mbed_official | 489:119543c9f674 | 682 | } |
| mbed_official | 489:119543c9f674 | 683 | |
| mbed_official | 489:119543c9f674 | 684 | return HAL_OK; |
| mbed_official | 489:119543c9f674 | 685 | } |
| mbed_official | 489:119543c9f674 | 686 | |
| mbed_official | 489:119543c9f674 | 687 | |
| mbed_official | 489:119543c9f674 | 688 | /** |
| mbed_official | 489:119543c9f674 | 689 | * @brief Disables dynamically FSMC_NAND ECC feature. |
| mbed_official | 489:119543c9f674 | 690 | * @param Device: Pointer to NAND device instance |
| mbed_official | 489:119543c9f674 | 691 | * @param Bank: NAND bank number |
| mbed_official | 489:119543c9f674 | 692 | * @retval HAL status |
| mbed_official | 489:119543c9f674 | 693 | */ |
| mbed_official | 489:119543c9f674 | 694 | HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank) |
| mbed_official | 489:119543c9f674 | 695 | { |
| mbed_official | 489:119543c9f674 | 696 | /* Check the parameters */ |
| mbed_official | 489:119543c9f674 | 697 | assert_param(IS_FSMC_NAND_DEVICE(Device)); |
| mbed_official | 489:119543c9f674 | 698 | assert_param(IS_FSMC_NAND_BANK(Bank)); |
| mbed_official | 489:119543c9f674 | 699 | |
| mbed_official | 489:119543c9f674 | 700 | /* Disable ECC feature */ |
| mbed_official | 489:119543c9f674 | 701 | if(Bank == FSMC_NAND_BANK2) |
| mbed_official | 489:119543c9f674 | 702 | { |
| mbed_official | 489:119543c9f674 | 703 | CLEAR_BIT(Device->PCR2, FSMC_PCRx_ECCEN); |
| mbed_official | 489:119543c9f674 | 704 | } |
| mbed_official | 489:119543c9f674 | 705 | else |
| mbed_official | 489:119543c9f674 | 706 | { |
| mbed_official | 489:119543c9f674 | 707 | CLEAR_BIT(Device->PCR3, FSMC_PCRx_ECCEN); |
| mbed_official | 489:119543c9f674 | 708 | } |
| mbed_official | 489:119543c9f674 | 709 | |
| mbed_official | 489:119543c9f674 | 710 | return HAL_OK; |
| mbed_official | 489:119543c9f674 | 711 | } |
| mbed_official | 489:119543c9f674 | 712 | |
| mbed_official | 489:119543c9f674 | 713 | /** |
| mbed_official | 489:119543c9f674 | 714 | * @brief Disables dynamically FSMC_NAND ECC feature. |
| mbed_official | 489:119543c9f674 | 715 | * @param Device: Pointer to NAND device instance |
| mbed_official | 489:119543c9f674 | 716 | * @param ECCval: Pointer to ECC value |
| mbed_official | 489:119543c9f674 | 717 | * @param Bank: NAND bank number |
| mbed_official | 489:119543c9f674 | 718 | * @param Timeout: Timeout wait value |
| mbed_official | 489:119543c9f674 | 719 | * @retval HAL status |
| mbed_official | 489:119543c9f674 | 720 | */ |
| mbed_official | 489:119543c9f674 | 721 | HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout) |
| mbed_official | 489:119543c9f674 | 722 | { |
| mbed_official | 489:119543c9f674 | 723 | uint32_t tickstart = 0; |
| mbed_official | 489:119543c9f674 | 724 | |
| mbed_official | 489:119543c9f674 | 725 | /* Check the parameters */ |
| mbed_official | 489:119543c9f674 | 726 | assert_param(IS_FSMC_NAND_DEVICE(Device)); |
| mbed_official | 489:119543c9f674 | 727 | assert_param(IS_FSMC_NAND_BANK(Bank)); |
| mbed_official | 489:119543c9f674 | 728 | |
| mbed_official | 489:119543c9f674 | 729 | /* Get tick */ |
| mbed_official | 489:119543c9f674 | 730 | tickstart = HAL_GetTick(); |
| mbed_official | 489:119543c9f674 | 731 | |
| mbed_official | 489:119543c9f674 | 732 | /* Wait untill FIFO is empty */ |
| mbed_official | 489:119543c9f674 | 733 | while(__FSMC_NAND_GET_FLAG(Device, Bank, FSMC_FLAG_FEMPT) == RESET) |
| mbed_official | 489:119543c9f674 | 734 | { |
| mbed_official | 489:119543c9f674 | 735 | /* Check for the Timeout */ |
| mbed_official | 489:119543c9f674 | 736 | if(Timeout != HAL_MAX_DELAY) |
| mbed_official | 489:119543c9f674 | 737 | { |
| mbed_official | 489:119543c9f674 | 738 | if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) |
| mbed_official | 489:119543c9f674 | 739 | { |
| mbed_official | 489:119543c9f674 | 740 | return HAL_TIMEOUT; |
| mbed_official | 489:119543c9f674 | 741 | } |
| mbed_official | 489:119543c9f674 | 742 | } |
| mbed_official | 489:119543c9f674 | 743 | } |
| mbed_official | 489:119543c9f674 | 744 | |
| mbed_official | 489:119543c9f674 | 745 | if(Bank == FSMC_NAND_BANK2) |
| mbed_official | 489:119543c9f674 | 746 | { |
| mbed_official | 489:119543c9f674 | 747 | /* Get the ECCR2 register value */ |
| mbed_official | 489:119543c9f674 | 748 | *ECCval = (uint32_t)Device->ECCR2; |
| mbed_official | 489:119543c9f674 | 749 | } |
| mbed_official | 489:119543c9f674 | 750 | else |
| mbed_official | 489:119543c9f674 | 751 | { |
| mbed_official | 489:119543c9f674 | 752 | /* Get the ECCR3 register value */ |
| mbed_official | 489:119543c9f674 | 753 | *ECCval = (uint32_t)Device->ECCR3; |
| mbed_official | 489:119543c9f674 | 754 | } |
| mbed_official | 489:119543c9f674 | 755 | |
| mbed_official | 489:119543c9f674 | 756 | return HAL_OK; |
| mbed_official | 489:119543c9f674 | 757 | } |
| mbed_official | 489:119543c9f674 | 758 | |
| mbed_official | 489:119543c9f674 | 759 | /** |
| mbed_official | 489:119543c9f674 | 760 | * @} |
| mbed_official | 489:119543c9f674 | 761 | */ |
| mbed_official | 489:119543c9f674 | 762 | |
| mbed_official | 489:119543c9f674 | 763 | /** |
| mbed_official | 489:119543c9f674 | 764 | * @} |
| mbed_official | 489:119543c9f674 | 765 | */ |
| mbed_official | 489:119543c9f674 | 766 | |
| mbed_official | 489:119543c9f674 | 767 | /** @defgroup FSMC_PCCARD FSMC PCCARD Controller functions |
| mbed_official | 489:119543c9f674 | 768 | * @brief PCCARD Controller functions |
| mbed_official | 489:119543c9f674 | 769 | * |
| mbed_official | 489:119543c9f674 | 770 | @verbatim |
| mbed_official | 489:119543c9f674 | 771 | ============================================================================== |
| mbed_official | 489:119543c9f674 | 772 | ##### How to use PCCARD device driver ##### |
| mbed_official | 489:119543c9f674 | 773 | ============================================================================== |
| mbed_official | 489:119543c9f674 | 774 | [..] |
| mbed_official | 489:119543c9f674 | 775 | This driver contains a set of APIs to interface with the FSMC PCCARD bank in order |
| mbed_official | 489:119543c9f674 | 776 | to run the PCCARD/compact flash external devices. |
| mbed_official | 489:119543c9f674 | 777 | |
| mbed_official | 489:119543c9f674 | 778 | (+) FSMC PCCARD bank reset using the function FSMC_PCCARD_DeInit() |
| mbed_official | 489:119543c9f674 | 779 | (+) FSMC PCCARD bank control configuration using the function FSMC_PCCARD_Init() |
| mbed_official | 489:119543c9f674 | 780 | (+) FSMC PCCARD bank common space timing configuration using the function |
| mbed_official | 489:119543c9f674 | 781 | FSMC_PCCARD_CommonSpace_Timing_Init() |
| mbed_official | 489:119543c9f674 | 782 | (+) FSMC PCCARD bank attribute space timing configuration using the function |
| mbed_official | 489:119543c9f674 | 783 | FSMC_PCCARD_AttributeSpace_Timing_Init() |
| mbed_official | 489:119543c9f674 | 784 | (+) FSMC PCCARD bank IO space timing configuration using the function |
| mbed_official | 489:119543c9f674 | 785 | FSMC_PCCARD_IOSpace_Timing_Init() |
| mbed_official | 489:119543c9f674 | 786 | |
| mbed_official | 489:119543c9f674 | 787 | |
| mbed_official | 489:119543c9f674 | 788 | @endverbatim |
| mbed_official | 489:119543c9f674 | 789 | * @{ |
| mbed_official | 489:119543c9f674 | 790 | */ |
| mbed_official | 489:119543c9f674 | 791 | |
| mbed_official | 489:119543c9f674 | 792 | /** @defgroup FSMC_PCCARD_Exported_Functions_Group1 Initialization and de-initialization functions |
| mbed_official | 489:119543c9f674 | 793 | * @brief Initialization and Configuration functions |
| mbed_official | 489:119543c9f674 | 794 | * |
| mbed_official | 489:119543c9f674 | 795 | @verbatim |
| mbed_official | 489:119543c9f674 | 796 | ============================================================================== |
| mbed_official | 489:119543c9f674 | 797 | ##### Initialization and de_initialization functions ##### |
| mbed_official | 489:119543c9f674 | 798 | ============================================================================== |
| mbed_official | 489:119543c9f674 | 799 | [..] |
| mbed_official | 489:119543c9f674 | 800 | This section provides functions allowing to: |
| mbed_official | 489:119543c9f674 | 801 | (+) Initialize and configure the FSMC PCCARD interface |
| mbed_official | 489:119543c9f674 | 802 | (+) De-initialize the FSMC PCCARD interface |
| mbed_official | 489:119543c9f674 | 803 | (+) Configure the FSMC clock and associated GPIOs |
| mbed_official | 489:119543c9f674 | 804 | |
| mbed_official | 489:119543c9f674 | 805 | @endverbatim |
| mbed_official | 489:119543c9f674 | 806 | * @{ |
| mbed_official | 489:119543c9f674 | 807 | */ |
| mbed_official | 489:119543c9f674 | 808 | |
| mbed_official | 489:119543c9f674 | 809 | /** |
| mbed_official | 489:119543c9f674 | 810 | * @brief Initializes the FSMC_PCCARD device according to the specified |
| mbed_official | 489:119543c9f674 | 811 | * control parameters in the FSMC_PCCARD_HandleTypeDef |
| mbed_official | 489:119543c9f674 | 812 | * @param Device: Pointer to PCCARD device instance |
| mbed_official | 489:119543c9f674 | 813 | * @param Init: Pointer to PCCARD Initialization structure |
| mbed_official | 489:119543c9f674 | 814 | * @retval HAL status |
| mbed_official | 489:119543c9f674 | 815 | */ |
| mbed_official | 489:119543c9f674 | 816 | HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_InitTypeDef *Init) |
| mbed_official | 489:119543c9f674 | 817 | { |
| mbed_official | 489:119543c9f674 | 818 | /* Check the parameters */ |
| mbed_official | 489:119543c9f674 | 819 | assert_param(IS_FSMC_PCCARD_DEVICE(Device)); |
| mbed_official | 489:119543c9f674 | 820 | assert_param(IS_FSMC_WAIT_FEATURE(Init->Waitfeature)); |
| mbed_official | 489:119543c9f674 | 821 | assert_param(IS_FSMC_TCLR_TIME(Init->TCLRSetupTime)); |
| mbed_official | 489:119543c9f674 | 822 | assert_param(IS_FSMC_TAR_TIME(Init->TARSetupTime)); |
| mbed_official | 489:119543c9f674 | 823 | |
| mbed_official | 489:119543c9f674 | 824 | /* Set FSMC_PCCARD device control parameters */ |
| mbed_official | 489:119543c9f674 | 825 | MODIFY_REG(Device->PCR4, \ |
| mbed_official | 489:119543c9f674 | 826 | (FSMC_PCRx_PTYP | FSMC_PCRx_PWAITEN | FSMC_PCRx_PWID | FSMC_PCRx_TCLR | FSMC_PCRx_TAR), \ |
| mbed_official | 489:119543c9f674 | 827 | (FSMC_PCR_MEMORY_TYPE_PCCARD | \ |
| mbed_official | 489:119543c9f674 | 828 | Init->Waitfeature | \ |
| mbed_official | 489:119543c9f674 | 829 | FSMC_NAND_PCC_MEM_BUS_WIDTH_16 | \ |
| mbed_official | 489:119543c9f674 | 830 | (Init->TCLRSetupTime << POSITION_VAL(FSMC_PCRx_TCLR)) | \ |
| mbed_official | 489:119543c9f674 | 831 | (Init->TARSetupTime << POSITION_VAL(FSMC_PCRx_TAR)))); |
| mbed_official | 489:119543c9f674 | 832 | |
| mbed_official | 489:119543c9f674 | 833 | return HAL_OK; |
| mbed_official | 489:119543c9f674 | 834 | |
| mbed_official | 489:119543c9f674 | 835 | } |
| mbed_official | 489:119543c9f674 | 836 | |
| mbed_official | 489:119543c9f674 | 837 | /** |
| mbed_official | 489:119543c9f674 | 838 | * @brief Initializes the FSMC_PCCARD Common space Timing according to the specified |
| mbed_official | 489:119543c9f674 | 839 | * parameters in the FSMC_NAND_PCC_TimingTypeDef |
| mbed_official | 489:119543c9f674 | 840 | * @param Device: Pointer to PCCARD device instance |
| mbed_official | 489:119543c9f674 | 841 | * @param Timing: Pointer to PCCARD timing structure |
| mbed_official | 489:119543c9f674 | 842 | * @retval HAL status |
| mbed_official | 489:119543c9f674 | 843 | */ |
| mbed_official | 489:119543c9f674 | 844 | HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing) |
| mbed_official | 489:119543c9f674 | 845 | { |
| mbed_official | 489:119543c9f674 | 846 | /* Check the parameters */ |
| mbed_official | 489:119543c9f674 | 847 | assert_param(IS_FSMC_PCCARD_DEVICE(Device)); |
| mbed_official | 489:119543c9f674 | 848 | assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime)); |
| mbed_official | 489:119543c9f674 | 849 | assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime)); |
| mbed_official | 489:119543c9f674 | 850 | assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime)); |
| mbed_official | 489:119543c9f674 | 851 | assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime)); |
| mbed_official | 489:119543c9f674 | 852 | |
| mbed_official | 489:119543c9f674 | 853 | /* Set PCCARD timing parameters */ |
| mbed_official | 489:119543c9f674 | 854 | MODIFY_REG(Device->PMEM4, PMEM_CLEAR_MASK, \ |
| mbed_official | 489:119543c9f674 | 855 | (Timing->SetupTime | \ |
| mbed_official | 489:119543c9f674 | 856 | ((Timing->WaitSetupTime) << POSITION_VAL(FSMC_PMEMx_MEMWAITx)) | \ |
| mbed_official | 489:119543c9f674 | 857 | ((Timing->HoldSetupTime) << POSITION_VAL(FSMC_PMEMx_MEMHOLDx)) | \ |
| mbed_official | 489:119543c9f674 | 858 | ((Timing->HiZSetupTime) << POSITION_VAL(FSMC_PMEMx_MEMHIZx)))); |
| mbed_official | 489:119543c9f674 | 859 | |
| mbed_official | 489:119543c9f674 | 860 | return HAL_OK; |
| mbed_official | 489:119543c9f674 | 861 | } |
| mbed_official | 489:119543c9f674 | 862 | |
| mbed_official | 489:119543c9f674 | 863 | /** |
| mbed_official | 489:119543c9f674 | 864 | * @brief Initializes the FSMC_PCCARD Attribute space Timing according to the specified |
| mbed_official | 489:119543c9f674 | 865 | * parameters in the FSMC_NAND_PCC_TimingTypeDef |
| mbed_official | 489:119543c9f674 | 866 | * @param Device: Pointer to PCCARD device instance |
| mbed_official | 489:119543c9f674 | 867 | * @param Timing: Pointer to PCCARD timing structure |
| mbed_official | 489:119543c9f674 | 868 | * @retval HAL status |
| mbed_official | 489:119543c9f674 | 869 | */ |
| mbed_official | 489:119543c9f674 | 870 | HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing) |
| mbed_official | 489:119543c9f674 | 871 | { |
| mbed_official | 489:119543c9f674 | 872 | /* Check the parameters */ |
| mbed_official | 489:119543c9f674 | 873 | assert_param(IS_FSMC_PCCARD_DEVICE(Device)); |
| mbed_official | 489:119543c9f674 | 874 | assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime)); |
| mbed_official | 489:119543c9f674 | 875 | assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime)); |
| mbed_official | 489:119543c9f674 | 876 | assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime)); |
| mbed_official | 489:119543c9f674 | 877 | assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime)); |
| mbed_official | 489:119543c9f674 | 878 | |
| mbed_official | 489:119543c9f674 | 879 | /* Set PCCARD timing parameters */ |
| mbed_official | 489:119543c9f674 | 880 | MODIFY_REG(Device->PATT4, PATT_CLEAR_MASK, \ |
| mbed_official | 489:119543c9f674 | 881 | (Timing->SetupTime | \ |
| mbed_official | 489:119543c9f674 | 882 | ((Timing->WaitSetupTime) << POSITION_VAL(FSMC_PATTx_ATTWAITx)) | \ |
| mbed_official | 489:119543c9f674 | 883 | ((Timing->HoldSetupTime) << POSITION_VAL(FSMC_PATTx_ATTHOLDx)) | \ |
| mbed_official | 489:119543c9f674 | 884 | ((Timing->HiZSetupTime) << POSITION_VAL(FSMC_PATTx_ATTHIZx)))); |
| mbed_official | 489:119543c9f674 | 885 | |
| mbed_official | 489:119543c9f674 | 886 | return HAL_OK; |
| mbed_official | 489:119543c9f674 | 887 | } |
| mbed_official | 489:119543c9f674 | 888 | |
| mbed_official | 489:119543c9f674 | 889 | /** |
| mbed_official | 489:119543c9f674 | 890 | * @brief Initializes the FSMC_PCCARD IO space Timing according to the specified |
| mbed_official | 489:119543c9f674 | 891 | * parameters in the FSMC_NAND_PCC_TimingTypeDef |
| mbed_official | 489:119543c9f674 | 892 | * @param Device: Pointer to PCCARD device instance |
| mbed_official | 489:119543c9f674 | 893 | * @param Timing: Pointer to PCCARD timing structure |
| mbed_official | 489:119543c9f674 | 894 | * @retval HAL status |
| mbed_official | 489:119543c9f674 | 895 | */ |
| mbed_official | 489:119543c9f674 | 896 | HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing) |
| mbed_official | 489:119543c9f674 | 897 | { |
| mbed_official | 489:119543c9f674 | 898 | /* Check the parameters */ |
| mbed_official | 489:119543c9f674 | 899 | assert_param(IS_FSMC_PCCARD_DEVICE(Device)); |
| mbed_official | 489:119543c9f674 | 900 | assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime)); |
| mbed_official | 489:119543c9f674 | 901 | assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime)); |
| mbed_official | 489:119543c9f674 | 902 | assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime)); |
| mbed_official | 489:119543c9f674 | 903 | assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime)); |
| mbed_official | 489:119543c9f674 | 904 | |
| mbed_official | 489:119543c9f674 | 905 | /* Set FSMC_PCCARD device timing parameters */ |
| mbed_official | 489:119543c9f674 | 906 | MODIFY_REG(Device->PIO4, PIO4_CLEAR_MASK, \ |
| mbed_official | 489:119543c9f674 | 907 | (Timing->SetupTime | \ |
| mbed_official | 489:119543c9f674 | 908 | (Timing->WaitSetupTime << POSITION_VAL(FSMC_PIO4_IOWAIT4)) | \ |
| mbed_official | 489:119543c9f674 | 909 | (Timing->HoldSetupTime << POSITION_VAL(FSMC_PIO4_IOHOLD4)) | \ |
| mbed_official | 489:119543c9f674 | 910 | (Timing->HiZSetupTime << POSITION_VAL(FSMC_PIO4_IOHIZ4)))); |
| mbed_official | 489:119543c9f674 | 911 | |
| mbed_official | 489:119543c9f674 | 912 | return HAL_OK; |
| mbed_official | 489:119543c9f674 | 913 | } |
| mbed_official | 489:119543c9f674 | 914 | |
| mbed_official | 489:119543c9f674 | 915 | /** |
| mbed_official | 489:119543c9f674 | 916 | * @brief DeInitializes the FSMC_PCCARD device |
| mbed_official | 489:119543c9f674 | 917 | * @param Device: Pointer to PCCARD device instance |
| mbed_official | 489:119543c9f674 | 918 | * @retval HAL status |
| mbed_official | 489:119543c9f674 | 919 | */ |
| mbed_official | 489:119543c9f674 | 920 | HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device) |
| mbed_official | 489:119543c9f674 | 921 | { |
| mbed_official | 489:119543c9f674 | 922 | /* Check the parameters */ |
| mbed_official | 489:119543c9f674 | 923 | assert_param(IS_FSMC_PCCARD_DEVICE(Device)); |
| mbed_official | 489:119543c9f674 | 924 | |
| mbed_official | 489:119543c9f674 | 925 | /* Disable the FSMC_PCCARD device */ |
| mbed_official | 489:119543c9f674 | 926 | __FSMC_PCCARD_DISABLE(Device); |
| mbed_official | 489:119543c9f674 | 927 | |
| mbed_official | 489:119543c9f674 | 928 | /* De-initialize the FSMC_PCCARD device */ |
| mbed_official | 489:119543c9f674 | 929 | WRITE_REG(Device->PCR4, 0x00000018); |
| mbed_official | 489:119543c9f674 | 930 | WRITE_REG(Device->SR4, 0x00000040); |
| mbed_official | 489:119543c9f674 | 931 | WRITE_REG(Device->PMEM4, 0xFCFCFCFC); |
| mbed_official | 489:119543c9f674 | 932 | WRITE_REG(Device->PATT4, 0xFCFCFCFC); |
| mbed_official | 489:119543c9f674 | 933 | WRITE_REG(Device->PIO4, 0xFCFCFCFC); |
| mbed_official | 489:119543c9f674 | 934 | |
| mbed_official | 489:119543c9f674 | 935 | return HAL_OK; |
| mbed_official | 489:119543c9f674 | 936 | } |
| mbed_official | 489:119543c9f674 | 937 | |
| mbed_official | 489:119543c9f674 | 938 | /** |
| mbed_official | 489:119543c9f674 | 939 | * @} |
| mbed_official | 489:119543c9f674 | 940 | */ |
| mbed_official | 489:119543c9f674 | 941 | |
| mbed_official | 489:119543c9f674 | 942 | /** |
| mbed_official | 489:119543c9f674 | 943 | * @} |
| mbed_official | 489:119543c9f674 | 944 | */ |
| mbed_official | 489:119543c9f674 | 945 | |
| mbed_official | 489:119543c9f674 | 946 | #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */ |
| mbed_official | 489:119543c9f674 | 947 | |
| mbed_official | 489:119543c9f674 | 948 | /** |
| mbed_official | 489:119543c9f674 | 949 | * @} |
| mbed_official | 489:119543c9f674 | 950 | */ |
| mbed_official | 489:119543c9f674 | 951 | |
| mbed_official | 489:119543c9f674 | 952 | /** |
| mbed_official | 489:119543c9f674 | 953 | * @} |
| mbed_official | 489:119543c9f674 | 954 | */ |
| mbed_official | 489:119543c9f674 | 955 | |
| mbed_official | 489:119543c9f674 | 956 | #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG || STM32F100xE */ |
| mbed_official | 489:119543c9f674 | 957 | |
| mbed_official | 489:119543c9f674 | 958 | #endif /* HAL_SRAM_MODULE_ENABLED || HAL_NOR_MODULE_ENABLED || HAL_PCCARD_MODULE_ENABLED || HAL_NAND_MODULE_ENABLED */ |
| mbed_official | 489:119543c9f674 | 959 | |
| mbed_official | 489:119543c9f674 | 960 | /** |
| mbed_official | 489:119543c9f674 | 961 | * @} |
| mbed_official | 489:119543c9f674 | 962 | */ |
| mbed_official | 489:119543c9f674 | 963 | |
| mbed_official | 489:119543c9f674 | 964 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
