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targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_tim.h@581:39197bcd20f2, 2015-07-02 (annotated)

Committer:: mbed_official
Date:: Thu Jul 02 16:30:08 2015 +0100
Revision:: 581:39197bcd20f2
Parent:: 489:119543c9f674

Synchronized with git revision ae2d3cdffe70184eb8736d94f76c45c93f4b7724

Full URL: https://github.com/mbedmicro/mbed/commit/ae2d3cdffe70184eb8736d94f76c45c93f4b7724/

Make it possible to build the core mbed library with yotta

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User	Revision	Line number	New contents of line
mbed_official	489:119543c9f674	1	/**
mbed_official	489:119543c9f674	2	******************************************************************************
mbed_official	489:119543c9f674	3	* @file stm32f1xx_hal_tim.h
mbed_official	489:119543c9f674	4	* @author MCD Application Team
mbed_official	489:119543c9f674	5	* @version V1.0.0
mbed_official	489:119543c9f674	6	* @date 15-December-2014
mbed_official	489:119543c9f674	7	* @brief Header file of TIM HAL module.
mbed_official	489:119543c9f674	8	******************************************************************************
mbed_official	489:119543c9f674	9	* @attention
mbed_official	489:119543c9f674	10	*
mbed_official	489:119543c9f674	11	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
mbed_official	489:119543c9f674	12	*
mbed_official	489:119543c9f674	13	* Redistribution and use in source and binary forms, with or without modification,
mbed_official	489:119543c9f674	14	* are permitted provided that the following conditions are met:
mbed_official	489:119543c9f674	15	* 1. Redistributions of source code must retain the above copyright notice,
mbed_official	489:119543c9f674	16	* this list of conditions and the following disclaimer.
mbed_official	489:119543c9f674	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official	489:119543c9f674	18	* this list of conditions and the following disclaimer in the documentation
mbed_official	489:119543c9f674	19	* and/or other materials provided with the distribution.
mbed_official	489:119543c9f674	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official	489:119543c9f674	21	* may be used to endorse or promote products derived from this software
mbed_official	489:119543c9f674	22	* without specific prior written permission.
mbed_official	489:119543c9f674	23	*
mbed_official	489:119543c9f674	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official	489:119543c9f674	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official	489:119543c9f674	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official	489:119543c9f674	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official	489:119543c9f674	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official	489:119543c9f674	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official	489:119543c9f674	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official	489:119543c9f674	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official	489:119543c9f674	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official	489:119543c9f674	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official	489:119543c9f674	34	*
mbed_official	489:119543c9f674	35	******************************************************************************
mbed_official	489:119543c9f674	36	*/
mbed_official	489:119543c9f674	37
mbed_official	489:119543c9f674	38	/* Define to prevent recursive inclusion -------------------------------------*/
mbed_official	489:119543c9f674	39	#ifndef __STM32F1xx_HAL_TIM_H
mbed_official	489:119543c9f674	40	#define __STM32F1xx_HAL_TIM_H
mbed_official	489:119543c9f674	41
mbed_official	489:119543c9f674	42	#ifdef __cplusplus
mbed_official	489:119543c9f674	43	extern "C" {
mbed_official	489:119543c9f674	44	#endif
mbed_official	489:119543c9f674	45
mbed_official	489:119543c9f674	46	/* Includes ------------------------------------------------------------------*/
mbed_official	489:119543c9f674	47	#include "stm32f1xx_hal_def.h"
mbed_official	489:119543c9f674	48
mbed_official	489:119543c9f674	49	/** @addtogroup STM32F1xx_HAL_Driver
mbed_official	489:119543c9f674	50	* @{
mbed_official	489:119543c9f674	51	*/
mbed_official	489:119543c9f674	52
mbed_official	489:119543c9f674	53	/** @addtogroup TIM
mbed_official	489:119543c9f674	54	* @{
mbed_official	489:119543c9f674	55	*/
mbed_official	489:119543c9f674	56
mbed_official	489:119543c9f674	57	/* Exported types ------------------------------------------------------------*/
mbed_official	489:119543c9f674	58	/** @defgroup TIM_Exported_Types TIM Exported Types
mbed_official	489:119543c9f674	59	* @{
mbed_official	489:119543c9f674	60	*/
mbed_official	489:119543c9f674	61	/**
mbed_official	489:119543c9f674	62	* @brief TIM Time base Configuration Structure definition
mbed_official	489:119543c9f674	63	*/
mbed_official	489:119543c9f674	64	typedef struct
mbed_official	489:119543c9f674	65	{
mbed_official	489:119543c9f674	66	uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
mbed_official	489:119543c9f674	67	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
mbed_official	489:119543c9f674	68
mbed_official	489:119543c9f674	69	uint32_t CounterMode; /*!< Specifies the counter mode.
mbed_official	489:119543c9f674	70	This parameter can be a value of @ref TIM_Counter_Mode */
mbed_official	489:119543c9f674	71
mbed_official	489:119543c9f674	72	uint32_t Period; /*!< Specifies the period value to be loaded into the active
mbed_official	489:119543c9f674	73	Auto-Reload Register at the next update event.
mbed_official	489:119543c9f674	74	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
mbed_official	489:119543c9f674	75
mbed_official	489:119543c9f674	76	uint32_t ClockDivision; /*!< Specifies the clock division.
mbed_official	489:119543c9f674	77	This parameter can be a value of @ref TIM_ClockDivision */
mbed_official	489:119543c9f674	78
mbed_official	489:119543c9f674	79	uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
mbed_official	489:119543c9f674	80	reaches zero, an update event is generated and counting restarts
mbed_official	489:119543c9f674	81	from the RCR value (N).
mbed_official	489:119543c9f674	82	This means in PWM mode that (N+1) corresponds to:
mbed_official	489:119543c9f674	83	- the number of PWM periods in edge-aligned mode
mbed_official	489:119543c9f674	84	- the number of half PWM period in center-aligned mode
mbed_official	489:119543c9f674	85	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
mbed_official	489:119543c9f674	86	@note This parameter is valid only for TIM1 and TIM8. */
mbed_official	489:119543c9f674	87	} TIM_Base_InitTypeDef;
mbed_official	489:119543c9f674	88
mbed_official	489:119543c9f674	89	/**
mbed_official	489:119543c9f674	90	* @brief TIM Output Compare Configuration Structure definition
mbed_official	489:119543c9f674	91	*/
mbed_official	489:119543c9f674	92	typedef struct
mbed_official	489:119543c9f674	93	{
mbed_official	489:119543c9f674	94	uint32_t OCMode; /*!< Specifies the TIM mode.
mbed_official	489:119543c9f674	95	This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
mbed_official	489:119543c9f674	96
mbed_official	489:119543c9f674	97	uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
mbed_official	489:119543c9f674	98	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
mbed_official	489:119543c9f674	99
mbed_official	489:119543c9f674	100	uint32_t OCPolarity; /*!< Specifies the output polarity.
mbed_official	489:119543c9f674	101	This parameter can be a value of @ref TIM_Output_Compare_Polarity */
mbed_official	489:119543c9f674	102
mbed_official	489:119543c9f674	103	uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
mbed_official	489:119543c9f674	104	This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
mbed_official	489:119543c9f674	105	@note This parameter is valid only for TIM1 and TIM8. */
mbed_official	489:119543c9f674	106
mbed_official	489:119543c9f674	107	uint32_t OCFastMode; /*!< Specifies the Fast mode state.
mbed_official	489:119543c9f674	108	This parameter can be a value of @ref TIM_Output_Fast_State
mbed_official	489:119543c9f674	109	@note This parameter is valid only in PWM1 and PWM2 mode. */
mbed_official	489:119543c9f674	110
mbed_official	489:119543c9f674	111
mbed_official	489:119543c9f674	112	uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
mbed_official	489:119543c9f674	113	This parameter can be a value of @ref TIM_Output_Compare_Idle_State
mbed_official	489:119543c9f674	114	@note This parameter is valid only for TIM1 and TIM8. */
mbed_official	489:119543c9f674	115
mbed_official	489:119543c9f674	116	uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
mbed_official	489:119543c9f674	117	This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
mbed_official	489:119543c9f674	118	@note This parameter is valid only for TIM1 and TIM8. */
mbed_official	489:119543c9f674	119	} TIM_OC_InitTypeDef;
mbed_official	489:119543c9f674	120
mbed_official	489:119543c9f674	121	/**
mbed_official	489:119543c9f674	122	* @brief TIM One Pulse Mode Configuration Structure definition
mbed_official	489:119543c9f674	123	*/
mbed_official	489:119543c9f674	124	typedef struct
mbed_official	489:119543c9f674	125	{
mbed_official	489:119543c9f674	126	uint32_t OCMode; /*!< Specifies the TIM mode.
mbed_official	489:119543c9f674	127	This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
mbed_official	489:119543c9f674	128
mbed_official	489:119543c9f674	129	uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
mbed_official	489:119543c9f674	130	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
mbed_official	489:119543c9f674	131
mbed_official	489:119543c9f674	132	uint32_t OCPolarity; /*!< Specifies the output polarity.
mbed_official	489:119543c9f674	133	This parameter can be a value of @ref TIM_Output_Compare_Polarity */
mbed_official	489:119543c9f674	134
mbed_official	489:119543c9f674	135	uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
mbed_official	489:119543c9f674	136	This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
mbed_official	489:119543c9f674	137	@note This parameter is valid only for TIM1 and TIM8. */
mbed_official	489:119543c9f674	138
mbed_official	489:119543c9f674	139	uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
mbed_official	489:119543c9f674	140	This parameter can be a value of @ref TIM_Output_Compare_Idle_State
mbed_official	489:119543c9f674	141	@note This parameter is valid only for TIM1 and TIM8. */
mbed_official	489:119543c9f674	142
mbed_official	489:119543c9f674	143	uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
mbed_official	489:119543c9f674	144	This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
mbed_official	489:119543c9f674	145	@note This parameter is valid only for TIM1 and TIM8. */
mbed_official	489:119543c9f674	146
mbed_official	489:119543c9f674	147	uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
mbed_official	489:119543c9f674	148	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
mbed_official	489:119543c9f674	149
mbed_official	489:119543c9f674	150	uint32_t ICSelection; /*!< Specifies the input.
mbed_official	489:119543c9f674	151	This parameter can be a value of @ref TIM_Input_Capture_Selection */
mbed_official	489:119543c9f674	152
mbed_official	489:119543c9f674	153	uint32_t ICFilter; /*!< Specifies the input capture filter.
mbed_official	489:119543c9f674	154	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
mbed_official	489:119543c9f674	155	} TIM_OnePulse_InitTypeDef;
mbed_official	489:119543c9f674	156
mbed_official	489:119543c9f674	157
mbed_official	489:119543c9f674	158	/**
mbed_official	489:119543c9f674	159	* @brief TIM Input Capture Configuration Structure definition
mbed_official	489:119543c9f674	160	*/
mbed_official	489:119543c9f674	161	typedef struct
mbed_official	489:119543c9f674	162	{
mbed_official	489:119543c9f674	163	uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
mbed_official	489:119543c9f674	164	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
mbed_official	489:119543c9f674	165
mbed_official	489:119543c9f674	166	uint32_t ICSelection; /*!< Specifies the input.
mbed_official	489:119543c9f674	167	This parameter can be a value of @ref TIM_Input_Capture_Selection */
mbed_official	489:119543c9f674	168
mbed_official	489:119543c9f674	169	uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
mbed_official	489:119543c9f674	170	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
mbed_official	489:119543c9f674	171
mbed_official	489:119543c9f674	172	uint32_t ICFilter; /*!< Specifies the input capture filter.
mbed_official	489:119543c9f674	173	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
mbed_official	489:119543c9f674	174	} TIM_IC_InitTypeDef;
mbed_official	489:119543c9f674	175
mbed_official	489:119543c9f674	176	/**
mbed_official	489:119543c9f674	177	* @brief TIM Encoder Configuration Structure definition
mbed_official	489:119543c9f674	178	*/
mbed_official	489:119543c9f674	179	typedef struct
mbed_official	489:119543c9f674	180	{
mbed_official	489:119543c9f674	181	uint32_t EncoderMode; /*!< Specifies the active edge of the input signal.
mbed_official	489:119543c9f674	182	This parameter can be a value of @ref TIM_Encoder_Mode */
mbed_official	489:119543c9f674	183
mbed_official	489:119543c9f674	184	uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
mbed_official	489:119543c9f674	185	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
mbed_official	489:119543c9f674	186
mbed_official	489:119543c9f674	187	uint32_t IC1Selection; /*!< Specifies the input.
mbed_official	489:119543c9f674	188	This parameter can be a value of @ref TIM_Input_Capture_Selection */
mbed_official	489:119543c9f674	189
mbed_official	489:119543c9f674	190	uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
mbed_official	489:119543c9f674	191	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
mbed_official	489:119543c9f674	192
mbed_official	489:119543c9f674	193	uint32_t IC1Filter; /*!< Specifies the input capture filter.
mbed_official	489:119543c9f674	194	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
mbed_official	489:119543c9f674	195
mbed_official	489:119543c9f674	196	uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.
mbed_official	489:119543c9f674	197	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
mbed_official	489:119543c9f674	198
mbed_official	489:119543c9f674	199	uint32_t IC2Selection; /*!< Specifies the input.
mbed_official	489:119543c9f674	200	This parameter can be a value of @ref TIM_Input_Capture_Selection */
mbed_official	489:119543c9f674	201
mbed_official	489:119543c9f674	202	uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler.
mbed_official	489:119543c9f674	203	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
mbed_official	489:119543c9f674	204
mbed_official	489:119543c9f674	205	uint32_t IC2Filter; /*!< Specifies the input capture filter.
mbed_official	489:119543c9f674	206	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
mbed_official	489:119543c9f674	207	} TIM_Encoder_InitTypeDef;
mbed_official	489:119543c9f674	208
mbed_official	489:119543c9f674	209
mbed_official	489:119543c9f674	210	/**
mbed_official	489:119543c9f674	211	* @brief TIM Clock Configuration Handle Structure definition
mbed_official	489:119543c9f674	212	*/
mbed_official	489:119543c9f674	213	typedef struct
mbed_official	489:119543c9f674	214	{
mbed_official	489:119543c9f674	215	uint32_t ClockSource; /*!< TIM clock sources
mbed_official	489:119543c9f674	216	This parameter can be a value of @ref TIM_Clock_Source */
mbed_official	489:119543c9f674	217	uint32_t ClockPolarity; /*!< TIM clock polarity
mbed_official	489:119543c9f674	218	This parameter can be a value of @ref TIM_Clock_Polarity */
mbed_official	489:119543c9f674	219	uint32_t ClockPrescaler; /*!< TIM clock prescaler
mbed_official	489:119543c9f674	220	This parameter can be a value of @ref TIM_Clock_Prescaler */
mbed_official	489:119543c9f674	221	uint32_t ClockFilter; /*!< TIM clock filter
mbed_official	489:119543c9f674	222	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
mbed_official	489:119543c9f674	223	}TIM_ClockConfigTypeDef;
mbed_official	489:119543c9f674	224
mbed_official	489:119543c9f674	225	/**
mbed_official	489:119543c9f674	226	* @brief TIM Clear Input Configuration Handle Structure definition
mbed_official	489:119543c9f674	227	*/
mbed_official	489:119543c9f674	228	typedef struct
mbed_official	489:119543c9f674	229	{
mbed_official	489:119543c9f674	230	uint32_t ClearInputState; /*!< TIM clear Input state
mbed_official	489:119543c9f674	231	This parameter can be ENABLE or DISABLE */
mbed_official	489:119543c9f674	232	uint32_t ClearInputSource; /*!< TIM clear Input sources
mbed_official	489:119543c9f674	233	This parameter can be a value of @ref TIM_ClearInput_Source */
mbed_official	489:119543c9f674	234	uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity
mbed_official	489:119543c9f674	235	This parameter can be a value of @ref TIM_ClearInput_Polarity */
mbed_official	489:119543c9f674	236	uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler
mbed_official	489:119543c9f674	237	This parameter can be a value of @ref TIM_ClearInput_Prescaler */
mbed_official	489:119543c9f674	238	uint32_t ClearInputFilter; /*!< TIM Clear Input filter
mbed_official	489:119543c9f674	239	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
mbed_official	489:119543c9f674	240	}TIM_ClearInputConfigTypeDef;
mbed_official	489:119543c9f674	241
mbed_official	489:119543c9f674	242	/**
mbed_official	489:119543c9f674	243	* @brief TIM Slave configuration Structure definition
mbed_official	489:119543c9f674	244	*/
mbed_official	489:119543c9f674	245	typedef struct {
mbed_official	489:119543c9f674	246	uint32_t SlaveMode; /*!< Slave mode selection
mbed_official	489:119543c9f674	247	This parameter can be a value of @ref TIM_Slave_Mode */
mbed_official	489:119543c9f674	248	uint32_t InputTrigger; /*!< Input Trigger source
mbed_official	489:119543c9f674	249	This parameter can be a value of @ref TIM_Trigger_Selection */
mbed_official	489:119543c9f674	250	uint32_t TriggerPolarity; /*!< Input Trigger polarity
mbed_official	489:119543c9f674	251	This parameter can be a value of @ref TIM_Trigger_Polarity */
mbed_official	489:119543c9f674	252	uint32_t TriggerPrescaler; /*!< Input trigger prescaler
mbed_official	489:119543c9f674	253	This parameter can be a value of @ref TIM_Trigger_Prescaler */
mbed_official	489:119543c9f674	254	uint32_t TriggerFilter; /*!< Input trigger filter
mbed_official	489:119543c9f674	255	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
mbed_official	489:119543c9f674	256
mbed_official	489:119543c9f674	257	}TIM_SlaveConfigTypeDef;
mbed_official	489:119543c9f674	258
mbed_official	489:119543c9f674	259	/**
mbed_official	489:119543c9f674	260	* @brief HAL State structures definition
mbed_official	489:119543c9f674	261	*/
mbed_official	489:119543c9f674	262	typedef enum
mbed_official	489:119543c9f674	263	{
mbed_official	489:119543c9f674	264	HAL_TIM_STATE_RESET = 0x00, /!< Peripheral not yet initialized or disabled /
mbed_official	489:119543c9f674	265	HAL_TIM_STATE_READY = 0x01, /!< Peripheral Initialized and ready for use /
mbed_official	489:119543c9f674	266	HAL_TIM_STATE_BUSY = 0x02, /!< An internal process is ongoing /
mbed_official	489:119543c9f674	267	HAL_TIM_STATE_TIMEOUT = 0x03, /!< Timeout state /
mbed_official	489:119543c9f674	268	HAL_TIM_STATE_ERROR = 0x04 /!< Reception process is ongoing /
mbed_official	489:119543c9f674	269	}HAL_TIM_StateTypeDef;
mbed_official	489:119543c9f674	270
mbed_official	489:119543c9f674	271	/**
mbed_official	489:119543c9f674	272	* @brief HAL Active channel structures definition
mbed_official	489:119543c9f674	273	*/
mbed_official	489:119543c9f674	274	typedef enum
mbed_official	489:119543c9f674	275	{
mbed_official	489:119543c9f674	276	HAL_TIM_ACTIVE_CHANNEL_1 = 0x01, /!< The active channel is 1 /
mbed_official	489:119543c9f674	277	HAL_TIM_ACTIVE_CHANNEL_2 = 0x02, /!< The active channel is 2 /
mbed_official	489:119543c9f674	278	HAL_TIM_ACTIVE_CHANNEL_3 = 0x04, /!< The active channel is 3 /
mbed_official	489:119543c9f674	279	HAL_TIM_ACTIVE_CHANNEL_4 = 0x08, /!< The active channel is 4 /
mbed_official	489:119543c9f674	280	HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00 /!< All active channels cleared /
mbed_official	489:119543c9f674	281	}HAL_TIM_ActiveChannel;
mbed_official	489:119543c9f674	282
mbed_official	489:119543c9f674	283	/**
mbed_official	489:119543c9f674	284	* @brief TIM Time Base Handle Structure definition
mbed_official	489:119543c9f674	285	*/
mbed_official	489:119543c9f674	286	typedef struct
mbed_official	489:119543c9f674	287	{
mbed_official	489:119543c9f674	288	TIM_TypeDef Instance; /!< Register base address */
mbed_official	489:119543c9f674	289	TIM_Base_InitTypeDef Init; /!< TIM Time Base required parameters /
mbed_official	489:119543c9f674	290	HAL_TIM_ActiveChannel Channel; /!< Active channel /
mbed_official	489:119543c9f674	291	DMA_HandleTypeDef hdma[7]; /!< DMA Handlers array
mbed_official	489:119543c9f674	292	This array is accessed by a @ref TIM_DMA_Handle_index */
mbed_official	489:119543c9f674	293	HAL_LockTypeDef Lock; /!< Locking object /
mbed_official	489:119543c9f674	294	__IO HAL_TIM_StateTypeDef State; /!< TIM operation state /
mbed_official	489:119543c9f674	295	}TIM_HandleTypeDef;
mbed_official	489:119543c9f674	296
mbed_official	489:119543c9f674	297	/**
mbed_official	489:119543c9f674	298	* @}
mbed_official	489:119543c9f674	299	*/
mbed_official	489:119543c9f674	300
mbed_official	489:119543c9f674	301	/* Exported constants --------------------------------------------------------*/
mbed_official	489:119543c9f674	302	/** @defgroup TIM_Exported_Constants TIM Exported Constants
mbed_official	489:119543c9f674	303	* @{
mbed_official	489:119543c9f674	304	*/
mbed_official	489:119543c9f674	305
mbed_official	489:119543c9f674	306	/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel Polarity
mbed_official	489:119543c9f674	307	* @{
mbed_official	489:119543c9f674	308	*/
mbed_official	489:119543c9f674	309	#define TIM_INPUTCHANNELPOLARITY_RISING ((uint32_t)0x00000000) /!< Polarity for TIx source /
mbed_official	489:119543c9f674	310	#define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P) /!< Polarity for TIx source /
mbed_official	489:119543c9f674	311	#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P \| TIM_CCER_CC1NP) /!< Polarity for TIx source /
mbed_official	489:119543c9f674	312	/**
mbed_official	489:119543c9f674	313	* @}
mbed_official	489:119543c9f674	314	*/
mbed_official	489:119543c9f674	315
mbed_official	489:119543c9f674	316	/** @defgroup TIM_ETR_Polarity TIM ETR Polarity
mbed_official	489:119543c9f674	317	* @{
mbed_official	489:119543c9f674	318	*/
mbed_official	489:119543c9f674	319	#define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /!< Polarity for ETR source /
mbed_official	489:119543c9f674	320	#define TIM_ETRPOLARITY_NONINVERTED ((uint32_t)0x0000) /!< Polarity for ETR source /
mbed_official	489:119543c9f674	321	/**
mbed_official	489:119543c9f674	322	* @}
mbed_official	489:119543c9f674	323	*/
mbed_official	489:119543c9f674	324
mbed_official	489:119543c9f674	325	/** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler
mbed_official	489:119543c9f674	326	* @{
mbed_official	489:119543c9f674	327	*/
mbed_official	489:119543c9f674	328	#define TIM_ETRPRESCALER_DIV1 ((uint32_t)0x0000) /!< No prescaler is used /
mbed_official	489:119543c9f674	329	#define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /!< ETR input source is divided by 2 /
mbed_official	489:119543c9f674	330	#define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /!< ETR input source is divided by 4 /
mbed_official	489:119543c9f674	331	#define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS) /!< ETR input source is divided by 8 /
mbed_official	489:119543c9f674	332	/**
mbed_official	489:119543c9f674	333	* @}
mbed_official	489:119543c9f674	334	*/
mbed_official	489:119543c9f674	335
mbed_official	489:119543c9f674	336	/** @defgroup TIM_Counter_Mode TIM Counter Mode
mbed_official	489:119543c9f674	337	* @{
mbed_official	489:119543c9f674	338	*/
mbed_official	489:119543c9f674	339	#define TIM_COUNTERMODE_UP ((uint32_t)0x0000)
mbed_official	489:119543c9f674	340	#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR
mbed_official	489:119543c9f674	341	#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0
mbed_official	489:119543c9f674	342	#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1
mbed_official	489:119543c9f674	343	#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS
mbed_official	489:119543c9f674	344	/**
mbed_official	489:119543c9f674	345	* @}
mbed_official	489:119543c9f674	346	*/
mbed_official	489:119543c9f674	347
mbed_official	489:119543c9f674	348	/** @defgroup TIM_ClockDivision TIM ClockDivision
mbed_official	489:119543c9f674	349	* @{
mbed_official	489:119543c9f674	350	*/
mbed_official	489:119543c9f674	351	#define TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x0000)
mbed_official	489:119543c9f674	352	#define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0)
mbed_official	489:119543c9f674	353	#define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1)
mbed_official	489:119543c9f674	354	/**
mbed_official	489:119543c9f674	355	* @}
mbed_official	489:119543c9f674	356	*/
mbed_official	489:119543c9f674	357
mbed_official	489:119543c9f674	358	/** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM modes
mbed_official	489:119543c9f674	359	* @{
mbed_official	489:119543c9f674	360	*/
mbed_official	489:119543c9f674	361	#define TIM_OCMODE_TIMING ((uint32_t)0x0000)
mbed_official	489:119543c9f674	362	#define TIM_OCMODE_ACTIVE (TIM_CCMR1_OC1M_0)
mbed_official	489:119543c9f674	363	#define TIM_OCMODE_INACTIVE (TIM_CCMR1_OC1M_1)
mbed_official	489:119543c9f674	364	#define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_0 \| TIM_CCMR1_OC1M_1)
mbed_official	489:119543c9f674	365	#define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_2)
mbed_official	489:119543c9f674	366	#define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M)
mbed_official	489:119543c9f674	367	#define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_0 \| TIM_CCMR1_OC1M_2)
mbed_official	489:119543c9f674	368	#define TIM_OCMODE_FORCED_INACTIVE (TIM_CCMR1_OC1M_2)
mbed_official	489:119543c9f674	369	/**
mbed_official	489:119543c9f674	370	* @}
mbed_official	489:119543c9f674	371	*/
mbed_official	489:119543c9f674	372
mbed_official	489:119543c9f674	373	/** @defgroup TIM_Output_Compare_State TIM Output Compare State
mbed_official	489:119543c9f674	374	* @{
mbed_official	489:119543c9f674	375	*/
mbed_official	489:119543c9f674	376	#define TIM_OUTPUTSTATE_DISABLE ((uint32_t)0x0000)
mbed_official	489:119543c9f674	377	#define TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E)
mbed_official	489:119543c9f674	378	/**
mbed_official	489:119543c9f674	379	* @}
mbed_official	489:119543c9f674	380	*/
mbed_official	489:119543c9f674	381
mbed_official	489:119543c9f674	382	/** @defgroup TIM_Output_Fast_State TIM Output Fast State
mbed_official	489:119543c9f674	383	* @{
mbed_official	489:119543c9f674	384	*/
mbed_official	489:119543c9f674	385	#define TIM_OCFAST_DISABLE ((uint32_t)0x0000)
mbed_official	489:119543c9f674	386	#define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE)
mbed_official	489:119543c9f674	387	/**
mbed_official	489:119543c9f674	388	* @}
mbed_official	489:119543c9f674	389	*/
mbed_official	489:119543c9f674	390
mbed_official	489:119543c9f674	391	/** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State
mbed_official	489:119543c9f674	392	* @{
mbed_official	489:119543c9f674	393	*/
mbed_official	489:119543c9f674	394	#define TIM_OUTPUTNSTATE_DISABLE ((uint32_t)0x0000)
mbed_official	489:119543c9f674	395	#define TIM_OUTPUTNSTATE_ENABLE (TIM_CCER_CC1NE)
mbed_official	489:119543c9f674	396	/**
mbed_official	489:119543c9f674	397	* @}
mbed_official	489:119543c9f674	398	*/
mbed_official	489:119543c9f674	399
mbed_official	489:119543c9f674	400	/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
mbed_official	489:119543c9f674	401	* @{
mbed_official	489:119543c9f674	402	*/
mbed_official	489:119543c9f674	403	#define TIM_OCPOLARITY_HIGH ((uint32_t)0x0000)
mbed_official	489:119543c9f674	404	#define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P)
mbed_official	489:119543c9f674	405	/**
mbed_official	489:119543c9f674	406	* @}
mbed_official	489:119543c9f674	407	*/
mbed_official	489:119543c9f674	408
mbed_official	489:119543c9f674	409	/** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity
mbed_official	489:119543c9f674	410	* @{
mbed_official	489:119543c9f674	411	*/
mbed_official	489:119543c9f674	412	#define TIM_OCNPOLARITY_HIGH ((uint32_t)0x0000)
mbed_official	489:119543c9f674	413	#define TIM_OCNPOLARITY_LOW (TIM_CCER_CC1NP)
mbed_official	489:119543c9f674	414	/**
mbed_official	489:119543c9f674	415	* @}
mbed_official	489:119543c9f674	416	*/
mbed_official	489:119543c9f674	417
mbed_official	489:119543c9f674	418	/** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State
mbed_official	489:119543c9f674	419	* @{
mbed_official	489:119543c9f674	420	*/
mbed_official	489:119543c9f674	421	#define TIM_OCIDLESTATE_SET (TIM_CR2_OIS1)
mbed_official	489:119543c9f674	422	#define TIM_OCIDLESTATE_RESET ((uint32_t)0x0000)
mbed_official	489:119543c9f674	423	/**
mbed_official	489:119543c9f674	424	* @}
mbed_official	489:119543c9f674	425	*/
mbed_official	489:119543c9f674	426
mbed_official	489:119543c9f674	427	/** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State
mbed_official	489:119543c9f674	428	* @{
mbed_official	489:119543c9f674	429	*/
mbed_official	489:119543c9f674	430	#define TIM_OCNIDLESTATE_SET (TIM_CR2_OIS1N)
mbed_official	489:119543c9f674	431	#define TIM_OCNIDLESTATE_RESET ((uint32_t)0x0000)
mbed_official	489:119543c9f674	432	/**
mbed_official	489:119543c9f674	433	* @}
mbed_official	489:119543c9f674	434	*/
mbed_official	489:119543c9f674	435
mbed_official	489:119543c9f674	436	/** @defgroup TIM_Channel TIM Channel
mbed_official	489:119543c9f674	437	* @{
mbed_official	489:119543c9f674	438	*/
mbed_official	489:119543c9f674	439	#define TIM_CHANNEL_1 ((uint32_t)0x0000)
mbed_official	489:119543c9f674	440	#define TIM_CHANNEL_2 ((uint32_t)0x0004)
mbed_official	489:119543c9f674	441	#define TIM_CHANNEL_3 ((uint32_t)0x0008)
mbed_official	489:119543c9f674	442	#define TIM_CHANNEL_4 ((uint32_t)0x000C)
mbed_official	489:119543c9f674	443	#define TIM_CHANNEL_ALL ((uint32_t)0x0018)
mbed_official	489:119543c9f674	444	/**
mbed_official	489:119543c9f674	445	* @}
mbed_official	489:119543c9f674	446	*/
mbed_official	489:119543c9f674	447
mbed_official	489:119543c9f674	448	/** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity
mbed_official	489:119543c9f674	449	* @{
mbed_official	489:119543c9f674	450	*/
mbed_official	489:119543c9f674	451	#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
mbed_official	489:119543c9f674	452	#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
mbed_official	489:119543c9f674	453	#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
mbed_official	489:119543c9f674	454	/**
mbed_official	489:119543c9f674	455	* @}
mbed_official	489:119543c9f674	456	*/
mbed_official	489:119543c9f674	457
mbed_official	489:119543c9f674	458	/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
mbed_official	489:119543c9f674	459	* @{
mbed_official	489:119543c9f674	460	*/
mbed_official	489:119543c9f674	461	#define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1, 2, 3 or 4 is selected to be
mbed_official	489:119543c9f674	462	connected to IC1, IC2, IC3 or IC4, respectively */
mbed_official	489:119543c9f674	463	#define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1) /*!< TIM Input 1, 2, 3 or 4 is selected to be
mbed_official	489:119543c9f674	464	connected to IC2, IC1, IC4 or IC3, respectively */
mbed_official	489:119543c9f674	465	#define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC /
mbed_official	489:119543c9f674	466	/**
mbed_official	489:119543c9f674	467	* @}
mbed_official	489:119543c9f674	468	*/
mbed_official	489:119543c9f674	469
mbed_official	489:119543c9f674	470	/** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
mbed_official	489:119543c9f674	471	* @{
mbed_official	489:119543c9f674	472	*/
mbed_official	489:119543c9f674	473	#define TIM_ICPSC_DIV1 ((uint32_t)0x0000) /!< Capture performed each time an edge is detected on the capture input /
mbed_official	489:119543c9f674	474	#define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /!< Capture performed once every 2 events /
mbed_official	489:119543c9f674	475	#define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /!< Capture performed once every 4 events /
mbed_official	489:119543c9f674	476	#define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /!< Capture performed once every 8 events /
mbed_official	489:119543c9f674	477	/**
mbed_official	489:119543c9f674	478	* @}
mbed_official	489:119543c9f674	479	*/
mbed_official	489:119543c9f674	480
mbed_official	489:119543c9f674	481	/** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode
mbed_official	489:119543c9f674	482	* @{
mbed_official	489:119543c9f674	483	*/
mbed_official	489:119543c9f674	484	#define TIM_OPMODE_SINGLE (TIM_CR1_OPM)
mbed_official	489:119543c9f674	485	#define TIM_OPMODE_REPETITIVE ((uint32_t)0x0000)
mbed_official	489:119543c9f674	486	/**
mbed_official	489:119543c9f674	487	* @}
mbed_official	489:119543c9f674	488	*/
mbed_official	489:119543c9f674	489
mbed_official	489:119543c9f674	490	/** @defgroup TIM_Encoder_Mode TIM Encoder Mode
mbed_official	489:119543c9f674	491	* @{
mbed_official	489:119543c9f674	492	*/
mbed_official	489:119543c9f674	493	#define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0)
mbed_official	489:119543c9f674	494	#define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1)
mbed_official	489:119543c9f674	495	#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 \| TIM_SMCR_SMS_0)
mbed_official	489:119543c9f674	496	/**
mbed_official	489:119543c9f674	497	* @}
mbed_official	489:119543c9f674	498	*/
mbed_official	489:119543c9f674	499
mbed_official	489:119543c9f674	500	/** @defgroup TIM_Interrupt_definition TIM Interrupt Definition
mbed_official	489:119543c9f674	501	* @{
mbed_official	489:119543c9f674	502	*/
mbed_official	489:119543c9f674	503	#define TIM_IT_UPDATE (TIM_DIER_UIE)
mbed_official	489:119543c9f674	504	#define TIM_IT_CC1 (TIM_DIER_CC1IE)
mbed_official	489:119543c9f674	505	#define TIM_IT_CC2 (TIM_DIER_CC2IE)
mbed_official	489:119543c9f674	506	#define TIM_IT_CC3 (TIM_DIER_CC3IE)
mbed_official	489:119543c9f674	507	#define TIM_IT_CC4 (TIM_DIER_CC4IE)
mbed_official	489:119543c9f674	508	#define TIM_IT_COM (TIM_DIER_COMIE)
mbed_official	489:119543c9f674	509	#define TIM_IT_TRIGGER (TIM_DIER_TIE)
mbed_official	489:119543c9f674	510	#define TIM_IT_BREAK (TIM_DIER_BIE)
mbed_official	489:119543c9f674	511	/**
mbed_official	489:119543c9f674	512	* @}
mbed_official	489:119543c9f674	513	*/
mbed_official	489:119543c9f674	514
mbed_official	489:119543c9f674	515	/** @defgroup TIM_Commutation_Source TIM Commutation Source
mbed_official	489:119543c9f674	516	* @{
mbed_official	489:119543c9f674	517	*/
mbed_official	489:119543c9f674	518	#define TIM_COMMUTATION_TRGI (TIM_CR2_CCUS)
mbed_official	489:119543c9f674	519	#define TIM_COMMUTATION_SOFTWARE ((uint32_t)0x0000)
mbed_official	489:119543c9f674	520
mbed_official	489:119543c9f674	521	/**
mbed_official	489:119543c9f674	522	* @}
mbed_official	489:119543c9f674	523	*/
mbed_official	489:119543c9f674	524
mbed_official	489:119543c9f674	525	/** @defgroup TIM_DMA_sources TIM DMA Sources
mbed_official	489:119543c9f674	526	* @{
mbed_official	489:119543c9f674	527	*/
mbed_official	489:119543c9f674	528	#define TIM_DMA_UPDATE (TIM_DIER_UDE)
mbed_official	489:119543c9f674	529	#define TIM_DMA_CC1 (TIM_DIER_CC1DE)
mbed_official	489:119543c9f674	530	#define TIM_DMA_CC2 (TIM_DIER_CC2DE)
mbed_official	489:119543c9f674	531	#define TIM_DMA_CC3 (TIM_DIER_CC3DE)
mbed_official	489:119543c9f674	532	#define TIM_DMA_CC4 (TIM_DIER_CC4DE)
mbed_official	489:119543c9f674	533	#define TIM_DMA_COM (TIM_DIER_COMDE)
mbed_official	489:119543c9f674	534	#define TIM_DMA_TRIGGER (TIM_DIER_TDE)
mbed_official	489:119543c9f674	535	/**
mbed_official	489:119543c9f674	536	* @}
mbed_official	489:119543c9f674	537	*/
mbed_official	489:119543c9f674	538
mbed_official	489:119543c9f674	539	/** @defgroup TIM_Event_Source TIM Event Source
mbed_official	489:119543c9f674	540	* @{
mbed_official	489:119543c9f674	541	*/
mbed_official	489:119543c9f674	542	#define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG
mbed_official	489:119543c9f674	543	#define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G
mbed_official	489:119543c9f674	544	#define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G
mbed_official	489:119543c9f674	545	#define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G
mbed_official	489:119543c9f674	546	#define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G
mbed_official	489:119543c9f674	547	#define TIM_EVENTSOURCE_COM TIM_EGR_COMG
mbed_official	489:119543c9f674	548	#define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG
mbed_official	489:119543c9f674	549	#define TIM_EVENTSOURCE_BREAK TIM_EGR_BG
mbed_official	489:119543c9f674	550	/**
mbed_official	489:119543c9f674	551	* @}
mbed_official	489:119543c9f674	552	*/
mbed_official	489:119543c9f674	553
mbed_official	489:119543c9f674	554	/** @defgroup TIM_Flag_definition TIM Flag Definition
mbed_official	489:119543c9f674	555	* @{
mbed_official	489:119543c9f674	556	*/
mbed_official	489:119543c9f674	557	#define TIM_FLAG_UPDATE (TIM_SR_UIF)
mbed_official	489:119543c9f674	558	#define TIM_FLAG_CC1 (TIM_SR_CC1IF)
mbed_official	489:119543c9f674	559	#define TIM_FLAG_CC2 (TIM_SR_CC2IF)
mbed_official	489:119543c9f674	560	#define TIM_FLAG_CC3 (TIM_SR_CC3IF)
mbed_official	489:119543c9f674	561	#define TIM_FLAG_CC4 (TIM_SR_CC4IF)
mbed_official	489:119543c9f674	562	#define TIM_FLAG_COM (TIM_SR_COMIF)
mbed_official	489:119543c9f674	563	#define TIM_FLAG_TRIGGER (TIM_SR_TIF)
mbed_official	489:119543c9f674	564	#define TIM_FLAG_BREAK (TIM_SR_BIF)
mbed_official	489:119543c9f674	565	#define TIM_FLAG_CC1OF (TIM_SR_CC1OF)
mbed_official	489:119543c9f674	566	#define TIM_FLAG_CC2OF (TIM_SR_CC2OF)
mbed_official	489:119543c9f674	567	#define TIM_FLAG_CC3OF (TIM_SR_CC3OF)
mbed_official	489:119543c9f674	568	#define TIM_FLAG_CC4OF (TIM_SR_CC4OF)
mbed_official	489:119543c9f674	569	/**
mbed_official	489:119543c9f674	570	* @}
mbed_official	489:119543c9f674	571	*/
mbed_official	489:119543c9f674	572
mbed_official	489:119543c9f674	573	/** @defgroup TIM_Clock_Source TIM Clock Source
mbed_official	489:119543c9f674	574	* @{
mbed_official	489:119543c9f674	575	*/
mbed_official	489:119543c9f674	576	#define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1)
mbed_official	489:119543c9f674	577	#define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0)
mbed_official	489:119543c9f674	578	#define TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x0000)
mbed_official	489:119543c9f674	579	#define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0)
mbed_official	489:119543c9f674	580	#define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1)
mbed_official	489:119543c9f674	581	#define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 \| TIM_SMCR_TS_1)
mbed_official	489:119543c9f674	582	#define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2)
mbed_official	489:119543c9f674	583	#define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 \| TIM_SMCR_TS_2)
mbed_official	489:119543c9f674	584	#define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 \| TIM_SMCR_TS_2)
mbed_official	489:119543c9f674	585	#define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS)
mbed_official	489:119543c9f674	586	/**
mbed_official	489:119543c9f674	587	* @}
mbed_official	489:119543c9f674	588	*/
mbed_official	489:119543c9f674	589
mbed_official	489:119543c9f674	590	/** @defgroup TIM_Clock_Polarity TIM Clock Polarity
mbed_official	489:119543c9f674	591	* @{
mbed_official	489:119543c9f674	592	*/
mbed_official	489:119543c9f674	593	#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx clock sources /
mbed_official	489:119543c9f674	594	#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx clock sources /
mbed_official	489:119543c9f674	595	#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /!< Polarity for TIx clock sources /
mbed_official	489:119543c9f674	596	#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /!< Polarity for TIx clock sources /
mbed_official	489:119543c9f674	597	#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /!< Polarity for TIx clock sources /
mbed_official	489:119543c9f674	598	/**
mbed_official	489:119543c9f674	599	* @}
mbed_official	489:119543c9f674	600	*/
mbed_official	489:119543c9f674	601
mbed_official	489:119543c9f674	602	/** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler
mbed_official	489:119543c9f674	603	* @{
mbed_official	489:119543c9f674	604	*/
mbed_official	489:119543c9f674	605	#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
mbed_official	489:119543c9f674	606	#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR Clock: Capture performed once every 2 events. /
mbed_official	489:119543c9f674	607	#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR Clock: Capture performed once every 4 events. /
mbed_official	489:119543c9f674	608	#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR Clock: Capture performed once every 8 events. /
mbed_official	489:119543c9f674	609	/**
mbed_official	489:119543c9f674	610	* @}
mbed_official	489:119543c9f674	611	*/
mbed_official	489:119543c9f674	612
mbed_official	489:119543c9f674	613	/** @defgroup TIM_ClearInput_Source TIM ClearInput Source
mbed_official	489:119543c9f674	614	* @{
mbed_official	489:119543c9f674	615	*/
mbed_official	489:119543c9f674	616	#define TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x0001)
mbed_official	489:119543c9f674	617	#define TIM_CLEARINPUTSOURCE_OCREFCLR ((uint32_t)0x0002)
mbed_official	489:119543c9f674	618	#define TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x0000)
mbed_official	489:119543c9f674	619	/**
mbed_official	489:119543c9f674	620	* @}
mbed_official	489:119543c9f674	621	*/
mbed_official	489:119543c9f674	622
mbed_official	489:119543c9f674	623	/** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity
mbed_official	489:119543c9f674	624	* @{
mbed_official	489:119543c9f674	625	*/
mbed_official	489:119543c9f674	626	#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx pin /
mbed_official	489:119543c9f674	627	#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx pin /
mbed_official	489:119543c9f674	628	/**
mbed_official	489:119543c9f674	629	* @}
mbed_official	489:119543c9f674	630	*/
mbed_official	489:119543c9f674	631
mbed_official	489:119543c9f674	632	/** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler
mbed_official	489:119543c9f674	633	* @{
mbed_official	489:119543c9f674	634	*/
mbed_official	489:119543c9f674	635	#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
mbed_official	489:119543c9f674	636	#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR pin: Capture performed once every 2 events. /
mbed_official	489:119543c9f674	637	#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR pin: Capture performed once every 4 events. /
mbed_official	489:119543c9f674	638	#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR pin: Capture performed once every 8 events. /
mbed_official	489:119543c9f674	639	/**
mbed_official	489:119543c9f674	640	* @}
mbed_official	489:119543c9f674	641	*/
mbed_official	489:119543c9f674	642
mbed_official	489:119543c9f674	643	/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR Off State Selection for Run mode state
mbed_official	489:119543c9f674	644	* @{
mbed_official	489:119543c9f674	645	*/
mbed_official	489:119543c9f674	646	#define TIM_OSSR_ENABLE (TIM_BDTR_OSSR)
mbed_official	489:119543c9f674	647	#define TIM_OSSR_DISABLE ((uint32_t)0x0000)
mbed_official	489:119543c9f674	648	/**
mbed_official	489:119543c9f674	649	* @}
mbed_official	489:119543c9f674	650	*/
mbed_official	489:119543c9f674	651
mbed_official	489:119543c9f674	652	/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI Off State Selection for Idle mode state
mbed_official	489:119543c9f674	653	* @{
mbed_official	489:119543c9f674	654	*/
mbed_official	489:119543c9f674	655	#define TIM_OSSI_ENABLE (TIM_BDTR_OSSI)
mbed_official	489:119543c9f674	656	#define TIM_OSSI_DISABLE ((uint32_t)0x0000)
mbed_official	489:119543c9f674	657	/**
mbed_official	489:119543c9f674	658	* @}
mbed_official	489:119543c9f674	659	*/
mbed_official	489:119543c9f674	660
mbed_official	489:119543c9f674	661	/** @defgroup TIM_Lock_level TIM Lock level
mbed_official	489:119543c9f674	662	* @{
mbed_official	489:119543c9f674	663	*/
mbed_official	489:119543c9f674	664	#define TIM_LOCKLEVEL_OFF ((uint32_t)0x0000)
mbed_official	489:119543c9f674	665	#define TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0)
mbed_official	489:119543c9f674	666	#define TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1)
mbed_official	489:119543c9f674	667	#define TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK)
mbed_official	489:119543c9f674	668	/**
mbed_official	489:119543c9f674	669	* @}
mbed_official	489:119543c9f674	670	*/
mbed_official	489:119543c9f674	671
mbed_official	489:119543c9f674	672	/** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable Disable
mbed_official	489:119543c9f674	673	* @{
mbed_official	489:119543c9f674	674	*/
mbed_official	489:119543c9f674	675	#define TIM_BREAK_ENABLE (TIM_BDTR_BKE)
mbed_official	489:119543c9f674	676	#define TIM_BREAK_DISABLE ((uint32_t)0x0000)
mbed_official	489:119543c9f674	677	/**
mbed_official	489:119543c9f674	678	* @}
mbed_official	489:119543c9f674	679	*/
mbed_official	489:119543c9f674	680
mbed_official	489:119543c9f674	681	/** @defgroup TIM_Break_Polarity TIM Break Input Polarity
mbed_official	489:119543c9f674	682	* @{
mbed_official	489:119543c9f674	683	*/
mbed_official	489:119543c9f674	684	#define TIM_BREAKPOLARITY_LOW ((uint32_t)0x0000)
mbed_official	489:119543c9f674	685	#define TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP)
mbed_official	489:119543c9f674	686	/**
mbed_official	489:119543c9f674	687	* @}
mbed_official	489:119543c9f674	688	*/
mbed_official	489:119543c9f674	689	/** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable
mbed_official	489:119543c9f674	690	* @{
mbed_official	489:119543c9f674	691	*/
mbed_official	489:119543c9f674	692	#define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE)
mbed_official	489:119543c9f674	693	#define TIM_AUTOMATICOUTPUT_DISABLE ((uint32_t)0x0000)
mbed_official	489:119543c9f674	694	/**
mbed_official	489:119543c9f674	695	* @}
mbed_official	489:119543c9f674	696	*/
mbed_official	489:119543c9f674	697
mbed_official	489:119543c9f674	698	/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
mbed_official	489:119543c9f674	699	* @{
mbed_official	489:119543c9f674	700	*/
mbed_official	489:119543c9f674	701	#define TIM_TRGO_RESET ((uint32_t)0x0000)
mbed_official	489:119543c9f674	702	#define TIM_TRGO_ENABLE (TIM_CR2_MMS_0)
mbed_official	489:119543c9f674	703	#define TIM_TRGO_UPDATE (TIM_CR2_MMS_1)
mbed_official	489:119543c9f674	704	#define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 \| TIM_CR2_MMS_0))
mbed_official	489:119543c9f674	705	#define TIM_TRGO_OC1REF (TIM_CR2_MMS_2)
mbed_official	489:119543c9f674	706	#define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 \| TIM_CR2_MMS_0))
mbed_official	489:119543c9f674	707	#define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 \| TIM_CR2_MMS_1))
mbed_official	489:119543c9f674	708	#define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 \| TIM_CR2_MMS_1 \| TIM_CR2_MMS_0))
mbed_official	489:119543c9f674	709	/**
mbed_official	489:119543c9f674	710	* @}
mbed_official	489:119543c9f674	711	*/
mbed_official	489:119543c9f674	712
mbed_official	489:119543c9f674	713	/** @defgroup TIM_Slave_Mode TIM Slave Mode
mbed_official	489:119543c9f674	714	* @{
mbed_official	489:119543c9f674	715	*/
mbed_official	489:119543c9f674	716	#define TIM_SLAVEMODE_DISABLE ((uint32_t)0x0000)
mbed_official	489:119543c9f674	717	#define TIM_SLAVEMODE_RESET ((uint32_t)0x0004)
mbed_official	489:119543c9f674	718	#define TIM_SLAVEMODE_GATED ((uint32_t)0x0005)
mbed_official	489:119543c9f674	719	#define TIM_SLAVEMODE_TRIGGER ((uint32_t)0x0006)
mbed_official	489:119543c9f674	720	#define TIM_SLAVEMODE_EXTERNAL1 ((uint32_t)0x0007)
mbed_official	489:119543c9f674	721	/**
mbed_official	489:119543c9f674	722	* @}
mbed_official	489:119543c9f674	723	*/
mbed_official	489:119543c9f674	724
mbed_official	489:119543c9f674	725	/** @defgroup TIM_Master_Slave_Mode TIM Master Slave Mode
mbed_official	489:119543c9f674	726	* @{
mbed_official	489:119543c9f674	727	*/
mbed_official	489:119543c9f674	728	#define TIM_MASTERSLAVEMODE_ENABLE ((uint32_t)0x0080)
mbed_official	489:119543c9f674	729	#define TIM_MASTERSLAVEMODE_DISABLE ((uint32_t)0x0000)
mbed_official	489:119543c9f674	730	/**
mbed_official	489:119543c9f674	731	* @}
mbed_official	489:119543c9f674	732	*/
mbed_official	489:119543c9f674	733
mbed_official	489:119543c9f674	734	/** @defgroup TIM_Trigger_Selection TIM Trigger Selection
mbed_official	489:119543c9f674	735	* @{
mbed_official	489:119543c9f674	736	*/
mbed_official	489:119543c9f674	737	#define TIM_TS_ITR0 ((uint32_t)0x0000)
mbed_official	489:119543c9f674	738	#define TIM_TS_ITR1 ((uint32_t)0x0010)
mbed_official	489:119543c9f674	739	#define TIM_TS_ITR2 ((uint32_t)0x0020)
mbed_official	489:119543c9f674	740	#define TIM_TS_ITR3 ((uint32_t)0x0030)
mbed_official	489:119543c9f674	741	#define TIM_TS_TI1F_ED ((uint32_t)0x0040)
mbed_official	489:119543c9f674	742	#define TIM_TS_TI1FP1 ((uint32_t)0x0050)
mbed_official	489:119543c9f674	743	#define TIM_TS_TI2FP2 ((uint32_t)0x0060)
mbed_official	489:119543c9f674	744	#define TIM_TS_ETRF ((uint32_t)0x0070)
mbed_official	489:119543c9f674	745	#define TIM_TS_NONE ((uint32_t)0xFFFF)
mbed_official	489:119543c9f674	746	/**
mbed_official	489:119543c9f674	747	* @}
mbed_official	489:119543c9f674	748	*/
mbed_official	489:119543c9f674	749
mbed_official	489:119543c9f674	750	/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
mbed_official	489:119543c9f674	751	* @{
mbed_official	489:119543c9f674	752	*/
mbed_official	489:119543c9f674	753	#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx trigger sources /
mbed_official	489:119543c9f674	754	#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx trigger sources /
mbed_official	489:119543c9f674	755	#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /!< Polarity for TIxFPx or TI1_ED trigger sources /
mbed_official	489:119543c9f674	756	#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /!< Polarity for TIxFPx or TI1_ED trigger sources /
mbed_official	489:119543c9f674	757	#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /!< Polarity for TIxFPx or TI1_ED trigger sources /
mbed_official	489:119543c9f674	758	/**
mbed_official	489:119543c9f674	759	* @}
mbed_official	489:119543c9f674	760	*/
mbed_official	489:119543c9f674	761
mbed_official	489:119543c9f674	762	/** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler
mbed_official	489:119543c9f674	763	* @{
mbed_official	489:119543c9f674	764	*/
mbed_official	489:119543c9f674	765	#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
mbed_official	489:119543c9f674	766	#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR Trigger: Capture performed once every 2 events. /
mbed_official	489:119543c9f674	767	#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR Trigger: Capture performed once every 4 events. /
mbed_official	489:119543c9f674	768	#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR Trigger: Capture performed once every 8 events. /
mbed_official	489:119543c9f674	769	/**
mbed_official	489:119543c9f674	770	* @}
mbed_official	489:119543c9f674	771	*/
mbed_official	489:119543c9f674	772
mbed_official	489:119543c9f674	773	/** @defgroup TIM_TI1_Selection TIM TI1 Input Selection
mbed_official	489:119543c9f674	774	* @{
mbed_official	489:119543c9f674	775	*/
mbed_official	489:119543c9f674	776	#define TIM_TI1SELECTION_CH1 ((uint32_t)0x0000)
mbed_official	489:119543c9f674	777	#define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S)
mbed_official	489:119543c9f674	778	/**
mbed_official	489:119543c9f674	779	* @}
mbed_official	489:119543c9f674	780	*/
mbed_official	489:119543c9f674	781
mbed_official	489:119543c9f674	782	/** @defgroup TIM_DMA_Base_address TIM DMA Base Address
mbed_official	489:119543c9f674	783	* @{
mbed_official	489:119543c9f674	784	*/
mbed_official	489:119543c9f674	785	#define TIM_DMABASE_CR1 (0x00000000)
mbed_official	489:119543c9f674	786	#define TIM_DMABASE_CR2 (0x00000001)
mbed_official	489:119543c9f674	787	#define TIM_DMABASE_SMCR (0x00000002)
mbed_official	489:119543c9f674	788	#define TIM_DMABASE_DIER (0x00000003)
mbed_official	489:119543c9f674	789	#define TIM_DMABASE_SR (0x00000004)
mbed_official	489:119543c9f674	790	#define TIM_DMABASE_EGR (0x00000005)
mbed_official	489:119543c9f674	791	#define TIM_DMABASE_CCMR1 (0x00000006)
mbed_official	489:119543c9f674	792	#define TIM_DMABASE_CCMR2 (0x00000007)
mbed_official	489:119543c9f674	793	#define TIM_DMABASE_CCER (0x00000008)
mbed_official	489:119543c9f674	794	#define TIM_DMABASE_CNT (0x00000009)
mbed_official	489:119543c9f674	795	#define TIM_DMABASE_PSC (0x0000000A)
mbed_official	489:119543c9f674	796	#define TIM_DMABASE_ARR (0x0000000B)
mbed_official	489:119543c9f674	797	#define TIM_DMABASE_RCR (0x0000000C)
mbed_official	489:119543c9f674	798	#define TIM_DMABASE_CCR1 (0x0000000D)
mbed_official	489:119543c9f674	799	#define TIM_DMABASE_CCR2 (0x0000000E)
mbed_official	489:119543c9f674	800	#define TIM_DMABASE_CCR3 (0x0000000F)
mbed_official	489:119543c9f674	801	#define TIM_DMABASE_CCR4 (0x00000010)
mbed_official	489:119543c9f674	802	#define TIM_DMABASE_BDTR (0x00000011)
mbed_official	489:119543c9f674	803	#define TIM_DMABASE_DCR (0x00000012)
mbed_official	489:119543c9f674	804	/**
mbed_official	489:119543c9f674	805	* @}
mbed_official	489:119543c9f674	806	*/
mbed_official	489:119543c9f674	807
mbed_official	489:119543c9f674	808	/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
mbed_official	489:119543c9f674	809	* @{
mbed_official	489:119543c9f674	810	*/
mbed_official	489:119543c9f674	811	#define TIM_DMABURSTLENGTH_1TRANSFER (0x00000000)
mbed_official	489:119543c9f674	812	#define TIM_DMABURSTLENGTH_2TRANSFERS (0x00000100)
mbed_official	489:119543c9f674	813	#define TIM_DMABURSTLENGTH_3TRANSFERS (0x00000200)
mbed_official	489:119543c9f674	814	#define TIM_DMABURSTLENGTH_4TRANSFERS (0x00000300)
mbed_official	489:119543c9f674	815	#define TIM_DMABURSTLENGTH_5TRANSFERS (0x00000400)
mbed_official	489:119543c9f674	816	#define TIM_DMABURSTLENGTH_6TRANSFERS (0x00000500)
mbed_official	489:119543c9f674	817	#define TIM_DMABURSTLENGTH_7TRANSFERS (0x00000600)
mbed_official	489:119543c9f674	818	#define TIM_DMABURSTLENGTH_8TRANSFERS (0x00000700)
mbed_official	489:119543c9f674	819	#define TIM_DMABURSTLENGTH_9TRANSFERS (0x00000800)
mbed_official	489:119543c9f674	820	#define TIM_DMABURSTLENGTH_10TRANSFERS (0x00000900)
mbed_official	489:119543c9f674	821	#define TIM_DMABURSTLENGTH_11TRANSFERS (0x00000A00)
mbed_official	489:119543c9f674	822	#define TIM_DMABURSTLENGTH_12TRANSFERS (0x00000B00)
mbed_official	489:119543c9f674	823	#define TIM_DMABURSTLENGTH_13TRANSFERS (0x00000C00)
mbed_official	489:119543c9f674	824	#define TIM_DMABURSTLENGTH_14TRANSFERS (0x00000D00)
mbed_official	489:119543c9f674	825	#define TIM_DMABURSTLENGTH_15TRANSFERS (0x00000E00)
mbed_official	489:119543c9f674	826	#define TIM_DMABURSTLENGTH_16TRANSFERS (0x00000F00)
mbed_official	489:119543c9f674	827	#define TIM_DMABURSTLENGTH_17TRANSFERS (0x00001000)
mbed_official	489:119543c9f674	828	#define TIM_DMABURSTLENGTH_18TRANSFERS (0x00001100)
mbed_official	489:119543c9f674	829	/**
mbed_official	489:119543c9f674	830	* @}
mbed_official	489:119543c9f674	831	*/
mbed_official	489:119543c9f674	832
mbed_official	489:119543c9f674	833	/** @defgroup TIM_DMA_Handle_index TIM DMA Handle Index
mbed_official	489:119543c9f674	834	* @{
mbed_official	489:119543c9f674	835	*/
mbed_official	489:119543c9f674	836	#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0) /!< Index of the DMA handle used for Update DMA requests /
mbed_official	489:119543c9f674	837	#define TIM_DMA_ID_CC1 ((uint16_t) 0x1) /!< Index of the DMA handle used for Capture/Compare 1 DMA requests /
mbed_official	489:119543c9f674	838	#define TIM_DMA_ID_CC2 ((uint16_t) 0x2) /!< Index of the DMA handle used for Capture/Compare 2 DMA requests /
mbed_official	489:119543c9f674	839	#define TIM_DMA_ID_CC3 ((uint16_t) 0x3) /!< Index of the DMA handle used for Capture/Compare 3 DMA requests /
mbed_official	489:119543c9f674	840	#define TIM_DMA_ID_CC4 ((uint16_t) 0x4) /!< Index of the DMA handle used for Capture/Compare 4 DMA requests /
mbed_official	489:119543c9f674	841	#define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x5) /!< Index of the DMA handle used for Commutation DMA requests /
mbed_official	489:119543c9f674	842	#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x6) /!< Index of the DMA handle used for Trigger DMA requests /
mbed_official	489:119543c9f674	843	/**
mbed_official	489:119543c9f674	844	* @}
mbed_official	489:119543c9f674	845	*/
mbed_official	489:119543c9f674	846
mbed_official	489:119543c9f674	847	/** @defgroup TIM_Channel_CC_State TIM Capture/Compare Channel State
mbed_official	489:119543c9f674	848	* @{
mbed_official	489:119543c9f674	849	*/
mbed_official	489:119543c9f674	850	#define TIM_CCx_ENABLE ((uint32_t)0x0001)
mbed_official	489:119543c9f674	851	#define TIM_CCx_DISABLE ((uint32_t)0x0000)
mbed_official	489:119543c9f674	852	#define TIM_CCxN_ENABLE ((uint32_t)0x0004)
mbed_official	489:119543c9f674	853	#define TIM_CCxN_DISABLE ((uint32_t)0x0000)
mbed_official	489:119543c9f674	854	/**
mbed_official	489:119543c9f674	855	* @}
mbed_official	489:119543c9f674	856	*/
mbed_official	489:119543c9f674	857
mbed_official	489:119543c9f674	858	/**
mbed_official	489:119543c9f674	859	* @}
mbed_official	489:119543c9f674	860	*/
mbed_official	489:119543c9f674	861
mbed_official	489:119543c9f674	862	/* Private Constants -----------------------------------------------------------*/
mbed_official	489:119543c9f674	863	/** @defgroup TIM_Private_Constants TIM Private Constants
mbed_official	489:119543c9f674	864	* @{
mbed_official	489:119543c9f674	865	*/
mbed_official	489:119543c9f674	866
mbed_official	489:119543c9f674	867	/* The counter of a timer instance is disabled only if all the CCx
mbed_official	489:119543c9f674	868	channels have been disabled */
mbed_official	489:119543c9f674	869	#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E \| TIM_CCER_CC2E \| TIM_CCER_CC3E \| TIM_CCER_CC4E))
mbed_official	489:119543c9f674	870
mbed_official	489:119543c9f674	871	/* The counter of a timer instance is disabled only if all the CCx and CCxN
mbed_official	489:119543c9f674	872	channels have been disabled */
mbed_official	489:119543c9f674	873	#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E \| TIM_CCER_CC2E \| TIM_CCER_CC3E \| TIM_CCER_CC4E))
mbed_official	489:119543c9f674	874	#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE \| TIM_CCER_CC2NE \| TIM_CCER_CC3NE))
mbed_official	489:119543c9f674	875
mbed_official	489:119543c9f674	876	/**
mbed_official	489:119543c9f674	877	* @}
mbed_official	489:119543c9f674	878	*/
mbed_official	489:119543c9f674	879
mbed_official	489:119543c9f674	880	/* Private Macros -----------------------------------------------------------*/
mbed_official	489:119543c9f674	881	/** @defgroup TIM_Private_Macros TIM Private Macros
mbed_official	489:119543c9f674	882	* @{
mbed_official	489:119543c9f674	883	*/
mbed_official	489:119543c9f674	884
mbed_official	489:119543c9f674	885	#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_COUNTERMODE_UP) \|\| \
mbed_official	489:119543c9f674	886	((MODE) == TIM_COUNTERMODE_DOWN) \|\| \
mbed_official	489:119543c9f674	887	((MODE) == TIM_COUNTERMODE_CENTERALIGNED1) \|\| \
mbed_official	489:119543c9f674	888	((MODE) == TIM_COUNTERMODE_CENTERALIGNED2) \|\| \
mbed_official	489:119543c9f674	889	((MODE) == TIM_COUNTERMODE_CENTERALIGNED3))
mbed_official	489:119543c9f674	890
mbed_official	489:119543c9f674	891	#define IS_TIM_CLOCKDIVISION_DIV(DIV) (((DIV) == TIM_CLOCKDIVISION_DIV1) \|\| \
mbed_official	489:119543c9f674	892	((DIV) == TIM_CLOCKDIVISION_DIV2) \|\| \
mbed_official	489:119543c9f674	893	((DIV) == TIM_CLOCKDIVISION_DIV4))
mbed_official	489:119543c9f674	894
mbed_official	489:119543c9f674	895	#define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) \|\| \
mbed_official	489:119543c9f674	896	((MODE) == TIM_OCMODE_PWM2))
mbed_official	489:119543c9f674	897
mbed_official	489:119543c9f674	898	#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) \|\| \
mbed_official	489:119543c9f674	899	((MODE) == TIM_OCMODE_ACTIVE) \|\| \
mbed_official	489:119543c9f674	900	((MODE) == TIM_OCMODE_INACTIVE) \|\| \
mbed_official	489:119543c9f674	901	((MODE) == TIM_OCMODE_TOGGLE) \|\| \
mbed_official	489:119543c9f674	902	((MODE) == TIM_OCMODE_FORCED_ACTIVE) \|\| \
mbed_official	489:119543c9f674	903	((MODE) == TIM_OCMODE_FORCED_INACTIVE))
mbed_official	489:119543c9f674	904
mbed_official	489:119543c9f674	905	#define IS_TIM_FAST_STATE(STATE) (((STATE) == TIM_OCFAST_DISABLE) \|\| \
mbed_official	489:119543c9f674	906	((STATE) == TIM_OCFAST_ENABLE))
mbed_official	489:119543c9f674	907
mbed_official	489:119543c9f674	908	#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPOLARITY_HIGH) \|\| \
mbed_official	489:119543c9f674	909	((POLARITY) == TIM_OCPOLARITY_LOW))
mbed_official	489:119543c9f674	910
mbed_official	489:119543c9f674	911	#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPOLARITY_HIGH) \|\| \
mbed_official	489:119543c9f674	912	((POLARITY) == TIM_OCNPOLARITY_LOW))
mbed_official	489:119543c9f674	913
mbed_official	489:119543c9f674	914	#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIDLESTATE_SET) \|\| \
mbed_official	489:119543c9f674	915	((STATE) == TIM_OCIDLESTATE_RESET))
mbed_official	489:119543c9f674	916
mbed_official	489:119543c9f674	917	#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIDLESTATE_SET) \|\| \
mbed_official	489:119543c9f674	918	((STATE) == TIM_OCNIDLESTATE_RESET))
mbed_official	489:119543c9f674	919
mbed_official	489:119543c9f674	920	#define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) \|\| \
mbed_official	489:119543c9f674	921	((CHANNEL) == TIM_CHANNEL_2) \|\| \
mbed_official	489:119543c9f674	922	((CHANNEL) == TIM_CHANNEL_3) \|\| \
mbed_official	489:119543c9f674	923	((CHANNEL) == TIM_CHANNEL_4) \|\| \
mbed_official	489:119543c9f674	924	((CHANNEL) == TIM_CHANNEL_ALL))
mbed_official	489:119543c9f674	925
mbed_official	489:119543c9f674	926	#define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) \|\| \
mbed_official	489:119543c9f674	927	((CHANNEL) == TIM_CHANNEL_2))
mbed_official	489:119543c9f674	928
mbed_official	489:119543c9f674	929	#define IS_TIM_COMPLEMENTARY_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) \|\| \
mbed_official	489:119543c9f674	930	((CHANNEL) == TIM_CHANNEL_2) \|\| \
mbed_official	489:119543c9f674	931	((CHANNEL) == TIM_CHANNEL_3))
mbed_official	489:119543c9f674	932
mbed_official	489:119543c9f674	933	#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPOLARITY_RISING) \|\| \
mbed_official	489:119543c9f674	934	((POLARITY) == TIM_ICPOLARITY_FALLING) \|\| \
mbed_official	489:119543c9f674	935	((POLARITY) == TIM_ICPOLARITY_BOTHEDGE))
mbed_official	489:119543c9f674	936
mbed_official	489:119543c9f674	937	#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSELECTION_DIRECTTI) \|\| \
mbed_official	489:119543c9f674	938	((SELECTION) == TIM_ICSELECTION_INDIRECTTI) \|\| \
mbed_official	489:119543c9f674	939	((SELECTION) == TIM_ICSELECTION_TRC))
mbed_official	489:119543c9f674	940
mbed_official	489:119543c9f674	941	#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) \|\| \
mbed_official	489:119543c9f674	942	((PRESCALER) == TIM_ICPSC_DIV2) \|\| \
mbed_official	489:119543c9f674	943	((PRESCALER) == TIM_ICPSC_DIV4) \|\| \
mbed_official	489:119543c9f674	944	((PRESCALER) == TIM_ICPSC_DIV8))
mbed_official	489:119543c9f674	945
mbed_official	489:119543c9f674	946	#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMODE_SINGLE) \|\| \
mbed_official	489:119543c9f674	947	((MODE) == TIM_OPMODE_REPETITIVE))
mbed_official	489:119543c9f674	948
mbed_official	489:119543c9f674	949	#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_ENCODERMODE_TI1) \|\| \
mbed_official	489:119543c9f674	950	((MODE) == TIM_ENCODERMODE_TI2) \|\| \
mbed_official	489:119543c9f674	951	((MODE) == TIM_ENCODERMODE_TI12))
mbed_official	489:119543c9f674	952
mbed_official	489:119543c9f674	953	#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFF80FF) == 0x00000000) && ((SOURCE) != 0x00000000))
mbed_official	489:119543c9f674	954
mbed_official	489:119543c9f674	955	#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00) == 0x00000000) && ((SOURCE) != 0x00000000))
mbed_official	489:119543c9f674	956
mbed_official	489:119543c9f674	957	#define IS_TIM_CLOCKSOURCE(CLOCK) (((CLOCK) == TIM_CLOCKSOURCE_INTERNAL) \|\| \
mbed_official	489:119543c9f674	958	((CLOCK) == TIM_CLOCKSOURCE_ETRMODE2) \|\| \
mbed_official	489:119543c9f674	959	((CLOCK) == TIM_CLOCKSOURCE_ITR0) \|\| \
mbed_official	489:119543c9f674	960	((CLOCK) == TIM_CLOCKSOURCE_ITR1) \|\| \
mbed_official	489:119543c9f674	961	((CLOCK) == TIM_CLOCKSOURCE_ITR2) \|\| \
mbed_official	489:119543c9f674	962	((CLOCK) == TIM_CLOCKSOURCE_ITR3) \|\| \
mbed_official	489:119543c9f674	963	((CLOCK) == TIM_CLOCKSOURCE_TI1ED) \|\| \
mbed_official	489:119543c9f674	964	((CLOCK) == TIM_CLOCKSOURCE_TI1) \|\| \
mbed_official	489:119543c9f674	965	((CLOCK) == TIM_CLOCKSOURCE_TI2) \|\| \
mbed_official	489:119543c9f674	966	((CLOCK) == TIM_CLOCKSOURCE_ETRMODE1))
mbed_official	489:119543c9f674	967
mbed_official	489:119543c9f674	968	#define IS_TIM_CLOCKPOLARITY(POLARITY) (((POLARITY) == TIM_CLOCKPOLARITY_INVERTED) \|\| \
mbed_official	489:119543c9f674	969	((POLARITY) == TIM_CLOCKPOLARITY_NONINVERTED) \|\| \
mbed_official	489:119543c9f674	970	((POLARITY) == TIM_CLOCKPOLARITY_RISING) \|\| \
mbed_official	489:119543c9f674	971	((POLARITY) == TIM_CLOCKPOLARITY_FALLING) \|\| \
mbed_official	489:119543c9f674	972	((POLARITY) == TIM_CLOCKPOLARITY_BOTHEDGE))
mbed_official	489:119543c9f674	973
mbed_official	489:119543c9f674	974	#define IS_TIM_CLOCKPRESCALER(PRESCALER) (((PRESCALER) == TIM_CLOCKPRESCALER_DIV1) \|\| \
mbed_official	489:119543c9f674	975	((PRESCALER) == TIM_CLOCKPRESCALER_DIV2) \|\| \
mbed_official	489:119543c9f674	976	((PRESCALER) == TIM_CLOCKPRESCALER_DIV4) \|\| \
mbed_official	489:119543c9f674	977	((PRESCALER) == TIM_CLOCKPRESCALER_DIV8))
mbed_official	489:119543c9f674	978
mbed_official	489:119543c9f674	979	#define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0xF)
mbed_official	489:119543c9f674	980
mbed_official	489:119543c9f674	981	#define IS_TIM_CLEARINPUT_SOURCE(SOURCE) (((SOURCE) == TIM_CLEARINPUTSOURCE_ETR) \|\| \
mbed_official	489:119543c9f674	982	((SOURCE) == TIM_CLEARINPUTSOURCE_OCREFCLR) \|\| \
mbed_official	489:119543c9f674	983	((SOURCE) == TIM_CLEARINPUTSOURCE_NONE))
mbed_official	489:119543c9f674	984
mbed_official	489:119543c9f674	985	#define IS_TIM_CLEARINPUT_POLARITY(POLARITY) (((POLARITY) == TIM_CLEARINPUTPOLARITY_INVERTED) \|\| \
mbed_official	489:119543c9f674	986	((POLARITY) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
mbed_official	489:119543c9f674	987
mbed_official	489:119543c9f674	988	#define IS_TIM_CLEARINPUT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV1) \|\| \
mbed_official	489:119543c9f674	989	((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV2) \|\| \
mbed_official	489:119543c9f674	990	((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV4) \|\| \
mbed_official	489:119543c9f674	991	((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV8))
mbed_official	489:119543c9f674	992
mbed_official	489:119543c9f674	993	#define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
mbed_official	489:119543c9f674	994
mbed_official	489:119543c9f674	995	#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSR_ENABLE) \|\| \
mbed_official	489:119543c9f674	996	((STATE) == TIM_OSSR_DISABLE))
mbed_official	489:119543c9f674	997
mbed_official	489:119543c9f674	998	#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSI_ENABLE) \|\| \
mbed_official	489:119543c9f674	999	((STATE) == TIM_OSSI_DISABLE))
mbed_official	489:119543c9f674	1000
mbed_official	489:119543c9f674	1001	#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLEVEL_OFF) \|\| \
mbed_official	489:119543c9f674	1002	((LEVEL) == TIM_LOCKLEVEL_1) \|\| \
mbed_official	489:119543c9f674	1003	((LEVEL) == TIM_LOCKLEVEL_2) \|\| \
mbed_official	489:119543c9f674	1004	((LEVEL) == TIM_LOCKLEVEL_3))
mbed_official	489:119543c9f674	1005
mbed_official	489:119543c9f674	1006	#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_BREAK_ENABLE) \|\| \
mbed_official	489:119543c9f674	1007	((STATE) == TIM_BREAK_DISABLE))
mbed_official	489:119543c9f674	1008
mbed_official	489:119543c9f674	1009	#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BREAKPOLARITY_LOW) \|\| \
mbed_official	489:119543c9f674	1010	((POLARITY) == TIM_BREAKPOLARITY_HIGH))
mbed_official	489:119543c9f674	1011
mbed_official	489:119543c9f674	1012	#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AUTOMATICOUTPUT_ENABLE) \|\| \
mbed_official	489:119543c9f674	1013	((STATE) == TIM_AUTOMATICOUTPUT_DISABLE))
mbed_official	489:119543c9f674	1014
mbed_official	489:119543c9f674	1015	#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO_RESET) \|\| \
mbed_official	489:119543c9f674	1016	((SOURCE) == TIM_TRGO_ENABLE) \|\| \
mbed_official	489:119543c9f674	1017	((SOURCE) == TIM_TRGO_UPDATE) \|\| \
mbed_official	489:119543c9f674	1018	((SOURCE) == TIM_TRGO_OC1) \|\| \
mbed_official	489:119543c9f674	1019	((SOURCE) == TIM_TRGO_OC1REF) \|\| \
mbed_official	489:119543c9f674	1020	((SOURCE) == TIM_TRGO_OC2REF) \|\| \
mbed_official	489:119543c9f674	1021	((SOURCE) == TIM_TRGO_OC3REF) \|\| \
mbed_official	489:119543c9f674	1022	((SOURCE) == TIM_TRGO_OC4REF))
mbed_official	489:119543c9f674	1023
mbed_official	489:119543c9f674	1024	#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) \|\| \
mbed_official	489:119543c9f674	1025	((MODE) == TIM_SLAVEMODE_GATED) \|\| \
mbed_official	489:119543c9f674	1026	((MODE) == TIM_SLAVEMODE_RESET) \|\| \
mbed_official	489:119543c9f674	1027	((MODE) == TIM_SLAVEMODE_TRIGGER) \|\| \
mbed_official	489:119543c9f674	1028	((MODE) == TIM_SLAVEMODE_EXTERNAL1))
mbed_official	489:119543c9f674	1029
mbed_official	489:119543c9f674	1030	#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MASTERSLAVEMODE_ENABLE) \|\| \
mbed_official	489:119543c9f674	1031	((STATE) == TIM_MASTERSLAVEMODE_DISABLE))
mbed_official	489:119543c9f674	1032
mbed_official	489:119543c9f674	1033	#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) \|\| \
mbed_official	489:119543c9f674	1034	((SELECTION) == TIM_TS_ITR1) \|\| \
mbed_official	489:119543c9f674	1035	((SELECTION) == TIM_TS_ITR2) \|\| \
mbed_official	489:119543c9f674	1036	((SELECTION) == TIM_TS_ITR3) \|\| \
mbed_official	489:119543c9f674	1037	((SELECTION) == TIM_TS_TI1F_ED) \|\| \
mbed_official	489:119543c9f674	1038	((SELECTION) == TIM_TS_TI1FP1) \|\| \
mbed_official	489:119543c9f674	1039	((SELECTION) == TIM_TS_TI2FP2) \|\| \
mbed_official	489:119543c9f674	1040	((SELECTION) == TIM_TS_ETRF))
mbed_official	489:119543c9f674	1041
mbed_official	489:119543c9f674	1042	#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) \|\| \
mbed_official	489:119543c9f674	1043	((SELECTION) == TIM_TS_ITR1) \|\| \
mbed_official	489:119543c9f674	1044	((SELECTION) == TIM_TS_ITR2) \|\| \
mbed_official	489:119543c9f674	1045	((SELECTION) == TIM_TS_ITR3) \|\| \
mbed_official	489:119543c9f674	1046	((SELECTION) == TIM_TS_NONE))
mbed_official	489:119543c9f674	1047
mbed_official	489:119543c9f674	1048	#define IS_TIM_TRIGGERPOLARITY(POLARITY) (((POLARITY) == TIM_TRIGGERPOLARITY_INVERTED ) \|\| \
mbed_official	489:119543c9f674	1049	((POLARITY) == TIM_TRIGGERPOLARITY_NONINVERTED) \|\| \
mbed_official	489:119543c9f674	1050	((POLARITY) == TIM_TRIGGERPOLARITY_RISING ) \|\| \
mbed_official	489:119543c9f674	1051	((POLARITY) == TIM_TRIGGERPOLARITY_FALLING ) \|\| \
mbed_official	489:119543c9f674	1052	((POLARITY) == TIM_TRIGGERPOLARITY_BOTHEDGE ))
mbed_official	489:119543c9f674	1053
mbed_official	489:119543c9f674	1054	#define IS_TIM_TRIGGERPRESCALER(PRESCALER) (((PRESCALER) == TIM_TRIGGERPRESCALER_DIV1) \|\| \
mbed_official	489:119543c9f674	1055	((PRESCALER) == TIM_TRIGGERPRESCALER_DIV2) \|\| \
mbed_official	489:119543c9f674	1056	((PRESCALER) == TIM_TRIGGERPRESCALER_DIV4) \|\| \
mbed_official	489:119543c9f674	1057	((PRESCALER) == TIM_TRIGGERPRESCALER_DIV8))
mbed_official	489:119543c9f674	1058
mbed_official	489:119543c9f674	1059	#define IS_TIM_TRIGGERFILTER(ICFILTER) ((ICFILTER) <= 0xF)
mbed_official	489:119543c9f674	1060
mbed_official	489:119543c9f674	1061	#define IS_TIM_TI1SELECTION(TI1SELECTION) (((TI1SELECTION) == TIM_TI1SELECTION_CH1) \|\| \
mbed_official	489:119543c9f674	1062	((TI1SELECTION) == TIM_TI1SELECTION_XORCOMBINATION))
mbed_official	489:119543c9f674	1063
mbed_official	489:119543c9f674	1064	#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABASE_CR1) \|\| \
mbed_official	489:119543c9f674	1065	((BASE) == TIM_DMABASE_CR2) \|\| \
mbed_official	489:119543c9f674	1066	((BASE) == TIM_DMABASE_SMCR) \|\| \
mbed_official	489:119543c9f674	1067	((BASE) == TIM_DMABASE_DIER) \|\| \
mbed_official	489:119543c9f674	1068	((BASE) == TIM_DMABASE_SR) \|\| \
mbed_official	489:119543c9f674	1069	((BASE) == TIM_DMABASE_EGR) \|\| \
mbed_official	489:119543c9f674	1070	((BASE) == TIM_DMABASE_CCMR1) \|\| \
mbed_official	489:119543c9f674	1071	((BASE) == TIM_DMABASE_CCMR2) \|\| \
mbed_official	489:119543c9f674	1072	((BASE) == TIM_DMABASE_CCER) \|\| \
mbed_official	489:119543c9f674	1073	((BASE) == TIM_DMABASE_CNT) \|\| \
mbed_official	489:119543c9f674	1074	((BASE) == TIM_DMABASE_PSC) \|\| \
mbed_official	489:119543c9f674	1075	((BASE) == TIM_DMABASE_ARR) \|\| \
mbed_official	489:119543c9f674	1076	((BASE) == TIM_DMABASE_RCR) \|\| \
mbed_official	489:119543c9f674	1077	((BASE) == TIM_DMABASE_CCR1) \|\| \
mbed_official	489:119543c9f674	1078	((BASE) == TIM_DMABASE_CCR2) \|\| \
mbed_official	489:119543c9f674	1079	((BASE) == TIM_DMABASE_CCR3) \|\| \
mbed_official	489:119543c9f674	1080	((BASE) == TIM_DMABASE_CCR4) \|\| \
mbed_official	489:119543c9f674	1081	((BASE) == TIM_DMABASE_BDTR) \|\| \
mbed_official	489:119543c9f674	1082	((BASE) == TIM_DMABASE_DCR))
mbed_official	489:119543c9f674	1083
mbed_official	489:119543c9f674	1084	#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABURSTLENGTH_1TRANSFER) \|\| \
mbed_official	489:119543c9f674	1085	((LENGTH) == TIM_DMABURSTLENGTH_2TRANSFERS) \|\| \
mbed_official	489:119543c9f674	1086	((LENGTH) == TIM_DMABURSTLENGTH_3TRANSFERS) \|\| \
mbed_official	489:119543c9f674	1087	((LENGTH) == TIM_DMABURSTLENGTH_4TRANSFERS) \|\| \
mbed_official	489:119543c9f674	1088	((LENGTH) == TIM_DMABURSTLENGTH_5TRANSFERS) \|\| \
mbed_official	489:119543c9f674	1089	((LENGTH) == TIM_DMABURSTLENGTH_6TRANSFERS) \|\| \
mbed_official	489:119543c9f674	1090	((LENGTH) == TIM_DMABURSTLENGTH_7TRANSFERS) \|\| \
mbed_official	489:119543c9f674	1091	((LENGTH) == TIM_DMABURSTLENGTH_8TRANSFERS) \|\| \
mbed_official	489:119543c9f674	1092	((LENGTH) == TIM_DMABURSTLENGTH_9TRANSFERS) \|\| \
mbed_official	489:119543c9f674	1093	((LENGTH) == TIM_DMABURSTLENGTH_10TRANSFERS) \|\| \
mbed_official	489:119543c9f674	1094	((LENGTH) == TIM_DMABURSTLENGTH_11TRANSFERS) \|\| \
mbed_official	489:119543c9f674	1095	((LENGTH) == TIM_DMABURSTLENGTH_12TRANSFERS) \|\| \
mbed_official	489:119543c9f674	1096	((LENGTH) == TIM_DMABURSTLENGTH_13TRANSFERS) \|\| \
mbed_official	489:119543c9f674	1097	((LENGTH) == TIM_DMABURSTLENGTH_14TRANSFERS) \|\| \
mbed_official	489:119543c9f674	1098	((LENGTH) == TIM_DMABURSTLENGTH_15TRANSFERS) \|\| \
mbed_official	489:119543c9f674	1099	((LENGTH) == TIM_DMABURSTLENGTH_16TRANSFERS) \|\| \
mbed_official	489:119543c9f674	1100	((LENGTH) == TIM_DMABURSTLENGTH_17TRANSFERS) \|\| \
mbed_official	489:119543c9f674	1101	((LENGTH) == TIM_DMABURSTLENGTH_18TRANSFERS))
mbed_official	489:119543c9f674	1102
mbed_official	489:119543c9f674	1103	#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
mbed_official	489:119543c9f674	1104
mbed_official	489:119543c9f674	1105	/** @brief Set TIM IC prescaler
mbed_official	489:119543c9f674	1106	* @param __HANDLE__: TIM handle
mbed_official	489:119543c9f674	1107	* @param __CHANNEL__: specifies TIM Channel
mbed_official	489:119543c9f674	1108	* @param __ICPSC__: specifies the prescaler value.
mbed_official	489:119543c9f674	1109	* @retval None
mbed_official	489:119543c9f674	1110	*/
mbed_official	489:119543c9f674	1111	#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
mbed_official	489:119543c9f674	1112	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 \|= (__ICPSC__)) :\
mbed_official	489:119543c9f674	1113	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 \|= ((__ICPSC__) << 8)) :\
mbed_official	489:119543c9f674	1114	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 \|= (__ICPSC__)) :\
mbed_official	489:119543c9f674	1115	((__HANDLE__)->Instance->CCMR2 \|= ((__ICPSC__) << 8)))
mbed_official	489:119543c9f674	1116
mbed_official	489:119543c9f674	1117	/** @brief Reset TIM IC prescaler
mbed_official	489:119543c9f674	1118	* @param __HANDLE__: TIM handle
mbed_official	489:119543c9f674	1119	* @param __CHANNEL__: specifies TIM Channel
mbed_official	489:119543c9f674	1120	* @retval None
mbed_official	489:119543c9f674	1121	*/
mbed_official	489:119543c9f674	1122	#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
mbed_official	489:119543c9f674	1123	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\
mbed_official	489:119543c9f674	1124	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\
mbed_official	489:119543c9f674	1125	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\
mbed_official	489:119543c9f674	1126	((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC))
mbed_official	489:119543c9f674	1127
mbed_official	489:119543c9f674	1128
mbed_official	489:119543c9f674	1129	/** @brief Set TIM IC polarity
mbed_official	489:119543c9f674	1130	* @param __HANDLE__: TIM handle
mbed_official	489:119543c9f674	1131	* @param __CHANNEL__: specifies TIM Channel
mbed_official	489:119543c9f674	1132	* @param __POLARITY__: specifies TIM Channel Polarity
mbed_official	489:119543c9f674	1133	* @retval None
mbed_official	489:119543c9f674	1134	*/
mbed_official	489:119543c9f674	1135	#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
mbed_official	489:119543c9f674	1136	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER \|= (__POLARITY__)) :\
mbed_official	489:119543c9f674	1137	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER \|= ((__POLARITY__) << 4)) :\
mbed_official	489:119543c9f674	1138	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER \|= ((__POLARITY__) << 8)) :\
mbed_official	489:119543c9f674	1139	((__HANDLE__)->Instance->CCER \|= (((__POLARITY__) << 12) & TIM_CCER_CC4P)))
mbed_official	489:119543c9f674	1140
mbed_official	489:119543c9f674	1141	/** @brief Reset TIM IC polarity
mbed_official	489:119543c9f674	1142	* @param __HANDLE__: TIM handle
mbed_official	489:119543c9f674	1143	* @param __CHANNEL__: specifies TIM Channel
mbed_official	489:119543c9f674	1144	* @retval None
mbed_official	489:119543c9f674	1145	*/
mbed_official	489:119543c9f674	1146	#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
mbed_official	489:119543c9f674	1147	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P \| TIM_CCER_CC1NP)) :\
mbed_official	489:119543c9f674	1148	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P \| TIM_CCER_CC2NP)) :\
mbed_official	489:119543c9f674	1149	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P \| TIM_CCER_CC3NP)) :\
mbed_official	489:119543c9f674	1150	((__HANDLE__)->Instance->CCER &= (uint16_t)~TIM_CCER_CC4P))
mbed_official	489:119543c9f674	1151
mbed_official	489:119543c9f674	1152	/**
mbed_official	489:119543c9f674	1153	* @}
mbed_official	489:119543c9f674	1154	*/
mbed_official	489:119543c9f674	1155
mbed_official	489:119543c9f674	1156	/* Private Functions --------------------------------------------------------*/
mbed_official	489:119543c9f674	1157	/** @addtogroup TIM_Private_Functions
mbed_official	489:119543c9f674	1158	* @{
mbed_official	489:119543c9f674	1159	*/
mbed_official	489:119543c9f674	1160	void TIM_Base_SetConfig(TIM_TypeDef TIMx, TIM_Base_InitTypeDef Structure);
mbed_official	489:119543c9f674	1161	void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
mbed_official	489:119543c9f674	1162	void TIM_OC2_SetConfig(TIM_TypeDef TIMx, TIM_OC_InitTypeDef OC_Config);
mbed_official	489:119543c9f674	1163	void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
mbed_official	489:119543c9f674	1164	void TIM_DMAError(DMA_HandleTypeDef *hdma);
mbed_official	489:119543c9f674	1165	void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
mbed_official	489:119543c9f674	1166	void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState);
mbed_official	489:119543c9f674	1167	/**
mbed_official	489:119543c9f674	1168	* @}
mbed_official	489:119543c9f674	1169	*/
mbed_official	489:119543c9f674	1170
mbed_official	489:119543c9f674	1171	/* Exported macros -----------------------------------------------------------*/
mbed_official	489:119543c9f674	1172	/** @defgroup TIM_Exported_Macros TIM Exported Macros
mbed_official	489:119543c9f674	1173	* @{
mbed_official	489:119543c9f674	1174	*/
mbed_official	489:119543c9f674	1175
mbed_official	489:119543c9f674	1176	/** @brief Reset TIM handle state
mbed_official	489:119543c9f674	1177	* @param __HANDLE__: TIM handle.
mbed_official	489:119543c9f674	1178	* @retval None
mbed_official	489:119543c9f674	1179	*/
mbed_official	489:119543c9f674	1180	#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
mbed_official	489:119543c9f674	1181
mbed_official	489:119543c9f674	1182	/**
mbed_official	489:119543c9f674	1183	* @brief Enable the TIM peripheral.
mbed_official	489:119543c9f674	1184	* @param __HANDLE__: TIM handle
mbed_official	489:119543c9f674	1185	* @retval None
mbed_official	489:119543c9f674	1186	*/
mbed_official	489:119543c9f674	1187	#define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1\|=(TIM_CR1_CEN))
mbed_official	489:119543c9f674	1188
mbed_official	489:119543c9f674	1189	/**
mbed_official	489:119543c9f674	1190	* @brief Enable the TIM main Output.
mbed_official	489:119543c9f674	1191	* @param __HANDLE__: TIM handle
mbed_official	489:119543c9f674	1192	* @retval None
mbed_official	489:119543c9f674	1193	*/
mbed_official	489:119543c9f674	1194	#define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR\|=(TIM_BDTR_MOE))
mbed_official	489:119543c9f674	1195
mbed_official	489:119543c9f674	1196	/**
mbed_official	489:119543c9f674	1197	* @brief Disable the TIM peripheral.
mbed_official	489:119543c9f674	1198	* @param __HANDLE__: TIM handle
mbed_official	489:119543c9f674	1199	* @retval None
mbed_official	489:119543c9f674	1200	*/
mbed_official	489:119543c9f674	1201	#define __HAL_TIM_DISABLE(__HANDLE__) \
mbed_official	489:119543c9f674	1202	do { \
mbed_official	489:119543c9f674	1203	if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \
mbed_official	489:119543c9f674	1204	{ \
mbed_official	489:119543c9f674	1205	if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \
mbed_official	489:119543c9f674	1206	{ \
mbed_official	489:119543c9f674	1207	(__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
mbed_official	489:119543c9f674	1208	} \
mbed_official	489:119543c9f674	1209	} \
mbed_official	489:119543c9f674	1210	} while(0)
mbed_official	489:119543c9f674	1211	/* The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN
mbed_official	489:119543c9f674	1212	channels have been disabled */
mbed_official	489:119543c9f674	1213	/**
mbed_official	489:119543c9f674	1214	* @brief Disable the TIM main Output.
mbed_official	489:119543c9f674	1215	* @param __HANDLE__: TIM handle
mbed_official	489:119543c9f674	1216	* @retval None
mbed_official	489:119543c9f674	1217	* @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled
mbed_official	489:119543c9f674	1218	*/
mbed_official	489:119543c9f674	1219	#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
mbed_official	489:119543c9f674	1220	do { \
mbed_official	489:119543c9f674	1221	if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \
mbed_official	489:119543c9f674	1222	{ \
mbed_official	489:119543c9f674	1223	if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \
mbed_official	489:119543c9f674	1224	{ \
mbed_official	489:119543c9f674	1225	(__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
mbed_official	489:119543c9f674	1226	} \
mbed_official	489:119543c9f674	1227	} \
mbed_official	489:119543c9f674	1228	} while(0)
mbed_official	489:119543c9f674	1229
mbed_official	489:119543c9f674	1230	/**
mbed_official	489:119543c9f674	1231	* @brief Enables the specified TIM interrupt.
mbed_official	489:119543c9f674	1232	* @param __HANDLE__: specifies the TIM Handle.
mbed_official	489:119543c9f674	1233	* @param __INTERRUPT__: specifies the TIM interrupt source to enable.
mbed_official	489:119543c9f674	1234	* This parameter can be one of the following values:
mbed_official	489:119543c9f674	1235	* @arg TIM_IT_UPDATE: Update interrupt
mbed_official	489:119543c9f674	1236	* @arg TIM_IT_CC1: Capture/Compare 1 interrupt
mbed_official	489:119543c9f674	1237	* @arg TIM_IT_CC2: Capture/Compare 2 interrupt
mbed_official	489:119543c9f674	1238	* @arg TIM_IT_CC3: Capture/Compare 3 interrupt
mbed_official	489:119543c9f674	1239	* @arg TIM_IT_CC4: Capture/Compare 4 interrupt
mbed_official	489:119543c9f674	1240	* @arg TIM_IT_COM: Commutation interrupt
mbed_official	489:119543c9f674	1241	* @arg TIM_IT_TRIGGER: Trigger interrupt
mbed_official	489:119543c9f674	1242	* @arg TIM_IT_BREAK: Break interrupt
mbed_official	489:119543c9f674	1243	* @retval None
mbed_official	489:119543c9f674	1244	*/
mbed_official	489:119543c9f674	1245	#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER \|= (__INTERRUPT__))
mbed_official	489:119543c9f674	1246
mbed_official	489:119543c9f674	1247	/**
mbed_official	489:119543c9f674	1248	* @brief Disables the specified TIM interrupt.
mbed_official	489:119543c9f674	1249	* @param __HANDLE__: specifies the TIM Handle.
mbed_official	489:119543c9f674	1250	* @param __INTERRUPT__: specifies the TIM interrupt source to disable.
mbed_official	489:119543c9f674	1251	* This parameter can be one of the following values:
mbed_official	489:119543c9f674	1252	* @arg TIM_IT_UPDATE: Update interrupt
mbed_official	489:119543c9f674	1253	* @arg TIM_IT_CC1: Capture/Compare 1 interrupt
mbed_official	489:119543c9f674	1254	* @arg TIM_IT_CC2: Capture/Compare 2 interrupt
mbed_official	489:119543c9f674	1255	* @arg TIM_IT_CC3: Capture/Compare 3 interrupt
mbed_official	489:119543c9f674	1256	* @arg TIM_IT_CC4: Capture/Compare 4 interrupt
mbed_official	489:119543c9f674	1257	* @arg TIM_IT_COM: Commutation interrupt
mbed_official	489:119543c9f674	1258	* @arg TIM_IT_TRIGGER: Trigger interrupt
mbed_official	489:119543c9f674	1259	* @arg TIM_IT_BREAK: Break interrupt
mbed_official	489:119543c9f674	1260	* @retval None
mbed_official	489:119543c9f674	1261	*/
mbed_official	489:119543c9f674	1262	#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
mbed_official	489:119543c9f674	1263
mbed_official	489:119543c9f674	1264	/**
mbed_official	489:119543c9f674	1265	* @brief Enables the specified DMA request.
mbed_official	489:119543c9f674	1266	* @param __HANDLE__: specifies the TIM Handle.
mbed_official	489:119543c9f674	1267	* @param __DMA__: specifies the TIM DMA request to enable.
mbed_official	489:119543c9f674	1268	* This parameter can be one of the following values:
mbed_official	489:119543c9f674	1269	* @arg TIM_DMA_UPDATE: Update DMA request
mbed_official	489:119543c9f674	1270	* @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
mbed_official	489:119543c9f674	1271	* @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
mbed_official	489:119543c9f674	1272	* @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
mbed_official	489:119543c9f674	1273	* @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
mbed_official	489:119543c9f674	1274	* @arg TIM_DMA_COM: Commutation DMA request
mbed_official	489:119543c9f674	1275	* @arg TIM_DMA_TRIGGER: Trigger DMA request
mbed_official	489:119543c9f674	1276	* @retval None
mbed_official	489:119543c9f674	1277	*/
mbed_official	489:119543c9f674	1278	#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER \|= (__DMA__))
mbed_official	489:119543c9f674	1279
mbed_official	489:119543c9f674	1280	/**
mbed_official	489:119543c9f674	1281	* @brief Disables the specified DMA request.
mbed_official	489:119543c9f674	1282	* @param __HANDLE__: specifies the TIM Handle.
mbed_official	489:119543c9f674	1283	* @param __DMA__: specifies the TIM DMA request to disable.
mbed_official	489:119543c9f674	1284	* This parameter can be one of the following values:
mbed_official	489:119543c9f674	1285	* @arg TIM_DMA_UPDATE: Update DMA request
mbed_official	489:119543c9f674	1286	* @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
mbed_official	489:119543c9f674	1287	* @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
mbed_official	489:119543c9f674	1288	* @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
mbed_official	489:119543c9f674	1289	* @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
mbed_official	489:119543c9f674	1290	* @arg TIM_DMA_COM: Commutation DMA request
mbed_official	489:119543c9f674	1291	* @arg TIM_DMA_TRIGGER: Trigger DMA request
mbed_official	489:119543c9f674	1292	* @retval None
mbed_official	489:119543c9f674	1293	*/
mbed_official	489:119543c9f674	1294	#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
mbed_official	489:119543c9f674	1295
mbed_official	489:119543c9f674	1296	/**
mbed_official	489:119543c9f674	1297	* @brief Checks whether the specified TIM interrupt flag is set or not.
mbed_official	489:119543c9f674	1298	* @param __HANDLE__: specifies the TIM Handle.
mbed_official	489:119543c9f674	1299	* @param __FLAG__: specifies the TIM interrupt flag to check.
mbed_official	489:119543c9f674	1300	* This parameter can be one of the following values:
mbed_official	489:119543c9f674	1301	* @arg TIM_FLAG_UPDATE: Update interrupt flag
mbed_official	489:119543c9f674	1302	* @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
mbed_official	489:119543c9f674	1303	* @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
mbed_official	489:119543c9f674	1304	* @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
mbed_official	489:119543c9f674	1305	* @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
mbed_official	489:119543c9f674	1306	* @arg TIM_FLAG_COM: Commutation interrupt flag
mbed_official	489:119543c9f674	1307	* @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
mbed_official	489:119543c9f674	1308	* @arg TIM_FLAG_BREAK: Break interrupt flag
mbed_official	489:119543c9f674	1309	* @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
mbed_official	489:119543c9f674	1310	* @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
mbed_official	489:119543c9f674	1311	* @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
mbed_official	489:119543c9f674	1312	* @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
mbed_official	489:119543c9f674	1313	* @retval The new state of __FLAG__ (TRUE or FALSE).
mbed_official	489:119543c9f674	1314	*/
mbed_official	489:119543c9f674	1315	#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
mbed_official	489:119543c9f674	1316
mbed_official	489:119543c9f674	1317	/**
mbed_official	489:119543c9f674	1318	* @brief Clears the specified TIM interrupt flag.
mbed_official	489:119543c9f674	1319	* @param __HANDLE__: specifies the TIM Handle.
mbed_official	489:119543c9f674	1320	* @param __FLAG__: specifies the TIM interrupt flag to clear.
mbed_official	489:119543c9f674	1321	* This parameter can be one of the following values:
mbed_official	489:119543c9f674	1322	* @arg TIM_FLAG_UPDATE: Update interrupt flag
mbed_official	489:119543c9f674	1323	* @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
mbed_official	489:119543c9f674	1324	* @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
mbed_official	489:119543c9f674	1325	* @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
mbed_official	489:119543c9f674	1326	* @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
mbed_official	489:119543c9f674	1327	* @arg TIM_FLAG_COM: Commutation interrupt flag
mbed_official	489:119543c9f674	1328	* @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
mbed_official	489:119543c9f674	1329	* @arg TIM_FLAG_BREAK: Break interrupt flag
mbed_official	489:119543c9f674	1330	* @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
mbed_official	489:119543c9f674	1331	* @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
mbed_official	489:119543c9f674	1332	* @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
mbed_official	489:119543c9f674	1333	* @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
mbed_official	489:119543c9f674	1334	* @retval The new state of __FLAG__ (TRUE or FALSE).
mbed_official	489:119543c9f674	1335	*/
mbed_official	489:119543c9f674	1336	#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
mbed_official	489:119543c9f674	1337
mbed_official	489:119543c9f674	1338	/**
mbed_official	489:119543c9f674	1339	* @brief Checks whether the specified TIM interrupt has occurred or not.
mbed_official	489:119543c9f674	1340	* @param __HANDLE__: TIM handle
mbed_official	489:119543c9f674	1341	* @param __INTERRUPT__: specifies the TIM interrupt source to check.
mbed_official	489:119543c9f674	1342	* @retval The state of TIM_IT (SET or RESET).
mbed_official	489:119543c9f674	1343	*/
mbed_official	489:119543c9f674	1344	#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
mbed_official	489:119543c9f674	1345
mbed_official	489:119543c9f674	1346	/**
mbed_official	489:119543c9f674	1347	* @brief Clear the TIM interrupt pending bits
mbed_official	489:119543c9f674	1348	* @param __HANDLE__: TIM handle
mbed_official	489:119543c9f674	1349	* @param __INTERRUPT__: specifies the interrupt pending bit to clear.
mbed_official	489:119543c9f674	1350	* @retval None
mbed_official	489:119543c9f674	1351	*/
mbed_official	489:119543c9f674	1352	#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
mbed_official	489:119543c9f674	1353
mbed_official	489:119543c9f674	1354	/**
mbed_official	489:119543c9f674	1355	* @brief Indicates whether or not the TIM Counter is used as downcounter
mbed_official	489:119543c9f674	1356	* @param __HANDLE__: TIM handle.
mbed_official	489:119543c9f674	1357	* @retval False (Counter used as upcounter) or True (Counter used as downcounter)
mbed_official	489:119543c9f674	1358	* @note This macro is particularly usefull to get the counting mode when the timer operates in Center-aligned mode or Encoder
mbed_official	489:119543c9f674	1359	mode.
mbed_official	489:119543c9f674	1360	*/
mbed_official	489:119543c9f674	1361	#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 & (TIM_CR1_DIR)) == (TIM_CR1_DIR))
mbed_official	489:119543c9f674	1362
mbed_official	489:119543c9f674	1363	/**
mbed_official	489:119543c9f674	1364	* @brief Sets the TIM active prescaler register value on update event.
mbed_official	489:119543c9f674	1365	* @param __HANDLE__: TIM handle.
mbed_official	489:119543c9f674	1366	* @param __PRESC__: specifies the active prescaler register new value.
mbed_official	489:119543c9f674	1367	* @retval None
mbed_official	489:119543c9f674	1368	*/
mbed_official	489:119543c9f674	1369	#define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
mbed_official	489:119543c9f674	1370
mbed_official	489:119543c9f674	1371	/**
mbed_official	489:119543c9f674	1372	* @brief Sets the TIM Capture Compare Register value on runtime without
mbed_official	489:119543c9f674	1373	* calling another time ConfigChannel function.
mbed_official	489:119543c9f674	1374	* @param __HANDLE__: TIM handle.
mbed_official	489:119543c9f674	1375	* @param __CHANNEL__ : TIM Channels to be configured.
mbed_official	489:119543c9f674	1376	* This parameter can be one of the following values:
mbed_official	489:119543c9f674	1377	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	489:119543c9f674	1378	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	489:119543c9f674	1379	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official	489:119543c9f674	1380	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official	489:119543c9f674	1381	* @param __COMPARE__: specifies the Capture Compare register new value.
mbed_official	489:119543c9f674	1382	* @retval None
mbed_official	489:119543c9f674	1383	*/
mbed_official	489:119543c9f674	1384	#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
mbed_official	489:119543c9f674	1385	((__IO uint32_t )(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)) = (__COMPARE__))
mbed_official	489:119543c9f674	1386
mbed_official	489:119543c9f674	1387	/**
mbed_official	489:119543c9f674	1388	* @brief Gets the TIM Capture Compare Register value on runtime
mbed_official	489:119543c9f674	1389	* @param __HANDLE__: TIM handle.
mbed_official	489:119543c9f674	1390	* @param __CHANNEL__ : TIM Channel associated with the capture compare register
mbed_official	489:119543c9f674	1391	* This parameter can be one of the following values:
mbed_official	489:119543c9f674	1392	* @arg TIM_CHANNEL_1: get capture/compare 1 register value
mbed_official	489:119543c9f674	1393	* @arg TIM_CHANNEL_2: get capture/compare 2 register value
mbed_official	489:119543c9f674	1394	* @arg TIM_CHANNEL_3: get capture/compare 3 register value
mbed_official	489:119543c9f674	1395	* @arg TIM_CHANNEL_4: get capture/compare 4 register value
mbed_official	489:119543c9f674	1396	* @retval None
mbed_official	489:119543c9f674	1397	*/
mbed_official	489:119543c9f674	1398	#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
mbed_official	489:119543c9f674	1399	((__IO uint32_t )(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)))
mbed_official	489:119543c9f674	1400
mbed_official	489:119543c9f674	1401	/**
mbed_official	489:119543c9f674	1402	* @brief Sets the TIM Counter Register value on runtime.
mbed_official	489:119543c9f674	1403	* @param __HANDLE__: TIM handle.
mbed_official	489:119543c9f674	1404	* @param __COUNTER__: specifies the Counter register new value.
mbed_official	489:119543c9f674	1405	* @retval None
mbed_official	489:119543c9f674	1406	*/
mbed_official	489:119543c9f674	1407	#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
mbed_official	489:119543c9f674	1408
mbed_official	489:119543c9f674	1409	/**
mbed_official	489:119543c9f674	1410	* @brief Gets the TIM Counter Register value on runtime.
mbed_official	489:119543c9f674	1411	* @param __HANDLE__: TIM handle.
mbed_official	489:119543c9f674	1412	* @retval None
mbed_official	489:119543c9f674	1413	*/
mbed_official	489:119543c9f674	1414	#define __HAL_TIM_GET_COUNTER(__HANDLE__) \
mbed_official	489:119543c9f674	1415	((__HANDLE__)->Instance->CNT)
mbed_official	489:119543c9f674	1416
mbed_official	489:119543c9f674	1417	/**
mbed_official	489:119543c9f674	1418	* @brief Sets the TIM Autoreload Register value on runtime without calling
mbed_official	489:119543c9f674	1419	* another time any Init function.
mbed_official	489:119543c9f674	1420	* @param __HANDLE__: TIM handle.
mbed_official	489:119543c9f674	1421	* @param __AUTORELOAD__: specifies the Counter register new value.
mbed_official	489:119543c9f674	1422	* @retval None
mbed_official	489:119543c9f674	1423	*/
mbed_official	489:119543c9f674	1424	#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
mbed_official	489:119543c9f674	1425	do{ \
mbed_official	489:119543c9f674	1426	(__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
mbed_official	489:119543c9f674	1427	(__HANDLE__)->Init.Period = (__AUTORELOAD__); \
mbed_official	489:119543c9f674	1428	} while(0)
mbed_official	489:119543c9f674	1429
mbed_official	489:119543c9f674	1430	/**
mbed_official	489:119543c9f674	1431	* @brief Gets the TIM Autoreload Register value on runtime
mbed_official	489:119543c9f674	1432	* @param __HANDLE__: TIM handle.
mbed_official	489:119543c9f674	1433	* @retval None
mbed_official	489:119543c9f674	1434	*/
mbed_official	489:119543c9f674	1435	#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) \
mbed_official	489:119543c9f674	1436	((__HANDLE__)->Instance->ARR)
mbed_official	489:119543c9f674	1437
mbed_official	489:119543c9f674	1438	/**
mbed_official	489:119543c9f674	1439	* @brief Sets the TIM Clock Division value on runtime without calling
mbed_official	489:119543c9f674	1440	* another time any Init function.
mbed_official	489:119543c9f674	1441	* @param __HANDLE__: TIM handle.
mbed_official	489:119543c9f674	1442	* @param __CKD__: specifies the clock division value.
mbed_official	489:119543c9f674	1443	* This parameter can be one of the following value:
mbed_official	489:119543c9f674	1444	* @arg TIM_CLOCKDIVISION_DIV1
mbed_official	489:119543c9f674	1445	* @arg TIM_CLOCKDIVISION_DIV2
mbed_official	489:119543c9f674	1446	* @arg TIM_CLOCKDIVISION_DIV4
mbed_official	489:119543c9f674	1447	* @retval None
mbed_official	489:119543c9f674	1448	*/
mbed_official	489:119543c9f674	1449	#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
mbed_official	489:119543c9f674	1450	do{ \
mbed_official	489:119543c9f674	1451	(__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD); \
mbed_official	489:119543c9f674	1452	(__HANDLE__)->Instance->CR1 \|= (__CKD__); \
mbed_official	489:119543c9f674	1453	(__HANDLE__)->Init.ClockDivision = (__CKD__); \
mbed_official	489:119543c9f674	1454	} while(0)
mbed_official	489:119543c9f674	1455
mbed_official	489:119543c9f674	1456	/**
mbed_official	489:119543c9f674	1457	* @brief Gets the TIM Clock Division value on runtime
mbed_official	489:119543c9f674	1458	* @param __HANDLE__: TIM handle.
mbed_official	489:119543c9f674	1459	* @retval None
mbed_official	489:119543c9f674	1460	*/
mbed_official	489:119543c9f674	1461	#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) \
mbed_official	489:119543c9f674	1462	((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
mbed_official	489:119543c9f674	1463
mbed_official	489:119543c9f674	1464	/**
mbed_official	489:119543c9f674	1465	* @brief Sets the TIM Input Capture prescaler on runtime without calling
mbed_official	489:119543c9f674	1466	* another time HAL_TIM_IC_ConfigChannel() function.
mbed_official	489:119543c9f674	1467	* @param __HANDLE__: TIM handle.
mbed_official	489:119543c9f674	1468	* @param __CHANNEL__ : TIM Channels to be configured.
mbed_official	489:119543c9f674	1469	* This parameter can be one of the following values:
mbed_official	489:119543c9f674	1470	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	489:119543c9f674	1471	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	489:119543c9f674	1472	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official	489:119543c9f674	1473	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official	489:119543c9f674	1474	* @param __ICPSC__: specifies the Input Capture4 prescaler new value.
mbed_official	489:119543c9f674	1475	* This parameter can be one of the following values:
mbed_official	489:119543c9f674	1476	* @arg TIM_ICPSC_DIV1: no prescaler
mbed_official	489:119543c9f674	1477	* @arg TIM_ICPSC_DIV2: capture is done once every 2 events
mbed_official	489:119543c9f674	1478	* @arg TIM_ICPSC_DIV4: capture is done once every 4 events
mbed_official	489:119543c9f674	1479	* @arg TIM_ICPSC_DIV8: capture is done once every 8 events
mbed_official	489:119543c9f674	1480	* @retval None
mbed_official	489:119543c9f674	1481	*/
mbed_official	489:119543c9f674	1482	#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
mbed_official	489:119543c9f674	1483	do{ \
mbed_official	489:119543c9f674	1484	TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \
mbed_official	489:119543c9f674	1485	TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
mbed_official	489:119543c9f674	1486	} while(0)
mbed_official	489:119543c9f674	1487
mbed_official	489:119543c9f674	1488	/**
mbed_official	489:119543c9f674	1489	* @brief Gets the TIM Input Capture prescaler on runtime
mbed_official	489:119543c9f674	1490	* @param __HANDLE__: TIM handle.
mbed_official	489:119543c9f674	1491	* @param __CHANNEL__: TIM Channels to be configured.
mbed_official	489:119543c9f674	1492	* This parameter can be one of the following values:
mbed_official	489:119543c9f674	1493	* @arg TIM_CHANNEL_1: get input capture 1 prescaler value
mbed_official	489:119543c9f674	1494	* @arg TIM_CHANNEL_2: get input capture 2 prescaler value
mbed_official	489:119543c9f674	1495	* @arg TIM_CHANNEL_3: get input capture 3 prescaler value
mbed_official	489:119543c9f674	1496	* @arg TIM_CHANNEL_4: get input capture 4 prescaler value
mbed_official	489:119543c9f674	1497	* @retval None
mbed_official	489:119543c9f674	1498	*/
mbed_official	489:119543c9f674	1499	#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \
mbed_official	489:119543c9f674	1500	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
mbed_official	489:119543c9f674	1501	((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8) :\
mbed_official	489:119543c9f674	1502	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
mbed_official	489:119543c9f674	1503	(((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8)
mbed_official	489:119543c9f674	1504
mbed_official	489:119543c9f674	1505	/**
mbed_official	489:119543c9f674	1506	* @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register
mbed_official	489:119543c9f674	1507	* @param __HANDLE__: TIM handle.
mbed_official	489:119543c9f674	1508	* @note When the USR bit of the TIMx_CR1 register is set, only counter
mbed_official	489:119543c9f674	1509	* overflow/underflow generates an update interrupt or DMA request (if
mbed_official	489:119543c9f674	1510	* enabled)
mbed_official	489:119543c9f674	1511	* @retval None
mbed_official	489:119543c9f674	1512	*/
mbed_official	489:119543c9f674	1513	#define __HAL_TIM_URS_ENABLE(__HANDLE__) \
mbed_official	489:119543c9f674	1514	((__HANDLE__)->Instance->CR1\|= (TIM_CR1_URS))
mbed_official	489:119543c9f674	1515
mbed_official	489:119543c9f674	1516	/**
mbed_official	489:119543c9f674	1517	* @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register
mbed_official	489:119543c9f674	1518	* @param __HANDLE__: TIM handle.
mbed_official	489:119543c9f674	1519	* @note When the USR bit of the TIMx_CR1 register is reset, any of the
mbed_official	489:119543c9f674	1520	* following events generate an update interrupt or DMA request (if
mbed_official	489:119543c9f674	1521	* enabled):
mbed_official	489:119543c9f674	1522	* (+) Counter overflow/underflow
mbed_official	489:119543c9f674	1523	* (+) Setting the UG bit
mbed_official	489:119543c9f674	1524	* (+) Update generation through the slave mode controller
mbed_official	489:119543c9f674	1525	* @retval None
mbed_official	489:119543c9f674	1526	*/
mbed_official	489:119543c9f674	1527	#define __HAL_TIM_URS_DISABLE(__HANDLE__) \
mbed_official	489:119543c9f674	1528	((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS))
mbed_official	489:119543c9f674	1529
mbed_official	489:119543c9f674	1530	/**
mbed_official	489:119543c9f674	1531	* @brief Sets the TIM Capture x input polarity on runtime.
mbed_official	489:119543c9f674	1532	* @param __HANDLE__: TIM handle.
mbed_official	489:119543c9f674	1533	* @param __CHANNEL__: TIM Channels to be configured.
mbed_official	489:119543c9f674	1534	* This parameter can be one of the following values:
mbed_official	489:119543c9f674	1535	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
mbed_official	489:119543c9f674	1536	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
mbed_official	489:119543c9f674	1537	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
mbed_official	489:119543c9f674	1538	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
mbed_official	489:119543c9f674	1539	* @param __POLARITY__: Polarity for TIx source
mbed_official	489:119543c9f674	1540	* @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
mbed_official	489:119543c9f674	1541	* @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
mbed_official	489:119543c9f674	1542	* @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
mbed_official	489:119543c9f674	1543	* @note The polarity TIM_INPUTCHANNELPOLARITY_BOTHEDGE is not authorized for TIM Channel 4.
mbed_official	489:119543c9f674	1544	* @retval None
mbed_official	489:119543c9f674	1545	*/
mbed_official	489:119543c9f674	1546	#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
mbed_official	489:119543c9f674	1547	do{ \
mbed_official	489:119543c9f674	1548	TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \
mbed_official	489:119543c9f674	1549	TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
mbed_official	489:119543c9f674	1550	}while(0)
mbed_official	489:119543c9f674	1551
mbed_official	489:119543c9f674	1552	/**
mbed_official	489:119543c9f674	1553	* @}
mbed_official	489:119543c9f674	1554	*/
mbed_official	489:119543c9f674	1555
mbed_official	489:119543c9f674	1556	/* Include TIM HAL Extension module */
mbed_official	489:119543c9f674	1557	#include "stm32f1xx_hal_tim_ex.h"
mbed_official	489:119543c9f674	1558
mbed_official	489:119543c9f674	1559	/* Exported functions --------------------------------------------------------*/
mbed_official	489:119543c9f674	1560	/** @addtogroup TIM_Exported_Functions
mbed_official	489:119543c9f674	1561	* @{
mbed_official	489:119543c9f674	1562	*/
mbed_official	489:119543c9f674	1563
mbed_official	489:119543c9f674	1564	/** @addtogroup TIM_Exported_Functions_Group1
mbed_official	489:119543c9f674	1565	* @{
mbed_official	489:119543c9f674	1566	*/
mbed_official	489:119543c9f674	1567	/* Time Base functions ********************************************************/
mbed_official	489:119543c9f674	1568	HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
mbed_official	489:119543c9f674	1569	HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
mbed_official	489:119543c9f674	1570	void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
mbed_official	489:119543c9f674	1571	void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
mbed_official	489:119543c9f674	1572	/* Blocking mode: Polling */
mbed_official	489:119543c9f674	1573	HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
mbed_official	489:119543c9f674	1574	HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
mbed_official	489:119543c9f674	1575	/* Non-Blocking mode: Interrupt */
mbed_official	489:119543c9f674	1576	HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
mbed_official	489:119543c9f674	1577	HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
mbed_official	489:119543c9f674	1578	/* Non-Blocking mode: DMA */
mbed_official	489:119543c9f674	1579	HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef htim, uint32_t pData, uint16_t Length);
mbed_official	489:119543c9f674	1580	HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
mbed_official	489:119543c9f674	1581	/**
mbed_official	489:119543c9f674	1582	* @}
mbed_official	489:119543c9f674	1583	*/
mbed_official	489:119543c9f674	1584
mbed_official	489:119543c9f674	1585	/** @addtogroup TIM_Exported_Functions_Group2
mbed_official	489:119543c9f674	1586	* @{
mbed_official	489:119543c9f674	1587	*/
mbed_official	489:119543c9f674	1588	/* Timer Output Compare functions **********************************************/
mbed_official	489:119543c9f674	1589	HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
mbed_official	489:119543c9f674	1590	HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
mbed_official	489:119543c9f674	1591	void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
mbed_official	489:119543c9f674	1592	void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
mbed_official	489:119543c9f674	1593	/* Blocking mode: Polling */
mbed_official	489:119543c9f674	1594	HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	489:119543c9f674	1595	HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	489:119543c9f674	1596	/* Non-Blocking mode: Interrupt */
mbed_official	489:119543c9f674	1597	HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	489:119543c9f674	1598	HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	489:119543c9f674	1599	/* Non-Blocking mode: DMA */
mbed_official	489:119543c9f674	1600	HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
mbed_official	489:119543c9f674	1601	HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	489:119543c9f674	1602
mbed_official	489:119543c9f674	1603	/**
mbed_official	489:119543c9f674	1604	* @}
mbed_official	489:119543c9f674	1605	*/
mbed_official	489:119543c9f674	1606
mbed_official	489:119543c9f674	1607	/** @addtogroup TIM_Exported_Functions_Group3
mbed_official	489:119543c9f674	1608	* @{
mbed_official	489:119543c9f674	1609	*/
mbed_official	489:119543c9f674	1610	/* Timer PWM functions *********************************************************/
mbed_official	489:119543c9f674	1611	HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
mbed_official	489:119543c9f674	1612	HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
mbed_official	489:119543c9f674	1613	void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
mbed_official	489:119543c9f674	1614	void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
mbed_official	489:119543c9f674	1615	/* Blocking mode: Polling */
mbed_official	489:119543c9f674	1616	HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	489:119543c9f674	1617	HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	489:119543c9f674	1618	/* Non-Blocking mode: Interrupt */
mbed_official	489:119543c9f674	1619	HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	489:119543c9f674	1620	HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	489:119543c9f674	1621	/* Non-Blocking mode: DMA */
mbed_official	489:119543c9f674	1622	HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
mbed_official	489:119543c9f674	1623	HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	489:119543c9f674	1624	/**
mbed_official	489:119543c9f674	1625	* @}
mbed_official	489:119543c9f674	1626	*/
mbed_official	489:119543c9f674	1627
mbed_official	489:119543c9f674	1628	/** @addtogroup TIM_Exported_Functions_Group4
mbed_official	489:119543c9f674	1629	* @{
mbed_official	489:119543c9f674	1630	*/
mbed_official	489:119543c9f674	1631	/* Timer Input Capture functions ***********************************************/
mbed_official	489:119543c9f674	1632	HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
mbed_official	489:119543c9f674	1633	HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
mbed_official	489:119543c9f674	1634	void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
mbed_official	489:119543c9f674	1635	void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
mbed_official	489:119543c9f674	1636	/* Blocking mode: Polling */
mbed_official	489:119543c9f674	1637	HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	489:119543c9f674	1638	HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	489:119543c9f674	1639	/* Non-Blocking mode: Interrupt */
mbed_official	489:119543c9f674	1640	HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	489:119543c9f674	1641	HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	489:119543c9f674	1642	/* Non-Blocking mode: DMA */
mbed_official	489:119543c9f674	1643	HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
mbed_official	489:119543c9f674	1644	HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	489:119543c9f674	1645	/**
mbed_official	489:119543c9f674	1646	* @}
mbed_official	489:119543c9f674	1647	*/
mbed_official	489:119543c9f674	1648
mbed_official	489:119543c9f674	1649	/** @addtogroup TIM_Exported_Functions_Group5
mbed_official	489:119543c9f674	1650	* @{
mbed_official	489:119543c9f674	1651	*/
mbed_official	489:119543c9f674	1652	/* Timer One Pulse functions ***************************************************/
mbed_official	489:119543c9f674	1653	HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
mbed_official	489:119543c9f674	1654	HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
mbed_official	489:119543c9f674	1655	void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
mbed_official	489:119543c9f674	1656	void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
mbed_official	489:119543c9f674	1657	/* Blocking mode: Polling */
mbed_official	489:119543c9f674	1658	HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
mbed_official	489:119543c9f674	1659	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
mbed_official	489:119543c9f674	1660	/* Non-Blocking mode: Interrupt */
mbed_official	489:119543c9f674	1661	HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
mbed_official	489:119543c9f674	1662	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
mbed_official	489:119543c9f674	1663	/**
mbed_official	489:119543c9f674	1664	* @}
mbed_official	489:119543c9f674	1665	*/
mbed_official	489:119543c9f674	1666
mbed_official	489:119543c9f674	1667	/** @addtogroup TIM_Exported_Functions_Group6
mbed_official	489:119543c9f674	1668	* @{
mbed_official	489:119543c9f674	1669	*/
mbed_official	489:119543c9f674	1670	/* Timer Encoder functions *****************************************************/
mbed_official	489:119543c9f674	1671	HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef htim, TIM_Encoder_InitTypeDef sConfig);
mbed_official	489:119543c9f674	1672	HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
mbed_official	489:119543c9f674	1673	void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
mbed_official	489:119543c9f674	1674	void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
mbed_official	489:119543c9f674	1675	/* Blocking mode: Polling */
mbed_official	489:119543c9f674	1676	HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	489:119543c9f674	1677	HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	489:119543c9f674	1678	/* Non-Blocking mode: Interrupt */
mbed_official	489:119543c9f674	1679	HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	489:119543c9f674	1680	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	489:119543c9f674	1681	/* Non-Blocking mode: DMA */
mbed_official	489:119543c9f674	1682	HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData1, uint32_t *pData2, uint16_t Length);
mbed_official	489:119543c9f674	1683	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	489:119543c9f674	1684
mbed_official	489:119543c9f674	1685	/**
mbed_official	489:119543c9f674	1686	* @}
mbed_official	489:119543c9f674	1687	*/
mbed_official	489:119543c9f674	1688
mbed_official	489:119543c9f674	1689	/** @addtogroup TIM_Exported_Functions_Group7
mbed_official	489:119543c9f674	1690	* @{
mbed_official	489:119543c9f674	1691	*/
mbed_official	489:119543c9f674	1692	/* Interrupt Handler functions **********************************************/
mbed_official	489:119543c9f674	1693	void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
mbed_official	489:119543c9f674	1694	/**
mbed_official	489:119543c9f674	1695	* @}
mbed_official	489:119543c9f674	1696	*/
mbed_official	489:119543c9f674	1697
mbed_official	489:119543c9f674	1698	/** @addtogroup TIM_Exported_Functions_Group8
mbed_official	489:119543c9f674	1699	* @{
mbed_official	489:119543c9f674	1700	*/
mbed_official	489:119543c9f674	1701	/* Control functions *********************************************************/
mbed_official	489:119543c9f674	1702	HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef htim, TIM_OC_InitTypeDef sConfig, uint32_t Channel);
mbed_official	489:119543c9f674	1703	HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef htim, TIM_OC_InitTypeDef sConfig, uint32_t Channel);
mbed_official	489:119543c9f674	1704	HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef htim, TIM_IC_InitTypeDef sConfig, uint32_t Channel);
mbed_official	489:119543c9f674	1705	HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef htim, TIM_OnePulse_InitTypeDef sConfig, uint32_t OutputChannel, uint32_t InputChannel);
mbed_official	489:119543c9f674	1706	HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef htim, TIM_ClearInputConfigTypeDef sClearInputConfig, uint32_t Channel);
mbed_official	489:119543c9f674	1707	HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef htim, TIM_ClockConfigTypeDef sClockSourceConfig);
mbed_official	489:119543c9f674	1708	HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
mbed_official	489:119543c9f674	1709	HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef htim, TIM_SlaveConfigTypeDef sSlaveConfig);
mbed_official	489:119543c9f674	1710	HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef htim, TIM_SlaveConfigTypeDef sSlaveConfig);
mbed_official	489:119543c9f674	1711	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
mbed_official	489:119543c9f674	1712	uint32_t *BurstBuffer, uint32_t BurstLength);
mbed_official	489:119543c9f674	1713	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
mbed_official	489:119543c9f674	1714	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
mbed_official	489:119543c9f674	1715	uint32_t *BurstBuffer, uint32_t BurstLength);
mbed_official	489:119543c9f674	1716	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
mbed_official	489:119543c9f674	1717	HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
mbed_official	489:119543c9f674	1718	uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
mbed_official	489:119543c9f674	1719
mbed_official	489:119543c9f674	1720	/**
mbed_official	489:119543c9f674	1721	* @}
mbed_official	489:119543c9f674	1722	*/
mbed_official	489:119543c9f674	1723
mbed_official	489:119543c9f674	1724	/** @addtogroup TIM_Exported_Functions_Group9
mbed_official	489:119543c9f674	1725	* @{
mbed_official	489:119543c9f674	1726	*/
mbed_official	489:119543c9f674	1727	/* Callback in non blocking modes (Interrupt and DMA) *************************/
mbed_official	489:119543c9f674	1728	void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
mbed_official	489:119543c9f674	1729	void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
mbed_official	489:119543c9f674	1730	void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
mbed_official	489:119543c9f674	1731	void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
mbed_official	489:119543c9f674	1732	void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
mbed_official	489:119543c9f674	1733	void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
mbed_official	489:119543c9f674	1734	/**
mbed_official	489:119543c9f674	1735	* @}
mbed_official	489:119543c9f674	1736	*/
mbed_official	489:119543c9f674	1737
mbed_official	489:119543c9f674	1738	/** @addtogroup TIM_Exported_Functions_Group10
mbed_official	489:119543c9f674	1739	* @{
mbed_official	489:119543c9f674	1740	*/
mbed_official	489:119543c9f674	1741	/* Peripheral State functions **************************************************/
mbed_official	489:119543c9f674	1742	HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
mbed_official	489:119543c9f674	1743	HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
mbed_official	489:119543c9f674	1744	HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
mbed_official	489:119543c9f674	1745	HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
mbed_official	489:119543c9f674	1746	HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
mbed_official	489:119543c9f674	1747	HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
mbed_official	489:119543c9f674	1748
mbed_official	489:119543c9f674	1749	/**
mbed_official	489:119543c9f674	1750	* @}
mbed_official	489:119543c9f674	1751	*/
mbed_official	489:119543c9f674	1752
mbed_official	489:119543c9f674	1753	/**
mbed_official	489:119543c9f674	1754	* @}
mbed_official	489:119543c9f674	1755	*/
mbed_official	489:119543c9f674	1756
mbed_official	489:119543c9f674	1757	/**
mbed_official	489:119543c9f674	1758	* @}
mbed_official	489:119543c9f674	1759	*/
mbed_official	489:119543c9f674	1760
mbed_official	489:119543c9f674	1761	/**
mbed_official	489:119543c9f674	1762	* @}
mbed_official	489:119543c9f674	1763	*/
mbed_official	489:119543c9f674	1764
mbed_official	489:119543c9f674	1765	#ifdef __cplusplus
mbed_official	489:119543c9f674	1766	}
mbed_official	489:119543c9f674	1767	#endif
mbed_official	489:119543c9f674	1768
mbed_official	489:119543c9f674	1769	#endif /* __STM32F1xx_HAL_TIM_H */
mbed_official	489:119543c9f674	1770
mbed_official	489:119543c9f674	1771	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/