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targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_rcc_ex.h@581:39197bcd20f2, 2015-07-02 (annotated)

Committer:: mbed_official
Date:: Thu Jul 02 16:30:08 2015 +0100
Revision:: 581:39197bcd20f2
Parent:: 489:119543c9f674

Synchronized with git revision ae2d3cdffe70184eb8736d94f76c45c93f4b7724

Full URL: https://github.com/mbedmicro/mbed/commit/ae2d3cdffe70184eb8736d94f76c45c93f4b7724/

Make it possible to build the core mbed library with yotta

Who changed what in which revision?

User	Revision	Line number	New contents of line
mbed_official	489:119543c9f674	1	/**
mbed_official	489:119543c9f674	2	******************************************************************************
mbed_official	489:119543c9f674	3	* @file stm32f1xx_hal_rcc_ex.h
mbed_official	489:119543c9f674	4	* @author MCD Application Team
mbed_official	489:119543c9f674	5	* @version V1.0.0
mbed_official	489:119543c9f674	6	* @date 15-December-2014
mbed_official	489:119543c9f674	7	* @brief Header file of RCC HAL Extension module.
mbed_official	489:119543c9f674	8	******************************************************************************
mbed_official	489:119543c9f674	9	* @attention
mbed_official	489:119543c9f674	10	*
mbed_official	489:119543c9f674	11	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
mbed_official	489:119543c9f674	12	*
mbed_official	489:119543c9f674	13	* Redistribution and use in source and binary forms, with or without modification,
mbed_official	489:119543c9f674	14	* are permitted provided that the following conditions are met:
mbed_official	489:119543c9f674	15	* 1. Redistributions of source code must retain the above copyright notice,
mbed_official	489:119543c9f674	16	* this list of conditions and the following disclaimer.
mbed_official	489:119543c9f674	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official	489:119543c9f674	18	* this list of conditions and the following disclaimer in the documentation
mbed_official	489:119543c9f674	19	* and/or other materials provided with the distribution.
mbed_official	489:119543c9f674	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official	489:119543c9f674	21	* may be used to endorse or promote products derived from this software
mbed_official	489:119543c9f674	22	* without specific prior written permission.
mbed_official	489:119543c9f674	23	*
mbed_official	489:119543c9f674	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official	489:119543c9f674	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official	489:119543c9f674	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official	489:119543c9f674	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official	489:119543c9f674	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official	489:119543c9f674	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official	489:119543c9f674	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official	489:119543c9f674	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official	489:119543c9f674	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official	489:119543c9f674	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official	489:119543c9f674	34	*
mbed_official	489:119543c9f674	35	******************************************************************************
mbed_official	489:119543c9f674	36	*/
mbed_official	489:119543c9f674	37
mbed_official	489:119543c9f674	38	/* Define to prevent recursive inclusion -------------------------------------*/
mbed_official	489:119543c9f674	39	#ifndef __STM32F1xx_HAL_RCC_EX_H
mbed_official	489:119543c9f674	40	#define __STM32F1xx_HAL_RCC_EX_H
mbed_official	489:119543c9f674	41
mbed_official	489:119543c9f674	42	#ifdef __cplusplus
mbed_official	489:119543c9f674	43	extern "C" {
mbed_official	489:119543c9f674	44	#endif
mbed_official	489:119543c9f674	45
mbed_official	489:119543c9f674	46	/* Includes ------------------------------------------------------------------*/
mbed_official	489:119543c9f674	47	#include "stm32f1xx_hal_def.h"
mbed_official	489:119543c9f674	48
mbed_official	489:119543c9f674	49	/** @addtogroup STM32F1xx_HAL_Driver
mbed_official	489:119543c9f674	50	* @{
mbed_official	489:119543c9f674	51	*/
mbed_official	489:119543c9f674	52
mbed_official	489:119543c9f674	53	/** @addtogroup RCCEx
mbed_official	489:119543c9f674	54	* @{
mbed_official	489:119543c9f674	55	*/
mbed_official	489:119543c9f674	56
mbed_official	489:119543c9f674	57	/** @addtogroup RCCEx_Private_Constants
mbed_official	489:119543c9f674	58	* @{
mbed_official	489:119543c9f674	59	*/
mbed_official	489:119543c9f674	60
mbed_official	489:119543c9f674	61	#if defined(STM32F105xC) \|\| defined(STM32F107xC)
mbed_official	489:119543c9f674	62
mbed_official	489:119543c9f674	63	/* Alias word address of PLLI2SON bit */
mbed_official	489:119543c9f674	64	#define PLLI2SON_BITNUMBER POSITION_VAL(RCC_CR_PLL3ON)
mbed_official	489:119543c9f674	65	#define RCC_CR_PLLI2SON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (PLLI2SON_BITNUMBER * 4)))
mbed_official	489:119543c9f674	66
mbed_official	489:119543c9f674	67	/** @defgroup RCCEx_PLL_Timeout PLL I2S Timeout
mbed_official	489:119543c9f674	68	* @{
mbed_official	489:119543c9f674	69	*/
mbed_official	489:119543c9f674	70	#define PLLI2S_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
mbed_official	489:119543c9f674	71	/**
mbed_official	489:119543c9f674	72	* @}
mbed_official	489:119543c9f674	73	*/
mbed_official	489:119543c9f674	74
mbed_official	489:119543c9f674	75	#endif /* STM32F105xC \|\| STM32F107xC */
mbed_official	489:119543c9f674	76
mbed_official	489:119543c9f674	77	#define CR_REG_INDEX ((uint8_t)1)
mbed_official	489:119543c9f674	78
mbed_official	489:119543c9f674	79	/**
mbed_official	489:119543c9f674	80	* @}
mbed_official	489:119543c9f674	81	*/
mbed_official	489:119543c9f674	82
mbed_official	489:119543c9f674	83	/** @addtogroup RCCEx_Private_Macros
mbed_official	489:119543c9f674	84	* @{
mbed_official	489:119543c9f674	85	*/
mbed_official	489:119543c9f674	86
mbed_official	489:119543c9f674	87	#if defined(STM32F105xC) \|\| defined(STM32F107xC)
mbed_official	489:119543c9f674	88	#define IS_RCC_PREDIV1_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_PREDIV1_SOURCE_HSE) \|\| \
mbed_official	489:119543c9f674	89	((__SOURCE__) == RCC_PREDIV1_SOURCE_PLL2))
mbed_official	489:119543c9f674	90	#endif /* STM32F105xC \|\| STM32F107xC */
mbed_official	489:119543c9f674	91
mbed_official	489:119543c9f674	92	#if defined(STM32F105xC) \|\| defined(STM32F107xC) \|\| defined (STM32F100xB) \|\| defined (STM32F100xE)
mbed_official	489:119543c9f674	93	#define IS_RCC_HSE_PREDIV(__DIV__) (((__DIV__) == RCC_HSE_PREDIV_DIV1) \|\| ((__DIV__) == RCC_HSE_PREDIV_DIV2) \|\| \
mbed_official	489:119543c9f674	94	((__DIV__) == RCC_HSE_PREDIV_DIV3) \|\| ((__DIV__) == RCC_HSE_PREDIV_DIV4) \|\| \
mbed_official	489:119543c9f674	95	((__DIV__) == RCC_HSE_PREDIV_DIV5) \|\| ((__DIV__) == RCC_HSE_PREDIV_DIV6) \|\| \
mbed_official	489:119543c9f674	96	((__DIV__) == RCC_HSE_PREDIV_DIV7) \|\| ((__DIV__) == RCC_HSE_PREDIV_DIV8) \|\| \
mbed_official	489:119543c9f674	97	((__DIV__) == RCC_HSE_PREDIV_DIV9) \|\| ((__DIV__) == RCC_HSE_PREDIV_DIV10) \|\| \
mbed_official	489:119543c9f674	98	((__DIV__) == RCC_HSE_PREDIV_DIV11) \|\| ((__DIV__) == RCC_HSE_PREDIV_DIV12) \|\| \
mbed_official	489:119543c9f674	99	((__DIV__) == RCC_HSE_PREDIV_DIV13) \|\| ((__DIV__) == RCC_HSE_PREDIV_DIV14) \|\| \
mbed_official	489:119543c9f674	100	((__DIV__) == RCC_HSE_PREDIV_DIV15) \|\| ((__DIV__) == RCC_HSE_PREDIV_DIV16))
mbed_official	489:119543c9f674	101
mbed_official	489:119543c9f674	102	#else
mbed_official	489:119543c9f674	103	#define IS_RCC_HSE_PREDIV(__DIV__) (((__DIV__) == RCC_HSE_PREDIV_DIV1) \|\| ((__DIV__) == RCC_HSE_PREDIV_DIV2))
mbed_official	489:119543c9f674	104	#endif /* STM32F105xC \|\| STM32F107xC \|\| STM32F100xB \|\| STM32F100xE */
mbed_official	489:119543c9f674	105
mbed_official	489:119543c9f674	106	#if defined(STM32F105xC) \|\| defined(STM32F107xC)
mbed_official	489:119543c9f674	107	#define IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLL_MUL4) \|\| ((__MUL__) == RCC_PLL_MUL5) \|\| \
mbed_official	489:119543c9f674	108	((__MUL__) == RCC_PLL_MUL6) \|\| ((__MUL__) == RCC_PLL_MUL7) \|\| \
mbed_official	489:119543c9f674	109	((__MUL__) == RCC_PLL_MUL8) \|\| ((__MUL__) == RCC_PLL_MUL9) \|\| \
mbed_official	489:119543c9f674	110	((__MUL__) == RCC_PLL_MUL6_5))
mbed_official	489:119543c9f674	111
mbed_official	489:119543c9f674	112	#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) \|\| ((__SOURCE__) == RCC_MCO1SOURCE_HSI) \
mbed_official	489:119543c9f674	113	\|\| ((__SOURCE__) == RCC_MCO1SOURCE_HSE) \|\| ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) \
mbed_official	489:119543c9f674	114	\|\| ((__SOURCE__) == RCC_MCO1SOURCE_PLL2CLK) \|\| ((__SOURCE__) == RCC_MCO1SOURCE_PLL3CLK) \
mbed_official	489:119543c9f674	115	\|\| ((__SOURCE__) == RCC_MCO1SOURCE_PLL3CLK_DIV2) \|\| ((__SOURCE__) == RCC_MCO1SOURCE_EXT_HSE) \
mbed_official	489:119543c9f674	116	\|\| ((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK))
mbed_official	489:119543c9f674	117
mbed_official	489:119543c9f674	118	#else
mbed_official	489:119543c9f674	119	#define IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLL_MUL2) \|\| ((__MUL__) == RCC_PLL_MUL3) \|\| \
mbed_official	489:119543c9f674	120	((__MUL__) == RCC_PLL_MUL4) \|\| ((__MUL__) == RCC_PLL_MUL5) \|\| \
mbed_official	489:119543c9f674	121	((__MUL__) == RCC_PLL_MUL6) \|\| ((__MUL__) == RCC_PLL_MUL7) \|\| \
mbed_official	489:119543c9f674	122	((__MUL__) == RCC_PLL_MUL8) \|\| ((__MUL__) == RCC_PLL_MUL9) \|\| \
mbed_official	489:119543c9f674	123	((__MUL__) == RCC_PLL_MUL10) \|\| ((__MUL__) == RCC_PLL_MUL11) \|\| \
mbed_official	489:119543c9f674	124	((__MUL__) == RCC_PLL_MUL12) \|\| ((__MUL__) == RCC_PLL_MUL13) \|\| \
mbed_official	489:119543c9f674	125	((__MUL__) == RCC_PLL_MUL14) \|\| ((__MUL__) == RCC_PLL_MUL15) \|\| \
mbed_official	489:119543c9f674	126	((__MUL__) == RCC_PLL_MUL16))
mbed_official	489:119543c9f674	127
mbed_official	489:119543c9f674	128	#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) \|\| ((__SOURCE__) == RCC_MCO1SOURCE_HSI) \
mbed_official	489:119543c9f674	129	\|\| ((__SOURCE__) == RCC_MCO1SOURCE_HSE) \|\| ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) \
mbed_official	489:119543c9f674	130	\|\| ((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK))
mbed_official	489:119543c9f674	131
mbed_official	489:119543c9f674	132	#endif /* STM32F105xC \|\| STM32F107xC*/
mbed_official	489:119543c9f674	133
mbed_official	489:119543c9f674	134	#define IS_RCC_ADCPLLCLK_DIV(__ADCCLK__) (((__ADCCLK__) == RCC_ADCPCLK2_DIV2) \|\| ((__ADCCLK__) == RCC_ADCPCLK2_DIV4) \|\| \
mbed_official	489:119543c9f674	135	((__ADCCLK__) == RCC_ADCPCLK2_DIV6) \|\| ((__ADCCLK__) == RCC_ADCPCLK2_DIV8))
mbed_official	489:119543c9f674	136
mbed_official	489:119543c9f674	137	#if defined(STM32F105xC) \|\| defined(STM32F107xC)
mbed_official	489:119543c9f674	138	#define IS_RCC_I2S2CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2S2CLKSOURCE_SYSCLK) \|\| ((__SOURCE__) == RCC_I2S2CLKSOURCE_PLLI2S_VCO))
mbed_official	489:119543c9f674	139
mbed_official	489:119543c9f674	140	#define IS_RCC_I2S3CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2S3CLKSOURCE_SYSCLK) \|\| ((__SOURCE__) == RCC_I2S3CLKSOURCE_PLLI2S_VCO))
mbed_official	489:119543c9f674	141
mbed_official	489:119543c9f674	142	#define IS_RCC_USBPLLCLK_DIV(__USBCLK__) (((__USBCLK__) == RCC_USBPLLCLK_DIV2) \|\| ((__USBCLK__) == RCC_USBPLLCLK_DIV3))
mbed_official	489:119543c9f674	143
mbed_official	489:119543c9f674	144	#define IS_RCC_PLLI2S_MUL(__MUL__) (((__MUL__) == RCC_PLLI2S_MUL8) \|\| ((__MUL__) == RCC_PLLI2S_MUL9) \|\| \
mbed_official	489:119543c9f674	145	((__MUL__) == RCC_PLLI2S_MUL10) \|\| ((__MUL__) == RCC_PLLI2S_MUL11) \|\| \
mbed_official	489:119543c9f674	146	((__MUL__) == RCC_PLLI2S_MUL12) \|\| ((__MUL__) == RCC_PLLI2S_MUL13) \|\| \
mbed_official	489:119543c9f674	147	((__MUL__) == RCC_PLLI2S_MUL14) \|\| ((__MUL__) == RCC_PLLI2S_MUL16) \|\| \
mbed_official	489:119543c9f674	148	((__MUL__) == RCC_PLLI2S_MUL20))
mbed_official	489:119543c9f674	149
mbed_official	489:119543c9f674	150	#define IS_RCC_HSE_PREDIV2(__DIV__) (((__DIV__) == RCC_HSE_PREDIV2_DIV1) \|\| ((__DIV__) == RCC_HSE_PREDIV2_DIV2) \|\| \
mbed_official	489:119543c9f674	151	((__DIV__) == RCC_HSE_PREDIV2_DIV3) \|\| ((__DIV__) == RCC_HSE_PREDIV2_DIV4) \|\| \
mbed_official	489:119543c9f674	152	((__DIV__) == RCC_HSE_PREDIV2_DIV5) \|\| ((__DIV__) == RCC_HSE_PREDIV2_DIV6) \|\| \
mbed_official	489:119543c9f674	153	((__DIV__) == RCC_HSE_PREDIV2_DIV7) \|\| ((__DIV__) == RCC_HSE_PREDIV2_DIV8) \|\| \
mbed_official	489:119543c9f674	154	((__DIV__) == RCC_HSE_PREDIV2_DIV9) \|\| ((__DIV__) == RCC_HSE_PREDIV2_DIV10) \|\| \
mbed_official	489:119543c9f674	155	((__DIV__) == RCC_HSE_PREDIV2_DIV11) \|\| ((__DIV__) == RCC_HSE_PREDIV2_DIV12) \|\| \
mbed_official	489:119543c9f674	156	((__DIV__) == RCC_HSE_PREDIV2_DIV13) \|\| ((__DIV__) == RCC_HSE_PREDIV2_DIV14) \|\| \
mbed_official	489:119543c9f674	157	((__DIV__) == RCC_HSE_PREDIV2_DIV15) \|\| ((__DIV__) == RCC_HSE_PREDIV2_DIV16))
mbed_official	489:119543c9f674	158
mbed_official	489:119543c9f674	159	#define IS_RCC_PLL2(__PLL__) (((__PLL__) == RCC_PLL2_NONE) \|\| ((__PLL__) == RCC_PLL2_OFF) \|\| \
mbed_official	489:119543c9f674	160	((__PLL__) == RCC_PLL2_ON))
mbed_official	489:119543c9f674	161
mbed_official	489:119543c9f674	162	#define IS_RCC_PLL2_MUL(__MUL__) (((__MUL__) == RCC_PLL2_MUL8) \|\| ((__MUL__) == RCC_PLL2_MUL9) \|\| \
mbed_official	489:119543c9f674	163	((__MUL__) == RCC_PLL2_MUL10) \|\| ((__MUL__) == RCC_PLL2_MUL11) \|\| \
mbed_official	489:119543c9f674	164	((__MUL__) == RCC_PLL2_MUL12) \|\| ((__MUL__) == RCC_PLL2_MUL13) \|\| \
mbed_official	489:119543c9f674	165	((__MUL__) == RCC_PLL2_MUL14) \|\| ((__MUL__) == RCC_PLL2_MUL16) \|\| \
mbed_official	489:119543c9f674	166	((__MUL__) == RCC_PLL2_MUL20))
mbed_official	489:119543c9f674	167
mbed_official	489:119543c9f674	168	#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
mbed_official	489:119543c9f674	169	((((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) \|\| \
mbed_official	489:119543c9f674	170	(((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) \|\| \
mbed_official	489:119543c9f674	171	(((__SELECTION__) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2) \|\| \
mbed_official	489:119543c9f674	172	(((__SELECTION__) & RCC_PERIPHCLK_I2S3) == RCC_PERIPHCLK_I2S3) \|\| \
mbed_official	489:119543c9f674	173	(((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB))
mbed_official	489:119543c9f674	174
mbed_official	489:119543c9f674	175	#elif defined(STM32F103xE) \|\| defined(STM32F103xG)
mbed_official	489:119543c9f674	176
mbed_official	489:119543c9f674	177	#define IS_RCC_I2S2CLKSOURCE(__SOURCE__) ((__SOURCE__) == RCC_I2S2CLKSOURCE_SYSCLK)
mbed_official	489:119543c9f674	178
mbed_official	489:119543c9f674	179	#define IS_RCC_I2S3CLKSOURCE(__SOURCE__) ((__SOURCE__) == RCC_I2S3CLKSOURCE_SYSCLK)
mbed_official	489:119543c9f674	180
mbed_official	489:119543c9f674	181	#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
mbed_official	489:119543c9f674	182	((((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) \|\| \
mbed_official	489:119543c9f674	183	(((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) \|\| \
mbed_official	489:119543c9f674	184	(((__SELECTION__) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2) \|\| \
mbed_official	489:119543c9f674	185	(((__SELECTION__) & RCC_PERIPHCLK_I2S3) == RCC_PERIPHCLK_I2S3) \|\| \
mbed_official	489:119543c9f674	186	(((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB))
mbed_official	489:119543c9f674	187
mbed_official	489:119543c9f674	188
mbed_official	489:119543c9f674	189	#elif defined(STM32F102x6) \|\| defined(STM32F102xB) \|\| defined(STM32F103x6) \|\| defined(STM32F103xB)
mbed_official	489:119543c9f674	190
mbed_official	489:119543c9f674	191	#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
mbed_official	489:119543c9f674	192	((((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) \|\| \
mbed_official	489:119543c9f674	193	(((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) \|\| \
mbed_official	489:119543c9f674	194	(((__SELECTION__) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB))
mbed_official	489:119543c9f674	195
mbed_official	489:119543c9f674	196	#else
mbed_official	489:119543c9f674	197
mbed_official	489:119543c9f674	198	#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
mbed_official	489:119543c9f674	199	((((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) \|\| \
mbed_official	489:119543c9f674	200	(((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC))
mbed_official	489:119543c9f674	201
mbed_official	489:119543c9f674	202	#endif /* STM32F105xC \|\| STM32F107xC */
mbed_official	489:119543c9f674	203
mbed_official	489:119543c9f674	204	#if defined(STM32F102x6) \|\| defined(STM32F102xB) \|\| defined(STM32F103x6) \|\| defined(STM32F103xB) \|\| defined(STM32F103xE) \|\| defined(STM32F103xG)
mbed_official	489:119543c9f674	205
mbed_official	489:119543c9f674	206	#define IS_RCC_USBPLLCLK_DIV(__USBCLK__) (((__USBCLK__) == RCC_USBPLLCLK_DIV1) \|\| ((__USBCLK__) == RCC_USBPLLCLK_DIV1_5))
mbed_official	489:119543c9f674	207
mbed_official	489:119543c9f674	208	#endif /* STM32F102x6 \|\| STM32F102xB \|\| STM32F103x6 \|\| STM32F103xB \|\| STM32F103xE \|\| STM32F103xG */
mbed_official	489:119543c9f674	209
mbed_official	489:119543c9f674	210	/**
mbed_official	489:119543c9f674	211	* @}
mbed_official	489:119543c9f674	212	*/
mbed_official	489:119543c9f674	213
mbed_official	489:119543c9f674	214	/* Exported types ------------------------------------------------------------*/
mbed_official	489:119543c9f674	215
mbed_official	489:119543c9f674	216	/** @defgroup RCCEx_Exported_Types RCCEx Exported Types
mbed_official	489:119543c9f674	217	* @{
mbed_official	489:119543c9f674	218	*/
mbed_official	489:119543c9f674	219
mbed_official	489:119543c9f674	220	#if defined(STM32F105xC) \|\| defined(STM32F107xC)
mbed_official	489:119543c9f674	221	/**
mbed_official	489:119543c9f674	222	* @brief RCC PLL2 configuration structure definition
mbed_official	489:119543c9f674	223	*/
mbed_official	489:119543c9f674	224	typedef struct
mbed_official	489:119543c9f674	225	{
mbed_official	489:119543c9f674	226	uint32_t PLL2State; /*!< The new state of the PLL2.
mbed_official	489:119543c9f674	227	This parameter can be a value of @ref RCCEx_PLL2_Config */
mbed_official	489:119543c9f674	228
mbed_official	489:119543c9f674	229	uint32_t PLL2MUL; /*!< PLL2MUL: Multiplication factor for PLL2 VCO input clock
mbed_official	489:119543c9f674	230	This parameter must be a value of @ref RCCEx_PLL2_Multiplication_Factor*/
mbed_official	489:119543c9f674	231
mbed_official	489:119543c9f674	232	#if defined(STM32F105xC) \|\| defined(STM32F107xC)
mbed_official	489:119543c9f674	233	uint32_t HSEPrediv2Value; /*!< The Prediv2 factor value.
mbed_official	489:119543c9f674	234	This parameter can be a value of @ref RCCEx_Prediv2_Factor */
mbed_official	489:119543c9f674	235
mbed_official	489:119543c9f674	236	#endif /* STM32F105xC \|\| STM32F107xC */
mbed_official	489:119543c9f674	237	} RCC_PLL2InitTypeDef;
mbed_official	489:119543c9f674	238
mbed_official	489:119543c9f674	239	#endif /* STM32F105xC \|\| STM32F107xC */
mbed_official	489:119543c9f674	240
mbed_official	489:119543c9f674	241	/**
mbed_official	489:119543c9f674	242	* @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
mbed_official	489:119543c9f674	243	*/
mbed_official	489:119543c9f674	244	typedef struct
mbed_official	489:119543c9f674	245	{
mbed_official	489:119543c9f674	246	uint32_t OscillatorType; /*!< The oscillators to be configured.
mbed_official	489:119543c9f674	247	This parameter can be a value of @ref RCC_Oscillator_Type */
mbed_official	489:119543c9f674	248
mbed_official	489:119543c9f674	249	#if defined(STM32F105xC) \|\| defined(STM32F107xC)
mbed_official	489:119543c9f674	250	uint32_t Prediv1Source; /*!< The Prediv1 source value.
mbed_official	489:119543c9f674	251	This parameter can be a value of @ref RCCEx_Prediv1_Source */
mbed_official	489:119543c9f674	252	#endif /* STM32F105xC \|\| STM32F107xC */
mbed_official	489:119543c9f674	253
mbed_official	489:119543c9f674	254	uint32_t HSEState; /*!< The new state of the HSE.
mbed_official	489:119543c9f674	255	This parameter can be a value of @ref __HAL_RCC_HSE_CONFIG */
mbed_official	489:119543c9f674	256
mbed_official	489:119543c9f674	257	uint32_t HSEPredivValue; /*!< The Prediv1 factor value (named PREDIV1 or PLLXTPRE in RM)
mbed_official	489:119543c9f674	258	This parameter can be a value of @ref RCCEx_Prediv1_Factor */
mbed_official	489:119543c9f674	259
mbed_official	489:119543c9f674	260	uint32_t LSEState; /*!< The new state of the LSE.
mbed_official	489:119543c9f674	261	This parameter can be a value of @ref __HAL_RCC_LSE_CONFIG */
mbed_official	489:119543c9f674	262
mbed_official	489:119543c9f674	263	uint32_t HSIState; /*!< The new state of the HSI.
mbed_official	489:119543c9f674	264	This parameter can be a value of @ref RCC_HSI_Config */
mbed_official	489:119543c9f674	265
mbed_official	489:119543c9f674	266	uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
mbed_official	489:119543c9f674	267	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
mbed_official	489:119543c9f674	268
mbed_official	489:119543c9f674	269	uint32_t LSIState; /*!< The new state of the LSI.
mbed_official	489:119543c9f674	270	This parameter can be a value of @ref RCC_LSI_Config */
mbed_official	489:119543c9f674	271
mbed_official	489:119543c9f674	272	RCC_PLLInitTypeDef PLL; /!< PLL structure parameters /
mbed_official	489:119543c9f674	273
mbed_official	489:119543c9f674	274	#if defined(STM32F105xC) \|\| defined(STM32F107xC)
mbed_official	489:119543c9f674	275	RCC_PLL2InitTypeDef PLL2; /!< PLL2 structure parameters /
mbed_official	489:119543c9f674	276	#endif /* STM32F105xC \|\| STM32F107xC */
mbed_official	489:119543c9f674	277	} RCC_OscInitTypeDef;
mbed_official	489:119543c9f674	278
mbed_official	489:119543c9f674	279	#if defined(STM32F105xC) \|\| defined(STM32F107xC)
mbed_official	489:119543c9f674	280	/**
mbed_official	489:119543c9f674	281	* @brief RCC PLLI2S configuration structure definition
mbed_official	489:119543c9f674	282	*/
mbed_official	489:119543c9f674	283	typedef struct
mbed_official	489:119543c9f674	284	{
mbed_official	489:119543c9f674	285	uint32_t PLLI2SMUL; /*!< PLLI2SMUL: Multiplication factor for PLLI2S VCO input clock
mbed_official	489:119543c9f674	286	This parameter must be a value of @ref RCCEx_PLLI2S_Multiplication_Factor*/
mbed_official	489:119543c9f674	287
mbed_official	489:119543c9f674	288	#if defined(STM32F105xC) \|\| defined(STM32F107xC)
mbed_official	489:119543c9f674	289	uint32_t HSEPrediv2Value; /*!< The Prediv2 factor value.
mbed_official	489:119543c9f674	290	This parameter can be a value of @ref RCCEx_Prediv2_Factor */
mbed_official	489:119543c9f674	291
mbed_official	489:119543c9f674	292	#endif /* STM32F105xC \|\| STM32F107xC */
mbed_official	489:119543c9f674	293	} RCC_PLLI2SInitTypeDef;
mbed_official	489:119543c9f674	294	#endif /* STM32F105xC \|\| STM32F107xC */
mbed_official	489:119543c9f674	295
mbed_official	489:119543c9f674	296	/**
mbed_official	489:119543c9f674	297	* @brief RCC extended clocks structure definition
mbed_official	489:119543c9f674	298	*/
mbed_official	489:119543c9f674	299	typedef struct
mbed_official	489:119543c9f674	300	{
mbed_official	489:119543c9f674	301	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
mbed_official	489:119543c9f674	302	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
mbed_official	489:119543c9f674	303
mbed_official	489:119543c9f674	304	uint32_t RTCClockSelection; /*!< specifies the RTC clock source.
mbed_official	489:119543c9f674	305	This parameter can be a value of @ref RCC_RTC_Clock_Source */
mbed_official	489:119543c9f674	306
mbed_official	489:119543c9f674	307	uint32_t AdcClockSelection; /*!< ADC clock source
mbed_official	489:119543c9f674	308	This parameter can be a value of @ref RCCEx_ADC_Prescaler */
mbed_official	489:119543c9f674	309
mbed_official	489:119543c9f674	310	#if defined (STM32F103xE) \|\| defined (STM32F103xG) \|\| defined (STM32F105xC) \|\| defined (STM32F107xC)
mbed_official	489:119543c9f674	311	uint32_t I2s2ClockSelection; /*!< I2S2 clock source
mbed_official	489:119543c9f674	312	This parameter can be a value of @ref RCCEx_I2S2_Clock_Source */
mbed_official	489:119543c9f674	313
mbed_official	489:119543c9f674	314	uint32_t I2s3ClockSelection; /*!< I2S3 clock source
mbed_official	489:119543c9f674	315	This parameter can be a value of @ref RCCEx_I2S3_Clock_Source */
mbed_official	489:119543c9f674	316
mbed_official	489:119543c9f674	317	#if defined (STM32F105xC) \|\| defined (STM32F107xC)
mbed_official	489:119543c9f674	318	RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters
mbed_official	489:119543c9f674	319	This parameter will be used only when PLLI2S is selected as Clock Source I2S2 or I2S3 */
mbed_official	489:119543c9f674	320
mbed_official	489:119543c9f674	321	#endif /* STM32F105xC \|\| STM32F107xC */
mbed_official	489:119543c9f674	322	#endif /* STM32F103xE \|\| STM32F103xG \|\| STM32F105xC \|\| STM32F107xC */
mbed_official	489:119543c9f674	323
mbed_official	489:119543c9f674	324	#if defined(STM32F102x6) \|\| defined(STM32F102xB) \|\| defined(STM32F103x6) \|\| defined(STM32F103xB) \|\| defined(STM32F103xE) \|\| \
mbed_official	489:119543c9f674	325	defined(STM32F103xG) \|\| defined(STM32F105xC) \|\| defined(STM32F107xC)
mbed_official	489:119543c9f674	326	uint32_t UsbClockSelection; /*!< USB clock source
mbed_official	489:119543c9f674	327	This parameter can be a value of @ref RCCEx_USB_Prescaler */
mbed_official	489:119543c9f674	328
mbed_official	489:119543c9f674	329	#endif /* STM32F102x6 \|\| STM32F102xB \|\| STM32F103x6 \|\| STM32F103xB \|\| STM32F103xE \|\| STM32F103xG \|\| STM32F105xC \|\| STM32F107xC */
mbed_official	489:119543c9f674	330	} RCC_PeriphCLKInitTypeDef;
mbed_official	489:119543c9f674	331
mbed_official	489:119543c9f674	332	/**
mbed_official	489:119543c9f674	333	* @}
mbed_official	489:119543c9f674	334	*/
mbed_official	489:119543c9f674	335
mbed_official	489:119543c9f674	336	/* Exported constants --------------------------------------------------------*/
mbed_official	489:119543c9f674	337
mbed_official	489:119543c9f674	338	/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
mbed_official	489:119543c9f674	339	* @{
mbed_official	489:119543c9f674	340	*/
mbed_official	489:119543c9f674	341
mbed_official	489:119543c9f674	342	/** @defgroup RCCEx_Periph_Clock_Selection Periph Clock Selection
mbed_official	489:119543c9f674	343	* @{
mbed_official	489:119543c9f674	344	*/
mbed_official	489:119543c9f674	345	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00000001)
mbed_official	489:119543c9f674	346	#define RCC_PERIPHCLK_ADC ((uint32_t)0x00000002)
mbed_official	489:119543c9f674	347	#if defined (STM32F103xE) \|\| defined (STM32F103xG) \|\| defined (STM32F105xC) \|\| defined (STM32F107xC)
mbed_official	489:119543c9f674	348	#define RCC_PERIPHCLK_I2S2 ((uint32_t)0x00000004)
mbed_official	489:119543c9f674	349	#define RCC_PERIPHCLK_I2S3 ((uint32_t)0x00000008)
mbed_official	489:119543c9f674	350	#endif /* STM32F103xE \|\| STM32F103xG \|\| STM32F105xC \|\| STM32F107xC */
mbed_official	489:119543c9f674	351	#if defined(STM32F102x6) \|\| defined(STM32F102xB) \|\| defined(STM32F103x6) \|\| defined(STM32F103xB) \|\| defined(STM32F103xE) \|\| \
mbed_official	489:119543c9f674	352	defined(STM32F103xG) \|\| defined(STM32F105xC) \|\| defined(STM32F107xC)
mbed_official	489:119543c9f674	353	#define RCC_PERIPHCLK_USB ((uint32_t)0x00000010)
mbed_official	489:119543c9f674	354	#endif /* STM32F102x6 \|\| STM32F102xB \|\| STM32F103x6 \|\| STM32F103xB \|\| STM32F103xE \|\| STM32F103xG \|\| STM32F105xC \|\| STM32F107xC */
mbed_official	489:119543c9f674	355
mbed_official	489:119543c9f674	356	/**
mbed_official	489:119543c9f674	357	* @}
mbed_official	489:119543c9f674	358	*/
mbed_official	489:119543c9f674	359
mbed_official	489:119543c9f674	360	/** @defgroup RCCEx_ADC_Prescaler ADC Prescaler
mbed_official	489:119543c9f674	361	* @{
mbed_official	489:119543c9f674	362	*/
mbed_official	489:119543c9f674	363	#define RCC_ADCPCLK2_DIV2 RCC_CFGR_ADCPRE_DIV2
mbed_official	489:119543c9f674	364	#define RCC_ADCPCLK2_DIV4 RCC_CFGR_ADCPRE_DIV4
mbed_official	489:119543c9f674	365	#define RCC_ADCPCLK2_DIV6 RCC_CFGR_ADCPRE_DIV6
mbed_official	489:119543c9f674	366	#define RCC_ADCPCLK2_DIV8 RCC_CFGR_ADCPRE_DIV8
mbed_official	489:119543c9f674	367
mbed_official	489:119543c9f674	368	/**
mbed_official	489:119543c9f674	369	* @}
mbed_official	489:119543c9f674	370	*/
mbed_official	489:119543c9f674	371
mbed_official	489:119543c9f674	372	#if defined (STM32F103xE) \|\| defined (STM32F103xG) \|\| defined (STM32F105xC) \|\| defined (STM32F107xC)
mbed_official	489:119543c9f674	373	/** @defgroup RCCEx_I2S2_Clock_Source I2S2 Clock Source
mbed_official	489:119543c9f674	374	* @{
mbed_official	489:119543c9f674	375	*/
mbed_official	489:119543c9f674	376	#define RCC_I2S2CLKSOURCE_SYSCLK ((uint32_t)0x00000000)
mbed_official	489:119543c9f674	377	#if defined(STM32F105xC) \|\| defined(STM32F107xC)
mbed_official	489:119543c9f674	378	#define RCC_I2S2CLKSOURCE_PLLI2S_VCO RCC_CFGR2_I2S2SRC
mbed_official	489:119543c9f674	379	#endif /* STM32F105xC \|\| STM32F107xC */
mbed_official	489:119543c9f674	380
mbed_official	489:119543c9f674	381	/**
mbed_official	489:119543c9f674	382	* @}
mbed_official	489:119543c9f674	383	*/
mbed_official	489:119543c9f674	384
mbed_official	489:119543c9f674	385	/** @defgroup RCCEx_I2S3_Clock_Source I2S3 Clock Source
mbed_official	489:119543c9f674	386	* @{
mbed_official	489:119543c9f674	387	*/
mbed_official	489:119543c9f674	388	#define RCC_I2S3CLKSOURCE_SYSCLK ((uint32_t)0x00000000)
mbed_official	489:119543c9f674	389	#if defined(STM32F105xC) \|\| defined(STM32F107xC)
mbed_official	489:119543c9f674	390	#define RCC_I2S3CLKSOURCE_PLLI2S_VCO RCC_CFGR2_I2S3SRC
mbed_official	489:119543c9f674	391	#endif /* STM32F105xC \|\| STM32F107xC */
mbed_official	489:119543c9f674	392
mbed_official	489:119543c9f674	393	/**
mbed_official	489:119543c9f674	394	* @}
mbed_official	489:119543c9f674	395	*/
mbed_official	489:119543c9f674	396
mbed_official	489:119543c9f674	397	#endif /* STM32F103xE \|\| STM32F103xG \|\| STM32F105xC \|\| STM32F107xC */
mbed_official	489:119543c9f674	398
mbed_official	489:119543c9f674	399	#if defined(STM32F102x6) \|\| defined(STM32F102xB) \|\| defined(STM32F103x6) \|\| defined(STM32F103xB) \|\| defined(STM32F103xE) \|\| defined(STM32F103xG)
mbed_official	489:119543c9f674	400
mbed_official	489:119543c9f674	401	/** @defgroup RCCEx_USB_Prescaler USB Prescaler
mbed_official	489:119543c9f674	402	* @{
mbed_official	489:119543c9f674	403	*/
mbed_official	489:119543c9f674	404	#define RCC_USBPLLCLK_DIV1 RCC_CFGR_USBPRE
mbed_official	489:119543c9f674	405	#define RCC_USBPLLCLK_DIV1_5 ((uint32_t)0x00000000)
mbed_official	489:119543c9f674	406
mbed_official	489:119543c9f674	407	/**
mbed_official	489:119543c9f674	408	* @}
mbed_official	489:119543c9f674	409	*/
mbed_official	489:119543c9f674	410
mbed_official	489:119543c9f674	411	#endif /* STM32F102x6 \|\| STM32F102xB \|\| STM32F103x6 \|\| STM32F103xB \|\| STM32F103xE \|\| STM32F103xG */
mbed_official	489:119543c9f674	412
mbed_official	489:119543c9f674	413
mbed_official	489:119543c9f674	414	#if defined(STM32F105xC) \|\| defined(STM32F107xC)
mbed_official	489:119543c9f674	415	/** @defgroup RCCEx_USB_Prescaler USB Prescaler
mbed_official	489:119543c9f674	416	* @{
mbed_official	489:119543c9f674	417	*/
mbed_official	489:119543c9f674	418	#define RCC_USBPLLCLK_DIV2 RCC_CFGR_OTGFSPRE
mbed_official	489:119543c9f674	419	#define RCC_USBPLLCLK_DIV3 ((uint32_t)0x00000000)
mbed_official	489:119543c9f674	420
mbed_official	489:119543c9f674	421	/**
mbed_official	489:119543c9f674	422	* @}
mbed_official	489:119543c9f674	423	*/
mbed_official	489:119543c9f674	424
mbed_official	489:119543c9f674	425	/** @defgroup RCCEx_PLLI2S_Multiplication_Factor PLLI2S Multiplication Factor
mbed_official	489:119543c9f674	426	* @{
mbed_official	489:119543c9f674	427	*/
mbed_official	489:119543c9f674	428
mbed_official	489:119543c9f674	429	#define RCC_PLLI2S_MUL8 RCC_CFGR2_PLL3MUL8 /!< PLLI2S input clock 8 */
mbed_official	489:119543c9f674	430	#define RCC_PLLI2S_MUL9 RCC_CFGR2_PLL3MUL9 /!< PLLI2S input clock 9 */
mbed_official	489:119543c9f674	431	#define RCC_PLLI2S_MUL10 RCC_CFGR2_PLL3MUL10 /!< PLLI2S input clock 10 */
mbed_official	489:119543c9f674	432	#define RCC_PLLI2S_MUL11 RCC_CFGR2_PLL3MUL11 /!< PLLI2S input clock 11 */
mbed_official	489:119543c9f674	433	#define RCC_PLLI2S_MUL12 RCC_CFGR2_PLL3MUL12 /!< PLLI2S input clock 12 */
mbed_official	489:119543c9f674	434	#define RCC_PLLI2S_MUL13 RCC_CFGR2_PLL3MUL13 /!< PLLI2S input clock 13 */
mbed_official	489:119543c9f674	435	#define RCC_PLLI2S_MUL14 RCC_CFGR2_PLL3MUL14 /!< PLLI2S input clock 14 */
mbed_official	489:119543c9f674	436	#define RCC_PLLI2S_MUL16 RCC_CFGR2_PLL3MUL16 /!< PLLI2S input clock 16 */
mbed_official	489:119543c9f674	437	#define RCC_PLLI2S_MUL20 RCC_CFGR2_PLL3MUL20 /!< PLLI2S input clock 20 */
mbed_official	489:119543c9f674	438
mbed_official	489:119543c9f674	439	/**
mbed_official	489:119543c9f674	440	* @}
mbed_official	489:119543c9f674	441	*/
mbed_official	489:119543c9f674	442	#endif /* STM32F105xC \|\| STM32F107xC */
mbed_official	489:119543c9f674	443
mbed_official	489:119543c9f674	444	#if defined(STM32F105xC) \|\| defined(STM32F107xC)
mbed_official	489:119543c9f674	445	/** @defgroup RCCEx_Prediv1_Source Prediv1 Source
mbed_official	489:119543c9f674	446	* @{
mbed_official	489:119543c9f674	447	*/
mbed_official	489:119543c9f674	448
mbed_official	489:119543c9f674	449	#define RCC_PREDIV1_SOURCE_HSE RCC_CFGR2_PREDIV1SRC_HSE
mbed_official	489:119543c9f674	450	#define RCC_PREDIV1_SOURCE_PLL2 RCC_CFGR2_PREDIV1SRC_PLL2
mbed_official	489:119543c9f674	451
mbed_official	489:119543c9f674	452	/**
mbed_official	489:119543c9f674	453	* @}
mbed_official	489:119543c9f674	454	*/
mbed_official	489:119543c9f674	455	#endif /* STM32F105xC \|\| STM32F107xC */
mbed_official	489:119543c9f674	456
mbed_official	489:119543c9f674	457	/** @defgroup RCCEx_Prediv1_Factor HSE Prediv1 Factor
mbed_official	489:119543c9f674	458	* @{
mbed_official	489:119543c9f674	459	*/
mbed_official	489:119543c9f674	460
mbed_official	489:119543c9f674	461	#define RCC_HSE_PREDIV_DIV1 ((uint32_t)0x00000000)
mbed_official	489:119543c9f674	462
mbed_official	489:119543c9f674	463	#if defined(STM32F105xC) \|\| defined(STM32F107xC) \|\| defined (STM32F100xB) \|\| defined (STM32F100xE)
mbed_official	489:119543c9f674	464	#define RCC_HSE_PREDIV_DIV2 RCC_CFGR2_PREDIV1_DIV2
mbed_official	489:119543c9f674	465	#define RCC_HSE_PREDIV_DIV3 RCC_CFGR2_PREDIV1_DIV3
mbed_official	489:119543c9f674	466	#define RCC_HSE_PREDIV_DIV4 RCC_CFGR2_PREDIV1_DIV4
mbed_official	489:119543c9f674	467	#define RCC_HSE_PREDIV_DIV5 RCC_CFGR2_PREDIV1_DIV5
mbed_official	489:119543c9f674	468	#define RCC_HSE_PREDIV_DIV6 RCC_CFGR2_PREDIV1_DIV6
mbed_official	489:119543c9f674	469	#define RCC_HSE_PREDIV_DIV7 RCC_CFGR2_PREDIV1_DIV7
mbed_official	489:119543c9f674	470	#define RCC_HSE_PREDIV_DIV8 RCC_CFGR2_PREDIV1_DIV8
mbed_official	489:119543c9f674	471	#define RCC_HSE_PREDIV_DIV9 RCC_CFGR2_PREDIV1_DIV9
mbed_official	489:119543c9f674	472	#define RCC_HSE_PREDIV_DIV10 RCC_CFGR2_PREDIV1_DIV10
mbed_official	489:119543c9f674	473	#define RCC_HSE_PREDIV_DIV11 RCC_CFGR2_PREDIV1_DIV11
mbed_official	489:119543c9f674	474	#define RCC_HSE_PREDIV_DIV12 RCC_CFGR2_PREDIV1_DIV12
mbed_official	489:119543c9f674	475	#define RCC_HSE_PREDIV_DIV13 RCC_CFGR2_PREDIV1_DIV13
mbed_official	489:119543c9f674	476	#define RCC_HSE_PREDIV_DIV14 RCC_CFGR2_PREDIV1_DIV14
mbed_official	489:119543c9f674	477	#define RCC_HSE_PREDIV_DIV15 RCC_CFGR2_PREDIV1_DIV15
mbed_official	489:119543c9f674	478	#define RCC_HSE_PREDIV_DIV16 RCC_CFGR2_PREDIV1_DIV16
mbed_official	489:119543c9f674	479	#else
mbed_official	489:119543c9f674	480	#define RCC_HSE_PREDIV_DIV2 RCC_CFGR_PLLXTPRE
mbed_official	489:119543c9f674	481	#endif /* STM32F105xC \|\| STM32F107xC \|\| STM32F100xB \|\| STM32F100xE */
mbed_official	489:119543c9f674	482
mbed_official	489:119543c9f674	483	/**
mbed_official	489:119543c9f674	484	* @}
mbed_official	489:119543c9f674	485	*/
mbed_official	489:119543c9f674	486
mbed_official	489:119543c9f674	487	#if defined(STM32F105xC) \|\| defined(STM32F107xC)
mbed_official	489:119543c9f674	488	/** @defgroup RCCEx_Prediv2_Factor HSE Prediv2 Factor
mbed_official	489:119543c9f674	489	* @{
mbed_official	489:119543c9f674	490	*/
mbed_official	489:119543c9f674	491
mbed_official	489:119543c9f674	492	#define RCC_HSE_PREDIV2_DIV1 RCC_CFGR2_PREDIV2_DIV1 /!< PREDIV2 input clock not divided /
mbed_official	489:119543c9f674	493	#define RCC_HSE_PREDIV2_DIV2 RCC_CFGR2_PREDIV2_DIV2 /!< PREDIV2 input clock divided by 2 /
mbed_official	489:119543c9f674	494	#define RCC_HSE_PREDIV2_DIV3 RCC_CFGR2_PREDIV2_DIV3 /!< PREDIV2 input clock divided by 3 /
mbed_official	489:119543c9f674	495	#define RCC_HSE_PREDIV2_DIV4 RCC_CFGR2_PREDIV2_DIV4 /!< PREDIV2 input clock divided by 4 /
mbed_official	489:119543c9f674	496	#define RCC_HSE_PREDIV2_DIV5 RCC_CFGR2_PREDIV2_DIV5 /!< PREDIV2 input clock divided by 5 /
mbed_official	489:119543c9f674	497	#define RCC_HSE_PREDIV2_DIV6 RCC_CFGR2_PREDIV2_DIV6 /!< PREDIV2 input clock divided by 6 /
mbed_official	489:119543c9f674	498	#define RCC_HSE_PREDIV2_DIV7 RCC_CFGR2_PREDIV2_DIV7 /!< PREDIV2 input clock divided by 7 /
mbed_official	489:119543c9f674	499	#define RCC_HSE_PREDIV2_DIV8 RCC_CFGR2_PREDIV2_DIV8 /!< PREDIV2 input clock divided by 8 /
mbed_official	489:119543c9f674	500	#define RCC_HSE_PREDIV2_DIV9 RCC_CFGR2_PREDIV2_DIV9 /!< PREDIV2 input clock divided by 9 /
mbed_official	489:119543c9f674	501	#define RCC_HSE_PREDIV2_DIV10 RCC_CFGR2_PREDIV2_DIV10 /!< PREDIV2 input clock divided by 10 /
mbed_official	489:119543c9f674	502	#define RCC_HSE_PREDIV2_DIV11 RCC_CFGR2_PREDIV2_DIV11 /!< PREDIV2 input clock divided by 11 /
mbed_official	489:119543c9f674	503	#define RCC_HSE_PREDIV2_DIV12 RCC_CFGR2_PREDIV2_DIV12 /!< PREDIV2 input clock divided by 12 /
mbed_official	489:119543c9f674	504	#define RCC_HSE_PREDIV2_DIV13 RCC_CFGR2_PREDIV2_DIV13 /!< PREDIV2 input clock divided by 13 /
mbed_official	489:119543c9f674	505	#define RCC_HSE_PREDIV2_DIV14 RCC_CFGR2_PREDIV2_DIV14 /!< PREDIV2 input clock divided by 14 /
mbed_official	489:119543c9f674	506	#define RCC_HSE_PREDIV2_DIV15 RCC_CFGR2_PREDIV2_DIV15 /!< PREDIV2 input clock divided by 15 /
mbed_official	489:119543c9f674	507	#define RCC_HSE_PREDIV2_DIV16 RCC_CFGR2_PREDIV2_DIV16 /!< PREDIV2 input clock divided by 16 /
mbed_official	489:119543c9f674	508
mbed_official	489:119543c9f674	509	/**
mbed_official	489:119543c9f674	510	* @}
mbed_official	489:119543c9f674	511	*/
mbed_official	489:119543c9f674	512
mbed_official	489:119543c9f674	513	/** @defgroup RCCEx_PLL2_Config PLL Config
mbed_official	489:119543c9f674	514	* @{
mbed_official	489:119543c9f674	515	*/
mbed_official	489:119543c9f674	516	#define RCC_PLL2_NONE ((uint32_t)0x00000000)
mbed_official	489:119543c9f674	517	#define RCC_PLL2_OFF ((uint32_t)0x00000001)
mbed_official	489:119543c9f674	518	#define RCC_PLL2_ON ((uint32_t)0x00000002)
mbed_official	489:119543c9f674	519
mbed_official	489:119543c9f674	520	/**
mbed_official	489:119543c9f674	521	* @}
mbed_official	489:119543c9f674	522	*/
mbed_official	489:119543c9f674	523
mbed_official	489:119543c9f674	524	/** @defgroup RCCEx_PLL2_Multiplication_Factor PLL2 Multiplication Factor
mbed_official	489:119543c9f674	525	* @{
mbed_official	489:119543c9f674	526	*/
mbed_official	489:119543c9f674	527
mbed_official	489:119543c9f674	528	#define RCC_PLL2_MUL8 RCC_CFGR2_PLL2MUL8 /!< PLL2 input clock 8 */
mbed_official	489:119543c9f674	529	#define RCC_PLL2_MUL9 RCC_CFGR2_PLL2MUL9 /!< PLL2 input clock 9 */
mbed_official	489:119543c9f674	530	#define RCC_PLL2_MUL10 RCC_CFGR2_PLL2MUL10 /!< PLL2 input clock 10 */
mbed_official	489:119543c9f674	531	#define RCC_PLL2_MUL11 RCC_CFGR2_PLL2MUL11 /!< PLL2 input clock 11 */
mbed_official	489:119543c9f674	532	#define RCC_PLL2_MUL12 RCC_CFGR2_PLL2MUL12 /!< PLL2 input clock 12 */
mbed_official	489:119543c9f674	533	#define RCC_PLL2_MUL13 RCC_CFGR2_PLL2MUL13 /!< PLL2 input clock 13 */
mbed_official	489:119543c9f674	534	#define RCC_PLL2_MUL14 RCC_CFGR2_PLL2MUL14 /!< PLL2 input clock 14 */
mbed_official	489:119543c9f674	535	#define RCC_PLL2_MUL16 RCC_CFGR2_PLL2MUL16 /!< PLL2 input clock 16 */
mbed_official	489:119543c9f674	536	#define RCC_PLL2_MUL20 RCC_CFGR2_PLL2MUL20 /!< PLL2 input clock 20 */
mbed_official	489:119543c9f674	537
mbed_official	489:119543c9f674	538	/**
mbed_official	489:119543c9f674	539	* @}
mbed_official	489:119543c9f674	540	*/
mbed_official	489:119543c9f674	541
mbed_official	489:119543c9f674	542	#endif /* STM32F105xC \|\| STM32F107xC */
mbed_official	489:119543c9f674	543
mbed_official	489:119543c9f674	544	/** @defgroup RCCEx_PLL_Multiplication_Factor PLL Multiplication Factor
mbed_official	489:119543c9f674	545	* @{
mbed_official	489:119543c9f674	546	*/
mbed_official	489:119543c9f674	547
mbed_official	489:119543c9f674	548	#if defined(STM32F105xC) \|\| defined(STM32F107xC)
mbed_official	489:119543c9f674	549	#else
mbed_official	489:119543c9f674	550	#define RCC_PLL_MUL2 RCC_CFGR_PLLMULL2
mbed_official	489:119543c9f674	551	#define RCC_PLL_MUL3 RCC_CFGR_PLLMULL3
mbed_official	489:119543c9f674	552	#endif /* STM32F105xC \|\| STM32F107xC */
mbed_official	489:119543c9f674	553	#define RCC_PLL_MUL4 RCC_CFGR_PLLMULL4
mbed_official	489:119543c9f674	554	#define RCC_PLL_MUL5 RCC_CFGR_PLLMULL5
mbed_official	489:119543c9f674	555	#define RCC_PLL_MUL6 RCC_CFGR_PLLMULL6
mbed_official	489:119543c9f674	556	#define RCC_PLL_MUL7 RCC_CFGR_PLLMULL7
mbed_official	489:119543c9f674	557	#define RCC_PLL_MUL8 RCC_CFGR_PLLMULL8
mbed_official	489:119543c9f674	558	#define RCC_PLL_MUL9 RCC_CFGR_PLLMULL9
mbed_official	489:119543c9f674	559	#if defined(STM32F105xC) \|\| defined(STM32F107xC)
mbed_official	489:119543c9f674	560	#define RCC_PLL_MUL6_5 RCC_CFGR_PLLMULL6_5
mbed_official	489:119543c9f674	561	#else
mbed_official	489:119543c9f674	562	#define RCC_PLL_MUL10 RCC_CFGR_PLLMULL10
mbed_official	489:119543c9f674	563	#define RCC_PLL_MUL11 RCC_CFGR_PLLMULL11
mbed_official	489:119543c9f674	564	#define RCC_PLL_MUL12 RCC_CFGR_PLLMULL12
mbed_official	489:119543c9f674	565	#define RCC_PLL_MUL13 RCC_CFGR_PLLMULL13
mbed_official	489:119543c9f674	566	#define RCC_PLL_MUL14 RCC_CFGR_PLLMULL14
mbed_official	489:119543c9f674	567	#define RCC_PLL_MUL15 RCC_CFGR_PLLMULL15
mbed_official	489:119543c9f674	568	#define RCC_PLL_MUL16 RCC_CFGR_PLLMULL16
mbed_official	489:119543c9f674	569	#endif /* STM32F105xC \|\| STM32F107xC */
mbed_official	489:119543c9f674	570
mbed_official	489:119543c9f674	571	/**
mbed_official	489:119543c9f674	572	* @}
mbed_official	489:119543c9f674	573	*/
mbed_official	489:119543c9f674	574
mbed_official	489:119543c9f674	575	/** @defgroup RCCEx_MCO1_Clock_Source MCO1 Clock Source
mbed_official	489:119543c9f674	576	* @{
mbed_official	489:119543c9f674	577	*/
mbed_official	489:119543c9f674	578	#define RCC_MCO1SOURCE_NOCLOCK ((uint32_t)RCC_CFGR_MCO_NOCLOCK)
mbed_official	489:119543c9f674	579	#define RCC_MCO1SOURCE_SYSCLK ((uint32_t)RCC_CFGR_MCO_SYSCLK)
mbed_official	489:119543c9f674	580	#define RCC_MCO1SOURCE_HSI ((uint32_t)RCC_CFGR_MCO_HSI)
mbed_official	489:119543c9f674	581	#define RCC_MCO1SOURCE_HSE ((uint32_t)RCC_CFGR_MCO_HSE)
mbed_official	489:119543c9f674	582	#define RCC_MCO1SOURCE_PLLCLK ((uint32_t)RCC_CFGR_MCO_PLLCLK_DIV2)
mbed_official	489:119543c9f674	583	#if defined(STM32F105xC) \|\| defined(STM32F107xC)
mbed_official	489:119543c9f674	584	#define RCC_MCO1SOURCE_PLL2CLK ((uint32_t)RCC_CFGR_MCO_PLL2CLK)
mbed_official	489:119543c9f674	585	#define RCC_MCO1SOURCE_PLL3CLK_DIV2 ((uint32_t)RCC_CFGR_MCO_PLL3CLK_DIV2)
mbed_official	489:119543c9f674	586	#define RCC_MCO1SOURCE_EXT_HSE ((uint32_t)RCC_CFGR_MCO_EXT_HSE)
mbed_official	489:119543c9f674	587	#define RCC_MCO1SOURCE_PLL3CLK ((uint32_t)RCC_CFGR_MCO_PLL3CLK)
mbed_official	489:119543c9f674	588	#endif /* STM32F105xC \|\| STM32F107xC*/
mbed_official	489:119543c9f674	589	/**
mbed_official	489:119543c9f674	590	* @}
mbed_official	489:119543c9f674	591	*/
mbed_official	489:119543c9f674	592
mbed_official	489:119543c9f674	593	#if defined(STM32F105xC) \|\| defined(STM32F107xC)
mbed_official	489:119543c9f674	594	/** @defgroup RCCEx_Interrupt RCCEx Interrupt
mbed_official	489:119543c9f674	595	* @{
mbed_official	489:119543c9f674	596	*/
mbed_official	489:119543c9f674	597	#define RCC_IT_PLL2RDY ((uint8_t)RCC_CIR_PLL2RDYF)
mbed_official	489:119543c9f674	598	#define RCC_IT_PLLI2SRDY ((uint8_t)RCC_CIR_PLL3RDYF)
mbed_official	489:119543c9f674	599	/**
mbed_official	489:119543c9f674	600	* @}
mbed_official	489:119543c9f674	601	*/
mbed_official	489:119543c9f674	602
mbed_official	489:119543c9f674	603	/** @defgroup RCCEx_Flag RCCEx Flag
mbed_official	489:119543c9f674	604	* Elements values convention: 0XXYYYYYb
mbed_official	489:119543c9f674	605	* - YYYYY : Flag position in the register
mbed_official	489:119543c9f674	606	* - XX : Register index
mbed_official	489:119543c9f674	607	* - 01: CR register
mbed_official	489:119543c9f674	608	* @{
mbed_official	489:119543c9f674	609	*/
mbed_official	489:119543c9f674	610	/* Flags in the CR register */
mbed_official	489:119543c9f674	611	#define RCC_FLAG_PLL2RDY ((uint8_t)((CR_REG_INDEX << 5) \| POSITION_VAL(RCC_CR_PLL2RDY)))
mbed_official	489:119543c9f674	612	#define RCC_FLAG_PLLI2SRDY ((uint8_t)((CR_REG_INDEX << 5) \| POSITION_VAL(RCC_CR_PLL3RDY)))
mbed_official	489:119543c9f674	613	/**
mbed_official	489:119543c9f674	614	* @}
mbed_official	489:119543c9f674	615	*/
mbed_official	489:119543c9f674	616	#endif /* STM32F105xC \|\| STM32F107xC*/
mbed_official	489:119543c9f674	617
mbed_official	489:119543c9f674	618	/**
mbed_official	489:119543c9f674	619	* @}
mbed_official	489:119543c9f674	620	*/
mbed_official	489:119543c9f674	621
mbed_official	489:119543c9f674	622	/* Exported macro ------------------------------------------------------------*/
mbed_official	489:119543c9f674	623	/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
mbed_official	489:119543c9f674	624	* @{
mbed_official	489:119543c9f674	625	*/
mbed_official	489:119543c9f674	626
mbed_official	489:119543c9f674	627	/** @defgroup RCCEx_Peripheral_Clock_Enable_Disable Peripheral Clock Enable Disable
mbed_official	489:119543c9f674	628	* @brief Enable or disable the AHB1 peripheral clock.
mbed_official	489:119543c9f674	629	* @note After reset, the peripheral clock (used for registers read/write access)
mbed_official	489:119543c9f674	630	* is disabled and the application software has to enable this clock before
mbed_official	489:119543c9f674	631	* using it.
mbed_official	489:119543c9f674	632	* @{
mbed_official	489:119543c9f674	633	*/
mbed_official	489:119543c9f674	634
mbed_official	489:119543c9f674	635	#if defined (STM32F101xE) \|\| defined (STM32F103xE) \|\| defined(STM32F101xG) \|\| defined(STM32F103xG) \|\| \
mbed_official	489:119543c9f674	636	defined (STM32F105xC) \|\| defined (STM32F107xC) \|\| defined (STM32F100xE)
mbed_official	489:119543c9f674	637	#define __HAL_RCC_DMA2_CLK_ENABLE() do { \
mbed_official	489:119543c9f674	638	__IO uint32_t tmpreg; \
mbed_official	489:119543c9f674	639	SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
mbed_official	489:119543c9f674	640	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	489:119543c9f674	641	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\
mbed_official	489:119543c9f674	642	UNUSED(tmpreg); \
mbed_official	489:119543c9f674	643	} while(0)
mbed_official	489:119543c9f674	644
mbed_official	489:119543c9f674	645	#define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN))
mbed_official	489:119543c9f674	646	#endif /* STM32F101xE \|\| STM32F103xE \|\| STM32F101xG \|\| STM32F103xG \|\| STM32F105xC \|\| STM32F107xC \|\| STM32F100xE */
mbed_official	489:119543c9f674	647
mbed_official	489:119543c9f674	648	#if defined (STM32F101xE) \|\| defined (STM32F103xE) \|\| defined(STM32F101xG) \|\| defined(STM32F103xG) \|\| defined (STM32F100xE)
mbed_official	489:119543c9f674	649	#define __HAL_RCC_FSMC_CLK_ENABLE() do { \
mbed_official	489:119543c9f674	650	__IO uint32_t tmpreg; \
mbed_official	489:119543c9f674	651	SET_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);\
mbed_official	489:119543c9f674	652	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	489:119543c9f674	653	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);\
mbed_official	489:119543c9f674	654	UNUSED(tmpreg); \
mbed_official	489:119543c9f674	655	} while(0)
mbed_official	489:119543c9f674	656
mbed_official	489:119543c9f674	657	#define __HAL_RCC_FSMC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FSMCEN))
mbed_official	489:119543c9f674	658	#endif /* STM32F101xE \|\| STM32F103xE \|\| STM32F101xG \|\| STM32F103xG \|\| STM32F100xE */
mbed_official	489:119543c9f674	659
mbed_official	489:119543c9f674	660	#if defined (STM32F103xE) \|\| defined(STM32F103xG)
mbed_official	489:119543c9f674	661	#define __HAL_RCC_SDIO_CLK_ENABLE() do { \
mbed_official	489:119543c9f674	662	__IO uint32_t tmpreg; \
mbed_official	489:119543c9f674	663	SET_BIT(RCC->AHBENR, RCC_AHBENR_SDIOEN);\
mbed_official	489:119543c9f674	664	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	489:119543c9f674	665	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_SDIOEN);\
mbed_official	489:119543c9f674	666	UNUSED(tmpreg); \
mbed_official	489:119543c9f674	667	} while(0)
mbed_official	489:119543c9f674	668
mbed_official	489:119543c9f674	669
mbed_official	489:119543c9f674	670	#define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SDIOEN))
mbed_official	489:119543c9f674	671	#endif /* STM32F103xE \|\| STM32F103xG */
mbed_official	489:119543c9f674	672
mbed_official	489:119543c9f674	673	#if defined(STM32F105xC) \|\| defined(STM32F107xC)
mbed_official	489:119543c9f674	674	#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do { \
mbed_official	489:119543c9f674	675	__IO uint32_t tmpreg; \
mbed_official	489:119543c9f674	676	SET_BIT(RCC->AHBENR, RCC_AHBENR_OTGFSEN);\
mbed_official	489:119543c9f674	677	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	489:119543c9f674	678	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_OTGFSEN);\
mbed_official	489:119543c9f674	679	UNUSED(tmpreg); \
mbed_official	489:119543c9f674	680	} while(0)
mbed_official	489:119543c9f674	681
mbed_official	489:119543c9f674	682
mbed_official	489:119543c9f674	683	#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_OTGFSEN))
mbed_official	489:119543c9f674	684	#endif /* STM32F105xC \|\| STM32F107xC*/
mbed_official	489:119543c9f674	685
mbed_official	489:119543c9f674	686	#if defined(STM32F107xC)
mbed_official	489:119543c9f674	687	#define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \
mbed_official	489:119543c9f674	688	__IO uint32_t tmpreg; \
mbed_official	489:119543c9f674	689	SET_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACEN);\
mbed_official	489:119543c9f674	690	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	489:119543c9f674	691	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACEN);\
mbed_official	489:119543c9f674	692	UNUSED(tmpreg); \
mbed_official	489:119543c9f674	693	} while(0)
mbed_official	489:119543c9f674	694
mbed_official	489:119543c9f674	695	#define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \
mbed_official	489:119543c9f674	696	__IO uint32_t tmpreg; \
mbed_official	489:119543c9f674	697	SET_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACTXEN);\
mbed_official	489:119543c9f674	698	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	489:119543c9f674	699	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACTXEN);\
mbed_official	489:119543c9f674	700	UNUSED(tmpreg); \
mbed_official	489:119543c9f674	701	} while(0)
mbed_official	489:119543c9f674	702
mbed_official	489:119543c9f674	703	#define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \
mbed_official	489:119543c9f674	704	__IO uint32_t tmpreg; \
mbed_official	489:119543c9f674	705	SET_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACRXEN);\
mbed_official	489:119543c9f674	706	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	489:119543c9f674	707	tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_ETHMACRXEN);\
mbed_official	489:119543c9f674	708	UNUSED(tmpreg); \
mbed_official	489:119543c9f674	709	} while(0)
mbed_official	489:119543c9f674	710
mbed_official	489:119543c9f674	711	#define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ETHMACEN))
mbed_official	489:119543c9f674	712	#define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ETHMACTXEN))
mbed_official	489:119543c9f674	713	#define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ETHMACRXEN))
mbed_official	489:119543c9f674	714
mbed_official	489:119543c9f674	715	/**
mbed_official	489:119543c9f674	716	* @brief Enable ETHERNET clock.
mbed_official	489:119543c9f674	717	*/
mbed_official	489:119543c9f674	718	#define __HAL_RCC_ETH_CLK_ENABLE() do { \
mbed_official	489:119543c9f674	719	__HAL_RCC_ETHMAC_CLK_ENABLE(); \
mbed_official	489:119543c9f674	720	__HAL_RCC_ETHMACTX_CLK_ENABLE(); \
mbed_official	489:119543c9f674	721	__HAL_RCC_ETHMACRX_CLK_ENABLE(); \
mbed_official	489:119543c9f674	722	} while(0)
mbed_official	489:119543c9f674	723	/**
mbed_official	489:119543c9f674	724	* @brief Disable ETHERNET clock.
mbed_official	489:119543c9f674	725	*/
mbed_official	489:119543c9f674	726	#define __HAL_RCC_ETH_CLK_DISABLE() do { \
mbed_official	489:119543c9f674	727	__HAL_RCC_ETHMACTX_CLK_DISABLE(); \
mbed_official	489:119543c9f674	728	__HAL_RCC_ETHMACRX_CLK_DISABLE(); \
mbed_official	489:119543c9f674	729	__HAL_RCC_ETHMAC_CLK_DISABLE(); \
mbed_official	489:119543c9f674	730	} while(0)
mbed_official	489:119543c9f674	731
mbed_official	489:119543c9f674	732	#endif /* STM32F107xC*/
mbed_official	489:119543c9f674	733
mbed_official	489:119543c9f674	734	/**
mbed_official	489:119543c9f674	735	* @}
mbed_official	489:119543c9f674	736	*/
mbed_official	489:119543c9f674	737
mbed_official	489:119543c9f674	738	/** @defgroup RCCEx_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enable Disable Status
mbed_official	489:119543c9f674	739	* @brief Get the enable or disable status of the AHB1 peripheral clock.
mbed_official	489:119543c9f674	740	* @note After reset, the peripheral clock (used for registers read/write access)
mbed_official	489:119543c9f674	741	* is disabled and the application software has to enable this clock before
mbed_official	489:119543c9f674	742	* using it.
mbed_official	489:119543c9f674	743	* @{
mbed_official	489:119543c9f674	744	*/
mbed_official	489:119543c9f674	745
mbed_official	489:119543c9f674	746	#if defined (STM32F101xE) \|\| defined (STM32F103xE) \|\| defined(STM32F101xG) \|\| defined(STM32F103xG) \|\| \
mbed_official	489:119543c9f674	747	defined (STM32F105xC) \|\| defined (STM32F107xC) \|\| defined (STM32F100xE)
mbed_official	489:119543c9f674	748	#define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) != RESET)
mbed_official	489:119543c9f674	749	#define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) == RESET)
mbed_official	489:119543c9f674	750	#endif /* STM32F101xE \|\| STM32F103xE \|\| STM32F101xG \|\| STM32F103xG \|\| STM32F105xC \|\| STM32F107xC \|\| STM32F100xE */
mbed_official	489:119543c9f674	751	#if defined (STM32F101xE) \|\| defined (STM32F103xE) \|\| defined(STM32F101xG) \|\| defined(STM32F103xG) \|\| defined (STM32F100xE)
mbed_official	489:119543c9f674	752	#define __HAL_RCC_FSMC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_FSMCEN)) != RESET)
mbed_official	489:119543c9f674	753	#define __HAL_RCC_FSMC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_FSMCEN)) == RESET)
mbed_official	489:119543c9f674	754	#endif /* STM32F101xE \|\| STM32F103xE \|\| STM32F101xG \|\| STM32F103xG \|\| STM32F100xE */
mbed_official	489:119543c9f674	755	#if defined (STM32F103xE) \|\| defined(STM32F103xG)
mbed_official	489:119543c9f674	756	#define __HAL_RCC_SDIO_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_SDIOEN)) != RESET)
mbed_official	489:119543c9f674	757	#define __HAL_RCC_SDIO_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_SDIOEN)) == RESET)
mbed_official	489:119543c9f674	758	#endif /* STM32F103xE \|\| STM32F103xG */
mbed_official	489:119543c9f674	759	#if defined(STM32F105xC) \|\| defined(STM32F107xC)
mbed_official	489:119543c9f674	760	#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_OTGFSEN)) != RESET)
mbed_official	489:119543c9f674	761	#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_OTGFSEN)) == RESET)
mbed_official	489:119543c9f674	762	#endif /* STM32F105xC \|\| STM32F107xC*/
mbed_official	489:119543c9f674	763	#if defined(STM32F107xC)
mbed_official	489:119543c9f674	764	#define __HAL_RCC_ETHMAC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACEN)) != RESET)
mbed_official	489:119543c9f674	765	#define __HAL_RCC_ETHMAC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACEN)) == RESET)
mbed_official	489:119543c9f674	766	#define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACTXEN)) != RESET)
mbed_official	489:119543c9f674	767	#define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACTXEN)) == RESET)
mbed_official	489:119543c9f674	768	#define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACRXEN)) != RESET)
mbed_official	489:119543c9f674	769	#define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_ETHMACRXEN)) == RESET)
mbed_official	489:119543c9f674	770	#endif /* STM32F107xC*/
mbed_official	489:119543c9f674	771
mbed_official	489:119543c9f674	772	/**
mbed_official	489:119543c9f674	773	* @}
mbed_official	489:119543c9f674	774	*/
mbed_official	489:119543c9f674	775
mbed_official	489:119543c9f674	776	/** @defgroup RCCEx_APB1_Clock_Enable_Disable APB1 Clock Enable Disable
mbed_official	489:119543c9f674	777	* @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
mbed_official	489:119543c9f674	778	* @note After reset, the peripheral clock (used for registers read/write access)
mbed_official	489:119543c9f674	779	* is disabled and the application software has to enable this clock before
mbed_official	489:119543c9f674	780	* using it.
mbed_official	489:119543c9f674	781	* @{
mbed_official	489:119543c9f674	782	*/
mbed_official	489:119543c9f674	783
mbed_official	489:119543c9f674	784	#if defined(STM32F103x6) \|\| defined(STM32F103xB) \|\| defined(STM32F103xE) \|\| defined(STM32F103xG) \|\| \
mbed_official	489:119543c9f674	785	defined(STM32F105xC) \|\|defined (STM32F107xC)
mbed_official	489:119543c9f674	786	#define __HAL_RCC_CAN1_CLK_ENABLE() do { \
mbed_official	489:119543c9f674	787	__IO uint32_t tmpreg; \
mbed_official	489:119543c9f674	788	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
mbed_official	489:119543c9f674	789	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	489:119543c9f674	790	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
mbed_official	489:119543c9f674	791	UNUSED(tmpreg); \
mbed_official	489:119543c9f674	792	} while(0)
mbed_official	489:119543c9f674	793
mbed_official	489:119543c9f674	794	#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
mbed_official	489:119543c9f674	795	#endif /* STM32F103x6 \|\| STM32F103xB \|\| STM32F103xE \|\| STM32F103xG \|\| STM32F105xC \|\| STM32F107xC */
mbed_official	489:119543c9f674	796
mbed_official	489:119543c9f674	797	#if defined(STM32F100xB) \|\| defined(STM32F100xE) \|\| defined(STM32F101xB) \|\| defined(STM32F101xE) \|\| \
mbed_official	489:119543c9f674	798	defined(STM32F101xG) \|\| defined(STM32F102xB) \|\| defined(STM32F103xB) \|\| defined(STM32F103xE) \|\| \
mbed_official	489:119543c9f674	799	defined(STM32F103xG) \|\| defined(STM32F105xC) \|\| defined(STM32F107xC)
mbed_official	489:119543c9f674	800	#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
mbed_official	489:119543c9f674	801	__IO uint32_t tmpreg; \
mbed_official	489:119543c9f674	802	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
mbed_official	489:119543c9f674	803	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	489:119543c9f674	804	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
mbed_official	489:119543c9f674	805	UNUSED(tmpreg); \
mbed_official	489:119543c9f674	806	} while(0)
mbed_official	489:119543c9f674	807
mbed_official	489:119543c9f674	808	#define __HAL_RCC_SPI2_CLK_ENABLE() do { \
mbed_official	489:119543c9f674	809	__IO uint32_t tmpreg; \
mbed_official	489:119543c9f674	810	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
mbed_official	489:119543c9f674	811	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	489:119543c9f674	812	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
mbed_official	489:119543c9f674	813	UNUSED(tmpreg); \
mbed_official	489:119543c9f674	814	} while(0)
mbed_official	489:119543c9f674	815
mbed_official	489:119543c9f674	816	#define __HAL_RCC_USART3_CLK_ENABLE() do { \
mbed_official	489:119543c9f674	817	__IO uint32_t tmpreg; \
mbed_official	489:119543c9f674	818	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
mbed_official	489:119543c9f674	819	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	489:119543c9f674	820	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
mbed_official	489:119543c9f674	821	UNUSED(tmpreg); \
mbed_official	489:119543c9f674	822	} while(0)
mbed_official	489:119543c9f674	823
mbed_official	489:119543c9f674	824	#define __HAL_RCC_I2C2_CLK_ENABLE() do { \
mbed_official	489:119543c9f674	825	__IO uint32_t tmpreg; \
mbed_official	489:119543c9f674	826	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
mbed_official	489:119543c9f674	827	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	489:119543c9f674	828	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
mbed_official	489:119543c9f674	829	UNUSED(tmpreg); \
mbed_official	489:119543c9f674	830	} while(0)
mbed_official	489:119543c9f674	831
mbed_official	489:119543c9f674	832	#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
mbed_official	489:119543c9f674	833	#define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
mbed_official	489:119543c9f674	834	#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
mbed_official	489:119543c9f674	835	#define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
mbed_official	489:119543c9f674	836	#endif /* STM32F100xB \|\| STM32F101xB \|\| STM32F101xE \|\| (...) \|\| STM32F105xC \|\| STM32F107xC */
mbed_official	489:119543c9f674	837
mbed_official	489:119543c9f674	838	#if defined(STM32F102x6) \|\| defined(STM32F102xB) \|\| defined(STM32F103x6) \|\| defined(STM32F103xB) \|\| defined(STM32F103xE) \|\| defined(STM32F103xG)
mbed_official	489:119543c9f674	839	#define __HAL_RCC_USB_CLK_ENABLE() do { \
mbed_official	489:119543c9f674	840	__IO uint32_t tmpreg; \
mbed_official	489:119543c9f674	841	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\
mbed_official	489:119543c9f674	842	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	489:119543c9f674	843	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USBEN);\
mbed_official	489:119543c9f674	844	UNUSED(tmpreg); \
mbed_official	489:119543c9f674	845	} while(0)
mbed_official	489:119543c9f674	846
mbed_official	489:119543c9f674	847	#define __HAL_RCC_USB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN))
mbed_official	489:119543c9f674	848	#endif /* STM32F102x6 \|\| STM32F102xB \|\| STM32F103x6 \|\| STM32F103xB \|\| STM32F103xE \|\| STM32F103xG */
mbed_official	489:119543c9f674	849
mbed_official	489:119543c9f674	850	#if defined(STM32F101xE) \|\| defined(STM32F103xE) \|\| defined(STM32F101xG) \|\| defined(STM32F103xG) \|\| \
mbed_official	489:119543c9f674	851	defined(STM32F105xC) \|\| defined(STM32F107xC)
mbed_official	489:119543c9f674	852	#define __HAL_RCC_TIM5_CLK_ENABLE() do { \
mbed_official	489:119543c9f674	853	__IO uint32_t tmpreg; \
mbed_official	489:119543c9f674	854	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
mbed_official	489:119543c9f674	855	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	489:119543c9f674	856	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
mbed_official	489:119543c9f674	857	UNUSED(tmpreg); \
mbed_official	489:119543c9f674	858	} while(0)
mbed_official	489:119543c9f674	859
mbed_official	489:119543c9f674	860	#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
mbed_official	489:119543c9f674	861	__IO uint32_t tmpreg; \
mbed_official	489:119543c9f674	862	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
mbed_official	489:119543c9f674	863	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	489:119543c9f674	864	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
mbed_official	489:119543c9f674	865	UNUSED(tmpreg); \
mbed_official	489:119543c9f674	866	} while(0)
mbed_official	489:119543c9f674	867
mbed_official	489:119543c9f674	868	#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
mbed_official	489:119543c9f674	869	__IO uint32_t tmpreg; \
mbed_official	489:119543c9f674	870	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
mbed_official	489:119543c9f674	871	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	489:119543c9f674	872	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
mbed_official	489:119543c9f674	873	UNUSED(tmpreg); \
mbed_official	489:119543c9f674	874	} while(0)
mbed_official	489:119543c9f674	875
mbed_official	489:119543c9f674	876	#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
mbed_official	489:119543c9f674	877	__IO uint32_t tmpreg; \
mbed_official	489:119543c9f674	878	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
mbed_official	489:119543c9f674	879	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	489:119543c9f674	880	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
mbed_official	489:119543c9f674	881	UNUSED(tmpreg); \
mbed_official	489:119543c9f674	882	} while(0)
mbed_official	489:119543c9f674	883
mbed_official	489:119543c9f674	884	#define __HAL_RCC_UART4_CLK_ENABLE() do { \
mbed_official	489:119543c9f674	885	__IO uint32_t tmpreg; \
mbed_official	489:119543c9f674	886	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
mbed_official	489:119543c9f674	887	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	489:119543c9f674	888	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
mbed_official	489:119543c9f674	889	UNUSED(tmpreg); \
mbed_official	489:119543c9f674	890	} while(0)
mbed_official	489:119543c9f674	891
mbed_official	489:119543c9f674	892	#define __HAL_RCC_UART5_CLK_ENABLE() do { \
mbed_official	489:119543c9f674	893	__IO uint32_t tmpreg; \
mbed_official	489:119543c9f674	894	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
mbed_official	489:119543c9f674	895	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	489:119543c9f674	896	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
mbed_official	489:119543c9f674	897	UNUSED(tmpreg); \
mbed_official	489:119543c9f674	898	} while(0)
mbed_official	489:119543c9f674	899
mbed_official	489:119543c9f674	900	#define __HAL_RCC_DAC_CLK_ENABLE() do { \
mbed_official	489:119543c9f674	901	__IO uint32_t tmpreg; \
mbed_official	489:119543c9f674	902	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
mbed_official	489:119543c9f674	903	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	489:119543c9f674	904	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
mbed_official	489:119543c9f674	905	UNUSED(tmpreg); \
mbed_official	489:119543c9f674	906	} while(0)
mbed_official	489:119543c9f674	907
mbed_official	489:119543c9f674	908	#define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
mbed_official	489:119543c9f674	909	#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
mbed_official	489:119543c9f674	910	#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
mbed_official	489:119543c9f674	911	#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
mbed_official	489:119543c9f674	912	#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
mbed_official	489:119543c9f674	913	#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
mbed_official	489:119543c9f674	914	#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
mbed_official	489:119543c9f674	915	#endif /* STM32F101xE \|\| STM32F103xE \|\| STM32F101xG \|\| (...) \|\| STM32F105xC \|\| STM32F107xC */
mbed_official	489:119543c9f674	916
mbed_official	489:119543c9f674	917	#if defined(STM32F100xB) \|\| defined (STM32F100xE)
mbed_official	489:119543c9f674	918	#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
mbed_official	489:119543c9f674	919	__IO uint32_t tmpreg; \
mbed_official	489:119543c9f674	920	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
mbed_official	489:119543c9f674	921	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	489:119543c9f674	922	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
mbed_official	489:119543c9f674	923	UNUSED(tmpreg); \
mbed_official	489:119543c9f674	924	} while(0)
mbed_official	489:119543c9f674	925
mbed_official	489:119543c9f674	926	#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
mbed_official	489:119543c9f674	927	__IO uint32_t tmpreg; \
mbed_official	489:119543c9f674	928	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
mbed_official	489:119543c9f674	929	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	489:119543c9f674	930	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
mbed_official	489:119543c9f674	931	UNUSED(tmpreg); \
mbed_official	489:119543c9f674	932	} while(0)
mbed_official	489:119543c9f674	933
mbed_official	489:119543c9f674	934	#define __HAL_RCC_DAC_CLK_ENABLE() do { \
mbed_official	489:119543c9f674	935	__IO uint32_t tmpreg; \
mbed_official	489:119543c9f674	936	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
mbed_official	489:119543c9f674	937	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	489:119543c9f674	938	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
mbed_official	489:119543c9f674	939	UNUSED(tmpreg); \
mbed_official	489:119543c9f674	940	} while(0)
mbed_official	489:119543c9f674	941
mbed_official	489:119543c9f674	942	#define __HAL_RCC_CEC_CLK_ENABLE() do { \
mbed_official	489:119543c9f674	943	__IO uint32_t tmpreg; \
mbed_official	489:119543c9f674	944	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
mbed_official	489:119543c9f674	945	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	489:119543c9f674	946	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
mbed_official	489:119543c9f674	947	UNUSED(tmpreg); \
mbed_official	489:119543c9f674	948	} while(0)
mbed_official	489:119543c9f674	949
mbed_official	489:119543c9f674	950	#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
mbed_official	489:119543c9f674	951	#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
mbed_official	489:119543c9f674	952	#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
mbed_official	489:119543c9f674	953	#define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))
mbed_official	489:119543c9f674	954	#endif /* STM32F100xB \|\| STM32F100xE */
mbed_official	489:119543c9f674	955
mbed_official	489:119543c9f674	956	#ifdef STM32F100xE
mbed_official	489:119543c9f674	957	#define __HAL_RCC_TIM5_CLK_ENABLE() do { \
mbed_official	489:119543c9f674	958	__IO uint32_t tmpreg; \
mbed_official	489:119543c9f674	959	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
mbed_official	489:119543c9f674	960	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	489:119543c9f674	961	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
mbed_official	489:119543c9f674	962	UNUSED(tmpreg); \
mbed_official	489:119543c9f674	963	} while(0)
mbed_official	489:119543c9f674	964
mbed_official	489:119543c9f674	965	#define __HAL_RCC_TIM12_CLK_ENABLE() do { \
mbed_official	489:119543c9f674	966	__IO uint32_t tmpreg; \
mbed_official	489:119543c9f674	967	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
mbed_official	489:119543c9f674	968	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	489:119543c9f674	969	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
mbed_official	489:119543c9f674	970	UNUSED(tmpreg); \
mbed_official	489:119543c9f674	971	} while(0)
mbed_official	489:119543c9f674	972
mbed_official	489:119543c9f674	973	#define __HAL_RCC_TIM13_CLK_ENABLE() do { \
mbed_official	489:119543c9f674	974	__IO uint32_t tmpreg; \
mbed_official	489:119543c9f674	975	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
mbed_official	489:119543c9f674	976	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	489:119543c9f674	977	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
mbed_official	489:119543c9f674	978	UNUSED(tmpreg); \
mbed_official	489:119543c9f674	979	} while(0)
mbed_official	489:119543c9f674	980
mbed_official	489:119543c9f674	981	#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
mbed_official	489:119543c9f674	982	__IO uint32_t tmpreg; \
mbed_official	489:119543c9f674	983	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
mbed_official	489:119543c9f674	984	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	489:119543c9f674	985	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
mbed_official	489:119543c9f674	986	UNUSED(tmpreg); \
mbed_official	489:119543c9f674	987	} while(0)
mbed_official	489:119543c9f674	988
mbed_official	489:119543c9f674	989	#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
mbed_official	489:119543c9f674	990	__IO uint32_t tmpreg; \
mbed_official	489:119543c9f674	991	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
mbed_official	489:119543c9f674	992	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	489:119543c9f674	993	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
mbed_official	489:119543c9f674	994	UNUSED(tmpreg); \
mbed_official	489:119543c9f674	995	} while(0)
mbed_official	489:119543c9f674	996
mbed_official	489:119543c9f674	997	#define __HAL_RCC_UART4_CLK_ENABLE() do { \
mbed_official	489:119543c9f674	998	__IO uint32_t tmpreg; \
mbed_official	489:119543c9f674	999	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
mbed_official	489:119543c9f674	1000	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	489:119543c9f674	1001	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
mbed_official	489:119543c9f674	1002	UNUSED(tmpreg); \
mbed_official	489:119543c9f674	1003	} while(0)
mbed_official	489:119543c9f674	1004
mbed_official	489:119543c9f674	1005	#define __HAL_RCC_UART5_CLK_ENABLE() do { \
mbed_official	489:119543c9f674	1006	__IO uint32_t tmpreg; \
mbed_official	489:119543c9f674	1007	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
mbed_official	489:119543c9f674	1008	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	489:119543c9f674	1009	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
mbed_official	489:119543c9f674	1010	UNUSED(tmpreg); \
mbed_official	489:119543c9f674	1011	} while(0)
mbed_official	489:119543c9f674	1012
mbed_official	489:119543c9f674	1013	#define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
mbed_official	489:119543c9f674	1014	#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
mbed_official	489:119543c9f674	1015	#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
mbed_official	489:119543c9f674	1016	#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
mbed_official	489:119543c9f674	1017	#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
mbed_official	489:119543c9f674	1018	#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
mbed_official	489:119543c9f674	1019	#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
mbed_official	489:119543c9f674	1020	#endif /* STM32F100xE */
mbed_official	489:119543c9f674	1021
mbed_official	489:119543c9f674	1022	#if defined(STM32F105xC) \|\| defined(STM32F107xC)
mbed_official	489:119543c9f674	1023	#define __HAL_RCC_CAN2_CLK_ENABLE() do { \
mbed_official	489:119543c9f674	1024	__IO uint32_t tmpreg; \
mbed_official	489:119543c9f674	1025	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
mbed_official	489:119543c9f674	1026	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	489:119543c9f674	1027	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
mbed_official	489:119543c9f674	1028	UNUSED(tmpreg); \
mbed_official	489:119543c9f674	1029	} while(0)
mbed_official	489:119543c9f674	1030
mbed_official	489:119543c9f674	1031	#define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
mbed_official	489:119543c9f674	1032	#endif /* STM32F105xC \|\| STM32F107xC */
mbed_official	489:119543c9f674	1033
mbed_official	489:119543c9f674	1034	#if defined(STM32F101xG) \|\| defined(STM32F103xG)
mbed_official	489:119543c9f674	1035	#define __HAL_RCC_TIM12_CLK_ENABLE() do { \
mbed_official	489:119543c9f674	1036	__IO uint32_t tmpreg; \
mbed_official	489:119543c9f674	1037	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
mbed_official	489:119543c9f674	1038	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	489:119543c9f674	1039	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
mbed_official	489:119543c9f674	1040	UNUSED(tmpreg); \
mbed_official	489:119543c9f674	1041	} while(0)
mbed_official	489:119543c9f674	1042
mbed_official	489:119543c9f674	1043	#define __HAL_RCC_TIM13_CLK_ENABLE() do { \
mbed_official	489:119543c9f674	1044	__IO uint32_t tmpreg; \
mbed_official	489:119543c9f674	1045	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
mbed_official	489:119543c9f674	1046	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	489:119543c9f674	1047	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
mbed_official	489:119543c9f674	1048	UNUSED(tmpreg); \
mbed_official	489:119543c9f674	1049	} while(0)
mbed_official	489:119543c9f674	1050
mbed_official	489:119543c9f674	1051	#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
mbed_official	489:119543c9f674	1052	__IO uint32_t tmpreg; \
mbed_official	489:119543c9f674	1053	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
mbed_official	489:119543c9f674	1054	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	489:119543c9f674	1055	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
mbed_official	489:119543c9f674	1056	UNUSED(tmpreg); \
mbed_official	489:119543c9f674	1057	} while(0)
mbed_official	489:119543c9f674	1058
mbed_official	489:119543c9f674	1059	#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
mbed_official	489:119543c9f674	1060	#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
mbed_official	489:119543c9f674	1061	#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
mbed_official	489:119543c9f674	1062	#endif /* STM32F101xG \|\| STM32F103xG*/
mbed_official	489:119543c9f674	1063
mbed_official	489:119543c9f674	1064	/**
mbed_official	489:119543c9f674	1065	* @}
mbed_official	489:119543c9f674	1066	*/
mbed_official	489:119543c9f674	1067
mbed_official	489:119543c9f674	1068	/** @defgroup RCCEx_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
mbed_official	489:119543c9f674	1069	* @brief Get the enable or disable status of the APB1 peripheral clock.
mbed_official	489:119543c9f674	1070	* @note After reset, the peripheral clock (used for registers read/write access)
mbed_official	489:119543c9f674	1071	* is disabled and the application software has to enable this clock before
mbed_official	489:119543c9f674	1072	* using it.
mbed_official	489:119543c9f674	1073	* @{
mbed_official	489:119543c9f674	1074	*/
mbed_official	489:119543c9f674	1075
mbed_official	489:119543c9f674	1076	#if defined(STM32F103x6) \|\| defined(STM32F103xB) \|\| defined(STM32F103xE) \|\| defined(STM32F103xG) \|\| \
mbed_official	489:119543c9f674	1077	defined(STM32F105xC) \|\|defined (STM32F107xC)
mbed_official	489:119543c9f674	1078	#define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET)
mbed_official	489:119543c9f674	1079	#define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)
mbed_official	489:119543c9f674	1080	#endif /* STM32F103x6 \|\| STM32F103xB \|\| STM32F103xE \|\| STM32F103xG \|\| STM32F105xC \|\| STM32F107xC */
mbed_official	489:119543c9f674	1081	#if defined(STM32F100xB) \|\| defined(STM32F100xE) \|\| defined(STM32F101xB) \|\| defined(STM32F101xE) \|\| \
mbed_official	489:119543c9f674	1082	defined(STM32F101xG) \|\| defined(STM32F102xB) \|\| defined(STM32F103xB) \|\| defined(STM32F103xE) \|\| \
mbed_official	489:119543c9f674	1083	defined(STM32F103xG) \|\| defined(STM32F105xC) \|\| defined(STM32F107xC)
mbed_official	489:119543c9f674	1084	#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
mbed_official	489:119543c9f674	1085	#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
mbed_official	489:119543c9f674	1086	#define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET)
mbed_official	489:119543c9f674	1087	#define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET)
mbed_official	489:119543c9f674	1088	#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
mbed_official	489:119543c9f674	1089	#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
mbed_official	489:119543c9f674	1090	#define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET)
mbed_official	489:119543c9f674	1091	#define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET)
mbed_official	489:119543c9f674	1092	#endif /* STM32F100xB \|\| STM32F101xB \|\| STM32F101xE \|\| (...) \|\| STM32F105xC \|\| STM32F107xC */
mbed_official	489:119543c9f674	1093	#if defined(STM32F102x6) \|\| defined(STM32F102xB) \|\| defined(STM32F103x6) \|\| defined(STM32F103xB) \|\| defined(STM32F103xE) \|\| defined(STM32F103xG)
mbed_official	489:119543c9f674	1094	#define __HAL_RCC_USB_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) != RESET)
mbed_official	489:119543c9f674	1095	#define __HAL_RCC_USB_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USBEN)) == RESET)
mbed_official	489:119543c9f674	1096	#endif /* STM32F102x6 \|\| STM32F102xB \|\| STM32F103x6 \|\| STM32F103xB \|\| STM32F103xE \|\| STM32F103xG */
mbed_official	489:119543c9f674	1097	#if defined(STM32F101xE) \|\| defined(STM32F103xE) \|\| defined(STM32F101xG) \|\| defined(STM32F103xG) \|\| \
mbed_official	489:119543c9f674	1098	defined(STM32F105xC) \|\| defined(STM32F107xC)
mbed_official	489:119543c9f674	1099	#define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET)
mbed_official	489:119543c9f674	1100	#define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET)
mbed_official	489:119543c9f674	1101	#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
mbed_official	489:119543c9f674	1102	#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
mbed_official	489:119543c9f674	1103	#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
mbed_official	489:119543c9f674	1104	#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
mbed_official	489:119543c9f674	1105	#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
mbed_official	489:119543c9f674	1106	#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
mbed_official	489:119543c9f674	1107	#define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)
mbed_official	489:119543c9f674	1108	#define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)
mbed_official	489:119543c9f674	1109	#define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)
mbed_official	489:119543c9f674	1110	#define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)
mbed_official	489:119543c9f674	1111	#define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
mbed_official	489:119543c9f674	1112	#define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)
mbed_official	489:119543c9f674	1113	#endif /* STM32F101xE \|\| STM32F103xE \|\| STM32F101xG \|\| (...) \|\| STM32F105xC \|\| STM32F107xC */
mbed_official	489:119543c9f674	1114	#if defined(STM32F100xB) \|\| defined (STM32F100xE)
mbed_official	489:119543c9f674	1115	#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
mbed_official	489:119543c9f674	1116	#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
mbed_official	489:119543c9f674	1117	#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
mbed_official	489:119543c9f674	1118	#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
mbed_official	489:119543c9f674	1119	#define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
mbed_official	489:119543c9f674	1120	#define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)
mbed_official	489:119543c9f674	1121	#define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET)
mbed_official	489:119543c9f674	1122	#define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET)
mbed_official	489:119543c9f674	1123	#endif /* STM32F100xB \|\| STM32F100xE */
mbed_official	489:119543c9f674	1124	#ifdef STM32F100xE
mbed_official	489:119543c9f674	1125	#define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET)
mbed_official	489:119543c9f674	1126	#define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET)
mbed_official	489:119543c9f674	1127	#define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
mbed_official	489:119543c9f674	1128	#define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
mbed_official	489:119543c9f674	1129	#define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
mbed_official	489:119543c9f674	1130	#define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
mbed_official	489:119543c9f674	1131	#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
mbed_official	489:119543c9f674	1132	#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
mbed_official	489:119543c9f674	1133	#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
mbed_official	489:119543c9f674	1134	#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
mbed_official	489:119543c9f674	1135	#define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)
mbed_official	489:119543c9f674	1136	#define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)
mbed_official	489:119543c9f674	1137	#define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)
mbed_official	489:119543c9f674	1138	#define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)
mbed_official	489:119543c9f674	1139	#define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET)
mbed_official	489:119543c9f674	1140	#define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET)
mbed_official	489:119543c9f674	1141	#endif /* STM32F100xE */
mbed_official	489:119543c9f674	1142	#if defined(STM32F105xC) \|\| defined(STM32F107xC)
mbed_official	489:119543c9f674	1143	#define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
mbed_official	489:119543c9f674	1144	#define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
mbed_official	489:119543c9f674	1145	#endif /* STM32F105xC \|\| STM32F107xC */
mbed_official	489:119543c9f674	1146	#if defined(STM32F101xG) \|\| defined(STM32F103xG)
mbed_official	489:119543c9f674	1147	#define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
mbed_official	489:119543c9f674	1148	#define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
mbed_official	489:119543c9f674	1149	#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
mbed_official	489:119543c9f674	1150	#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
mbed_official	489:119543c9f674	1151	#endif /* STM32F101xG \|\| STM32F103xG*/
mbed_official	489:119543c9f674	1152
mbed_official	489:119543c9f674	1153	/**
mbed_official	489:119543c9f674	1154	* @}
mbed_official	489:119543c9f674	1155	*/
mbed_official	489:119543c9f674	1156
mbed_official	489:119543c9f674	1157	/** @defgroup RCCEx_APB2_Clock_Enable_Disable APB2 Clock Enable Disable
mbed_official	489:119543c9f674	1158	* @brief Enable or disable the High Speed APB (APB2) peripheral clock.
mbed_official	489:119543c9f674	1159	* @note After reset, the peripheral clock (used for registers read/write access)
mbed_official	489:119543c9f674	1160	* is disabled and the application software has to enable this clock before
mbed_official	489:119543c9f674	1161	* using it.
mbed_official	489:119543c9f674	1162	* @{
mbed_official	489:119543c9f674	1163	*/
mbed_official	489:119543c9f674	1164
mbed_official	489:119543c9f674	1165	#if defined(STM32F101xG) \|\| defined(STM32F103x6) \|\| defined(STM32F103xB) \|\| defined(STM32F105xC) \|\| \
mbed_official	489:119543c9f674	1166	defined(STM32F107xC) \|\| defined(STM32F103xE) \|\| defined(STM32F103xG)
mbed_official	489:119543c9f674	1167	#define __HAL_RCC_ADC2_CLK_ENABLE() do { \
mbed_official	489:119543c9f674	1168	__IO uint32_t tmpreg; \
mbed_official	489:119543c9f674	1169	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
mbed_official	489:119543c9f674	1170	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	489:119543c9f674	1171	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
mbed_official	489:119543c9f674	1172	UNUSED(tmpreg); \
mbed_official	489:119543c9f674	1173	} while(0)
mbed_official	489:119543c9f674	1174
mbed_official	489:119543c9f674	1175	#define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
mbed_official	489:119543c9f674	1176	#endif /* STM32F101xG \|\| STM32F103x6 \|\| STM32F103xB \|\| STM32F105xC \|\| STM32F107xC \|\| STM32F103xE \|\| STM32F103xG */
mbed_official	489:119543c9f674	1177
mbed_official	489:119543c9f674	1178	#if defined (STM32F100xB) \|\| defined (STM32F100xE)
mbed_official	489:119543c9f674	1179	#define __HAL_RCC_TIM15_CLK_ENABLE() do { \
mbed_official	489:119543c9f674	1180	__IO uint32_t tmpreg; \
mbed_official	489:119543c9f674	1181	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\
mbed_official	489:119543c9f674	1182	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	489:119543c9f674	1183	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\
mbed_official	489:119543c9f674	1184	UNUSED(tmpreg); \
mbed_official	489:119543c9f674	1185	} while(0)
mbed_official	489:119543c9f674	1186
mbed_official	489:119543c9f674	1187	#define __HAL_RCC_TIM16_CLK_ENABLE() do { \
mbed_official	489:119543c9f674	1188	__IO uint32_t tmpreg; \
mbed_official	489:119543c9f674	1189	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\
mbed_official	489:119543c9f674	1190	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	489:119543c9f674	1191	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\
mbed_official	489:119543c9f674	1192	UNUSED(tmpreg); \
mbed_official	489:119543c9f674	1193	} while(0)
mbed_official	489:119543c9f674	1194
mbed_official	489:119543c9f674	1195	#define __HAL_RCC_TIM17_CLK_ENABLE() do { \
mbed_official	489:119543c9f674	1196	__IO uint32_t tmpreg; \
mbed_official	489:119543c9f674	1197	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\
mbed_official	489:119543c9f674	1198	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	489:119543c9f674	1199	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\
mbed_official	489:119543c9f674	1200	UNUSED(tmpreg); \
mbed_official	489:119543c9f674	1201	} while(0)
mbed_official	489:119543c9f674	1202
mbed_official	489:119543c9f674	1203	#define __HAL_RCC_TIM15_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM15EN))
mbed_official	489:119543c9f674	1204	#define __HAL_RCC_TIM16_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM16EN))
mbed_official	489:119543c9f674	1205	#define __HAL_RCC_TIM17_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM17EN))
mbed_official	489:119543c9f674	1206	#endif /* STM32F100xB \|\| STM32F100xE */
mbed_official	489:119543c9f674	1207
mbed_official	489:119543c9f674	1208	#if defined(STM32F100xE) \|\| defined(STM32F101xB) \|\| defined(STM32F101xE) \|\| defined(STM32F101xG) \|\| \
mbed_official	489:119543c9f674	1209	defined(STM32F100xB) \|\| defined(STM32F103xB) \|\| defined(STM32F103xE) \|\| defined(STM32F103xG) \|\| \
mbed_official	489:119543c9f674	1210	defined(STM32F105xC) \|\| defined(STM32F107xC)
mbed_official	489:119543c9f674	1211	#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
mbed_official	489:119543c9f674	1212	__IO uint32_t tmpreg; \
mbed_official	489:119543c9f674	1213	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPEEN);\
mbed_official	489:119543c9f674	1214	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	489:119543c9f674	1215	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPEEN);\
mbed_official	489:119543c9f674	1216	UNUSED(tmpreg); \
mbed_official	489:119543c9f674	1217	} while(0)
mbed_official	489:119543c9f674	1218
mbed_official	489:119543c9f674	1219	#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPEEN))
mbed_official	489:119543c9f674	1220	#endif /* STM32F101x6 \|\| STM32F101xB \|\| STM32F101xE \|\| (...) \|\| STM32F105xC \|\| STM32F107xC */
mbed_official	489:119543c9f674	1221
mbed_official	489:119543c9f674	1222	#if defined (STM32F101xE) \|\| defined (STM32F103xE) \|\| defined(STM32F101xG) \|\| defined(STM32F103xG)
mbed_official	489:119543c9f674	1223	#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
mbed_official	489:119543c9f674	1224	__IO uint32_t tmpreg; \
mbed_official	489:119543c9f674	1225	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPFEN);\
mbed_official	489:119543c9f674	1226	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	489:119543c9f674	1227	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPFEN);\
mbed_official	489:119543c9f674	1228	UNUSED(tmpreg); \
mbed_official	489:119543c9f674	1229	} while(0)
mbed_official	489:119543c9f674	1230
mbed_official	489:119543c9f674	1231	#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
mbed_official	489:119543c9f674	1232	__IO uint32_t tmpreg; \
mbed_official	489:119543c9f674	1233	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPGEN);\
mbed_official	489:119543c9f674	1234	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	489:119543c9f674	1235	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPGEN);\
mbed_official	489:119543c9f674	1236	UNUSED(tmpreg); \
mbed_official	489:119543c9f674	1237	} while(0)
mbed_official	489:119543c9f674	1238
mbed_official	489:119543c9f674	1239	#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPFEN))
mbed_official	489:119543c9f674	1240	#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPGEN))
mbed_official	489:119543c9f674	1241	#endif /* STM32F101xE \|\| STM32F103xE \|\| STM32F101xG \|\| STM32F103xG*/
mbed_official	489:119543c9f674	1242
mbed_official	489:119543c9f674	1243	#if defined (STM32F103xE) \|\| defined (STM32F103xG)
mbed_official	489:119543c9f674	1244	#define __HAL_RCC_TIM8_CLK_ENABLE() do { \
mbed_official	489:119543c9f674	1245	__IO uint32_t tmpreg; \
mbed_official	489:119543c9f674	1246	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
mbed_official	489:119543c9f674	1247	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	489:119543c9f674	1248	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
mbed_official	489:119543c9f674	1249	UNUSED(tmpreg); \
mbed_official	489:119543c9f674	1250	} while(0)
mbed_official	489:119543c9f674	1251
mbed_official	489:119543c9f674	1252	#define __HAL_RCC_ADC3_CLK_ENABLE() do { \
mbed_official	489:119543c9f674	1253	__IO uint32_t tmpreg; \
mbed_official	489:119543c9f674	1254	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
mbed_official	489:119543c9f674	1255	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	489:119543c9f674	1256	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
mbed_official	489:119543c9f674	1257	UNUSED(tmpreg); \
mbed_official	489:119543c9f674	1258	} while(0)
mbed_official	489:119543c9f674	1259
mbed_official	489:119543c9f674	1260	#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
mbed_official	489:119543c9f674	1261	#define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
mbed_official	489:119543c9f674	1262	#endif /* STM32F103xE \|\| STM32F103xG */
mbed_official	489:119543c9f674	1263
mbed_official	489:119543c9f674	1264	#if defined (STM32F100xE)
mbed_official	489:119543c9f674	1265	#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
mbed_official	489:119543c9f674	1266	__IO uint32_t tmpreg; \
mbed_official	489:119543c9f674	1267	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPFEN);\
mbed_official	489:119543c9f674	1268	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	489:119543c9f674	1269	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPFEN);\
mbed_official	489:119543c9f674	1270	UNUSED(tmpreg); \
mbed_official	489:119543c9f674	1271	} while(0)
mbed_official	489:119543c9f674	1272
mbed_official	489:119543c9f674	1273	#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
mbed_official	489:119543c9f674	1274	__IO uint32_t tmpreg; \
mbed_official	489:119543c9f674	1275	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPGEN);\
mbed_official	489:119543c9f674	1276	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	489:119543c9f674	1277	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPGEN);\
mbed_official	489:119543c9f674	1278	UNUSED(tmpreg); \
mbed_official	489:119543c9f674	1279	} while(0)
mbed_official	489:119543c9f674	1280
mbed_official	489:119543c9f674	1281	#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPFEN))
mbed_official	489:119543c9f674	1282	#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPGEN))
mbed_official	489:119543c9f674	1283	#endif /* STM32F100xE */
mbed_official	489:119543c9f674	1284
mbed_official	489:119543c9f674	1285	#if defined(STM32F101xG) \|\| defined(STM32F103xG)
mbed_official	489:119543c9f674	1286	#define __HAL_RCC_TIM9_CLK_ENABLE() do { \
mbed_official	489:119543c9f674	1287	__IO uint32_t tmpreg; \
mbed_official	489:119543c9f674	1288	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
mbed_official	489:119543c9f674	1289	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	489:119543c9f674	1290	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
mbed_official	489:119543c9f674	1291	UNUSED(tmpreg); \
mbed_official	489:119543c9f674	1292	} while(0)
mbed_official	489:119543c9f674	1293
mbed_official	489:119543c9f674	1294	#define __HAL_RCC_TIM10_CLK_ENABLE() do { \
mbed_official	489:119543c9f674	1295	__IO uint32_t tmpreg; \
mbed_official	489:119543c9f674	1296	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
mbed_official	489:119543c9f674	1297	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	489:119543c9f674	1298	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
mbed_official	489:119543c9f674	1299	UNUSED(tmpreg); \
mbed_official	489:119543c9f674	1300	} while(0)
mbed_official	489:119543c9f674	1301
mbed_official	489:119543c9f674	1302	#define __HAL_RCC_TIM11_CLK_ENABLE() do { \
mbed_official	489:119543c9f674	1303	__IO uint32_t tmpreg; \
mbed_official	489:119543c9f674	1304	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
mbed_official	489:119543c9f674	1305	/* Delay after an RCC peripheral clock enabling */ \
mbed_official	489:119543c9f674	1306	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
mbed_official	489:119543c9f674	1307	UNUSED(tmpreg); \
mbed_official	489:119543c9f674	1308	} while(0)
mbed_official	489:119543c9f674	1309
mbed_official	489:119543c9f674	1310	#define __HAL_RCC_TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))
mbed_official	489:119543c9f674	1311	#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
mbed_official	489:119543c9f674	1312	#define __HAL_RCC_TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))
mbed_official	489:119543c9f674	1313	#endif /* STM32F101xG \|\| STM32F103xG */
mbed_official	489:119543c9f674	1314
mbed_official	489:119543c9f674	1315	/**
mbed_official	489:119543c9f674	1316	* @}
mbed_official	489:119543c9f674	1317	*/
mbed_official	489:119543c9f674	1318
mbed_official	489:119543c9f674	1319	/** @defgroup RCCEx_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
mbed_official	489:119543c9f674	1320	* @brief Get the enable or disable status of the APB2 peripheral clock.
mbed_official	489:119543c9f674	1321	* @note After reset, the peripheral clock (used for registers read/write access)
mbed_official	489:119543c9f674	1322	* is disabled and the application software has to enable this clock before
mbed_official	489:119543c9f674	1323	* using it.
mbed_official	489:119543c9f674	1324	* @{
mbed_official	489:119543c9f674	1325	*/
mbed_official	489:119543c9f674	1326
mbed_official	489:119543c9f674	1327	#if defined(STM32F101xG) \|\| defined(STM32F103x6) \|\| defined(STM32F103xB) \|\| defined(STM32F105xC) \|\| \
mbed_official	489:119543c9f674	1328	defined(STM32F107xC) \|\| defined(STM32F103xE) \|\| defined(STM32F103xG)
mbed_official	489:119543c9f674	1329	#define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET)
mbed_official	489:119543c9f674	1330	#define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET)
mbed_official	489:119543c9f674	1331	#endif /* STM32F101xG \|\| STM32F103x6 \|\| STM32F103xB \|\| STM32F105xC \|\| STM32F107xC \|\| STM32F103xE \|\| STM32F103xG */
mbed_official	489:119543c9f674	1332	#if defined (STM32F100xB) \|\| defined (STM32F100xE)
mbed_official	489:119543c9f674	1333	#define __HAL_RCC_TIM15_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) != RESET)
mbed_official	489:119543c9f674	1334	#define __HAL_RCC_TIM15_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM15EN)) == RESET)
mbed_official	489:119543c9f674	1335	#define __HAL_RCC_TIM16_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) != RESET)
mbed_official	489:119543c9f674	1336	#define __HAL_RCC_TIM16_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM16EN)) == RESET)
mbed_official	489:119543c9f674	1337	#define __HAL_RCC_TIM17_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) != RESET)
mbed_official	489:119543c9f674	1338	#define __HAL_RCC_TIM17_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM17EN)) == RESET)
mbed_official	489:119543c9f674	1339	#endif /* STM32F100xB \|\| STM32F100xE */
mbed_official	489:119543c9f674	1340	#if defined(STM32F100xE) \|\| defined(STM32F101xB) \|\| defined(STM32F101xE) \|\| defined(STM32F101xG) \|\| \
mbed_official	489:119543c9f674	1341	defined(STM32F100xB) \|\| defined(STM32F103xB) \|\| defined(STM32F103xE) \|\| defined(STM32F103xG) \|\| \
mbed_official	489:119543c9f674	1342	defined(STM32F105xC) \|\| defined(STM32F107xC)
mbed_official	489:119543c9f674	1343	#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPEEN)) != RESET)
mbed_official	489:119543c9f674	1344	#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPEEN)) == RESET)
mbed_official	489:119543c9f674	1345	#endif /* STM32F101x6 \|\| STM32F101xB \|\| STM32F101xE \|\| (...) \|\| STM32F105xC \|\| STM32F107xC */
mbed_official	489:119543c9f674	1346	#if defined (STM32F101xE) \|\| defined (STM32F103xE) \|\| defined(STM32F101xG) \|\| defined(STM32F103xG)
mbed_official	489:119543c9f674	1347	#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) != RESET)
mbed_official	489:119543c9f674	1348	#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) == RESET)
mbed_official	489:119543c9f674	1349	#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) != RESET)
mbed_official	489:119543c9f674	1350	#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) == RESET)
mbed_official	489:119543c9f674	1351	#endif /* STM32F101xE \|\| STM32F103xE \|\| STM32F101xG \|\| STM32F103xG*/
mbed_official	489:119543c9f674	1352	#if defined (STM32F103xE) \|\| defined (STM32F103xG)
mbed_official	489:119543c9f674	1353	#define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)
mbed_official	489:119543c9f674	1354	#define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)
mbed_official	489:119543c9f674	1355	#define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET)
mbed_official	489:119543c9f674	1356	#define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET)
mbed_official	489:119543c9f674	1357	#endif /* STM32F103xE \|\| STM32F103xG */
mbed_official	489:119543c9f674	1358	#if defined (STM32F100xE)
mbed_official	489:119543c9f674	1359	#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) != RESET)
mbed_official	489:119543c9f674	1360	#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPFEN)) == RESET)
mbed_official	489:119543c9f674	1361	#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) != RESET)
mbed_official	489:119543c9f674	1362	#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPGEN)) == RESET)
mbed_official	489:119543c9f674	1363	#endif /* STM32F100xE */
mbed_official	489:119543c9f674	1364	#if defined(STM32F101xG) \|\| defined(STM32F103xG)
mbed_official	489:119543c9f674	1365	#define __HAL_RCC_TIM9_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) != RESET)
mbed_official	489:119543c9f674	1366	#define __HAL_RCC_TIM9_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) == RESET)
mbed_official	489:119543c9f674	1367	#define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)
mbed_official	489:119543c9f674	1368	#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)
mbed_official	489:119543c9f674	1369	#define __HAL_RCC_TIM11_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) != RESET)
mbed_official	489:119543c9f674	1370	#define __HAL_RCC_TIM11_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) == RESET)
mbed_official	489:119543c9f674	1371	#endif /* STM32F101xG \|\| STM32F103xG */
mbed_official	489:119543c9f674	1372
mbed_official	489:119543c9f674	1373	/**
mbed_official	489:119543c9f674	1374	* @}
mbed_official	489:119543c9f674	1375	*/
mbed_official	489:119543c9f674	1376
mbed_official	489:119543c9f674	1377	#if defined(STM32F105xC) \|\| defined(STM32F107xC)
mbed_official	489:119543c9f674	1378	/** @defgroup RCCEx_Peripheral_Clock_Force_Release Peripheral Clock Force Release
mbed_official	489:119543c9f674	1379	* @brief Force or release AHB peripheral reset.
mbed_official	489:119543c9f674	1380	* @{
mbed_official	489:119543c9f674	1381	*/
mbed_official	489:119543c9f674	1382	#define __HAL_RCC_AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFF)
mbed_official	489:119543c9f674	1383	#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_OTGFSRST))
mbed_official	489:119543c9f674	1384	#if defined(STM32F107xC)
mbed_official	489:119543c9f674	1385	#define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_ETHMACRST))
mbed_official	489:119543c9f674	1386	#endif /* STM32F107xC */
mbed_official	489:119543c9f674	1387
mbed_official	489:119543c9f674	1388	#define __HAL_RCC_AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00)
mbed_official	489:119543c9f674	1389	#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_OTGFSRST))
mbed_official	489:119543c9f674	1390	#if defined(STM32F107xC)
mbed_official	489:119543c9f674	1391	#define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_ETHMACRST))
mbed_official	489:119543c9f674	1392	#endif /* STM32F107xC */
mbed_official	489:119543c9f674	1393
mbed_official	489:119543c9f674	1394	/**
mbed_official	489:119543c9f674	1395	* @}
mbed_official	489:119543c9f674	1396	*/
mbed_official	489:119543c9f674	1397	#endif /* STM32F105xC \|\| STM32F107xC */
mbed_official	489:119543c9f674	1398
mbed_official	489:119543c9f674	1399	/** @defgroup RCCEx_APB1_Force_Release_Reset APB1 Force Release Reset
mbed_official	489:119543c9f674	1400	* @brief Force or release APB1 peripheral reset.
mbed_official	489:119543c9f674	1401	* @{
mbed_official	489:119543c9f674	1402	*/
mbed_official	489:119543c9f674	1403
mbed_official	489:119543c9f674	1404	#if defined(STM32F103x6) \|\| defined(STM32F103xB) \|\| defined(STM32F103xE) \|\| defined(STM32F103xG) \|\| \
mbed_official	489:119543c9f674	1405	defined(STM32F105xC) \|\|defined (STM32F107xC)
mbed_official	489:119543c9f674	1406	#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN1RST))
mbed_official	489:119543c9f674	1407
mbed_official	489:119543c9f674	1408	#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
mbed_official	489:119543c9f674	1409	#endif /* STM32F103x6 \|\| STM32F103xB \|\| STM32F103xE \|\| STM32F103xG \|\| STM32F105xC \|\| STM32F107xC */
mbed_official	489:119543c9f674	1410
mbed_official	489:119543c9f674	1411	#if defined(STM32F100xB) \|\| defined(STM32F100xE) \|\| defined(STM32F101xB) \|\| defined(STM32F101xE) \|\| \
mbed_official	489:119543c9f674	1412	defined(STM32F101xG) \|\| defined(STM32F102xB) \|\| defined(STM32F103xB) \|\| defined(STM32F103xE) \|\| \
mbed_official	489:119543c9f674	1413	defined(STM32F103xG) \|\| defined(STM32F105xC) \|\| defined(STM32F107xC)
mbed_official	489:119543c9f674	1414	#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM4RST))
mbed_official	489:119543c9f674	1415	#define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI2RST))
mbed_official	489:119543c9f674	1416	#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART3RST))
mbed_official	489:119543c9f674	1417	#define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C2RST))
mbed_official	489:119543c9f674	1418
mbed_official	489:119543c9f674	1419	#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
mbed_official	489:119543c9f674	1420	#define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
mbed_official	489:119543c9f674	1421	#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
mbed_official	489:119543c9f674	1422	#define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
mbed_official	489:119543c9f674	1423	#endif /* STM32F100xB \|\| STM32F101xB \|\| STM32F101xE \|\| (...) \|\| STM32F105xC \|\| STM32F107xC */
mbed_official	489:119543c9f674	1424
mbed_official	489:119543c9f674	1425	#if defined(STM32F102x6) \|\| defined(STM32F102xB) \|\| defined(STM32F103x6) \|\| defined(STM32F103xB) \|\| defined(STM32F103xE) \|\| defined(STM32F103xG)
mbed_official	489:119543c9f674	1426	#define __HAL_RCC_USB_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USBRST))
mbed_official	489:119543c9f674	1427	#define __HAL_RCC_USB_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USBRST))
mbed_official	489:119543c9f674	1428	#endif /* STM32F102x6 \|\| STM32F102xB \|\| STM32F103x6 \|\| STM32F103xB \|\| STM32F103xE \|\| STM32F103xG */
mbed_official	489:119543c9f674	1429
mbed_official	489:119543c9f674	1430	#if defined(STM32F101xE) \|\| defined(STM32F103xE) \|\| defined(STM32F101xG) \|\| defined(STM32F103xG) \|\| \
mbed_official	489:119543c9f674	1431	defined(STM32F105xC) \|\| defined(STM32F107xC)
mbed_official	489:119543c9f674	1432	#define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM5RST))
mbed_official	489:119543c9f674	1433	#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM6RST))
mbed_official	489:119543c9f674	1434	#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM7RST))
mbed_official	489:119543c9f674	1435	#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI3RST))
mbed_official	489:119543c9f674	1436	#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART4RST))
mbed_official	489:119543c9f674	1437	#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART5RST))
mbed_official	489:119543c9f674	1438	#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_DACRST))
mbed_official	489:119543c9f674	1439
mbed_official	489:119543c9f674	1440	#define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
mbed_official	489:119543c9f674	1441	#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
mbed_official	489:119543c9f674	1442	#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
mbed_official	489:119543c9f674	1443	#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
mbed_official	489:119543c9f674	1444	#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
mbed_official	489:119543c9f674	1445	#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
mbed_official	489:119543c9f674	1446	#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
mbed_official	489:119543c9f674	1447	#endif /* STM32F101xE \|\| STM32F103xE \|\| STM32F101xG \|\| (...) \|\| STM32F105xC \|\| STM32F107xC */
mbed_official	489:119543c9f674	1448
mbed_official	489:119543c9f674	1449	#if defined(STM32F100xB) \|\| defined (STM32F100xE)
mbed_official	489:119543c9f674	1450	#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM6RST))
mbed_official	489:119543c9f674	1451	#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM7RST))
mbed_official	489:119543c9f674	1452	#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_DACRST))
mbed_official	489:119543c9f674	1453	#define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CECRST))
mbed_official	489:119543c9f674	1454
mbed_official	489:119543c9f674	1455	#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
mbed_official	489:119543c9f674	1456	#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
mbed_official	489:119543c9f674	1457	#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
mbed_official	489:119543c9f674	1458	#define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST))
mbed_official	489:119543c9f674	1459	#endif /* STM32F100xB \|\| STM32F100xE */
mbed_official	489:119543c9f674	1460
mbed_official	489:119543c9f674	1461	#if defined (STM32F100xE)
mbed_official	489:119543c9f674	1462	#define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM5RST))
mbed_official	489:119543c9f674	1463	#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM12RST))
mbed_official	489:119543c9f674	1464	#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM13RST))
mbed_official	489:119543c9f674	1465	#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM14RST))
mbed_official	489:119543c9f674	1466	#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI3RST))
mbed_official	489:119543c9f674	1467	#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART4RST))
mbed_official	489:119543c9f674	1468	#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART5RST))
mbed_official	489:119543c9f674	1469
mbed_official	489:119543c9f674	1470	#define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
mbed_official	489:119543c9f674	1471	#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
mbed_official	489:119543c9f674	1472	#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
mbed_official	489:119543c9f674	1473	#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
mbed_official	489:119543c9f674	1474	#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
mbed_official	489:119543c9f674	1475	#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
mbed_official	489:119543c9f674	1476	#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
mbed_official	489:119543c9f674	1477	#endif /* STM32F100xE */
mbed_official	489:119543c9f674	1478
mbed_official	489:119543c9f674	1479	#if defined(STM32F105xC) \|\| defined(STM32F107xC)
mbed_official	489:119543c9f674	1480	#define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN2RST))
mbed_official	489:119543c9f674	1481
mbed_official	489:119543c9f674	1482	#define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
mbed_official	489:119543c9f674	1483	#endif /* STM32F105xC \|\| STM32F107xC */
mbed_official	489:119543c9f674	1484
mbed_official	489:119543c9f674	1485	#if defined(STM32F101xG) \|\| defined(STM32F103xG)
mbed_official	489:119543c9f674	1486	#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM12RST))
mbed_official	489:119543c9f674	1487	#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM13RST))
mbed_official	489:119543c9f674	1488	#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM14RST))
mbed_official	489:119543c9f674	1489
mbed_official	489:119543c9f674	1490	#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
mbed_official	489:119543c9f674	1491	#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
mbed_official	489:119543c9f674	1492	#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
mbed_official	489:119543c9f674	1493	#endif /* STM32F101xG \|\| STM32F103xG */
mbed_official	489:119543c9f674	1494
mbed_official	489:119543c9f674	1495	/**
mbed_official	489:119543c9f674	1496	* @}
mbed_official	489:119543c9f674	1497	*/
mbed_official	489:119543c9f674	1498
mbed_official	489:119543c9f674	1499	/** @defgroup RCCEx_APB2_Force_Release_Reset APB2 Force Release Reset
mbed_official	489:119543c9f674	1500	* @brief Force or release APB2 peripheral reset.
mbed_official	489:119543c9f674	1501	* @{
mbed_official	489:119543c9f674	1502	*/
mbed_official	489:119543c9f674	1503
mbed_official	489:119543c9f674	1504	#if defined(STM32F101xG) \|\| defined(STM32F103x6) \|\| defined(STM32F103xB) \|\| defined(STM32F105xC) \|\| \
mbed_official	489:119543c9f674	1505	defined(STM32F107xC) \|\| defined(STM32F103xE) \|\| defined(STM32F103xG)
mbed_official	489:119543c9f674	1506	#define __HAL_RCC_ADC2_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_ADC2RST))
mbed_official	489:119543c9f674	1507
mbed_official	489:119543c9f674	1508	#define __HAL_RCC_ADC2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC2RST))
mbed_official	489:119543c9f674	1509	#endif /* STM32F101xG \|\| STM32F103x6 \|\| STM32F103xB \|\| STM32F105xC \|\| STM32F107xC \|\| STM32F103xE \|\| STM32F103xG */
mbed_official	489:119543c9f674	1510
mbed_official	489:119543c9f674	1511	#if defined (STM32F100xB) \|\| defined (STM32F100xE)
mbed_official	489:119543c9f674	1512	#define __HAL_RCC_TIM15_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM15RST))
mbed_official	489:119543c9f674	1513	#define __HAL_RCC_TIM16_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM16RST))
mbed_official	489:119543c9f674	1514	#define __HAL_RCC_TIM17_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM17RST))
mbed_official	489:119543c9f674	1515
mbed_official	489:119543c9f674	1516	#define __HAL_RCC_TIM15_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM15RST))
mbed_official	489:119543c9f674	1517	#define __HAL_RCC_TIM16_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM16RST))
mbed_official	489:119543c9f674	1518	#define __HAL_RCC_TIM17_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM17RST))
mbed_official	489:119543c9f674	1519	#endif /* STM32F100xB \|\| STM32F100xE */
mbed_official	489:119543c9f674	1520
mbed_official	489:119543c9f674	1521	#if defined(STM32F100xE) \|\| defined(STM32F101xB) \|\| defined(STM32F101xE) \|\| defined(STM32F101xG) \|\| \
mbed_official	489:119543c9f674	1522	defined(STM32F100xB) \|\| defined(STM32F103xB) \|\| defined(STM32F103xE) \|\| defined(STM32F103xG) \|\| \
mbed_official	489:119543c9f674	1523	defined(STM32F105xC) \|\| defined(STM32F107xC)
mbed_official	489:119543c9f674	1524	#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_IOPERST))
mbed_official	489:119543c9f674	1525
mbed_official	489:119543c9f674	1526	#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPERST))
mbed_official	489:119543c9f674	1527	#endif /* STM32F101x6 \|\| STM32F101xB \|\| STM32F101xE \|\| (...) \|\| STM32F105xC \|\| STM32F107xC */
mbed_official	489:119543c9f674	1528
mbed_official	489:119543c9f674	1529	#if defined (STM32F101xE) \|\| defined (STM32F103xE) \|\| defined(STM32F101xG) \|\| defined(STM32F103xG)
mbed_official	489:119543c9f674	1530	#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_IOPFRST))
mbed_official	489:119543c9f674	1531	#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_IOPGRST))
mbed_official	489:119543c9f674	1532
mbed_official	489:119543c9f674	1533	#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPFRST))
mbed_official	489:119543c9f674	1534	#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPGRST))
mbed_official	489:119543c9f674	1535	#endif /* STM32F101xE \|\| STM32F103xE \|\| STM32F101xG \|\| STM32F103xG*/
mbed_official	489:119543c9f674	1536
mbed_official	489:119543c9f674	1537	#if defined (STM32F103xE) \|\| defined (STM32F103xG)
mbed_official	489:119543c9f674	1538	#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM8RST))
mbed_official	489:119543c9f674	1539	#define __HAL_RCC_ADC3_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_ADC3RST))
mbed_official	489:119543c9f674	1540
mbed_official	489:119543c9f674	1541	#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
mbed_official	489:119543c9f674	1542	#define __HAL_RCC_ADC3_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC3RST))
mbed_official	489:119543c9f674	1543	#endif /* STM32F103xE \|\| STM32F103xG */
mbed_official	489:119543c9f674	1544
mbed_official	489:119543c9f674	1545	#if defined (STM32F100xE)
mbed_official	489:119543c9f674	1546	#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_IOPFRST))
mbed_official	489:119543c9f674	1547	#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_IOPGRST))
mbed_official	489:119543c9f674	1548
mbed_official	489:119543c9f674	1549	#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPFRST))
mbed_official	489:119543c9f674	1550	#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPGRST))
mbed_official	489:119543c9f674	1551	#endif /* STM32F100xE */
mbed_official	489:119543c9f674	1552
mbed_official	489:119543c9f674	1553	#if defined(STM32F101xG) \|\| defined(STM32F103xG)
mbed_official	489:119543c9f674	1554	#define __HAL_RCC_TIM9_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM9RST))
mbed_official	489:119543c9f674	1555	#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM10RST))
mbed_official	489:119543c9f674	1556	#define __HAL_RCC_TIM11_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM11RST))
mbed_official	489:119543c9f674	1557
mbed_official	489:119543c9f674	1558	#define __HAL_RCC_TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST))
mbed_official	489:119543c9f674	1559	#define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
mbed_official	489:119543c9f674	1560	#define __HAL_RCC_TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST))
mbed_official	489:119543c9f674	1561	#endif /* STM32F101xG \|\| STM32F103xG*/
mbed_official	489:119543c9f674	1562
mbed_official	489:119543c9f674	1563	/**
mbed_official	489:119543c9f674	1564	* @}
mbed_official	489:119543c9f674	1565	*/
mbed_official	489:119543c9f674	1566
mbed_official	489:119543c9f674	1567	/** @defgroup RCCEx_HSE_Configuration HSE Configuration
mbed_official	489:119543c9f674	1568	* @{
mbed_official	489:119543c9f674	1569	*/
mbed_official	489:119543c9f674	1570
mbed_official	489:119543c9f674	1571	#if defined(STM32F105xC) \|\| defined(STM32F107xC) \|\| defined (STM32F100xB) \|\| defined (STM32F100xE)
mbed_official	489:119543c9f674	1572	/**
mbed_official	489:119543c9f674	1573	* @brief Macro to configure the External High Speed oscillator (HSE) Predivision factor for PLL.
mbed_official	489:119543c9f674	1574	* @note Predivision factor can not be changed if PLL is used as system clock
mbed_official	489:119543c9f674	1575	* In this case, you have to select another source of the system clock, disable the PLL and
mbed_official	489:119543c9f674	1576	* then change the HSE predivision factor.
mbed_official	489:119543c9f674	1577	* @param __HSE_PREDIV_VALUE__: specifies the division value applied to HSE.
mbed_official	489:119543c9f674	1578	* This parameter must be a number between RCC_HSE_PREDIV_DIV1 and RCC_HSE_PREDIV_DIV16.
mbed_official	489:119543c9f674	1579	*/
mbed_official	489:119543c9f674	1580	#define __HAL_RCC_HSE_PREDIV_CONFIG(__HSE_PREDIV_VALUE__) MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV1, (uint32_t)(__HSE_PREDIV_VALUE__))
mbed_official	489:119543c9f674	1581	#else
mbed_official	489:119543c9f674	1582	/**
mbed_official	489:119543c9f674	1583	* @brief Macro to configure the External High Speed oscillator (HSE) Predivision factor for PLL.
mbed_official	489:119543c9f674	1584	* @note Predivision factor can not be changed if PLL is used as system clock
mbed_official	489:119543c9f674	1585	* In this case, you have to select another source of the system clock, disable the PLL and
mbed_official	489:119543c9f674	1586	* then change the HSE predivision factor.
mbed_official	489:119543c9f674	1587	* @param __HSE_PREDIV_VALUE__: specifies the division value applied to HSE.
mbed_official	489:119543c9f674	1588	* This parameter must be a number between RCC_HSE_PREDIV_DIV1 and RCC_HSE_PREDIV_DIV2.
mbed_official	489:119543c9f674	1589	*/
mbed_official	489:119543c9f674	1590	#define __HAL_RCC_HSE_PREDIV_CONFIG(__HSE_PREDIV_VALUE__) \
mbed_official	489:119543c9f674	1591	MODIFY_REG(RCC->CFGR,RCC_CFGR_PLLXTPRE, (uint32_t)(__HSE_PREDIV_VALUE__))
mbed_official	489:119543c9f674	1592
mbed_official	489:119543c9f674	1593	#endif /* STM32F105xC \|\| STM32F107xC */
mbed_official	489:119543c9f674	1594
mbed_official	489:119543c9f674	1595	#if defined(STM32F105xC) \|\| defined(STM32F107xC) \|\| defined (STM32F100xB) \|\| defined (STM32F100xE)
mbed_official	489:119543c9f674	1596	/**
mbed_official	489:119543c9f674	1597	* @brief Macro to get prediv1 factor for PLL.
mbed_official	489:119543c9f674	1598	*/
mbed_official	489:119543c9f674	1599	#define __HAL_RCC_HSE_GET_PREDIV() READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1)
mbed_official	489:119543c9f674	1600
mbed_official	489:119543c9f674	1601	#else
mbed_official	489:119543c9f674	1602	/**
mbed_official	489:119543c9f674	1603	* @brief Macro to get prediv1 factor for PLL.
mbed_official	489:119543c9f674	1604	*/
mbed_official	489:119543c9f674	1605	#define __HAL_RCC_HSE_GET_PREDIV() READ_BIT(RCC->CFGR, RCC_CFGR_PLLXTPRE)
mbed_official	489:119543c9f674	1606
mbed_official	489:119543c9f674	1607	#endif /* STM32F105xC \|\| STM32F107xC \|\| STM32F100xB \|\| STM32F100xE */
mbed_official	489:119543c9f674	1608
mbed_official	489:119543c9f674	1609	/**
mbed_official	489:119543c9f674	1610	* @}
mbed_official	489:119543c9f674	1611	*/
mbed_official	489:119543c9f674	1612
mbed_official	489:119543c9f674	1613	#if defined(STM32F105xC) \|\| defined(STM32F107xC)
mbed_official	489:119543c9f674	1614	/** @defgroup RCCEx_PLLI2S_Configuration PLLI2S Configuration
mbed_official	489:119543c9f674	1615	* @{
mbed_official	489:119543c9f674	1616	*/
mbed_official	489:119543c9f674	1617
mbed_official	489:119543c9f674	1618	/** @brief Macros to enable the main PLLI2S.
mbed_official	489:119543c9f674	1619	* @note After enabling the main PLLI2S, the application software should wait on
mbed_official	489:119543c9f674	1620	* PLLI2SRDY flag to be set indicating that PLLI2S clock is stable and can
mbed_official	489:119543c9f674	1621	* be used as system clock source.
mbed_official	489:119543c9f674	1622	* @note The main PLLI2S is disabled by hardware when entering STOP and STANDBY modes.
mbed_official	489:119543c9f674	1623	*/
mbed_official	489:119543c9f674	1624	#define __HAL_RCC_PLLI2S_ENABLE() ((__IO uint32_t ) RCC_CR_PLLI2SON_BB = ENABLE)
mbed_official	489:119543c9f674	1625
mbed_official	489:119543c9f674	1626	/** @brief Macros to disable the main PLLI2S.
mbed_official	489:119543c9f674	1627	* @note The main PLLI2S is disabled by hardware when entering STOP and STANDBY modes.
mbed_official	489:119543c9f674	1628	*/
mbed_official	489:119543c9f674	1629	#define __HAL_RCC_PLLI2S_DISABLE() ((__IO uint32_t ) RCC_CR_PLLI2SON_BB = DISABLE)
mbed_official	489:119543c9f674	1630
mbed_official	489:119543c9f674	1631	/** @brief macros to configure the main PLLI2S multiplication factor.
mbed_official	489:119543c9f674	1632	* @note This function must be used only when the main PLLI2S is disabled.
mbed_official	489:119543c9f674	1633	*
mbed_official	489:119543c9f674	1634	* @param __PLLI2SMUL__: specifies the multiplication factor for PLLI2S VCO output clock
mbed_official	489:119543c9f674	1635	* This parameter can be one of the following values:
mbed_official	489:119543c9f674	1636	* @arg RCC_PLLI2S_MUL8: PLLI2SVCO = PLLI2S clock entry x 8
mbed_official	489:119543c9f674	1637	* @arg RCC_PLLI2S_MUL9: PLLI2SVCO = PLLI2S clock entry x 9
mbed_official	489:119543c9f674	1638	* @arg RCC_PLLI2S_MUL10: PLLI2SVCO = PLLI2S clock entry x 10
mbed_official	489:119543c9f674	1639	* @arg RCC_PLLI2S_MUL11: PLLI2SVCO = PLLI2S clock entry x 11
mbed_official	489:119543c9f674	1640	* @arg RCC_PLLI2S_MUL12: PLLI2SVCO = PLLI2S clock entry x 12
mbed_official	489:119543c9f674	1641	* @arg RCC_PLLI2S_MUL13: PLLI2SVCO = PLLI2S clock entry x 13
mbed_official	489:119543c9f674	1642	* @arg RCC_PLLI2S_MUL14: PLLI2SVCO = PLLI2S clock entry x 14
mbed_official	489:119543c9f674	1643	* @arg RCC_PLLI2S_MUL16: PLLI2SVCO = PLLI2S clock entry x 16
mbed_official	489:119543c9f674	1644	* @arg RCC_PLLI2S_MUL20: PLLI2SVCO = PLLI2S clock entry x 20
mbed_official	489:119543c9f674	1645	*
mbed_official	489:119543c9f674	1646	*/
mbed_official	489:119543c9f674	1647	#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SMUL__)\
mbed_official	489:119543c9f674	1648	MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PLL3MUL,(__PLLI2SMUL__))
mbed_official	489:119543c9f674	1649
mbed_official	489:119543c9f674	1650	/**
mbed_official	489:119543c9f674	1651	* @}
mbed_official	489:119543c9f674	1652	*/
mbed_official	489:119543c9f674	1653
mbed_official	489:119543c9f674	1654	#endif /* STM32F105xC \|\| STM32F107xC */
mbed_official	489:119543c9f674	1655
mbed_official	489:119543c9f674	1656	/** @defgroup RCCEx_Peripheral_Configuration Peripheral Configuration
mbed_official	489:119543c9f674	1657	* @brief Macros to configure clock source of different peripherals.
mbed_official	489:119543c9f674	1658	* @{
mbed_official	489:119543c9f674	1659	*/
mbed_official	489:119543c9f674	1660
mbed_official	489:119543c9f674	1661	#if defined(STM32F102x6) \|\| defined(STM32F102xB) \|\| defined(STM32F103x6) \|\| defined(STM32F103xB) \|\| defined(STM32F103xE) \|\| defined(STM32F103xG)
mbed_official	489:119543c9f674	1662	/** @brief Macro to configure the USB clock.
mbed_official	489:119543c9f674	1663	* @param __USBCLKSOURCE__: specifies the USB clock source.
mbed_official	489:119543c9f674	1664	* This parameter can be one of the following values:
mbed_official	489:119543c9f674	1665	* @arg RCC_USBPLLCLK_DIV1: PLL clock divided by 1 selected as USB clock
mbed_official	489:119543c9f674	1666	* @arg RCC_USBPLLCLK_DIV1_5: PLL clock divided by 1.5 selected as USB clock
mbed_official	489:119543c9f674	1667	*/
mbed_official	489:119543c9f674	1668	#define __HAL_RCC_USB_CONFIG(__USBCLKSOURCE__) \
mbed_official	489:119543c9f674	1669	MODIFY_REG(RCC->CFGR, RCC_CFGR_USBPRE, (uint32_t)(__USBCLKSOURCE__))
mbed_official	489:119543c9f674	1670
mbed_official	489:119543c9f674	1671	/** @brief Macro to get the USB clock (USBCLK).
mbed_official	489:119543c9f674	1672	* @retval The clock source can be one of the following values:
mbed_official	489:119543c9f674	1673	* @arg RCC_USBPLLCLK_DIV1: PLL clock divided by 1 selected as USB clock
mbed_official	489:119543c9f674	1674	* @arg RCC_USBPLLCLK_DIV1_5: PLL clock divided by 1.5 selected as USB clock
mbed_official	489:119543c9f674	1675	*/
mbed_official	489:119543c9f674	1676	#define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_USBPRE)))
mbed_official	489:119543c9f674	1677
mbed_official	489:119543c9f674	1678	#endif /* STM32F102x6 \|\| STM32F102xB \|\| STM32F103x6 \|\| STM32F103xB \|\| STM32F103xE \|\| STM32F103xG */
mbed_official	489:119543c9f674	1679
mbed_official	489:119543c9f674	1680	#if defined(STM32F105xC) \|\| defined(STM32F107xC)
mbed_official	489:119543c9f674	1681
mbed_official	489:119543c9f674	1682	/** @brief Macro to configure the USB OTSclock.
mbed_official	489:119543c9f674	1683	* @param __USBCLKSOURCE__: specifies the USB clock source.
mbed_official	489:119543c9f674	1684	* This parameter can be one of the following values:
mbed_official	489:119543c9f674	1685	* @arg RCC_USBPLLCLK_DIV2: PLL clock divided by 2 selected as USB OTG FS clock
mbed_official	489:119543c9f674	1686	* @arg RCC_USBPLLCLK_DIV3: PLL clock divided by 3 selected as USB OTG FS clock
mbed_official	489:119543c9f674	1687	*/
mbed_official	489:119543c9f674	1688	#define __HAL_RCC_USB_CONFIG(__USBCLKSOURCE__) \
mbed_official	489:119543c9f674	1689	MODIFY_REG(RCC->CFGR, RCC_CFGR_OTGFSPRE, (uint32_t)(__USBCLKSOURCE__))
mbed_official	489:119543c9f674	1690
mbed_official	489:119543c9f674	1691	/** @brief Macro to get the USB clock (USBCLK).
mbed_official	489:119543c9f674	1692	* @retval The clock source can be one of the following values:
mbed_official	489:119543c9f674	1693	* @arg RCC_USBPLLCLK_DIV2: PLL clock divided by 2 selected as USB OTG FS clock
mbed_official	489:119543c9f674	1694	* @arg RCC_USBPLLCLK_DIV3: PLL clock divided by 3 selected as USB OTG FS clock
mbed_official	489:119543c9f674	1695	*/
mbed_official	489:119543c9f674	1696	#define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_OTGFSPRE)))
mbed_official	489:119543c9f674	1697
mbed_official	489:119543c9f674	1698	#endif /* STM32F105xC \|\| STM32F107xC */
mbed_official	489:119543c9f674	1699
mbed_official	489:119543c9f674	1700	/** @brief Macro to configure the ADCx clock (x=1 to 3 depending on devices).
mbed_official	489:119543c9f674	1701	* @param __ADCCLKSOURCE__: specifies the ADC clock source.
mbed_official	489:119543c9f674	1702	* This parameter can be one of the following values:
mbed_official	489:119543c9f674	1703	* @arg RCC_ADCPCLK2_DIV2: PCLK2 clock divided by 2 selected as ADC clock
mbed_official	489:119543c9f674	1704	* @arg RCC_ADCPCLK2_DIV4: PCLK2 clock divided by 4 selected as ADC clock
mbed_official	489:119543c9f674	1705	* @arg RCC_ADCPCLK2_DIV6: PCLK2 clock divided by 6 selected as ADC clock
mbed_official	489:119543c9f674	1706	* @arg RCC_ADCPCLK2_DIV8: PCLK2 clock divided by 8 selected as ADC clock
mbed_official	489:119543c9f674	1707	*/
mbed_official	489:119543c9f674	1708	#define __HAL_RCC_ADC_CONFIG(__ADCCLKSOURCE__) \
mbed_official	489:119543c9f674	1709	MODIFY_REG(RCC->CFGR, RCC_CFGR_ADCPRE, (uint32_t)(__ADCCLKSOURCE__))
mbed_official	489:119543c9f674	1710
mbed_official	489:119543c9f674	1711	/** @brief Macro to get the ADC clock (ADCxCLK, x=1 to 3 depending on devices).
mbed_official	489:119543c9f674	1712	* @retval The clock source can be one of the following values:
mbed_official	489:119543c9f674	1713	* @arg RCC_ADCPCLK2_DIV2: PCLK2 clock divided by 2 selected as ADC clock
mbed_official	489:119543c9f674	1714	* @arg RCC_ADCPCLK2_DIV4: PCLK2 clock divided by 4 selected as ADC clock
mbed_official	489:119543c9f674	1715	* @arg RCC_ADCPCLK2_DIV6: PCLK2 clock divided by 6 selected as ADC clock
mbed_official	489:119543c9f674	1716	* @arg RCC_ADCPCLK2_DIV8: PCLK2 clock divided by 8 selected as ADC clock
mbed_official	489:119543c9f674	1717	*/
mbed_official	489:119543c9f674	1718	#define __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_ADCPRE)))
mbed_official	489:119543c9f674	1719
mbed_official	489:119543c9f674	1720	/**
mbed_official	489:119543c9f674	1721	* @}
mbed_official	489:119543c9f674	1722	*/
mbed_official	489:119543c9f674	1723
mbed_official	489:119543c9f674	1724	#if defined(STM32F105xC) \|\| defined(STM32F107xC)
mbed_official	489:119543c9f674	1725
mbed_official	489:119543c9f674	1726	/** @addtogroup RCCEx_HSE_Configuration
mbed_official	489:119543c9f674	1727	* @{
mbed_official	489:119543c9f674	1728	*/
mbed_official	489:119543c9f674	1729
mbed_official	489:119543c9f674	1730	/**
mbed_official	489:119543c9f674	1731	* @brief Macro to configure the PLL2 & PLLI2S Predivision factor.
mbed_official	489:119543c9f674	1732	* @note Predivision factor can not be changed if PLL2 is used indirectly as system clock
mbed_official	489:119543c9f674	1733	* In this case, you have to select another source of the system clock, disable the PLL2 and PLLI2S and
mbed_official	489:119543c9f674	1734	* then change the PREDIV2 factor.
mbed_official	489:119543c9f674	1735	* @param __HSE_PREDIV2_VALUE__: specifies the PREDIV2 value applied to PLL2 & PLLI2S.
mbed_official	489:119543c9f674	1736	* This parameter must be a number between RCC_HSE_PREDIV2_DIV1 and RCC_HSE_PREDIV2_DIV16.
mbed_official	489:119543c9f674	1737	*/
mbed_official	489:119543c9f674	1738	#define __HAL_RCC_HSE_PREDIV2_CONFIG(__HSE_PREDIV2_VALUE__) \
mbed_official	489:119543c9f674	1739	MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV2, (uint32_t)(__HSE_PREDIV2_VALUE__))
mbed_official	489:119543c9f674	1740
mbed_official	489:119543c9f674	1741	/**
mbed_official	489:119543c9f674	1742	* @brief Macro to get prediv2 factor for PLL2 & PLL3.
mbed_official	489:119543c9f674	1743	*/
mbed_official	489:119543c9f674	1744	#define __HAL_RCC_HSE_GET_PREDIV2() READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV2)
mbed_official	489:119543c9f674	1745
mbed_official	489:119543c9f674	1746	/**
mbed_official	489:119543c9f674	1747	* @}
mbed_official	489:119543c9f674	1748	*/
mbed_official	489:119543c9f674	1749
mbed_official	489:119543c9f674	1750	/** @addtogroup RCCEx_PLLI2S_Configuration
mbed_official	489:119543c9f674	1751	* @{
mbed_official	489:119543c9f674	1752	*/
mbed_official	489:119543c9f674	1753
mbed_official	489:119543c9f674	1754	/** @brief Macros to enable the main PLL2.
mbed_official	489:119543c9f674	1755	* @note After enabling the main PLL2, the application software should wait on
mbed_official	489:119543c9f674	1756	* PLL2RDY flag to be set indicating that PLL2 clock is stable and can
mbed_official	489:119543c9f674	1757	* be used as system clock source.
mbed_official	489:119543c9f674	1758	* @note The main PLL2 is disabled by hardware when entering STOP and STANDBY modes.
mbed_official	489:119543c9f674	1759	*/
mbed_official	489:119543c9f674	1760	#define __HAL_RCC_PLL2_ENABLE() ((__IO uint32_t ) CR_PLL2ON_BB = ENABLE)
mbed_official	489:119543c9f674	1761
mbed_official	489:119543c9f674	1762	/** @brief Macros to disable the main PLL2.
mbed_official	489:119543c9f674	1763	* @note The main PLL2 can not be disabled if it is used indirectly as system clock source
mbed_official	489:119543c9f674	1764	* @note The main PLL2 is disabled by hardware when entering STOP and STANDBY modes.
mbed_official	489:119543c9f674	1765	*/
mbed_official	489:119543c9f674	1766	#define __HAL_RCC_PLL2_DISABLE() ((__IO uint32_t ) CR_PLL2ON_BB = DISABLE)
mbed_official	489:119543c9f674	1767
mbed_official	489:119543c9f674	1768	/** @brief macros to configure the main PLL2 multiplication factor.
mbed_official	489:119543c9f674	1769	* @note This function must be used only when the main PLL2 is disabled.
mbed_official	489:119543c9f674	1770	*
mbed_official	489:119543c9f674	1771	* @param __PLL2MUL__: specifies the multiplication factor for PLL2 VCO output clock
mbed_official	489:119543c9f674	1772	* This parameter can be one of the following values:
mbed_official	489:119543c9f674	1773	* @arg RCC_PLL2_MUL8: PLL2VCO = PLL2 clock entry x 8
mbed_official	489:119543c9f674	1774	* @arg RCC_PLL2_MUL9: PLL2VCO = PLL2 clock entry x 9
mbed_official	489:119543c9f674	1775	* @arg RCC_PLL2_MUL10: PLL2VCO = PLL2 clock entry x 10
mbed_official	489:119543c9f674	1776	* @arg RCC_PLL2_MUL11: PLL2VCO = PLL2 clock entry x 11
mbed_official	489:119543c9f674	1777	* @arg RCC_PLL2_MUL12: PLL2VCO = PLL2 clock entry x 12
mbed_official	489:119543c9f674	1778	* @arg RCC_PLL2_MUL13: PLL2VCO = PLL2 clock entry x 13
mbed_official	489:119543c9f674	1779	* @arg RCC_PLL2_MUL14: PLL2VCO = PLL2 clock entry x 14
mbed_official	489:119543c9f674	1780	* @arg RCC_PLL2_MUL16: PLL2VCO = PLL2 clock entry x 16
mbed_official	489:119543c9f674	1781	* @arg RCC_PLL2_MUL20: PLL2VCO = PLL2 clock entry x 20
mbed_official	489:119543c9f674	1782	*
mbed_official	489:119543c9f674	1783	*/
mbed_official	489:119543c9f674	1784	#define __HAL_RCC_PLL2_CONFIG(__PLL2MUL__)\
mbed_official	489:119543c9f674	1785	MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PLL2MUL,(__PLL2MUL__))
mbed_official	489:119543c9f674	1786
mbed_official	489:119543c9f674	1787	/**
mbed_official	489:119543c9f674	1788	* @}
mbed_official	489:119543c9f674	1789	*/
mbed_official	489:119543c9f674	1790
mbed_official	489:119543c9f674	1791	/** @defgroup RCCEx_I2S_Configuration I2S Configuration
mbed_official	489:119543c9f674	1792	* @brief Macros to configure clock source of I2S peripherals.
mbed_official	489:119543c9f674	1793	* @{
mbed_official	489:119543c9f674	1794	*/
mbed_official	489:119543c9f674	1795
mbed_official	489:119543c9f674	1796	/** @brief Macro to configure the I2S2 clock.
mbed_official	489:119543c9f674	1797	* @param __I2S2CLKSOURCE__: specifies the I2S2 clock source.
mbed_official	489:119543c9f674	1798	* This parameter can be one of the following values:
mbed_official	489:119543c9f674	1799	* @arg RCC_I2S2CLKSOURCE_SYSCLK: system clock selected as I2S3 clock entry
mbed_official	489:119543c9f674	1800	* @arg RCC_I2S2CLKSOURCE_PLLI2S_VCO: PLLI2S VCO clock selected as I2S3 clock entry
mbed_official	489:119543c9f674	1801	*/
mbed_official	489:119543c9f674	1802	#define __HAL_RCC_I2S2_CONFIG(__I2S2CLKSOURCE__) \
mbed_official	489:119543c9f674	1803	MODIFY_REG(RCC->CFGR2, RCC_CFGR2_I2S2SRC, (uint32_t)(__I2S2CLKSOURCE__))
mbed_official	489:119543c9f674	1804
mbed_official	489:119543c9f674	1805	/** @brief Macro to get the I2S2 clock (I2S2CLK).
mbed_official	489:119543c9f674	1806	* @retval The clock source can be one of the following values:
mbed_official	489:119543c9f674	1807	* @arg RCC_I2S2CLKSOURCE_SYSCLK: system clock selected as I2S3 clock entry
mbed_official	489:119543c9f674	1808	* @arg RCC_I2S2CLKSOURCE_PLLI2S_VCO: PLLI2S VCO clock selected as I2S3 clock entry
mbed_official	489:119543c9f674	1809	*/
mbed_official	489:119543c9f674	1810	#define __HAL_RCC_GET_I2S2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_I2S2SRC)))
mbed_official	489:119543c9f674	1811
mbed_official	489:119543c9f674	1812	/** @brief Macro to configure the I2S3 clock.
mbed_official	489:119543c9f674	1813	* @param __I2S2CLKSOURCE__: specifies the I2S3 clock source.
mbed_official	489:119543c9f674	1814	* This parameter can be one of the following values:
mbed_official	489:119543c9f674	1815	* @arg RCC_I2S3CLKSOURCE_SYSCLK: system clock selected as I2S3 clock entry
mbed_official	489:119543c9f674	1816	* @arg RCC_I2S3CLKSOURCE_PLLI2S_VCO: PLLI2S VCO clock selected as I2S3 clock entry
mbed_official	489:119543c9f674	1817	*/
mbed_official	489:119543c9f674	1818	#define __HAL_RCC_I2S3_CONFIG(__I2S2CLKSOURCE__) \
mbed_official	489:119543c9f674	1819	MODIFY_REG(RCC->CFGR2, RCC_CFGR2_I2S3SRC, (uint32_t)(__I2S2CLKSOURCE__))
mbed_official	489:119543c9f674	1820
mbed_official	489:119543c9f674	1821	/** @brief Macro to get the I2S3 clock (I2S3CLK).
mbed_official	489:119543c9f674	1822	* @retval The clock source can be one of the following values:
mbed_official	489:119543c9f674	1823	* @arg RCC_I2S3CLKSOURCE_SYSCLK: system clock selected as I2S3 clock entry
mbed_official	489:119543c9f674	1824	* @arg RCC_I2S3CLKSOURCE_PLLI2S_VCO: PLLI2S VCO clock selected as I2S3 clock entry
mbed_official	489:119543c9f674	1825	*/
mbed_official	489:119543c9f674	1826	#define __HAL_RCC_GET_I2S3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_I2S3SRC)))
mbed_official	489:119543c9f674	1827
mbed_official	489:119543c9f674	1828	/**
mbed_official	489:119543c9f674	1829	* @}
mbed_official	489:119543c9f674	1830	*/
mbed_official	489:119543c9f674	1831
mbed_official	489:119543c9f674	1832	#endif /* STM32F105xC \|\| STM32F107xC */
mbed_official	489:119543c9f674	1833	/**
mbed_official	489:119543c9f674	1834	* @}
mbed_official	489:119543c9f674	1835	*/
mbed_official	489:119543c9f674	1836
mbed_official	489:119543c9f674	1837	/* Exported functions --------------------------------------------------------*/
mbed_official	489:119543c9f674	1838	/** @addtogroup RCCEx_Exported_Functions
mbed_official	489:119543c9f674	1839	* @{
mbed_official	489:119543c9f674	1840	*/
mbed_official	489:119543c9f674	1841
mbed_official	489:119543c9f674	1842	/** @addtogroup RCCEx_Exported_Functions_Group1
mbed_official	489:119543c9f674	1843	* @{
mbed_official	489:119543c9f674	1844	*/
mbed_official	489:119543c9f674	1845
mbed_official	489:119543c9f674	1846	HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
mbed_official	489:119543c9f674	1847	void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
mbed_official	489:119543c9f674	1848	uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
mbed_official	489:119543c9f674	1849
mbed_official	489:119543c9f674	1850	/**
mbed_official	489:119543c9f674	1851	* @}
mbed_official	489:119543c9f674	1852	*/
mbed_official	489:119543c9f674	1853
mbed_official	489:119543c9f674	1854	#if defined(STM32F105xC) \|\| defined(STM32F107xC)
mbed_official	489:119543c9f674	1855	/** @addtogroup RCCEx_Exported_Functions_Group2
mbed_official	489:119543c9f674	1856	* @{
mbed_official	489:119543c9f674	1857	*/
mbed_official	489:119543c9f674	1858	HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit);
mbed_official	489:119543c9f674	1859	HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void);
mbed_official	489:119543c9f674	1860
mbed_official	489:119543c9f674	1861	/**
mbed_official	489:119543c9f674	1862	* @}
mbed_official	489:119543c9f674	1863	*/
mbed_official	489:119543c9f674	1864
mbed_official	489:119543c9f674	1865	/** @addtogroup RCCEx_Exported_Functions_Group3
mbed_official	489:119543c9f674	1866	* @{
mbed_official	489:119543c9f674	1867	*/
mbed_official	489:119543c9f674	1868	HAL_StatusTypeDef HAL_RCCEx_EnablePLL2(RCC_PLL2InitTypeDef *PLL2Init);
mbed_official	489:119543c9f674	1869	HAL_StatusTypeDef HAL_RCCEx_DisablePLL2(void);
mbed_official	489:119543c9f674	1870
mbed_official	489:119543c9f674	1871	/**
mbed_official	489:119543c9f674	1872	* @}
mbed_official	489:119543c9f674	1873	*/
mbed_official	489:119543c9f674	1874	#endif /* STM32F105xC \|\| STM32F107xC */
mbed_official	489:119543c9f674	1875
mbed_official	489:119543c9f674	1876	/**
mbed_official	489:119543c9f674	1877	* @}
mbed_official	489:119543c9f674	1878	*/
mbed_official	489:119543c9f674	1879
mbed_official	489:119543c9f674	1880	/**
mbed_official	489:119543c9f674	1881	* @}
mbed_official	489:119543c9f674	1882	*/
mbed_official	489:119543c9f674	1883
mbed_official	489:119543c9f674	1884	/**
mbed_official	489:119543c9f674	1885	* @}
mbed_official	489:119543c9f674	1886	*/
mbed_official	489:119543c9f674	1887
mbed_official	489:119543c9f674	1888	#ifdef __cplusplus
mbed_official	489:119543c9f674	1889	}
mbed_official	489:119543c9f674	1890	#endif
mbed_official	489:119543c9f674	1891
mbed_official	489:119543c9f674	1892	#endif /* __STM32F1xx_HAL_RCC_EX_H */
mbed_official	489:119543c9f674	1893
mbed_official	489:119543c9f674	1894	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/
mbed_official	489:119543c9f674	1895