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This library was superseded by mbed-dev - https://os.mbed.com/users/mbed_official/code/mbed-dev/.

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If you are looking for a stable and tested release, please import one of the official mbed library releases:

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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Last commit 20 Feb 2019 by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_rcc_ex.c@581:39197bcd20f2, 2015-07-02 (annotated)

Committer:
mbed_official
Date:
Thu Jul 02 16:30:08 2015 +0100
Revision:
581:39197bcd20f2
Parent:
489:119543c9f674 
Synchronized with git revision ae2d3cdffe70184eb8736d94f76c45c93f4b7724



Full URL: https://github.com/mbedmicro/mbed/commit/ae2d3cdffe70184eb8736d94f76c45c93f4b7724/



Make it possible to build the core mbed library with yotta

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 489:119543c9f674 1 /**
mbed_official 489:119543c9f674 2 ******************************************************************************
mbed_official 489:119543c9f674 3 * @file stm32f1xx_hal_rcc_ex.c
mbed_official 489:119543c9f674 4 * @author MCD Application Team
mbed_official 489:119543c9f674 5 * @version V1.0.0
mbed_official 489:119543c9f674 6 * @date 15-December-2014
mbed_official 489:119543c9f674 7 * @brief Extended RCC HAL module driver.
mbed_official 489:119543c9f674 8 *
mbed_official 489:119543c9f674 9 * This file provides firmware functions to manage the following
mbed_official 489:119543c9f674 10 * functionalities RCC extension peripheral:
mbed_official 489:119543c9f674 11 * + Extended Peripheral Control functions
mbed_official 489:119543c9f674 12 *
mbed_official 489:119543c9f674 13 ******************************************************************************
mbed_official 489:119543c9f674 14 * @attention
mbed_official 489:119543c9f674 15 *
mbed_official 489:119543c9f674 16 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
mbed_official 489:119543c9f674 17 *
mbed_official 489:119543c9f674 18 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 489:119543c9f674 19 * are permitted provided that the following conditions are met:
mbed_official 489:119543c9f674 20 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 489:119543c9f674 21 * this list of conditions and the following disclaimer.
mbed_official 489:119543c9f674 22 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 489:119543c9f674 23 * this list of conditions and the following disclaimer in the documentation
mbed_official 489:119543c9f674 24 * and/or other materials provided with the distribution.
mbed_official 489:119543c9f674 25 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 489:119543c9f674 26 * may be used to endorse or promote products derived from this software
mbed_official 489:119543c9f674 27 * without specific prior written permission.
mbed_official 489:119543c9f674 28 *
mbed_official 489:119543c9f674 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 489:119543c9f674 30 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 489:119543c9f674 31 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 489:119543c9f674 32 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 489:119543c9f674 33 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 489:119543c9f674 34 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 489:119543c9f674 35 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 489:119543c9f674 36 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 489:119543c9f674 37 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 489:119543c9f674 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 489:119543c9f674 39 *
mbed_official 489:119543c9f674 40 ******************************************************************************
mbed_official 489:119543c9f674 41 */
mbed_official 489:119543c9f674 42
mbed_official 489:119543c9f674 43 /* Includes ------------------------------------------------------------------*/
mbed_official 489:119543c9f674 44 #include "stm32f1xx_hal.h"
mbed_official 489:119543c9f674 45
mbed_official 489:119543c9f674 46 /** @addtogroup STM32F1xx_HAL_Driver
mbed_official 489:119543c9f674 47 * @{
mbed_official 489:119543c9f674 48 */
mbed_official 489:119543c9f674 49
mbed_official 489:119543c9f674 50 #ifdef HAL_RCC_MODULE_ENABLED
mbed_official 489:119543c9f674 51
mbed_official 489:119543c9f674 52 /** @defgroup RCCEx RCCEx
mbed_official 489:119543c9f674 53 * @brief RCC Extension HAL module driver
mbed_official 489:119543c9f674 54 * @{
mbed_official 489:119543c9f674 55 */
mbed_official 489:119543c9f674 56
mbed_official 489:119543c9f674 57 /* Private typedef -----------------------------------------------------------*/
mbed_official 489:119543c9f674 58 /* Private define ------------------------------------------------------------*/
mbed_official 489:119543c9f674 59 /** @defgroup RCCEx_Private_Constants RCCEx Private Constants
mbed_official 489:119543c9f674 60 * @{
mbed_official 489:119543c9f674 61 */
mbed_official 489:119543c9f674 62 #define PLL2_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
mbed_official 489:119543c9f674 63
mbed_official 489:119543c9f674 64 /* Alias word address of PLL2ON bit */
mbed_official 489:119543c9f674 65 #define PLL2ON_BITNUMBER POSITION_VAL(RCC_CR_PLL2ON)
mbed_official 489:119543c9f674 66 #define CR_PLL2ON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (PLL2ON_BITNUMBER * 4)))
mbed_official 489:119543c9f674 67
mbed_official 489:119543c9f674 68
mbed_official 489:119543c9f674 69 /**
mbed_official 489:119543c9f674 70 * @}
mbed_official 489:119543c9f674 71 */
mbed_official 489:119543c9f674 72 /* Private macro -------------------------------------------------------------*/
mbed_official 489:119543c9f674 73 /** @defgroup RCCEx_Private_Macros RCCEx Private Macros
mbed_official 489:119543c9f674 74 * @{
mbed_official 489:119543c9f674 75 */
mbed_official 489:119543c9f674 76 /**
mbed_official 489:119543c9f674 77 * @}
mbed_official 489:119543c9f674 78 */
mbed_official 489:119543c9f674 79
mbed_official 489:119543c9f674 80 /** @defgroup RCCEx_Private_Macros RCCEx Private Macros
mbed_official 489:119543c9f674 81 * @{
mbed_official 489:119543c9f674 82 */
mbed_official 489:119543c9f674 83
mbed_official 489:119543c9f674 84 /**
mbed_official 489:119543c9f674 85 * @}
mbed_official 489:119543c9f674 86 */
mbed_official 489:119543c9f674 87
mbed_official 489:119543c9f674 88
mbed_official 489:119543c9f674 89 /* Private variables ---------------------------------------------------------*/
mbed_official 489:119543c9f674 90 /* Private function prototypes -----------------------------------------------*/
mbed_official 489:119543c9f674 91 /* Private functions ---------------------------------------------------------*/
mbed_official 489:119543c9f674 92
mbed_official 489:119543c9f674 93 /**
mbed_official 489:119543c9f674 94 * @}
mbed_official 489:119543c9f674 95 */
mbed_official 489:119543c9f674 96
mbed_official 489:119543c9f674 97 /** @addtogroup RCC
mbed_official 489:119543c9f674 98 * @{
mbed_official 489:119543c9f674 99 */
mbed_official 489:119543c9f674 100
mbed_official 489:119543c9f674 101 /** @addtogroup RCC_Exported_Functions
mbed_official 489:119543c9f674 102 * @{
mbed_official 489:119543c9f674 103 */
mbed_official 489:119543c9f674 104
mbed_official 489:119543c9f674 105 #if defined(STM32F105xC) || defined(STM32F107xC) || defined (STM32F100xB) || defined (STM32F100xE)
mbed_official 489:119543c9f674 106 /** @addtogroup RCC_Exported_Functions_Group1
mbed_official 489:119543c9f674 107 * @{
mbed_official 489:119543c9f674 108 */
mbed_official 489:119543c9f674 109
mbed_official 489:119543c9f674 110 /**
mbed_official 489:119543c9f674 111 * @brief Resets the RCC clock configuration to the default reset state.
mbed_official 489:119543c9f674 112 * @note The default reset state of the clock configuration is given below:
mbed_official 489:119543c9f674 113 * - HSI ON and used as system clock source
mbed_official 489:119543c9f674 114 * - HSE and PLL OFF
mbed_official 489:119543c9f674 115 * - AHB, APB1 and APB2 prescaler set to 1.
mbed_official 489:119543c9f674 116 * - CSS and MCO1 OFF
mbed_official 489:119543c9f674 117 * - All interrupts disabled
mbed_official 489:119543c9f674 118 * @note This function doesn't modify the configuration of the
mbed_official 489:119543c9f674 119 * - Peripheral clocks
mbed_official 489:119543c9f674 120 * - LSI, LSE and RTC clocks
mbed_official 489:119543c9f674 121 * @retval None
mbed_official 489:119543c9f674 122 */
mbed_official 489:119543c9f674 123 void HAL_RCC_DeInit(void)
mbed_official 489:119543c9f674 124 {
mbed_official 489:119543c9f674 125 /* Switch SYSCLK to HSI */
mbed_official 489:119543c9f674 126 CLEAR_BIT(RCC->CFGR, RCC_CFGR_SW);
mbed_official 489:119543c9f674 127
mbed_official 489:119543c9f674 128 /* Reset HSEON, CSSON, & PLLON bits */
mbed_official 489:119543c9f674 129 CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON);
mbed_official 489:119543c9f674 130
mbed_official 489:119543c9f674 131 /* Reset HSEBYP bit */
mbed_official 489:119543c9f674 132 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
mbed_official 489:119543c9f674 133
mbed_official 489:119543c9f674 134 /* Reset CFGR register */
mbed_official 489:119543c9f674 135 CLEAR_REG(RCC->CFGR);
mbed_official 489:119543c9f674 136
mbed_official 489:119543c9f674 137 /* Set HSITRIM bits to the reset value */
mbed_official 489:119543c9f674 138 MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, ((uint32_t)0x10 << POSITION_VAL(RCC_CR_HSITRIM)));
mbed_official 489:119543c9f674 139
mbed_official 489:119543c9f674 140 /* Reset CFGR2 register */
mbed_official 489:119543c9f674 141 CLEAR_REG(RCC->CFGR2);
mbed_official 489:119543c9f674 142
mbed_official 489:119543c9f674 143 /* Disable all interrupts */
mbed_official 489:119543c9f674 144 CLEAR_REG(RCC->CIR);
mbed_official 489:119543c9f674 145 }
mbed_official 489:119543c9f674 146 /**
mbed_official 489:119543c9f674 147 * @}
mbed_official 489:119543c9f674 148 */
mbed_official 489:119543c9f674 149
mbed_official 489:119543c9f674 150 #endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */
mbed_official 489:119543c9f674 151
mbed_official 489:119543c9f674 152 #if defined(STM32F105xC) || defined(STM32F107xC)
mbed_official 489:119543c9f674 153 /** @addtogroup RCC_Exported_Functions_Group1
mbed_official 489:119543c9f674 154 * @{
mbed_official 489:119543c9f674 155 */
mbed_official 489:119543c9f674 156
mbed_official 489:119543c9f674 157 /**
mbed_official 489:119543c9f674 158 * @brief Initializes the RCC Oscillators according to the specified parameters in the
mbed_official 489:119543c9f674 159 * RCC_OscInitTypeDef.
mbed_official 489:119543c9f674 160 * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
mbed_official 489:119543c9f674 161 * contains the configuration information for the RCC Oscillators.
mbed_official 489:119543c9f674 162 * @note The PLL is not disabled when used as system clock.
mbed_official 489:119543c9f674 163 * @note The PLL is not disabled when USB OTG FS clock is enabled (specific to devices with USB FS)
mbed_official 489:119543c9f674 164 * @retval HAL status
mbed_official 489:119543c9f674 165 */
mbed_official 489:119543c9f674 166 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
mbed_official 489:119543c9f674 167 {
mbed_official 489:119543c9f674 168 uint32_t tickstart = 0;
mbed_official 489:119543c9f674 169
mbed_official 489:119543c9f674 170 /* Check the parameters */
mbed_official 489:119543c9f674 171 assert_param(RCC_OscInitStruct != NULL);
mbed_official 489:119543c9f674 172 assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
mbed_official 489:119543c9f674 173
mbed_official 489:119543c9f674 174 /*------------------------------- HSE Configuration ------------------------*/
mbed_official 489:119543c9f674 175 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
mbed_official 489:119543c9f674 176 {
mbed_official 489:119543c9f674 177 /* Check the parameters */
mbed_official 489:119543c9f674 178 assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
mbed_official 489:119543c9f674 179
mbed_official 489:119543c9f674 180 /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
mbed_official 489:119543c9f674 181 if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
mbed_official 489:119543c9f674 182 || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE)))
mbed_official 489:119543c9f674 183 {
mbed_official 489:119543c9f674 184 if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState != RCC_HSE_ON) && (RCC_OscInitStruct->HSEState != RCC_HSE_BYPASS))
mbed_official 489:119543c9f674 185 {
mbed_official 489:119543c9f674 186 return HAL_ERROR;
mbed_official 489:119543c9f674 187 }
mbed_official 489:119543c9f674 188 }
mbed_official 489:119543c9f674 189 else
mbed_official 489:119543c9f674 190 {
mbed_official 489:119543c9f674 191 /* Reset HSEON and HSEBYP bits before configuring the HSE --------------*/
mbed_official 489:119543c9f674 192 __HAL_RCC_HSE_CONFIG(RCC_HSE_OFF);
mbed_official 489:119543c9f674 193
mbed_official 489:119543c9f674 194 /* Get Start Tick*/
mbed_official 489:119543c9f674 195 tickstart = HAL_GetTick();
mbed_official 489:119543c9f674 196
mbed_official 489:119543c9f674 197 /* Wait till HSE is disabled */
mbed_official 489:119543c9f674 198 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
mbed_official 489:119543c9f674 199 {
mbed_official 489:119543c9f674 200 if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
mbed_official 489:119543c9f674 201 {
mbed_official 489:119543c9f674 202 return HAL_TIMEOUT;
mbed_official 489:119543c9f674 203 }
mbed_official 489:119543c9f674 204 }
mbed_official 489:119543c9f674 205
mbed_official 489:119543c9f674 206 /* Set the new HSE configuration ---------------------------------------*/
mbed_official 489:119543c9f674 207 __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
mbed_official 489:119543c9f674 208
mbed_official 489:119543c9f674 209 /* Check the HSE State */
mbed_official 489:119543c9f674 210 if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
mbed_official 489:119543c9f674 211 {
mbed_official 489:119543c9f674 212 /* Get Start Tick*/
mbed_official 489:119543c9f674 213 tickstart = HAL_GetTick();
mbed_official 489:119543c9f674 214
mbed_official 489:119543c9f674 215 /* Wait till HSE is ready */
mbed_official 489:119543c9f674 216 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
mbed_official 489:119543c9f674 217 {
mbed_official 489:119543c9f674 218 if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
mbed_official 489:119543c9f674 219 {
mbed_official 489:119543c9f674 220 return HAL_TIMEOUT;
mbed_official 489:119543c9f674 221 }
mbed_official 489:119543c9f674 222 }
mbed_official 489:119543c9f674 223 }
mbed_official 489:119543c9f674 224 else
mbed_official 489:119543c9f674 225 {
mbed_official 489:119543c9f674 226 /* Get Start Tick*/
mbed_official 489:119543c9f674 227 tickstart = HAL_GetTick();
mbed_official 489:119543c9f674 228
mbed_official 489:119543c9f674 229 /* Wait till HSE is disabled */
mbed_official 489:119543c9f674 230 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
mbed_official 489:119543c9f674 231 {
mbed_official 489:119543c9f674 232 if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
mbed_official 489:119543c9f674 233 {
mbed_official 489:119543c9f674 234 return HAL_TIMEOUT;
mbed_official 489:119543c9f674 235 }
mbed_official 489:119543c9f674 236 }
mbed_official 489:119543c9f674 237 }
mbed_official 489:119543c9f674 238 }
mbed_official 489:119543c9f674 239 }
mbed_official 489:119543c9f674 240 /*----------------------------- HSI Configuration --------------------------*/
mbed_official 489:119543c9f674 241 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
mbed_official 489:119543c9f674 242 {
mbed_official 489:119543c9f674 243 /* Check the parameters */
mbed_official 489:119543c9f674 244 assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
mbed_official 489:119543c9f674 245 assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
mbed_official 489:119543c9f674 246
mbed_official 489:119543c9f674 247 /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
mbed_official 489:119543c9f674 248 if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
mbed_official 489:119543c9f674 249 || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI_DIV2)))
mbed_official 489:119543c9f674 250 {
mbed_official 489:119543c9f674 251 /* When HSI is used as system clock it will not disabled */
mbed_official 489:119543c9f674 252 if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
mbed_official 489:119543c9f674 253 {
mbed_official 489:119543c9f674 254 return HAL_ERROR;
mbed_official 489:119543c9f674 255 }
mbed_official 489:119543c9f674 256 /* Otherwise, just the calibration is allowed */
mbed_official 489:119543c9f674 257 else
mbed_official 489:119543c9f674 258 {
mbed_official 489:119543c9f674 259 /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
mbed_official 489:119543c9f674 260 __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
mbed_official 489:119543c9f674 261 }
mbed_official 489:119543c9f674 262 }
mbed_official 489:119543c9f674 263 else
mbed_official 489:119543c9f674 264 {
mbed_official 489:119543c9f674 265 /* Check the HSI State */
mbed_official 489:119543c9f674 266 if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF)
mbed_official 489:119543c9f674 267 {
mbed_official 489:119543c9f674 268 /* Enable the Internal High Speed oscillator (HSI). */
mbed_official 489:119543c9f674 269 __HAL_RCC_HSI_ENABLE();
mbed_official 489:119543c9f674 270
mbed_official 489:119543c9f674 271 /* Get Start Tick*/
mbed_official 489:119543c9f674 272 tickstart = HAL_GetTick();
mbed_official 489:119543c9f674 273
mbed_official 489:119543c9f674 274 /* Wait till HSI is ready */
mbed_official 489:119543c9f674 275 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
mbed_official 489:119543c9f674 276 {
mbed_official 489:119543c9f674 277 if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
mbed_official 489:119543c9f674 278 {
mbed_official 489:119543c9f674 279 return HAL_TIMEOUT;
mbed_official 489:119543c9f674 280 }
mbed_official 489:119543c9f674 281 }
mbed_official 489:119543c9f674 282
mbed_official 489:119543c9f674 283 /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
mbed_official 489:119543c9f674 284 __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
mbed_official 489:119543c9f674 285 }
mbed_official 489:119543c9f674 286 else
mbed_official 489:119543c9f674 287 {
mbed_official 489:119543c9f674 288 /* Disable the Internal High Speed oscillator (HSI). */
mbed_official 489:119543c9f674 289 __HAL_RCC_HSI_DISABLE();
mbed_official 489:119543c9f674 290
mbed_official 489:119543c9f674 291 /* Get Start Tick*/
mbed_official 489:119543c9f674 292 tickstart = HAL_GetTick();
mbed_official 489:119543c9f674 293
mbed_official 489:119543c9f674 294 /* Wait till HSI is disabled */
mbed_official 489:119543c9f674 295 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
mbed_official 489:119543c9f674 296 {
mbed_official 489:119543c9f674 297 if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
mbed_official 489:119543c9f674 298 {
mbed_official 489:119543c9f674 299 return HAL_TIMEOUT;
mbed_official 489:119543c9f674 300 }
mbed_official 489:119543c9f674 301 }
mbed_official 489:119543c9f674 302 }
mbed_official 489:119543c9f674 303 }
mbed_official 489:119543c9f674 304 }
mbed_official 489:119543c9f674 305 /*------------------------------ LSI Configuration -------------------------*/
mbed_official 489:119543c9f674 306 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
mbed_official 489:119543c9f674 307 {
mbed_official 489:119543c9f674 308 /* Check the parameters */
mbed_official 489:119543c9f674 309 assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
mbed_official 489:119543c9f674 310
mbed_official 489:119543c9f674 311 /* Check the LSI State */
mbed_official 489:119543c9f674 312 if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF)
mbed_official 489:119543c9f674 313 {
mbed_official 489:119543c9f674 314 /* Enable the Internal Low Speed oscillator (LSI). */
mbed_official 489:119543c9f674 315 __HAL_RCC_LSI_ENABLE();
mbed_official 489:119543c9f674 316
mbed_official 489:119543c9f674 317 /* Get Start Tick*/
mbed_official 489:119543c9f674 318 tickstart = HAL_GetTick();
mbed_official 489:119543c9f674 319
mbed_official 489:119543c9f674 320 /* Wait till LSI is ready */
mbed_official 489:119543c9f674 321 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
mbed_official 489:119543c9f674 322 {
mbed_official 489:119543c9f674 323 if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
mbed_official 489:119543c9f674 324 {
mbed_official 489:119543c9f674 325 return HAL_TIMEOUT;
mbed_official 489:119543c9f674 326 }
mbed_official 489:119543c9f674 327 }
mbed_official 489:119543c9f674 328 /* To have a fully stabilized clock in the specified range, a software temporization of 1ms
mbed_official 489:119543c9f674 329 should be added.*/
mbed_official 489:119543c9f674 330 HAL_Delay(1);
mbed_official 489:119543c9f674 331 }
mbed_official 489:119543c9f674 332 else
mbed_official 489:119543c9f674 333 {
mbed_official 489:119543c9f674 334 /* Disable the Internal Low Speed oscillator (LSI). */
mbed_official 489:119543c9f674 335 __HAL_RCC_LSI_DISABLE();
mbed_official 489:119543c9f674 336
mbed_official 489:119543c9f674 337 /* Get Start Tick*/
mbed_official 489:119543c9f674 338 tickstart = HAL_GetTick();
mbed_official 489:119543c9f674 339
mbed_official 489:119543c9f674 340 /* Wait till LSI is disabled */
mbed_official 489:119543c9f674 341 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
mbed_official 489:119543c9f674 342 {
mbed_official 489:119543c9f674 343 if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
mbed_official 489:119543c9f674 344 {
mbed_official 489:119543c9f674 345 return HAL_TIMEOUT;
mbed_official 489:119543c9f674 346 }
mbed_official 489:119543c9f674 347 }
mbed_official 489:119543c9f674 348 }
mbed_official 489:119543c9f674 349 }
mbed_official 489:119543c9f674 350 /*------------------------------ LSE Configuration -------------------------*/
mbed_official 489:119543c9f674 351 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
mbed_official 489:119543c9f674 352 {
mbed_official 489:119543c9f674 353 /* Check the parameters */
mbed_official 489:119543c9f674 354 assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
mbed_official 489:119543c9f674 355
mbed_official 489:119543c9f674 356 /* Enable Power Clock*/
mbed_official 489:119543c9f674 357 __HAL_RCC_PWR_CLK_ENABLE();
mbed_official 489:119543c9f674 358
mbed_official 489:119543c9f674 359 /* Enable write access to Backup domain */
mbed_official 489:119543c9f674 360 SET_BIT(PWR->CR, PWR_CR_DBP);
mbed_official 489:119543c9f674 361
mbed_official 489:119543c9f674 362 /* Wait for Backup domain Write protection disable */
mbed_official 489:119543c9f674 363 tickstart = HAL_GetTick();
mbed_official 489:119543c9f674 364
mbed_official 489:119543c9f674 365 while((PWR->CR & PWR_CR_DBP) == RESET)
mbed_official 489:119543c9f674 366 {
mbed_official 489:119543c9f674 367 if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
mbed_official 489:119543c9f674 368 {
mbed_official 489:119543c9f674 369 return HAL_TIMEOUT;
mbed_official 489:119543c9f674 370 }
mbed_official 489:119543c9f674 371 }
mbed_official 489:119543c9f674 372
mbed_official 489:119543c9f674 373 /* Reset LSEON and LSEBYP bits before configuring the LSE ----------------*/
mbed_official 489:119543c9f674 374 __HAL_RCC_LSE_CONFIG(RCC_LSE_OFF);
mbed_official 489:119543c9f674 375
mbed_official 489:119543c9f674 376 /* Get Start Tick*/
mbed_official 489:119543c9f674 377 tickstart = HAL_GetTick();
mbed_official 489:119543c9f674 378
mbed_official 489:119543c9f674 379 /* Wait till LSE is disabled */
mbed_official 489:119543c9f674 380 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
mbed_official 489:119543c9f674 381 {
mbed_official 489:119543c9f674 382 if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
mbed_official 489:119543c9f674 383 {
mbed_official 489:119543c9f674 384 return HAL_TIMEOUT;
mbed_official 489:119543c9f674 385 }
mbed_official 489:119543c9f674 386 }
mbed_official 489:119543c9f674 387
mbed_official 489:119543c9f674 388 /* Set the new LSE configuration -----------------------------------------*/
mbed_official 489:119543c9f674 389 __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
mbed_official 489:119543c9f674 390 /* Check the LSE State */
mbed_official 489:119543c9f674 391 if((RCC_OscInitStruct->LSEState) == RCC_LSE_ON)
mbed_official 489:119543c9f674 392 {
mbed_official 489:119543c9f674 393 /* Get Start Tick*/
mbed_official 489:119543c9f674 394 tickstart = HAL_GetTick();
mbed_official 489:119543c9f674 395
mbed_official 489:119543c9f674 396 /* Wait till LSE is ready */
mbed_official 489:119543c9f674 397 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
mbed_official 489:119543c9f674 398 {
mbed_official 489:119543c9f674 399 if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
mbed_official 489:119543c9f674 400 {
mbed_official 489:119543c9f674 401 return HAL_TIMEOUT;
mbed_official 489:119543c9f674 402 }
mbed_official 489:119543c9f674 403 }
mbed_official 489:119543c9f674 404 }
mbed_official 489:119543c9f674 405 else
mbed_official 489:119543c9f674 406 {
mbed_official 489:119543c9f674 407 /* Get Start Tick*/
mbed_official 489:119543c9f674 408 tickstart = HAL_GetTick();
mbed_official 489:119543c9f674 409
mbed_official 489:119543c9f674 410 /* Wait till LSE is disabled */
mbed_official 489:119543c9f674 411 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
mbed_official 489:119543c9f674 412 {
mbed_official 489:119543c9f674 413 if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
mbed_official 489:119543c9f674 414 {
mbed_official 489:119543c9f674 415 return HAL_TIMEOUT;
mbed_official 489:119543c9f674 416 }
mbed_official 489:119543c9f674 417 }
mbed_official 489:119543c9f674 418 }
mbed_official 489:119543c9f674 419 }
mbed_official 489:119543c9f674 420
mbed_official 489:119543c9f674 421 /*-------------------------------- PLL2 Configuration -----------------------*/
mbed_official 489:119543c9f674 422 /* Check the parameters */
mbed_official 489:119543c9f674 423 assert_param(IS_RCC_PLL2(RCC_OscInitStruct->PLL2.PLL2State));
mbed_official 489:119543c9f674 424 if ((RCC_OscInitStruct->PLL2.PLL2State) != RCC_PLL2_NONE)
mbed_official 489:119543c9f674 425 {
mbed_official 489:119543c9f674 426 /* This bit can not be cleared if the PLL2 clock is used indirectly as system
mbed_official 489:119543c9f674 427 clock (i.e. it is used as PLL clock entry that is used as system clock). */
mbed_official 489:119543c9f674 428 if((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && \
mbed_official 489:119543c9f674 429 (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && \
mbed_official 489:119543c9f674 430 ((READ_BIT(RCC->CFGR2,RCC_CFGR2_PREDIV1SRC)) == RCC_CFGR2_PREDIV1SRC_PLL2))
mbed_official 489:119543c9f674 431 {
mbed_official 489:119543c9f674 432 return HAL_ERROR;
mbed_official 489:119543c9f674 433 }
mbed_official 489:119543c9f674 434 else
mbed_official 489:119543c9f674 435 {
mbed_official 489:119543c9f674 436 if((RCC_OscInitStruct->PLL2.PLL2State) == RCC_PLL2_ON)
mbed_official 489:119543c9f674 437 {
mbed_official 489:119543c9f674 438 /* Check the parameters */
mbed_official 489:119543c9f674 439 assert_param(IS_RCC_PLL2_MUL(RCC_OscInitStruct->PLL2.PLL2MUL));
mbed_official 489:119543c9f674 440 assert_param(IS_RCC_HSE_PREDIV2(RCC_OscInitStruct->PLL2.HSEPrediv2Value));
mbed_official 489:119543c9f674 441
mbed_official 489:119543c9f674 442 /* Prediv2 can be written only when the PLLI2S is disabled. */
mbed_official 489:119543c9f674 443 /* Return an error only if new value is different from the programmed value */
mbed_official 489:119543c9f674 444 if (HAL_IS_BIT_SET(RCC->CR,RCC_CR_PLL3ON) && \
mbed_official 489:119543c9f674 445 (__HAL_RCC_HSE_GET_PREDIV2() != RCC_OscInitStruct->PLL2.HSEPrediv2Value))
mbed_official 489:119543c9f674 446 {
mbed_official 489:119543c9f674 447 return HAL_ERROR;
mbed_official 489:119543c9f674 448 }
mbed_official 489:119543c9f674 449
mbed_official 489:119543c9f674 450 /* Disable the main PLL2. */
mbed_official 489:119543c9f674 451 __HAL_RCC_PLL2_DISABLE();
mbed_official 489:119543c9f674 452
mbed_official 489:119543c9f674 453 /* Get Start Tick*/
mbed_official 489:119543c9f674 454 tickstart = HAL_GetTick();
mbed_official 489:119543c9f674 455
mbed_official 489:119543c9f674 456 /* Wait till PLL2 is disabled */
mbed_official 489:119543c9f674 457 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET)
mbed_official 489:119543c9f674 458 {
mbed_official 489:119543c9f674 459 if((HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE)
mbed_official 489:119543c9f674 460 {
mbed_official 489:119543c9f674 461 return HAL_TIMEOUT;
mbed_official 489:119543c9f674 462 }
mbed_official 489:119543c9f674 463 }
mbed_official 489:119543c9f674 464
mbed_official 489:119543c9f674 465 /* Configure the HSE prediv2 factor --------------------------------*/
mbed_official 489:119543c9f674 466 __HAL_RCC_HSE_PREDIV2_CONFIG(RCC_OscInitStruct->PLL2.HSEPrediv2Value);
mbed_official 489:119543c9f674 467
mbed_official 489:119543c9f674 468 /* Configure the main PLL2 multiplication factors. */
mbed_official 489:119543c9f674 469 __HAL_RCC_PLL2_CONFIG(RCC_OscInitStruct->PLL2.PLL2MUL);
mbed_official 489:119543c9f674 470
mbed_official 489:119543c9f674 471 /* Enable the main PLL2. */
mbed_official 489:119543c9f674 472 __HAL_RCC_PLL2_ENABLE();
mbed_official 489:119543c9f674 473
mbed_official 489:119543c9f674 474 /* Get Start Tick*/
mbed_official 489:119543c9f674 475 tickstart = HAL_GetTick();
mbed_official 489:119543c9f674 476
mbed_official 489:119543c9f674 477 /* Wait till PLL2 is ready */
mbed_official 489:119543c9f674 478 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == RESET)
mbed_official 489:119543c9f674 479 {
mbed_official 489:119543c9f674 480 if((HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE)
mbed_official 489:119543c9f674 481 {
mbed_official 489:119543c9f674 482 return HAL_TIMEOUT;
mbed_official 489:119543c9f674 483 }
mbed_official 489:119543c9f674 484 }
mbed_official 489:119543c9f674 485 }
mbed_official 489:119543c9f674 486 else
mbed_official 489:119543c9f674 487 {
mbed_official 489:119543c9f674 488 /* Set PREDIV1 source to HSE */
mbed_official 489:119543c9f674 489 CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC);
mbed_official 489:119543c9f674 490
mbed_official 489:119543c9f674 491 /* Disable the main PLL2. */
mbed_official 489:119543c9f674 492 __HAL_RCC_PLL2_DISABLE();
mbed_official 489:119543c9f674 493
mbed_official 489:119543c9f674 494 /* Get Start Tick*/
mbed_official 489:119543c9f674 495 tickstart = HAL_GetTick();
mbed_official 489:119543c9f674 496
mbed_official 489:119543c9f674 497 /* Wait till PLL2 is disabled */
mbed_official 489:119543c9f674 498 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET)
mbed_official 489:119543c9f674 499 {
mbed_official 489:119543c9f674 500 if((HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE)
mbed_official 489:119543c9f674 501 {
mbed_official 489:119543c9f674 502 return HAL_TIMEOUT;
mbed_official 489:119543c9f674 503 }
mbed_official 489:119543c9f674 504 }
mbed_official 489:119543c9f674 505 }
mbed_official 489:119543c9f674 506 }
mbed_official 489:119543c9f674 507 }
mbed_official 489:119543c9f674 508
mbed_official 489:119543c9f674 509 /*-------------------------------- PLL Configuration -----------------------*/
mbed_official 489:119543c9f674 510 /* Check the parameters */
mbed_official 489:119543c9f674 511 assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
mbed_official 489:119543c9f674 512 if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
mbed_official 489:119543c9f674 513 {
mbed_official 489:119543c9f674 514 /* Check if the PLL is used as system clock or not */
mbed_official 489:119543c9f674 515 if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
mbed_official 489:119543c9f674 516 {
mbed_official 489:119543c9f674 517 if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
mbed_official 489:119543c9f674 518 {
mbed_official 489:119543c9f674 519 /* Check the parameters */
mbed_official 489:119543c9f674 520 assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
mbed_official 489:119543c9f674 521 assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL));
mbed_official 489:119543c9f674 522
mbed_official 489:119543c9f674 523 /* Disable the main PLL. */
mbed_official 489:119543c9f674 524 __HAL_RCC_PLL_DISABLE();
mbed_official 489:119543c9f674 525
mbed_official 489:119543c9f674 526 /* Get Start Tick*/
mbed_official 489:119543c9f674 527 tickstart = HAL_GetTick();
mbed_official 489:119543c9f674 528
mbed_official 489:119543c9f674 529 /* Wait till PLL is disabled */
mbed_official 489:119543c9f674 530 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
mbed_official 489:119543c9f674 531 {
mbed_official 489:119543c9f674 532 if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
mbed_official 489:119543c9f674 533 {
mbed_official 489:119543c9f674 534 return HAL_TIMEOUT;
mbed_official 489:119543c9f674 535 }
mbed_official 489:119543c9f674 536 }
mbed_official 489:119543c9f674 537
mbed_official 489:119543c9f674 538 /* Configure the HSE prediv1 factor and source --------------------------------*/
mbed_official 489:119543c9f674 539 /* It can be written only when the PLL is disabled. Not used in PLL source is different than HSE */
mbed_official 489:119543c9f674 540 if(RCC_OscInitStruct->PLL.PLLSource == RCC_PLLSOURCE_HSE)
mbed_official 489:119543c9f674 541 {
mbed_official 489:119543c9f674 542 /* Check the parameter */
mbed_official 489:119543c9f674 543 assert_param(IS_RCC_PREDIV1_SOURCE(RCC_OscInitStruct->Prediv1Source));
mbed_official 489:119543c9f674 544 assert_param(IS_RCC_HSE_PREDIV(RCC_OscInitStruct->HSEPredivValue));
mbed_official 489:119543c9f674 545
mbed_official 489:119543c9f674 546 /* Set PREDIV1 source */
mbed_official 489:119543c9f674 547 SET_BIT(RCC->CFGR2, RCC_OscInitStruct->Prediv1Source);
mbed_official 489:119543c9f674 548
mbed_official 489:119543c9f674 549 /* Set PREDIV1 Value */
mbed_official 489:119543c9f674 550 __HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue);
mbed_official 489:119543c9f674 551 }
mbed_official 489:119543c9f674 552
mbed_official 489:119543c9f674 553 /* Configure the main PLL clock source and multiplication factors. */
mbed_official 489:119543c9f674 554 __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
mbed_official 489:119543c9f674 555 RCC_OscInitStruct->PLL.PLLMUL);
mbed_official 489:119543c9f674 556 /* Enable the main PLL. */
mbed_official 489:119543c9f674 557 __HAL_RCC_PLL_ENABLE();
mbed_official 489:119543c9f674 558
mbed_official 489:119543c9f674 559 /* Get Start Tick*/
mbed_official 489:119543c9f674 560 tickstart = HAL_GetTick();
mbed_official 489:119543c9f674 561
mbed_official 489:119543c9f674 562 /* Wait till PLL is ready */
mbed_official 489:119543c9f674 563 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
mbed_official 489:119543c9f674 564 {
mbed_official 489:119543c9f674 565 if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
mbed_official 489:119543c9f674 566 {
mbed_official 489:119543c9f674 567 return HAL_TIMEOUT;
mbed_official 489:119543c9f674 568 }
mbed_official 489:119543c9f674 569 }
mbed_official 489:119543c9f674 570 }
mbed_official 489:119543c9f674 571 else
mbed_official 489:119543c9f674 572 {
mbed_official 489:119543c9f674 573 /* Disable the main PLL. */
mbed_official 489:119543c9f674 574 __HAL_RCC_PLL_DISABLE();
mbed_official 489:119543c9f674 575
mbed_official 489:119543c9f674 576 /* Get Start Tick*/
mbed_official 489:119543c9f674 577 tickstart = HAL_GetTick();
mbed_official 489:119543c9f674 578
mbed_official 489:119543c9f674 579 /* Wait till PLL is disabled */
mbed_official 489:119543c9f674 580 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
mbed_official 489:119543c9f674 581 {
mbed_official 489:119543c9f674 582 if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
mbed_official 489:119543c9f674 583 {
mbed_official 489:119543c9f674 584 return HAL_TIMEOUT;
mbed_official 489:119543c9f674 585 }
mbed_official 489:119543c9f674 586 }
mbed_official 489:119543c9f674 587 }
mbed_official 489:119543c9f674 588 }
mbed_official 489:119543c9f674 589 else
mbed_official 489:119543c9f674 590 {
mbed_official 489:119543c9f674 591 return HAL_ERROR;
mbed_official 489:119543c9f674 592 }
mbed_official 489:119543c9f674 593 }
mbed_official 489:119543c9f674 594
mbed_official 489:119543c9f674 595 return HAL_OK;
mbed_official 489:119543c9f674 596 }
mbed_official 489:119543c9f674 597 /**
mbed_official 489:119543c9f674 598 * @}
mbed_official 489:119543c9f674 599 */
mbed_official 489:119543c9f674 600
mbed_official 489:119543c9f674 601 #endif /* STM32F105xC STM32F107xC */
mbed_official 489:119543c9f674 602
mbed_official 489:119543c9f674 603 #if defined(STM32F101x6) || defined(STM32F101xB) || defined(STM32F101xE) || defined(STM32F101xG) || \
mbed_official 489:119543c9f674 604 defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || defined(STM32F103xB) || \
mbed_official 489:119543c9f674 605 defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
mbed_official 489:119543c9f674 606 /** @addtogroup RCC_Exported_Functions_Group1
mbed_official 489:119543c9f674 607 * @{
mbed_official 489:119543c9f674 608 */
mbed_official 489:119543c9f674 609
mbed_official 489:119543c9f674 610 /**
mbed_official 489:119543c9f674 611 * @brief Initializes the CPU, AHB and APB busses clocks according to the specified
mbed_official 489:119543c9f674 612 * parameters in the RCC_ClkInitStruct.
mbed_official 489:119543c9f674 613 * @param RCC_ClkInitStruct: pointer to an RCC_OscInitTypeDef structure that
mbed_official 489:119543c9f674 614 * contains the configuration information for the RCC peripheral.
mbed_official 489:119543c9f674 615 * @param FLatency: FLASH Latency
mbed_official 489:119543c9f674 616 * This parameter can be one of the following values:
mbed_official 489:119543c9f674 617 * @arg FLASH_LATENCY_0: FLASH 0 Latency cycle
mbed_official 489:119543c9f674 618 *
mbed_official 489:119543c9f674 619 * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
mbed_official 489:119543c9f674 620 * and updated by HAL_RCC_GetHCLKFreq() function called within this function
mbed_official 489:119543c9f674 621 *
mbed_official 489:119543c9f674 622 * @note The HSI is used (enabled by hardware) as system clock source after
mbed_official 489:119543c9f674 623 * startup from Reset, wake-up from STOP and STANDBY mode, or in case
mbed_official 489:119543c9f674 624 * of failure of the HSE used directly or indirectly as system clock
mbed_official 489:119543c9f674 625 * (if the Clock Security System CSS is enabled).
mbed_official 489:119543c9f674 626 *
mbed_official 489:119543c9f674 627 * @note A switch from one clock source to another occurs only if the target
mbed_official 489:119543c9f674 628 * clock source is ready (clock stable after startup delay or PLL locked).
mbed_official 489:119543c9f674 629 * If a clock source which is not yet ready is selected, the switch will
mbed_official 489:119543c9f674 630 * occur when the clock source will be ready.
mbed_official 489:119543c9f674 631 * You can use HAL_RCC_GetClockConfig() function to know which clock is
mbed_official 489:119543c9f674 632 * currently used as system clock source.
mbed_official 489:119543c9f674 633 * @retval None
mbed_official 489:119543c9f674 634 */
mbed_official 489:119543c9f674 635 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
mbed_official 489:119543c9f674 636 {
mbed_official 489:119543c9f674 637 uint32_t tickstart = 0;
mbed_official 489:119543c9f674 638
mbed_official 489:119543c9f674 639 /* Check the parameters */
mbed_official 489:119543c9f674 640 assert_param(RCC_ClkInitStruct != NULL);
mbed_official 489:119543c9f674 641 assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));
mbed_official 489:119543c9f674 642 assert_param(IS_FLASH_LATENCY(FLatency));
mbed_official 489:119543c9f674 643
mbed_official 489:119543c9f674 644 /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
mbed_official 489:119543c9f674 645 must be correctly programmed according to the frequency of the CPU clock
mbed_official 489:119543c9f674 646 (HCLK) of the device. */
mbed_official 489:119543c9f674 647
mbed_official 489:119543c9f674 648 /* Increasing the CPU frequency */
mbed_official 489:119543c9f674 649 if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY))
mbed_official 489:119543c9f674 650 {
mbed_official 489:119543c9f674 651 /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
mbed_official 489:119543c9f674 652 __HAL_FLASH_SET_LATENCY(FLatency);
mbed_official 489:119543c9f674 653
mbed_official 489:119543c9f674 654 /* Check that the new number of wait states is taken into account to access the Flash
mbed_official 489:119543c9f674 655 memory by reading the FLASH_ACR register */
mbed_official 489:119543c9f674 656 if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
mbed_official 489:119543c9f674 657 {
mbed_official 489:119543c9f674 658 return HAL_ERROR;
mbed_official 489:119543c9f674 659 }
mbed_official 489:119543c9f674 660 /*-------------------------- HCLK Configuration --------------------------*/
mbed_official 489:119543c9f674 661 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
mbed_official 489:119543c9f674 662 {
mbed_official 489:119543c9f674 663 assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
mbed_official 489:119543c9f674 664 MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
mbed_official 489:119543c9f674 665 }
mbed_official 489:119543c9f674 666
mbed_official 489:119543c9f674 667 /*------------------------- SYSCLK Configuration ---------------------------*/
mbed_official 489:119543c9f674 668 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
mbed_official 489:119543c9f674 669 {
mbed_official 489:119543c9f674 670 assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
mbed_official 489:119543c9f674 671
mbed_official 489:119543c9f674 672 /* HSE is selected as System Clock Source */
mbed_official 489:119543c9f674 673 if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
mbed_official 489:119543c9f674 674 {
mbed_official 489:119543c9f674 675 /* Check the HSE ready flag */
mbed_official 489:119543c9f674 676 if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
mbed_official 489:119543c9f674 677 {
mbed_official 489:119543c9f674 678 return HAL_ERROR;
mbed_official 489:119543c9f674 679 }
mbed_official 489:119543c9f674 680 }
mbed_official 489:119543c9f674 681 /* PLL is selected as System Clock Source */
mbed_official 489:119543c9f674 682 else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
mbed_official 489:119543c9f674 683 {
mbed_official 489:119543c9f674 684 /* Check the PLL ready flag */
mbed_official 489:119543c9f674 685 if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
mbed_official 489:119543c9f674 686 {
mbed_official 489:119543c9f674 687 return HAL_ERROR;
mbed_official 489:119543c9f674 688 }
mbed_official 489:119543c9f674 689 }
mbed_official 489:119543c9f674 690 /* HSI is selected as System Clock Source */
mbed_official 489:119543c9f674 691 else
mbed_official 489:119543c9f674 692 {
mbed_official 489:119543c9f674 693 /* Check the HSI ready flag */
mbed_official 489:119543c9f674 694 if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
mbed_official 489:119543c9f674 695 {
mbed_official 489:119543c9f674 696 return HAL_ERROR;
mbed_official 489:119543c9f674 697 }
mbed_official 489:119543c9f674 698 }
mbed_official 489:119543c9f674 699
mbed_official 489:119543c9f674 700 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
mbed_official 489:119543c9f674 701
mbed_official 489:119543c9f674 702 /* Get Start Tick*/
mbed_official 489:119543c9f674 703 tickstart = HAL_GetTick();
mbed_official 489:119543c9f674 704
mbed_official 489:119543c9f674 705 if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
mbed_official 489:119543c9f674 706 {
mbed_official 489:119543c9f674 707 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
mbed_official 489:119543c9f674 708 {
mbed_official 489:119543c9f674 709 if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
mbed_official 489:119543c9f674 710 {
mbed_official 489:119543c9f674 711 return HAL_TIMEOUT;
mbed_official 489:119543c9f674 712 }
mbed_official 489:119543c9f674 713 }
mbed_official 489:119543c9f674 714 }
mbed_official 489:119543c9f674 715 else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
mbed_official 489:119543c9f674 716 {
mbed_official 489:119543c9f674 717 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
mbed_official 489:119543c9f674 718 {
mbed_official 489:119543c9f674 719 if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
mbed_official 489:119543c9f674 720 {
mbed_official 489:119543c9f674 721 return HAL_TIMEOUT;
mbed_official 489:119543c9f674 722 }
mbed_official 489:119543c9f674 723 }
mbed_official 489:119543c9f674 724 }
mbed_official 489:119543c9f674 725 else
mbed_official 489:119543c9f674 726 {
mbed_official 489:119543c9f674 727 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
mbed_official 489:119543c9f674 728 {
mbed_official 489:119543c9f674 729 if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
mbed_official 489:119543c9f674 730 {
mbed_official 489:119543c9f674 731 return HAL_TIMEOUT;
mbed_official 489:119543c9f674 732 }
mbed_official 489:119543c9f674 733 }
mbed_official 489:119543c9f674 734 }
mbed_official 489:119543c9f674 735 }
mbed_official 489:119543c9f674 736 }
mbed_official 489:119543c9f674 737 /* Decreasing the CPU frequency */
mbed_official 489:119543c9f674 738 else
mbed_official 489:119543c9f674 739 {
mbed_official 489:119543c9f674 740 /*-------------------------- HCLK Configuration --------------------------*/
mbed_official 489:119543c9f674 741 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
mbed_official 489:119543c9f674 742 {
mbed_official 489:119543c9f674 743 assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
mbed_official 489:119543c9f674 744 MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
mbed_official 489:119543c9f674 745 }
mbed_official 489:119543c9f674 746
mbed_official 489:119543c9f674 747 /*------------------------- SYSCLK Configuration -------------------------*/
mbed_official 489:119543c9f674 748 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
mbed_official 489:119543c9f674 749 {
mbed_official 489:119543c9f674 750 assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
mbed_official 489:119543c9f674 751
mbed_official 489:119543c9f674 752 /* HSE is selected as System Clock Source */
mbed_official 489:119543c9f674 753 if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
mbed_official 489:119543c9f674 754 {
mbed_official 489:119543c9f674 755 /* Check the HSE ready flag */
mbed_official 489:119543c9f674 756 if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
mbed_official 489:119543c9f674 757 {
mbed_official 489:119543c9f674 758 return HAL_ERROR;
mbed_official 489:119543c9f674 759 }
mbed_official 489:119543c9f674 760 }
mbed_official 489:119543c9f674 761 /* PLL is selected as System Clock Source */
mbed_official 489:119543c9f674 762 else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
mbed_official 489:119543c9f674 763 {
mbed_official 489:119543c9f674 764 /* Check the PLL ready flag */
mbed_official 489:119543c9f674 765 if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
mbed_official 489:119543c9f674 766 {
mbed_official 489:119543c9f674 767 return HAL_ERROR;
mbed_official 489:119543c9f674 768 }
mbed_official 489:119543c9f674 769 }
mbed_official 489:119543c9f674 770 /* HSI is selected as System Clock Source */
mbed_official 489:119543c9f674 771 else
mbed_official 489:119543c9f674 772 {
mbed_official 489:119543c9f674 773 /* Check the HSI ready flag */
mbed_official 489:119543c9f674 774 if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
mbed_official 489:119543c9f674 775 {
mbed_official 489:119543c9f674 776 return HAL_ERROR;
mbed_official 489:119543c9f674 777 }
mbed_official 489:119543c9f674 778 }
mbed_official 489:119543c9f674 779
mbed_official 489:119543c9f674 780 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
mbed_official 489:119543c9f674 781
mbed_official 489:119543c9f674 782 /* Get Start Tick*/
mbed_official 489:119543c9f674 783 tickstart = HAL_GetTick();
mbed_official 489:119543c9f674 784
mbed_official 489:119543c9f674 785 if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
mbed_official 489:119543c9f674 786 {
mbed_official 489:119543c9f674 787 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
mbed_official 489:119543c9f674 788 {
mbed_official 489:119543c9f674 789 if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
mbed_official 489:119543c9f674 790 {
mbed_official 489:119543c9f674 791 return HAL_TIMEOUT;
mbed_official 489:119543c9f674 792 }
mbed_official 489:119543c9f674 793 }
mbed_official 489:119543c9f674 794 }
mbed_official 489:119543c9f674 795 else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
mbed_official 489:119543c9f674 796 {
mbed_official 489:119543c9f674 797 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
mbed_official 489:119543c9f674 798 {
mbed_official 489:119543c9f674 799 if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
mbed_official 489:119543c9f674 800 {
mbed_official 489:119543c9f674 801 return HAL_TIMEOUT;
mbed_official 489:119543c9f674 802 }
mbed_official 489:119543c9f674 803 }
mbed_official 489:119543c9f674 804 }
mbed_official 489:119543c9f674 805 else
mbed_official 489:119543c9f674 806 {
mbed_official 489:119543c9f674 807 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
mbed_official 489:119543c9f674 808 {
mbed_official 489:119543c9f674 809 if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
mbed_official 489:119543c9f674 810 {
mbed_official 489:119543c9f674 811 return HAL_TIMEOUT;
mbed_official 489:119543c9f674 812 }
mbed_official 489:119543c9f674 813 }
mbed_official 489:119543c9f674 814 }
mbed_official 489:119543c9f674 815 }
mbed_official 489:119543c9f674 816
mbed_official 489:119543c9f674 817 /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
mbed_official 489:119543c9f674 818 __HAL_FLASH_SET_LATENCY(FLatency);
mbed_official 489:119543c9f674 819
mbed_official 489:119543c9f674 820 /* Check that the new number of wait states is taken into account to access the Flash
mbed_official 489:119543c9f674 821 memory by reading the FLASH_ACR register */
mbed_official 489:119543c9f674 822 if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
mbed_official 489:119543c9f674 823 {
mbed_official 489:119543c9f674 824 return HAL_ERROR;
mbed_official 489:119543c9f674 825 }
mbed_official 489:119543c9f674 826 }
mbed_official 489:119543c9f674 827
mbed_official 489:119543c9f674 828 /*-------------------------- PCLK1 Configuration ---------------------------*/
mbed_official 489:119543c9f674 829 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
mbed_official 489:119543c9f674 830 {
mbed_official 489:119543c9f674 831 assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
mbed_official 489:119543c9f674 832 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
mbed_official 489:119543c9f674 833 }
mbed_official 489:119543c9f674 834
mbed_official 489:119543c9f674 835 /*-------------------------- PCLK2 Configuration ---------------------------*/
mbed_official 489:119543c9f674 836 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
mbed_official 489:119543c9f674 837 {
mbed_official 489:119543c9f674 838 assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
mbed_official 489:119543c9f674 839 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
mbed_official 489:119543c9f674 840 }
mbed_official 489:119543c9f674 841
mbed_official 489:119543c9f674 842 /* Configure the source of time base considering new system clocks settings*/
mbed_official 489:119543c9f674 843 HAL_InitTick (TICK_INT_PRIORITY);
mbed_official 489:119543c9f674 844
mbed_official 489:119543c9f674 845 return HAL_OK;
mbed_official 489:119543c9f674 846 }
mbed_official 489:119543c9f674 847 /**
mbed_official 489:119543c9f674 848 * @}
mbed_official 489:119543c9f674 849 */
mbed_official 489:119543c9f674 850
mbed_official 489:119543c9f674 851 #endif /* STM32F101x6 || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */
mbed_official 489:119543c9f674 852
mbed_official 489:119543c9f674 853 #if defined(STM32F105xC) || defined(STM32F107xC)
mbed_official 489:119543c9f674 854 /** @addtogroup RCC_Exported_Functions_Group2
mbed_official 489:119543c9f674 855 * @{
mbed_official 489:119543c9f674 856 */
mbed_official 489:119543c9f674 857
mbed_official 489:119543c9f674 858 /**
mbed_official 489:119543c9f674 859 * @brief Returns the SYSCLK frequency
mbed_official 489:119543c9f674 860 *
mbed_official 489:119543c9f674 861 * @note The system frequency computed by this function is not the real
mbed_official 489:119543c9f674 862 * frequency in the chip. It is calculated based on the predefined
mbed_official 489:119543c9f674 863 * constant and the selected clock source:
mbed_official 489:119543c9f674 864 * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
mbed_official 489:119543c9f674 865 * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE
mbed_official 489:119543c9f674 866 * divided by PREDIV factor(**)
mbed_official 489:119543c9f674 867 * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE
mbed_official 489:119543c9f674 868 * divided by PREDIV factor(**) or HSI_VALUE(*) multiplied by the PLL factor.
mbed_official 489:119543c9f674 869 * @note (*) HSI_VALUE is a constant defined in stm32f1xx_hal_conf.h file (default value
mbed_official 489:119543c9f674 870 * 8 MHz).
mbed_official 489:119543c9f674 871 * @note (**) HSE_VALUE is a constant defined in stm32f1xx_hal_conf.h file (default value
mbed_official 489:119543c9f674 872 * 8 MHz), user has to ensure that HSE_VALUE is same as the real
mbed_official 489:119543c9f674 873 * frequency of the crystal used. Otherwise, this function may
mbed_official 489:119543c9f674 874 * have wrong result.
mbed_official 489:119543c9f674 875 *
mbed_official 489:119543c9f674 876 * @note The result of this function could be not correct when using fractional
mbed_official 489:119543c9f674 877 * value for HSE crystal.
mbed_official 489:119543c9f674 878 *
mbed_official 489:119543c9f674 879 * @note This function can be used by the user application to compute the
mbed_official 489:119543c9f674 880 * baudrate for the communication peripherals or configure other parameters.
mbed_official 489:119543c9f674 881 *
mbed_official 489:119543c9f674 882 * @note Each time SYSCLK changes, this function must be called to update the
mbed_official 489:119543c9f674 883 * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
mbed_official 489:119543c9f674 884 *
mbed_official 489:119543c9f674 885 *
mbed_official 489:119543c9f674 886 * @retval SYSCLK frequency
mbed_official 489:119543c9f674 887 */
mbed_official 489:119543c9f674 888 uint32_t HAL_RCC_GetSysClockFreq(void)
mbed_official 489:119543c9f674 889 {
mbed_official 489:119543c9f674 890 const uint8_t aPLLMULFactorTable[12] = {0, 0, 4, 5, 6, 7, 8, 9, 0, 0, 0, 13};
mbed_official 489:119543c9f674 891 const uint8_t aPredivFactorTable[16] = { 1, 2, 3, 4, 5, 6, 7, 8, 9,10, 11, 12, 13, 14, 15, 16};
mbed_official 489:119543c9f674 892
mbed_official 489:119543c9f674 893 uint32_t tmp_reg = 0, prediv1 = 0, pllclk = 0, pllmul = 0;
mbed_official 489:119543c9f674 894 uint32_t sysclockfreq = 0;
mbed_official 489:119543c9f674 895 uint32_t prediv2 = 0, pll2mul = 0;
mbed_official 489:119543c9f674 896
mbed_official 489:119543c9f674 897 tmp_reg = RCC->CFGR;
mbed_official 489:119543c9f674 898
mbed_official 489:119543c9f674 899 /* Get SYSCLK source -------------------------------------------------------*/
mbed_official 489:119543c9f674 900 switch (tmp_reg & RCC_CFGR_SWS)
mbed_official 489:119543c9f674 901 {
mbed_official 489:119543c9f674 902 case RCC_CFGR_SWS_HSE: /* HSE used as system clock */
mbed_official 489:119543c9f674 903 {
mbed_official 489:119543c9f674 904 sysclockfreq = HSE_VALUE;
mbed_official 489:119543c9f674 905 break;
mbed_official 489:119543c9f674 906 }
mbed_official 489:119543c9f674 907 case RCC_CFGR_SWS_PLL: /* PLL used as system clock */
mbed_official 489:119543c9f674 908 {
mbed_official 489:119543c9f674 909 pllmul = aPLLMULFactorTable[(uint32_t)(tmp_reg & RCC_CFGR_PLLMULL) >> POSITION_VAL(RCC_CFGR_PLLMULL)];
mbed_official 489:119543c9f674 910
mbed_official 489:119543c9f674 911 if ((tmp_reg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2)
mbed_official 489:119543c9f674 912 {
mbed_official 489:119543c9f674 913 prediv1 = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> POSITION_VAL(RCC_CFGR2_PREDIV1)];
mbed_official 489:119543c9f674 914 if(HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC))
mbed_official 489:119543c9f674 915 {
mbed_official 489:119543c9f674 916 /* PLL2 selected as Prediv1 source */
mbed_official 489:119543c9f674 917 /* PLLCLK = PLL2CLK / PREDIV1 * PLLMUL with PLL2CLK = HSE/PREDIV2 * PLL2MUL */
mbed_official 489:119543c9f674 918 prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> POSITION_VAL(RCC_CFGR2_PREDIV2)) + 1;
mbed_official 489:119543c9f674 919 pll2mul = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> POSITION_VAL(RCC_CFGR2_PLL2MUL)) + 2;
mbed_official 489:119543c9f674 920 pllclk = (uint32_t)((((HSE_VALUE / prediv2) * pll2mul) / prediv1) * pllmul);
mbed_official 489:119543c9f674 921 }
mbed_official 489:119543c9f674 922 else
mbed_official 489:119543c9f674 923 {
mbed_official 489:119543c9f674 924 /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */
mbed_official 489:119543c9f674 925 pllclk = (uint32_t)((HSE_VALUE / prediv1) * pllmul);
mbed_official 489:119543c9f674 926 }
mbed_official 489:119543c9f674 927
mbed_official 489:119543c9f674 928 /* If PLLMUL was set to 13 means that it was to cover the case PLLMUL 6.5 (avoid using float) */
mbed_official 489:119543c9f674 929 /* In this case need to divide pllclk by 2 */
mbed_official 489:119543c9f674 930 if (pllmul == aPLLMULFactorTable[(uint32_t)(RCC_CFGR_PLLMULL6_5) >> POSITION_VAL(RCC_CFGR_PLLMULL)])
mbed_official 489:119543c9f674 931 {
mbed_official 489:119543c9f674 932 pllclk = pllclk / 2;
mbed_official 489:119543c9f674 933 }
mbed_official 489:119543c9f674 934 }
mbed_official 489:119543c9f674 935 else
mbed_official 489:119543c9f674 936 {
mbed_official 489:119543c9f674 937 /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */
mbed_official 489:119543c9f674 938 pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul);
mbed_official 489:119543c9f674 939 }
mbed_official 489:119543c9f674 940 sysclockfreq = pllclk;
mbed_official 489:119543c9f674 941 break;
mbed_official 489:119543c9f674 942 }
mbed_official 489:119543c9f674 943 case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */
mbed_official 489:119543c9f674 944 default: /* HSI used as system clock */
mbed_official 489:119543c9f674 945 {
mbed_official 489:119543c9f674 946 sysclockfreq = HSI_VALUE;
mbed_official 489:119543c9f674 947 break;
mbed_official 489:119543c9f674 948 }
mbed_official 489:119543c9f674 949 }
mbed_official 489:119543c9f674 950 return sysclockfreq;
mbed_official 489:119543c9f674 951 }
mbed_official 489:119543c9f674 952
mbed_official 489:119543c9f674 953
mbed_official 489:119543c9f674 954 /**
mbed_official 489:119543c9f674 955 * @brief Configures the RCC_OscInitStruct according to the internal
mbed_official 489:119543c9f674 956 * RCC configuration registers.
mbed_official 489:119543c9f674 957 * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
mbed_official 489:119543c9f674 958 * will be configured.
mbed_official 489:119543c9f674 959 * @retval None
mbed_official 489:119543c9f674 960 */
mbed_official 489:119543c9f674 961 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
mbed_official 489:119543c9f674 962 {
mbed_official 489:119543c9f674 963 /* Check the parameters */
mbed_official 489:119543c9f674 964 assert_param(RCC_OscInitStruct != NULL);
mbed_official 489:119543c9f674 965
mbed_official 489:119543c9f674 966 /* Set all possible values for the Oscillator type parameter ---------------*/
mbed_official 489:119543c9f674 967 RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI \
mbed_official 489:119543c9f674 968 | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI;
mbed_official 489:119543c9f674 969
mbed_official 489:119543c9f674 970 /* Get the Prediv1 source --------------------------------------------------*/
mbed_official 489:119543c9f674 971 RCC_OscInitStruct->Prediv1Source = READ_BIT(RCC->CFGR2,RCC_CFGR2_PREDIV1SRC);
mbed_official 489:119543c9f674 972
mbed_official 489:119543c9f674 973 /* Get the HSE configuration -----------------------------------------------*/
mbed_official 489:119543c9f674 974 if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
mbed_official 489:119543c9f674 975 {
mbed_official 489:119543c9f674 976 RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
mbed_official 489:119543c9f674 977 }
mbed_official 489:119543c9f674 978 else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON)
mbed_official 489:119543c9f674 979 {
mbed_official 489:119543c9f674 980 RCC_OscInitStruct->HSEState = RCC_HSE_ON;
mbed_official 489:119543c9f674 981 }
mbed_official 489:119543c9f674 982 else
mbed_official 489:119543c9f674 983 {
mbed_official 489:119543c9f674 984 RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
mbed_official 489:119543c9f674 985 }
mbed_official 489:119543c9f674 986
mbed_official 489:119543c9f674 987 RCC_OscInitStruct->HSEPredivValue = __HAL_RCC_HSE_GET_PREDIV();
mbed_official 489:119543c9f674 988
mbed_official 489:119543c9f674 989 /* Get the HSI configuration -----------------------------------------------*/
mbed_official 489:119543c9f674 990 if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION)
mbed_official 489:119543c9f674 991 {
mbed_official 489:119543c9f674 992 RCC_OscInitStruct->HSIState = RCC_HSI_ON;
mbed_official 489:119543c9f674 993 }
mbed_official 489:119543c9f674 994 else
mbed_official 489:119543c9f674 995 {
mbed_official 489:119543c9f674 996 RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
mbed_official 489:119543c9f674 997 }
mbed_official 489:119543c9f674 998
mbed_official 489:119543c9f674 999 RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR & RCC_CR_HSITRIM) >> POSITION_VAL(RCC_CR_HSITRIM));
mbed_official 489:119543c9f674 1000
mbed_official 489:119543c9f674 1001 /* Get the LSE configuration -----------------------------------------------*/
mbed_official 489:119543c9f674 1002 if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
mbed_official 489:119543c9f674 1003 {
mbed_official 489:119543c9f674 1004 RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
mbed_official 489:119543c9f674 1005 }
mbed_official 489:119543c9f674 1006 else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
mbed_official 489:119543c9f674 1007 {
mbed_official 489:119543c9f674 1008 RCC_OscInitStruct->LSEState = RCC_LSE_ON;
mbed_official 489:119543c9f674 1009 }
mbed_official 489:119543c9f674 1010 else
mbed_official 489:119543c9f674 1011 {
mbed_official 489:119543c9f674 1012 RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
mbed_official 489:119543c9f674 1013 }
mbed_official 489:119543c9f674 1014
mbed_official 489:119543c9f674 1015 /* Get the LSI configuration -----------------------------------------------*/
mbed_official 489:119543c9f674 1016 if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION)
mbed_official 489:119543c9f674 1017 {
mbed_official 489:119543c9f674 1018 RCC_OscInitStruct->LSIState = RCC_LSI_ON;
mbed_official 489:119543c9f674 1019 }
mbed_official 489:119543c9f674 1020 else
mbed_official 489:119543c9f674 1021 {
mbed_official 489:119543c9f674 1022 RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
mbed_official 489:119543c9f674 1023 }
mbed_official 489:119543c9f674 1024
mbed_official 489:119543c9f674 1025 /* Get the PLL configuration -----------------------------------------------*/
mbed_official 489:119543c9f674 1026 if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON)
mbed_official 489:119543c9f674 1027 {
mbed_official 489:119543c9f674 1028 RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
mbed_official 489:119543c9f674 1029 }
mbed_official 489:119543c9f674 1030 else
mbed_official 489:119543c9f674 1031 {
mbed_official 489:119543c9f674 1032 RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
mbed_official 489:119543c9f674 1033 }
mbed_official 489:119543c9f674 1034 RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLSRC);
mbed_official 489:119543c9f674 1035 RCC_OscInitStruct->PLL.PLLMUL = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLMULL);
mbed_official 489:119543c9f674 1036
mbed_official 489:119543c9f674 1037 /* Get the PLL2 configuration -----------------------------------------------*/
mbed_official 489:119543c9f674 1038 if((RCC->CR &RCC_CR_PLL2ON) == RCC_CR_PLL2ON)
mbed_official 489:119543c9f674 1039 {
mbed_official 489:119543c9f674 1040 RCC_OscInitStruct->PLL2.PLL2State = RCC_PLL2_ON;
mbed_official 489:119543c9f674 1041 }
mbed_official 489:119543c9f674 1042 else
mbed_official 489:119543c9f674 1043 {
mbed_official 489:119543c9f674 1044 RCC_OscInitStruct->PLL2.PLL2State = RCC_PLL2_OFF;
mbed_official 489:119543c9f674 1045 }
mbed_official 489:119543c9f674 1046 RCC_OscInitStruct->PLL2.HSEPrediv2Value = __HAL_RCC_HSE_GET_PREDIV2();
mbed_official 489:119543c9f674 1047 RCC_OscInitStruct->PLL2.PLL2MUL = (uint32_t)(RCC->CFGR2 & RCC_CFGR2_PLL2MUL);
mbed_official 489:119543c9f674 1048 }
mbed_official 489:119543c9f674 1049
mbed_official 489:119543c9f674 1050 /**
mbed_official 489:119543c9f674 1051 * @}
mbed_official 489:119543c9f674 1052 */
mbed_official 489:119543c9f674 1053
mbed_official 489:119543c9f674 1054 #endif /* STM32F105xC || STM32F107xC*/
mbed_official 489:119543c9f674 1055
mbed_official 489:119543c9f674 1056 #if defined (STM32F100xB) || defined (STM32F100xE)
mbed_official 489:119543c9f674 1057 /** @addtogroup RCC_Exported_Functions_Group2
mbed_official 489:119543c9f674 1058 * @{
mbed_official 489:119543c9f674 1059 */
mbed_official 489:119543c9f674 1060
mbed_official 489:119543c9f674 1061 /**
mbed_official 489:119543c9f674 1062 * @brief Returns the SYSCLK frequency
mbed_official 489:119543c9f674 1063 *
mbed_official 489:119543c9f674 1064 * @note The system frequency computed by this function is not the real
mbed_official 489:119543c9f674 1065 * frequency in the chip. It is calculated based on the predefined
mbed_official 489:119543c9f674 1066 * constant and the selected clock source:
mbed_official 489:119543c9f674 1067 * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
mbed_official 489:119543c9f674 1068 * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE
mbed_official 489:119543c9f674 1069 * divided by PREDIV factor(**)
mbed_official 489:119543c9f674 1070 * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE
mbed_official 489:119543c9f674 1071 * divided by PREDIV factor(**) or HSI_VALUE(*) multiplied by the PLL factor.
mbed_official 489:119543c9f674 1072 * @note (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
mbed_official 489:119543c9f674 1073 * 8 MHz).
mbed_official 489:119543c9f674 1074 * @note (**) HSE_VALUE is a constant defined in stm32f1xx_hal_conf.h file (default value
mbed_official 489:119543c9f674 1075 * 8 MHz), user has to ensure that HSE_VALUE is same as the real
mbed_official 489:119543c9f674 1076 * frequency of the crystal used. Otherwise, this function may
mbed_official 489:119543c9f674 1077 * have wrong result.
mbed_official 489:119543c9f674 1078 *
mbed_official 489:119543c9f674 1079 * @note The result of this function could be not correct when using fractional
mbed_official 489:119543c9f674 1080 * value for HSE crystal.
mbed_official 489:119543c9f674 1081 *
mbed_official 489:119543c9f674 1082 * @note This function can be used by the user application to compute the
mbed_official 489:119543c9f674 1083 * baudrate for the communication peripherals or configure other parameters.
mbed_official 489:119543c9f674 1084 *
mbed_official 489:119543c9f674 1085 * @note Each time SYSCLK changes, this function must be called to update the
mbed_official 489:119543c9f674 1086 * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
mbed_official 489:119543c9f674 1087 *
mbed_official 489:119543c9f674 1088 *
mbed_official 489:119543c9f674 1089 * @retval SYSCLK frequency
mbed_official 489:119543c9f674 1090 */
mbed_official 489:119543c9f674 1091 uint32_t HAL_RCC_GetSysClockFreq(void)
mbed_official 489:119543c9f674 1092 {
mbed_official 489:119543c9f674 1093 const uint8_t aPLLMULFactorTable[16] = { 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16};
mbed_official 489:119543c9f674 1094 const uint8_t aPredivFactorTable[16] = { 1, 2, 3, 4, 5, 6, 7, 8, 9,10, 11, 12, 13, 14, 15, 16};
mbed_official 489:119543c9f674 1095 uint32_t tmp_reg = 0, prediv1 = 0, pllclk = 0, pllmul = 0;
mbed_official 489:119543c9f674 1096 uint32_t sysclockfreq = 0;
mbed_official 489:119543c9f674 1097
mbed_official 489:119543c9f674 1098 tmp_reg = RCC->CFGR;
mbed_official 489:119543c9f674 1099
mbed_official 489:119543c9f674 1100 /* Get SYSCLK source -------------------------------------------------------*/
mbed_official 489:119543c9f674 1101 switch (tmp_reg & RCC_CFGR_SWS)
mbed_official 489:119543c9f674 1102 {
mbed_official 489:119543c9f674 1103 case RCC_CFGR_SWS_HSE: /* HSE used as system clock */
mbed_official 489:119543c9f674 1104 {
mbed_official 489:119543c9f674 1105 sysclockfreq = HSE_VALUE;
mbed_official 489:119543c9f674 1106 break;
mbed_official 489:119543c9f674 1107 }
mbed_official 489:119543c9f674 1108 case RCC_CFGR_SWS_PLL: /* PLL used as system clock */
mbed_official 489:119543c9f674 1109 {
mbed_official 489:119543c9f674 1110 pllmul = aPLLMULFactorTable[(uint32_t)(tmp_reg & RCC_CFGR_PLLMULL) >> POSITION_VAL(RCC_CFGR_PLLMULL)];
mbed_official 489:119543c9f674 1111 if ((tmp_reg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2)
mbed_official 489:119543c9f674 1112 {
mbed_official 489:119543c9f674 1113 prediv1 = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> POSITION_VAL(RCC_CFGR2_PREDIV1)];
mbed_official 489:119543c9f674 1114 /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */
mbed_official 489:119543c9f674 1115 pllclk = (uint32_t)((HSE_VALUE / prediv1) * pllmul);
mbed_official 489:119543c9f674 1116 }
mbed_official 489:119543c9f674 1117 else
mbed_official 489:119543c9f674 1118 {
mbed_official 489:119543c9f674 1119 /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */
mbed_official 489:119543c9f674 1120 pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul);
mbed_official 489:119543c9f674 1121 }
mbed_official 489:119543c9f674 1122 sysclockfreq = pllclk;
mbed_official 489:119543c9f674 1123 break;
mbed_official 489:119543c9f674 1124 }
mbed_official 489:119543c9f674 1125 case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */
mbed_official 489:119543c9f674 1126 default: /* HSI used as system clock */
mbed_official 489:119543c9f674 1127 {
mbed_official 489:119543c9f674 1128 sysclockfreq = HSI_VALUE;
mbed_official 489:119543c9f674 1129 break;
mbed_official 489:119543c9f674 1130 }
mbed_official 489:119543c9f674 1131 }
mbed_official 489:119543c9f674 1132 return sysclockfreq;
mbed_official 489:119543c9f674 1133 }
mbed_official 489:119543c9f674 1134 /**
mbed_official 489:119543c9f674 1135 * @}
mbed_official 489:119543c9f674 1136 */
mbed_official 489:119543c9f674 1137
mbed_official 489:119543c9f674 1138 #endif /* STM32F100xB || STM32F100xE*/
mbed_official 489:119543c9f674 1139
mbed_official 489:119543c9f674 1140 #if defined(STM32F101x6) || defined(STM32F101xB) || defined(STM32F101xE) || defined(STM32F101xG) || \
mbed_official 489:119543c9f674 1141 defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || defined(STM32F103xB) || \
mbed_official 489:119543c9f674 1142 defined(STM32F103xE) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
mbed_official 489:119543c9f674 1143 /** @addtogroup RCC_Exported_Functions_Group2
mbed_official 489:119543c9f674 1144 * @{
mbed_official 489:119543c9f674 1145 */
mbed_official 489:119543c9f674 1146
mbed_official 489:119543c9f674 1147 /**
mbed_official 489:119543c9f674 1148 * @brief Configures the RCC_ClkInitStruct according to the internal
mbed_official 489:119543c9f674 1149 * RCC configuration registers.
mbed_official 489:119543c9f674 1150 * @param RCC_ClkInitStruct: pointer to an RCC_ClkInitTypeDef structure that
mbed_official 489:119543c9f674 1151 * will be configured.
mbed_official 489:119543c9f674 1152 * @param pFLatency: Pointer on the Flash Latency.
mbed_official 489:119543c9f674 1153 * @retval None
mbed_official 489:119543c9f674 1154 */
mbed_official 489:119543c9f674 1155 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)
mbed_official 489:119543c9f674 1156 {
mbed_official 489:119543c9f674 1157 /* Check the parameters */
mbed_official 489:119543c9f674 1158 assert_param(RCC_ClkInitStruct != NULL);
mbed_official 489:119543c9f674 1159 assert_param(pFLatency != NULL);
mbed_official 489:119543c9f674 1160
mbed_official 489:119543c9f674 1161 /* Set all possible values for the Clock type parameter --------------------*/
mbed_official 489:119543c9f674 1162 RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
mbed_official 489:119543c9f674 1163
mbed_official 489:119543c9f674 1164 /* Get the SYSCLK configuration --------------------------------------------*/
mbed_official 489:119543c9f674 1165 RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
mbed_official 489:119543c9f674 1166
mbed_official 489:119543c9f674 1167 /* Get the HCLK configuration ----------------------------------------------*/
mbed_official 489:119543c9f674 1168 RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE);
mbed_official 489:119543c9f674 1169
mbed_official 489:119543c9f674 1170 /* Get the APB1 configuration ----------------------------------------------*/
mbed_official 489:119543c9f674 1171 RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1);
mbed_official 489:119543c9f674 1172
mbed_official 489:119543c9f674 1173 /* Get the APB2 configuration ----------------------------------------------*/
mbed_official 489:119543c9f674 1174 RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3);
mbed_official 489:119543c9f674 1175
mbed_official 489:119543c9f674 1176 /* Get the Flash Wait State (Latency) configuration ------------------------*/
mbed_official 489:119543c9f674 1177 *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
mbed_official 489:119543c9f674 1178 }
mbed_official 489:119543c9f674 1179 /**
mbed_official 489:119543c9f674 1180 * @}
mbed_official 489:119543c9f674 1181 */
mbed_official 489:119543c9f674 1182
mbed_official 489:119543c9f674 1183 #endif /* STM32F101x6 || STM32F101xB || STM32F101xE || (...) || STM32F105xC || STM32F107xC */
mbed_official 489:119543c9f674 1184
mbed_official 489:119543c9f674 1185 /**
mbed_official 489:119543c9f674 1186 * @}
mbed_official 489:119543c9f674 1187 */
mbed_official 489:119543c9f674 1188
mbed_official 489:119543c9f674 1189 /**
mbed_official 489:119543c9f674 1190 * @}
mbed_official 489:119543c9f674 1191 */
mbed_official 489:119543c9f674 1192
mbed_official 489:119543c9f674 1193 /** @addtogroup RCCEx
mbed_official 489:119543c9f674 1194 * @{
mbed_official 489:119543c9f674 1195 */
mbed_official 489:119543c9f674 1196
mbed_official 489:119543c9f674 1197 /** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions
mbed_official 489:119543c9f674 1198 * @{
mbed_official 489:119543c9f674 1199 */
mbed_official 489:119543c9f674 1200
mbed_official 489:119543c9f674 1201 /** @defgroup RCCEx_Exported_Functions_Group1 Peripheral Control functions
mbed_official 489:119543c9f674 1202 * @brief Extended Peripheral Control functions
mbed_official 489:119543c9f674 1203 *
mbed_official 489:119543c9f674 1204 @verbatim
mbed_official 489:119543c9f674 1205 ===============================================================================
mbed_official 489:119543c9f674 1206 ##### Extended Peripheral Control functions #####
mbed_official 489:119543c9f674 1207 ===============================================================================
mbed_official 489:119543c9f674 1208 [..]
mbed_official 489:119543c9f674 1209 This subsection provides a set of functions allowing to control the RCC Clocks
mbed_official 489:119543c9f674 1210 frequencies.
mbed_official 489:119543c9f674 1211 [..]
mbed_official 489:119543c9f674 1212 (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
mbed_official 489:119543c9f674 1213 select the RTC clock source; in this case the Backup domain will be reset in
mbed_official 489:119543c9f674 1214 order to modify the RTC Clock source, as consequence RTC registers (including
mbed_official 489:119543c9f674 1215 the backup registers) and RCC_BDCR register are set to their reset values.
mbed_official 489:119543c9f674 1216
mbed_official 489:119543c9f674 1217 @endverbatim
mbed_official 489:119543c9f674 1218 * @{
mbed_official 489:119543c9f674 1219 */
mbed_official 489:119543c9f674 1220
mbed_official 489:119543c9f674 1221 /**
mbed_official 489:119543c9f674 1222 * @brief Initializes the RCC extended peripherals clocks according to the specified parameters in the
mbed_official 489:119543c9f674 1223 * RCC_PeriphCLKInitTypeDef.
mbed_official 489:119543c9f674 1224 * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
mbed_official 489:119543c9f674 1225 * contains the configuration information for the Extended Peripherals clocks(RTC clock).
mbed_official 489:119543c9f674 1226 *
mbed_official 489:119543c9f674 1227 * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
mbed_official 489:119543c9f674 1228 * the RTC clock source; in this case the Backup domain will be reset in
mbed_official 489:119543c9f674 1229 * order to modify the RTC Clock source, as consequence RTC registers (including
mbed_official 489:119543c9f674 1230 * the backup registers) are set to their reset values.
mbed_official 489:119543c9f674 1231 *
mbed_official 489:119543c9f674 1232 * @note In case of STM32F105xC or STM32F107xC devices, PLLI2S will be enabled if requested on
mbed_official 489:119543c9f674 1233 * one of 2 I2S interfaces. When PLLI2S is enabled, you need to call HAL_RCCEx_DisablePLLI2S to
mbed_official 489:119543c9f674 1234 * manually disable it.
mbed_official 489:119543c9f674 1235 *
mbed_official 489:119543c9f674 1236 * @retval HAL status
mbed_official 489:119543c9f674 1237 */
mbed_official 489:119543c9f674 1238 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
mbed_official 489:119543c9f674 1239 {
mbed_official 489:119543c9f674 1240 uint32_t tickstart = 0, tmp_reg = 0;
mbed_official 489:119543c9f674 1241 #if defined(STM32F105xC) || defined(STM32F107xC)
mbed_official 489:119543c9f674 1242 uint32_t pllactive = 0;
mbed_official 489:119543c9f674 1243 #endif /* STM32F105xC || STM32F107xC */
mbed_official 489:119543c9f674 1244
mbed_official 489:119543c9f674 1245 /* Check the parameters */
mbed_official 489:119543c9f674 1246 assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
mbed_official 489:119543c9f674 1247
mbed_official 489:119543c9f674 1248 /*------------------------------- RTC/LCD Configuration ------------------------*/
mbed_official 489:119543c9f674 1249 if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
mbed_official 489:119543c9f674 1250 {
mbed_official 489:119543c9f674 1251 /* Enable Power Controller clock */
mbed_official 489:119543c9f674 1252 __HAL_RCC_PWR_CLK_ENABLE();
mbed_official 489:119543c9f674 1253
mbed_official 489:119543c9f674 1254 /* Enable write access to Backup domain */
mbed_official 489:119543c9f674 1255 SET_BIT(PWR->CR, PWR_CR_DBP);
mbed_official 489:119543c9f674 1256
mbed_official 489:119543c9f674 1257 /* Wait for Backup domain Write protection disable */
mbed_official 489:119543c9f674 1258 tickstart = HAL_GetTick();
mbed_official 489:119543c9f674 1259
mbed_official 489:119543c9f674 1260 while((PWR->CR & PWR_CR_DBP) == RESET)
mbed_official 489:119543c9f674 1261 {
mbed_official 489:119543c9f674 1262 if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
mbed_official 489:119543c9f674 1263 {
mbed_official 489:119543c9f674 1264 return HAL_TIMEOUT;
mbed_official 489:119543c9f674 1265 }
mbed_official 489:119543c9f674 1266 }
mbed_official 489:119543c9f674 1267
mbed_official 489:119543c9f674 1268 tmp_reg = (RCC->BDCR & RCC_BDCR_RTCSEL);
mbed_official 489:119543c9f674 1269 /* Reset the Backup domain only if the RTC Clock source selection is modified */
mbed_official 489:119543c9f674 1270 if((tmp_reg != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
mbed_official 489:119543c9f674 1271 {
mbed_official 489:119543c9f674 1272 /* Store the content of BDCR register before the reset of Backup Domain */
mbed_official 489:119543c9f674 1273 tmp_reg = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
mbed_official 489:119543c9f674 1274 /* RTC Clock selection can be changed only if the Backup Domain is reset */
mbed_official 489:119543c9f674 1275 __HAL_RCC_BACKUPRESET_FORCE();
mbed_official 489:119543c9f674 1276 __HAL_RCC_BACKUPRESET_RELEASE();
mbed_official 489:119543c9f674 1277 /* Restore the Content of BDCR register */
mbed_official 489:119543c9f674 1278 RCC->BDCR = tmp_reg;
mbed_official 489:119543c9f674 1279 }
mbed_official 489:119543c9f674 1280
mbed_official 489:119543c9f674 1281 /* If LSE is selected as RTC clock source, wait for LSE reactivation */
mbed_official 489:119543c9f674 1282 if ((PeriphClkInit->RTCClockSelection == RCC_RTCCLKSOURCE_LSE))
mbed_official 489:119543c9f674 1283 {
mbed_official 489:119543c9f674 1284 /* Get timeout */
mbed_official 489:119543c9f674 1285 tickstart = HAL_GetTick();
mbed_official 489:119543c9f674 1286
mbed_official 489:119543c9f674 1287 /* Wait till LSE is ready */
mbed_official 489:119543c9f674 1288 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
mbed_official 489:119543c9f674 1289 {
mbed_official 489:119543c9f674 1290 if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
mbed_official 489:119543c9f674 1291 {
mbed_official 489:119543c9f674 1292 return HAL_TIMEOUT;
mbed_official 489:119543c9f674 1293 }
mbed_official 489:119543c9f674 1294 }
mbed_official 489:119543c9f674 1295 }
mbed_official 489:119543c9f674 1296
mbed_official 489:119543c9f674 1297 __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
mbed_official 489:119543c9f674 1298 }
mbed_official 489:119543c9f674 1299
mbed_official 489:119543c9f674 1300 /*------------------------------ ADC clock Configuration ------------------*/
mbed_official 489:119543c9f674 1301 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)
mbed_official 489:119543c9f674 1302 {
mbed_official 489:119543c9f674 1303 /* Check the parameters */
mbed_official 489:119543c9f674 1304 assert_param(IS_RCC_ADCPLLCLK_DIV(PeriphClkInit->AdcClockSelection));
mbed_official 489:119543c9f674 1305
mbed_official 489:119543c9f674 1306 /* Configure the ADC clock source */
mbed_official 489:119543c9f674 1307 __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection);
mbed_official 489:119543c9f674 1308 }
mbed_official 489:119543c9f674 1309
mbed_official 489:119543c9f674 1310 #if defined(STM32F105xC) || defined(STM32F107xC)
mbed_official 489:119543c9f674 1311 /*------------------------------ I2S2 Configuration ------------------------*/
mbed_official 489:119543c9f674 1312 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S2) == RCC_PERIPHCLK_I2S2)
mbed_official 489:119543c9f674 1313 {
mbed_official 489:119543c9f674 1314 /* Check the parameters */
mbed_official 489:119543c9f674 1315 assert_param(IS_RCC_I2S2CLKSOURCE(PeriphClkInit->I2s2ClockSelection));
mbed_official 489:119543c9f674 1316
mbed_official 489:119543c9f674 1317 /* Configure the I2S2 clock source */
mbed_official 489:119543c9f674 1318 __HAL_RCC_I2S2_CONFIG(PeriphClkInit->I2s2ClockSelection);
mbed_official 489:119543c9f674 1319 }
mbed_official 489:119543c9f674 1320
mbed_official 489:119543c9f674 1321 /*------------------------------ I2S3 Configuration ------------------------*/
mbed_official 489:119543c9f674 1322 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S3) == RCC_PERIPHCLK_I2S3)
mbed_official 489:119543c9f674 1323 {
mbed_official 489:119543c9f674 1324 /* Check the parameters */
mbed_official 489:119543c9f674 1325 assert_param(IS_RCC_I2S3CLKSOURCE(PeriphClkInit->I2s3ClockSelection));
mbed_official 489:119543c9f674 1326
mbed_official 489:119543c9f674 1327 /* Configure the I2S3 clock source */
mbed_official 489:119543c9f674 1328 __HAL_RCC_I2S3_CONFIG(PeriphClkInit->I2s3ClockSelection);
mbed_official 489:119543c9f674 1329 }
mbed_official 489:119543c9f674 1330
mbed_official 489:119543c9f674 1331 /*------------------------------ PLL I2S Configuration ----------------------*/
mbed_official 489:119543c9f674 1332 /* Check that PLLI2S need to be enabled */
mbed_official 489:119543c9f674 1333 if (HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_I2S2SRC) || HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_I2S3SRC))
mbed_official 489:119543c9f674 1334 {
mbed_official 489:119543c9f674 1335 /* Update flag to indicate that PLL I2S should be active */
mbed_official 489:119543c9f674 1336 pllactive = 1;
mbed_official 489:119543c9f674 1337 }
mbed_official 489:119543c9f674 1338
mbed_official 489:119543c9f674 1339 /* Check if PLL I2S need to be enabled */
mbed_official 489:119543c9f674 1340 if (pllactive == 1)
mbed_official 489:119543c9f674 1341 {
mbed_official 489:119543c9f674 1342 /* Enable PLL I2S only if not active */
mbed_official 489:119543c9f674 1343 if (HAL_IS_BIT_CLR(RCC->CR, RCC_CR_PLL3ON))
mbed_official 489:119543c9f674 1344 {
mbed_official 489:119543c9f674 1345 /* Check the parameters */
mbed_official 489:119543c9f674 1346 assert_param(IS_RCC_PLLI2S_MUL(PeriphClkInit->PLLI2S.PLLI2SMUL));
mbed_official 489:119543c9f674 1347 assert_param(IS_RCC_HSE_PREDIV2(PeriphClkInit->PLLI2S.HSEPrediv2Value));
mbed_official 489:119543c9f674 1348
mbed_official 489:119543c9f674 1349 /* Prediv2 can be written only when the PLL2 is disabled. */
mbed_official 489:119543c9f674 1350 /* Return an error only if new value is different from the programmed value */
mbed_official 489:119543c9f674 1351 if (HAL_IS_BIT_SET(RCC->CR,RCC_CR_PLL2ON) && \
mbed_official 489:119543c9f674 1352 (__HAL_RCC_HSE_GET_PREDIV2() != PeriphClkInit->PLLI2S.HSEPrediv2Value))
mbed_official 489:119543c9f674 1353 {
mbed_official 489:119543c9f674 1354 return HAL_ERROR;
mbed_official 489:119543c9f674 1355 }
mbed_official 489:119543c9f674 1356
mbed_official 489:119543c9f674 1357 /* Configure the HSE prediv2 factor --------------------------------*/
mbed_official 489:119543c9f674 1358 __HAL_RCC_HSE_PREDIV2_CONFIG(PeriphClkInit->PLLI2S.HSEPrediv2Value);
mbed_official 489:119543c9f674 1359
mbed_official 489:119543c9f674 1360 /* Configure the main PLLI2S multiplication factors. */
mbed_official 489:119543c9f674 1361 __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SMUL);
mbed_official 489:119543c9f674 1362
mbed_official 489:119543c9f674 1363 /* Enable the main PLLI2S. */
mbed_official 489:119543c9f674 1364 __HAL_RCC_PLLI2S_ENABLE();
mbed_official 489:119543c9f674 1365
mbed_official 489:119543c9f674 1366 /* Get Start Tick*/
mbed_official 489:119543c9f674 1367 tickstart = HAL_GetTick();
mbed_official 489:119543c9f674 1368
mbed_official 489:119543c9f674 1369 /* Wait till PLLI2S is ready */
mbed_official 489:119543c9f674 1370 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
mbed_official 489:119543c9f674 1371 {
mbed_official 489:119543c9f674 1372 if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
mbed_official 489:119543c9f674 1373 {
mbed_official 489:119543c9f674 1374 return HAL_TIMEOUT;
mbed_official 489:119543c9f674 1375 }
mbed_official 489:119543c9f674 1376 }
mbed_official 489:119543c9f674 1377 }
mbed_official 489:119543c9f674 1378 else
mbed_official 489:119543c9f674 1379 {
mbed_official 489:119543c9f674 1380 /* Return an error only if user wants to change the PLLI2SMUL whereas PLLI2S is active */
mbed_official 489:119543c9f674 1381 if (READ_BIT(RCC->CFGR2, RCC_CFGR2_PLL3MUL) != PeriphClkInit->PLLI2S.PLLI2SMUL)
mbed_official 489:119543c9f674 1382 {
mbed_official 489:119543c9f674 1383 return HAL_ERROR;
mbed_official 489:119543c9f674 1384 }
mbed_official 489:119543c9f674 1385 }
mbed_official 489:119543c9f674 1386 }
mbed_official 489:119543c9f674 1387 #endif /* STM32F105xC || STM32F107xC */
mbed_official 489:119543c9f674 1388
mbed_official 489:119543c9f674 1389 #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || \
mbed_official 489:119543c9f674 1390 defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
mbed_official 489:119543c9f674 1391 /*------------------------------ USB clock Configuration ------------------*/
mbed_official 489:119543c9f674 1392 if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == RCC_PERIPHCLK_USB)
mbed_official 489:119543c9f674 1393 {
mbed_official 489:119543c9f674 1394 /* Check the parameters */
mbed_official 489:119543c9f674 1395 assert_param(IS_RCC_USBPLLCLK_DIV(PeriphClkInit->UsbClockSelection));
mbed_official 489:119543c9f674 1396
mbed_official 489:119543c9f674 1397 /* Configure the USB clock source */
mbed_official 489:119543c9f674 1398 __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
mbed_official 489:119543c9f674 1399 }
mbed_official 489:119543c9f674 1400 #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
mbed_official 489:119543c9f674 1401
mbed_official 489:119543c9f674 1402 return HAL_OK;
mbed_official 489:119543c9f674 1403 }
mbed_official 489:119543c9f674 1404
mbed_official 489:119543c9f674 1405 /**
mbed_official 489:119543c9f674 1406 * @brief Get the PeriphClkInit according to the internal
mbed_official 489:119543c9f674 1407 * RCC configuration registers.
mbed_official 489:119543c9f674 1408 * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
mbed_official 489:119543c9f674 1409 * returns the configuration information for the Extended Peripherals clocks(RTC, I2S, ADC clocks).
mbed_official 489:119543c9f674 1410 * @retval None
mbed_official 489:119543c9f674 1411 */
mbed_official 489:119543c9f674 1412 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
mbed_official 489:119543c9f674 1413 {
mbed_official 489:119543c9f674 1414 uint32_t srcclk = 0;
mbed_official 489:119543c9f674 1415
mbed_official 489:119543c9f674 1416 /* Set all possible values for the extended clock type parameter------------*/
mbed_official 489:119543c9f674 1417 PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_RTC;
mbed_official 489:119543c9f674 1418
mbed_official 489:119543c9f674 1419 /* Get the RTC configuration -----------------------------------------------*/
mbed_official 489:119543c9f674 1420 srcclk = __HAL_RCC_GET_RTC_SOURCE();
mbed_official 489:119543c9f674 1421 /* Source clock is LSE or LSI*/
mbed_official 489:119543c9f674 1422 PeriphClkInit->RTCClockSelection = srcclk;
mbed_official 489:119543c9f674 1423
mbed_official 489:119543c9f674 1424 /* Get the ADC clock configuration -----------------------------------------*/
mbed_official 489:119543c9f674 1425 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_ADC;
mbed_official 489:119543c9f674 1426 PeriphClkInit->AdcClockSelection = __HAL_RCC_GET_ADC_SOURCE();
mbed_official 489:119543c9f674 1427
mbed_official 489:119543c9f674 1428 #if defined(STM32F105xC) || defined(STM32F107xC)
mbed_official 489:119543c9f674 1429 /* Get the I2S2 clock configuration -----------------------------------------*/
mbed_official 489:119543c9f674 1430 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S2;
mbed_official 489:119543c9f674 1431 PeriphClkInit->I2s2ClockSelection = __HAL_RCC_GET_I2S2_SOURCE();
mbed_official 489:119543c9f674 1432
mbed_official 489:119543c9f674 1433 /* Get the I2S3 clock configuration -----------------------------------------*/
mbed_official 489:119543c9f674 1434 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S3;
mbed_official 489:119543c9f674 1435 PeriphClkInit->I2s3ClockSelection = __HAL_RCC_GET_I2S3_SOURCE();
mbed_official 489:119543c9f674 1436
mbed_official 489:119543c9f674 1437 #endif /* STM32F105xC || STM32F107xC */
mbed_official 489:119543c9f674 1438
mbed_official 489:119543c9f674 1439 #if defined(STM32F103xE) || defined(STM32F103xG)
mbed_official 489:119543c9f674 1440 /* Get the I2S2 clock configuration -----------------------------------------*/
mbed_official 489:119543c9f674 1441 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S2;
mbed_official 489:119543c9f674 1442 PeriphClkInit->I2s2ClockSelection = RCC_I2S2CLKSOURCE_SYSCLK;
mbed_official 489:119543c9f674 1443
mbed_official 489:119543c9f674 1444 /* Get the I2S3 clock configuration -----------------------------------------*/
mbed_official 489:119543c9f674 1445 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2S3;
mbed_official 489:119543c9f674 1446 PeriphClkInit->I2s3ClockSelection = RCC_I2S3CLKSOURCE_SYSCLK;
mbed_official 489:119543c9f674 1447
mbed_official 489:119543c9f674 1448 #endif /* STM32F103xE || STM32F103xG */
mbed_official 489:119543c9f674 1449
mbed_official 489:119543c9f674 1450 #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || \
mbed_official 489:119543c9f674 1451 defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
mbed_official 489:119543c9f674 1452 /* Get the USB clock configuration -----------------------------------------*/
mbed_official 489:119543c9f674 1453 PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USB;
mbed_official 489:119543c9f674 1454 PeriphClkInit->UsbClockSelection = __HAL_RCC_GET_USB_SOURCE();
mbed_official 489:119543c9f674 1455 #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
mbed_official 489:119543c9f674 1456 }
mbed_official 489:119543c9f674 1457
mbed_official 489:119543c9f674 1458 /**
mbed_official 489:119543c9f674 1459 * @brief Returns the peripheral clock frequency
mbed_official 489:119543c9f674 1460 * @note Returns 0 if peripheral clock is unknown
mbed_official 489:119543c9f674 1461 * @param PeriphClk: Peripheral clock identifier
mbed_official 489:119543c9f674 1462 * This parameter can be one of the following values:
mbed_official 489:119543c9f674 1463 * @arg RCC_PERIPHCLK_RTC: RTC peripheral clock
mbed_official 489:119543c9f674 1464 * @arg RCC_PERIPHCLK_ADC: ADC peripheral clock
mbed_official 489:119543c9f674 1465 * @arg RCC_PERIPHCLK_I2S2: I2S2 peripheral clock (STM32F103xE, STM32F103xG, STM32F105xC & STM32F107xC)
mbed_official 489:119543c9f674 1466 * @arg RCC_PERIPHCLK_I2S3: I2S3 peripheral clock (STM32F103xE, STM32F103xG, STM32F105xC & STM32F107xC)
mbed_official 489:119543c9f674 1467 * @arg RCC_PERIPHCLK_USB: USB peripheral clock (STM32F102xx, STM32F103xx, STM32F105xC & STM32F107xC)
mbed_official 489:119543c9f674 1468 * @retval Frequency in Hz (0: means that no available frequency for the peripheral)
mbed_official 489:119543c9f674 1469 */
mbed_official 489:119543c9f674 1470 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
mbed_official 489:119543c9f674 1471 {
mbed_official 489:119543c9f674 1472 #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || \
mbed_official 489:119543c9f674 1473 defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
mbed_official 489:119543c9f674 1474 #if defined(STM32F105xC) || defined(STM32F107xC)
mbed_official 489:119543c9f674 1475 const uint8_t aPLLMULFactorTable[12] = {0, 0, 4, 5, 6, 7, 8, 9, 0, 0, 0, 13};
mbed_official 489:119543c9f674 1476 const uint8_t aPredivFactorTable[16] = { 1, 2, 3, 4, 5, 6, 7, 8, 9,10, 11, 12, 13, 14, 15, 16};
mbed_official 489:119543c9f674 1477 #else
mbed_official 489:119543c9f674 1478 const uint8_t aPLLMULFactorTable[16] = { 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 16};
mbed_official 489:119543c9f674 1479 const uint8_t aPredivFactorTable[2] = { 1, 2};
mbed_official 489:119543c9f674 1480 #endif
mbed_official 489:119543c9f674 1481 #endif
mbed_official 489:119543c9f674 1482 uint32_t tmp_reg = 0, frequency = 0;
mbed_official 489:119543c9f674 1483 #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || \
mbed_official 489:119543c9f674 1484 defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
mbed_official 489:119543c9f674 1485 uint32_t prediv1 = 0, pllclk = 0, pllmul = 0;
mbed_official 489:119543c9f674 1486 #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
mbed_official 489:119543c9f674 1487 #if defined(STM32F105xC) || defined(STM32F107xC)
mbed_official 489:119543c9f674 1488 uint32_t pll2mul = 0, pll3mul = 0, prediv2 = 0;
mbed_official 489:119543c9f674 1489 #endif /* STM32F105xC || STM32F107xC */
mbed_official 489:119543c9f674 1490
mbed_official 489:119543c9f674 1491 /* Check the parameters */
mbed_official 489:119543c9f674 1492 assert_param(IS_RCC_PERIPHCLOCK(PeriphClk));
mbed_official 489:119543c9f674 1493
mbed_official 489:119543c9f674 1494 switch (PeriphClk)
mbed_official 489:119543c9f674 1495 {
mbed_official 489:119543c9f674 1496 #if defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || \
mbed_official 489:119543c9f674 1497 defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC)
mbed_official 489:119543c9f674 1498 case RCC_PERIPHCLK_USB:
mbed_official 489:119543c9f674 1499 {
mbed_official 489:119543c9f674 1500 /* Get RCC configuration ------------------------------------------------------*/
mbed_official 489:119543c9f674 1501 tmp_reg = RCC->CFGR;
mbed_official 489:119543c9f674 1502
mbed_official 489:119543c9f674 1503 /* Check if PLL is enabled */
mbed_official 489:119543c9f674 1504 if (HAL_IS_BIT_SET(RCC->CR,RCC_CR_PLLON))
mbed_official 489:119543c9f674 1505 {
mbed_official 489:119543c9f674 1506 pllmul = aPLLMULFactorTable[(uint32_t)(tmp_reg & RCC_CFGR_PLLMULL) >> POSITION_VAL(RCC_CFGR_PLLMULL)];
mbed_official 489:119543c9f674 1507 if ((tmp_reg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2)
mbed_official 489:119543c9f674 1508 {
mbed_official 489:119543c9f674 1509 #if defined(STM32F105xC) || defined(STM32F107xC) || defined (STM32F100xB) || defined (STM32F100xE)
mbed_official 489:119543c9f674 1510 prediv1 = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> POSITION_VAL(RCC_CFGR2_PREDIV1)];
mbed_official 489:119543c9f674 1511 #else
mbed_official 489:119543c9f674 1512 prediv1 = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> POSITION_VAL(RCC_CFGR_PLLXTPRE)];
mbed_official 489:119543c9f674 1513 #endif /* STM32F105xC || STM32F107xC || STM32F100xB || STM32F100xE */
mbed_official 489:119543c9f674 1514
mbed_official 489:119543c9f674 1515 #if defined(STM32F105xC) || defined(STM32F107xC)
mbed_official 489:119543c9f674 1516 if(HAL_IS_BIT_SET(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC))
mbed_official 489:119543c9f674 1517 {
mbed_official 489:119543c9f674 1518 /* PLL2 selected as Prediv1 source */
mbed_official 489:119543c9f674 1519 /* PLLCLK = PLL2CLK / PREDIV1 * PLLMUL with PLL2CLK = HSE/PREDIV2 * PLL2MUL */
mbed_official 489:119543c9f674 1520 prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> POSITION_VAL(RCC_CFGR2_PREDIV2)) + 1;
mbed_official 489:119543c9f674 1521 pll2mul = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> POSITION_VAL(RCC_CFGR2_PLL2MUL)) + 2;
mbed_official 489:119543c9f674 1522 pllclk = (uint32_t)((((HSE_VALUE / prediv2) * pll2mul) / prediv1) * pllmul);
mbed_official 489:119543c9f674 1523 }
mbed_official 489:119543c9f674 1524 else
mbed_official 489:119543c9f674 1525 {
mbed_official 489:119543c9f674 1526 /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */
mbed_official 489:119543c9f674 1527 pllclk = (uint32_t)((HSE_VALUE / prediv1) * pllmul);
mbed_official 489:119543c9f674 1528 }
mbed_official 489:119543c9f674 1529
mbed_official 489:119543c9f674 1530 /* If PLLMUL was set to 13 means that it was to cover the case PLLMUL 6.5 (avoid using float) */
mbed_official 489:119543c9f674 1531 /* In this case need to divide pllclk by 2 */
mbed_official 489:119543c9f674 1532 if (pllmul == aPLLMULFactorTable[(uint32_t)(RCC_CFGR_PLLMULL6_5) >> POSITION_VAL(RCC_CFGR_PLLMULL)])
mbed_official 489:119543c9f674 1533 {
mbed_official 489:119543c9f674 1534 pllclk = pllclk / 2;
mbed_official 489:119543c9f674 1535 }
mbed_official 489:119543c9f674 1536 #else
mbed_official 489:119543c9f674 1537 if ((tmp_reg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2)
mbed_official 489:119543c9f674 1538 {
mbed_official 489:119543c9f674 1539 /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */
mbed_official 489:119543c9f674 1540 pllclk = (uint32_t)((HSE_VALUE / prediv1) * pllmul);
mbed_official 489:119543c9f674 1541 }
mbed_official 489:119543c9f674 1542 #endif /* STM32F105xC || STM32F107xC */
mbed_official 489:119543c9f674 1543 }
mbed_official 489:119543c9f674 1544 else
mbed_official 489:119543c9f674 1545 {
mbed_official 489:119543c9f674 1546 /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */
mbed_official 489:119543c9f674 1547 pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul);
mbed_official 489:119543c9f674 1548 }
mbed_official 489:119543c9f674 1549
mbed_official 489:119543c9f674 1550 /* Calcul of the USB frequency*/
mbed_official 489:119543c9f674 1551 #if defined(STM32F105xC) || defined(STM32F107xC)
mbed_official 489:119543c9f674 1552 /* USBCLK = PLLVCO = (2 x PLLCLK) / USB prescaler */
mbed_official 489:119543c9f674 1553 if (__HAL_RCC_GET_USB_SOURCE() == RCC_USBPLLCLK_DIV2)
mbed_official 489:119543c9f674 1554 {
mbed_official 489:119543c9f674 1555 /* Prescaler of 2 selected for USB */
mbed_official 489:119543c9f674 1556 frequency = pllclk;
mbed_official 489:119543c9f674 1557 }
mbed_official 489:119543c9f674 1558 else
mbed_official 489:119543c9f674 1559 {
mbed_official 489:119543c9f674 1560 /* Prescaler of 3 selected for USB */
mbed_official 489:119543c9f674 1561 frequency = (2 * pllclk) / 3;
mbed_official 489:119543c9f674 1562 }
mbed_official 489:119543c9f674 1563 #else
mbed_official 489:119543c9f674 1564 /* USBCLK = PLLCLK / USB prescaler */
mbed_official 489:119543c9f674 1565 if (__HAL_RCC_GET_USB_SOURCE() == RCC_USBPLLCLK_DIV1)
mbed_official 489:119543c9f674 1566 {
mbed_official 489:119543c9f674 1567 /* No prescaler selected for USB */
mbed_official 489:119543c9f674 1568 frequency = pllclk;
mbed_official 489:119543c9f674 1569 }
mbed_official 489:119543c9f674 1570 else
mbed_official 489:119543c9f674 1571 {
mbed_official 489:119543c9f674 1572 /* Prescaler of 1.5 selected for USB */
mbed_official 489:119543c9f674 1573 frequency = (pllclk * 2) / 3;
mbed_official 489:119543c9f674 1574 }
mbed_official 489:119543c9f674 1575 #endif
mbed_official 489:119543c9f674 1576 }
mbed_official 489:119543c9f674 1577 break;
mbed_official 489:119543c9f674 1578 }
mbed_official 489:119543c9f674 1579 #endif /* STM32F102x6 || STM32F102xB || STM32F103x6 || STM32F103xB || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
mbed_official 489:119543c9f674 1580 #if defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F105xC) || defined (STM32F107xC)
mbed_official 489:119543c9f674 1581 case RCC_PERIPHCLK_I2S2:
mbed_official 489:119543c9f674 1582 {
mbed_official 489:119543c9f674 1583 #if defined (STM32F103xE) || defined (STM32F103xG)
mbed_official 489:119543c9f674 1584 /* SYSCLK used as source clock for I2S2 */
mbed_official 489:119543c9f674 1585 frequency = HAL_RCC_GetSysClockFreq();
mbed_official 489:119543c9f674 1586 #else
mbed_official 489:119543c9f674 1587 if (__HAL_RCC_GET_I2S2_SOURCE() == RCC_I2S2CLKSOURCE_SYSCLK)
mbed_official 489:119543c9f674 1588 {
mbed_official 489:119543c9f674 1589 /* SYSCLK used as source clock for I2S2 */
mbed_official 489:119543c9f674 1590 frequency = HAL_RCC_GetSysClockFreq();
mbed_official 489:119543c9f674 1591 }
mbed_official 489:119543c9f674 1592 else
mbed_official 489:119543c9f674 1593 {
mbed_official 489:119543c9f674 1594 /* Check if PLLI2S is enabled */
mbed_official 489:119543c9f674 1595 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON))
mbed_official 489:119543c9f674 1596 {
mbed_official 489:119543c9f674 1597 /* PLLI2SVCO = 2 * PLLI2SCLK = 2 * (HSE/PREDIV2 * PLL3MUL) */
mbed_official 489:119543c9f674 1598 prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> POSITION_VAL(RCC_CFGR2_PREDIV2)) + 1;
mbed_official 489:119543c9f674 1599 pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> POSITION_VAL(RCC_CFGR2_PLL3MUL)) + 2;
mbed_official 489:119543c9f674 1600 frequency = (uint32_t)(2 * ((HSE_VALUE / prediv2) * pll3mul));
mbed_official 489:119543c9f674 1601 }
mbed_official 489:119543c9f674 1602 }
mbed_official 489:119543c9f674 1603 #endif /* STM32F103xE || STM32F103xG */
mbed_official 489:119543c9f674 1604 break;
mbed_official 489:119543c9f674 1605 }
mbed_official 489:119543c9f674 1606 case RCC_PERIPHCLK_I2S3:
mbed_official 489:119543c9f674 1607 {
mbed_official 489:119543c9f674 1608 #if defined (STM32F103xE) || defined (STM32F103xG)
mbed_official 489:119543c9f674 1609 /* SYSCLK used as source clock for I2S3 */
mbed_official 489:119543c9f674 1610 frequency = HAL_RCC_GetSysClockFreq();
mbed_official 489:119543c9f674 1611 #else
mbed_official 489:119543c9f674 1612 if (__HAL_RCC_GET_I2S3_SOURCE() == RCC_I2S3CLKSOURCE_SYSCLK)
mbed_official 489:119543c9f674 1613 {
mbed_official 489:119543c9f674 1614 /* SYSCLK used as source clock for I2S3 */
mbed_official 489:119543c9f674 1615 frequency = HAL_RCC_GetSysClockFreq();
mbed_official 489:119543c9f674 1616 }
mbed_official 489:119543c9f674 1617 else
mbed_official 489:119543c9f674 1618 {
mbed_official 489:119543c9f674 1619 /* Check if PLLI2S is enabled */
mbed_official 489:119543c9f674 1620 if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_PLL3ON))
mbed_official 489:119543c9f674 1621 {
mbed_official 489:119543c9f674 1622 /* PLLI2SVCO = 2 * PLLI2SCLK = 2 * (HSE/PREDIV2 * PLL3MUL) */
mbed_official 489:119543c9f674 1623 prediv2 = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> POSITION_VAL(RCC_CFGR2_PREDIV2)) + 1;
mbed_official 489:119543c9f674 1624 pll3mul = ((RCC->CFGR2 & RCC_CFGR2_PLL3MUL) >> POSITION_VAL(RCC_CFGR2_PLL3MUL)) + 2;
mbed_official 489:119543c9f674 1625 frequency = (uint32_t)(2 * ((HSE_VALUE / prediv2) * pll3mul));
mbed_official 489:119543c9f674 1626 }
mbed_official 489:119543c9f674 1627 }
mbed_official 489:119543c9f674 1628 #endif /* STM32F103xE || STM32F103xG */
mbed_official 489:119543c9f674 1629 break;
mbed_official 489:119543c9f674 1630 }
mbed_official 489:119543c9f674 1631 #endif /* STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
mbed_official 489:119543c9f674 1632 case RCC_PERIPHCLK_RTC:
mbed_official 489:119543c9f674 1633 {
mbed_official 489:119543c9f674 1634 /* Get RCC BDCR configuration ------------------------------------------------------*/
mbed_official 489:119543c9f674 1635 tmp_reg = RCC->BDCR;
mbed_official 489:119543c9f674 1636
mbed_official 489:119543c9f674 1637 /* Check if LSE is ready if RTC clock selection is LSE */
mbed_official 489:119543c9f674 1638 if (((tmp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_LSE) && (HAL_IS_BIT_SET(tmp_reg, RCC_BDCR_LSERDY)))
mbed_official 489:119543c9f674 1639 {
mbed_official 489:119543c9f674 1640 frequency = LSE_VALUE;
mbed_official 489:119543c9f674 1641 }
mbed_official 489:119543c9f674 1642 /* Check if LSI is ready if RTC clock selection is LSI */
mbed_official 489:119543c9f674 1643 else if (((tmp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_LSI) && (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY)))
mbed_official 489:119543c9f674 1644 {
mbed_official 489:119543c9f674 1645 frequency = LSI_VALUE;
mbed_official 489:119543c9f674 1646 }
mbed_official 489:119543c9f674 1647 else if (((tmp_reg & RCC_BDCR_RTCSEL) == RCC_RTCCLKSOURCE_HSE_DIV128) && (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)))
mbed_official 489:119543c9f674 1648 {
mbed_official 489:119543c9f674 1649 frequency = HSE_VALUE / 128;
mbed_official 489:119543c9f674 1650 }
mbed_official 489:119543c9f674 1651 /* Clock not enabled for RTC*/
mbed_official 489:119543c9f674 1652 else
mbed_official 489:119543c9f674 1653 {
mbed_official 489:119543c9f674 1654 frequency = 0;
mbed_official 489:119543c9f674 1655 }
mbed_official 489:119543c9f674 1656 break;
mbed_official 489:119543c9f674 1657 }
mbed_official 489:119543c9f674 1658 case RCC_PERIPHCLK_ADC:
mbed_official 489:119543c9f674 1659 {
mbed_official 489:119543c9f674 1660 frequency = HAL_RCC_GetPCLK2Freq() / (((__HAL_RCC_GET_ADC_SOURCE() >> POSITION_VAL(RCC_CFGR_ADCPRE_DIV4)) + 1) * 2);
mbed_official 489:119543c9f674 1661 break;
mbed_official 489:119543c9f674 1662 }
mbed_official 489:119543c9f674 1663 default:
mbed_official 489:119543c9f674 1664 {
mbed_official 489:119543c9f674 1665 break;
mbed_official 489:119543c9f674 1666 }
mbed_official 489:119543c9f674 1667 }
mbed_official 489:119543c9f674 1668 return(frequency);
mbed_official 489:119543c9f674 1669 }
mbed_official 489:119543c9f674 1670
mbed_official 489:119543c9f674 1671 /**
mbed_official 489:119543c9f674 1672 * @}
mbed_official 489:119543c9f674 1673 */
mbed_official 489:119543c9f674 1674
mbed_official 489:119543c9f674 1675 #if defined(STM32F105xC) || defined(STM32F107xC)
mbed_official 489:119543c9f674 1676 /** @defgroup RCCEx_Exported_Functions_Group2 PLLI2S Management function
mbed_official 489:119543c9f674 1677 * @brief PLLI2S Management functions
mbed_official 489:119543c9f674 1678 *
mbed_official 489:119543c9f674 1679 @verbatim
mbed_official 489:119543c9f674 1680 ===============================================================================
mbed_official 489:119543c9f674 1681 ##### Extended PLLI2S Management functions #####
mbed_official 489:119543c9f674 1682 ===============================================================================
mbed_official 489:119543c9f674 1683 [..]
mbed_official 489:119543c9f674 1684 This subsection provides a set of functions allowing to control the PLLI2S
mbed_official 489:119543c9f674 1685 activation or deactivation
mbed_official 489:119543c9f674 1686 @endverbatim
mbed_official 489:119543c9f674 1687 * @{
mbed_official 489:119543c9f674 1688 */
mbed_official 489:119543c9f674 1689
mbed_official 489:119543c9f674 1690 /**
mbed_official 489:119543c9f674 1691 * @brief Enable PLLI2S
mbed_official 489:119543c9f674 1692 * @param PLLI2SInit: pointer to an RCC_PLLI2SInitTypeDef structure that
mbed_official 489:119543c9f674 1693 * contains the configuration information for the PLLI2S
mbed_official 489:119543c9f674 1694 * @note The PLLI2S configuration not modified if used by I2S2 or I2S3 Interface.
mbed_official 489:119543c9f674 1695 * @retval HAL status
mbed_official 489:119543c9f674 1696 */
mbed_official 489:119543c9f674 1697 HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit)
mbed_official 489:119543c9f674 1698 {
mbed_official 489:119543c9f674 1699 uint32_t tickstart = 0;
mbed_official 489:119543c9f674 1700
mbed_official 489:119543c9f674 1701 /* Check that PLL I2S has not been already enabled by I2S2 or I2S3*/
mbed_official 489:119543c9f674 1702 if (HAL_IS_BIT_CLR(RCC->CFGR2, RCC_CFGR2_I2S2SRC) && HAL_IS_BIT_CLR(RCC->CFGR2, RCC_CFGR2_I2S3SRC))
mbed_official 489:119543c9f674 1703 {
mbed_official 489:119543c9f674 1704 /* Check the parameters */
mbed_official 489:119543c9f674 1705 assert_param(IS_RCC_PLLI2S_MUL(PLLI2SInit->PLLI2SMUL));
mbed_official 489:119543c9f674 1706 assert_param(IS_RCC_HSE_PREDIV2(PLLI2SInit->HSEPrediv2Value));
mbed_official 489:119543c9f674 1707
mbed_official 489:119543c9f674 1708 /* Prediv2 can be written only when the PLL2 is disabled. */
mbed_official 489:119543c9f674 1709 /* Return an error only if new value is different from the programmed value */
mbed_official 489:119543c9f674 1710 if (HAL_IS_BIT_SET(RCC->CR,RCC_CR_PLL2ON) && \
mbed_official 489:119543c9f674 1711 (__HAL_RCC_HSE_GET_PREDIV2() != PLLI2SInit->HSEPrediv2Value))
mbed_official 489:119543c9f674 1712 {
mbed_official 489:119543c9f674 1713 return HAL_ERROR;
mbed_official 489:119543c9f674 1714 }
mbed_official 489:119543c9f674 1715
mbed_official 489:119543c9f674 1716 /* Disable the main PLLI2S. */
mbed_official 489:119543c9f674 1717 __HAL_RCC_PLLI2S_DISABLE();
mbed_official 489:119543c9f674 1718
mbed_official 489:119543c9f674 1719 /* Get Start Tick*/
mbed_official 489:119543c9f674 1720 tickstart = HAL_GetTick();
mbed_official 489:119543c9f674 1721
mbed_official 489:119543c9f674 1722 /* Wait till PLLI2S is ready */
mbed_official 489:119543c9f674 1723 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
mbed_official 489:119543c9f674 1724 {
mbed_official 489:119543c9f674 1725 if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
mbed_official 489:119543c9f674 1726 {
mbed_official 489:119543c9f674 1727 return HAL_TIMEOUT;
mbed_official 489:119543c9f674 1728 }
mbed_official 489:119543c9f674 1729 }
mbed_official 489:119543c9f674 1730
mbed_official 489:119543c9f674 1731 /* Configure the HSE prediv2 factor --------------------------------*/
mbed_official 489:119543c9f674 1732 __HAL_RCC_HSE_PREDIV2_CONFIG(PLLI2SInit->HSEPrediv2Value);
mbed_official 489:119543c9f674 1733
mbed_official 489:119543c9f674 1734
mbed_official 489:119543c9f674 1735 /* Configure the main PLLI2S multiplication factors. */
mbed_official 489:119543c9f674 1736 __HAL_RCC_PLLI2S_CONFIG(PLLI2SInit->PLLI2SMUL);
mbed_official 489:119543c9f674 1737
mbed_official 489:119543c9f674 1738 /* Enable the main PLLI2S. */
mbed_official 489:119543c9f674 1739 __HAL_RCC_PLLI2S_ENABLE();
mbed_official 489:119543c9f674 1740
mbed_official 489:119543c9f674 1741 /* Get Start Tick*/
mbed_official 489:119543c9f674 1742 tickstart = HAL_GetTick();
mbed_official 489:119543c9f674 1743
mbed_official 489:119543c9f674 1744 /* Wait till PLLI2S is ready */
mbed_official 489:119543c9f674 1745 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
mbed_official 489:119543c9f674 1746 {
mbed_official 489:119543c9f674 1747 if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
mbed_official 489:119543c9f674 1748 {
mbed_official 489:119543c9f674 1749 return HAL_TIMEOUT;
mbed_official 489:119543c9f674 1750 }
mbed_official 489:119543c9f674 1751 }
mbed_official 489:119543c9f674 1752 }
mbed_official 489:119543c9f674 1753 else
mbed_official 489:119543c9f674 1754 {
mbed_official 489:119543c9f674 1755 /* PLLI2S cannot be modified as already used by I2S2 or I2S3 */
mbed_official 489:119543c9f674 1756 return HAL_ERROR;
mbed_official 489:119543c9f674 1757 }
mbed_official 489:119543c9f674 1758
mbed_official 489:119543c9f674 1759 return HAL_OK;
mbed_official 489:119543c9f674 1760 }
mbed_official 489:119543c9f674 1761
mbed_official 489:119543c9f674 1762 /**
mbed_official 489:119543c9f674 1763 * @brief Disable PLLI2S
mbed_official 489:119543c9f674 1764 * @note PLLI2S is not disabled if used by I2S2 or I2S3 Interface.
mbed_official 489:119543c9f674 1765 * @retval HAL status
mbed_official 489:119543c9f674 1766 */
mbed_official 489:119543c9f674 1767 HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void)
mbed_official 489:119543c9f674 1768 {
mbed_official 489:119543c9f674 1769 uint32_t tickstart = 0;
mbed_official 489:119543c9f674 1770
mbed_official 489:119543c9f674 1771 /* Disable PLL I2S as not requested by I2S2 or I2S3*/
mbed_official 489:119543c9f674 1772 if (HAL_IS_BIT_CLR(RCC->CFGR2, RCC_CFGR2_I2S2SRC) && HAL_IS_BIT_CLR(RCC->CFGR2, RCC_CFGR2_I2S3SRC))
mbed_official 489:119543c9f674 1773 {
mbed_official 489:119543c9f674 1774 /* Disable the main PLLI2S. */
mbed_official 489:119543c9f674 1775 __HAL_RCC_PLLI2S_DISABLE();
mbed_official 489:119543c9f674 1776
mbed_official 489:119543c9f674 1777 /* Get Start Tick*/
mbed_official 489:119543c9f674 1778 tickstart = HAL_GetTick();
mbed_official 489:119543c9f674 1779
mbed_official 489:119543c9f674 1780 /* Wait till PLLI2S is ready */
mbed_official 489:119543c9f674 1781 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
mbed_official 489:119543c9f674 1782 {
mbed_official 489:119543c9f674 1783 if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
mbed_official 489:119543c9f674 1784 {
mbed_official 489:119543c9f674 1785 return HAL_TIMEOUT;
mbed_official 489:119543c9f674 1786 }
mbed_official 489:119543c9f674 1787 }
mbed_official 489:119543c9f674 1788 }
mbed_official 489:119543c9f674 1789 else
mbed_official 489:119543c9f674 1790 {
mbed_official 489:119543c9f674 1791 /* PLLI2S is currently used by I2S2 or I2S3. Cannot be disabled.*/
mbed_official 489:119543c9f674 1792 return HAL_ERROR;
mbed_official 489:119543c9f674 1793 }
mbed_official 489:119543c9f674 1794
mbed_official 489:119543c9f674 1795 return HAL_OK;
mbed_official 489:119543c9f674 1796 }
mbed_official 489:119543c9f674 1797
mbed_official 489:119543c9f674 1798 /**
mbed_official 489:119543c9f674 1799 * @}
mbed_official 489:119543c9f674 1800 */
mbed_official 489:119543c9f674 1801
mbed_official 489:119543c9f674 1802 /** @defgroup RCCEx_Exported_Functions_Group3 PLL2 Management function
mbed_official 489:119543c9f674 1803 * @brief PLL2 Management functions
mbed_official 489:119543c9f674 1804 *
mbed_official 489:119543c9f674 1805 @verbatim
mbed_official 489:119543c9f674 1806 ===============================================================================
mbed_official 489:119543c9f674 1807 ##### Extended PLL2 Management functions #####
mbed_official 489:119543c9f674 1808 ===============================================================================
mbed_official 489:119543c9f674 1809 [..]
mbed_official 489:119543c9f674 1810 This subsection provides a set of functions allowing to control the PLL2
mbed_official 489:119543c9f674 1811 activation or deactivation
mbed_official 489:119543c9f674 1812 @endverbatim
mbed_official 489:119543c9f674 1813 * @{
mbed_official 489:119543c9f674 1814 */
mbed_official 489:119543c9f674 1815
mbed_official 489:119543c9f674 1816 /**
mbed_official 489:119543c9f674 1817 * @brief Enable PLL2
mbed_official 489:119543c9f674 1818 * @param PLL2Init: pointer to an RCC_PLL2InitTypeDef structure that
mbed_official 489:119543c9f674 1819 * contains the configuration information for the PLL2
mbed_official 489:119543c9f674 1820 * @note The PLL2 configuration not modified if used indirectly as system clock.
mbed_official 489:119543c9f674 1821 * @retval HAL status
mbed_official 489:119543c9f674 1822 */
mbed_official 489:119543c9f674 1823 HAL_StatusTypeDef HAL_RCCEx_EnablePLL2(RCC_PLL2InitTypeDef *PLL2Init)
mbed_official 489:119543c9f674 1824 {
mbed_official 489:119543c9f674 1825 uint32_t tickstart = 0;
mbed_official 489:119543c9f674 1826
mbed_official 489:119543c9f674 1827 /* This bit can not be cleared if the PLL2 clock is used indirectly as system
mbed_official 489:119543c9f674 1828 clock (i.e. it is used as PLL clock entry that is used as system clock). */
mbed_official 489:119543c9f674 1829 if((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && \
mbed_official 489:119543c9f674 1830 (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && \
mbed_official 489:119543c9f674 1831 ((READ_BIT(RCC->CFGR2,RCC_CFGR2_PREDIV1SRC)) == RCC_CFGR2_PREDIV1SRC_PLL2))
mbed_official 489:119543c9f674 1832 {
mbed_official 489:119543c9f674 1833 return HAL_ERROR;
mbed_official 489:119543c9f674 1834 }
mbed_official 489:119543c9f674 1835 else
mbed_official 489:119543c9f674 1836 {
mbed_official 489:119543c9f674 1837 /* Check the parameters */
mbed_official 489:119543c9f674 1838 assert_param(IS_RCC_PLL2_MUL(PLL2Init->PLL2MUL));
mbed_official 489:119543c9f674 1839 assert_param(IS_RCC_HSE_PREDIV2(PLL2Init->HSEPrediv2Value));
mbed_official 489:119543c9f674 1840
mbed_official 489:119543c9f674 1841 /* Prediv2 can be written only when the PLLI2S is disabled. */
mbed_official 489:119543c9f674 1842 /* Return an error only if new value is different from the programmed value */
mbed_official 489:119543c9f674 1843 if (HAL_IS_BIT_SET(RCC->CR,RCC_CR_PLL3ON) && \
mbed_official 489:119543c9f674 1844 (__HAL_RCC_HSE_GET_PREDIV2() != PLL2Init->HSEPrediv2Value))
mbed_official 489:119543c9f674 1845 {
mbed_official 489:119543c9f674 1846 return HAL_ERROR;
mbed_official 489:119543c9f674 1847 }
mbed_official 489:119543c9f674 1848
mbed_official 489:119543c9f674 1849 /* Disable the main PLL2. */
mbed_official 489:119543c9f674 1850 __HAL_RCC_PLL2_DISABLE();
mbed_official 489:119543c9f674 1851
mbed_official 489:119543c9f674 1852 /* Get Start Tick*/
mbed_official 489:119543c9f674 1853 tickstart = HAL_GetTick();
mbed_official 489:119543c9f674 1854
mbed_official 489:119543c9f674 1855 /* Wait till PLL2 is disabled */
mbed_official 489:119543c9f674 1856 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET)
mbed_official 489:119543c9f674 1857 {
mbed_official 489:119543c9f674 1858 if((HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE)
mbed_official 489:119543c9f674 1859 {
mbed_official 489:119543c9f674 1860 return HAL_TIMEOUT;
mbed_official 489:119543c9f674 1861 }
mbed_official 489:119543c9f674 1862 }
mbed_official 489:119543c9f674 1863
mbed_official 489:119543c9f674 1864 /* Configure the HSE prediv2 factor --------------------------------*/
mbed_official 489:119543c9f674 1865 __HAL_RCC_HSE_PREDIV2_CONFIG(PLL2Init->HSEPrediv2Value);
mbed_official 489:119543c9f674 1866
mbed_official 489:119543c9f674 1867 /* Configure the main PLL2 multiplication factors. */
mbed_official 489:119543c9f674 1868 __HAL_RCC_PLL2_CONFIG(PLL2Init->PLL2MUL);
mbed_official 489:119543c9f674 1869
mbed_official 489:119543c9f674 1870 /* Enable the main PLL2. */
mbed_official 489:119543c9f674 1871 __HAL_RCC_PLL2_ENABLE();
mbed_official 489:119543c9f674 1872
mbed_official 489:119543c9f674 1873 /* Get Start Tick*/
mbed_official 489:119543c9f674 1874 tickstart = HAL_GetTick();
mbed_official 489:119543c9f674 1875
mbed_official 489:119543c9f674 1876 /* Wait till PLL2 is ready */
mbed_official 489:119543c9f674 1877 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == RESET)
mbed_official 489:119543c9f674 1878 {
mbed_official 489:119543c9f674 1879 if((HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE)
mbed_official 489:119543c9f674 1880 {
mbed_official 489:119543c9f674 1881 return HAL_TIMEOUT;
mbed_official 489:119543c9f674 1882 }
mbed_official 489:119543c9f674 1883 }
mbed_official 489:119543c9f674 1884 }
mbed_official 489:119543c9f674 1885
mbed_official 489:119543c9f674 1886 return HAL_OK;
mbed_official 489:119543c9f674 1887 }
mbed_official 489:119543c9f674 1888
mbed_official 489:119543c9f674 1889 /**
mbed_official 489:119543c9f674 1890 * @brief Disable PLL2
mbed_official 489:119543c9f674 1891 * @note PLL2 is not disabled if used indirectly as system clock.
mbed_official 489:119543c9f674 1892 * @retval HAL status
mbed_official 489:119543c9f674 1893 */
mbed_official 489:119543c9f674 1894 HAL_StatusTypeDef HAL_RCCEx_DisablePLL2(void)
mbed_official 489:119543c9f674 1895 {
mbed_official 489:119543c9f674 1896 uint32_t tickstart = 0;
mbed_official 489:119543c9f674 1897
mbed_official 489:119543c9f674 1898 /* This bit can not be cleared if the PLL2 clock is used indirectly as system
mbed_official 489:119543c9f674 1899 clock (i.e. it is used as PLL clock entry that is used as system clock). */
mbed_official 489:119543c9f674 1900 if((__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) && \
mbed_official 489:119543c9f674 1901 (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && \
mbed_official 489:119543c9f674 1902 ((READ_BIT(RCC->CFGR2,RCC_CFGR2_PREDIV1SRC)) == RCC_CFGR2_PREDIV1SRC_PLL2))
mbed_official 489:119543c9f674 1903 {
mbed_official 489:119543c9f674 1904 return HAL_ERROR;
mbed_official 489:119543c9f674 1905 }
mbed_official 489:119543c9f674 1906 else
mbed_official 489:119543c9f674 1907 {
mbed_official 489:119543c9f674 1908 /* Disable the main PLL2. */
mbed_official 489:119543c9f674 1909 __HAL_RCC_PLL2_DISABLE();
mbed_official 489:119543c9f674 1910
mbed_official 489:119543c9f674 1911 /* Get Start Tick*/
mbed_official 489:119543c9f674 1912 tickstart = HAL_GetTick();
mbed_official 489:119543c9f674 1913
mbed_official 489:119543c9f674 1914 /* Wait till PLL2 is disabled */
mbed_official 489:119543c9f674 1915 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != RESET)
mbed_official 489:119543c9f674 1916 {
mbed_official 489:119543c9f674 1917 if((HAL_GetTick() - tickstart ) > PLL2_TIMEOUT_VALUE)
mbed_official 489:119543c9f674 1918 {
mbed_official 489:119543c9f674 1919 return HAL_TIMEOUT;
mbed_official 489:119543c9f674 1920 }
mbed_official 489:119543c9f674 1921 }
mbed_official 489:119543c9f674 1922 }
mbed_official 489:119543c9f674 1923
mbed_official 489:119543c9f674 1924 return HAL_OK;
mbed_official 489:119543c9f674 1925 }
mbed_official 489:119543c9f674 1926
mbed_official 489:119543c9f674 1927 /**
mbed_official 489:119543c9f674 1928 * @}
mbed_official 489:119543c9f674 1929 */
mbed_official 489:119543c9f674 1930 #endif /* STM32F105xC || STM32F107xC */
mbed_official 489:119543c9f674 1931
mbed_official 489:119543c9f674 1932 /**
mbed_official 489:119543c9f674 1933 * @}
mbed_official 489:119543c9f674 1934 */
mbed_official 489:119543c9f674 1935
mbed_official 489:119543c9f674 1936 /**
mbed_official 489:119543c9f674 1937 * @}
mbed_official 489:119543c9f674 1938 */
mbed_official 489:119543c9f674 1939
mbed_official 489:119543c9f674 1940 #endif /* HAL_RCC_MODULE_ENABLED */
mbed_official 489:119543c9f674 1941 /**
mbed_official 489:119543c9f674 1942 * @}
mbed_official 489:119543c9f674 1943 */
mbed_official 489:119543c9f674 1944
mbed_official 489:119543c9f674 1945 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
mbed_official 489:119543c9f674 1946