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Last commit 20 Feb 2019 by mbed official

targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_eth.c@581:39197bcd20f2, 2015-07-02 (annotated)

Committer:
mbed_official
Date:
Thu Jul 02 16:30:08 2015 +0100
Revision:
581:39197bcd20f2
Parent:
489:119543c9f674 
Synchronized with git revision ae2d3cdffe70184eb8736d94f76c45c93f4b7724



Full URL: https://github.com/mbedmicro/mbed/commit/ae2d3cdffe70184eb8736d94f76c45c93f4b7724/



Make it possible to build the core mbed library with yotta

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 489:119543c9f674 1 /**
mbed_official 489:119543c9f674 2 ******************************************************************************
mbed_official 489:119543c9f674 3 * @file stm32f1xx_hal_eth.c
mbed_official 489:119543c9f674 4 * @author MCD Application Team
mbed_official 489:119543c9f674 5 * @version V1.0.0
mbed_official 489:119543c9f674 6 * @date 15-December-2014
mbed_official 489:119543c9f674 7 * @brief ETH HAL module driver.
mbed_official 489:119543c9f674 8 * This file provides firmware functions to manage the following
mbed_official 489:119543c9f674 9 * functionalities of the Ethernet (ETH) peripheral:
mbed_official 489:119543c9f674 10 * + Initialization and de-initialization functions
mbed_official 489:119543c9f674 11 * + IO operation functions
mbed_official 489:119543c9f674 12 * + Peripheral Control functions
mbed_official 489:119543c9f674 13 * + Peripheral State and Errors functions
mbed_official 489:119543c9f674 14 *
mbed_official 489:119543c9f674 15 @verbatim
mbed_official 489:119543c9f674 16 ==============================================================================
mbed_official 489:119543c9f674 17 ##### How to use this driver #####
mbed_official 489:119543c9f674 18 ==============================================================================
mbed_official 489:119543c9f674 19 [..]
mbed_official 489:119543c9f674 20 (#)Declare a ETH_HandleTypeDef handle structure, for example:
mbed_official 489:119543c9f674 21 ETH_HandleTypeDef heth;
mbed_official 489:119543c9f674 22
mbed_official 489:119543c9f674 23 (#)Fill parameters of Init structure in heth handle
mbed_official 489:119543c9f674 24
mbed_official 489:119543c9f674 25 (#)Call HAL_ETH_Init() API to initialize the Ethernet peripheral (MAC, DMA, ...)
mbed_official 489:119543c9f674 26
mbed_official 489:119543c9f674 27 (#)Initialize the ETH low level resources through the HAL_ETH_MspInit() API:
mbed_official 489:119543c9f674 28 (##) Enable the Ethernet interface clock using
mbed_official 489:119543c9f674 29 (+++) __HAL_RCC_ETHMAC_CLK_ENABLE();
mbed_official 489:119543c9f674 30 (+++) __HAL_RCC_ETHMACTX_CLK_ENABLE();
mbed_official 489:119543c9f674 31 (+++) __HAL_RCC_ETHMACRX_CLK_ENABLE();
mbed_official 489:119543c9f674 32
mbed_official 489:119543c9f674 33 (##) Initialize the related GPIO clocks
mbed_official 489:119543c9f674 34 (##) Configure Ethernet pin-out
mbed_official 489:119543c9f674 35 (##) Configure Ethernet NVIC interrupt (IT mode)
mbed_official 489:119543c9f674 36
mbed_official 489:119543c9f674 37 (#)Initialize Ethernet DMA Descriptors in chain mode and point to allocated buffers:
mbed_official 489:119543c9f674 38 (##) HAL_ETH_DMATxDescListInit(); for Transmission process
mbed_official 489:119543c9f674 39 (##) HAL_ETH_DMARxDescListInit(); for Reception process
mbed_official 489:119543c9f674 40
mbed_official 489:119543c9f674 41 (#)Enable MAC and DMA transmission and reception:
mbed_official 489:119543c9f674 42 (##) HAL_ETH_Start();
mbed_official 489:119543c9f674 43
mbed_official 489:119543c9f674 44 (#)Prepare ETH DMA TX Descriptors and give the hand to ETH DMA to transfer
mbed_official 489:119543c9f674 45 the frame to MAC TX FIFO:
mbed_official 489:119543c9f674 46 (##) HAL_ETH_TransmitFrame();
mbed_official 489:119543c9f674 47
mbed_official 489:119543c9f674 48 (#)Poll for a received frame in ETH RX DMA Descriptors and get received
mbed_official 489:119543c9f674 49 frame parameters
mbed_official 489:119543c9f674 50 (##) HAL_ETH_GetReceivedFrame(); (should be called into an infinite loop)
mbed_official 489:119543c9f674 51
mbed_official 489:119543c9f674 52 (#) Get a received frame when an ETH RX interrupt occurs:
mbed_official 489:119543c9f674 53 (##) HAL_ETH_GetReceivedFrame_IT(); (called in IT mode only)
mbed_official 489:119543c9f674 54
mbed_official 489:119543c9f674 55 (#) Communicate with external PHY device:
mbed_official 489:119543c9f674 56 (##) Read a specific register from the PHY
mbed_official 489:119543c9f674 57 HAL_ETH_ReadPHYRegister();
mbed_official 489:119543c9f674 58 (##) Write data to a specific RHY register:
mbed_official 489:119543c9f674 59 HAL_ETH_WritePHYRegister();
mbed_official 489:119543c9f674 60
mbed_official 489:119543c9f674 61 (#) Configure the Ethernet MAC after ETH peripheral initialization
mbed_official 489:119543c9f674 62 HAL_ETH_ConfigMAC(); all MAC parameters should be filled.
mbed_official 489:119543c9f674 63
mbed_official 489:119543c9f674 64 (#) Configure the Ethernet DMA after ETH peripheral initialization
mbed_official 489:119543c9f674 65 HAL_ETH_ConfigDMA(); all DMA parameters should be filled.
mbed_official 489:119543c9f674 66
mbed_official 489:119543c9f674 67 -@- The PTP protocol and the DMA descriptors ring mode are not supported
mbed_official 489:119543c9f674 68 in this driver
mbed_official 489:119543c9f674 69
mbed_official 489:119543c9f674 70 @endverbatim
mbed_official 489:119543c9f674 71 ******************************************************************************
mbed_official 489:119543c9f674 72 * @attention
mbed_official 489:119543c9f674 73 *
mbed_official 489:119543c9f674 74 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
mbed_official 489:119543c9f674 75 *
mbed_official 489:119543c9f674 76 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 489:119543c9f674 77 * are permitted provided that the following conditions are met:
mbed_official 489:119543c9f674 78 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 489:119543c9f674 79 * this list of conditions and the following disclaimer.
mbed_official 489:119543c9f674 80 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 489:119543c9f674 81 * this list of conditions and the following disclaimer in the documentation
mbed_official 489:119543c9f674 82 * and/or other materials provided with the distribution.
mbed_official 489:119543c9f674 83 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 489:119543c9f674 84 * may be used to endorse or promote products derived from this software
mbed_official 489:119543c9f674 85 * without specific prior written permission.
mbed_official 489:119543c9f674 86 *
mbed_official 489:119543c9f674 87 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 489:119543c9f674 88 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 489:119543c9f674 89 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 489:119543c9f674 90 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 489:119543c9f674 91 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 489:119543c9f674 92 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 489:119543c9f674 93 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 489:119543c9f674 94 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 489:119543c9f674 95 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 489:119543c9f674 96 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 489:119543c9f674 97 *
mbed_official 489:119543c9f674 98 ******************************************************************************
mbed_official 489:119543c9f674 99 */
mbed_official 489:119543c9f674 100
mbed_official 489:119543c9f674 101 /* Includes ------------------------------------------------------------------*/
mbed_official 489:119543c9f674 102 #include "stm32f1xx_hal.h"
mbed_official 489:119543c9f674 103
mbed_official 489:119543c9f674 104 /** @addtogroup STM32F1xx_HAL_Driver
mbed_official 489:119543c9f674 105 * @{
mbed_official 489:119543c9f674 106 */
mbed_official 489:119543c9f674 107 #if defined (STM32F107xC)
mbed_official 489:119543c9f674 108
mbed_official 489:119543c9f674 109 /** @defgroup ETH ETH
mbed_official 489:119543c9f674 110 * @brief ETH HAL module driver
mbed_official 489:119543c9f674 111 * @{
mbed_official 489:119543c9f674 112 */
mbed_official 489:119543c9f674 113
mbed_official 489:119543c9f674 114 #ifdef HAL_ETH_MODULE_ENABLED
mbed_official 489:119543c9f674 115
mbed_official 489:119543c9f674 116 /* Private typedef -----------------------------------------------------------*/
mbed_official 489:119543c9f674 117 /* Private define ------------------------------------------------------------*/
mbed_official 489:119543c9f674 118 /** @defgroup ETH_Private_Constants ETH Private Constants
mbed_official 489:119543c9f674 119 * @{
mbed_official 489:119543c9f674 120 */
mbed_official 489:119543c9f674 121 #define LINKED_STATE_TIMEOUT_VALUE ((uint32_t)2000) /* 2000 ms */
mbed_official 489:119543c9f674 122 #define AUTONEGO_COMPLETED_TIMEOUT_VALUE ((uint32_t)1000) /* 1000 ms */
mbed_official 489:119543c9f674 123
mbed_official 489:119543c9f674 124 /**
mbed_official 489:119543c9f674 125 * @}
mbed_official 489:119543c9f674 126 */
mbed_official 489:119543c9f674 127
mbed_official 489:119543c9f674 128 /* Private macro -------------------------------------------------------------*/
mbed_official 489:119543c9f674 129 /* Private variables ---------------------------------------------------------*/
mbed_official 489:119543c9f674 130 /* Private function prototypes -----------------------------------------------*/
mbed_official 489:119543c9f674 131 /** @defgroup ETH_Private_Functions ETH Private Functions
mbed_official 489:119543c9f674 132 * @{
mbed_official 489:119543c9f674 133 */
mbed_official 489:119543c9f674 134 static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err);
mbed_official 489:119543c9f674 135 static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr);
mbed_official 489:119543c9f674 136 static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth);
mbed_official 489:119543c9f674 137 static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth);
mbed_official 489:119543c9f674 138 static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth);
mbed_official 489:119543c9f674 139 static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth);
mbed_official 489:119543c9f674 140 static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth);
mbed_official 489:119543c9f674 141 static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth);
mbed_official 489:119543c9f674 142 static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth);
mbed_official 489:119543c9f674 143 static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth);
mbed_official 489:119543c9f674 144 static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth);
mbed_official 489:119543c9f674 145
mbed_official 489:119543c9f674 146 /**
mbed_official 489:119543c9f674 147 * @}
mbed_official 489:119543c9f674 148 */
mbed_official 489:119543c9f674 149 /* Private functions ---------------------------------------------------------*/
mbed_official 489:119543c9f674 150
mbed_official 489:119543c9f674 151 /** @defgroup ETH_Exported_Functions ETH Exported Functions
mbed_official 489:119543c9f674 152 * @{
mbed_official 489:119543c9f674 153 */
mbed_official 489:119543c9f674 154
mbed_official 489:119543c9f674 155 /** @defgroup ETH_Exported_Functions_Group1 Initialization and de-initialization functions
mbed_official 489:119543c9f674 156 * @brief Initialization and Configuration functions
mbed_official 489:119543c9f674 157 *
mbed_official 489:119543c9f674 158 @verbatim
mbed_official 489:119543c9f674 159 ===============================================================================
mbed_official 489:119543c9f674 160 ##### Initialization and de-initialization functions #####
mbed_official 489:119543c9f674 161 ===============================================================================
mbed_official 489:119543c9f674 162 [..] This section provides functions allowing to:
mbed_official 489:119543c9f674 163 (+) Initialize and configure the Ethernet peripheral
mbed_official 489:119543c9f674 164 (+) De-initialize the Ethernet peripheral
mbed_official 489:119543c9f674 165
mbed_official 489:119543c9f674 166 @endverbatim
mbed_official 489:119543c9f674 167 * @{
mbed_official 489:119543c9f674 168 */
mbed_official 489:119543c9f674 169
mbed_official 489:119543c9f674 170 /**
mbed_official 489:119543c9f674 171 * @brief Initializes the Ethernet MAC and DMA according to default
mbed_official 489:119543c9f674 172 * parameters.
mbed_official 489:119543c9f674 173 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 489:119543c9f674 174 * the configuration information for ETHERNET module
mbed_official 489:119543c9f674 175 * @retval HAL status
mbed_official 489:119543c9f674 176 */
mbed_official 489:119543c9f674 177 HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
mbed_official 489:119543c9f674 178 {
mbed_official 489:119543c9f674 179 uint32_t tmpreg = 0, phyreg = 0;
mbed_official 489:119543c9f674 180 uint32_t hclk = 60000000;
mbed_official 489:119543c9f674 181 uint32_t tickstart = 0;
mbed_official 489:119543c9f674 182 uint32_t err = ETH_SUCCESS;
mbed_official 489:119543c9f674 183
mbed_official 489:119543c9f674 184 /* Check the ETH peripheral state */
mbed_official 489:119543c9f674 185 if(heth == NULL)
mbed_official 489:119543c9f674 186 {
mbed_official 489:119543c9f674 187 return HAL_ERROR;
mbed_official 489:119543c9f674 188 }
mbed_official 489:119543c9f674 189
mbed_official 489:119543c9f674 190 /* Check parameters */
mbed_official 489:119543c9f674 191 assert_param(IS_ETH_AUTONEGOTIATION(heth->Init.AutoNegotiation));
mbed_official 489:119543c9f674 192 assert_param(IS_ETH_RX_MODE(heth->Init.RxMode));
mbed_official 489:119543c9f674 193 assert_param(IS_ETH_CHECKSUM_MODE(heth->Init.ChecksumMode));
mbed_official 489:119543c9f674 194 assert_param(IS_ETH_MEDIA_INTERFACE(heth->Init.MediaInterface));
mbed_official 489:119543c9f674 195
mbed_official 489:119543c9f674 196 if(heth->State == HAL_ETH_STATE_RESET)
mbed_official 489:119543c9f674 197 {
mbed_official 489:119543c9f674 198 /* Allocate lock resource and initialize it */
mbed_official 489:119543c9f674 199 heth-> Lock = HAL_UNLOCKED;
mbed_official 489:119543c9f674 200
mbed_official 489:119543c9f674 201 /* Init the low level hardware : GPIO, CLOCK, NVIC. */
mbed_official 489:119543c9f674 202 HAL_ETH_MspInit(heth);
mbed_official 489:119543c9f674 203 }
mbed_official 489:119543c9f674 204
mbed_official 489:119543c9f674 205 /* Select MII or RMII Mode*/
mbed_official 489:119543c9f674 206 AFIO->MAPR &= ~(AFIO_MAPR_MII_RMII_SEL);
mbed_official 489:119543c9f674 207 AFIO->MAPR |= (uint32_t)heth->Init.MediaInterface;
mbed_official 489:119543c9f674 208
mbed_official 489:119543c9f674 209 /* Ethernet Software reset */
mbed_official 489:119543c9f674 210 /* Set the SWR bit: resets all MAC subsystem internal registers and logic */
mbed_official 489:119543c9f674 211 /* After reset all the registers holds their respective reset values */
mbed_official 489:119543c9f674 212 (heth->Instance)->DMABMR |= ETH_DMABMR_SR;
mbed_official 489:119543c9f674 213
mbed_official 489:119543c9f674 214 /* Wait for software reset */
mbed_official 489:119543c9f674 215 while (((heth->Instance)->DMABMR & ETH_DMABMR_SR) != (uint32_t)RESET)
mbed_official 489:119543c9f674 216 {
mbed_official 489:119543c9f674 217 }
mbed_official 489:119543c9f674 218
mbed_official 489:119543c9f674 219 /*-------------------------------- MAC Initialization ----------------------*/
mbed_official 489:119543c9f674 220 /* Get the ETHERNET MACMIIAR value */
mbed_official 489:119543c9f674 221 tmpreg = (heth->Instance)->MACMIIAR;
mbed_official 489:119543c9f674 222 /* Clear CSR Clock Range CR[2:0] bits */
mbed_official 489:119543c9f674 223 tmpreg &= ETH_MACMIIAR_CR_MASK;
mbed_official 489:119543c9f674 224
mbed_official 489:119543c9f674 225 /* Get hclk frequency value */
mbed_official 489:119543c9f674 226 hclk = HAL_RCC_GetHCLKFreq();
mbed_official 489:119543c9f674 227
mbed_official 489:119543c9f674 228 /* Set CR bits depending on hclk value */
mbed_official 489:119543c9f674 229 if((hclk >= 20000000)&&(hclk < 35000000))
mbed_official 489:119543c9f674 230 {
mbed_official 489:119543c9f674 231 /* CSR Clock Range between 20-35 MHz */
mbed_official 489:119543c9f674 232 tmpreg |= (uint32_t)ETH_MACMIIAR_CR_DIV16;
mbed_official 489:119543c9f674 233 }
mbed_official 489:119543c9f674 234 else if((hclk >= 35000000)&&(hclk < 60000000))
mbed_official 489:119543c9f674 235 {
mbed_official 489:119543c9f674 236 /* CSR Clock Range between 35-60 MHz */
mbed_official 489:119543c9f674 237 tmpreg |= (uint32_t)ETH_MACMIIAR_CR_DIV26;
mbed_official 489:119543c9f674 238 }
mbed_official 489:119543c9f674 239 else
mbed_official 489:119543c9f674 240 {
mbed_official 489:119543c9f674 241 /* CSR Clock Range between 60-72 MHz */
mbed_official 489:119543c9f674 242 tmpreg |= (uint32_t)ETH_MACMIIAR_CR_DIV42;
mbed_official 489:119543c9f674 243 }
mbed_official 489:119543c9f674 244
mbed_official 489:119543c9f674 245 /* Write to ETHERNET MAC MIIAR: Configure the ETHERNET CSR Clock Range */
mbed_official 489:119543c9f674 246 (heth->Instance)->MACMIIAR = (uint32_t)tmpreg;
mbed_official 489:119543c9f674 247
mbed_official 489:119543c9f674 248 /*-------------------- PHY initialization and configuration ----------------*/
mbed_official 489:119543c9f674 249 /* Put the PHY in reset mode */
mbed_official 489:119543c9f674 250 if((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_RESET)) != HAL_OK)
mbed_official 489:119543c9f674 251 {
mbed_official 489:119543c9f674 252 /* In case of write timeout */
mbed_official 489:119543c9f674 253 err = ETH_ERROR;
mbed_official 489:119543c9f674 254
mbed_official 489:119543c9f674 255 /* Config MAC and DMA */
mbed_official 489:119543c9f674 256 ETH_MACDMAConfig(heth, err);
mbed_official 489:119543c9f674 257
mbed_official 489:119543c9f674 258 /* Set the ETH peripheral state to READY */
mbed_official 489:119543c9f674 259 heth->State = HAL_ETH_STATE_READY;
mbed_official 489:119543c9f674 260
mbed_official 489:119543c9f674 261 /* Return HAL_ERROR */
mbed_official 489:119543c9f674 262 return HAL_ERROR;
mbed_official 489:119543c9f674 263 }
mbed_official 489:119543c9f674 264
mbed_official 489:119543c9f674 265 /* Delay to assure PHY reset */
mbed_official 489:119543c9f674 266 HAL_Delay(PHY_RESET_DELAY);
mbed_official 489:119543c9f674 267
mbed_official 489:119543c9f674 268 if((heth->Init).AutoNegotiation != ETH_AUTONEGOTIATION_DISABLE)
mbed_official 489:119543c9f674 269 {
mbed_official 489:119543c9f674 270 /* Get tick */
mbed_official 489:119543c9f674 271 tickstart = HAL_GetTick();
mbed_official 489:119543c9f674 272
mbed_official 489:119543c9f674 273 /* We wait for linked status */
mbed_official 489:119543c9f674 274 do
mbed_official 489:119543c9f674 275 {
mbed_official 489:119543c9f674 276 HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg);
mbed_official 489:119543c9f674 277
mbed_official 489:119543c9f674 278 /* Check for the Timeout */
mbed_official 489:119543c9f674 279 if((HAL_GetTick() - tickstart ) > LINKED_STATE_TIMEOUT_VALUE)
mbed_official 489:119543c9f674 280 {
mbed_official 489:119543c9f674 281 /* In case of write timeout */
mbed_official 489:119543c9f674 282 err = ETH_ERROR;
mbed_official 489:119543c9f674 283
mbed_official 489:119543c9f674 284 /* Config MAC and DMA */
mbed_official 489:119543c9f674 285 ETH_MACDMAConfig(heth, err);
mbed_official 489:119543c9f674 286
mbed_official 489:119543c9f674 287 heth->State= HAL_ETH_STATE_READY;
mbed_official 489:119543c9f674 288
mbed_official 489:119543c9f674 289 /* Process Unlocked */
mbed_official 489:119543c9f674 290 __HAL_UNLOCK(heth);
mbed_official 489:119543c9f674 291
mbed_official 489:119543c9f674 292 return HAL_TIMEOUT;
mbed_official 489:119543c9f674 293 }
mbed_official 489:119543c9f674 294 } while (((phyreg & PHY_LINKED_STATUS) != PHY_LINKED_STATUS));
mbed_official 489:119543c9f674 295
mbed_official 489:119543c9f674 296
mbed_official 489:119543c9f674 297 /* Enable Auto-Negotiation */
mbed_official 489:119543c9f674 298 if((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_AUTONEGOTIATION)) != HAL_OK)
mbed_official 489:119543c9f674 299 {
mbed_official 489:119543c9f674 300 /* In case of write timeout */
mbed_official 489:119543c9f674 301 err = ETH_ERROR;
mbed_official 489:119543c9f674 302
mbed_official 489:119543c9f674 303 /* Config MAC and DMA */
mbed_official 489:119543c9f674 304 ETH_MACDMAConfig(heth, err);
mbed_official 489:119543c9f674 305
mbed_official 489:119543c9f674 306 /* Set the ETH peripheral state to READY */
mbed_official 489:119543c9f674 307 heth->State = HAL_ETH_STATE_READY;
mbed_official 489:119543c9f674 308
mbed_official 489:119543c9f674 309 /* Return HAL_ERROR */
mbed_official 489:119543c9f674 310 return HAL_ERROR;
mbed_official 489:119543c9f674 311 }
mbed_official 489:119543c9f674 312
mbed_official 489:119543c9f674 313 /* Get tick */
mbed_official 489:119543c9f674 314 tickstart = HAL_GetTick();
mbed_official 489:119543c9f674 315
mbed_official 489:119543c9f674 316 /* Wait until the auto-negotiation will be completed */
mbed_official 489:119543c9f674 317 do
mbed_official 489:119543c9f674 318 {
mbed_official 489:119543c9f674 319 HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg);
mbed_official 489:119543c9f674 320
mbed_official 489:119543c9f674 321 /* Check for the Timeout */
mbed_official 489:119543c9f674 322 if((HAL_GetTick() - tickstart ) > AUTONEGO_COMPLETED_TIMEOUT_VALUE)
mbed_official 489:119543c9f674 323 {
mbed_official 489:119543c9f674 324 /* In case of write timeout */
mbed_official 489:119543c9f674 325 err = ETH_ERROR;
mbed_official 489:119543c9f674 326
mbed_official 489:119543c9f674 327 /* Config MAC and DMA */
mbed_official 489:119543c9f674 328 ETH_MACDMAConfig(heth, err);
mbed_official 489:119543c9f674 329
mbed_official 489:119543c9f674 330 heth->State= HAL_ETH_STATE_READY;
mbed_official 489:119543c9f674 331
mbed_official 489:119543c9f674 332 /* Process Unlocked */
mbed_official 489:119543c9f674 333 __HAL_UNLOCK(heth);
mbed_official 489:119543c9f674 334
mbed_official 489:119543c9f674 335 return HAL_TIMEOUT;
mbed_official 489:119543c9f674 336 }
mbed_official 489:119543c9f674 337
mbed_official 489:119543c9f674 338 } while (((phyreg & PHY_AUTONEGO_COMPLETE) != PHY_AUTONEGO_COMPLETE));
mbed_official 489:119543c9f674 339
mbed_official 489:119543c9f674 340 /* Read the result of the auto-negotiation */
mbed_official 489:119543c9f674 341 if((HAL_ETH_ReadPHYRegister(heth, PHY_SR, &phyreg)) != HAL_OK)
mbed_official 489:119543c9f674 342 {
mbed_official 489:119543c9f674 343 /* In case of write timeout */
mbed_official 489:119543c9f674 344 err = ETH_ERROR;
mbed_official 489:119543c9f674 345
mbed_official 489:119543c9f674 346 /* Config MAC and DMA */
mbed_official 489:119543c9f674 347 ETH_MACDMAConfig(heth, err);
mbed_official 489:119543c9f674 348
mbed_official 489:119543c9f674 349 /* Set the ETH peripheral state to READY */
mbed_official 489:119543c9f674 350 heth->State = HAL_ETH_STATE_READY;
mbed_official 489:119543c9f674 351
mbed_official 489:119543c9f674 352 /* Return HAL_ERROR */
mbed_official 489:119543c9f674 353 return HAL_ERROR;
mbed_official 489:119543c9f674 354 }
mbed_official 489:119543c9f674 355
mbed_official 489:119543c9f674 356 /* Configure the MAC with the Duplex Mode fixed by the auto-negotiation process */
mbed_official 489:119543c9f674 357 if((phyreg & PHY_DUPLEX_STATUS) != (uint32_t)RESET)
mbed_official 489:119543c9f674 358 {
mbed_official 489:119543c9f674 359 /* Set Ethernet duplex mode to Full-duplex following the auto-negotiation */
mbed_official 489:119543c9f674 360 (heth->Init).DuplexMode = ETH_MODE_FULLDUPLEX;
mbed_official 489:119543c9f674 361 }
mbed_official 489:119543c9f674 362 else
mbed_official 489:119543c9f674 363 {
mbed_official 489:119543c9f674 364 /* Set Ethernet duplex mode to Half-duplex following the auto-negotiation */
mbed_official 489:119543c9f674 365 (heth->Init).DuplexMode = ETH_MODE_HALFDUPLEX;
mbed_official 489:119543c9f674 366 }
mbed_official 489:119543c9f674 367 /* Configure the MAC with the speed fixed by the auto-negotiation process */
mbed_official 489:119543c9f674 368 if((phyreg & PHY_SPEED_STATUS) == PHY_SPEED_STATUS)
mbed_official 489:119543c9f674 369 {
mbed_official 489:119543c9f674 370 /* Set Ethernet speed to 10M following the auto-negotiation */
mbed_official 489:119543c9f674 371 (heth->Init).Speed = ETH_SPEED_10M;
mbed_official 489:119543c9f674 372 }
mbed_official 489:119543c9f674 373 else
mbed_official 489:119543c9f674 374 {
mbed_official 489:119543c9f674 375 /* Set Ethernet speed to 100M following the auto-negotiation */
mbed_official 489:119543c9f674 376 (heth->Init).Speed = ETH_SPEED_100M;
mbed_official 489:119543c9f674 377 }
mbed_official 489:119543c9f674 378 }
mbed_official 489:119543c9f674 379 else /* AutoNegotiation Disable */
mbed_official 489:119543c9f674 380 {
mbed_official 489:119543c9f674 381 /* Check parameters */
mbed_official 489:119543c9f674 382 assert_param(IS_ETH_SPEED(heth->Init.Speed));
mbed_official 489:119543c9f674 383 assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode));
mbed_official 489:119543c9f674 384
mbed_official 489:119543c9f674 385 /* Set MAC Speed and Duplex Mode */
mbed_official 489:119543c9f674 386 if(HAL_ETH_WritePHYRegister(heth, PHY_BCR, ((uint16_t)((heth->Init).DuplexMode >> 3) |
mbed_official 489:119543c9f674 387 (uint16_t)((heth->Init).Speed >> 1))) != HAL_OK)
mbed_official 489:119543c9f674 388 {
mbed_official 489:119543c9f674 389 /* In case of write timeout */
mbed_official 489:119543c9f674 390 err = ETH_ERROR;
mbed_official 489:119543c9f674 391
mbed_official 489:119543c9f674 392 /* Config MAC and DMA */
mbed_official 489:119543c9f674 393 ETH_MACDMAConfig(heth, err);
mbed_official 489:119543c9f674 394
mbed_official 489:119543c9f674 395 /* Set the ETH peripheral state to READY */
mbed_official 489:119543c9f674 396 heth->State = HAL_ETH_STATE_READY;
mbed_official 489:119543c9f674 397
mbed_official 489:119543c9f674 398 /* Return HAL_ERROR */
mbed_official 489:119543c9f674 399 return HAL_ERROR;
mbed_official 489:119543c9f674 400 }
mbed_official 489:119543c9f674 401
mbed_official 489:119543c9f674 402 /* Delay to assure PHY configuration */
mbed_official 489:119543c9f674 403 HAL_Delay(PHY_CONFIG_DELAY);
mbed_official 489:119543c9f674 404 }
mbed_official 489:119543c9f674 405
mbed_official 489:119543c9f674 406 /* Config MAC and DMA */
mbed_official 489:119543c9f674 407 ETH_MACDMAConfig(heth, err);
mbed_official 489:119543c9f674 408
mbed_official 489:119543c9f674 409 /* Set ETH HAL State to Ready */
mbed_official 489:119543c9f674 410 heth->State= HAL_ETH_STATE_READY;
mbed_official 489:119543c9f674 411
mbed_official 489:119543c9f674 412 /* Return function status */
mbed_official 489:119543c9f674 413 return HAL_OK;
mbed_official 489:119543c9f674 414 }
mbed_official 489:119543c9f674 415
mbed_official 489:119543c9f674 416 /**
mbed_official 489:119543c9f674 417 * @brief De-Initializes the ETH peripheral.
mbed_official 489:119543c9f674 418 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 489:119543c9f674 419 * the configuration information for ETHERNET module
mbed_official 489:119543c9f674 420 * @retval HAL status
mbed_official 489:119543c9f674 421 */
mbed_official 489:119543c9f674 422 HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth)
mbed_official 489:119543c9f674 423 {
mbed_official 489:119543c9f674 424 /* Set the ETH peripheral state to BUSY */
mbed_official 489:119543c9f674 425 heth->State = HAL_ETH_STATE_BUSY;
mbed_official 489:119543c9f674 426
mbed_official 489:119543c9f674 427 /* De-Init the low level hardware : GPIO, CLOCK, NVIC. */
mbed_official 489:119543c9f674 428 HAL_ETH_MspDeInit(heth);
mbed_official 489:119543c9f674 429
mbed_official 489:119543c9f674 430 /* Set ETH HAL state to Disabled */
mbed_official 489:119543c9f674 431 heth->State= HAL_ETH_STATE_RESET;
mbed_official 489:119543c9f674 432
mbed_official 489:119543c9f674 433 /* Release Lock */
mbed_official 489:119543c9f674 434 __HAL_UNLOCK(heth);
mbed_official 489:119543c9f674 435
mbed_official 489:119543c9f674 436 /* Return function status */
mbed_official 489:119543c9f674 437 return HAL_OK;
mbed_official 489:119543c9f674 438 }
mbed_official 489:119543c9f674 439
mbed_official 489:119543c9f674 440 /**
mbed_official 489:119543c9f674 441 * @brief Initializes the DMA Tx descriptors in chain mode.
mbed_official 489:119543c9f674 442 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 489:119543c9f674 443 * the configuration information for ETHERNET module
mbed_official 489:119543c9f674 444 * @param DMATxDescTab: Pointer to the first Tx desc list
mbed_official 489:119543c9f674 445 * @param TxBuff: Pointer to the first TxBuffer list
mbed_official 489:119543c9f674 446 * @param TxBuffCount: Number of the used Tx desc in the list
mbed_official 489:119543c9f674 447 * @retval HAL status
mbed_official 489:119543c9f674 448 */
mbed_official 489:119543c9f674 449 HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t *TxBuff, uint32_t TxBuffCount)
mbed_official 489:119543c9f674 450 {
mbed_official 489:119543c9f674 451 uint32_t i = 0;
mbed_official 489:119543c9f674 452 ETH_DMADescTypeDef *dmatxdesc;
mbed_official 489:119543c9f674 453
mbed_official 489:119543c9f674 454 /* Process Locked */
mbed_official 489:119543c9f674 455 __HAL_LOCK(heth);
mbed_official 489:119543c9f674 456
mbed_official 489:119543c9f674 457 /* Set the ETH peripheral state to BUSY */
mbed_official 489:119543c9f674 458 heth->State = HAL_ETH_STATE_BUSY;
mbed_official 489:119543c9f674 459
mbed_official 489:119543c9f674 460 /* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */
mbed_official 489:119543c9f674 461 heth->TxDesc = DMATxDescTab;
mbed_official 489:119543c9f674 462
mbed_official 489:119543c9f674 463 /* Fill each DMATxDesc descriptor with the right values */
mbed_official 489:119543c9f674 464 for(i=0; i < TxBuffCount; i++)
mbed_official 489:119543c9f674 465 {
mbed_official 489:119543c9f674 466 /* Get the pointer on the ith member of the Tx Desc list */
mbed_official 489:119543c9f674 467 dmatxdesc = DMATxDescTab + i;
mbed_official 489:119543c9f674 468
mbed_official 489:119543c9f674 469 /* Set Second Address Chained bit */
mbed_official 489:119543c9f674 470 dmatxdesc->Status = ETH_DMATXDESC_TCH;
mbed_official 489:119543c9f674 471
mbed_official 489:119543c9f674 472 /* Set Buffer1 address pointer */
mbed_official 489:119543c9f674 473 dmatxdesc->Buffer1Addr = (uint32_t)(&TxBuff[i*ETH_TX_BUF_SIZE]);
mbed_official 489:119543c9f674 474
mbed_official 489:119543c9f674 475 if ((heth->Init).ChecksumMode == ETH_CHECKSUM_BY_HARDWARE)
mbed_official 489:119543c9f674 476 {
mbed_official 489:119543c9f674 477 /* Set the DMA Tx descriptors checksum insertion */
mbed_official 489:119543c9f674 478 dmatxdesc->Status |= ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL;
mbed_official 489:119543c9f674 479 }
mbed_official 489:119543c9f674 480
mbed_official 489:119543c9f674 481 /* Initialize the next descriptor with the Next Descriptor Polling Enable */
mbed_official 489:119543c9f674 482 if(i < (TxBuffCount-1))
mbed_official 489:119543c9f674 483 {
mbed_official 489:119543c9f674 484 /* Set next descriptor address register with next descriptor base address */
mbed_official 489:119543c9f674 485 dmatxdesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab+i+1);
mbed_official 489:119543c9f674 486 }
mbed_official 489:119543c9f674 487 else
mbed_official 489:119543c9f674 488 {
mbed_official 489:119543c9f674 489 /* For last descriptor, set next descriptor address register equal to the first descriptor base address */
mbed_official 489:119543c9f674 490 dmatxdesc->Buffer2NextDescAddr = (uint32_t) DMATxDescTab;
mbed_official 489:119543c9f674 491 }
mbed_official 489:119543c9f674 492 }
mbed_official 489:119543c9f674 493
mbed_official 489:119543c9f674 494 /* Set Transmit Descriptor List Address Register */
mbed_official 489:119543c9f674 495 (heth->Instance)->DMATDLAR = (uint32_t) DMATxDescTab;
mbed_official 489:119543c9f674 496
mbed_official 489:119543c9f674 497 /* Set ETH HAL State to Ready */
mbed_official 489:119543c9f674 498 heth->State= HAL_ETH_STATE_READY;
mbed_official 489:119543c9f674 499
mbed_official 489:119543c9f674 500 /* Process Unlocked */
mbed_official 489:119543c9f674 501 __HAL_UNLOCK(heth);
mbed_official 489:119543c9f674 502
mbed_official 489:119543c9f674 503 /* Return function status */
mbed_official 489:119543c9f674 504 return HAL_OK;
mbed_official 489:119543c9f674 505 }
mbed_official 489:119543c9f674 506
mbed_official 489:119543c9f674 507 /**
mbed_official 489:119543c9f674 508 * @brief Initializes the DMA Rx descriptors in chain mode.
mbed_official 489:119543c9f674 509 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 489:119543c9f674 510 * the configuration information for ETHERNET module
mbed_official 489:119543c9f674 511 * @param DMARxDescTab: Pointer to the first Rx desc list
mbed_official 489:119543c9f674 512 * @param RxBuff: Pointer to the first RxBuffer list
mbed_official 489:119543c9f674 513 * @param RxBuffCount: Number of the used Rx desc in the list
mbed_official 489:119543c9f674 514 * @retval HAL status
mbed_official 489:119543c9f674 515 */
mbed_official 489:119543c9f674 516 HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount)
mbed_official 489:119543c9f674 517 {
mbed_official 489:119543c9f674 518 uint32_t i = 0;
mbed_official 489:119543c9f674 519 ETH_DMADescTypeDef *DMARxDesc;
mbed_official 489:119543c9f674 520
mbed_official 489:119543c9f674 521 /* Process Locked */
mbed_official 489:119543c9f674 522 __HAL_LOCK(heth);
mbed_official 489:119543c9f674 523
mbed_official 489:119543c9f674 524 /* Set the ETH peripheral state to BUSY */
mbed_official 489:119543c9f674 525 heth->State = HAL_ETH_STATE_BUSY;
mbed_official 489:119543c9f674 526
mbed_official 489:119543c9f674 527 /* Set the Ethernet RxDesc pointer with the first one of the DMARxDescTab list */
mbed_official 489:119543c9f674 528 heth->RxDesc = DMARxDescTab;
mbed_official 489:119543c9f674 529
mbed_official 489:119543c9f674 530 /* Fill each DMARxDesc descriptor with the right values */
mbed_official 489:119543c9f674 531 for(i=0; i < RxBuffCount; i++)
mbed_official 489:119543c9f674 532 {
mbed_official 489:119543c9f674 533 /* Get the pointer on the ith member of the Rx Desc list */
mbed_official 489:119543c9f674 534 DMARxDesc = DMARxDescTab+i;
mbed_official 489:119543c9f674 535
mbed_official 489:119543c9f674 536 /* Set Own bit of the Rx descriptor Status */
mbed_official 489:119543c9f674 537 DMARxDesc->Status = ETH_DMARXDESC_OWN;
mbed_official 489:119543c9f674 538
mbed_official 489:119543c9f674 539 /* Set Buffer1 size and Second Address Chained bit */
mbed_official 489:119543c9f674 540 DMARxDesc->ControlBufferSize = ETH_DMARXDESC_RCH | ETH_RX_BUF_SIZE;
mbed_official 489:119543c9f674 541
mbed_official 489:119543c9f674 542 /* Set Buffer1 address pointer */
mbed_official 489:119543c9f674 543 DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff[i*ETH_RX_BUF_SIZE]);
mbed_official 489:119543c9f674 544
mbed_official 489:119543c9f674 545 if((heth->Init).RxMode == ETH_RXINTERRUPT_MODE)
mbed_official 489:119543c9f674 546 {
mbed_official 489:119543c9f674 547 /* Enable Ethernet DMA Rx Descriptor interrupt */
mbed_official 489:119543c9f674 548 DMARxDesc->ControlBufferSize &= ~ETH_DMARXDESC_DIC;
mbed_official 489:119543c9f674 549 }
mbed_official 489:119543c9f674 550
mbed_official 489:119543c9f674 551 /* Initialize the next descriptor with the Next Descriptor Polling Enable */
mbed_official 489:119543c9f674 552 if(i < (RxBuffCount-1))
mbed_official 489:119543c9f674 553 {
mbed_official 489:119543c9f674 554 /* Set next descriptor address register with next descriptor base address */
mbed_official 489:119543c9f674 555 DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab+i+1);
mbed_official 489:119543c9f674 556 }
mbed_official 489:119543c9f674 557 else
mbed_official 489:119543c9f674 558 {
mbed_official 489:119543c9f674 559 /* For last descriptor, set next descriptor address register equal to the first descriptor base address */
mbed_official 489:119543c9f674 560 DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab);
mbed_official 489:119543c9f674 561 }
mbed_official 489:119543c9f674 562 }
mbed_official 489:119543c9f674 563
mbed_official 489:119543c9f674 564 /* Set Receive Descriptor List Address Register */
mbed_official 489:119543c9f674 565 (heth->Instance)->DMARDLAR = (uint32_t) DMARxDescTab;
mbed_official 489:119543c9f674 566
mbed_official 489:119543c9f674 567 /* Set ETH HAL State to Ready */
mbed_official 489:119543c9f674 568 heth->State= HAL_ETH_STATE_READY;
mbed_official 489:119543c9f674 569
mbed_official 489:119543c9f674 570 /* Process Unlocked */
mbed_official 489:119543c9f674 571 __HAL_UNLOCK(heth);
mbed_official 489:119543c9f674 572
mbed_official 489:119543c9f674 573 /* Return function status */
mbed_official 489:119543c9f674 574 return HAL_OK;
mbed_official 489:119543c9f674 575 }
mbed_official 489:119543c9f674 576
mbed_official 489:119543c9f674 577 /**
mbed_official 489:119543c9f674 578 * @brief Initializes the ETH MSP.
mbed_official 489:119543c9f674 579 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 489:119543c9f674 580 * the configuration information for ETHERNET module
mbed_official 489:119543c9f674 581 * @retval None
mbed_official 489:119543c9f674 582 */
mbed_official 489:119543c9f674 583 __weak void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
mbed_official 489:119543c9f674 584 {
mbed_official 489:119543c9f674 585 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 489:119543c9f674 586 the HAL_ETH_MspInit could be implemented in the user file
mbed_official 489:119543c9f674 587 */
mbed_official 489:119543c9f674 588 }
mbed_official 489:119543c9f674 589
mbed_official 489:119543c9f674 590 /**
mbed_official 489:119543c9f674 591 * @brief DeInitializes ETH MSP.
mbed_official 489:119543c9f674 592 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 489:119543c9f674 593 * the configuration information for ETHERNET module
mbed_official 489:119543c9f674 594 * @retval None
mbed_official 489:119543c9f674 595 */
mbed_official 489:119543c9f674 596 __weak void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
mbed_official 489:119543c9f674 597 {
mbed_official 489:119543c9f674 598 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 489:119543c9f674 599 the HAL_ETH_MspDeInit could be implemented in the user file
mbed_official 489:119543c9f674 600 */
mbed_official 489:119543c9f674 601 }
mbed_official 489:119543c9f674 602
mbed_official 489:119543c9f674 603 /**
mbed_official 489:119543c9f674 604 * @}
mbed_official 489:119543c9f674 605 */
mbed_official 489:119543c9f674 606
mbed_official 489:119543c9f674 607 /** @defgroup ETH_Exported_Functions_Group2 IO operation functions
mbed_official 489:119543c9f674 608 * @brief Data transfers functions
mbed_official 489:119543c9f674 609 *
mbed_official 489:119543c9f674 610 @verbatim
mbed_official 489:119543c9f674 611 ==============================================================================
mbed_official 489:119543c9f674 612 ##### IO operation functions #####
mbed_official 489:119543c9f674 613 ==============================================================================
mbed_official 489:119543c9f674 614 [..] This section provides functions allowing to:
mbed_official 489:119543c9f674 615 (+) Transmit a frame
mbed_official 489:119543c9f674 616 HAL_ETH_TransmitFrame();
mbed_official 489:119543c9f674 617 (+) Receive a frame
mbed_official 489:119543c9f674 618 HAL_ETH_GetReceivedFrame();
mbed_official 489:119543c9f674 619 HAL_ETH_GetReceivedFrame_IT();
mbed_official 489:119543c9f674 620 (+) Read from an External PHY register
mbed_official 489:119543c9f674 621 HAL_ETH_ReadPHYRegister();
mbed_official 489:119543c9f674 622 (+) Write to an External PHY register
mbed_official 489:119543c9f674 623 HAL_ETH_WritePHYRegister();
mbed_official 489:119543c9f674 624
mbed_official 489:119543c9f674 625 @endverbatim
mbed_official 489:119543c9f674 626
mbed_official 489:119543c9f674 627 * @{
mbed_official 489:119543c9f674 628 */
mbed_official 489:119543c9f674 629
mbed_official 489:119543c9f674 630 /**
mbed_official 489:119543c9f674 631 * @brief Sends an Ethernet frame.
mbed_official 489:119543c9f674 632 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 489:119543c9f674 633 * the configuration information for ETHERNET module
mbed_official 489:119543c9f674 634 * @param FrameLength: Amount of data to be sent
mbed_official 489:119543c9f674 635 * @retval HAL status
mbed_official 489:119543c9f674 636 */
mbed_official 489:119543c9f674 637 HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength)
mbed_official 489:119543c9f674 638 {
mbed_official 489:119543c9f674 639 uint32_t bufcount = 0, size = 0, i = 0;
mbed_official 489:119543c9f674 640
mbed_official 489:119543c9f674 641 /* Process Locked */
mbed_official 489:119543c9f674 642 __HAL_LOCK(heth);
mbed_official 489:119543c9f674 643
mbed_official 489:119543c9f674 644 /* Set the ETH peripheral state to BUSY */
mbed_official 489:119543c9f674 645 heth->State = HAL_ETH_STATE_BUSY;
mbed_official 489:119543c9f674 646
mbed_official 489:119543c9f674 647 if (FrameLength == 0)
mbed_official 489:119543c9f674 648 {
mbed_official 489:119543c9f674 649 /* Set ETH HAL state to READY */
mbed_official 489:119543c9f674 650 heth->State = HAL_ETH_STATE_READY;
mbed_official 489:119543c9f674 651
mbed_official 489:119543c9f674 652 /* Process Unlocked */
mbed_official 489:119543c9f674 653 __HAL_UNLOCK(heth);
mbed_official 489:119543c9f674 654
mbed_official 489:119543c9f674 655 return HAL_ERROR;
mbed_official 489:119543c9f674 656 }
mbed_official 489:119543c9f674 657
mbed_official 489:119543c9f674 658 /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */
mbed_official 489:119543c9f674 659 if(((heth->TxDesc)->Status & ETH_DMATXDESC_OWN) != (uint32_t)RESET)
mbed_official 489:119543c9f674 660 {
mbed_official 489:119543c9f674 661 /* OWN bit set */
mbed_official 489:119543c9f674 662 heth->State = HAL_ETH_STATE_BUSY_TX;
mbed_official 489:119543c9f674 663
mbed_official 489:119543c9f674 664 /* Process Unlocked */
mbed_official 489:119543c9f674 665 __HAL_UNLOCK(heth);
mbed_official 489:119543c9f674 666
mbed_official 489:119543c9f674 667 return HAL_ERROR;
mbed_official 489:119543c9f674 668 }
mbed_official 489:119543c9f674 669
mbed_official 489:119543c9f674 670 /* Get the number of needed Tx buffers for the current frame */
mbed_official 489:119543c9f674 671 if (FrameLength > ETH_TX_BUF_SIZE)
mbed_official 489:119543c9f674 672 {
mbed_official 489:119543c9f674 673 bufcount = FrameLength/ETH_TX_BUF_SIZE;
mbed_official 489:119543c9f674 674 if (FrameLength % ETH_TX_BUF_SIZE)
mbed_official 489:119543c9f674 675 {
mbed_official 489:119543c9f674 676 bufcount++;
mbed_official 489:119543c9f674 677 }
mbed_official 489:119543c9f674 678 }
mbed_official 489:119543c9f674 679 else
mbed_official 489:119543c9f674 680 {
mbed_official 489:119543c9f674 681 bufcount = 1;
mbed_official 489:119543c9f674 682 }
mbed_official 489:119543c9f674 683 if (bufcount == 1)
mbed_official 489:119543c9f674 684 {
mbed_official 489:119543c9f674 685 /* Set LAST and FIRST segment */
mbed_official 489:119543c9f674 686 heth->TxDesc->Status |=ETH_DMATXDESC_FS|ETH_DMATXDESC_LS;
mbed_official 489:119543c9f674 687 /* Set frame size */
mbed_official 489:119543c9f674 688 heth->TxDesc->ControlBufferSize = (FrameLength & ETH_DMATXDESC_TBS1);
mbed_official 489:119543c9f674 689 /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
mbed_official 489:119543c9f674 690 heth->TxDesc->Status |= ETH_DMATXDESC_OWN;
mbed_official 489:119543c9f674 691 /* Point to next descriptor */
mbed_official 489:119543c9f674 692 heth->TxDesc= (ETH_DMADescTypeDef *)(heth->TxDesc->Buffer2NextDescAddr);
mbed_official 489:119543c9f674 693 }
mbed_official 489:119543c9f674 694 else
mbed_official 489:119543c9f674 695 {
mbed_official 489:119543c9f674 696 for (i=0; i< bufcount; i++)
mbed_official 489:119543c9f674 697 {
mbed_official 489:119543c9f674 698 /* Clear FIRST and LAST segment bits */
mbed_official 489:119543c9f674 699 heth->TxDesc->Status &= ~(ETH_DMATXDESC_FS | ETH_DMATXDESC_LS);
mbed_official 489:119543c9f674 700
mbed_official 489:119543c9f674 701 if (i == 0)
mbed_official 489:119543c9f674 702 {
mbed_official 489:119543c9f674 703 /* Setting the first segment bit */
mbed_official 489:119543c9f674 704 heth->TxDesc->Status |= ETH_DMATXDESC_FS;
mbed_official 489:119543c9f674 705 }
mbed_official 489:119543c9f674 706
mbed_official 489:119543c9f674 707 /* Program size */
mbed_official 489:119543c9f674 708 heth->TxDesc->ControlBufferSize = (ETH_TX_BUF_SIZE & ETH_DMATXDESC_TBS1);
mbed_official 489:119543c9f674 709
mbed_official 489:119543c9f674 710 if (i == (bufcount-1))
mbed_official 489:119543c9f674 711 {
mbed_official 489:119543c9f674 712 /* Setting the last segment bit */
mbed_official 489:119543c9f674 713 heth->TxDesc->Status |= ETH_DMATXDESC_LS;
mbed_official 489:119543c9f674 714 size = FrameLength - (bufcount-1)*ETH_TX_BUF_SIZE;
mbed_official 489:119543c9f674 715 heth->TxDesc->ControlBufferSize = (size & ETH_DMATXDESC_TBS1);
mbed_official 489:119543c9f674 716 }
mbed_official 489:119543c9f674 717
mbed_official 489:119543c9f674 718 /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
mbed_official 489:119543c9f674 719 heth->TxDesc->Status |= ETH_DMATXDESC_OWN;
mbed_official 489:119543c9f674 720 /* point to next descriptor */
mbed_official 489:119543c9f674 721 heth->TxDesc = (ETH_DMADescTypeDef *)(heth->TxDesc->Buffer2NextDescAddr);
mbed_official 489:119543c9f674 722 }
mbed_official 489:119543c9f674 723 }
mbed_official 489:119543c9f674 724
mbed_official 489:119543c9f674 725 /* When Tx Buffer unavailable flag is set: clear it and resume transmission */
mbed_official 489:119543c9f674 726 if (((heth->Instance)->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET)
mbed_official 489:119543c9f674 727 {
mbed_official 489:119543c9f674 728 /* Clear TBUS ETHERNET DMA flag */
mbed_official 489:119543c9f674 729 (heth->Instance)->DMASR = ETH_DMASR_TBUS;
mbed_official 489:119543c9f674 730 /* Resume DMA transmission*/
mbed_official 489:119543c9f674 731 (heth->Instance)->DMATPDR = 0;
mbed_official 489:119543c9f674 732 }
mbed_official 489:119543c9f674 733
mbed_official 489:119543c9f674 734 /* Set ETH HAL State to Ready */
mbed_official 489:119543c9f674 735 heth->State = HAL_ETH_STATE_READY;
mbed_official 489:119543c9f674 736
mbed_official 489:119543c9f674 737 /* Process Unlocked */
mbed_official 489:119543c9f674 738 __HAL_UNLOCK(heth);
mbed_official 489:119543c9f674 739
mbed_official 489:119543c9f674 740 /* Return function status */
mbed_official 489:119543c9f674 741 return HAL_OK;
mbed_official 489:119543c9f674 742 }
mbed_official 489:119543c9f674 743
mbed_official 489:119543c9f674 744 /**
mbed_official 489:119543c9f674 745 * @brief Checks for received frames.
mbed_official 489:119543c9f674 746 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 489:119543c9f674 747 * the configuration information for ETHERNET module
mbed_official 489:119543c9f674 748 * @retval HAL status
mbed_official 489:119543c9f674 749 */
mbed_official 489:119543c9f674 750 HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth)
mbed_official 489:119543c9f674 751 {
mbed_official 489:119543c9f674 752 uint32_t framelength = 0;
mbed_official 489:119543c9f674 753
mbed_official 489:119543c9f674 754 /* Process Locked */
mbed_official 489:119543c9f674 755 __HAL_LOCK(heth);
mbed_official 489:119543c9f674 756
mbed_official 489:119543c9f674 757 /* Check the ETH state to BUSY */
mbed_official 489:119543c9f674 758 heth->State = HAL_ETH_STATE_BUSY;
mbed_official 489:119543c9f674 759
mbed_official 489:119543c9f674 760 /* Check if segment is not owned by DMA */
mbed_official 489:119543c9f674 761 /* (((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && ((heth->RxDesc->Status & ETH_DMARXDESC_LS) != (uint32_t)RESET)) */
mbed_official 489:119543c9f674 762 if(((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET))
mbed_official 489:119543c9f674 763 {
mbed_official 489:119543c9f674 764 /* Check if last segment */
mbed_official 489:119543c9f674 765 if(((heth->RxDesc->Status & ETH_DMARXDESC_LS) != (uint32_t)RESET))
mbed_official 489:119543c9f674 766 {
mbed_official 489:119543c9f674 767 /* increment segment count */
mbed_official 489:119543c9f674 768 (heth->RxFrameInfos).SegCount++;
mbed_official 489:119543c9f674 769
mbed_official 489:119543c9f674 770 /* Check if last segment is first segment: one segment contains the frame */
mbed_official 489:119543c9f674 771 if ((heth->RxFrameInfos).SegCount == 1)
mbed_official 489:119543c9f674 772 {
mbed_official 489:119543c9f674 773 (heth->RxFrameInfos).FSRxDesc =heth->RxDesc;
mbed_official 489:119543c9f674 774 }
mbed_official 489:119543c9f674 775
mbed_official 489:119543c9f674 776 heth->RxFrameInfos.LSRxDesc = heth->RxDesc;
mbed_official 489:119543c9f674 777
mbed_official 489:119543c9f674 778 /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
mbed_official 489:119543c9f674 779 framelength = (((heth->RxDesc)->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4;
mbed_official 489:119543c9f674 780 heth->RxFrameInfos.length = framelength;
mbed_official 489:119543c9f674 781
mbed_official 489:119543c9f674 782 /* Get the address of the buffer start address */
mbed_official 489:119543c9f674 783 heth->RxFrameInfos.buffer = ((heth->RxFrameInfos).FSRxDesc)->Buffer1Addr;
mbed_official 489:119543c9f674 784 /* point to next descriptor */
mbed_official 489:119543c9f674 785 heth->RxDesc = (ETH_DMADescTypeDef*) ((heth->RxDesc)->Buffer2NextDescAddr);
mbed_official 489:119543c9f674 786
mbed_official 489:119543c9f674 787 /* Set HAL State to Ready */
mbed_official 489:119543c9f674 788 heth->State = HAL_ETH_STATE_READY;
mbed_official 489:119543c9f674 789
mbed_official 489:119543c9f674 790 /* Process Unlocked */
mbed_official 489:119543c9f674 791 __HAL_UNLOCK(heth);
mbed_official 489:119543c9f674 792
mbed_official 489:119543c9f674 793 /* Return function status */
mbed_official 489:119543c9f674 794 return HAL_OK;
mbed_official 489:119543c9f674 795 }
mbed_official 489:119543c9f674 796 /* Check if first segment */
mbed_official 489:119543c9f674 797 else if((heth->RxDesc->Status & ETH_DMARXDESC_FS) != (uint32_t)RESET)
mbed_official 489:119543c9f674 798 {
mbed_official 489:119543c9f674 799 (heth->RxFrameInfos).FSRxDesc = heth->RxDesc;
mbed_official 489:119543c9f674 800 (heth->RxFrameInfos).LSRxDesc = NULL;
mbed_official 489:119543c9f674 801 (heth->RxFrameInfos).SegCount = 1;
mbed_official 489:119543c9f674 802 /* Point to next descriptor */
mbed_official 489:119543c9f674 803 heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
mbed_official 489:119543c9f674 804 }
mbed_official 489:119543c9f674 805 /* Check if intermediate segment */
mbed_official 489:119543c9f674 806 else
mbed_official 489:119543c9f674 807 {
mbed_official 489:119543c9f674 808 (heth->RxFrameInfos).SegCount++;
mbed_official 489:119543c9f674 809 /* Point to next descriptor */
mbed_official 489:119543c9f674 810 heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
mbed_official 489:119543c9f674 811 }
mbed_official 489:119543c9f674 812 }
mbed_official 489:119543c9f674 813
mbed_official 489:119543c9f674 814 /* Set ETH HAL State to Ready */
mbed_official 489:119543c9f674 815 heth->State = HAL_ETH_STATE_READY;
mbed_official 489:119543c9f674 816
mbed_official 489:119543c9f674 817 /* Process Unlocked */
mbed_official 489:119543c9f674 818 __HAL_UNLOCK(heth);
mbed_official 489:119543c9f674 819
mbed_official 489:119543c9f674 820 /* Return function status */
mbed_official 489:119543c9f674 821 return HAL_ERROR;
mbed_official 489:119543c9f674 822 }
mbed_official 489:119543c9f674 823
mbed_official 489:119543c9f674 824 /**
mbed_official 489:119543c9f674 825 * @brief Gets the Received frame in interrupt mode.
mbed_official 489:119543c9f674 826 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 489:119543c9f674 827 * the configuration information for ETHERNET module
mbed_official 489:119543c9f674 828 * @retval HAL status
mbed_official 489:119543c9f674 829 */
mbed_official 489:119543c9f674 830 HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth)
mbed_official 489:119543c9f674 831 {
mbed_official 489:119543c9f674 832 uint32_t descriptorscancounter = 0;
mbed_official 489:119543c9f674 833
mbed_official 489:119543c9f674 834 /* Process Locked */
mbed_official 489:119543c9f674 835 __HAL_LOCK(heth);
mbed_official 489:119543c9f674 836
mbed_official 489:119543c9f674 837 /* Set ETH HAL State to BUSY */
mbed_official 489:119543c9f674 838 heth->State = HAL_ETH_STATE_BUSY;
mbed_official 489:119543c9f674 839
mbed_official 489:119543c9f674 840 /* Scan descriptors owned by CPU */
mbed_official 489:119543c9f674 841 while (((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && (descriptorscancounter < ETH_RXBUFNB))
mbed_official 489:119543c9f674 842 {
mbed_official 489:119543c9f674 843 /* Just for security */
mbed_official 489:119543c9f674 844 descriptorscancounter++;
mbed_official 489:119543c9f674 845
mbed_official 489:119543c9f674 846 /* Check if first segment in frame */
mbed_official 489:119543c9f674 847 /* ((heth->RxDesc->Status & ETH_DMARXDESC_FS) != (uint32_t)RESET) && ((heth->RxDesc->Status & ETH_DMARXDESC_LS) == (uint32_t)RESET)) */
mbed_official 489:119543c9f674 848 if((heth->RxDesc->Status & (ETH_DMARXDESC_FS | ETH_DMARXDESC_LS)) == (uint32_t)ETH_DMARXDESC_FS)
mbed_official 489:119543c9f674 849 {
mbed_official 489:119543c9f674 850 heth->RxFrameInfos.FSRxDesc = heth->RxDesc;
mbed_official 489:119543c9f674 851 heth->RxFrameInfos.SegCount = 1;
mbed_official 489:119543c9f674 852 /* Point to next descriptor */
mbed_official 489:119543c9f674 853 heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
mbed_official 489:119543c9f674 854 }
mbed_official 489:119543c9f674 855 /* Check if intermediate segment */
mbed_official 489:119543c9f674 856 /* ((heth->RxDesc->Status & ETH_DMARXDESC_LS) == (uint32_t)RESET)&& ((heth->RxDesc->Status & ETH_DMARXDESC_FS) == (uint32_t)RESET)) */
mbed_official 489:119543c9f674 857 else if ((heth->RxDesc->Status & (ETH_DMARXDESC_LS | ETH_DMARXDESC_FS)) == (uint32_t)RESET)
mbed_official 489:119543c9f674 858 {
mbed_official 489:119543c9f674 859 /* Increment segment count */
mbed_official 489:119543c9f674 860 (heth->RxFrameInfos.SegCount)++;
mbed_official 489:119543c9f674 861 /* Point to next descriptor */
mbed_official 489:119543c9f674 862 heth->RxDesc = (ETH_DMADescTypeDef*)(heth->RxDesc->Buffer2NextDescAddr);
mbed_official 489:119543c9f674 863 }
mbed_official 489:119543c9f674 864 /* Should be last segment */
mbed_official 489:119543c9f674 865 else
mbed_official 489:119543c9f674 866 {
mbed_official 489:119543c9f674 867 /* Last segment */
mbed_official 489:119543c9f674 868 heth->RxFrameInfos.LSRxDesc = heth->RxDesc;
mbed_official 489:119543c9f674 869
mbed_official 489:119543c9f674 870 /* Increment segment count */
mbed_official 489:119543c9f674 871 (heth->RxFrameInfos.SegCount)++;
mbed_official 489:119543c9f674 872
mbed_official 489:119543c9f674 873 /* Check if last segment is first segment: one segment contains the frame */
mbed_official 489:119543c9f674 874 if ((heth->RxFrameInfos.SegCount) == 1)
mbed_official 489:119543c9f674 875 {
mbed_official 489:119543c9f674 876 heth->RxFrameInfos.FSRxDesc = heth->RxDesc;
mbed_official 489:119543c9f674 877 }
mbed_official 489:119543c9f674 878
mbed_official 489:119543c9f674 879 /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
mbed_official 489:119543c9f674 880 heth->RxFrameInfos.length = (((heth->RxDesc)->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4;
mbed_official 489:119543c9f674 881
mbed_official 489:119543c9f674 882 /* Get the address of the buffer start address */
mbed_official 489:119543c9f674 883 heth->RxFrameInfos.buffer =((heth->RxFrameInfos).FSRxDesc)->Buffer1Addr;
mbed_official 489:119543c9f674 884
mbed_official 489:119543c9f674 885 /* Point to next descriptor */
mbed_official 489:119543c9f674 886 heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
mbed_official 489:119543c9f674 887
mbed_official 489:119543c9f674 888 /* Set HAL State to Ready */
mbed_official 489:119543c9f674 889 heth->State = HAL_ETH_STATE_READY;
mbed_official 489:119543c9f674 890
mbed_official 489:119543c9f674 891 /* Process Unlocked */
mbed_official 489:119543c9f674 892 __HAL_UNLOCK(heth);
mbed_official 489:119543c9f674 893
mbed_official 489:119543c9f674 894 /* Return function status */
mbed_official 489:119543c9f674 895 return HAL_OK;
mbed_official 489:119543c9f674 896 }
mbed_official 489:119543c9f674 897 }
mbed_official 489:119543c9f674 898
mbed_official 489:119543c9f674 899 /* Set HAL State to Ready */
mbed_official 489:119543c9f674 900 heth->State = HAL_ETH_STATE_READY;
mbed_official 489:119543c9f674 901
mbed_official 489:119543c9f674 902 /* Process Unlocked */
mbed_official 489:119543c9f674 903 __HAL_UNLOCK(heth);
mbed_official 489:119543c9f674 904
mbed_official 489:119543c9f674 905 /* Return function status */
mbed_official 489:119543c9f674 906 return HAL_ERROR;
mbed_official 489:119543c9f674 907 }
mbed_official 489:119543c9f674 908
mbed_official 489:119543c9f674 909 /**
mbed_official 489:119543c9f674 910 * @brief This function handles ETH interrupt request.
mbed_official 489:119543c9f674 911 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 489:119543c9f674 912 * the configuration information for ETHERNET module
mbed_official 489:119543c9f674 913 * @retval HAL status
mbed_official 489:119543c9f674 914 */
mbed_official 489:119543c9f674 915 void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth)
mbed_official 489:119543c9f674 916 {
mbed_official 489:119543c9f674 917 /* Frame received */
mbed_official 489:119543c9f674 918 if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_R))
mbed_official 489:119543c9f674 919 {
mbed_official 489:119543c9f674 920 /* Receive complete callback */
mbed_official 489:119543c9f674 921 HAL_ETH_RxCpltCallback(heth);
mbed_official 489:119543c9f674 922
mbed_official 489:119543c9f674 923 /* Clear the Eth DMA Rx IT pending bits */
mbed_official 489:119543c9f674 924 __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_R);
mbed_official 489:119543c9f674 925
mbed_official 489:119543c9f674 926 /* Set HAL State to Ready */
mbed_official 489:119543c9f674 927 heth->State = HAL_ETH_STATE_READY;
mbed_official 489:119543c9f674 928
mbed_official 489:119543c9f674 929 /* Process Unlocked */
mbed_official 489:119543c9f674 930 __HAL_UNLOCK(heth);
mbed_official 489:119543c9f674 931
mbed_official 489:119543c9f674 932 }
mbed_official 489:119543c9f674 933 /* Frame transmitted */
mbed_official 489:119543c9f674 934 else if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_T))
mbed_official 489:119543c9f674 935 {
mbed_official 489:119543c9f674 936 /* Transfer complete callback */
mbed_official 489:119543c9f674 937 HAL_ETH_TxCpltCallback(heth);
mbed_official 489:119543c9f674 938
mbed_official 489:119543c9f674 939 /* Clear the Eth DMA Tx IT pending bits */
mbed_official 489:119543c9f674 940 __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_T);
mbed_official 489:119543c9f674 941
mbed_official 489:119543c9f674 942 /* Set HAL State to Ready */
mbed_official 489:119543c9f674 943 heth->State = HAL_ETH_STATE_READY;
mbed_official 489:119543c9f674 944
mbed_official 489:119543c9f674 945 /* Process Unlocked */
mbed_official 489:119543c9f674 946 __HAL_UNLOCK(heth);
mbed_official 489:119543c9f674 947 }
mbed_official 489:119543c9f674 948
mbed_official 489:119543c9f674 949 /* Clear the interrupt flags */
mbed_official 489:119543c9f674 950 __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_NIS);
mbed_official 489:119543c9f674 951
mbed_official 489:119543c9f674 952 /* ETH DMA Error */
mbed_official 489:119543c9f674 953 if(__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_AIS))
mbed_official 489:119543c9f674 954 {
mbed_official 489:119543c9f674 955 /* Ethernet Error callback */
mbed_official 489:119543c9f674 956 HAL_ETH_ErrorCallback(heth);
mbed_official 489:119543c9f674 957
mbed_official 489:119543c9f674 958 /* Clear the interrupt flags */
mbed_official 489:119543c9f674 959 __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_FLAG_AIS);
mbed_official 489:119543c9f674 960
mbed_official 489:119543c9f674 961 /* Set HAL State to Ready */
mbed_official 489:119543c9f674 962 heth->State = HAL_ETH_STATE_READY;
mbed_official 489:119543c9f674 963
mbed_official 489:119543c9f674 964 /* Process Unlocked */
mbed_official 489:119543c9f674 965 __HAL_UNLOCK(heth);
mbed_official 489:119543c9f674 966 }
mbed_official 489:119543c9f674 967 }
mbed_official 489:119543c9f674 968
mbed_official 489:119543c9f674 969 /**
mbed_official 489:119543c9f674 970 * @brief Tx Transfer completed callbacks.
mbed_official 489:119543c9f674 971 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 489:119543c9f674 972 * the configuration information for ETHERNET module
mbed_official 489:119543c9f674 973 * @retval None
mbed_official 489:119543c9f674 974 */
mbed_official 489:119543c9f674 975 __weak void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth)
mbed_official 489:119543c9f674 976 {
mbed_official 489:119543c9f674 977 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 489:119543c9f674 978 the HAL_ETH_TxCpltCallback could be implemented in the user file
mbed_official 489:119543c9f674 979 */
mbed_official 489:119543c9f674 980 }
mbed_official 489:119543c9f674 981
mbed_official 489:119543c9f674 982 /**
mbed_official 489:119543c9f674 983 * @brief Rx Transfer completed callbacks.
mbed_official 489:119543c9f674 984 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 489:119543c9f674 985 * the configuration information for ETHERNET module
mbed_official 489:119543c9f674 986 * @retval None
mbed_official 489:119543c9f674 987 */
mbed_official 489:119543c9f674 988 __weak void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth)
mbed_official 489:119543c9f674 989 {
mbed_official 489:119543c9f674 990 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 489:119543c9f674 991 the HAL_ETH_TxCpltCallback could be implemented in the user file
mbed_official 489:119543c9f674 992 */
mbed_official 489:119543c9f674 993 }
mbed_official 489:119543c9f674 994
mbed_official 489:119543c9f674 995 /**
mbed_official 489:119543c9f674 996 * @brief Ethernet transfer error callbacks
mbed_official 489:119543c9f674 997 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 489:119543c9f674 998 * the configuration information for ETHERNET module
mbed_official 489:119543c9f674 999 * @retval None
mbed_official 489:119543c9f674 1000 */
mbed_official 489:119543c9f674 1001 __weak void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth)
mbed_official 489:119543c9f674 1002 {
mbed_official 489:119543c9f674 1003 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 489:119543c9f674 1004 the HAL_ETH_TxCpltCallback could be implemented in the user file
mbed_official 489:119543c9f674 1005 */
mbed_official 489:119543c9f674 1006 }
mbed_official 489:119543c9f674 1007
mbed_official 489:119543c9f674 1008 /**
mbed_official 489:119543c9f674 1009 * @brief Reads a PHY register
mbed_official 489:119543c9f674 1010 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 489:119543c9f674 1011 * the configuration information for ETHERNET module
mbed_official 489:119543c9f674 1012 * @param PHYReg: PHY register address, is the index of one of the 32 PHY register.
mbed_official 489:119543c9f674 1013 * This parameter can be one of the following values:
mbed_official 489:119543c9f674 1014 * PHY_BCR: Transceiver Basic Control Register,
mbed_official 489:119543c9f674 1015 * PHY_BSR: Transceiver Basic Status Register.
mbed_official 489:119543c9f674 1016 * More PHY register could be read depending on the used PHY
mbed_official 489:119543c9f674 1017 * @param RegValue: PHY register value
mbed_official 489:119543c9f674 1018 * @retval HAL status
mbed_official 489:119543c9f674 1019 */
mbed_official 489:119543c9f674 1020 HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue)
mbed_official 489:119543c9f674 1021 {
mbed_official 489:119543c9f674 1022 uint32_t tmpreg = 0;
mbed_official 489:119543c9f674 1023 uint32_t tickstart = 0;
mbed_official 489:119543c9f674 1024
mbed_official 489:119543c9f674 1025 /* Check parameters */
mbed_official 489:119543c9f674 1026 assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress));
mbed_official 489:119543c9f674 1027
mbed_official 489:119543c9f674 1028 /* Check the ETH peripheral state */
mbed_official 489:119543c9f674 1029 if(heth->State == HAL_ETH_STATE_BUSY_RD)
mbed_official 489:119543c9f674 1030 {
mbed_official 489:119543c9f674 1031 return HAL_BUSY;
mbed_official 489:119543c9f674 1032 }
mbed_official 489:119543c9f674 1033 /* Set ETH HAL State to BUSY_RD */
mbed_official 489:119543c9f674 1034 heth->State = HAL_ETH_STATE_BUSY_RD;
mbed_official 489:119543c9f674 1035
mbed_official 489:119543c9f674 1036 /* Get the ETHERNET MACMIIAR value */
mbed_official 489:119543c9f674 1037 tmpreg = heth->Instance->MACMIIAR;
mbed_official 489:119543c9f674 1038
mbed_official 489:119543c9f674 1039 /* Keep only the CSR Clock Range CR[2:0] bits value */
mbed_official 489:119543c9f674 1040 tmpreg &= ~ETH_MACMIIAR_CR_MASK;
mbed_official 489:119543c9f674 1041
mbed_official 489:119543c9f674 1042 /* Prepare the MII address register value */
mbed_official 489:119543c9f674 1043 tmpreg |=(((uint32_t)heth->Init.PhyAddress << 11) & ETH_MACMIIAR_PA); /* Set the PHY device address */
mbed_official 489:119543c9f674 1044 tmpreg |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR); /* Set the PHY register address */
mbed_official 489:119543c9f674 1045 tmpreg &= ~ETH_MACMIIAR_MW; /* Set the read mode */
mbed_official 489:119543c9f674 1046 tmpreg |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */
mbed_official 489:119543c9f674 1047
mbed_official 489:119543c9f674 1048 /* Write the result value into the MII Address register */
mbed_official 489:119543c9f674 1049 heth->Instance->MACMIIAR = tmpreg;
mbed_official 489:119543c9f674 1050
mbed_official 489:119543c9f674 1051 /* Get tick */
mbed_official 489:119543c9f674 1052 tickstart = HAL_GetTick();
mbed_official 489:119543c9f674 1053
mbed_official 489:119543c9f674 1054 /* Check for the Busy flag */
mbed_official 489:119543c9f674 1055 while((tmpreg & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB)
mbed_official 489:119543c9f674 1056 {
mbed_official 489:119543c9f674 1057 /* Check for the Timeout */
mbed_official 489:119543c9f674 1058 if((HAL_GetTick() - tickstart ) > PHY_READ_TO)
mbed_official 489:119543c9f674 1059 {
mbed_official 489:119543c9f674 1060 heth->State= HAL_ETH_STATE_READY;
mbed_official 489:119543c9f674 1061
mbed_official 489:119543c9f674 1062 /* Process Unlocked */
mbed_official 489:119543c9f674 1063 __HAL_UNLOCK(heth);
mbed_official 489:119543c9f674 1064
mbed_official 489:119543c9f674 1065 return HAL_TIMEOUT;
mbed_official 489:119543c9f674 1066 }
mbed_official 489:119543c9f674 1067
mbed_official 489:119543c9f674 1068 tmpreg = heth->Instance->MACMIIAR;
mbed_official 489:119543c9f674 1069 }
mbed_official 489:119543c9f674 1070
mbed_official 489:119543c9f674 1071 /* Get MACMIIDR value */
mbed_official 489:119543c9f674 1072 *RegValue = (uint16_t)(heth->Instance->MACMIIDR);
mbed_official 489:119543c9f674 1073
mbed_official 489:119543c9f674 1074 /* Set ETH HAL State to READY */
mbed_official 489:119543c9f674 1075 heth->State = HAL_ETH_STATE_READY;
mbed_official 489:119543c9f674 1076
mbed_official 489:119543c9f674 1077 /* Return function status */
mbed_official 489:119543c9f674 1078 return HAL_OK;
mbed_official 489:119543c9f674 1079 }
mbed_official 489:119543c9f674 1080
mbed_official 489:119543c9f674 1081 /**
mbed_official 489:119543c9f674 1082 * @brief Writes to a PHY register.
mbed_official 489:119543c9f674 1083 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 489:119543c9f674 1084 * the configuration information for ETHERNET module
mbed_official 489:119543c9f674 1085 * @param PHYReg: PHY register address, is the index of one of the 32 PHY register.
mbed_official 489:119543c9f674 1086 * This parameter can be one of the following values:
mbed_official 489:119543c9f674 1087 * PHY_BCR: Transceiver Control Register.
mbed_official 489:119543c9f674 1088 * More PHY register could be written depending on the used PHY
mbed_official 489:119543c9f674 1089 * @param RegValue: the value to write
mbed_official 489:119543c9f674 1090 * @retval HAL status
mbed_official 489:119543c9f674 1091 */
mbed_official 489:119543c9f674 1092 HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue)
mbed_official 489:119543c9f674 1093 {
mbed_official 489:119543c9f674 1094 uint32_t tmpreg = 0;
mbed_official 489:119543c9f674 1095 uint32_t tickstart = 0;
mbed_official 489:119543c9f674 1096
mbed_official 489:119543c9f674 1097 /* Check parameters */
mbed_official 489:119543c9f674 1098 assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress));
mbed_official 489:119543c9f674 1099
mbed_official 489:119543c9f674 1100 /* Check the ETH peripheral state */
mbed_official 489:119543c9f674 1101 if(heth->State == HAL_ETH_STATE_BUSY_WR)
mbed_official 489:119543c9f674 1102 {
mbed_official 489:119543c9f674 1103 return HAL_BUSY;
mbed_official 489:119543c9f674 1104 }
mbed_official 489:119543c9f674 1105 /* Set ETH HAL State to BUSY_WR */
mbed_official 489:119543c9f674 1106 heth->State = HAL_ETH_STATE_BUSY_WR;
mbed_official 489:119543c9f674 1107
mbed_official 489:119543c9f674 1108 /* Get the ETHERNET MACMIIAR value */
mbed_official 489:119543c9f674 1109 tmpreg = heth->Instance->MACMIIAR;
mbed_official 489:119543c9f674 1110
mbed_official 489:119543c9f674 1111 /* Keep only the CSR Clock Range CR[2:0] bits value */
mbed_official 489:119543c9f674 1112 tmpreg &= ~ETH_MACMIIAR_CR_MASK;
mbed_official 489:119543c9f674 1113
mbed_official 489:119543c9f674 1114 /* Prepare the MII register address value */
mbed_official 489:119543c9f674 1115 tmpreg |=(((uint32_t)heth->Init.PhyAddress<<11) & ETH_MACMIIAR_PA); /* Set the PHY device address */
mbed_official 489:119543c9f674 1116 tmpreg |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR); /* Set the PHY register address */
mbed_official 489:119543c9f674 1117 tmpreg |= ETH_MACMIIAR_MW; /* Set the write mode */
mbed_official 489:119543c9f674 1118 tmpreg |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */
mbed_official 489:119543c9f674 1119
mbed_official 489:119543c9f674 1120 /* Give the value to the MII data register */
mbed_official 489:119543c9f674 1121 heth->Instance->MACMIIDR = (uint16_t)RegValue;
mbed_official 489:119543c9f674 1122
mbed_official 489:119543c9f674 1123 /* Write the result value into the MII Address register */
mbed_official 489:119543c9f674 1124 heth->Instance->MACMIIAR = tmpreg;
mbed_official 489:119543c9f674 1125
mbed_official 489:119543c9f674 1126 /* Get tick */
mbed_official 489:119543c9f674 1127 tickstart = HAL_GetTick();
mbed_official 489:119543c9f674 1128
mbed_official 489:119543c9f674 1129 /* Check for the Busy flag */
mbed_official 489:119543c9f674 1130 while((tmpreg & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB)
mbed_official 489:119543c9f674 1131 {
mbed_official 489:119543c9f674 1132 /* Check for the Timeout */
mbed_official 489:119543c9f674 1133 if((HAL_GetTick() - tickstart ) > PHY_WRITE_TO)
mbed_official 489:119543c9f674 1134 {
mbed_official 489:119543c9f674 1135 heth->State= HAL_ETH_STATE_READY;
mbed_official 489:119543c9f674 1136
mbed_official 489:119543c9f674 1137 /* Process Unlocked */
mbed_official 489:119543c9f674 1138 __HAL_UNLOCK(heth);
mbed_official 489:119543c9f674 1139
mbed_official 489:119543c9f674 1140 return HAL_TIMEOUT;
mbed_official 489:119543c9f674 1141 }
mbed_official 489:119543c9f674 1142
mbed_official 489:119543c9f674 1143 tmpreg = heth->Instance->MACMIIAR;
mbed_official 489:119543c9f674 1144 }
mbed_official 489:119543c9f674 1145
mbed_official 489:119543c9f674 1146 /* Set ETH HAL State to READY */
mbed_official 489:119543c9f674 1147 heth->State = HAL_ETH_STATE_READY;
mbed_official 489:119543c9f674 1148
mbed_official 489:119543c9f674 1149 /* Return function status */
mbed_official 489:119543c9f674 1150 return HAL_OK;
mbed_official 489:119543c9f674 1151 }
mbed_official 489:119543c9f674 1152
mbed_official 489:119543c9f674 1153 /**
mbed_official 489:119543c9f674 1154 * @}
mbed_official 489:119543c9f674 1155 */
mbed_official 489:119543c9f674 1156
mbed_official 489:119543c9f674 1157 /** @defgroup ETH_Exported_Functions_Group3 Peripheral Control functions
mbed_official 489:119543c9f674 1158 * @brief Peripheral Control functions
mbed_official 489:119543c9f674 1159 *
mbed_official 489:119543c9f674 1160 @verbatim
mbed_official 489:119543c9f674 1161 ===============================================================================
mbed_official 489:119543c9f674 1162 ##### Peripheral Control functions #####
mbed_official 489:119543c9f674 1163 ===============================================================================
mbed_official 489:119543c9f674 1164 [..] This section provides functions allowing to:
mbed_official 489:119543c9f674 1165 (+) Enable MAC and DMA transmission and reception.
mbed_official 489:119543c9f674 1166 HAL_ETH_Start();
mbed_official 489:119543c9f674 1167 (+) Disable MAC and DMA transmission and reception.
mbed_official 489:119543c9f674 1168 HAL_ETH_Stop();
mbed_official 489:119543c9f674 1169 (+) Set the MAC configuration in runtime mode
mbed_official 489:119543c9f674 1170 HAL_ETH_ConfigMAC();
mbed_official 489:119543c9f674 1171 (+) Set the DMA configuration in runtime mode
mbed_official 489:119543c9f674 1172 HAL_ETH_ConfigDMA();
mbed_official 489:119543c9f674 1173
mbed_official 489:119543c9f674 1174 @endverbatim
mbed_official 489:119543c9f674 1175 * @{
mbed_official 489:119543c9f674 1176 */
mbed_official 489:119543c9f674 1177
mbed_official 489:119543c9f674 1178 /**
mbed_official 489:119543c9f674 1179 * @brief Enables Ethernet MAC and DMA reception/transmission
mbed_official 489:119543c9f674 1180 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 489:119543c9f674 1181 * the configuration information for ETHERNET module
mbed_official 489:119543c9f674 1182 * @retval HAL status
mbed_official 489:119543c9f674 1183 */
mbed_official 489:119543c9f674 1184 HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth)
mbed_official 489:119543c9f674 1185 {
mbed_official 489:119543c9f674 1186 /* Process Locked */
mbed_official 489:119543c9f674 1187 __HAL_LOCK(heth);
mbed_official 489:119543c9f674 1188
mbed_official 489:119543c9f674 1189 /* Set the ETH peripheral state to BUSY */
mbed_official 489:119543c9f674 1190 heth->State = HAL_ETH_STATE_BUSY;
mbed_official 489:119543c9f674 1191
mbed_official 489:119543c9f674 1192 /* Enable transmit state machine of the MAC for transmission on the MII */
mbed_official 489:119543c9f674 1193 ETH_MACTransmissionEnable(heth);
mbed_official 489:119543c9f674 1194
mbed_official 489:119543c9f674 1195 /* Enable receive state machine of the MAC for reception from the MII */
mbed_official 489:119543c9f674 1196 ETH_MACReceptionEnable(heth);
mbed_official 489:119543c9f674 1197
mbed_official 489:119543c9f674 1198 /* Flush Transmit FIFO */
mbed_official 489:119543c9f674 1199 ETH_FlushTransmitFIFO(heth);
mbed_official 489:119543c9f674 1200
mbed_official 489:119543c9f674 1201 /* Start DMA transmission */
mbed_official 489:119543c9f674 1202 ETH_DMATransmissionEnable(heth);
mbed_official 489:119543c9f674 1203
mbed_official 489:119543c9f674 1204 /* Start DMA reception */
mbed_official 489:119543c9f674 1205 ETH_DMAReceptionEnable(heth);
mbed_official 489:119543c9f674 1206
mbed_official 489:119543c9f674 1207 /* Set the ETH state to READY*/
mbed_official 489:119543c9f674 1208 heth->State= HAL_ETH_STATE_READY;
mbed_official 489:119543c9f674 1209
mbed_official 489:119543c9f674 1210 /* Process Unlocked */
mbed_official 489:119543c9f674 1211 __HAL_UNLOCK(heth);
mbed_official 489:119543c9f674 1212
mbed_official 489:119543c9f674 1213 /* Return function status */
mbed_official 489:119543c9f674 1214 return HAL_OK;
mbed_official 489:119543c9f674 1215 }
mbed_official 489:119543c9f674 1216
mbed_official 489:119543c9f674 1217 /**
mbed_official 489:119543c9f674 1218 * @brief Stop Ethernet MAC and DMA reception/transmission
mbed_official 489:119543c9f674 1219 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 489:119543c9f674 1220 * the configuration information for ETHERNET module
mbed_official 489:119543c9f674 1221 * @retval HAL status
mbed_official 489:119543c9f674 1222 */
mbed_official 489:119543c9f674 1223 HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth)
mbed_official 489:119543c9f674 1224 {
mbed_official 489:119543c9f674 1225 /* Process Locked */
mbed_official 489:119543c9f674 1226 __HAL_LOCK(heth);
mbed_official 489:119543c9f674 1227
mbed_official 489:119543c9f674 1228 /* Set the ETH peripheral state to BUSY */
mbed_official 489:119543c9f674 1229 heth->State = HAL_ETH_STATE_BUSY;
mbed_official 489:119543c9f674 1230
mbed_official 489:119543c9f674 1231 /* Stop DMA transmission */
mbed_official 489:119543c9f674 1232 ETH_DMATransmissionDisable(heth);
mbed_official 489:119543c9f674 1233
mbed_official 489:119543c9f674 1234 /* Stop DMA reception */
mbed_official 489:119543c9f674 1235 ETH_DMAReceptionDisable(heth);
mbed_official 489:119543c9f674 1236
mbed_official 489:119543c9f674 1237 /* Disable receive state machine of the MAC for reception from the MII */
mbed_official 489:119543c9f674 1238 ETH_MACReceptionDisable(heth);
mbed_official 489:119543c9f674 1239
mbed_official 489:119543c9f674 1240 /* Flush Transmit FIFO */
mbed_official 489:119543c9f674 1241 ETH_FlushTransmitFIFO(heth);
mbed_official 489:119543c9f674 1242
mbed_official 489:119543c9f674 1243 /* Disable transmit state machine of the MAC for transmission on the MII */
mbed_official 489:119543c9f674 1244 ETH_MACTransmissionDisable(heth);
mbed_official 489:119543c9f674 1245
mbed_official 489:119543c9f674 1246 /* Set the ETH state*/
mbed_official 489:119543c9f674 1247 heth->State = HAL_ETH_STATE_READY;
mbed_official 489:119543c9f674 1248
mbed_official 489:119543c9f674 1249 /* Process Unlocked */
mbed_official 489:119543c9f674 1250 __HAL_UNLOCK(heth);
mbed_official 489:119543c9f674 1251
mbed_official 489:119543c9f674 1252 /* Return function status */
mbed_official 489:119543c9f674 1253 return HAL_OK;
mbed_official 489:119543c9f674 1254 }
mbed_official 489:119543c9f674 1255
mbed_official 489:119543c9f674 1256 /**
mbed_official 489:119543c9f674 1257 * @brief Set ETH MAC Configuration.
mbed_official 489:119543c9f674 1258 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 489:119543c9f674 1259 * the configuration information for ETHERNET module
mbed_official 489:119543c9f674 1260 * @param macconf: MAC Configuration structure
mbed_official 489:119543c9f674 1261 * @retval HAL status
mbed_official 489:119543c9f674 1262 */
mbed_official 489:119543c9f674 1263 HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf)
mbed_official 489:119543c9f674 1264 {
mbed_official 489:119543c9f674 1265 uint32_t tmpreg = 0;
mbed_official 489:119543c9f674 1266
mbed_official 489:119543c9f674 1267 /* Process Locked */
mbed_official 489:119543c9f674 1268 __HAL_LOCK(heth);
mbed_official 489:119543c9f674 1269
mbed_official 489:119543c9f674 1270 /* Set the ETH peripheral state to BUSY */
mbed_official 489:119543c9f674 1271 heth->State= HAL_ETH_STATE_BUSY;
mbed_official 489:119543c9f674 1272
mbed_official 489:119543c9f674 1273 assert_param(IS_ETH_SPEED(heth->Init.Speed));
mbed_official 489:119543c9f674 1274 assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode));
mbed_official 489:119543c9f674 1275
mbed_official 489:119543c9f674 1276 if (macconf != NULL)
mbed_official 489:119543c9f674 1277 {
mbed_official 489:119543c9f674 1278 /* Check the parameters */
mbed_official 489:119543c9f674 1279 assert_param(IS_ETH_WATCHDOG(macconf->Watchdog));
mbed_official 489:119543c9f674 1280 assert_param(IS_ETH_JABBER(macconf->Jabber));
mbed_official 489:119543c9f674 1281 assert_param(IS_ETH_INTER_FRAME_GAP(macconf->InterFrameGap));
mbed_official 489:119543c9f674 1282 assert_param(IS_ETH_CARRIER_SENSE(macconf->CarrierSense));
mbed_official 489:119543c9f674 1283 assert_param(IS_ETH_RECEIVE_OWN(macconf->ReceiveOwn));
mbed_official 489:119543c9f674 1284 assert_param(IS_ETH_LOOPBACK_MODE(macconf->LoopbackMode));
mbed_official 489:119543c9f674 1285 assert_param(IS_ETH_CHECKSUM_OFFLOAD(macconf->ChecksumOffload));
mbed_official 489:119543c9f674 1286 assert_param(IS_ETH_RETRY_TRANSMISSION(macconf->RetryTransmission));
mbed_official 489:119543c9f674 1287 assert_param(IS_ETH_AUTOMATIC_PADCRC_STRIP(macconf->AutomaticPadCRCStrip));
mbed_official 489:119543c9f674 1288 assert_param(IS_ETH_BACKOFF_LIMIT(macconf->BackOffLimit));
mbed_official 489:119543c9f674 1289 assert_param(IS_ETH_DEFERRAL_CHECK(macconf->DeferralCheck));
mbed_official 489:119543c9f674 1290 assert_param(IS_ETH_RECEIVE_ALL(macconf->ReceiveAll));
mbed_official 489:119543c9f674 1291 assert_param(IS_ETH_SOURCE_ADDR_FILTER(macconf->SourceAddrFilter));
mbed_official 489:119543c9f674 1292 assert_param(IS_ETH_CONTROL_FRAMES(macconf->PassControlFrames));
mbed_official 489:119543c9f674 1293 assert_param(IS_ETH_BROADCAST_FRAMES_RECEPTION(macconf->BroadcastFramesReception));
mbed_official 489:119543c9f674 1294 assert_param(IS_ETH_DESTINATION_ADDR_FILTER(macconf->DestinationAddrFilter));
mbed_official 489:119543c9f674 1295 assert_param(IS_ETH_PROMISCUOUS_MODE(macconf->PromiscuousMode));
mbed_official 489:119543c9f674 1296 assert_param(IS_ETH_MULTICAST_FRAMES_FILTER(macconf->MulticastFramesFilter));
mbed_official 489:119543c9f674 1297 assert_param(IS_ETH_UNICAST_FRAMES_FILTER(macconf->UnicastFramesFilter));
mbed_official 489:119543c9f674 1298 assert_param(IS_ETH_PAUSE_TIME(macconf->PauseTime));
mbed_official 489:119543c9f674 1299 assert_param(IS_ETH_ZEROQUANTA_PAUSE(macconf->ZeroQuantaPause));
mbed_official 489:119543c9f674 1300 assert_param(IS_ETH_PAUSE_LOW_THRESHOLD(macconf->PauseLowThreshold));
mbed_official 489:119543c9f674 1301 assert_param(IS_ETH_UNICAST_PAUSE_FRAME_DETECT(macconf->UnicastPauseFrameDetect));
mbed_official 489:119543c9f674 1302 assert_param(IS_ETH_RECEIVE_FLOWCONTROL(macconf->ReceiveFlowControl));
mbed_official 489:119543c9f674 1303 assert_param(IS_ETH_TRANSMIT_FLOWCONTROL(macconf->TransmitFlowControl));
mbed_official 489:119543c9f674 1304 assert_param(IS_ETH_VLAN_TAG_COMPARISON(macconf->VLANTagComparison));
mbed_official 489:119543c9f674 1305 assert_param(IS_ETH_VLAN_TAG_IDENTIFIER(macconf->VLANTagIdentifier));
mbed_official 489:119543c9f674 1306
mbed_official 489:119543c9f674 1307 /*------------------------ ETHERNET MACCR Configuration --------------------*/
mbed_official 489:119543c9f674 1308 /* Get the ETHERNET MACCR value */
mbed_official 489:119543c9f674 1309 tmpreg = (heth->Instance)->MACCR;
mbed_official 489:119543c9f674 1310 /* Clear WD, PCE, PS, TE and RE bits */
mbed_official 489:119543c9f674 1311 tmpreg &= ETH_MACCR_CLEAR_MASK;
mbed_official 489:119543c9f674 1312
mbed_official 489:119543c9f674 1313 tmpreg |= (uint32_t)(macconf->Watchdog |
mbed_official 489:119543c9f674 1314 macconf->Jabber |
mbed_official 489:119543c9f674 1315 macconf->InterFrameGap |
mbed_official 489:119543c9f674 1316 macconf->CarrierSense |
mbed_official 489:119543c9f674 1317 (heth->Init).Speed |
mbed_official 489:119543c9f674 1318 macconf->ReceiveOwn |
mbed_official 489:119543c9f674 1319 macconf->LoopbackMode |
mbed_official 489:119543c9f674 1320 (heth->Init).DuplexMode |
mbed_official 489:119543c9f674 1321 macconf->ChecksumOffload |
mbed_official 489:119543c9f674 1322 macconf->RetryTransmission |
mbed_official 489:119543c9f674 1323 macconf->AutomaticPadCRCStrip |
mbed_official 489:119543c9f674 1324 macconf->BackOffLimit |
mbed_official 489:119543c9f674 1325 macconf->DeferralCheck);
mbed_official 489:119543c9f674 1326
mbed_official 489:119543c9f674 1327 /* Write to ETHERNET MACCR */
mbed_official 489:119543c9f674 1328 (heth->Instance)->MACCR = (uint32_t)tmpreg;
mbed_official 489:119543c9f674 1329
mbed_official 489:119543c9f674 1330 /* Wait until the write operation will be taken into account :
mbed_official 489:119543c9f674 1331 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 489:119543c9f674 1332 tmpreg = (heth->Instance)->MACCR;
mbed_official 489:119543c9f674 1333 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 489:119543c9f674 1334 (heth->Instance)->MACCR = tmpreg;
mbed_official 489:119543c9f674 1335
mbed_official 489:119543c9f674 1336 /*----------------------- ETHERNET MACFFR Configuration --------------------*/
mbed_official 489:119543c9f674 1337 /* Write to ETHERNET MACFFR */
mbed_official 489:119543c9f674 1338 (heth->Instance)->MACFFR = (uint32_t)(macconf->ReceiveAll |
mbed_official 489:119543c9f674 1339 macconf->SourceAddrFilter |
mbed_official 489:119543c9f674 1340 macconf->PassControlFrames |
mbed_official 489:119543c9f674 1341 macconf->BroadcastFramesReception |
mbed_official 489:119543c9f674 1342 macconf->DestinationAddrFilter |
mbed_official 489:119543c9f674 1343 macconf->PromiscuousMode |
mbed_official 489:119543c9f674 1344 macconf->MulticastFramesFilter |
mbed_official 489:119543c9f674 1345 macconf->UnicastFramesFilter);
mbed_official 489:119543c9f674 1346
mbed_official 489:119543c9f674 1347 /* Wait until the write operation will be taken into account :
mbed_official 489:119543c9f674 1348 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 489:119543c9f674 1349 tmpreg = (heth->Instance)->MACFFR;
mbed_official 489:119543c9f674 1350 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 489:119543c9f674 1351 (heth->Instance)->MACFFR = tmpreg;
mbed_official 489:119543c9f674 1352
mbed_official 489:119543c9f674 1353 /*--------------- ETHERNET MACHTHR and MACHTLR Configuration ---------------*/
mbed_official 489:119543c9f674 1354 /* Write to ETHERNET MACHTHR */
mbed_official 489:119543c9f674 1355 (heth->Instance)->MACHTHR = (uint32_t)macconf->HashTableHigh;
mbed_official 489:119543c9f674 1356
mbed_official 489:119543c9f674 1357 /* Write to ETHERNET MACHTLR */
mbed_official 489:119543c9f674 1358 (heth->Instance)->MACHTLR = (uint32_t)macconf->HashTableLow;
mbed_official 489:119543c9f674 1359 /*----------------------- ETHERNET MACFCR Configuration --------------------*/
mbed_official 489:119543c9f674 1360
mbed_official 489:119543c9f674 1361 /* Get the ETHERNET MACFCR value */
mbed_official 489:119543c9f674 1362 tmpreg = (heth->Instance)->MACFCR;
mbed_official 489:119543c9f674 1363 /* Clear xx bits */
mbed_official 489:119543c9f674 1364 tmpreg &= ETH_MACFCR_CLEAR_MASK;
mbed_official 489:119543c9f674 1365
mbed_official 489:119543c9f674 1366 tmpreg |= (uint32_t)((macconf->PauseTime << 16) |
mbed_official 489:119543c9f674 1367 macconf->ZeroQuantaPause |
mbed_official 489:119543c9f674 1368 macconf->PauseLowThreshold |
mbed_official 489:119543c9f674 1369 macconf->UnicastPauseFrameDetect |
mbed_official 489:119543c9f674 1370 macconf->ReceiveFlowControl |
mbed_official 489:119543c9f674 1371 macconf->TransmitFlowControl);
mbed_official 489:119543c9f674 1372
mbed_official 489:119543c9f674 1373 /* Write to ETHERNET MACFCR */
mbed_official 489:119543c9f674 1374 (heth->Instance)->MACFCR = (uint32_t)tmpreg;
mbed_official 489:119543c9f674 1375
mbed_official 489:119543c9f674 1376 /* Wait until the write operation will be taken into account :
mbed_official 489:119543c9f674 1377 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 489:119543c9f674 1378 tmpreg = (heth->Instance)->MACFCR;
mbed_official 489:119543c9f674 1379 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 489:119543c9f674 1380 (heth->Instance)->MACFCR = tmpreg;
mbed_official 489:119543c9f674 1381
mbed_official 489:119543c9f674 1382 /*----------------------- ETHERNET MACVLANTR Configuration -----------------*/
mbed_official 489:119543c9f674 1383 (heth->Instance)->MACVLANTR = (uint32_t)(macconf->VLANTagComparison |
mbed_official 489:119543c9f674 1384 macconf->VLANTagIdentifier);
mbed_official 489:119543c9f674 1385
mbed_official 489:119543c9f674 1386 /* Wait until the write operation will be taken into account :
mbed_official 489:119543c9f674 1387 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 489:119543c9f674 1388 tmpreg = (heth->Instance)->MACVLANTR;
mbed_official 489:119543c9f674 1389 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 489:119543c9f674 1390 (heth->Instance)->MACVLANTR = tmpreg;
mbed_official 489:119543c9f674 1391 }
mbed_official 489:119543c9f674 1392 else /* macconf == NULL : here we just configure Speed and Duplex mode */
mbed_official 489:119543c9f674 1393 {
mbed_official 489:119543c9f674 1394 /*------------------------ ETHERNET MACCR Configuration --------------------*/
mbed_official 489:119543c9f674 1395 /* Get the ETHERNET MACCR value */
mbed_official 489:119543c9f674 1396 tmpreg = (heth->Instance)->MACCR;
mbed_official 489:119543c9f674 1397
mbed_official 489:119543c9f674 1398 /* Clear FES and DM bits */
mbed_official 489:119543c9f674 1399 tmpreg &= ~((uint32_t)0x00004800);
mbed_official 489:119543c9f674 1400
mbed_official 489:119543c9f674 1401 tmpreg |= (uint32_t)(heth->Init.Speed | heth->Init.DuplexMode);
mbed_official 489:119543c9f674 1402
mbed_official 489:119543c9f674 1403 /* Write to ETHERNET MACCR */
mbed_official 489:119543c9f674 1404 (heth->Instance)->MACCR = (uint32_t)tmpreg;
mbed_official 489:119543c9f674 1405
mbed_official 489:119543c9f674 1406 /* Wait until the write operation will be taken into account:
mbed_official 489:119543c9f674 1407 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 489:119543c9f674 1408 tmpreg = (heth->Instance)->MACCR;
mbed_official 489:119543c9f674 1409 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 489:119543c9f674 1410 (heth->Instance)->MACCR = tmpreg;
mbed_official 489:119543c9f674 1411 }
mbed_official 489:119543c9f674 1412
mbed_official 489:119543c9f674 1413 /* Set the ETH state to Ready */
mbed_official 489:119543c9f674 1414 heth->State= HAL_ETH_STATE_READY;
mbed_official 489:119543c9f674 1415
mbed_official 489:119543c9f674 1416 /* Process Unlocked */
mbed_official 489:119543c9f674 1417 __HAL_UNLOCK(heth);
mbed_official 489:119543c9f674 1418
mbed_official 489:119543c9f674 1419 /* Return function status */
mbed_official 489:119543c9f674 1420 return HAL_OK;
mbed_official 489:119543c9f674 1421 }
mbed_official 489:119543c9f674 1422
mbed_official 489:119543c9f674 1423 /**
mbed_official 489:119543c9f674 1424 * @brief Sets ETH DMA Configuration.
mbed_official 489:119543c9f674 1425 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 489:119543c9f674 1426 * the configuration information for ETHERNET module
mbed_official 489:119543c9f674 1427 * @param dmaconf: DMA Configuration structure
mbed_official 489:119543c9f674 1428 * @retval HAL status
mbed_official 489:119543c9f674 1429 */
mbed_official 489:119543c9f674 1430 HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf)
mbed_official 489:119543c9f674 1431 {
mbed_official 489:119543c9f674 1432 uint32_t tmpreg = 0;
mbed_official 489:119543c9f674 1433
mbed_official 489:119543c9f674 1434 /* Process Locked */
mbed_official 489:119543c9f674 1435 __HAL_LOCK(heth);
mbed_official 489:119543c9f674 1436
mbed_official 489:119543c9f674 1437 /* Set the ETH peripheral state to BUSY */
mbed_official 489:119543c9f674 1438 heth->State= HAL_ETH_STATE_BUSY;
mbed_official 489:119543c9f674 1439
mbed_official 489:119543c9f674 1440 /* Check parameters */
mbed_official 489:119543c9f674 1441 assert_param(IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(dmaconf->DropTCPIPChecksumErrorFrame));
mbed_official 489:119543c9f674 1442 assert_param(IS_ETH_RECEIVE_STORE_FORWARD(dmaconf->ReceiveStoreForward));
mbed_official 489:119543c9f674 1443 assert_param(IS_ETH_FLUSH_RECEIVE_FRAME(dmaconf->FlushReceivedFrame));
mbed_official 489:119543c9f674 1444 assert_param(IS_ETH_TRANSMIT_STORE_FORWARD(dmaconf->TransmitStoreForward));
mbed_official 489:119543c9f674 1445 assert_param(IS_ETH_TRANSMIT_THRESHOLD_CONTROL(dmaconf->TransmitThresholdControl));
mbed_official 489:119543c9f674 1446 assert_param(IS_ETH_FORWARD_ERROR_FRAMES(dmaconf->ForwardErrorFrames));
mbed_official 489:119543c9f674 1447 assert_param(IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(dmaconf->ForwardUndersizedGoodFrames));
mbed_official 489:119543c9f674 1448 assert_param(IS_ETH_RECEIVE_THRESHOLD_CONTROL(dmaconf->ReceiveThresholdControl));
mbed_official 489:119543c9f674 1449 assert_param(IS_ETH_SECOND_FRAME_OPERATE(dmaconf->SecondFrameOperate));
mbed_official 489:119543c9f674 1450 assert_param(IS_ETH_ADDRESS_ALIGNED_BEATS(dmaconf->AddressAlignedBeats));
mbed_official 489:119543c9f674 1451 assert_param(IS_ETH_FIXED_BURST(dmaconf->FixedBurst));
mbed_official 489:119543c9f674 1452 assert_param(IS_ETH_RXDMA_BURST_LENGTH(dmaconf->RxDMABurstLength));
mbed_official 489:119543c9f674 1453 assert_param(IS_ETH_TXDMA_BURST_LENGTH(dmaconf->TxDMABurstLength));
mbed_official 489:119543c9f674 1454 assert_param(IS_ETH_DMA_DESC_SKIP_LENGTH(dmaconf->DescriptorSkipLength));
mbed_official 489:119543c9f674 1455 assert_param(IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(dmaconf->DMAArbitration));
mbed_official 489:119543c9f674 1456
mbed_official 489:119543c9f674 1457 /*----------------------- ETHERNET DMAOMR Configuration --------------------*/
mbed_official 489:119543c9f674 1458 /* Get the ETHERNET DMAOMR value */
mbed_official 489:119543c9f674 1459 tmpreg = (heth->Instance)->DMAOMR;
mbed_official 489:119543c9f674 1460 /* Clear xx bits */
mbed_official 489:119543c9f674 1461 tmpreg &= ETH_DMAOMR_CLEAR_MASK;
mbed_official 489:119543c9f674 1462
mbed_official 489:119543c9f674 1463 tmpreg |= (uint32_t)(dmaconf->DropTCPIPChecksumErrorFrame |
mbed_official 489:119543c9f674 1464 dmaconf->ReceiveStoreForward |
mbed_official 489:119543c9f674 1465 dmaconf->FlushReceivedFrame |
mbed_official 489:119543c9f674 1466 dmaconf->TransmitStoreForward |
mbed_official 489:119543c9f674 1467 dmaconf->TransmitThresholdControl |
mbed_official 489:119543c9f674 1468 dmaconf->ForwardErrorFrames |
mbed_official 489:119543c9f674 1469 dmaconf->ForwardUndersizedGoodFrames |
mbed_official 489:119543c9f674 1470 dmaconf->ReceiveThresholdControl |
mbed_official 489:119543c9f674 1471 dmaconf->SecondFrameOperate);
mbed_official 489:119543c9f674 1472
mbed_official 489:119543c9f674 1473 /* Write to ETHERNET DMAOMR */
mbed_official 489:119543c9f674 1474 (heth->Instance)->DMAOMR = (uint32_t)tmpreg;
mbed_official 489:119543c9f674 1475
mbed_official 489:119543c9f674 1476 /* Wait until the write operation will be taken into account:
mbed_official 489:119543c9f674 1477 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 489:119543c9f674 1478 tmpreg = (heth->Instance)->DMAOMR;
mbed_official 489:119543c9f674 1479 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 489:119543c9f674 1480 (heth->Instance)->DMAOMR = tmpreg;
mbed_official 489:119543c9f674 1481
mbed_official 489:119543c9f674 1482 /*----------------------- ETHERNET DMABMR Configuration --------------------*/
mbed_official 489:119543c9f674 1483 (heth->Instance)->DMABMR = (uint32_t)(dmaconf->AddressAlignedBeats |
mbed_official 489:119543c9f674 1484 dmaconf->FixedBurst |
mbed_official 489:119543c9f674 1485 dmaconf->RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */
mbed_official 489:119543c9f674 1486 dmaconf->TxDMABurstLength |
mbed_official 489:119543c9f674 1487 (dmaconf->DescriptorSkipLength << 2) |
mbed_official 489:119543c9f674 1488 dmaconf->DMAArbitration |
mbed_official 489:119543c9f674 1489 ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */
mbed_official 489:119543c9f674 1490
mbed_official 489:119543c9f674 1491 /* Wait until the write operation will be taken into account:
mbed_official 489:119543c9f674 1492 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 489:119543c9f674 1493 tmpreg = (heth->Instance)->DMABMR;
mbed_official 489:119543c9f674 1494 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 489:119543c9f674 1495 (heth->Instance)->DMABMR = tmpreg;
mbed_official 489:119543c9f674 1496
mbed_official 489:119543c9f674 1497 /* Set the ETH state to Ready */
mbed_official 489:119543c9f674 1498 heth->State= HAL_ETH_STATE_READY;
mbed_official 489:119543c9f674 1499
mbed_official 489:119543c9f674 1500 /* Process Unlocked */
mbed_official 489:119543c9f674 1501 __HAL_UNLOCK(heth);
mbed_official 489:119543c9f674 1502
mbed_official 489:119543c9f674 1503 /* Return function status */
mbed_official 489:119543c9f674 1504 return HAL_OK;
mbed_official 489:119543c9f674 1505 }
mbed_official 489:119543c9f674 1506
mbed_official 489:119543c9f674 1507 /**
mbed_official 489:119543c9f674 1508 * @}
mbed_official 489:119543c9f674 1509 */
mbed_official 489:119543c9f674 1510
mbed_official 489:119543c9f674 1511 /** @defgroup ETH_Exported_Functions_Group4 Peripheral State functions
mbed_official 489:119543c9f674 1512 * @brief Peripheral State functions
mbed_official 489:119543c9f674 1513 *
mbed_official 489:119543c9f674 1514 @verbatim
mbed_official 489:119543c9f674 1515 ===============================================================================
mbed_official 489:119543c9f674 1516 ##### Peripheral State functions #####
mbed_official 489:119543c9f674 1517 ===============================================================================
mbed_official 489:119543c9f674 1518 [..]
mbed_official 489:119543c9f674 1519 This subsection permits to get in run-time the status of the peripheral
mbed_official 489:119543c9f674 1520 and the data flow.
mbed_official 489:119543c9f674 1521 (+) Get the ETH handle state:
mbed_official 489:119543c9f674 1522 HAL_ETH_GetState();
mbed_official 489:119543c9f674 1523
mbed_official 489:119543c9f674 1524
mbed_official 489:119543c9f674 1525 @endverbatim
mbed_official 489:119543c9f674 1526 * @{
mbed_official 489:119543c9f674 1527 */
mbed_official 489:119543c9f674 1528
mbed_official 489:119543c9f674 1529 /**
mbed_official 489:119543c9f674 1530 * @brief Return the ETH HAL state
mbed_official 489:119543c9f674 1531 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 489:119543c9f674 1532 * the configuration information for ETHERNET module
mbed_official 489:119543c9f674 1533 * @retval HAL state
mbed_official 489:119543c9f674 1534 */
mbed_official 489:119543c9f674 1535 HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth)
mbed_official 489:119543c9f674 1536 {
mbed_official 489:119543c9f674 1537 /* Return ETH state */
mbed_official 489:119543c9f674 1538 return heth->State;
mbed_official 489:119543c9f674 1539 }
mbed_official 489:119543c9f674 1540
mbed_official 489:119543c9f674 1541 /**
mbed_official 489:119543c9f674 1542 * @}
mbed_official 489:119543c9f674 1543 */
mbed_official 489:119543c9f674 1544
mbed_official 489:119543c9f674 1545 /**
mbed_official 489:119543c9f674 1546 * @}
mbed_official 489:119543c9f674 1547 */
mbed_official 489:119543c9f674 1548
mbed_official 489:119543c9f674 1549 /** @addtogroup ETH_Private_Functions
mbed_official 489:119543c9f674 1550 * @{
mbed_official 489:119543c9f674 1551 */
mbed_official 489:119543c9f674 1552
mbed_official 489:119543c9f674 1553 /**
mbed_official 489:119543c9f674 1554 * @brief Configures Ethernet MAC and DMA with default parameters.
mbed_official 489:119543c9f674 1555 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 489:119543c9f674 1556 * the configuration information for ETHERNET module
mbed_official 489:119543c9f674 1557 * @param err: Ethernet Init error
mbed_official 489:119543c9f674 1558 * @retval HAL status
mbed_official 489:119543c9f674 1559 */
mbed_official 489:119543c9f674 1560 static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err)
mbed_official 489:119543c9f674 1561 {
mbed_official 489:119543c9f674 1562 ETH_MACInitTypeDef macinit;
mbed_official 489:119543c9f674 1563 ETH_DMAInitTypeDef dmainit;
mbed_official 489:119543c9f674 1564 uint32_t tmpreg = 0;
mbed_official 489:119543c9f674 1565
mbed_official 489:119543c9f674 1566 if (err != ETH_SUCCESS) /* Auto-negotiation failed */
mbed_official 489:119543c9f674 1567 {
mbed_official 489:119543c9f674 1568 /* Set Ethernet duplex mode to Full-duplex */
mbed_official 489:119543c9f674 1569 (heth->Init).DuplexMode = ETH_MODE_FULLDUPLEX;
mbed_official 489:119543c9f674 1570
mbed_official 489:119543c9f674 1571 /* Set Ethernet speed to 100M */
mbed_official 489:119543c9f674 1572 (heth->Init).Speed = ETH_SPEED_100M;
mbed_official 489:119543c9f674 1573 }
mbed_official 489:119543c9f674 1574
mbed_official 489:119543c9f674 1575 /* Ethernet MAC default initialization **************************************/
mbed_official 489:119543c9f674 1576 macinit.Watchdog = ETH_WATCHDOG_ENABLE;
mbed_official 489:119543c9f674 1577 macinit.Jabber = ETH_JABBER_ENABLE;
mbed_official 489:119543c9f674 1578 macinit.InterFrameGap = ETH_INTERFRAMEGAP_96BIT;
mbed_official 489:119543c9f674 1579 macinit.CarrierSense = ETH_CARRIERSENCE_ENABLE;
mbed_official 489:119543c9f674 1580 macinit.ReceiveOwn = ETH_RECEIVEOWN_ENABLE;
mbed_official 489:119543c9f674 1581 macinit.LoopbackMode = ETH_LOOPBACKMODE_DISABLE;
mbed_official 489:119543c9f674 1582 if(heth->Init.ChecksumMode == ETH_CHECKSUM_BY_HARDWARE)
mbed_official 489:119543c9f674 1583 {
mbed_official 489:119543c9f674 1584 macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_ENABLE;
mbed_official 489:119543c9f674 1585 }
mbed_official 489:119543c9f674 1586 else
mbed_official 489:119543c9f674 1587 {
mbed_official 489:119543c9f674 1588 macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_DISABLE;
mbed_official 489:119543c9f674 1589 }
mbed_official 489:119543c9f674 1590 macinit.RetryTransmission = ETH_RETRYTRANSMISSION_DISABLE;
mbed_official 489:119543c9f674 1591 macinit.AutomaticPadCRCStrip = ETH_AUTOMATICPADCRCSTRIP_DISABLE;
mbed_official 489:119543c9f674 1592 macinit.BackOffLimit = ETH_BACKOFFLIMIT_10;
mbed_official 489:119543c9f674 1593 macinit.DeferralCheck = ETH_DEFFERRALCHECK_DISABLE;
mbed_official 489:119543c9f674 1594 macinit.ReceiveAll = ETH_RECEIVEAll_DISABLE;
mbed_official 489:119543c9f674 1595 macinit.SourceAddrFilter = ETH_SOURCEADDRFILTER_DISABLE;
mbed_official 489:119543c9f674 1596 macinit.PassControlFrames = ETH_PASSCONTROLFRAMES_BLOCKALL;
mbed_official 489:119543c9f674 1597 macinit.BroadcastFramesReception = ETH_BROADCASTFRAMESRECEPTION_ENABLE;
mbed_official 489:119543c9f674 1598 macinit.DestinationAddrFilter = ETH_DESTINATIONADDRFILTER_NORMAL;
mbed_official 489:119543c9f674 1599 macinit.PromiscuousMode = ETH_PROMISCUOUS_MODE_DISABLE;
mbed_official 489:119543c9f674 1600 macinit.MulticastFramesFilter = ETH_MULTICASTFRAMESFILTER_PERFECT;
mbed_official 489:119543c9f674 1601 macinit.UnicastFramesFilter = ETH_UNICASTFRAMESFILTER_PERFECT;
mbed_official 489:119543c9f674 1602 macinit.HashTableHigh = 0x0;
mbed_official 489:119543c9f674 1603 macinit.HashTableLow = 0x0;
mbed_official 489:119543c9f674 1604 macinit.PauseTime = 0x0;
mbed_official 489:119543c9f674 1605 macinit.ZeroQuantaPause = ETH_ZEROQUANTAPAUSE_DISABLE;
mbed_official 489:119543c9f674 1606 macinit.PauseLowThreshold = ETH_PAUSELOWTHRESHOLD_MINUS4;
mbed_official 489:119543c9f674 1607 macinit.UnicastPauseFrameDetect = ETH_UNICASTPAUSEFRAMEDETECT_DISABLE;
mbed_official 489:119543c9f674 1608 macinit.ReceiveFlowControl = ETH_RECEIVEFLOWCONTROL_DISABLE;
mbed_official 489:119543c9f674 1609 macinit.TransmitFlowControl = ETH_TRANSMITFLOWCONTROL_DISABLE;
mbed_official 489:119543c9f674 1610 macinit.VLANTagComparison = ETH_VLANTAGCOMPARISON_16BIT;
mbed_official 489:119543c9f674 1611 macinit.VLANTagIdentifier = 0x0;
mbed_official 489:119543c9f674 1612
mbed_official 489:119543c9f674 1613 /*------------------------ ETHERNET MACCR Configuration --------------------*/
mbed_official 489:119543c9f674 1614 /* Get the ETHERNET MACCR value */
mbed_official 489:119543c9f674 1615 tmpreg = (heth->Instance)->MACCR;
mbed_official 489:119543c9f674 1616 /* Clear WD, PCE, PS, TE and RE bits */
mbed_official 489:119543c9f674 1617 tmpreg &= ETH_MACCR_CLEAR_MASK;
mbed_official 489:119543c9f674 1618 /* Set the WD bit according to ETH Watchdog value */
mbed_official 489:119543c9f674 1619 /* Set the JD: bit according to ETH Jabber value */
mbed_official 489:119543c9f674 1620 /* Set the IFG bit according to ETH InterFrameGap value */
mbed_official 489:119543c9f674 1621 /* Set the DCRS bit according to ETH CarrierSense value */
mbed_official 489:119543c9f674 1622 /* Set the FES bit according to ETH Speed value */
mbed_official 489:119543c9f674 1623 /* Set the DO bit according to ETH ReceiveOwn value */
mbed_official 489:119543c9f674 1624 /* Set the LM bit according to ETH LoopbackMode value */
mbed_official 489:119543c9f674 1625 /* Set the DM bit according to ETH Mode value */
mbed_official 489:119543c9f674 1626 /* Set the IPCO bit according to ETH ChecksumOffload value */
mbed_official 489:119543c9f674 1627 /* Set the DR bit according to ETH RetryTransmission value */
mbed_official 489:119543c9f674 1628 /* Set the ACS bit according to ETH AutomaticPadCRCStrip value */
mbed_official 489:119543c9f674 1629 /* Set the BL bit according to ETH BackOffLimit value */
mbed_official 489:119543c9f674 1630 /* Set the DC bit according to ETH DeferralCheck value */
mbed_official 489:119543c9f674 1631 tmpreg |= (uint32_t)(macinit.Watchdog |
mbed_official 489:119543c9f674 1632 macinit.Jabber |
mbed_official 489:119543c9f674 1633 macinit.InterFrameGap |
mbed_official 489:119543c9f674 1634 macinit.CarrierSense |
mbed_official 489:119543c9f674 1635 (heth->Init).Speed |
mbed_official 489:119543c9f674 1636 macinit.ReceiveOwn |
mbed_official 489:119543c9f674 1637 macinit.LoopbackMode |
mbed_official 489:119543c9f674 1638 (heth->Init).DuplexMode |
mbed_official 489:119543c9f674 1639 macinit.ChecksumOffload |
mbed_official 489:119543c9f674 1640 macinit.RetryTransmission |
mbed_official 489:119543c9f674 1641 macinit.AutomaticPadCRCStrip |
mbed_official 489:119543c9f674 1642 macinit.BackOffLimit |
mbed_official 489:119543c9f674 1643 macinit.DeferralCheck);
mbed_official 489:119543c9f674 1644
mbed_official 489:119543c9f674 1645 /* Write to ETHERNET MACCR */
mbed_official 489:119543c9f674 1646 (heth->Instance)->MACCR = (uint32_t)tmpreg;
mbed_official 489:119543c9f674 1647
mbed_official 489:119543c9f674 1648 /* Wait until the write operation will be taken into account:
mbed_official 489:119543c9f674 1649 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 489:119543c9f674 1650 tmpreg = (heth->Instance)->MACCR;
mbed_official 489:119543c9f674 1651 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 489:119543c9f674 1652 (heth->Instance)->MACCR = tmpreg;
mbed_official 489:119543c9f674 1653
mbed_official 489:119543c9f674 1654 /*----------------------- ETHERNET MACFFR Configuration --------------------*/
mbed_official 489:119543c9f674 1655 /* Set the RA bit according to ETH ReceiveAll value */
mbed_official 489:119543c9f674 1656 /* Set the SAF and SAIF bits according to ETH SourceAddrFilter value */
mbed_official 489:119543c9f674 1657 /* Set the PCF bit according to ETH PassControlFrames value */
mbed_official 489:119543c9f674 1658 /* Set the DBF bit according to ETH BroadcastFramesReception value */
mbed_official 489:119543c9f674 1659 /* Set the DAIF bit according to ETH DestinationAddrFilter value */
mbed_official 489:119543c9f674 1660 /* Set the PR bit according to ETH PromiscuousMode value */
mbed_official 489:119543c9f674 1661 /* Set the PM, HMC and HPF bits according to ETH MulticastFramesFilter value */
mbed_official 489:119543c9f674 1662 /* Set the HUC and HPF bits according to ETH UnicastFramesFilter value */
mbed_official 489:119543c9f674 1663 /* Write to ETHERNET MACFFR */
mbed_official 489:119543c9f674 1664 (heth->Instance)->MACFFR = (uint32_t)(macinit.ReceiveAll |
mbed_official 489:119543c9f674 1665 macinit.SourceAddrFilter |
mbed_official 489:119543c9f674 1666 macinit.PassControlFrames |
mbed_official 489:119543c9f674 1667 macinit.BroadcastFramesReception |
mbed_official 489:119543c9f674 1668 macinit.DestinationAddrFilter |
mbed_official 489:119543c9f674 1669 macinit.PromiscuousMode |
mbed_official 489:119543c9f674 1670 macinit.MulticastFramesFilter |
mbed_official 489:119543c9f674 1671 macinit.UnicastFramesFilter);
mbed_official 489:119543c9f674 1672
mbed_official 489:119543c9f674 1673 /* Wait until the write operation will be taken into account:
mbed_official 489:119543c9f674 1674 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 489:119543c9f674 1675 tmpreg = (heth->Instance)->MACFFR;
mbed_official 489:119543c9f674 1676 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 489:119543c9f674 1677 (heth->Instance)->MACFFR = tmpreg;
mbed_official 489:119543c9f674 1678
mbed_official 489:119543c9f674 1679 /*--------------- ETHERNET MACHTHR and MACHTLR Configuration --------------*/
mbed_official 489:119543c9f674 1680 /* Write to ETHERNET MACHTHR */
mbed_official 489:119543c9f674 1681 (heth->Instance)->MACHTHR = (uint32_t)macinit.HashTableHigh;
mbed_official 489:119543c9f674 1682
mbed_official 489:119543c9f674 1683 /* Write to ETHERNET MACHTLR */
mbed_official 489:119543c9f674 1684 (heth->Instance)->MACHTLR = (uint32_t)macinit.HashTableLow;
mbed_official 489:119543c9f674 1685 /*----------------------- ETHERNET MACFCR Configuration -------------------*/
mbed_official 489:119543c9f674 1686
mbed_official 489:119543c9f674 1687 /* Get the ETHERNET MACFCR value */
mbed_official 489:119543c9f674 1688 tmpreg = (heth->Instance)->MACFCR;
mbed_official 489:119543c9f674 1689 /* Clear xx bits */
mbed_official 489:119543c9f674 1690 tmpreg &= ETH_MACFCR_CLEAR_MASK;
mbed_official 489:119543c9f674 1691
mbed_official 489:119543c9f674 1692 /* Set the PT bit according to ETH PauseTime value */
mbed_official 489:119543c9f674 1693 /* Set the DZPQ bit according to ETH ZeroQuantaPause value */
mbed_official 489:119543c9f674 1694 /* Set the PLT bit according to ETH PauseLowThreshold value */
mbed_official 489:119543c9f674 1695 /* Set the UP bit according to ETH UnicastPauseFrameDetect value */
mbed_official 489:119543c9f674 1696 /* Set the RFE bit according to ETH ReceiveFlowControl value */
mbed_official 489:119543c9f674 1697 /* Set the TFE bit according to ETH TransmitFlowControl value */
mbed_official 489:119543c9f674 1698 tmpreg |= (uint32_t)((macinit.PauseTime << 16) |
mbed_official 489:119543c9f674 1699 macinit.ZeroQuantaPause |
mbed_official 489:119543c9f674 1700 macinit.PauseLowThreshold |
mbed_official 489:119543c9f674 1701 macinit.UnicastPauseFrameDetect |
mbed_official 489:119543c9f674 1702 macinit.ReceiveFlowControl |
mbed_official 489:119543c9f674 1703 macinit.TransmitFlowControl);
mbed_official 489:119543c9f674 1704
mbed_official 489:119543c9f674 1705 /* Write to ETHERNET MACFCR */
mbed_official 489:119543c9f674 1706 (heth->Instance)->MACFCR = (uint32_t)tmpreg;
mbed_official 489:119543c9f674 1707
mbed_official 489:119543c9f674 1708 /* Wait until the write operation will be taken into account:
mbed_official 489:119543c9f674 1709 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 489:119543c9f674 1710 tmpreg = (heth->Instance)->MACFCR;
mbed_official 489:119543c9f674 1711 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 489:119543c9f674 1712 (heth->Instance)->MACFCR = tmpreg;
mbed_official 489:119543c9f674 1713
mbed_official 489:119543c9f674 1714 /*----------------------- ETHERNET MACVLANTR Configuration ----------------*/
mbed_official 489:119543c9f674 1715 /* Set the ETV bit according to ETH VLANTagComparison value */
mbed_official 489:119543c9f674 1716 /* Set the VL bit according to ETH VLANTagIdentifier value */
mbed_official 489:119543c9f674 1717 (heth->Instance)->MACVLANTR = (uint32_t)(macinit.VLANTagComparison |
mbed_official 489:119543c9f674 1718 macinit.VLANTagIdentifier);
mbed_official 489:119543c9f674 1719
mbed_official 489:119543c9f674 1720 /* Wait until the write operation will be taken into account:
mbed_official 489:119543c9f674 1721 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 489:119543c9f674 1722 tmpreg = (heth->Instance)->MACVLANTR;
mbed_official 489:119543c9f674 1723 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 489:119543c9f674 1724 (heth->Instance)->MACVLANTR = tmpreg;
mbed_official 489:119543c9f674 1725
mbed_official 489:119543c9f674 1726 /* Ethernet DMA default initialization ************************************/
mbed_official 489:119543c9f674 1727 dmainit.DropTCPIPChecksumErrorFrame = ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE;
mbed_official 489:119543c9f674 1728 dmainit.ReceiveStoreForward = ETH_RECEIVESTOREFORWARD_ENABLE;
mbed_official 489:119543c9f674 1729 dmainit.FlushReceivedFrame = ETH_FLUSHRECEIVEDFRAME_ENABLE;
mbed_official 489:119543c9f674 1730 dmainit.TransmitStoreForward = ETH_TRANSMITSTOREFORWARD_ENABLE;
mbed_official 489:119543c9f674 1731 dmainit.TransmitThresholdControl = ETH_TRANSMITTHRESHOLDCONTROL_64BYTES;
mbed_official 489:119543c9f674 1732 dmainit.ForwardErrorFrames = ETH_FORWARDERRORFRAMES_DISABLE;
mbed_official 489:119543c9f674 1733 dmainit.ForwardUndersizedGoodFrames = ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE;
mbed_official 489:119543c9f674 1734 dmainit.ReceiveThresholdControl = ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES;
mbed_official 489:119543c9f674 1735 dmainit.SecondFrameOperate = ETH_SECONDFRAMEOPERARTE_ENABLE;
mbed_official 489:119543c9f674 1736 dmainit.AddressAlignedBeats = ETH_ADDRESSALIGNEDBEATS_ENABLE;
mbed_official 489:119543c9f674 1737 dmainit.FixedBurst = ETH_FIXEDBURST_ENABLE;
mbed_official 489:119543c9f674 1738 dmainit.RxDMABurstLength = ETH_RXDMABURSTLENGTH_32BEAT;
mbed_official 489:119543c9f674 1739 dmainit.TxDMABurstLength = ETH_TXDMABURSTLENGTH_32BEAT;
mbed_official 489:119543c9f674 1740 dmainit.DescriptorSkipLength = 0x0;
mbed_official 489:119543c9f674 1741 dmainit.DMAArbitration = ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1;
mbed_official 489:119543c9f674 1742
mbed_official 489:119543c9f674 1743 /* Get the ETHERNET DMAOMR value */
mbed_official 489:119543c9f674 1744 tmpreg = (heth->Instance)->DMAOMR;
mbed_official 489:119543c9f674 1745 /* Clear xx bits */
mbed_official 489:119543c9f674 1746 tmpreg &= ETH_DMAOMR_CLEAR_MASK;
mbed_official 489:119543c9f674 1747
mbed_official 489:119543c9f674 1748 /* Set the DT bit according to ETH DropTCPIPChecksumErrorFrame value */
mbed_official 489:119543c9f674 1749 /* Set the RSF bit according to ETH ReceiveStoreForward value */
mbed_official 489:119543c9f674 1750 /* Set the DFF bit according to ETH FlushReceivedFrame value */
mbed_official 489:119543c9f674 1751 /* Set the TSF bit according to ETH TransmitStoreForward value */
mbed_official 489:119543c9f674 1752 /* Set the TTC bit according to ETH TransmitThresholdControl value */
mbed_official 489:119543c9f674 1753 /* Set the FEF bit according to ETH ForwardErrorFrames value */
mbed_official 489:119543c9f674 1754 /* Set the FUF bit according to ETH ForwardUndersizedGoodFrames value */
mbed_official 489:119543c9f674 1755 /* Set the RTC bit according to ETH ReceiveThresholdControl value */
mbed_official 489:119543c9f674 1756 /* Set the OSF bit according to ETH SecondFrameOperate value */
mbed_official 489:119543c9f674 1757 tmpreg |= (uint32_t)(dmainit.DropTCPIPChecksumErrorFrame |
mbed_official 489:119543c9f674 1758 dmainit.ReceiveStoreForward |
mbed_official 489:119543c9f674 1759 dmainit.FlushReceivedFrame |
mbed_official 489:119543c9f674 1760 dmainit.TransmitStoreForward |
mbed_official 489:119543c9f674 1761 dmainit.TransmitThresholdControl |
mbed_official 489:119543c9f674 1762 dmainit.ForwardErrorFrames |
mbed_official 489:119543c9f674 1763 dmainit.ForwardUndersizedGoodFrames |
mbed_official 489:119543c9f674 1764 dmainit.ReceiveThresholdControl |
mbed_official 489:119543c9f674 1765 dmainit.SecondFrameOperate);
mbed_official 489:119543c9f674 1766
mbed_official 489:119543c9f674 1767 /* Write to ETHERNET DMAOMR */
mbed_official 489:119543c9f674 1768 (heth->Instance)->DMAOMR = (uint32_t)tmpreg;
mbed_official 489:119543c9f674 1769
mbed_official 489:119543c9f674 1770 /* Wait until the write operation will be taken into account:
mbed_official 489:119543c9f674 1771 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 489:119543c9f674 1772 tmpreg = (heth->Instance)->DMAOMR;
mbed_official 489:119543c9f674 1773 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 489:119543c9f674 1774 (heth->Instance)->DMAOMR = tmpreg;
mbed_official 489:119543c9f674 1775
mbed_official 489:119543c9f674 1776 /*----------------------- ETHERNET DMABMR Configuration ------------------*/
mbed_official 489:119543c9f674 1777 /* Set the AAL bit according to ETH AddressAlignedBeats value */
mbed_official 489:119543c9f674 1778 /* Set the FB bit according to ETH FixedBurst value */
mbed_official 489:119543c9f674 1779 /* Set the RPBL and 4*PBL bits according to ETH RxDMABurstLength value */
mbed_official 489:119543c9f674 1780 /* Set the PBL and 4*PBL bits according to ETH TxDMABurstLength value */
mbed_official 489:119543c9f674 1781 /* Set the DSL bit according to ETH DesciptorSkipLength value */
mbed_official 489:119543c9f674 1782 /* Set the PR and DA bits according to ETH DMAArbitration value */
mbed_official 489:119543c9f674 1783 (heth->Instance)->DMABMR = (uint32_t)(dmainit.AddressAlignedBeats |
mbed_official 489:119543c9f674 1784 dmainit.FixedBurst |
mbed_official 489:119543c9f674 1785 dmainit.RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */
mbed_official 489:119543c9f674 1786 dmainit.TxDMABurstLength |
mbed_official 489:119543c9f674 1787 (dmainit.DescriptorSkipLength << 2) |
mbed_official 489:119543c9f674 1788 dmainit.DMAArbitration |
mbed_official 489:119543c9f674 1789 ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */
mbed_official 489:119543c9f674 1790
mbed_official 489:119543c9f674 1791 /* Wait until the write operation will be taken into account:
mbed_official 489:119543c9f674 1792 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 489:119543c9f674 1793 tmpreg = (heth->Instance)->DMABMR;
mbed_official 489:119543c9f674 1794 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 489:119543c9f674 1795 (heth->Instance)->DMABMR = tmpreg;
mbed_official 489:119543c9f674 1796
mbed_official 489:119543c9f674 1797 if((heth->Init).RxMode == ETH_RXINTERRUPT_MODE)
mbed_official 489:119543c9f674 1798 {
mbed_official 489:119543c9f674 1799 /* Enable the Ethernet Rx Interrupt */
mbed_official 489:119543c9f674 1800 __HAL_ETH_DMA_ENABLE_IT((heth), ETH_DMA_IT_NIS | ETH_DMA_IT_R);
mbed_official 489:119543c9f674 1801 }
mbed_official 489:119543c9f674 1802
mbed_official 489:119543c9f674 1803 /* Initialize MAC address in ethernet MAC */
mbed_official 489:119543c9f674 1804 ETH_MACAddressConfig(heth, ETH_MAC_ADDRESS0, heth->Init.MACAddr);
mbed_official 489:119543c9f674 1805 }
mbed_official 489:119543c9f674 1806
mbed_official 489:119543c9f674 1807 /**
mbed_official 489:119543c9f674 1808 * @brief Configures the selected MAC address.
mbed_official 489:119543c9f674 1809 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 489:119543c9f674 1810 * the configuration information for ETHERNET module
mbed_official 489:119543c9f674 1811 * @param MacAddr: The MAC address to configure
mbed_official 489:119543c9f674 1812 * This parameter can be one of the following values:
mbed_official 489:119543c9f674 1813 * @arg ETH_MAC_Address0: MAC Address0
mbed_official 489:119543c9f674 1814 * @arg ETH_MAC_Address1: MAC Address1
mbed_official 489:119543c9f674 1815 * @arg ETH_MAC_Address2: MAC Address2
mbed_official 489:119543c9f674 1816 * @arg ETH_MAC_Address3: MAC Address3
mbed_official 489:119543c9f674 1817 * @param Addr: Pointer to MAC address buffer data (6 bytes)
mbed_official 489:119543c9f674 1818 * @retval HAL status
mbed_official 489:119543c9f674 1819 */
mbed_official 489:119543c9f674 1820 static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr)
mbed_official 489:119543c9f674 1821 {
mbed_official 489:119543c9f674 1822 uint32_t tmpreg;
mbed_official 489:119543c9f674 1823
mbed_official 489:119543c9f674 1824 /* Check the parameters */
mbed_official 489:119543c9f674 1825 assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr));
mbed_official 489:119543c9f674 1826
mbed_official 489:119543c9f674 1827 /* Calculate the selected MAC address high register */
mbed_official 489:119543c9f674 1828 tmpreg = ((uint32_t)Addr[5] << 8) | (uint32_t)Addr[4];
mbed_official 489:119543c9f674 1829 /* Load the selected MAC address high register */
mbed_official 489:119543c9f674 1830 (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_HBASE + MacAddr))) = tmpreg;
mbed_official 489:119543c9f674 1831 /* Calculate the selected MAC address low register */
mbed_official 489:119543c9f674 1832 tmpreg = ((uint32_t)Addr[3] << 24) | ((uint32_t)Addr[2] << 16) | ((uint32_t)Addr[1] << 8) | Addr[0];
mbed_official 489:119543c9f674 1833
mbed_official 489:119543c9f674 1834 /* Load the selected MAC address low register */
mbed_official 489:119543c9f674 1835 (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_LBASE + MacAddr))) = tmpreg;
mbed_official 489:119543c9f674 1836 }
mbed_official 489:119543c9f674 1837
mbed_official 489:119543c9f674 1838 /**
mbed_official 489:119543c9f674 1839 * @brief Enables the MAC transmission.
mbed_official 489:119543c9f674 1840 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 489:119543c9f674 1841 * the configuration information for ETHERNET module
mbed_official 489:119543c9f674 1842 * @retval None
mbed_official 489:119543c9f674 1843 */
mbed_official 489:119543c9f674 1844 static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth)
mbed_official 489:119543c9f674 1845 {
mbed_official 489:119543c9f674 1846 __IO uint32_t tmpreg = 0;
mbed_official 489:119543c9f674 1847
mbed_official 489:119543c9f674 1848 /* Enable the MAC transmission */
mbed_official 489:119543c9f674 1849 (heth->Instance)->MACCR |= ETH_MACCR_TE;
mbed_official 489:119543c9f674 1850
mbed_official 489:119543c9f674 1851 /* Wait until the write operation will be taken into account:
mbed_official 489:119543c9f674 1852 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 489:119543c9f674 1853 tmpreg = (heth->Instance)->MACCR;
mbed_official 489:119543c9f674 1854 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 489:119543c9f674 1855 (heth->Instance)->MACCR = tmpreg;
mbed_official 489:119543c9f674 1856 }
mbed_official 489:119543c9f674 1857
mbed_official 489:119543c9f674 1858 /**
mbed_official 489:119543c9f674 1859 * @brief Disables the MAC transmission.
mbed_official 489:119543c9f674 1860 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 489:119543c9f674 1861 * the configuration information for ETHERNET module
mbed_official 489:119543c9f674 1862 * @retval None
mbed_official 489:119543c9f674 1863 */
mbed_official 489:119543c9f674 1864 static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth)
mbed_official 489:119543c9f674 1865 {
mbed_official 489:119543c9f674 1866 __IO uint32_t tmpreg = 0;
mbed_official 489:119543c9f674 1867
mbed_official 489:119543c9f674 1868 /* Disable the MAC transmission */
mbed_official 489:119543c9f674 1869 (heth->Instance)->MACCR &= ~ETH_MACCR_TE;
mbed_official 489:119543c9f674 1870
mbed_official 489:119543c9f674 1871 /* Wait until the write operation will be taken into account:
mbed_official 489:119543c9f674 1872 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 489:119543c9f674 1873 tmpreg = (heth->Instance)->MACCR;
mbed_official 489:119543c9f674 1874 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 489:119543c9f674 1875 (heth->Instance)->MACCR = tmpreg;
mbed_official 489:119543c9f674 1876 }
mbed_official 489:119543c9f674 1877
mbed_official 489:119543c9f674 1878 /**
mbed_official 489:119543c9f674 1879 * @brief Enables the MAC reception.
mbed_official 489:119543c9f674 1880 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 489:119543c9f674 1881 * the configuration information for ETHERNET module
mbed_official 489:119543c9f674 1882 * @retval None
mbed_official 489:119543c9f674 1883 */
mbed_official 489:119543c9f674 1884 static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth)
mbed_official 489:119543c9f674 1885 {
mbed_official 489:119543c9f674 1886 __IO uint32_t tmpreg = 0;
mbed_official 489:119543c9f674 1887
mbed_official 489:119543c9f674 1888 /* Enable the MAC reception */
mbed_official 489:119543c9f674 1889 (heth->Instance)->MACCR |= ETH_MACCR_RE;
mbed_official 489:119543c9f674 1890
mbed_official 489:119543c9f674 1891 /* Wait until the write operation will be taken into account:
mbed_official 489:119543c9f674 1892 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 489:119543c9f674 1893 tmpreg = (heth->Instance)->MACCR;
mbed_official 489:119543c9f674 1894 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 489:119543c9f674 1895 (heth->Instance)->MACCR = tmpreg;
mbed_official 489:119543c9f674 1896 }
mbed_official 489:119543c9f674 1897
mbed_official 489:119543c9f674 1898 /**
mbed_official 489:119543c9f674 1899 * @brief Disables the MAC reception.
mbed_official 489:119543c9f674 1900 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 489:119543c9f674 1901 * the configuration information for ETHERNET module
mbed_official 489:119543c9f674 1902 * @retval None
mbed_official 489:119543c9f674 1903 */
mbed_official 489:119543c9f674 1904 static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth)
mbed_official 489:119543c9f674 1905 {
mbed_official 489:119543c9f674 1906 __IO uint32_t tmpreg = 0;
mbed_official 489:119543c9f674 1907
mbed_official 489:119543c9f674 1908 /* Disable the MAC reception */
mbed_official 489:119543c9f674 1909 (heth->Instance)->MACCR &= ~ETH_MACCR_RE;
mbed_official 489:119543c9f674 1910
mbed_official 489:119543c9f674 1911 /* Wait until the write operation will be taken into account:
mbed_official 489:119543c9f674 1912 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 489:119543c9f674 1913 tmpreg = (heth->Instance)->MACCR;
mbed_official 489:119543c9f674 1914 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 489:119543c9f674 1915 (heth->Instance)->MACCR = tmpreg;
mbed_official 489:119543c9f674 1916 }
mbed_official 489:119543c9f674 1917
mbed_official 489:119543c9f674 1918 /**
mbed_official 489:119543c9f674 1919 * @brief Enables the DMA transmission.
mbed_official 489:119543c9f674 1920 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 489:119543c9f674 1921 * the configuration information for ETHERNET module
mbed_official 489:119543c9f674 1922 * @retval None
mbed_official 489:119543c9f674 1923 */
mbed_official 489:119543c9f674 1924 static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth)
mbed_official 489:119543c9f674 1925 {
mbed_official 489:119543c9f674 1926 /* Enable the DMA transmission */
mbed_official 489:119543c9f674 1927 (heth->Instance)->DMAOMR |= ETH_DMAOMR_ST;
mbed_official 489:119543c9f674 1928 }
mbed_official 489:119543c9f674 1929
mbed_official 489:119543c9f674 1930 /**
mbed_official 489:119543c9f674 1931 * @brief Disables the DMA transmission.
mbed_official 489:119543c9f674 1932 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 489:119543c9f674 1933 * the configuration information for ETHERNET module
mbed_official 489:119543c9f674 1934 * @retval None
mbed_official 489:119543c9f674 1935 */
mbed_official 489:119543c9f674 1936 static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth)
mbed_official 489:119543c9f674 1937 {
mbed_official 489:119543c9f674 1938 /* Disable the DMA transmission */
mbed_official 489:119543c9f674 1939 (heth->Instance)->DMAOMR &= ~ETH_DMAOMR_ST;
mbed_official 489:119543c9f674 1940 }
mbed_official 489:119543c9f674 1941
mbed_official 489:119543c9f674 1942 /**
mbed_official 489:119543c9f674 1943 * @brief Enables the DMA reception.
mbed_official 489:119543c9f674 1944 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 489:119543c9f674 1945 * the configuration information for ETHERNET module
mbed_official 489:119543c9f674 1946 * @retval None
mbed_official 489:119543c9f674 1947 */
mbed_official 489:119543c9f674 1948 static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth)
mbed_official 489:119543c9f674 1949 {
mbed_official 489:119543c9f674 1950 /* Enable the DMA reception */
mbed_official 489:119543c9f674 1951 (heth->Instance)->DMAOMR |= ETH_DMAOMR_SR;
mbed_official 489:119543c9f674 1952 }
mbed_official 489:119543c9f674 1953
mbed_official 489:119543c9f674 1954 /**
mbed_official 489:119543c9f674 1955 * @brief Disables the DMA reception.
mbed_official 489:119543c9f674 1956 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 489:119543c9f674 1957 * the configuration information for ETHERNET module
mbed_official 489:119543c9f674 1958 * @retval None
mbed_official 489:119543c9f674 1959 */
mbed_official 489:119543c9f674 1960 static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth)
mbed_official 489:119543c9f674 1961 {
mbed_official 489:119543c9f674 1962 /* Disable the DMA reception */
mbed_official 489:119543c9f674 1963 (heth->Instance)->DMAOMR &= ~ETH_DMAOMR_SR;
mbed_official 489:119543c9f674 1964 }
mbed_official 489:119543c9f674 1965
mbed_official 489:119543c9f674 1966 /**
mbed_official 489:119543c9f674 1967 * @brief Clears the ETHERNET transmit FIFO.
mbed_official 489:119543c9f674 1968 * @param heth: pointer to a ETH_HandleTypeDef structure that contains
mbed_official 489:119543c9f674 1969 * the configuration information for ETHERNET module
mbed_official 489:119543c9f674 1970 * @retval None
mbed_official 489:119543c9f674 1971 */
mbed_official 489:119543c9f674 1972 static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth)
mbed_official 489:119543c9f674 1973 {
mbed_official 489:119543c9f674 1974 __IO uint32_t tmpreg = 0;
mbed_official 489:119543c9f674 1975
mbed_official 489:119543c9f674 1976 /* Set the Flush Transmit FIFO bit */
mbed_official 489:119543c9f674 1977 (heth->Instance)->DMAOMR |= ETH_DMAOMR_FTF;
mbed_official 489:119543c9f674 1978
mbed_official 489:119543c9f674 1979 /* Wait until the write operation will be taken into account:
mbed_official 489:119543c9f674 1980 at least four TX_CLK/RX_CLK clock cycles */
mbed_official 489:119543c9f674 1981 tmpreg = (heth->Instance)->DMAOMR;
mbed_official 489:119543c9f674 1982 HAL_Delay(ETH_REG_WRITE_DELAY);
mbed_official 489:119543c9f674 1983 (heth->Instance)->DMAOMR = tmpreg;
mbed_official 489:119543c9f674 1984 }
mbed_official 489:119543c9f674 1985
mbed_official 489:119543c9f674 1986 /**
mbed_official 489:119543c9f674 1987 * @}
mbed_official 489:119543c9f674 1988 */
mbed_official 489:119543c9f674 1989
mbed_official 489:119543c9f674 1990 #endif /* HAL_ETH_MODULE_ENABLED */
mbed_official 489:119543c9f674 1991 /**
mbed_official 489:119543c9f674 1992 * @}
mbed_official 489:119543c9f674 1993 */
mbed_official 489:119543c9f674 1994
mbed_official 489:119543c9f674 1995 #endif /* STM32F107xC */
mbed_official 489:119543c9f674 1996 /**
mbed_official 489:119543c9f674 1997 * @}
mbed_official 489:119543c9f674 1998 */
mbed_official 489:119543c9f674 1999
mbed_official 489:119543c9f674 2000 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/