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Superseded

This library was superseded by mbed-dev - https://os.mbed.com/users/mbed_official/code/mbed-dev/.

Development branch of the mbed library sources. This library is kept in synch with the latest changes from the mbed SDK and it is not guaranteed to work.

If you are looking for a stable and tested release, please import one of the official mbed library releases:

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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Last commit 20 Feb 2019 by mbed official

targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/RZ_A1_Init.c@390:35c2c1cf29cd, 2014-11-06 (annotated)

Committer:
mbed_official
Date:
Thu Nov 06 11:00:10 2014 +0000
Revision:
390:35c2c1cf29cd
Child:
424:73631a54077f
Synchronized with git revision 8724eb616b6e07a3bd111d3022652eb5bbefe9b7



Full URL: https://github.com/mbedmicro/mbed/commit/8724eb616b6e07a3bd111d3022652eb5bbefe9b7/



[RZ/A1H] mbed-RZ first release

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 390:35c2c1cf29cd 1 /*******************************************************************************
mbed_official 390:35c2c1cf29cd 2 * DISCLAIMER
mbed_official 390:35c2c1cf29cd 3 * This software is supplied by Renesas Electronics Corporation and is only
mbed_official 390:35c2c1cf29cd 4 * intended for use with Renesas products. No other uses are authorized. This
mbed_official 390:35c2c1cf29cd 5 * software is owned by Renesas Electronics Corporation and is protected under
mbed_official 390:35c2c1cf29cd 6 * all applicable laws, including copyright laws.
mbed_official 390:35c2c1cf29cd 7 * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
mbed_official 390:35c2c1cf29cd 8 * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
mbed_official 390:35c2c1cf29cd 9 * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
mbed_official 390:35c2c1cf29cd 10 * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
mbed_official 390:35c2c1cf29cd 11 * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
mbed_official 390:35c2c1cf29cd 12 * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
mbed_official 390:35c2c1cf29cd 13 * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
mbed_official 390:35c2c1cf29cd 14 * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
mbed_official 390:35c2c1cf29cd 15 * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
mbed_official 390:35c2c1cf29cd 16 * Renesas reserves the right, without notice, to make changes to this software
mbed_official 390:35c2c1cf29cd 17 * and to discontinue the availability of this software. By using this software,
mbed_official 390:35c2c1cf29cd 18 * you agree to the additional terms and conditions found by accessing the
mbed_official 390:35c2c1cf29cd 19 * following link:
mbed_official 390:35c2c1cf29cd 20 * http://www.renesas.com/disclaimer
mbed_official 390:35c2c1cf29cd 21 * Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
mbed_official 390:35c2c1cf29cd 22 *******************************************************************************/
mbed_official 390:35c2c1cf29cd 23 /**************************************************************************//**
mbed_official 390:35c2c1cf29cd 24 * @file RZ_A1_Init.c
mbed_official 390:35c2c1cf29cd 25 * $Rev: 624 $
mbed_official 390:35c2c1cf29cd 26 * $Date:: 2013-04-24 13:37:48 +0900#$
mbed_official 390:35c2c1cf29cd 27 * @brief RZ_A1 Initialize
mbed_official 390:35c2c1cf29cd 28 ******************************************************************************/
mbed_official 390:35c2c1cf29cd 29
mbed_official 390:35c2c1cf29cd 30 /******************************************************************************
mbed_official 390:35c2c1cf29cd 31 Includes <System Includes> , "Project Includes"
mbed_official 390:35c2c1cf29cd 32 ******************************************************************************/
mbed_official 390:35c2c1cf29cd 33 #include "MBRZA1H.h"
mbed_official 390:35c2c1cf29cd 34 #include "RZ_A1_Init.h"
mbed_official 390:35c2c1cf29cd 35
mbed_official 390:35c2c1cf29cd 36 /******************************************************************************
mbed_official 390:35c2c1cf29cd 37 Typedef definitions
mbed_official 390:35c2c1cf29cd 38 ******************************************************************************/
mbed_official 390:35c2c1cf29cd 39
mbed_official 390:35c2c1cf29cd 40 /******************************************************************************
mbed_official 390:35c2c1cf29cd 41 Macro definitions
mbed_official 390:35c2c1cf29cd 42 ******************************************************************************/
mbed_official 390:35c2c1cf29cd 43 #define CS2_SDRAM_MODE_16BIT_CAS2_BR_BW (*(volatile uint16_t*)0x3FFFD040)
mbed_official 390:35c2c1cf29cd 44 #define CS3_SDRAM_MODE_16BIT_CAS2_BR_BW (*(volatile uint16_t*)0x3FFFE040)
mbed_official 390:35c2c1cf29cd 45
mbed_official 390:35c2c1cf29cd 46 #define GPIO_PORT0_BOOTMODE_BITMASK (0x000fu)
mbed_official 390:35c2c1cf29cd 47
mbed_official 390:35c2c1cf29cd 48 /******************************************************************************
mbed_official 390:35c2c1cf29cd 49 Imported global variables and functions (from other files)
mbed_official 390:35c2c1cf29cd 50 ******************************************************************************/
mbed_official 390:35c2c1cf29cd 51
mbed_official 390:35c2c1cf29cd 52 /******************************************************************************
mbed_official 390:35c2c1cf29cd 53 Exported global variables and functions (to be accessed by other files)
mbed_official 390:35c2c1cf29cd 54 ******************************************************************************/
mbed_official 390:35c2c1cf29cd 55
mbed_official 390:35c2c1cf29cd 56 /******************************************************************************
mbed_official 390:35c2c1cf29cd 57 Private global variables and functions
mbed_official 390:35c2c1cf29cd 58 ******************************************************************************/
mbed_official 390:35c2c1cf29cd 59
mbed_official 390:35c2c1cf29cd 60 /**************************************************************************//**
mbed_official 390:35c2c1cf29cd 61 * Function Name: RZ_A1_SetSramWriteEnable
mbed_official 390:35c2c1cf29cd 62 * @brief Initialize Board settings
mbed_official 390:35c2c1cf29cd 63 *
mbed_official 390:35c2c1cf29cd 64 * Description:<br>
mbed_official 390:35c2c1cf29cd 65 * Set SRAM write enable
mbed_official 390:35c2c1cf29cd 66 * @param none
mbed_official 390:35c2c1cf29cd 67 * @retval none
mbed_official 390:35c2c1cf29cd 68 ******************************************************************************/
mbed_official 390:35c2c1cf29cd 69 void RZ_A1_SetSramWriteEnable(void)
mbed_official 390:35c2c1cf29cd 70 {
mbed_official 390:35c2c1cf29cd 71 /* Enable SRAM write access */
mbed_official 390:35c2c1cf29cd 72 CPG.SYSCR3 = 0x0F;
mbed_official 390:35c2c1cf29cd 73
mbed_official 390:35c2c1cf29cd 74 return;
mbed_official 390:35c2c1cf29cd 75 }
mbed_official 390:35c2c1cf29cd 76
mbed_official 390:35c2c1cf29cd 77 /**************************************************************************//**
mbed_official 390:35c2c1cf29cd 78 * Function Name: RZ_A1_InitClock
mbed_official 390:35c2c1cf29cd 79 * @brief Initialize Board settings
mbed_official 390:35c2c1cf29cd 80 *
mbed_official 390:35c2c1cf29cd 81 * Description:<br>
mbed_official 390:35c2c1cf29cd 82 * Initialize Clock
mbed_official 390:35c2c1cf29cd 83 * @param none
mbed_official 390:35c2c1cf29cd 84 * @retval none
mbed_official 390:35c2c1cf29cd 85 ******************************************************************************/
mbed_official 390:35c2c1cf29cd 86 void RZ_A1_InitClock(void)
mbed_official 390:35c2c1cf29cd 87 {
mbed_official 390:35c2c1cf29cd 88 /* Cancel L2C standby status before clock change */
mbed_official 390:35c2c1cf29cd 89 L2CREG15_POWER_CTRL = 0x00000001;
mbed_official 390:35c2c1cf29cd 90
mbed_official 390:35c2c1cf29cd 91 /* Clock settings */
mbed_official 390:35c2c1cf29cd 92 /* ClockMode0 */
mbed_official 390:35c2c1cf29cd 93 CPG.FRQCR = 0x1035; /* CPU Clock =399.99MHz */
mbed_official 390:35c2c1cf29cd 94 CPG.FRQCR2 = 0x0001; /* G Clock =266.66MHz */
mbed_official 390:35c2c1cf29cd 95
mbed_official 390:35c2c1cf29cd 96 return;
mbed_official 390:35c2c1cf29cd 97 }
mbed_official 390:35c2c1cf29cd 98
mbed_official 390:35c2c1cf29cd 99 /**************************************************************************//**
mbed_official 390:35c2c1cf29cd 100 * Function Name: RZ_A1_IsClockMode0
mbed_official 390:35c2c1cf29cd 101 * @brief Query Clock Mode
mbed_official 390:35c2c1cf29cd 102 *
mbed_official 390:35c2c1cf29cd 103 * Description:<br>
mbed_official 390:35c2c1cf29cd 104 * Answer ClockMode0 or not
mbed_official 390:35c2c1cf29cd 105 * @param none
mbed_official 390:35c2c1cf29cd 106 * @retval true : clock mode 0
mbed_official 390:35c2c1cf29cd 107 * @retval false : clock mode 1
mbed_official 390:35c2c1cf29cd 108 ******************************************************************************/
mbed_official 390:35c2c1cf29cd 109 int RZ_A1_IsClockMode0(void)
mbed_official 390:35c2c1cf29cd 110 {
mbed_official 390:35c2c1cf29cd 111 /* ClockMode0 */
mbed_official 390:35c2c1cf29cd 112 return true;
mbed_official 390:35c2c1cf29cd 113 }
mbed_official 390:35c2c1cf29cd 114
mbed_official 390:35c2c1cf29cd 115 /**************************************************************************//**
mbed_official 390:35c2c1cf29cd 116 * Function Name: RZ_A1_InitBus
mbed_official 390:35c2c1cf29cd 117 * @brief Initialize Bus
mbed_official 390:35c2c1cf29cd 118 *
mbed_official 390:35c2c1cf29cd 119 * Description:<br>
mbed_official 390:35c2c1cf29cd 120 * Initialize CS0-CS3 pin and access timing
mbed_official 390:35c2c1cf29cd 121 * @param none
mbed_official 390:35c2c1cf29cd 122 * @retval none
mbed_official 390:35c2c1cf29cd 123 ******************************************************************************/
mbed_official 390:35c2c1cf29cd 124 void RZ_A1_InitBus(void)
mbed_official 390:35c2c1cf29cd 125 {
mbed_official 390:35c2c1cf29cd 126 /***********************************************************************/
mbed_official 390:35c2c1cf29cd 127 /* Set pin alternative mode of NOR_FLASH(CS0, CS1) and SDRAM(CS2, CS3) */
mbed_official 390:35c2c1cf29cd 128 /***********************************************************************/
mbed_official 390:35c2c1cf29cd 129
mbed_official 390:35c2c1cf29cd 130 /* PORT9 partly set to Alternative Mode 1
mbed_official 390:35c2c1cf29cd 131 P9_1(A25), P9_0(A24)
mbed_official 390:35c2c1cf29cd 132 */
mbed_official 390:35c2c1cf29cd 133 GPIO.PIBC9 &= ~(uint16_t)0x0003u;
mbed_official 390:35c2c1cf29cd 134 GPIO.PBDC9 &= ~(uint16_t)0x0003u;
mbed_official 390:35c2c1cf29cd 135 GPIO.PM9 |= (uint16_t)0x0003u;
mbed_official 390:35c2c1cf29cd 136 GPIO.PMC9 &= ~(uint16_t)0x0003u;
mbed_official 390:35c2c1cf29cd 137 GPIO.PIPC9 &= ~(uint16_t)0x0003u;
mbed_official 390:35c2c1cf29cd 138
mbed_official 390:35c2c1cf29cd 139 GPIO.PBDC9 &= ~(uint16_t)0x0003u;
mbed_official 390:35c2c1cf29cd 140 GPIO.PFC9 &= ~(uint16_t)0x0003u;
mbed_official 390:35c2c1cf29cd 141 GPIO.PFCE9 &= ~(uint16_t)0x0003u;
mbed_official 390:35c2c1cf29cd 142 GPIO.PFCAE9 &= ~(uint16_t)0x0003u;
mbed_official 390:35c2c1cf29cd 143
mbed_official 390:35c2c1cf29cd 144 GPIO.PIPC9 |= (uint16_t)0x0003u;
mbed_official 390:35c2c1cf29cd 145 GPIO.PMC9 |= (uint16_t)0x0003u;
mbed_official 390:35c2c1cf29cd 146
mbed_official 390:35c2c1cf29cd 147 /* PORT8 fully set to Alternative Mode 1
mbed_official 390:35c2c1cf29cd 148 P8_15(A23), P8_14(A22), P8_13(A21), P8_12(A20),
mbed_official 390:35c2c1cf29cd 149 P8_11(A19), P8_10(A18), P8_9(A17), P8_8(A16),
mbed_official 390:35c2c1cf29cd 150 P8_7(A15), P8_6(A14), P8_5(A13), P8_4(A12),
mbed_official 390:35c2c1cf29cd 151 P8_3(A11), P8_2(A10), P8_1(A9), P8_0(A8),
mbed_official 390:35c2c1cf29cd 152 */
mbed_official 390:35c2c1cf29cd 153 GPIO.PIBC8 = 0x0000u;
mbed_official 390:35c2c1cf29cd 154 GPIO.PBDC8 = 0x0000u;
mbed_official 390:35c2c1cf29cd 155 GPIO.PM8 = 0xffffu;
mbed_official 390:35c2c1cf29cd 156 GPIO.PMC8 = 0x0000u;
mbed_official 390:35c2c1cf29cd 157 GPIO.PIPC8 = 0x0000u;
mbed_official 390:35c2c1cf29cd 158
mbed_official 390:35c2c1cf29cd 159 GPIO.PBDC8 = 0x0000u;
mbed_official 390:35c2c1cf29cd 160 GPIO.PFC8 = 0x0000u;
mbed_official 390:35c2c1cf29cd 161 GPIO.PFCE8 = 0x0000u;
mbed_official 390:35c2c1cf29cd 162 GPIO.PFCAE8 = 0x0000u;
mbed_official 390:35c2c1cf29cd 163
mbed_official 390:35c2c1cf29cd 164 GPIO.PIPC8 = 0xffffu;
mbed_official 390:35c2c1cf29cd 165 GPIO.PMC8 = 0xffffu;
mbed_official 390:35c2c1cf29cd 166
mbed_official 390:35c2c1cf29cd 167 /* PORT7 fully set to Alternative Mode 1
mbed_official 390:35c2c1cf29cd 168 P7_15(A7), P7_14(A6), P7_13(A5), P7_12(A4),
mbed_official 390:35c2c1cf29cd 169 P7_11(A3), P7_10(A2), P7_9(A1), P7_8(RD#),
mbed_official 390:35c2c1cf29cd 170 P7_7(DQMLU#), P7_6(WE#0/DQMLL#), P7_5(RD/WR#), P7_4(CKE),
mbed_official 390:35c2c1cf29cd 171 P7_3(CAS#), P7_2(RAS#), P7_1(CS3#), P7_0(CS0#)
mbed_official 390:35c2c1cf29cd 172 */
mbed_official 390:35c2c1cf29cd 173 GPIO.PIBC7 = 0x0000u;
mbed_official 390:35c2c1cf29cd 174 GPIO.PBDC7 = 0x0000u;
mbed_official 390:35c2c1cf29cd 175 GPIO.PM7 = 0xffffu;
mbed_official 390:35c2c1cf29cd 176 GPIO.PMC7 = 0x0000u;
mbed_official 390:35c2c1cf29cd 177 GPIO.PIPC7 = 0x0000u;
mbed_official 390:35c2c1cf29cd 178
mbed_official 390:35c2c1cf29cd 179 GPIO.PBDC7 = 0x0000u;
mbed_official 390:35c2c1cf29cd 180 GPIO.PFC7 = 0x0000u;
mbed_official 390:35c2c1cf29cd 181 GPIO.PFCE7 = 0x0000u;
mbed_official 390:35c2c1cf29cd 182 GPIO.PFCAE7 = 0x0000u;
mbed_official 390:35c2c1cf29cd 183
mbed_official 390:35c2c1cf29cd 184 GPIO.PIPC7 = 0xffffu;
mbed_official 390:35c2c1cf29cd 185 GPIO.PMC7 = 0xffffu;
mbed_official 390:35c2c1cf29cd 186
mbed_official 390:35c2c1cf29cd 187 /* PORT6 fully set to Alternative Mode 1
mbed_official 390:35c2c1cf29cd 188 P6_15(D15), P6_14(D14), P6_13(D13), P6_12(D12),
mbed_official 390:35c2c1cf29cd 189 P6_11(D11), P6_10(D10), P6_9(D9), P6_8(D8),
mbed_official 390:35c2c1cf29cd 190 P6_7(D7), P6_6(D6), P6_5(D5), P6_4(D4),
mbed_official 390:35c2c1cf29cd 191 P6_3(D3), P6_2(D2), P6_1(D1), P6_0(D0)
mbed_official 390:35c2c1cf29cd 192 Alternative Mode 1
mbed_official 390:35c2c1cf29cd 193 */
mbed_official 390:35c2c1cf29cd 194 GPIO.PIBC6 = 0x0000u;
mbed_official 390:35c2c1cf29cd 195 GPIO.PBDC6 = 0x0000u;
mbed_official 390:35c2c1cf29cd 196 GPIO.PM6 = 0xffffu;
mbed_official 390:35c2c1cf29cd 197 GPIO.PMC6 = 0x0000u;
mbed_official 390:35c2c1cf29cd 198 GPIO.PIPC6 = 0x0000u;
mbed_official 390:35c2c1cf29cd 199
mbed_official 390:35c2c1cf29cd 200 GPIO.PBDC6 = 0xffffu;
mbed_official 390:35c2c1cf29cd 201 GPIO.PFC6 = 0x0000u;
mbed_official 390:35c2c1cf29cd 202 GPIO.PFCE6 = 0x0000u;
mbed_official 390:35c2c1cf29cd 203 GPIO.PFCAE6 = 0x0000u;
mbed_official 390:35c2c1cf29cd 204
mbed_official 390:35c2c1cf29cd 205 GPIO.PIPC6 = 0xffffu;
mbed_official 390:35c2c1cf29cd 206 GPIO.PMC6 = 0xffffu;
mbed_official 390:35c2c1cf29cd 207
mbed_official 390:35c2c1cf29cd 208 /* PORT5 partly set to Alternative Mode 6
mbed_official 390:35c2c1cf29cd 209 P5_8(CS2#),
mbed_official 390:35c2c1cf29cd 210 */
mbed_official 390:35c2c1cf29cd 211 GPIO.PIBC5 &= ~(uint16_t)0x0100u;
mbed_official 390:35c2c1cf29cd 212 GPIO.PBDC5 &= ~(uint16_t)0x0100u;
mbed_official 390:35c2c1cf29cd 213 GPIO.PM5 |= (uint16_t)0x0100u;
mbed_official 390:35c2c1cf29cd 214 GPIO.PMC5 &= ~(uint16_t)0x0100u;
mbed_official 390:35c2c1cf29cd 215 GPIO.PIPC5 &= ~(uint16_t)0x0100u;
mbed_official 390:35c2c1cf29cd 216
mbed_official 390:35c2c1cf29cd 217 GPIO.PBDC5 &= ~(uint16_t)0x0100u;
mbed_official 390:35c2c1cf29cd 218 GPIO.PFC5 |= (uint16_t)0x0100u;
mbed_official 390:35c2c1cf29cd 219 GPIO.PFCE5 &= ~(uint16_t)0x0100u;
mbed_official 390:35c2c1cf29cd 220 GPIO.PFCAE5 |= (uint16_t)0x0100u;
mbed_official 390:35c2c1cf29cd 221
mbed_official 390:35c2c1cf29cd 222 GPIO.PIPC5 |= (uint16_t)0x0100u;
mbed_official 390:35c2c1cf29cd 223 GPIO.PMC5 |= (uint16_t)0x0100u;
mbed_official 390:35c2c1cf29cd 224
mbed_official 390:35c2c1cf29cd 225 /* PORT3 partly set to Alternative Mode 7
mbed_official 390:35c2c1cf29cd 226 P3_7(CS1#),
mbed_official 390:35c2c1cf29cd 227 */
mbed_official 390:35c2c1cf29cd 228 GPIO.PIBC3 &= ~(uint16_t)0x0080u;
mbed_official 390:35c2c1cf29cd 229 GPIO.PBDC3 &= ~(uint16_t)0x0080u;
mbed_official 390:35c2c1cf29cd 230 GPIO.PM3 |= (uint16_t)0x0080u;
mbed_official 390:35c2c1cf29cd 231 GPIO.PMC3 &= ~(uint16_t)0x0080u;
mbed_official 390:35c2c1cf29cd 232 GPIO.PIPC3 &= ~(uint16_t)0x0080u;
mbed_official 390:35c2c1cf29cd 233
mbed_official 390:35c2c1cf29cd 234 GPIO.PBDC3 &= ~(uint16_t)0x0080u;
mbed_official 390:35c2c1cf29cd 235 GPIO.PFC3 &= ~(uint16_t)0x0080u;
mbed_official 390:35c2c1cf29cd 236 GPIO.PFCE3 |= (uint16_t)0x0080u;
mbed_official 390:35c2c1cf29cd 237 GPIO.PFCAE3 |= (uint16_t)0x0080u;
mbed_official 390:35c2c1cf29cd 238
mbed_official 390:35c2c1cf29cd 239 GPIO.PIPC3 |= (uint16_t)0x0080u;
mbed_official 390:35c2c1cf29cd 240 GPIO.PMC3 |= (uint16_t)0x0080u;
mbed_official 390:35c2c1cf29cd 241
mbed_official 390:35c2c1cf29cd 242 /***********************************************************************/
mbed_official 390:35c2c1cf29cd 243 /* Set bus access timing of NOR_FLASH(CS0, CS1) and SDRAM(CS2, CS3) */
mbed_official 390:35c2c1cf29cd 244 /***********************************************************************/
mbed_official 390:35c2c1cf29cd 245
mbed_official 390:35c2c1cf29cd 246 /* CSn Bus Control Register */
mbed_official 390:35c2c1cf29cd 247 BSC.CS0BCR = 0x10000c00;/* IWW=001b(1cyc),TYPE=000b(Normal),BSZ=10b(16bit)*/
mbed_official 390:35c2c1cf29cd 248 BSC.CS1BCR = 0x10000c00;/* IWW=001b(1cyc),TYPE=000b(Normal),BSZ=10b(16bit)*/
mbed_official 390:35c2c1cf29cd 249 BSC.CS2BCR = 0x00004c00;/* TYPE=100b(SDRAM), BSZ=10b(16bit) */
mbed_official 390:35c2c1cf29cd 250 BSC.CS3BCR = 0x00004c00;/* TYPE=100b(SDRAM), BSZ=10b(16bit) */
mbed_official 390:35c2c1cf29cd 251
mbed_official 390:35c2c1cf29cd 252 /* CS0 Wait Control Register(Normal type) */
mbed_official 390:35c2c1cf29cd 253 /* BAS=0b SW=01b(1.5cyc) WR=0110b(6cyc) WM=1b(ignore) HW=00b(0.5cyc) */
mbed_official 390:35c2c1cf29cd 254 BSC.CS0WCR = 0x00000b40;
mbed_official 390:35c2c1cf29cd 255 /* CS1 Wait Control Register(Normal type) */
mbed_official 390:35c2c1cf29cd 256 /* BAS=0b SW=01b(1.5cyc) WR=0110b(6cyc) WM=1b(ignore) HW=00b(0.5cyc) */
mbed_official 390:35c2c1cf29cd 257 BSC.CS1WCR = 0x00000b40;
mbed_official 390:35c2c1cf29cd 258
mbed_official 390:35c2c1cf29cd 259 /* CS2,3 Wait Control Register(SDRAM type) */
mbed_official 390:35c2c1cf29cd 260 BSC.CS2WCR = 0x00000480;/* A2CL=01b 2cycle */
mbed_official 390:35c2c1cf29cd 261 BSC.CS3WCR = 0x00002492;/* WTRP=01b 1cycle, WTRCD=01b 1cycle, A3CL=01b 2cycle, TRWL=10b 2cycle, WTRC=10b 5cycle */
mbed_official 390:35c2c1cf29cd 262
mbed_official 390:35c2c1cf29cd 263 /* SDRAM Control Register */
mbed_official 390:35c2c1cf29cd 264 BSC.SDCR = 0x00120812;
mbed_official 390:35c2c1cf29cd 265
mbed_official 390:35c2c1cf29cd 266 /* Refresh Timer Constant Register */
mbed_official 390:35c2c1cf29cd 267 BSC.RTCOR = 0xa55a0020;
mbed_official 390:35c2c1cf29cd 268
mbed_official 390:35c2c1cf29cd 269 /* Refresh Timer Control Status Register */
mbed_official 390:35c2c1cf29cd 270 BSC.RTCSR = 0xa55a0010;
mbed_official 390:35c2c1cf29cd 271
mbed_official 390:35c2c1cf29cd 272 /* Write SDRAM Mode Register */
mbed_official 390:35c2c1cf29cd 273 CS2_SDRAM_MODE_16BIT_CAS2_BR_BW = 0x0000;
mbed_official 390:35c2c1cf29cd 274 CS3_SDRAM_MODE_16BIT_CAS2_BR_BW = 0x0000;
mbed_official 390:35c2c1cf29cd 275
mbed_official 390:35c2c1cf29cd 276 return;
mbed_official 390:35c2c1cf29cd 277 }
mbed_official 390:35c2c1cf29cd 278
mbed_official 390:35c2c1cf29cd 279 /******************************************************************************
mbed_official 390:35c2c1cf29cd 280 End of file
mbed_official 390:35c2c1cf29cd 281 ******************************************************************************/