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Last commit 20 Feb 2019 by mbed official

targets/cmsis/TARGET_STM/TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc_ex.h@369:2e96f1b71984, 2014-10-27 (annotated)

Committer:
mbed_official
Date:
Mon Oct 27 09:45:07 2014 +0000
Revision:
369:2e96f1b71984
Parent:
226:b062af740e40 
Synchronized with git revision 2d1f64de28cfb25c0e602532e3ce5ad1d9accbed



Full URL: https://github.com/mbedmicro/mbed/commit/2d1f64de28cfb25c0e602532e3ce5ad1d9accbed/



CMSIS: NUCLEO_F401RE - Update STM32Cube driver

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 87:085cde657901 1 /**
mbed_official 87:085cde657901 2 ******************************************************************************
mbed_official 87:085cde657901 3 * @file stm32f4xx_hal_rcc_ex.h
mbed_official 87:085cde657901 4 * @author MCD Application Team
mbed_official 369:2e96f1b71984 5 * @version V1.1.0
mbed_official 369:2e96f1b71984 6 * @date 19-June-2014
mbed_official 87:085cde657901 7 * @brief Header file of RCC HAL Extension module.
mbed_official 87:085cde657901 8 ******************************************************************************
mbed_official 87:085cde657901 9 * @attention
mbed_official 87:085cde657901 10 *
mbed_official 87:085cde657901 11 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
mbed_official 87:085cde657901 12 *
mbed_official 87:085cde657901 13 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 87:085cde657901 14 * are permitted provided that the following conditions are met:
mbed_official 87:085cde657901 15 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 87:085cde657901 16 * this list of conditions and the following disclaimer.
mbed_official 87:085cde657901 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 87:085cde657901 18 * this list of conditions and the following disclaimer in the documentation
mbed_official 87:085cde657901 19 * and/or other materials provided with the distribution.
mbed_official 87:085cde657901 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 87:085cde657901 21 * may be used to endorse or promote products derived from this software
mbed_official 87:085cde657901 22 * without specific prior written permission.
mbed_official 87:085cde657901 23 *
mbed_official 87:085cde657901 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 87:085cde657901 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 87:085cde657901 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 87:085cde657901 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 87:085cde657901 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 87:085cde657901 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 87:085cde657901 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 87:085cde657901 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 87:085cde657901 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 87:085cde657901 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 87:085cde657901 34 *
mbed_official 87:085cde657901 35 ******************************************************************************
mbed_official 87:085cde657901 36 */
mbed_official 87:085cde657901 37
mbed_official 87:085cde657901 38 /* Define to prevent recursive inclusion -------------------------------------*/
mbed_official 87:085cde657901 39 #ifndef __STM32F4xx_HAL_RCC_EX_H
mbed_official 87:085cde657901 40 #define __STM32F4xx_HAL_RCC_EX_H
mbed_official 87:085cde657901 41
mbed_official 87:085cde657901 42 #ifdef __cplusplus
mbed_official 87:085cde657901 43 extern "C" {
mbed_official 87:085cde657901 44 #endif
mbed_official 87:085cde657901 45
mbed_official 87:085cde657901 46 /* Includes ------------------------------------------------------------------*/
mbed_official 87:085cde657901 47 #include "stm32f4xx_hal_def.h"
mbed_official 87:085cde657901 48
mbed_official 87:085cde657901 49 /** @addtogroup STM32F4xx_HAL_Driver
mbed_official 87:085cde657901 50 * @{
mbed_official 87:085cde657901 51 */
mbed_official 87:085cde657901 52
mbed_official 87:085cde657901 53 /** @addtogroup RCCEx
mbed_official 87:085cde657901 54 * @{
mbed_official 87:085cde657901 55 */
mbed_official 87:085cde657901 56
mbed_official 87:085cde657901 57 /* Exported types ------------------------------------------------------------*/
mbed_official 87:085cde657901 58 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
mbed_official 87:085cde657901 59 /**
mbed_official 87:085cde657901 60 * @brief PLLI2S Clock structure definition
mbed_official 87:085cde657901 61 */
mbed_official 87:085cde657901 62 typedef struct
mbed_official 87:085cde657901 63 {
mbed_official 226:b062af740e40 64 uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
mbed_official 226:b062af740e40 65 This parameter must be a number between Min_Data = 192 and Max_Data = 432.
mbed_official 87:085cde657901 66 This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
mbed_official 87:085cde657901 67
mbed_official 226:b062af740e40 68 uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock.
mbed_official 226:b062af740e40 69 This parameter must be a number between Min_Data = 2 and Max_Data = 7.
mbed_official 87:085cde657901 70 This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
mbed_official 87:085cde657901 71
mbed_official 87:085cde657901 72 uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI1 clock.
mbed_official 226:b062af740e40 73 This parameter must be a number between Min_Data = 2 and Max_Data = 15.
mbed_official 87:085cde657901 74 This parameter will be used only when PLLI2S is selected as Clock Source SAI */
mbed_official 87:085cde657901 75 }RCC_PLLI2SInitTypeDef;
mbed_official 87:085cde657901 76
mbed_official 87:085cde657901 77 /**
mbed_official 87:085cde657901 78 * @brief PLLSAI Clock structure definition
mbed_official 87:085cde657901 79 */
mbed_official 87:085cde657901 80 typedef struct
mbed_official 87:085cde657901 81 {
mbed_official 87:085cde657901 82 uint32_t PLLSAIN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
mbed_official 226:b062af740e40 83 This parameter must be a number between Min_Data = 192 and Max_Data = 432.
mbed_official 87:085cde657901 84 This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */
mbed_official 87:085cde657901 85
mbed_official 87:085cde657901 86 uint32_t PLLSAIQ; /*!< Specifies the division factor for SAI1 clock.
mbed_official 226:b062af740e40 87 This parameter must be a number between Min_Data = 2 and Max_Data = 15.
mbed_official 87:085cde657901 88 This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */
mbed_official 87:085cde657901 89
mbed_official 87:085cde657901 90 uint32_t PLLSAIR; /*!< specifies the division factor for LTDC clock
mbed_official 226:b062af740e40 91 This parameter must be a number between Min_Data = 2 and Max_Data = 7.
mbed_official 87:085cde657901 92 This parameter will be used only when PLLSAI is selected as Clock Source LTDC */
mbed_official 87:085cde657901 93
mbed_official 87:085cde657901 94 }RCC_PLLSAIInitTypeDef;
mbed_official 87:085cde657901 95 /**
mbed_official 87:085cde657901 96 * @brief RCC extended clocks structure definition
mbed_official 87:085cde657901 97 */
mbed_official 87:085cde657901 98 typedef struct
mbed_official 87:085cde657901 99 {
mbed_official 87:085cde657901 100 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
mbed_official 87:085cde657901 101 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
mbed_official 87:085cde657901 102
mbed_official 226:b062af740e40 103 RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters.
mbed_official 87:085cde657901 104 This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
mbed_official 87:085cde657901 105
mbed_official 226:b062af740e40 106 RCC_PLLSAIInitTypeDef PLLSAI; /*!< PLL SAI structure parameters.
mbed_official 87:085cde657901 107 This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC */
mbed_official 87:085cde657901 108
mbed_official 226:b062af740e40 109 uint32_t PLLI2SDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
mbed_official 87:085cde657901 110 This parameter must be a number between Min_Data = 1 and Max_Data = 32
mbed_official 87:085cde657901 111 This parameter will be used only when PLLI2S is selected as Clock Source SAI */
mbed_official 87:085cde657901 112
mbed_official 87:085cde657901 113 uint32_t PLLSAIDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
mbed_official 87:085cde657901 114 This parameter must be a number between Min_Data = 1 and Max_Data = 32
mbed_official 87:085cde657901 115 This parameter will be used only when PLLSAI is selected as Clock Source SAI */
mbed_official 87:085cde657901 116
mbed_official 87:085cde657901 117 uint32_t PLLSAIDivR; /*!< Specifies the PLLSAI division factor for LTDC clock.
mbed_official 87:085cde657901 118 This parameter must be one value of @ref RCCEx_PLLSAI_DIVR */
mbed_official 87:085cde657901 119
mbed_official 226:b062af740e40 120 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection.
mbed_official 87:085cde657901 121 This parameter can be a value of @ref RCC_RTC_Clock_Source */
mbed_official 87:085cde657901 122
mbed_official 226:b062af740e40 123 uint8_t TIMPresSelection; /*!< Specifies TIM Clock Prescalers Selection.
mbed_official 87:085cde657901 124 This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
mbed_official 87:085cde657901 125
mbed_official 87:085cde657901 126 }RCC_PeriphCLKInitTypeDef;
mbed_official 87:085cde657901 127 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
mbed_official 87:085cde657901 128
mbed_official 369:2e96f1b71984 129 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) ||\
mbed_official 369:2e96f1b71984 130 defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
mbed_official 87:085cde657901 131 /**
mbed_official 87:085cde657901 132 * @brief PLLI2S Clock structure definition
mbed_official 87:085cde657901 133 */
mbed_official 87:085cde657901 134 typedef struct
mbed_official 87:085cde657901 135 {
mbed_official 369:2e96f1b71984 136 #if defined(STM32F411xE)
mbed_official 369:2e96f1b71984 137 uint32_t PLLI2SM; /*!< PLLM: Division factor for PLLI2S VCO input clock.
mbed_official 369:2e96f1b71984 138 This parameter must be a number between Min_Data = 2 and Max_Data = 62 */
mbed_official 369:2e96f1b71984 139 #endif /* STM32F411xE */
mbed_official 369:2e96f1b71984 140
mbed_official 226:b062af740e40 141 uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
mbed_official 87:085cde657901 142 This parameter must be a number between Min_Data = 192 and Max_Data = 432
mbed_official 87:085cde657901 143 This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
mbed_official 87:085cde657901 144
mbed_official 226:b062af740e40 145 uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock.
mbed_official 226:b062af740e40 146 This parameter must be a number between Min_Data = 2 and Max_Data = 7.
mbed_official 87:085cde657901 147 This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
mbed_official 87:085cde657901 148
mbed_official 87:085cde657901 149 }RCC_PLLI2SInitTypeDef;
mbed_official 87:085cde657901 150
mbed_official 87:085cde657901 151
mbed_official 87:085cde657901 152 /**
mbed_official 87:085cde657901 153 * @brief RCC extended clocks structure definition
mbed_official 87:085cde657901 154 */
mbed_official 87:085cde657901 155 typedef struct
mbed_official 87:085cde657901 156 {
mbed_official 87:085cde657901 157 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
mbed_official 87:085cde657901 158 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
mbed_official 87:085cde657901 159
mbed_official 226:b062af740e40 160 RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters.
mbed_official 87:085cde657901 161 This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
mbed_official 87:085cde657901 162
mbed_official 226:b062af740e40 163 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection.
mbed_official 369:2e96f1b71984 164 This parameter can be a value of @ref RCC_RTC_Clock_Source */
mbed_official 87:085cde657901 165
mbed_official 87:085cde657901 166 }RCC_PeriphCLKInitTypeDef;
mbed_official 369:2e96f1b71984 167 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE */
mbed_official 87:085cde657901 168 /* Exported constants --------------------------------------------------------*/
mbed_official 87:085cde657901 169 /** @defgroup RCCEx_Exported_Constants
mbed_official 87:085cde657901 170 * @{
mbed_official 87:085cde657901 171 */
mbed_official 87:085cde657901 172
mbed_official 87:085cde657901 173 /** @defgroup RCCEx_Periph_Clock_Selection
mbed_official 87:085cde657901 174 * @{
mbed_official 87:085cde657901 175 */
mbed_official 87:085cde657901 176 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
mbed_official 87:085cde657901 177 #define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001)
mbed_official 87:085cde657901 178 #define RCC_PERIPHCLK_SAI_PLLI2S ((uint32_t)0x00000002)
mbed_official 87:085cde657901 179 #define RCC_PERIPHCLK_SAI_PLLSAI ((uint32_t)0x00000004)
mbed_official 87:085cde657901 180 #define RCC_PERIPHCLK_LTDC ((uint32_t)0x00000008)
mbed_official 87:085cde657901 181 #define RCC_PERIPHCLK_TIM ((uint32_t)0x00000010)
mbed_official 87:085cde657901 182 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00000020)
mbed_official 87:085cde657901 183 #define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x0000002F))
mbed_official 87:085cde657901 184 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
mbed_official 87:085cde657901 185
mbed_official 369:2e96f1b71984 186 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) ||\
mbed_official 369:2e96f1b71984 187 defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
mbed_official 87:085cde657901 188 #define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001)
mbed_official 87:085cde657901 189 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00000002)
mbed_official 87:085cde657901 190 #define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x00000003))
mbed_official 369:2e96f1b71984 191 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE */
mbed_official 87:085cde657901 192
mbed_official 87:085cde657901 193 /**
mbed_official 87:085cde657901 194 * @}
mbed_official 87:085cde657901 195 */
mbed_official 87:085cde657901 196
mbed_official 87:085cde657901 197 /** @defgroup RCCEx_BitAddress_AliasRegion
mbed_official 87:085cde657901 198 * @brief RCC registers bit address in the alias region
mbed_official 87:085cde657901 199 * @{
mbed_official 87:085cde657901 200 */
mbed_official 87:085cde657901 201 /* --- CR Register ---*/
mbed_official 87:085cde657901 202 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
mbed_official 87:085cde657901 203 /* Alias word address of PLLSAION bit */
mbed_official 87:085cde657901 204 #define PLLSAION_BitNumber 0x1C
mbed_official 87:085cde657901 205 #define CR_PLLSAION_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (PLLSAION_BitNumber * 4))
mbed_official 87:085cde657901 206
mbed_official 87:085cde657901 207 /* --- DCKCFGR Register ---*/
mbed_official 87:085cde657901 208 /* Alias word address of TIMPRE bit */
mbed_official 87:085cde657901 209 #define RCC_DCKCFGR_OFFSET (RCC_OFFSET + 0x8C)
mbed_official 87:085cde657901 210 #define TIMPRE_BitNumber 0x18
mbed_official 87:085cde657901 211 #define DCKCFGR_TIMPRE_BB (PERIPH_BB_BASE + (RCC_DCKCFGR_OFFSET * 32) + (TIMPRE_BitNumber * 4))
mbed_official 87:085cde657901 212 /**
mbed_official 87:085cde657901 213 * @}
mbed_official 87:085cde657901 214 */
mbed_official 87:085cde657901 215
mbed_official 87:085cde657901 216 /** @defgroup RCCEx_PLLI2S_Clock_Source
mbed_official 87:085cde657901 217 * @{
mbed_official 87:085cde657901 218 */
mbed_official 87:085cde657901 219 #define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
mbed_official 87:085cde657901 220 /**
mbed_official 87:085cde657901 221 * @}
mbed_official 87:085cde657901 222 */
mbed_official 87:085cde657901 223
mbed_official 87:085cde657901 224 /** @defgroup RCCEx_PLLSAI_Clock_Source
mbed_official 87:085cde657901 225 * @{
mbed_official 87:085cde657901 226 */
mbed_official 87:085cde657901 227 #define IS_RCC_PLLSAIN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
mbed_official 87:085cde657901 228 #define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
mbed_official 87:085cde657901 229 #define IS_RCC_PLLSAIR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
mbed_official 87:085cde657901 230 /**
mbed_official 87:085cde657901 231 * @}
mbed_official 87:085cde657901 232 */
mbed_official 87:085cde657901 233
mbed_official 87:085cde657901 234 /** @defgroup RCCEx_PLLSAI_DIVQ
mbed_official 87:085cde657901 235 * @{
mbed_official 87:085cde657901 236 */
mbed_official 87:085cde657901 237 #define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
mbed_official 87:085cde657901 238 /**
mbed_official 87:085cde657901 239 * @}
mbed_official 87:085cde657901 240 */
mbed_official 87:085cde657901 241
mbed_official 87:085cde657901 242 /** @defgroup RCCEx_PLLI2S_DIVQ
mbed_official 87:085cde657901 243 * @{
mbed_official 87:085cde657901 244 */
mbed_official 87:085cde657901 245 #define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
mbed_official 87:085cde657901 246
mbed_official 87:085cde657901 247 /**
mbed_official 87:085cde657901 248 * @}
mbed_official 87:085cde657901 249 */
mbed_official 87:085cde657901 250
mbed_official 87:085cde657901 251 /** @defgroup RCCEx_PLLSAI_DIVR
mbed_official 87:085cde657901 252 * @{
mbed_official 87:085cde657901 253 */
mbed_official 87:085cde657901 254 #define RCC_PLLSAIDIVR_2 ((uint32_t)0x00000000)
mbed_official 87:085cde657901 255 #define RCC_PLLSAIDIVR_4 ((uint32_t)0x00010000)
mbed_official 87:085cde657901 256 #define RCC_PLLSAIDIVR_8 ((uint32_t)0x00020000)
mbed_official 87:085cde657901 257 #define RCC_PLLSAIDIVR_16 ((uint32_t)0x00030000)
mbed_official 87:085cde657901 258 #define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDIVR_2) ||\
mbed_official 87:085cde657901 259 ((VALUE) == RCC_PLLSAIDIVR_4) ||\
mbed_official 87:085cde657901 260 ((VALUE) == RCC_PLLSAIDIVR_8) ||\
mbed_official 87:085cde657901 261 ((VALUE) == RCC_PLLSAIDIVR_16))
mbed_official 87:085cde657901 262
mbed_official 87:085cde657901 263 /**
mbed_official 87:085cde657901 264 * @}
mbed_official 87:085cde657901 265 */
mbed_official 87:085cde657901 266
mbed_official 87:085cde657901 267 /** @defgroup RCCEx_SAI_BlockA_Clock_Source
mbed_official 87:085cde657901 268 * @{
mbed_official 87:085cde657901 269 */
mbed_official 87:085cde657901 270 #define RCC_SAIACLKSOURCE_PLLSAI ((uint32_t)0x00000000)
mbed_official 87:085cde657901 271 #define RCC_SAIACLKSOURCE_PLLI2S ((uint32_t)0x00100000)
mbed_official 87:085cde657901 272 #define RCC_SAIACLKSOURCE_EXT ((uint32_t)0x00200000)
mbed_official 87:085cde657901 273 /**
mbed_official 87:085cde657901 274 * @}
mbed_official 87:085cde657901 275 */
mbed_official 87:085cde657901 276
mbed_official 87:085cde657901 277 /** @defgroup RCCEx_SAI_BlockB_Clock_Source
mbed_official 87:085cde657901 278 * @{
mbed_official 87:085cde657901 279 */
mbed_official 87:085cde657901 280 #define RCC_SAIBCLKSOURCE_PLLSAI ((uint32_t)0x00000000)
mbed_official 87:085cde657901 281 #define RCC_SAIBCLKSOURCE_PLLI2S ((uint32_t)0x00400000)
mbed_official 87:085cde657901 282 #define RCC_SAIBCLKSOURCE_EXT ((uint32_t)0x00800000)
mbed_official 87:085cde657901 283 /**
mbed_official 87:085cde657901 284 * @}
mbed_official 87:085cde657901 285 */
mbed_official 87:085cde657901 286
mbed_official 87:085cde657901 287 /** @defgroup RCCEx_TIM_PRescaler_Selection
mbed_official 87:085cde657901 288 * @{
mbed_official 87:085cde657901 289 */
mbed_official 87:085cde657901 290 #define RCC_TIMPRES_DESACTIVATED ((uint8_t)0x00)
mbed_official 87:085cde657901 291 #define RCC_TIMPRES_ACTIVATED ((uint8_t)0x01)
mbed_official 87:085cde657901 292 /**
mbed_official 87:085cde657901 293 * @}
mbed_official 87:085cde657901 294 */
mbed_official 87:085cde657901 295 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
mbed_official 369:2e96f1b71984 296
mbed_official 369:2e96f1b71984 297 #if defined(STM32F411xE)
mbed_official 369:2e96f1b71984 298 /** @defgroup RCCEx_PLLI2S_PLLI2SM
mbed_official 369:2e96f1b71984 299 * @{
mbed_official 369:2e96f1b71984 300 */
mbed_official 369:2e96f1b71984 301 #define IS_RCC_PLLI2SM_VALUE(VALUE) ((VALUE) <= 63)
mbed_official 87:085cde657901 302 /**
mbed_official 87:085cde657901 303 * @}
mbed_official 87:085cde657901 304 */
mbed_official 87:085cde657901 305
mbed_official 369:2e96f1b71984 306 /** @defgroup RCCEx_LSE_Dual_Mode_Selection
mbed_official 369:2e96f1b71984 307 * @{
mbed_official 369:2e96f1b71984 308 */
mbed_official 369:2e96f1b71984 309 #define RCC_LSE_LOWPOWER_MODE ((uint8_t)0x00)
mbed_official 369:2e96f1b71984 310 #define RCC_LSE_HIGHDRIVE_MODE ((uint8_t)0x01)
mbed_official 369:2e96f1b71984 311 #define IS_RCC_LSE_MODE(MODE) (((MODE) == RCC_LSE_LOWPOWER_MODE) ||\
mbed_official 369:2e96f1b71984 312 ((MODE) == RCC_LSE_HIGHDRIVE_MODE))
mbed_official 369:2e96f1b71984 313 /**
mbed_official 369:2e96f1b71984 314 * @}
mbed_official 369:2e96f1b71984 315 */
mbed_official 369:2e96f1b71984 316
mbed_official 369:2e96f1b71984 317 #endif /* STM32F411xE */
mbed_official 87:085cde657901 318 /**
mbed_official 87:085cde657901 319 * @}
mbed_official 87:085cde657901 320 */
mbed_official 87:085cde657901 321
mbed_official 87:085cde657901 322 /* Exported macro ------------------------------------------------------------*/
mbed_official 87:085cde657901 323
mbed_official 369:2e96f1b71984 324 /*----------------------------------- STM32F42xxx/STM32F43xxx----------------------------------*/
mbed_official 369:2e96f1b71984 325 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
mbed_official 87:085cde657901 326 /** @brief Enables or disables the AHB1 peripheral clock.
mbed_official 87:085cde657901 327 * @note After reset, the peripheral clock (used for registers read/write access)
mbed_official 87:085cde657901 328 * is disabled and the application software has to enable this clock before
mbed_official 87:085cde657901 329 * using it.
mbed_official 87:085cde657901 330 */
mbed_official 369:2e96f1b71984 331 #define __GPIOI_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOIEN))
mbed_official 369:2e96f1b71984 332 #define __GPIOF_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOFEN))
mbed_official 369:2e96f1b71984 333 #define __GPIOG_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOGEN))
mbed_official 369:2e96f1b71984 334 #define __GPIOJ_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOJEN))
mbed_official 369:2e96f1b71984 335 #define __GPIOK_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOKEN))
mbed_official 369:2e96f1b71984 336 #define __DMA2D_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_DMA2DEN))
mbed_official 369:2e96f1b71984 337 #define __ETHMAC_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_ETHMACEN))
mbed_official 369:2e96f1b71984 338 #define __ETHMACTX_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_ETHMACTXEN))
mbed_official 369:2e96f1b71984 339 #define __ETHMACRX_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_ETHMACRXEN))
mbed_official 369:2e96f1b71984 340 #define __ETHMACPTP_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_ETHMACPTPEN))
mbed_official 369:2e96f1b71984 341 #define __USB_OTG_HS_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_OTGHSEN))
mbed_official 369:2e96f1b71984 342 #define __USB_OTG_HS_ULPI_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_OTGHSULPIEN))
mbed_official 87:085cde657901 343
mbed_official 369:2e96f1b71984 344 #define __GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
mbed_official 369:2e96f1b71984 345 #define __GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
mbed_official 369:2e96f1b71984 346 #define __GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN))
mbed_official 369:2e96f1b71984 347 #define __GPIOJ_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOJEN))
mbed_official 369:2e96f1b71984 348 #define __GPIOK_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOKEN))
mbed_official 369:2e96f1b71984 349 #define __DMA2D_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2DEN))
mbed_official 369:2e96f1b71984 350 #define __ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN))
mbed_official 369:2e96f1b71984 351 #define __ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN))
mbed_official 369:2e96f1b71984 352 #define __ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN))
mbed_official 369:2e96f1b71984 353 #define __ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN))
mbed_official 369:2e96f1b71984 354 #define __USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
mbed_official 369:2e96f1b71984 355 #define __USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
mbed_official 369:2e96f1b71984 356
mbed_official 369:2e96f1b71984 357 /**
mbed_official 369:2e96f1b71984 358 * @brief Enable ETHERNET clock.
mbed_official 369:2e96f1b71984 359 */
mbed_official 369:2e96f1b71984 360 #define __ETH_CLK_ENABLE() do { \
mbed_official 369:2e96f1b71984 361 __ETHMAC_CLK_ENABLE(); \
mbed_official 369:2e96f1b71984 362 __ETHMACTX_CLK_ENABLE(); \
mbed_official 369:2e96f1b71984 363 __ETHMACRX_CLK_ENABLE(); \
mbed_official 369:2e96f1b71984 364 } while(0)
mbed_official 369:2e96f1b71984 365 /**
mbed_official 369:2e96f1b71984 366 * @brief Disable ETHERNET clock.
mbed_official 369:2e96f1b71984 367 */
mbed_official 369:2e96f1b71984 368 #define __ETH_CLK_DISABLE() do { \
mbed_official 369:2e96f1b71984 369 __ETHMACTX_CLK_DISABLE(); \
mbed_official 369:2e96f1b71984 370 __ETHMACRX_CLK_DISABLE(); \
mbed_official 369:2e96f1b71984 371 __ETHMAC_CLK_DISABLE(); \
mbed_official 369:2e96f1b71984 372 } while(0)
mbed_official 369:2e96f1b71984 373
mbed_official 369:2e96f1b71984 374 /** @brief Enable or disable the AHB2 peripheral clock.
mbed_official 369:2e96f1b71984 375 * @note After reset, the peripheral clock (used for registers read/write access)
mbed_official 369:2e96f1b71984 376 * is disabled and the application software has to enable this clock before
mbed_official 369:2e96f1b71984 377 * using it.
mbed_official 369:2e96f1b71984 378 */
mbed_official 369:2e96f1b71984 379
mbed_official 369:2e96f1b71984 380 #define __DCMI_CLK_ENABLE() (RCC->AHB2ENR |= (RCC_AHB2ENR_DCMIEN))
mbed_official 369:2e96f1b71984 381 #define __DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
mbed_official 369:2e96f1b71984 382
mbed_official 369:2e96f1b71984 383 #if defined(STM32F437xx)|| defined(STM32F439xx)
mbed_official 369:2e96f1b71984 384 #define __CRYP_CLK_ENABLE() (RCC->AHB2ENR |= (RCC_AHB2ENR_CRYPEN))
mbed_official 369:2e96f1b71984 385 #define __HASH_CLK_ENABLE() (RCC->AHB2ENR |= (RCC_AHB2ENR_HASHEN))
mbed_official 369:2e96f1b71984 386
mbed_official 369:2e96f1b71984 387 #define __CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN))
mbed_official 369:2e96f1b71984 388 #define __HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN))
mbed_official 369:2e96f1b71984 389 #endif /* STM32F437xx || STM32F439xx */
mbed_official 369:2e96f1b71984 390
mbed_official 369:2e96f1b71984 391 /** @brief Enables or disables the AHB3 peripheral clock.
mbed_official 369:2e96f1b71984 392 * @note After reset, the peripheral clock (used for registers read/write access)
mbed_official 369:2e96f1b71984 393 * is disabled and the application software has to enable this clock before
mbed_official 369:2e96f1b71984 394 * using it.
mbed_official 369:2e96f1b71984 395 */
mbed_official 369:2e96f1b71984 396 #define __FMC_CLK_ENABLE() (RCC->AHB3ENR |= (RCC_AHB3ENR_FMCEN))
mbed_official 369:2e96f1b71984 397 #define __FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN))
mbed_official 369:2e96f1b71984 398
mbed_official 369:2e96f1b71984 399 /** @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
mbed_official 369:2e96f1b71984 400 * @note After reset, the peripheral clock (used for registers read/write access)
mbed_official 369:2e96f1b71984 401 * is disabled and the application software has to enable this clock before
mbed_official 369:2e96f1b71984 402 * using it.
mbed_official 369:2e96f1b71984 403 */
mbed_official 369:2e96f1b71984 404 #define __TIM6_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM6EN))
mbed_official 369:2e96f1b71984 405 #define __TIM7_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM7EN))
mbed_official 369:2e96f1b71984 406 #define __TIM12_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM12EN))
mbed_official 369:2e96f1b71984 407 #define __TIM13_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM13EN))
mbed_official 369:2e96f1b71984 408 #define __TIM14_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM14EN))
mbed_official 369:2e96f1b71984 409 #define __WWDG_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_WWDGEN))
mbed_official 369:2e96f1b71984 410 #define __USART3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART3EN))
mbed_official 369:2e96f1b71984 411 #define __UART4_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_UART4EN))
mbed_official 369:2e96f1b71984 412 #define __UART5_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_UART5EN))
mbed_official 369:2e96f1b71984 413 #define __CAN1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_CAN1EN))
mbed_official 369:2e96f1b71984 414 #define __CAN2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_CAN2EN))
mbed_official 369:2e96f1b71984 415 #define __DAC_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_DACEN))
mbed_official 369:2e96f1b71984 416 #define __UART7_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_UART7EN))
mbed_official 369:2e96f1b71984 417 #define __UART8_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_UART8EN))
mbed_official 369:2e96f1b71984 418
mbed_official 369:2e96f1b71984 419 #define __TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
mbed_official 369:2e96f1b71984 420 #define __TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
mbed_official 369:2e96f1b71984 421 #define __TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
mbed_official 369:2e96f1b71984 422 #define __TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
mbed_official 369:2e96f1b71984 423 #define __TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
mbed_official 369:2e96f1b71984 424 #define __WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
mbed_official 369:2e96f1b71984 425 #define __USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
mbed_official 369:2e96f1b71984 426 #define __UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
mbed_official 369:2e96f1b71984 427 #define __UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
mbed_official 369:2e96f1b71984 428 #define __CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
mbed_official 369:2e96f1b71984 429 #define __CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
mbed_official 369:2e96f1b71984 430 #define __DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
mbed_official 369:2e96f1b71984 431 #define __UART7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN))
mbed_official 369:2e96f1b71984 432 #define __UART8_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN))
mbed_official 369:2e96f1b71984 433
mbed_official 369:2e96f1b71984 434 /** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
mbed_official 369:2e96f1b71984 435 * @note After reset, the peripheral clock (used for registers read/write access)
mbed_official 369:2e96f1b71984 436 * is disabled and the application software has to enable this clock before
mbed_official 369:2e96f1b71984 437 * using it.
mbed_official 369:2e96f1b71984 438 */
mbed_official 369:2e96f1b71984 439 #define __TIM8_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM8EN))
mbed_official 369:2e96f1b71984 440 #define __ADC2_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_ADC2EN))
mbed_official 369:2e96f1b71984 441 #define __ADC3_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_ADC3EN))
mbed_official 369:2e96f1b71984 442 #define __SPI5_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SPI5EN))
mbed_official 369:2e96f1b71984 443 #define __SPI6_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SPI6EN))
mbed_official 369:2e96f1b71984 444 #define __SAI1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SAI1EN))
mbed_official 369:2e96f1b71984 445
mbed_official 369:2e96f1b71984 446 #define __TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
mbed_official 369:2e96f1b71984 447 #define __ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
mbed_official 369:2e96f1b71984 448 #define __ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
mbed_official 369:2e96f1b71984 449 #define __SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
mbed_official 369:2e96f1b71984 450 #define __SPI6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI6EN))
mbed_official 369:2e96f1b71984 451 #define __SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))
mbed_official 369:2e96f1b71984 452
mbed_official 369:2e96f1b71984 453 #if defined(STM32F429xx)|| defined(STM32F439xx)
mbed_official 369:2e96f1b71984 454 #define __LTDC_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_LTDCEN))
mbed_official 369:2e96f1b71984 455
mbed_official 369:2e96f1b71984 456 #define __LTDC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_LTDCEN))
mbed_official 369:2e96f1b71984 457 #endif /* STM32F429xx || STM32F439xx */
mbed_official 369:2e96f1b71984 458
mbed_official 369:2e96f1b71984 459 /** @brief Force or release AHB1 peripheral reset.
mbed_official 369:2e96f1b71984 460 */
mbed_official 369:2e96f1b71984 461 #define __GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST))
mbed_official 369:2e96f1b71984 462 #define __GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST))
mbed_official 369:2e96f1b71984 463 #define __GPIOI_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOIRST))
mbed_official 369:2e96f1b71984 464 #define __ETHMAC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETHMACRST))
mbed_official 369:2e96f1b71984 465 #define __OTGHS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST))
mbed_official 369:2e96f1b71984 466 #define __GPIOJ_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOJRST))
mbed_official 369:2e96f1b71984 467 #define __GPIOK_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOKRST))
mbed_official 369:2e96f1b71984 468 #define __DMA2D_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2DRST))
mbed_official 369:2e96f1b71984 469
mbed_official 369:2e96f1b71984 470 #define __GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
mbed_official 369:2e96f1b71984 471 #define __GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
mbed_official 369:2e96f1b71984 472 #define __GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
mbed_official 369:2e96f1b71984 473 #define __ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST))
mbed_official 369:2e96f1b71984 474 #define __OTGHS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
mbed_official 369:2e96f1b71984 475 #define __GPIOJ_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOJRST))
mbed_official 369:2e96f1b71984 476 #define __GPIOK_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOKRST))
mbed_official 369:2e96f1b71984 477 #define __DMA2D_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2DRST))
mbed_official 369:2e96f1b71984 478
mbed_official 369:2e96f1b71984 479 /** @brief Force or release AHB2 peripheral reset.
mbed_official 369:2e96f1b71984 480 */
mbed_official 369:2e96f1b71984 481 #define __DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST))
mbed_official 369:2e96f1b71984 482 #define __DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
mbed_official 369:2e96f1b71984 483
mbed_official 369:2e96f1b71984 484 #if defined(STM32F437xx)|| defined(STM32F439xx)
mbed_official 369:2e96f1b71984 485 #define __CRYP_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST))
mbed_official 369:2e96f1b71984 486 #define __HASH_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST))
mbed_official 369:2e96f1b71984 487
mbed_official 369:2e96f1b71984 488 #define __CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST))
mbed_official 369:2e96f1b71984 489 #define __HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST))
mbed_official 369:2e96f1b71984 490 #endif /* STM32F437xx || STM32F439xx */
mbed_official 369:2e96f1b71984 491
mbed_official 369:2e96f1b71984 492 /** @brief Force or release AHB3 peripheral reset
mbed_official 369:2e96f1b71984 493 */
mbed_official 369:2e96f1b71984 494 #define __FMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST))
mbed_official 369:2e96f1b71984 495 #define __FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST))
mbed_official 369:2e96f1b71984 496
mbed_official 369:2e96f1b71984 497 /** @brief Force or release APB1 peripheral reset.
mbed_official 369:2e96f1b71984 498 */
mbed_official 369:2e96f1b71984 499 #define __TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
mbed_official 369:2e96f1b71984 500 #define __TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
mbed_official 369:2e96f1b71984 501 #define __TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
mbed_official 369:2e96f1b71984 502 #define __TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
mbed_official 369:2e96f1b71984 503 #define __TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
mbed_official 369:2e96f1b71984 504 #define __USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
mbed_official 369:2e96f1b71984 505 #define __UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
mbed_official 369:2e96f1b71984 506 #define __UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
mbed_official 369:2e96f1b71984 507 #define __CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST))
mbed_official 369:2e96f1b71984 508 #define __CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST))
mbed_official 369:2e96f1b71984 509 #define __DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
mbed_official 369:2e96f1b71984 510 #define __UART7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART7RST))
mbed_official 369:2e96f1b71984 511 #define __UART8_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART8RST))
mbed_official 369:2e96f1b71984 512
mbed_official 369:2e96f1b71984 513 #define __TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
mbed_official 369:2e96f1b71984 514 #define __TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
mbed_official 369:2e96f1b71984 515 #define __TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
mbed_official 369:2e96f1b71984 516 #define __TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
mbed_official 369:2e96f1b71984 517 #define __TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
mbed_official 369:2e96f1b71984 518 #define __USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
mbed_official 369:2e96f1b71984 519 #define __UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
mbed_official 369:2e96f1b71984 520 #define __UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
mbed_official 369:2e96f1b71984 521 #define __CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
mbed_official 369:2e96f1b71984 522 #define __CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
mbed_official 369:2e96f1b71984 523 #define __DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
mbed_official 369:2e96f1b71984 524 #define __UART7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART7RST))
mbed_official 369:2e96f1b71984 525 #define __UART8_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST))
mbed_official 369:2e96f1b71984 526
mbed_official 369:2e96f1b71984 527 /** @brief Force or release APB2 peripheral reset.
mbed_official 369:2e96f1b71984 528 */
mbed_official 369:2e96f1b71984 529 #define __TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))
mbed_official 369:2e96f1b71984 530 #define __SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST))
mbed_official 369:2e96f1b71984 531 #define __SPI6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI6RST))
mbed_official 369:2e96f1b71984 532 #define __SAI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST))
mbed_official 369:2e96f1b71984 533
mbed_official 369:2e96f1b71984 534 #define __TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
mbed_official 369:2e96f1b71984 535 #define __SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
mbed_official 369:2e96f1b71984 536 #define __SPI6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI6RST))
mbed_official 369:2e96f1b71984 537 #define __SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST))
mbed_official 369:2e96f1b71984 538
mbed_official 369:2e96f1b71984 539 #if defined(STM32F429xx)|| defined(STM32F439xx)
mbed_official 369:2e96f1b71984 540 #define __LTDC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_LTDCRST))
mbed_official 369:2e96f1b71984 541 #define __LTDC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_LTDCRST))
mbed_official 369:2e96f1b71984 542 #endif /* STM32F429xx|| STM32F439xx */
mbed_official 369:2e96f1b71984 543
mbed_official 369:2e96f1b71984 544 /** @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
mbed_official 369:2e96f1b71984 545 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
mbed_official 369:2e96f1b71984 546 * power consumption.
mbed_official 369:2e96f1b71984 547 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
mbed_official 369:2e96f1b71984 548 * @note By default, all peripheral clocks are enabled during SLEEP mode.
mbed_official 369:2e96f1b71984 549 */
mbed_official 369:2e96f1b71984 550 #define __GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN))
mbed_official 369:2e96f1b71984 551 #define __GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN))
mbed_official 369:2e96f1b71984 552 #define __GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOILPEN))
mbed_official 369:2e96f1b71984 553 #define __SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN))
mbed_official 369:2e96f1b71984 554 #define __ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACLPEN))
mbed_official 369:2e96f1b71984 555 #define __ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACTXLPEN))
mbed_official 369:2e96f1b71984 556 #define __ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACRXLPEN))
mbed_official 369:2e96f1b71984 557 #define __ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACPTPLPEN))
mbed_official 369:2e96f1b71984 558 #define __OTGHS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN))
mbed_official 369:2e96f1b71984 559 #define __OTGHSULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN))
mbed_official 369:2e96f1b71984 560 #define __GPIOJ_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOJLPEN))
mbed_official 369:2e96f1b71984 561 #define __GPIOK_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOKLPEN))
mbed_official 369:2e96f1b71984 562 #define __SRAM3_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM3LPEN))
mbed_official 369:2e96f1b71984 563 #define __DMA2D_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2DLPEN))
mbed_official 369:2e96f1b71984 564
mbed_official 369:2e96f1b71984 565 #define __GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
mbed_official 369:2e96f1b71984 566 #define __GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
mbed_official 369:2e96f1b71984 567 #define __GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN))
mbed_official 369:2e96f1b71984 568 #define __SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
mbed_official 369:2e96f1b71984 569 #define __ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN))
mbed_official 369:2e96f1b71984 570 #define __ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN))
mbed_official 369:2e96f1b71984 571 #define __ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN))
mbed_official 369:2e96f1b71984 572 #define __ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN))
mbed_official 369:2e96f1b71984 573 #define __OTGHS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
mbed_official 369:2e96f1b71984 574 #define __OTGHSULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
mbed_official 369:2e96f1b71984 575 #define __GPIOJ_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOJLPEN))
mbed_official 369:2e96f1b71984 576 #define __GPIOK_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOKLPEN))
mbed_official 369:2e96f1b71984 577 #define __DMA2D_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2DLPEN))
mbed_official 369:2e96f1b71984 578
mbed_official 369:2e96f1b71984 579 /** @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
mbed_official 369:2e96f1b71984 580 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
mbed_official 369:2e96f1b71984 581 * power consumption.
mbed_official 369:2e96f1b71984 582 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
mbed_official 369:2e96f1b71984 583 * @note By default, all peripheral clocks are enabled during SLEEP mode.
mbed_official 369:2e96f1b71984 584 */
mbed_official 369:2e96f1b71984 585 #define __DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))
mbed_official 369:2e96f1b71984 586 #define __DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
mbed_official 369:2e96f1b71984 587
mbed_official 369:2e96f1b71984 588 #if defined(STM32F437xx)|| defined(STM32F439xx)
mbed_official 369:2e96f1b71984 589 #define __CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN))
mbed_official 369:2e96f1b71984 590 #define __HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN))
mbed_official 369:2e96f1b71984 591
mbed_official 369:2e96f1b71984 592 #define __CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN))
mbed_official 369:2e96f1b71984 593 #define __HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN))
mbed_official 369:2e96f1b71984 594 #endif /* STM32F437xx || STM32F439xx */
mbed_official 369:2e96f1b71984 595
mbed_official 369:2e96f1b71984 596 /** @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
mbed_official 369:2e96f1b71984 597 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
mbed_official 369:2e96f1b71984 598 * power consumption.
mbed_official 369:2e96f1b71984 599 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
mbed_official 369:2e96f1b71984 600 * @note By default, all peripheral clocks are enabled during SLEEP mode.
mbed_official 369:2e96f1b71984 601 */
mbed_official 369:2e96f1b71984 602 #define __FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN))
mbed_official 369:2e96f1b71984 603 #define __FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN))
mbed_official 369:2e96f1b71984 604
mbed_official 369:2e96f1b71984 605 /** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
mbed_official 369:2e96f1b71984 606 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
mbed_official 369:2e96f1b71984 607 * power consumption.
mbed_official 369:2e96f1b71984 608 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
mbed_official 369:2e96f1b71984 609 * @note By default, all peripheral clocks are enabled during SLEEP mode.
mbed_official 369:2e96f1b71984 610 */
mbed_official 369:2e96f1b71984 611 #define __TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN))
mbed_official 369:2e96f1b71984 612 #define __TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN))
mbed_official 369:2e96f1b71984 613 #define __TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN))
mbed_official 369:2e96f1b71984 614 #define __TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN))
mbed_official 369:2e96f1b71984 615 #define __TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN))
mbed_official 369:2e96f1b71984 616 #define __USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN))
mbed_official 369:2e96f1b71984 617 #define __UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN))
mbed_official 369:2e96f1b71984 618 #define __UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN))
mbed_official 369:2e96f1b71984 619 #define __CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN))
mbed_official 369:2e96f1b71984 620 #define __CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN))
mbed_official 369:2e96f1b71984 621 #define __DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN))
mbed_official 369:2e96f1b71984 622 #define __UART7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART7LPEN))
mbed_official 369:2e96f1b71984 623 #define __UART8_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART8LPEN))
mbed_official 369:2e96f1b71984 624
mbed_official 369:2e96f1b71984 625 #define __TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
mbed_official 369:2e96f1b71984 626 #define __TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
mbed_official 369:2e96f1b71984 627 #define __TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
mbed_official 369:2e96f1b71984 628 #define __TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
mbed_official 369:2e96f1b71984 629 #define __TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
mbed_official 369:2e96f1b71984 630 #define __USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
mbed_official 369:2e96f1b71984 631 #define __UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
mbed_official 369:2e96f1b71984 632 #define __UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
mbed_official 369:2e96f1b71984 633 #define __CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
mbed_official 369:2e96f1b71984 634 #define __CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
mbed_official 369:2e96f1b71984 635 #define __DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
mbed_official 369:2e96f1b71984 636 #define __UART7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN))
mbed_official 369:2e96f1b71984 637 #define __UART8_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN))
mbed_official 369:2e96f1b71984 638
mbed_official 369:2e96f1b71984 639 /** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
mbed_official 369:2e96f1b71984 640 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
mbed_official 369:2e96f1b71984 641 * power consumption.
mbed_official 369:2e96f1b71984 642 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
mbed_official 369:2e96f1b71984 643 * @note By default, all peripheral clocks are enabled during SLEEP mode.
mbed_official 369:2e96f1b71984 644 */
mbed_official 369:2e96f1b71984 645 #define __TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN))
mbed_official 369:2e96f1b71984 646 #define __ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN))
mbed_official 369:2e96f1b71984 647 #define __ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN))
mbed_official 369:2e96f1b71984 648 #define __SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN))
mbed_official 369:2e96f1b71984 649 #define __SPI6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI6LPEN))
mbed_official 369:2e96f1b71984 650 #define __SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN))
mbed_official 369:2e96f1b71984 651
mbed_official 369:2e96f1b71984 652 #define __TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
mbed_official 369:2e96f1b71984 653 #define __ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
mbed_official 369:2e96f1b71984 654 #define __ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
mbed_official 369:2e96f1b71984 655 #define __SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
mbed_official 369:2e96f1b71984 656 #define __SPI6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI6LPEN))
mbed_official 369:2e96f1b71984 657 #define __SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN))
mbed_official 369:2e96f1b71984 658
mbed_official 369:2e96f1b71984 659 #if defined(STM32F429xx)|| defined(STM32F439xx)
mbed_official 369:2e96f1b71984 660 #define __LTDC_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_LTDCLPEN))
mbed_official 369:2e96f1b71984 661
mbed_official 369:2e96f1b71984 662 #define __LTDC_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_LTDCLPEN))
mbed_official 369:2e96f1b71984 663 #endif /* STM32F429xx || STM32F439xx */
mbed_official 369:2e96f1b71984 664 #endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */
mbed_official 369:2e96f1b71984 665 /*---------------------------------------------------------------------------------------------*/
mbed_official 369:2e96f1b71984 666
mbed_official 369:2e96f1b71984 667 /*----------------------------------- STM32F40xxx/STM32F41xxx----------------------------------*/
mbed_official 369:2e96f1b71984 668 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
mbed_official 369:2e96f1b71984 669 /** @brief Enables or disables the AHB1 peripheral clock.
mbed_official 369:2e96f1b71984 670 * @note After reset, the peripheral clock (used for registers read/write access)
mbed_official 369:2e96f1b71984 671 * is disabled and the application software has to enable this clock before
mbed_official 369:2e96f1b71984 672 * using it.
mbed_official 369:2e96f1b71984 673 */
mbed_official 369:2e96f1b71984 674 #define __GPIOI_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOIEN))
mbed_official 369:2e96f1b71984 675 #define __GPIOF_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOFEN))
mbed_official 369:2e96f1b71984 676 #define __GPIOG_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_GPIOGEN))
mbed_official 369:2e96f1b71984 677 #define __USB_OTG_HS_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_OTGHSEN))
mbed_official 369:2e96f1b71984 678 #define __USB_OTG_HS_ULPI_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_OTGHSULPIEN))
mbed_official 369:2e96f1b71984 679
mbed_official 369:2e96f1b71984 680 #define __GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
mbed_official 369:2e96f1b71984 681 #define __GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
mbed_official 369:2e96f1b71984 682 #define __GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN))
mbed_official 369:2e96f1b71984 683 #define __USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
mbed_official 369:2e96f1b71984 684 #define __USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
mbed_official 369:2e96f1b71984 685
mbed_official 369:2e96f1b71984 686 #if defined(STM32F407xx)|| defined(STM32F417xx)
mbed_official 369:2e96f1b71984 687 /**
mbed_official 369:2e96f1b71984 688 * @brief Enable ETHERNET clock.
mbed_official 369:2e96f1b71984 689 */
mbed_official 87:085cde657901 690 #define __ETHMAC_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_ETHMACEN))
mbed_official 87:085cde657901 691 #define __ETHMACTX_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_ETHMACTXEN))
mbed_official 87:085cde657901 692 #define __ETHMACRX_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_ETHMACRXEN))
mbed_official 369:2e96f1b71984 693 #define __ETHMACPTP_CLK_ENABLE() (RCC->AHB1ENR |= (RCC_AHB1ENR_ETHMACPTPEN))
mbed_official 87:085cde657901 694 #define __ETH_CLK_ENABLE() do { \
mbed_official 87:085cde657901 695 __ETHMAC_CLK_ENABLE(); \
mbed_official 87:085cde657901 696 __ETHMACTX_CLK_ENABLE(); \
mbed_official 87:085cde657901 697 __ETHMACRX_CLK_ENABLE(); \
mbed_official 87:085cde657901 698 } while(0)
mbed_official 87:085cde657901 699
mbed_official 87:085cde657901 700 /**
mbed_official 87:085cde657901 701 * @brief Disable ETHERNET clock.
mbed_official 87:085cde657901 702 */
mbed_official 369:2e96f1b71984 703 #define __ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN))
mbed_official 369:2e96f1b71984 704 #define __ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN))
mbed_official 369:2e96f1b71984 705 #define __ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN))
mbed_official 369:2e96f1b71984 706 #define __ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN))
mbed_official 87:085cde657901 707 #define __ETH_CLK_DISABLE() do { \
mbed_official 87:085cde657901 708 __ETHMACTX_CLK_DISABLE(); \
mbed_official 87:085cde657901 709 __ETHMACRX_CLK_DISABLE(); \
mbed_official 87:085cde657901 710 __ETHMAC_CLK_DISABLE(); \
mbed_official 87:085cde657901 711 } while(0)
mbed_official 369:2e96f1b71984 712 #endif /* STM32F407xx || STM32F417xx */
mbed_official 87:085cde657901 713
mbed_official 87:085cde657901 714 /** @brief Enable or disable the AHB2 peripheral clock.
mbed_official 87:085cde657901 715 * @note After reset, the peripheral clock (used for registers read/write access)
mbed_official 87:085cde657901 716 * is disabled and the application software has to enable this clock before
mbed_official 87:085cde657901 717 * using it.
mbed_official 87:085cde657901 718 */
mbed_official 369:2e96f1b71984 719 #if defined(STM32F407xx)|| defined(STM32F417xx)
mbed_official 87:085cde657901 720 #define __DCMI_CLK_ENABLE() (RCC->AHB2ENR |= (RCC_AHB2ENR_DCMIEN))
mbed_official 87:085cde657901 721 #define __DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
mbed_official 369:2e96f1b71984 722 #endif /* STM32F407xx || STM32F417xx */
mbed_official 87:085cde657901 723
mbed_official 369:2e96f1b71984 724 #if defined(STM32F415xx) || defined(STM32F417xx)
mbed_official 87:085cde657901 725 #define __CRYP_CLK_ENABLE() (RCC->AHB2ENR |= (RCC_AHB2ENR_CRYPEN))
mbed_official 87:085cde657901 726 #define __HASH_CLK_ENABLE() (RCC->AHB2ENR |= (RCC_AHB2ENR_HASHEN))
mbed_official 87:085cde657901 727
mbed_official 87:085cde657901 728 #define __CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN))
mbed_official 87:085cde657901 729 #define __HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN))
mbed_official 369:2e96f1b71984 730 #endif /* STM32F415xx || STM32F417xx */
mbed_official 87:085cde657901 731
mbed_official 87:085cde657901 732 /** @brief Enables or disables the AHB3 peripheral clock.
mbed_official 87:085cde657901 733 * @note After reset, the peripheral clock (used for registers read/write access)
mbed_official 87:085cde657901 734 * is disabled and the application software has to enable this clock before
mbed_official 87:085cde657901 735 * using it.
mbed_official 87:085cde657901 736 */
mbed_official 87:085cde657901 737 #define __FSMC_CLK_ENABLE() (RCC->AHB3ENR |= (RCC_AHB3ENR_FSMCEN))
mbed_official 87:085cde657901 738 #define __FSMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FSMCEN))
mbed_official 87:085cde657901 739
mbed_official 87:085cde657901 740 /** @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
mbed_official 87:085cde657901 741 * @note After reset, the peripheral clock (used for registers read/write access)
mbed_official 87:085cde657901 742 * is disabled and the application software has to enable this clock before
mbed_official 87:085cde657901 743 * using it.
mbed_official 87:085cde657901 744 */
mbed_official 87:085cde657901 745 #define __TIM6_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM6EN))
mbed_official 87:085cde657901 746 #define __TIM7_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM7EN))
mbed_official 87:085cde657901 747 #define __TIM12_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM12EN))
mbed_official 87:085cde657901 748 #define __TIM13_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM13EN))
mbed_official 87:085cde657901 749 #define __TIM14_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM14EN))
mbed_official 87:085cde657901 750 #define __WWDG_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_WWDGEN))
mbed_official 87:085cde657901 751 #define __USART3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART3EN))
mbed_official 87:085cde657901 752 #define __UART4_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_UART4EN))
mbed_official 87:085cde657901 753 #define __UART5_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_UART5EN))
mbed_official 87:085cde657901 754 #define __CAN1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_CAN1EN))
mbed_official 87:085cde657901 755 #define __CAN2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_CAN2EN))
mbed_official 87:085cde657901 756 #define __DAC_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_DACEN))
mbed_official 87:085cde657901 757
mbed_official 87:085cde657901 758 #define __TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
mbed_official 87:085cde657901 759 #define __TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
mbed_official 87:085cde657901 760 #define __TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
mbed_official 87:085cde657901 761 #define __TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
mbed_official 87:085cde657901 762 #define __TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
mbed_official 87:085cde657901 763 #define __WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
mbed_official 87:085cde657901 764 #define __USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
mbed_official 87:085cde657901 765 #define __UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
mbed_official 87:085cde657901 766 #define __UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
mbed_official 87:085cde657901 767 #define __CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
mbed_official 87:085cde657901 768 #define __CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
mbed_official 87:085cde657901 769 #define __DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
mbed_official 87:085cde657901 770
mbed_official 87:085cde657901 771 /** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
mbed_official 87:085cde657901 772 * @note After reset, the peripheral clock (used for registers read/write access)
mbed_official 87:085cde657901 773 * is disabled and the application software has to enable this clock before
mbed_official 87:085cde657901 774 * using it.
mbed_official 87:085cde657901 775 */
mbed_official 87:085cde657901 776 #define __TIM8_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM8EN))
mbed_official 87:085cde657901 777 #define __ADC2_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_ADC2EN))
mbed_official 87:085cde657901 778 #define __ADC3_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_ADC3EN))
mbed_official 87:085cde657901 779
mbed_official 87:085cde657901 780 #define __TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
mbed_official 87:085cde657901 781 #define __ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
mbed_official 87:085cde657901 782 #define __ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
mbed_official 87:085cde657901 783
mbed_official 87:085cde657901 784 /** @brief Force or release AHB1 peripheral reset.
mbed_official 87:085cde657901 785 */
mbed_official 87:085cde657901 786 #define __GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST))
mbed_official 87:085cde657901 787 #define __GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST))
mbed_official 87:085cde657901 788 #define __GPIOI_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOIRST))
mbed_official 87:085cde657901 789 #define __ETHMAC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETHMACRST))
mbed_official 87:085cde657901 790 #define __OTGHS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST))
mbed_official 87:085cde657901 791
mbed_official 87:085cde657901 792 #define __GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
mbed_official 87:085cde657901 793 #define __GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
mbed_official 87:085cde657901 794 #define __GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
mbed_official 87:085cde657901 795 #define __ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST))
mbed_official 87:085cde657901 796 #define __OTGHS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
mbed_official 87:085cde657901 797
mbed_official 87:085cde657901 798 /** @brief Force or release AHB2 peripheral reset.
mbed_official 87:085cde657901 799 */
mbed_official 369:2e96f1b71984 800 #if defined(STM32F407xx)|| defined(STM32F417xx)
mbed_official 87:085cde657901 801 #define __DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST))
mbed_official 87:085cde657901 802 #define __DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
mbed_official 369:2e96f1b71984 803 #endif /* STM32F407xx || STM32F417xx */
mbed_official 87:085cde657901 804
mbed_official 369:2e96f1b71984 805 #if defined(STM32F415xx) || defined(STM32F417xx)
mbed_official 87:085cde657901 806 #define __CRYP_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST))
mbed_official 87:085cde657901 807 #define __HASH_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST))
mbed_official 87:085cde657901 808
mbed_official 87:085cde657901 809 #define __CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST))
mbed_official 87:085cde657901 810 #define __HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST))
mbed_official 87:085cde657901 811
mbed_official 369:2e96f1b71984 812 #endif /* STM32F415xx || STM32F417xx */
mbed_official 87:085cde657901 813
mbed_official 87:085cde657901 814 /** @brief Force or release AHB3 peripheral reset
mbed_official 87:085cde657901 815 */
mbed_official 87:085cde657901 816 #define __FSMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FSMCRST))
mbed_official 87:085cde657901 817 #define __FSMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FSMCRST))
mbed_official 87:085cde657901 818
mbed_official 87:085cde657901 819 /** @brief Force or release APB1 peripheral reset.
mbed_official 369:2e96f1b71984 820 */
mbed_official 87:085cde657901 821 #define __TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
mbed_official 87:085cde657901 822 #define __TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
mbed_official 87:085cde657901 823 #define __TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
mbed_official 87:085cde657901 824 #define __TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
mbed_official 87:085cde657901 825 #define __TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
mbed_official 87:085cde657901 826 #define __USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
mbed_official 87:085cde657901 827 #define __UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
mbed_official 87:085cde657901 828 #define __UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
mbed_official 87:085cde657901 829 #define __CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST))
mbed_official 87:085cde657901 830 #define __CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST))
mbed_official 87:085cde657901 831 #define __DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
mbed_official 87:085cde657901 832
mbed_official 87:085cde657901 833 #define __TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
mbed_official 87:085cde657901 834 #define __TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
mbed_official 87:085cde657901 835 #define __TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
mbed_official 87:085cde657901 836 #define __TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
mbed_official 87:085cde657901 837 #define __TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
mbed_official 87:085cde657901 838 #define __USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
mbed_official 87:085cde657901 839 #define __UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
mbed_official 87:085cde657901 840 #define __UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
mbed_official 87:085cde657901 841 #define __CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
mbed_official 87:085cde657901 842 #define __CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
mbed_official 87:085cde657901 843 #define __DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
mbed_official 87:085cde657901 844
mbed_official 87:085cde657901 845 /** @brief Force or release APB2 peripheral reset.
mbed_official 87:085cde657901 846 */
mbed_official 87:085cde657901 847 #define __TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))
mbed_official 87:085cde657901 848 #define __TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
mbed_official 87:085cde657901 849
mbed_official 87:085cde657901 850 /** @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
mbed_official 87:085cde657901 851 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
mbed_official 87:085cde657901 852 * power consumption.
mbed_official 87:085cde657901 853 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
mbed_official 87:085cde657901 854 * @note By default, all peripheral clocks are enabled during SLEEP mode.
mbed_official 369:2e96f1b71984 855 */
mbed_official 87:085cde657901 856 #define __GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN))
mbed_official 87:085cde657901 857 #define __GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN))
mbed_official 87:085cde657901 858 #define __GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOILPEN))
mbed_official 87:085cde657901 859 #define __SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN))
mbed_official 87:085cde657901 860 #define __ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACLPEN))
mbed_official 87:085cde657901 861 #define __ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACTXLPEN))
mbed_official 87:085cde657901 862 #define __ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACRXLPEN))
mbed_official 87:085cde657901 863 #define __ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACPTPLPEN))
mbed_official 87:085cde657901 864 #define __OTGHS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN))
mbed_official 87:085cde657901 865 #define __OTGHSULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN))
mbed_official 87:085cde657901 866
mbed_official 87:085cde657901 867 #define __GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
mbed_official 87:085cde657901 868 #define __GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
mbed_official 87:085cde657901 869 #define __GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN))
mbed_official 87:085cde657901 870 #define __SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
mbed_official 87:085cde657901 871 #define __ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN))
mbed_official 87:085cde657901 872 #define __ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN))
mbed_official 87:085cde657901 873 #define __ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN))
mbed_official 87:085cde657901 874 #define __ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN))
mbed_official 87:085cde657901 875 #define __OTGHS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
mbed_official 87:085cde657901 876 #define __OTGHSULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
mbed_official 87:085cde657901 877
mbed_official 87:085cde657901 878 /** @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
mbed_official 87:085cde657901 879 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
mbed_official 87:085cde657901 880 * power consumption.
mbed_official 87:085cde657901 881 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
mbed_official 87:085cde657901 882 * @note By default, all peripheral clocks are enabled during SLEEP mode.
mbed_official 87:085cde657901 883 */
mbed_official 369:2e96f1b71984 884 #if defined(STM32F407xx)|| defined(STM32F417xx)
mbed_official 87:085cde657901 885 #define __DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))
mbed_official 87:085cde657901 886 #define __DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
mbed_official 369:2e96f1b71984 887 #endif /* STM32F407xx || STM32F417xx */
mbed_official 87:085cde657901 888
mbed_official 369:2e96f1b71984 889 #if defined(STM32F415xx) || defined(STM32F417xx)
mbed_official 87:085cde657901 890 #define __CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN))
mbed_official 87:085cde657901 891 #define __HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN))
mbed_official 87:085cde657901 892
mbed_official 87:085cde657901 893 #define __CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN))
mbed_official 87:085cde657901 894 #define __HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN))
mbed_official 369:2e96f1b71984 895 #endif /* STM32F415xx || STM32F417xx */
mbed_official 87:085cde657901 896
mbed_official 87:085cde657901 897 /** @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
mbed_official 87:085cde657901 898 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
mbed_official 87:085cde657901 899 * power consumption.
mbed_official 87:085cde657901 900 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
mbed_official 87:085cde657901 901 * @note By default, all peripheral clocks are enabled during SLEEP mode.
mbed_official 87:085cde657901 902 */
mbed_official 87:085cde657901 903 #define __FSMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FSMCLPEN))
mbed_official 87:085cde657901 904 #define __FSMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FSMCLPEN))
mbed_official 87:085cde657901 905
mbed_official 87:085cde657901 906 /** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
mbed_official 87:085cde657901 907 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
mbed_official 87:085cde657901 908 * power consumption.
mbed_official 87:085cde657901 909 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
mbed_official 87:085cde657901 910 * @note By default, all peripheral clocks are enabled during SLEEP mode.
mbed_official 87:085cde657901 911 */
mbed_official 87:085cde657901 912 #define __TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN))
mbed_official 87:085cde657901 913 #define __TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN))
mbed_official 87:085cde657901 914 #define __TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN))
mbed_official 87:085cde657901 915 #define __TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN))
mbed_official 87:085cde657901 916 #define __TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN))
mbed_official 87:085cde657901 917 #define __USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN))
mbed_official 87:085cde657901 918 #define __UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN))
mbed_official 87:085cde657901 919 #define __UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN))
mbed_official 87:085cde657901 920 #define __CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN))
mbed_official 87:085cde657901 921 #define __CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN))
mbed_official 87:085cde657901 922 #define __DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN))
mbed_official 87:085cde657901 923
mbed_official 87:085cde657901 924 #define __TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
mbed_official 87:085cde657901 925 #define __TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
mbed_official 87:085cde657901 926 #define __TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
mbed_official 87:085cde657901 927 #define __TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
mbed_official 87:085cde657901 928 #define __TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
mbed_official 87:085cde657901 929 #define __USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
mbed_official 87:085cde657901 930 #define __UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
mbed_official 87:085cde657901 931 #define __UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
mbed_official 87:085cde657901 932 #define __CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
mbed_official 87:085cde657901 933 #define __CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
mbed_official 87:085cde657901 934 #define __DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
mbed_official 87:085cde657901 935
mbed_official 87:085cde657901 936 /** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
mbed_official 87:085cde657901 937 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
mbed_official 87:085cde657901 938 * power consumption.
mbed_official 87:085cde657901 939 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
mbed_official 87:085cde657901 940 * @note By default, all peripheral clocks are enabled during SLEEP mode.
mbed_official 369:2e96f1b71984 941 */
mbed_official 87:085cde657901 942 #define __TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN))
mbed_official 87:085cde657901 943 #define __ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN))
mbed_official 87:085cde657901 944 #define __ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN))
mbed_official 87:085cde657901 945
mbed_official 87:085cde657901 946 #define __TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
mbed_official 87:085cde657901 947 #define __ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
mbed_official 87:085cde657901 948 #define __ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
mbed_official 369:2e96f1b71984 949 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
mbed_official 369:2e96f1b71984 950 /*---------------------------------------------------------------------------------------------*/
mbed_official 87:085cde657901 951
mbed_official 369:2e96f1b71984 952 /*------------------------------------------ STM32F411xx --------------------------------------*/
mbed_official 369:2e96f1b71984 953 #if defined(STM32F411xE)
mbed_official 369:2e96f1b71984 954 /** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
mbed_official 369:2e96f1b71984 955 */
mbed_official 369:2e96f1b71984 956 #define __SPI5_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SPI5EN))
mbed_official 369:2e96f1b71984 957 #define __SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
mbed_official 369:2e96f1b71984 958
mbed_official 369:2e96f1b71984 959 /** @brief Force or release APB2 peripheral reset.
mbed_official 369:2e96f1b71984 960 */
mbed_official 369:2e96f1b71984 961 #define __SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST))
mbed_official 369:2e96f1b71984 962 #define __SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
mbed_official 369:2e96f1b71984 963
mbed_official 369:2e96f1b71984 964 /** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
mbed_official 369:2e96f1b71984 965 */
mbed_official 369:2e96f1b71984 966 #define __SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN))
mbed_official 87:085cde657901 967 #define __SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
mbed_official 87:085cde657901 968
mbed_official 369:2e96f1b71984 969 #endif /* STM32F411xE */
mbed_official 369:2e96f1b71984 970 /*---------------------------------------------------------------------------------------------*/
mbed_official 369:2e96f1b71984 971
mbed_official 369:2e96f1b71984 972 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
mbed_official 369:2e96f1b71984 973 defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
mbed_official 87:085cde657901 974
mbed_official 87:085cde657901 975 /** @brief Macro to configure the Timers clocks prescalers
mbed_official 87:085cde657901 976 * @note This feature is only available with STM32F429x/439x Devices.
mbed_official 87:085cde657901 977 * @param __PRESC__ : specifies the Timers clocks prescalers selection
mbed_official 87:085cde657901 978 * This parameter can be one of the following values:
mbed_official 87:085cde657901 979 * @arg RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is
mbed_official 87:085cde657901 980 * equal to HPRE if PPREx is corresponding to division by 1 or 2,
mbed_official 87:085cde657901 981 * else it is equal to [(HPRE * PPREx) / 2] if PPREx is corresponding to
mbed_official 87:085cde657901 982 * division by 4 or more.
mbed_official 87:085cde657901 983 * @arg RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is
mbed_official 87:085cde657901 984 * equal to HPRE if PPREx is corresponding to division by 1, 2 or 4,
mbed_official 87:085cde657901 985 * else it is equal to [(HPRE * PPREx) / 4] if PPREx is corresponding
mbed_official 87:085cde657901 986 * to division by 8 or more.
mbed_official 87:085cde657901 987 */
mbed_official 87:085cde657901 988 #define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) (*(__IO uint32_t *) DCKCFGR_TIMPRE_BB = (__PRESC__))
mbed_official 87:085cde657901 989
mbed_official 369:2e96f1b71984 990 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx) || STM32F401xC || STM32F401xE || STM32F411xE */
mbed_official 369:2e96f1b71984 991
mbed_official 369:2e96f1b71984 992 #if defined(STM32F411xE)
mbed_official 369:2e96f1b71984 993
mbed_official 369:2e96f1b71984 994 /** @brief Macro to configure the PLLI2S clock multiplication and division factors .
mbed_official 369:2e96f1b71984 995 * @note This macro must be used only when the PLLI2S is disabled.
mbed_official 369:2e96f1b71984 996 * @note This macro must be used only when the PLLI2S is disabled.
mbed_official 369:2e96f1b71984 997 * @note PLLI2S clock source is common with the main PLL (configured in
mbed_official 369:2e96f1b71984 998 * HAL_RCC_ClockConfig() API).
mbed_official 369:2e96f1b71984 999 * @param __PLLI2SM__: specifies the division factor for PLLI2S VCO input clock
mbed_official 369:2e96f1b71984 1000 * This parameter must be a number between Min_Data = 2 and Max_Data = 63.
mbed_official 369:2e96f1b71984 1001 * @note You have to set the PLLI2SM parameter correctly to ensure that the VCO input
mbed_official 369:2e96f1b71984 1002 * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
mbed_official 369:2e96f1b71984 1003 * of 2 MHz to limit PLLI2S jitter.
mbed_official 369:2e96f1b71984 1004 * @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock
mbed_official 369:2e96f1b71984 1005 * This parameter must be a number between Min_Data = 192 and Max_Data = 432.
mbed_official 369:2e96f1b71984 1006 * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
mbed_official 369:2e96f1b71984 1007 * output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
mbed_official 369:2e96f1b71984 1008 * @param __PLLI2SR__: specifies the division factor for I2S clock
mbed_official 369:2e96f1b71984 1009 * This parameter must be a number between Min_Data = 2 and Max_Data = 7.
mbed_official 369:2e96f1b71984 1010 * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
mbed_official 369:2e96f1b71984 1011 * on the I2S clock frequency.
mbed_official 369:2e96f1b71984 1012 */
mbed_official 369:2e96f1b71984 1013 #define __HAL_RCC_PLLI2S_I2SCLK_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) |\
mbed_official 369:2e96f1b71984 1014 ((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR)) | (__PLLI2SM__))
mbed_official 369:2e96f1b71984 1015 #endif /* STM32F411xE */
mbed_official 369:2e96f1b71984 1016
mbed_official 369:2e96f1b71984 1017
mbed_official 369:2e96f1b71984 1018 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
mbed_official 369:2e96f1b71984 1019
mbed_official 87:085cde657901 1020 /** @brief Macros to Enable or Disable the PLLISAI.
mbed_official 87:085cde657901 1021 * @note The PLLSAI is only available with STM32F429x/439x Devices.
mbed_official 87:085cde657901 1022 * @note The PLLSAI is disabled by hardware when entering STOP and STANDBY modes.
mbed_official 87:085cde657901 1023 */
mbed_official 87:085cde657901 1024 #define __HAL_RCC_PLLSAI_ENABLE() (*(__IO uint32_t *) CR_PLLSAION_BB = ENABLE)
mbed_official 87:085cde657901 1025 #define __HAL_RCC_PLLSAI_DISABLE() (*(__IO uint32_t *) CR_PLLSAION_BB = DISABLE)
mbed_official 87:085cde657901 1026
mbed_official 87:085cde657901 1027 /** @brief Macro to configure the PLLSAI clock multiplication and division factors.
mbed_official 87:085cde657901 1028 * @note The PLLSAI is only available with STM32F429x/439x Devices.
mbed_official 87:085cde657901 1029 * @note This function must be used only when the PLLSAI is disabled.
mbed_official 87:085cde657901 1030 * @note PLLSAI clock source is common with the main PLL (configured in
mbed_official 87:085cde657901 1031 * RCC_PLLConfig function )
mbed_official 87:085cde657901 1032 * @param __PLLSAIN__: specifies the multiplication factor for PLLSAI VCO output clock.
mbed_official 87:085cde657901 1033 * This parameter must be a number between Min_Data = 192 and Max_Data = 432.
mbed_official 87:085cde657901 1034 * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO
mbed_official 87:085cde657901 1035 * output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
mbed_official 87:085cde657901 1036 * @param __PLLSAIQ__: specifies the division factor for SAI1 clock
mbed_official 87:085cde657901 1037 * This parameter must be a number between Min_Data = 2 and Max_Data = 15.
mbed_official 87:085cde657901 1038 * @param __PLLSAIR__: specifies the division factor for LTDC clock
mbed_official 87:085cde657901 1039 * This parameter must be a number between Min_Data = 2 and Max_Data = 7.
mbed_official 87:085cde657901 1040 */
mbed_official 87:085cde657901 1041 #define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIQ__, __PLLSAIR__) (RCC->PLLSAICFGR = ((__PLLSAIN__) << 6) | ((__PLLSAIQ__) << 24) | ((__PLLSAIR__) << 28))
mbed_official 87:085cde657901 1042
mbed_official 87:085cde657901 1043 /** @brief Macro used by the SAI HAL driver to configure the PLLI2S clock multiplication and division factors.
mbed_official 87:085cde657901 1044 * @note This macro must be used only when the PLLI2S is disabled.
mbed_official 87:085cde657901 1045 * @note PLLI2S clock source is common with the main PLL (configured in
mbed_official 87:085cde657901 1046 * HAL_RCC_ClockConfig() API)
mbed_official 87:085cde657901 1047 * @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock.
mbed_official 87:085cde657901 1048 * This parameter must be a number between Min_Data = 192 and Max_Data = 432.
mbed_official 87:085cde657901 1049 * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
mbed_official 87:085cde657901 1050 * output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
mbed_official 87:085cde657901 1051 * @param __PLLI2SQ__: specifies the division factor for SAI1 clock.
mbed_official 87:085cde657901 1052 * This parameter must be a number between Min_Data = 2 and Max_Data = 15.
mbed_official 87:085cde657901 1053 * @note the PLLI2SQ parameter is only available with STM32F429x/439x Devices
mbed_official 87:085cde657901 1054 * and can be configured using the __HAL_RCC_PLLI2S_PLLSAICLK_CONFIG() macro
mbed_official 87:085cde657901 1055 * @param __PLLI2SR__: specifies the division factor for I2S clock
mbed_official 87:085cde657901 1056 * This parameter must be a number between Min_Data = 2 and Max_Data = 7.
mbed_official 87:085cde657901 1057 * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
mbed_official 87:085cde657901 1058 * on the I2S clock frequency.
mbed_official 87:085cde657901 1059 */
mbed_official 87:085cde657901 1060 #define __HAL_RCC_PLLI2S_SAICLK_CONFIG(__PLLI2SN__, __PLLI2SQ__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SN__) << 6) | ((__PLLI2SQ__) << 24) | ((__PLLI2SR__) << 28))
mbed_official 87:085cde657901 1061
mbed_official 87:085cde657901 1062 /** @brief Macro to configure the SAI clock Divider coming from PLLI2S.
mbed_official 87:085cde657901 1063 * @note The SAI peripheral is only available with STM32F429x/439x Devices.
mbed_official 87:085cde657901 1064 * @note This function must be called before enabling the PLLI2S.
mbed_official 87:085cde657901 1065 * @param __PLLI2SDivQ__: specifies the PLLI2S division factor for SAI1 clock .
mbed_official 87:085cde657901 1066 * This parameter must be a number between 1 and 32.
mbed_official 87:085cde657901 1067 * SAI1 clock frequency = f(PLLI2SQ) / __PLLI2SDivQ__
mbed_official 87:085cde657901 1068 */
mbed_official 87:085cde657901 1069 #define __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(__PLLI2SDivQ__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVQ, (__PLLI2SDivQ__)-1))
mbed_official 87:085cde657901 1070
mbed_official 87:085cde657901 1071 /** @brief Macro to configure the SAI clock Divider coming from PLLSAI.
mbed_official 87:085cde657901 1072 * @note The SAI peripheral is only available with STM32F429x/439x Devices.
mbed_official 87:085cde657901 1073 * @note This function must be called before enabling the PLLSAI.
mbed_official 87:085cde657901 1074 * @param __PLLSAIDivQ__: specifies the PLLSAI division factor for SAI1 clock .
mbed_official 87:085cde657901 1075 * This parameter must be a number between Min_Data = 1 and Max_Data = 32.
mbed_official 87:085cde657901 1076 * SAI1 clock frequency = f(PLLSAIQ) / __PLLSAIDivQ__
mbed_official 87:085cde657901 1077 */
mbed_official 87:085cde657901 1078 #define __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(__PLLSAIDivQ__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVQ, ((__PLLSAIDivQ__)-1)<<8))
mbed_official 87:085cde657901 1079
mbed_official 87:085cde657901 1080 /** @brief Macro to configure the LTDC clock Divider coming from PLLSAI.
mbed_official 87:085cde657901 1081 *
mbed_official 87:085cde657901 1082 * @note The LTDC peripheral is only available with STM32F429x/439x Devices.
mbed_official 87:085cde657901 1083 * @note This function must be called before enabling the PLLSAI.
mbed_official 87:085cde657901 1084 * @param __PLLSAIDivR__: specifies the PLLSAI division factor for LTDC clock .
mbed_official 87:085cde657901 1085 * This parameter must be a number between Min_Data = 2 and Max_Data = 16.
mbed_official 87:085cde657901 1086 * LTDC clock frequency = f(PLLSAIR) / __PLLSAIDivR__
mbed_official 87:085cde657901 1087 */
mbed_official 87:085cde657901 1088 #define __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(__PLLSAIDivR__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVR, (__PLLSAIDivR__)))
mbed_official 87:085cde657901 1089
mbed_official 87:085cde657901 1090 /** @brief Macro to configure SAI1BlockA clock source selection.
mbed_official 87:085cde657901 1091 * @note The SAI peripheral is only available with STM32F429x/439x Devices.
mbed_official 87:085cde657901 1092 * @note This function must be called before enabling PLLSAI, PLLI2S and
mbed_official 87:085cde657901 1093 * the SAI clock.
mbed_official 87:085cde657901 1094 * @param __SOURCE__: specifies the SAI Block A clock source.
mbed_official 87:085cde657901 1095 * This parameter can be one of the following values:
mbed_official 87:085cde657901 1096 * @arg RCC_SAIACLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
mbed_official 87:085cde657901 1097 * as SAI1 Block A clock.
mbed_official 87:085cde657901 1098 * @arg RCC_SAIACLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
mbed_official 87:085cde657901 1099 * as SAI1 Block A clock.
mbed_official 87:085cde657901 1100 * @arg RCC_SAIACLKSOURCE_Ext: External clock mapped on the I2S_CKIN pin
mbed_official 87:085cde657901 1101 * used as SAI1 Block A clock.
mbed_official 87:085cde657901 1102 */
mbed_official 87:085cde657901 1103 #define __HAL_RCC_SAI_BLOCKACLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1ASRC, (__SOURCE__)))
mbed_official 87:085cde657901 1104
mbed_official 87:085cde657901 1105 /** @brief Macro to configure SAI1BlockB clock source selection.
mbed_official 87:085cde657901 1106 * @note The SAI peripheral is only available with STM32F429x/439x Devices.
mbed_official 87:085cde657901 1107 * @note This function must be called before enabling PLLSAI, PLLI2S and
mbed_official 87:085cde657901 1108 * the SAI clock.
mbed_official 87:085cde657901 1109 * @param __SOURCE__: specifies the SAI Block B clock source.
mbed_official 87:085cde657901 1110 * This parameter can be one of the following values:
mbed_official 87:085cde657901 1111 * @arg RCC_SAIBCLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
mbed_official 87:085cde657901 1112 * as SAI1 Block B clock.
mbed_official 87:085cde657901 1113 * @arg RCC_SAIBCLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
mbed_official 87:085cde657901 1114 * as SAI1 Block B clock.
mbed_official 87:085cde657901 1115 * @arg RCC_SAIBCLKSOURCE_Ext: External clock mapped on the I2S_CKIN pin
mbed_official 87:085cde657901 1116 * used as SAI1 Block B clock.
mbed_official 87:085cde657901 1117 */
mbed_official 87:085cde657901 1118 #define __HAL_RCC_SAI_BLOCKBCLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1BSRC, (__SOURCE__)))
mbed_official 87:085cde657901 1119
mbed_official 87:085cde657901 1120 /** @brief Enable PLLSAI_RDY interrupt.
mbed_official 87:085cde657901 1121 */
mbed_official 87:085cde657901 1122 #define __HAL_RCC_PLLSAI_ENABLE_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYIE))
mbed_official 87:085cde657901 1123
mbed_official 87:085cde657901 1124 /** @brief Disable PLLSAI_RDY interrupt.
mbed_official 87:085cde657901 1125 */
mbed_official 87:085cde657901 1126 #define __HAL_RCC_PLLSAI_DISABLE_IT() (RCC->CIR &= ~(RCC_CIR_PLLSAIRDYIE))
mbed_official 87:085cde657901 1127
mbed_official 87:085cde657901 1128 /** @brief Clear the PLLSAI RDY interrupt pending bits.
mbed_official 87:085cde657901 1129 */
mbed_official 87:085cde657901 1130 #define __HAL_RCC_PLLSAI_CLEAR_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYF))
mbed_official 87:085cde657901 1131
mbed_official 87:085cde657901 1132 /** @brief Check the PLLSAI RDY interrupt has occurred or not.
mbed_official 87:085cde657901 1133 * @retval The new state (TRUE or FALSE).
mbed_official 87:085cde657901 1134 */
mbed_official 87:085cde657901 1135 #define __HAL_RCC_PLLSAI_GET_IT() ((RCC->CIR & (RCC_CIR_PLLSAIRDYIE)) == (RCC_CIR_PLLSAIRDYIE))
mbed_official 87:085cde657901 1136
mbed_official 87:085cde657901 1137 /** @brief Check PLLSAI RDY flag is set or not.
mbed_official 87:085cde657901 1138 * @retval The new state (TRUE or FALSE).
mbed_official 87:085cde657901 1139 */
mbed_official 87:085cde657901 1140 #define __HAL_RCC_PLLSAI_GET_FLAG() ((RCC->CR & (RCC_CR_PLLSAIRDY)) == (RCC_CR_PLLSAIRDY))
mbed_official 87:085cde657901 1141
mbed_official 87:085cde657901 1142 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
mbed_official 87:085cde657901 1143
mbed_official 87:085cde657901 1144 /* Exported functions --------------------------------------------------------*/
mbed_official 87:085cde657901 1145 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
mbed_official 87:085cde657901 1146 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
mbed_official 87:085cde657901 1147
mbed_official 369:2e96f1b71984 1148 #if defined(STM32F411xE)
mbed_official 369:2e96f1b71984 1149 void HAL_RCCEx_SelectLSEMode(uint8_t Mode);
mbed_official 369:2e96f1b71984 1150 #endif /* STM32F411xE */
mbed_official 87:085cde657901 1151 /**
mbed_official 87:085cde657901 1152 * @}
mbed_official 87:085cde657901 1153 */
mbed_official 87:085cde657901 1154
mbed_official 87:085cde657901 1155 /**
mbed_official 87:085cde657901 1156 * @}
mbed_official 87:085cde657901 1157 */
mbed_official 87:085cde657901 1158
mbed_official 87:085cde657901 1159 #ifdef __cplusplus
mbed_official 87:085cde657901 1160 }
mbed_official 87:085cde657901 1161 #endif
mbed_official 87:085cde657901 1162
mbed_official 87:085cde657901 1163 #endif /* __STM32F4xx_HAL_RCC_EX_H */
mbed_official 87:085cde657901 1164
mbed_official 87:085cde657901 1165 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/