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targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal_spi.c@392:2b59412bb664, 2014-11-07 (annotated)

Committer:: mbed_official
Date:: Fri Nov 07 08:15:08 2014 +0000
Revision:: 392:2b59412bb664
Parent:: targets/cmsis/TARGET_STM/TARGET_NUCLEO_F091RC/stm32f0xx_hal_spi.c@340:28d1f895c6fe
Child:: 441:d2c15dda23c1

Synchronized with git revision eec0be05cd92349bee83c65f9e1302b25b5badf4

Full URL: https://github.com/mbedmicro/mbed/commit/eec0be05cd92349bee83c65f9e1302b25b5badf4/

Targets: STM32F0 - Factorisation of NUCLEO_F030R8/F072RB/F091RC cmsis folders

Who changed what in which revision?

User	Revision	Line number	New contents of line
mbed_official	340:28d1f895c6fe	1	/**
mbed_official	340:28d1f895c6fe	2	******************************************************************************
mbed_official	340:28d1f895c6fe	3	* @file stm32f0xx_hal_spi.c
mbed_official	340:28d1f895c6fe	4	* @author MCD Application Team
mbed_official	340:28d1f895c6fe	5	* @version V1.1.0
mbed_official	340:28d1f895c6fe	6	* @date 03-Oct-2014
mbed_official	340:28d1f895c6fe	7	* @brief SPI HAL module driver.
mbed_official	340:28d1f895c6fe	8	* This file provides firmware functions to manage the following
mbed_official	340:28d1f895c6fe	9	* functionalities of the SPI peripheral:
mbed_official	340:28d1f895c6fe	10	* + Initialization/de-initialization functions
mbed_official	340:28d1f895c6fe	11	* + I/O operation functions
mbed_official	340:28d1f895c6fe	12	* + Peripheral Control functions
mbed_official	340:28d1f895c6fe	13	* + Peripheral State functions
mbed_official	340:28d1f895c6fe	14	*
mbed_official	340:28d1f895c6fe	15	@verbatim
mbed_official	340:28d1f895c6fe	16	===============================================================================
mbed_official	340:28d1f895c6fe	17	##### How to use this driver #####
mbed_official	340:28d1f895c6fe	18	===============================================================================
mbed_official	340:28d1f895c6fe	19	[..]
mbed_official	340:28d1f895c6fe	20	The SPI HAL driver can be used as follows:
mbed_official	340:28d1f895c6fe	21
mbed_official	340:28d1f895c6fe	22	(#) Declare a SPI_HandleTypeDef handle structure, for example:
mbed_official	340:28d1f895c6fe	23	SPI_HandleTypeDef hspi;
mbed_official	340:28d1f895c6fe	24
mbed_official	340:28d1f895c6fe	25	(#)Initialize the SPI low level resources by implement the HAL_SPI_MspInit ()API:
mbed_official	340:28d1f895c6fe	26	(##) Enable the SPIx interface clock
mbed_official	340:28d1f895c6fe	27	(##) SPI pins configuration
mbed_official	340:28d1f895c6fe	28	(+++) Enable the clock for the SPI GPIOs
mbed_official	340:28d1f895c6fe	29	(+++) Configure these SPI pins as alternate function push-pull
mbed_official	340:28d1f895c6fe	30	(##) NVIC configuration if you need to use interrupt process
mbed_official	340:28d1f895c6fe	31	(+++) Configure the SPIx interrupt priority
mbed_official	340:28d1f895c6fe	32	(+++) Enable the NVIC SPI IRQ handle
mbed_official	340:28d1f895c6fe	33	(##) DMA Configuration if you need to use DMA process
mbed_official	340:28d1f895c6fe	34	(+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive channel
mbed_official	340:28d1f895c6fe	35	(+++) Enable the DMAx interface clock using
mbed_official	340:28d1f895c6fe	36	(+++) Configure the DMA handle parameters
mbed_official	340:28d1f895c6fe	37	(+++) Configure the DMA Tx or Rx channel
mbed_official	340:28d1f895c6fe	38	(+++) Associate the initilalized hdma_tx handle to the hspi DMA Tx or Rx handle
mbed_official	340:28d1f895c6fe	39	(+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx channel
mbed_official	340:28d1f895c6fe	40
mbed_official	340:28d1f895c6fe	41	(#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS
mbed_official	340:28d1f895c6fe	42	management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.
mbed_official	340:28d1f895c6fe	43
mbed_official	340:28d1f895c6fe	44	(#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
mbed_official	340:28d1f895c6fe	45	(++) These APIs configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
mbed_official	340:28d1f895c6fe	46	by calling the customed HAL_SPI_MspInit(&hspi) API.
mbed_official	340:28d1f895c6fe	47
mbed_official	340:28d1f895c6fe	48	[..]
mbed_official	340:28d1f895c6fe	49	Using the HAL it is not possible to reach all supported SPI frequency with the differents SPI Modes,
mbed_official	340:28d1f895c6fe	50	the following table resume the max SPI frequency reached with data size 8bits/16bits:
mbed_official	340:28d1f895c6fe	51	+-----------------------------------------------------------------------------------------+
mbed_official	340:28d1f895c6fe	52	\| \| \| 2Lines Fullduplex \| 2Lines RxOnly \| 1Line \|
mbed_official	340:28d1f895c6fe	53	\| Process \| Tranfert mode \|--------------------\|--------------------\|--------------------\|
mbed_official	340:28d1f895c6fe	54	\| \| \| Master \| Slave \| Master \| Slave \| Master \| Slave \|
mbed_official	340:28d1f895c6fe	55	\|=========================================================================================\|
mbed_official	340:28d1f895c6fe	56	\| T \| Polling \| Fcpu/32 \| Fcpu/32 \| NA \| NA \| NA \| NA \|
mbed_official	340:28d1f895c6fe	57	\| X \|----------------\|----------\|---------\|----------\|---------\|----------\|---------\|
mbed_official	340:28d1f895c6fe	58	\| / \| Interrupt \| Fcpu/32 \| Fcpu/32 \| NA \| NA \| NA \| NA \|
mbed_official	340:28d1f895c6fe	59	\| R \|----------------\|----------\|---------\|----------\|---------\|----------\|---------\|
mbed_official	340:28d1f895c6fe	60	\| X \| DMA \| Fcpu/32 \| Fcpu/16 \| NA \| NA \| NA \| NA \|
mbed_official	340:28d1f895c6fe	61	\|=========\|================\|==========\|=========\|==========\|=========\|==========\|=========\|
mbed_official	340:28d1f895c6fe	62	\| \| Polling \| Fcpu/32 \| Fcpu/16 \| Fcpu/16 \| Fcpu/16 \| Fcpu/16 \| Fcpu/16 \|
mbed_official	340:28d1f895c6fe	63	\| \|----------------\|----------\|---------\|----------\|---------\|----------\|---------\|
mbed_official	340:28d1f895c6fe	64	\| R \| Interrupt \| Fcpu/16 \| Fcpu/16 \| Fcpu/16 \| Fcpu/16 \| Fcpu/16 \| Fcpu/16 \|
mbed_official	340:28d1f895c6fe	65	\| X \|----------------\|----------\|---------\|----------\|---------\|----------\|---------\|
mbed_official	340:28d1f895c6fe	66	\| \| DMA \| Fcpu/4 \| Fcpu/8 \| Fcpu/4 \| Fcpu/4 \| Fcpu/8 \| Fcpu/16 \|
mbed_official	340:28d1f895c6fe	67	\|=========\|================\|==========\|=========\|==========\|=========\|==========\|=========\|
mbed_official	340:28d1f895c6fe	68	\| \| Polling \| Fcpu/16 \| Fcpu/16 \| NA \| NA \| Fcpu/16 \| Fcpu/16 \|
mbed_official	340:28d1f895c6fe	69	\| \|----------------\|----------\|---------\|----------\|---------\|----------\|---------\|
mbed_official	340:28d1f895c6fe	70	\| T \| Interrupt \| Fcpu/32 \| Fcpu/16 \| NA \| NA \| Fcpu/16 \| Fcpu/16 \|
mbed_official	340:28d1f895c6fe	71	\| X \|----------------\|----------\|---------\|----------\|---------\|----------\|---------\|
mbed_official	340:28d1f895c6fe	72	\| \| DMA \| Fcpu/2 \| Fcpu/16 \| NA \| NA \| Fcpu/8 \| Fcpu/16 \|
mbed_official	340:28d1f895c6fe	73	+-----------------------------------------------------------------------------------------+
mbed_official	340:28d1f895c6fe	74	@note The max SPI frequency depend on SPI data size (4bits, 5bits,..., 8bits,...15bits, 16bits),
mbed_official	340:28d1f895c6fe	75	SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA).
mbed_official	340:28d1f895c6fe	76	@note
mbed_official	340:28d1f895c6fe	77	(#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA()
mbed_official	340:28d1f895c6fe	78	(#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA()
mbed_official	340:28d1f895c6fe	79	(#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA()
mbed_official	340:28d1f895c6fe	80
mbed_official	340:28d1f895c6fe	81	@endverbatim
mbed_official	340:28d1f895c6fe	82	******************************************************************************
mbed_official	340:28d1f895c6fe	83	* @attention
mbed_official	340:28d1f895c6fe	84	*
mbed_official	340:28d1f895c6fe	85	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
mbed_official	340:28d1f895c6fe	86	*
mbed_official	340:28d1f895c6fe	87	* Redistribution and use in source and binary forms, with or without modification,
mbed_official	340:28d1f895c6fe	88	* are permitted provided that the following conditions are met:
mbed_official	340:28d1f895c6fe	89	* 1. Redistributions of source code must retain the above copyright notice,
mbed_official	340:28d1f895c6fe	90	* this list of conditions and the following disclaimer.
mbed_official	340:28d1f895c6fe	91	* 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official	340:28d1f895c6fe	92	* this list of conditions and the following disclaimer in the documentation
mbed_official	340:28d1f895c6fe	93	* and/or other materials provided with the distribution.
mbed_official	340:28d1f895c6fe	94	* 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official	340:28d1f895c6fe	95	* may be used to endorse or promote products derived from this software
mbed_official	340:28d1f895c6fe	96	* without specific prior written permission.
mbed_official	340:28d1f895c6fe	97	*
mbed_official	340:28d1f895c6fe	98	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official	340:28d1f895c6fe	99	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official	340:28d1f895c6fe	100	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official	340:28d1f895c6fe	101	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official	340:28d1f895c6fe	102	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official	340:28d1f895c6fe	103	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official	340:28d1f895c6fe	104	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official	340:28d1f895c6fe	105	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official	340:28d1f895c6fe	106	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official	340:28d1f895c6fe	107	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official	340:28d1f895c6fe	108	*
mbed_official	340:28d1f895c6fe	109	******************************************************************************
mbed_official	340:28d1f895c6fe	110	*/
mbed_official	340:28d1f895c6fe	111
mbed_official	340:28d1f895c6fe	112	/* Includes ------------------------------------------------------------------*/
mbed_official	340:28d1f895c6fe	113	#include "stm32f0xx_hal.h"
mbed_official	340:28d1f895c6fe	114
mbed_official	340:28d1f895c6fe	115	/** @addtogroup STM32F0xx_HAL_Driver
mbed_official	340:28d1f895c6fe	116	* @{
mbed_official	340:28d1f895c6fe	117	*/
mbed_official	340:28d1f895c6fe	118
mbed_official	340:28d1f895c6fe	119	/** @defgroup SPI SPI HAL module driver
mbed_official	340:28d1f895c6fe	120	* @brief SPI HAL module driver
mbed_official	340:28d1f895c6fe	121	* @{
mbed_official	340:28d1f895c6fe	122	*/
mbed_official	340:28d1f895c6fe	123	#ifdef HAL_SPI_MODULE_ENABLED
mbed_official	340:28d1f895c6fe	124
mbed_official	340:28d1f895c6fe	125	/* Private typedef -----------------------------------------------------------*/
mbed_official	340:28d1f895c6fe	126	/* Private define ------------------------------------------------------------*/
mbed_official	340:28d1f895c6fe	127
mbed_official	340:28d1f895c6fe	128	/** @defgroup SPI_Private_Constants SPI Private Constants
mbed_official	340:28d1f895c6fe	129	* @{
mbed_official	340:28d1f895c6fe	130	*/
mbed_official	340:28d1f895c6fe	131	#define SPI_DEFAULT_TIMEOUT 50
mbed_official	340:28d1f895c6fe	132	/**
mbed_official	340:28d1f895c6fe	133	* @}
mbed_official	340:28d1f895c6fe	134	*/
mbed_official	340:28d1f895c6fe	135
mbed_official	340:28d1f895c6fe	136	/* Private macro -------------------------------------------------------------*/
mbed_official	340:28d1f895c6fe	137	/* Private variables ---------------------------------------------------------*/
mbed_official	340:28d1f895c6fe	138	/* Private function prototypes -----------------------------------------------*/
mbed_official	340:28d1f895c6fe	139	/** @defgroup SPI_Private_Functions SPI Private Functions
mbed_official	340:28d1f895c6fe	140	* @{
mbed_official	340:28d1f895c6fe	141	*/
mbed_official	340:28d1f895c6fe	142
mbed_official	340:28d1f895c6fe	143	static void HAL_SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
mbed_official	340:28d1f895c6fe	144	static void HAL_SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
mbed_official	340:28d1f895c6fe	145	static void HAL_SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);
mbed_official	340:28d1f895c6fe	146	static void HAL_SPI_DMAError(DMA_HandleTypeDef *hdma);
mbed_official	340:28d1f895c6fe	147	static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout);
mbed_official	340:28d1f895c6fe	148	static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, uint32_t Timeout);
mbed_official	340:28d1f895c6fe	149	static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
mbed_official	340:28d1f895c6fe	150	static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
mbed_official	340:28d1f895c6fe	151	static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
mbed_official	340:28d1f895c6fe	152	static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
mbed_official	340:28d1f895c6fe	153	static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
mbed_official	340:28d1f895c6fe	154	static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
mbed_official	340:28d1f895c6fe	155	static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
mbed_official	340:28d1f895c6fe	156	static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
mbed_official	340:28d1f895c6fe	157	static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
mbed_official	340:28d1f895c6fe	158	static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
mbed_official	340:28d1f895c6fe	159	static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
mbed_official	340:28d1f895c6fe	160	static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
mbed_official	340:28d1f895c6fe	161	static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi);
mbed_official	340:28d1f895c6fe	162	static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi);
mbed_official	340:28d1f895c6fe	163	static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi);
mbed_official	340:28d1f895c6fe	164	static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout);
mbed_official	340:28d1f895c6fe	165	static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout);
mbed_official	340:28d1f895c6fe	166	/**
mbed_official	340:28d1f895c6fe	167	* @}
mbed_official	340:28d1f895c6fe	168	*/
mbed_official	340:28d1f895c6fe	169
mbed_official	340:28d1f895c6fe	170	/* Exported functions ---------------------------------------------------------*/
mbed_official	340:28d1f895c6fe	171
mbed_official	340:28d1f895c6fe	172	/** @defgroup SPI_Exported_Functions SPI Exported Functions
mbed_official	340:28d1f895c6fe	173	* @{
mbed_official	340:28d1f895c6fe	174	*/
mbed_official	340:28d1f895c6fe	175
mbed_official	340:28d1f895c6fe	176	/** @defgroup SPI_Exported_Functions_Group1 Initialization/de-initialization functions
mbed_official	340:28d1f895c6fe	177	* @brief Initialization and Configuration functions
mbed_official	340:28d1f895c6fe	178	*
mbed_official	340:28d1f895c6fe	179	@verbatim
mbed_official	340:28d1f895c6fe	180	===============================================================================
mbed_official	340:28d1f895c6fe	181	##### Initialization and Configuration functions #####
mbed_official	340:28d1f895c6fe	182	===============================================================================
mbed_official	340:28d1f895c6fe	183	[..] This subsection provides a set of functions allowing to initialize and
mbed_official	340:28d1f895c6fe	184	de-initialiaze the SPIx peripheral:
mbed_official	340:28d1f895c6fe	185
mbed_official	340:28d1f895c6fe	186	(+) User must Implement HAL_SPI_MspInit() function in which he configures
mbed_official	340:28d1f895c6fe	187	all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
mbed_official	340:28d1f895c6fe	188
mbed_official	340:28d1f895c6fe	189	(+) Call the function HAL_SPI_Init() to configure the selected device with
mbed_official	340:28d1f895c6fe	190	the selected configuration:
mbed_official	340:28d1f895c6fe	191	(++) Mode
mbed_official	340:28d1f895c6fe	192	(++) Direction
mbed_official	340:28d1f895c6fe	193	(++) Data Size
mbed_official	340:28d1f895c6fe	194	(++) Clock Polarity and Phase
mbed_official	340:28d1f895c6fe	195	(++) NSS Management
mbed_official	340:28d1f895c6fe	196	(++) BaudRate Prescaler
mbed_official	340:28d1f895c6fe	197	(++) FirstBit
mbed_official	340:28d1f895c6fe	198	(++) TIMode
mbed_official	340:28d1f895c6fe	199	(++) CRC Calculation
mbed_official	340:28d1f895c6fe	200	(++) CRC Polynomial if CRC enabled
mbed_official	340:28d1f895c6fe	201	(++) CRC Length, used only with Data8 and Data16
mbed_official	340:28d1f895c6fe	202	(++) FIFO reception threshold
mbed_official	340:28d1f895c6fe	203
mbed_official	340:28d1f895c6fe	204	(+) Call the function HAL_SPI_DeInit() to restore the default configuration
mbed_official	340:28d1f895c6fe	205	of the selected SPIx periperal.
mbed_official	340:28d1f895c6fe	206
mbed_official	340:28d1f895c6fe	207	@endverbatim
mbed_official	340:28d1f895c6fe	208	* @{
mbed_official	340:28d1f895c6fe	209	*/
mbed_official	340:28d1f895c6fe	210
mbed_official	340:28d1f895c6fe	211	/**
mbed_official	340:28d1f895c6fe	212	* @brief Initializes the SPI according to the specified parameters
mbed_official	340:28d1f895c6fe	213	* in the SPI_InitTypeDef and create the associated handle.
mbed_official	340:28d1f895c6fe	214	* @param hspi: SPI handle
mbed_official	340:28d1f895c6fe	215	* @retval HAL status
mbed_official	340:28d1f895c6fe	216	*/
mbed_official	340:28d1f895c6fe	217	HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
mbed_official	340:28d1f895c6fe	218	{
mbed_official	340:28d1f895c6fe	219	uint32_t frxth;
mbed_official	340:28d1f895c6fe	220
mbed_official	340:28d1f895c6fe	221	/* Check the SPI handle allocation */
mbed_official	340:28d1f895c6fe	222	if(hspi == HAL_NULL)
mbed_official	340:28d1f895c6fe	223	{
mbed_official	340:28d1f895c6fe	224	return HAL_ERROR;
mbed_official	340:28d1f895c6fe	225	}
mbed_official	340:28d1f895c6fe	226
mbed_official	340:28d1f895c6fe	227	/* Check the parameters */
mbed_official	340:28d1f895c6fe	228	assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
mbed_official	340:28d1f895c6fe	229	assert_param(IS_SPI_MODE(hspi->Init.Mode));
mbed_official	340:28d1f895c6fe	230	assert_param(IS_SPI_DIRECTION(hspi->Init.Direction));
mbed_official	340:28d1f895c6fe	231	assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
mbed_official	340:28d1f895c6fe	232	assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
mbed_official	340:28d1f895c6fe	233	assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
mbed_official	340:28d1f895c6fe	234	assert_param(IS_SPI_NSS(hspi->Init.NSS));
mbed_official	340:28d1f895c6fe	235	assert_param(IS_SPI_NSSP(hspi->Init.NSSPMode));
mbed_official	340:28d1f895c6fe	236	assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
mbed_official	340:28d1f895c6fe	237	assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
mbed_official	340:28d1f895c6fe	238	assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
mbed_official	340:28d1f895c6fe	239	assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
mbed_official	340:28d1f895c6fe	240	assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
mbed_official	340:28d1f895c6fe	241	assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength));
mbed_official	340:28d1f895c6fe	242
mbed_official	340:28d1f895c6fe	243	hspi->State = HAL_SPI_STATE_BUSY;
mbed_official	340:28d1f895c6fe	244
mbed_official	340:28d1f895c6fe	245	/* Init the low level hardware : GPIO, CLOCK, NVIC... */
mbed_official	340:28d1f895c6fe	246	HAL_SPI_MspInit(hspi);
mbed_official	340:28d1f895c6fe	247
mbed_official	340:28d1f895c6fe	248	/* Disable the selected SPI peripheral */
mbed_official	340:28d1f895c6fe	249	__HAL_SPI_DISABLE(hspi);
mbed_official	340:28d1f895c6fe	250
mbed_official	340:28d1f895c6fe	251	/* Align by default the rs fifo threshold on the data size */
mbed_official	340:28d1f895c6fe	252	if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
mbed_official	340:28d1f895c6fe	253	{
mbed_official	340:28d1f895c6fe	254	frxth = SPI_RXFIFO_THRESHOLD_HF;
mbed_official	340:28d1f895c6fe	255	}
mbed_official	340:28d1f895c6fe	256	else
mbed_official	340:28d1f895c6fe	257	{
mbed_official	340:28d1f895c6fe	258	frxth = SPI_RXFIFO_THRESHOLD_QF;
mbed_official	340:28d1f895c6fe	259	}
mbed_official	340:28d1f895c6fe	260
mbed_official	340:28d1f895c6fe	261	/* CRC calculation is valid only for 16Bit and 8 Bit */
mbed_official	340:28d1f895c6fe	262	if(( hspi->Init.DataSize != SPI_DATASIZE_16BIT ) && ( hspi->Init.DataSize != SPI_DATASIZE_8BIT ))
mbed_official	340:28d1f895c6fe	263	{
mbed_official	340:28d1f895c6fe	264	/* CRC must be disabled */
mbed_official	340:28d1f895c6fe	265	hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLED;
mbed_official	340:28d1f895c6fe	266	}
mbed_official	340:28d1f895c6fe	267
mbed_official	340:28d1f895c6fe	268	/* Align the CRC Length on the data size */
mbed_official	340:28d1f895c6fe	269	if( hspi->Init.CRCLength == SPI_CRC_LENGTH_DATASIZE)
mbed_official	340:28d1f895c6fe	270	{
mbed_official	340:28d1f895c6fe	271	/* CRC Lengtht aligned on the data size : value set by default */
mbed_official	340:28d1f895c6fe	272	if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
mbed_official	340:28d1f895c6fe	273	{
mbed_official	340:28d1f895c6fe	274	hspi->Init.CRCLength = SPI_CRC_LENGTH_16BIT;
mbed_official	340:28d1f895c6fe	275	}
mbed_official	340:28d1f895c6fe	276	else
mbed_official	340:28d1f895c6fe	277	{
mbed_official	340:28d1f895c6fe	278	hspi->Init.CRCLength = SPI_CRC_LENGTH_8BIT;
mbed_official	340:28d1f895c6fe	279	}
mbed_official	340:28d1f895c6fe	280	}
mbed_official	340:28d1f895c6fe	281
mbed_official	340:28d1f895c6fe	282	/---------------------------- SPIx CR1 & CR2 Configuration ------------------------/
mbed_official	340:28d1f895c6fe	283	/* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management,
mbed_official	340:28d1f895c6fe	284	Communication speed, First bit, CRC calculation state, CRC Length */
mbed_official	340:28d1f895c6fe	285	hspi->Instance->CR1 = (hspi->Init.Mode \| hspi->Init.Direction \|
mbed_official	340:28d1f895c6fe	286	hspi->Init.CLKPolarity \| hspi->Init.CLKPhase \| (hspi->Init.NSS & SPI_CR1_SSM) \|
mbed_official	340:28d1f895c6fe	287	hspi->Init.BaudRatePrescaler \| hspi->Init.FirstBit \| hspi->Init.CRCCalculation);
mbed_official	340:28d1f895c6fe	288
mbed_official	340:28d1f895c6fe	289	if( hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
mbed_official	340:28d1f895c6fe	290	{
mbed_official	340:28d1f895c6fe	291	hspi->Instance->CR1\|= SPI_CR1_CRCL;
mbed_official	340:28d1f895c6fe	292	}
mbed_official	340:28d1f895c6fe	293
mbed_official	340:28d1f895c6fe	294	/* Configure : NSS management */
mbed_official	340:28d1f895c6fe	295	/* Configure : Rx Fifo Threshold */
mbed_official	340:28d1f895c6fe	296	hspi->Instance->CR2 = (((hspi->Init.NSS >> 16) & SPI_CR2_SSOE) \| hspi->Init.TIMode \| hspi->Init.NSSPMode \|
mbed_official	340:28d1f895c6fe	297	hspi->Init.DataSize ) \| frxth;
mbed_official	340:28d1f895c6fe	298
mbed_official	340:28d1f895c6fe	299	/---------------------------- SPIx CRCPOLY Configuration --------------------/
mbed_official	340:28d1f895c6fe	300	/* Configure : CRC Polynomial */
mbed_official	340:28d1f895c6fe	301	hspi->Instance->CRCPR = hspi->Init.CRCPolynomial;
mbed_official	340:28d1f895c6fe	302
mbed_official	340:28d1f895c6fe	303	/* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
mbed_official	340:28d1f895c6fe	304	hspi->Instance->I2SCFGR &= (uint16_t)(~SPI_I2SCFGR_I2SMOD);
mbed_official	340:28d1f895c6fe	305
mbed_official	340:28d1f895c6fe	306	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official	340:28d1f895c6fe	307	hspi->State= HAL_SPI_STATE_READY;
mbed_official	340:28d1f895c6fe	308
mbed_official	340:28d1f895c6fe	309	return HAL_OK;
mbed_official	340:28d1f895c6fe	310	}
mbed_official	340:28d1f895c6fe	311
mbed_official	340:28d1f895c6fe	312	/**
mbed_official	340:28d1f895c6fe	313	* @brief DeInitializes the SPI peripheral
mbed_official	340:28d1f895c6fe	314	* @param hspi: SPI handle
mbed_official	340:28d1f895c6fe	315	* @retval HAL status
mbed_official	340:28d1f895c6fe	316	*/
mbed_official	340:28d1f895c6fe	317	HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
mbed_official	340:28d1f895c6fe	318	{
mbed_official	340:28d1f895c6fe	319	/* Check the SPI handle allocation */
mbed_official	340:28d1f895c6fe	320	if(hspi == HAL_NULL)
mbed_official	340:28d1f895c6fe	321	{
mbed_official	340:28d1f895c6fe	322	return HAL_ERROR;
mbed_official	340:28d1f895c6fe	323	}
mbed_official	340:28d1f895c6fe	324
mbed_official	340:28d1f895c6fe	325	/* Check the parameters */
mbed_official	340:28d1f895c6fe	326	assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
mbed_official	340:28d1f895c6fe	327
mbed_official	340:28d1f895c6fe	328	hspi->State = HAL_SPI_STATE_BUSY;
mbed_official	340:28d1f895c6fe	329
mbed_official	340:28d1f895c6fe	330	/* Disable the SPI Peripheral Clock */
mbed_official	340:28d1f895c6fe	331	__HAL_SPI_DISABLE(hspi);
mbed_official	340:28d1f895c6fe	332
mbed_official	340:28d1f895c6fe	333	/* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
mbed_official	340:28d1f895c6fe	334	HAL_SPI_MspDeInit(hspi);
mbed_official	340:28d1f895c6fe	335
mbed_official	340:28d1f895c6fe	336	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official	340:28d1f895c6fe	337	hspi->State = HAL_SPI_STATE_RESET;
mbed_official	340:28d1f895c6fe	338
mbed_official	340:28d1f895c6fe	339	__HAL_UNLOCK(hspi);
mbed_official	340:28d1f895c6fe	340
mbed_official	340:28d1f895c6fe	341	return HAL_OK;
mbed_official	340:28d1f895c6fe	342	}
mbed_official	340:28d1f895c6fe	343
mbed_official	340:28d1f895c6fe	344	/**
mbed_official	340:28d1f895c6fe	345	* @brief SPI MSP Init
mbed_official	340:28d1f895c6fe	346	* @param hspi: SPI handle
mbed_official	340:28d1f895c6fe	347	* @retval None
mbed_official	340:28d1f895c6fe	348	*/
mbed_official	340:28d1f895c6fe	349	__weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
mbed_official	340:28d1f895c6fe	350	{
mbed_official	340:28d1f895c6fe	351	/* NOTE : This function Should not be modified, when the callback is needed,
mbed_official	340:28d1f895c6fe	352	the HAL_SPI_MspInit could be implenetd in the user file
mbed_official	340:28d1f895c6fe	353	*/
mbed_official	340:28d1f895c6fe	354	}
mbed_official	340:28d1f895c6fe	355
mbed_official	340:28d1f895c6fe	356	/**
mbed_official	340:28d1f895c6fe	357	* @brief SPI MSP DeInit
mbed_official	340:28d1f895c6fe	358	* @param hspi: SPI handle
mbed_official	340:28d1f895c6fe	359	* @retval None
mbed_official	340:28d1f895c6fe	360	*/
mbed_official	340:28d1f895c6fe	361	__weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
mbed_official	340:28d1f895c6fe	362	{
mbed_official	340:28d1f895c6fe	363	/* NOTE : This function Should not be modified, when the callback is needed,
mbed_official	340:28d1f895c6fe	364	the HAL_SPI_MspDeInit could be implenetd in the user file
mbed_official	340:28d1f895c6fe	365	*/
mbed_official	340:28d1f895c6fe	366	}
mbed_official	340:28d1f895c6fe	367
mbed_official	340:28d1f895c6fe	368	/**
mbed_official	340:28d1f895c6fe	369	* @}
mbed_official	340:28d1f895c6fe	370	*/
mbed_official	340:28d1f895c6fe	371
mbed_official	340:28d1f895c6fe	372	/** @defgroup SPI_Exported_Functions_Group2 I/O operation functions
mbed_official	340:28d1f895c6fe	373	* @brief Data transfers functions
mbed_official	340:28d1f895c6fe	374	*
mbed_official	340:28d1f895c6fe	375	@verbatim
mbed_official	340:28d1f895c6fe	376	===============================================================================
mbed_official	340:28d1f895c6fe	377	##### IO operation functions #####
mbed_official	340:28d1f895c6fe	378	===============================================================================
mbed_official	340:28d1f895c6fe	379	This subsection provides a set of functions allowing to manage the SPI
mbed_official	340:28d1f895c6fe	380	data transfers.
mbed_official	340:28d1f895c6fe	381
mbed_official	340:28d1f895c6fe	382	[..] The SPI supports master and slave mode :
mbed_official	340:28d1f895c6fe	383
mbed_official	340:28d1f895c6fe	384	(#) There are two modes of transfer:
mbed_official	340:28d1f895c6fe	385	(++) Blocking mode: The communication is performed in polling mode.
mbed_official	340:28d1f895c6fe	386	The HAL status of all data processing is returned by the same function
mbed_official	340:28d1f895c6fe	387	after finishing transfer.
mbed_official	340:28d1f895c6fe	388	(++) Non Blocking mode: The communication is performed using Interrupts
mbed_official	340:28d1f895c6fe	389	or DMA, These APIs return the HAL status.
mbed_official	340:28d1f895c6fe	390	The end of the data processing will be indicated through the
mbed_official	340:28d1f895c6fe	391	dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
mbed_official	340:28d1f895c6fe	392	using DMA mode.
mbed_official	340:28d1f895c6fe	393	The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
mbed_official	340:28d1f895c6fe	394	will be executed respectivelly at the end of the transmit or Receive process
mbed_official	340:28d1f895c6fe	395	The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected
mbed_official	340:28d1f895c6fe	396
mbed_official	340:28d1f895c6fe	397	(#) Blocking mode APIs are :
mbed_official	340:28d1f895c6fe	398	(++) HAL_SPI_Transmit()in 1Line (simplex) and 2Lines (full duplex) mode
mbed_official	340:28d1f895c6fe	399	(++) HAL_SPI_Receive() in 1Line (simplex) and 2Lines (full duplex) mode
mbed_official	340:28d1f895c6fe	400	(++) HAL_SPI_TransmitReceive() in full duplex mode
mbed_official	340:28d1f895c6fe	401
mbed_official	340:28d1f895c6fe	402	(#) Non Blocking mode APIs with Interrupt are :
mbed_official	340:28d1f895c6fe	403	(++) HAL_SPI_Transmit_IT()in 1Line (simplex) and 2Lines (full duplex) mode
mbed_official	340:28d1f895c6fe	404	(++) HAL_SPI_Receive_IT() in 1Line (simplex) and 2Lines (full duplex) mode
mbed_official	340:28d1f895c6fe	405	(++) HAL_SPI_TransmitReceive_IT()in full duplex mode
mbed_official	340:28d1f895c6fe	406	(++) HAL_SPI_IRQHandler()
mbed_official	340:28d1f895c6fe	407
mbed_official	340:28d1f895c6fe	408	(#) Non Blocking mode functions with DMA are :
mbed_official	340:28d1f895c6fe	409	(++) HAL_SPI_Transmit_DMA()in 1Line (simplex) and 2Lines (full duplex) mode
mbed_official	340:28d1f895c6fe	410	(++) HAL_SPI_Receive_DMA() in 1Line (simplex) and 2Lines (full duplex) mode
mbed_official	340:28d1f895c6fe	411	(++) HAL_SPI_TransmitReceie_DMA() in full duplex mode
mbed_official	340:28d1f895c6fe	412
mbed_official	340:28d1f895c6fe	413	(#) A set of Transfer Complete Callbacks are provided in Non Blocking mode:
mbed_official	340:28d1f895c6fe	414	(++) HAL_SPI_TxCpltCallback()
mbed_official	340:28d1f895c6fe	415	(++) HAL_SPI_RxCpltCallback()
mbed_official	340:28d1f895c6fe	416	(++) HAL_SPI_ErrorCallback()
mbed_official	340:28d1f895c6fe	417	(++) HAL_SPI_TxRxCpltCallback()
mbed_official	340:28d1f895c6fe	418
mbed_official	340:28d1f895c6fe	419	@endverbatim
mbed_official	340:28d1f895c6fe	420	* @{
mbed_official	340:28d1f895c6fe	421	*/
mbed_official	340:28d1f895c6fe	422
mbed_official	340:28d1f895c6fe	423	/**
mbed_official	340:28d1f895c6fe	424	* @brief Transmit an amount of data in blocking mode
mbed_official	340:28d1f895c6fe	425	* @param hspi: SPI handle
mbed_official	340:28d1f895c6fe	426	* @param pData: pointer to data buffer
mbed_official	340:28d1f895c6fe	427	* @param Size: amount of data to be sent
mbed_official	340:28d1f895c6fe	428	* @param Timeout: Timeout duration
mbed_official	340:28d1f895c6fe	429	* @retval HAL status
mbed_official	340:28d1f895c6fe	430	*/
mbed_official	340:28d1f895c6fe	431	HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size, uint32_t Timeout)
mbed_official	340:28d1f895c6fe	432	{
mbed_official	340:28d1f895c6fe	433	assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
mbed_official	340:28d1f895c6fe	434
mbed_official	340:28d1f895c6fe	435	if(hspi->State != HAL_SPI_STATE_READY)
mbed_official	340:28d1f895c6fe	436	{
mbed_official	340:28d1f895c6fe	437	return HAL_BUSY;
mbed_official	340:28d1f895c6fe	438	}
mbed_official	340:28d1f895c6fe	439
mbed_official	340:28d1f895c6fe	440	if((pData == HAL_NULL ) \|\| (Size == 0))
mbed_official	340:28d1f895c6fe	441	{
mbed_official	340:28d1f895c6fe	442	return HAL_ERROR;
mbed_official	340:28d1f895c6fe	443	}
mbed_official	340:28d1f895c6fe	444
mbed_official	340:28d1f895c6fe	445	/* Process Locked */
mbed_official	340:28d1f895c6fe	446	__HAL_LOCK(hspi);
mbed_official	340:28d1f895c6fe	447
mbed_official	340:28d1f895c6fe	448	/* Set the transaction information */
mbed_official	340:28d1f895c6fe	449	hspi->State = HAL_SPI_STATE_BUSY_TX;
mbed_official	340:28d1f895c6fe	450	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official	340:28d1f895c6fe	451	hspi->pTxBuffPtr = pData;
mbed_official	340:28d1f895c6fe	452	hspi->TxXferSize = Size;
mbed_official	340:28d1f895c6fe	453	hspi->TxXferCount = Size;
mbed_official	340:28d1f895c6fe	454	hspi->pRxBuffPtr = HAL_NULL;
mbed_official	340:28d1f895c6fe	455	hspi->RxXferSize = 0;
mbed_official	340:28d1f895c6fe	456	hspi->RxXferCount = 0;
mbed_official	340:28d1f895c6fe	457
mbed_official	340:28d1f895c6fe	458	/* Reset CRC Calculation */
mbed_official	340:28d1f895c6fe	459	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	340:28d1f895c6fe	460	{
mbed_official	340:28d1f895c6fe	461	__HAL_SPI_RESET_CRC(hspi);
mbed_official	340:28d1f895c6fe	462	}
mbed_official	340:28d1f895c6fe	463
mbed_official	340:28d1f895c6fe	464	/* Configure communication direction : 1Line */
mbed_official	340:28d1f895c6fe	465	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
mbed_official	340:28d1f895c6fe	466	{
mbed_official	340:28d1f895c6fe	467	__HAL_SPI_1LINE_TX(hspi);
mbed_official	340:28d1f895c6fe	468	}
mbed_official	340:28d1f895c6fe	469
mbed_official	340:28d1f895c6fe	470	/* Check if the SPI is already enabled */
mbed_official	340:28d1f895c6fe	471	if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official	340:28d1f895c6fe	472	{
mbed_official	340:28d1f895c6fe	473	/* Enable SPI peripheral */
mbed_official	340:28d1f895c6fe	474	__HAL_SPI_ENABLE(hspi);
mbed_official	340:28d1f895c6fe	475	}
mbed_official	340:28d1f895c6fe	476
mbed_official	340:28d1f895c6fe	477	/* Transmit data in 16 Bit mode */
mbed_official	340:28d1f895c6fe	478	if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
mbed_official	340:28d1f895c6fe	479	{
mbed_official	340:28d1f895c6fe	480	while (hspi->TxXferCount > 0)
mbed_official	340:28d1f895c6fe	481	{
mbed_official	340:28d1f895c6fe	482	/* Wait until TXE flag is set to send data */
mbed_official	340:28d1f895c6fe	483	if(SPI_WaitFlagStateUntilTimeout(hspi,SPI_FLAG_TXE,SPI_FLAG_TXE,Timeout) != HAL_OK)
mbed_official	340:28d1f895c6fe	484	{
mbed_official	340:28d1f895c6fe	485	return HAL_TIMEOUT;
mbed_official	340:28d1f895c6fe	486	}
mbed_official	340:28d1f895c6fe	487	hspi->Instance->DR = ((uint16_t )hspi->pTxBuffPtr);
mbed_official	340:28d1f895c6fe	488	hspi->pTxBuffPtr += sizeof(uint16_t);
mbed_official	340:28d1f895c6fe	489	hspi->TxXferCount--;
mbed_official	340:28d1f895c6fe	490	}
mbed_official	340:28d1f895c6fe	491	}
mbed_official	340:28d1f895c6fe	492	/* Transmit data in 8 Bit mode */
mbed_official	340:28d1f895c6fe	493	else
mbed_official	340:28d1f895c6fe	494	{
mbed_official	340:28d1f895c6fe	495	while (hspi->TxXferCount > 0)
mbed_official	340:28d1f895c6fe	496	{
mbed_official	340:28d1f895c6fe	497	if(hspi->TxXferCount != 0x1)
mbed_official	340:28d1f895c6fe	498	{
mbed_official	340:28d1f895c6fe	499	/* Wait until TXE flag is set to send data */
mbed_official	340:28d1f895c6fe	500	if(SPI_WaitFlagStateUntilTimeout(hspi,SPI_FLAG_TXE,SPI_FLAG_TXE,Timeout) != HAL_OK)
mbed_official	340:28d1f895c6fe	501	{
mbed_official	340:28d1f895c6fe	502	return HAL_TIMEOUT;
mbed_official	340:28d1f895c6fe	503	}
mbed_official	340:28d1f895c6fe	504	hspi->Instance->DR = ((uint16_t)hspi->pTxBuffPtr);
mbed_official	340:28d1f895c6fe	505	hspi->pTxBuffPtr += sizeof(uint16_t);
mbed_official	340:28d1f895c6fe	506	hspi->TxXferCount -= 2;
mbed_official	340:28d1f895c6fe	507	}
mbed_official	340:28d1f895c6fe	508	else
mbed_official	340:28d1f895c6fe	509	{
mbed_official	340:28d1f895c6fe	510	/* Wait until TXE flag is set to send data */
mbed_official	340:28d1f895c6fe	511	if(SPI_WaitFlagStateUntilTimeout(hspi,SPI_FLAG_TXE,SPI_FLAG_TXE,Timeout) != HAL_OK)
mbed_official	340:28d1f895c6fe	512	{
mbed_official	340:28d1f895c6fe	513	return HAL_TIMEOUT;
mbed_official	340:28d1f895c6fe	514	}
mbed_official	340:28d1f895c6fe	515	((__IO uint8_t)&hspi->Instance->DR) = (*hspi->pTxBuffPtr++);
mbed_official	340:28d1f895c6fe	516	hspi->TxXferCount--;
mbed_official	340:28d1f895c6fe	517	}
mbed_official	340:28d1f895c6fe	518	}
mbed_official	340:28d1f895c6fe	519	}
mbed_official	340:28d1f895c6fe	520
mbed_official	340:28d1f895c6fe	521	/* Enable CRC Transmission */
mbed_official	340:28d1f895c6fe	522	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	340:28d1f895c6fe	523	{
mbed_official	340:28d1f895c6fe	524	hspi->Instance->CR1\|= SPI_CR1_CRCNEXT;
mbed_official	340:28d1f895c6fe	525	}
mbed_official	340:28d1f895c6fe	526
mbed_official	340:28d1f895c6fe	527	/* Check the end of the transaction */
mbed_official	340:28d1f895c6fe	528	if(SPI_EndRxTxTransaction(hspi,Timeout) != HAL_OK)
mbed_official	340:28d1f895c6fe	529	{
mbed_official	340:28d1f895c6fe	530	return HAL_TIMEOUT;
mbed_official	340:28d1f895c6fe	531	}
mbed_official	340:28d1f895c6fe	532
mbed_official	340:28d1f895c6fe	533	/* Clear OVERUN flag in 2 Lines communication mode because received is not read */
mbed_official	340:28d1f895c6fe	534	if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
mbed_official	340:28d1f895c6fe	535	{
mbed_official	340:28d1f895c6fe	536	__HAL_SPI_CLEAR_OVRFLAG(hspi);
mbed_official	340:28d1f895c6fe	537	}
mbed_official	340:28d1f895c6fe	538
mbed_official	340:28d1f895c6fe	539	hspi->State = HAL_SPI_STATE_READY;
mbed_official	340:28d1f895c6fe	540
mbed_official	340:28d1f895c6fe	541	/* Process Unlocked */
mbed_official	340:28d1f895c6fe	542	__HAL_UNLOCK(hspi);
mbed_official	340:28d1f895c6fe	543
mbed_official	340:28d1f895c6fe	544	if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
mbed_official	340:28d1f895c6fe	545	{
mbed_official	340:28d1f895c6fe	546	return HAL_ERROR;
mbed_official	340:28d1f895c6fe	547	}
mbed_official	340:28d1f895c6fe	548	else
mbed_official	340:28d1f895c6fe	549	{
mbed_official	340:28d1f895c6fe	550	return HAL_OK;
mbed_official	340:28d1f895c6fe	551	}
mbed_official	340:28d1f895c6fe	552	}
mbed_official	340:28d1f895c6fe	553
mbed_official	340:28d1f895c6fe	554	/**
mbed_official	340:28d1f895c6fe	555	* @brief Receive an amount of data in blocking mode
mbed_official	340:28d1f895c6fe	556	* @param hspi: SPI handle
mbed_official	340:28d1f895c6fe	557	* @param pData: pointer to data buffer
mbed_official	340:28d1f895c6fe	558	* @param Size: amount of data to be sent
mbed_official	340:28d1f895c6fe	559	* @param Timeout: Timeout duration
mbed_official	340:28d1f895c6fe	560	* @retval HAL status
mbed_official	340:28d1f895c6fe	561	*/
mbed_official	340:28d1f895c6fe	562	HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size, uint32_t Timeout)
mbed_official	340:28d1f895c6fe	563	{
mbed_official	340:28d1f895c6fe	564	__IO uint16_t tmpreg;
mbed_official	340:28d1f895c6fe	565
mbed_official	340:28d1f895c6fe	566	if(hspi->State != HAL_SPI_STATE_READY)
mbed_official	340:28d1f895c6fe	567	{
mbed_official	340:28d1f895c6fe	568	return HAL_BUSY;
mbed_official	340:28d1f895c6fe	569	}
mbed_official	340:28d1f895c6fe	570
mbed_official	340:28d1f895c6fe	571	if((pData == HAL_NULL ) \|\| (Size == 0))
mbed_official	340:28d1f895c6fe	572	{
mbed_official	340:28d1f895c6fe	573	return HAL_ERROR;
mbed_official	340:28d1f895c6fe	574	}
mbed_official	340:28d1f895c6fe	575
mbed_official	340:28d1f895c6fe	576	if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
mbed_official	340:28d1f895c6fe	577	{
mbed_official	340:28d1f895c6fe	578	/* the receive process is not supported in 2Lines direction master mode */
mbed_official	340:28d1f895c6fe	579	/* in this case we call the transmitReceive process */
mbed_official	340:28d1f895c6fe	580	return HAL_SPI_TransmitReceive(hspi,pData,pData,Size,Timeout);
mbed_official	340:28d1f895c6fe	581	}
mbed_official	340:28d1f895c6fe	582
mbed_official	340:28d1f895c6fe	583	/* Process Locked */
mbed_official	340:28d1f895c6fe	584	__HAL_LOCK(hspi);
mbed_official	340:28d1f895c6fe	585
mbed_official	340:28d1f895c6fe	586	hspi->State = HAL_SPI_STATE_BUSY_RX;
mbed_official	340:28d1f895c6fe	587	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official	340:28d1f895c6fe	588	hspi->pRxBuffPtr = pData;
mbed_official	340:28d1f895c6fe	589	hspi->RxXferSize = Size;
mbed_official	340:28d1f895c6fe	590	hspi->RxXferCount = Size;
mbed_official	340:28d1f895c6fe	591	hspi->pTxBuffPtr = HAL_NULL;
mbed_official	340:28d1f895c6fe	592	hspi->TxXferSize = 0;
mbed_official	340:28d1f895c6fe	593	hspi->TxXferCount = 0;
mbed_official	340:28d1f895c6fe	594
mbed_official	340:28d1f895c6fe	595	/* Reset CRC Calculation */
mbed_official	340:28d1f895c6fe	596	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	340:28d1f895c6fe	597	{
mbed_official	340:28d1f895c6fe	598	__HAL_SPI_RESET_CRC(hspi);
mbed_official	340:28d1f895c6fe	599	}
mbed_official	340:28d1f895c6fe	600
mbed_official	340:28d1f895c6fe	601	/* Set the Rx Fido thresold */
mbed_official	340:28d1f895c6fe	602	if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
mbed_official	340:28d1f895c6fe	603	{
mbed_official	340:28d1f895c6fe	604	/* set fiforxthresold according the reception data lenght: 16bit */
mbed_official	340:28d1f895c6fe	605	CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
mbed_official	340:28d1f895c6fe	606	}
mbed_official	340:28d1f895c6fe	607	else
mbed_official	340:28d1f895c6fe	608	{
mbed_official	340:28d1f895c6fe	609	/* set fiforxthresold according the reception data lenght: 8bit */
mbed_official	340:28d1f895c6fe	610	SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
mbed_official	340:28d1f895c6fe	611	}
mbed_official	340:28d1f895c6fe	612
mbed_official	340:28d1f895c6fe	613	/* Configure communication direction 1Line and enabled SPI if needed */
mbed_official	340:28d1f895c6fe	614	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
mbed_official	340:28d1f895c6fe	615	{
mbed_official	340:28d1f895c6fe	616	__HAL_SPI_1LINE_RX(hspi);
mbed_official	340:28d1f895c6fe	617	}
mbed_official	340:28d1f895c6fe	618
mbed_official	340:28d1f895c6fe	619	/* Check if the SPI is already enabled */
mbed_official	340:28d1f895c6fe	620	if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official	340:28d1f895c6fe	621	{
mbed_official	340:28d1f895c6fe	622	/* Enable SPI peripheral */
mbed_official	340:28d1f895c6fe	623	__HAL_SPI_ENABLE(hspi);
mbed_official	340:28d1f895c6fe	624	}
mbed_official	340:28d1f895c6fe	625
mbed_official	340:28d1f895c6fe	626	/* Receive data in 8 Bit mode */
mbed_official	340:28d1f895c6fe	627	if(hspi->Init.DataSize <= SPI_DATASIZE_8BIT)
mbed_official	340:28d1f895c6fe	628	{
mbed_official	340:28d1f895c6fe	629	while(hspi->RxXferCount > 1)
mbed_official	340:28d1f895c6fe	630	{
mbed_official	340:28d1f895c6fe	631	/* Wait until the RXNE flag */
mbed_official	340:28d1f895c6fe	632	if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
mbed_official	340:28d1f895c6fe	633	{
mbed_official	340:28d1f895c6fe	634	return HAL_TIMEOUT;
mbed_official	340:28d1f895c6fe	635	}
mbed_official	340:28d1f895c6fe	636	(hspi->pRxBuffPtr++)= (__IO uint8_t *)&hspi->Instance->DR;
mbed_official	340:28d1f895c6fe	637	hspi->RxXferCount--;
mbed_official	340:28d1f895c6fe	638	}
mbed_official	340:28d1f895c6fe	639	}
mbed_official	340:28d1f895c6fe	640	else /* Receive data in 16 Bit mode */
mbed_official	340:28d1f895c6fe	641	{
mbed_official	340:28d1f895c6fe	642	while(hspi->RxXferCount > 1 )
mbed_official	340:28d1f895c6fe	643	{
mbed_official	340:28d1f895c6fe	644	/* Wait until RXNE flag is reset to read data */
mbed_official	340:28d1f895c6fe	645	if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
mbed_official	340:28d1f895c6fe	646	{
mbed_official	340:28d1f895c6fe	647	return HAL_TIMEOUT;
mbed_official	340:28d1f895c6fe	648	}
mbed_official	340:28d1f895c6fe	649	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
mbed_official	340:28d1f895c6fe	650	hspi->pRxBuffPtr += sizeof(uint16_t);
mbed_official	340:28d1f895c6fe	651	hspi->RxXferCount--;
mbed_official	340:28d1f895c6fe	652	}
mbed_official	340:28d1f895c6fe	653	}
mbed_official	340:28d1f895c6fe	654
mbed_official	340:28d1f895c6fe	655	/* Enable CRC Transmission */
mbed_official	340:28d1f895c6fe	656	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	340:28d1f895c6fe	657	{
mbed_official	340:28d1f895c6fe	658	hspi->Instance->CR1 \|= SPI_CR1_CRCNEXT;
mbed_official	340:28d1f895c6fe	659	}
mbed_official	340:28d1f895c6fe	660
mbed_official	340:28d1f895c6fe	661	/* Wait until RXNE flag is set */
mbed_official	340:28d1f895c6fe	662	if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
mbed_official	340:28d1f895c6fe	663	{
mbed_official	340:28d1f895c6fe	664	return HAL_TIMEOUT;
mbed_official	340:28d1f895c6fe	665	}
mbed_official	340:28d1f895c6fe	666
mbed_official	340:28d1f895c6fe	667	/* Receive last data in 16 Bit mode */
mbed_official	340:28d1f895c6fe	668	if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
mbed_official	340:28d1f895c6fe	669	{
mbed_official	340:28d1f895c6fe	670	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
mbed_official	340:28d1f895c6fe	671	hspi->pRxBuffPtr += sizeof(uint16_t);
mbed_official	340:28d1f895c6fe	672	}
mbed_official	340:28d1f895c6fe	673	/* Receive last data in 8 Bit mode */
mbed_official	340:28d1f895c6fe	674	else
mbed_official	340:28d1f895c6fe	675	{
mbed_official	340:28d1f895c6fe	676	(hspi->pRxBuffPtr++) = (__IO uint8_t *)&hspi->Instance->DR;
mbed_official	340:28d1f895c6fe	677	}
mbed_official	340:28d1f895c6fe	678	hspi->RxXferCount--;
mbed_official	340:28d1f895c6fe	679
mbed_official	340:28d1f895c6fe	680	/* Read CRC from DR to close CRC calculation process */
mbed_official	340:28d1f895c6fe	681	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	340:28d1f895c6fe	682	{
mbed_official	340:28d1f895c6fe	683	/* Wait until TXE flag */
mbed_official	340:28d1f895c6fe	684	if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
mbed_official	340:28d1f895c6fe	685	{
mbed_official	340:28d1f895c6fe	686	/* Erreur on the CRC reception */
mbed_official	340:28d1f895c6fe	687	hspi->ErrorCode\|= HAL_SPI_ERROR_CRC;
mbed_official	340:28d1f895c6fe	688	}
mbed_official	340:28d1f895c6fe	689	if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
mbed_official	340:28d1f895c6fe	690	{
mbed_official	340:28d1f895c6fe	691	tmpreg = hspi->Instance->DR;
mbed_official	340:28d1f895c6fe	692	}
mbed_official	340:28d1f895c6fe	693	else
mbed_official	340:28d1f895c6fe	694	{
mbed_official	340:28d1f895c6fe	695	tmpreg = (__IO uint8_t )&hspi->Instance->DR;
mbed_official	340:28d1f895c6fe	696	if((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
mbed_official	340:28d1f895c6fe	697	{
mbed_official	340:28d1f895c6fe	698	if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
mbed_official	340:28d1f895c6fe	699	{
mbed_official	340:28d1f895c6fe	700	/* Erreur on the CRC reception */
mbed_official	340:28d1f895c6fe	701	hspi->ErrorCode\|= HAL_SPI_ERROR_CRC;
mbed_official	340:28d1f895c6fe	702	}
mbed_official	340:28d1f895c6fe	703	tmpreg = (__IO uint8_t )&hspi->Instance->DR;
mbed_official	340:28d1f895c6fe	704	}
mbed_official	340:28d1f895c6fe	705	}
mbed_official	340:28d1f895c6fe	706	}
mbed_official	340:28d1f895c6fe	707
mbed_official	340:28d1f895c6fe	708	/* Check the end of the transaction */
mbed_official	340:28d1f895c6fe	709	if(SPI_EndRxTransaction(hspi,Timeout) != HAL_OK)
mbed_official	340:28d1f895c6fe	710	{
mbed_official	340:28d1f895c6fe	711	return HAL_TIMEOUT;
mbed_official	340:28d1f895c6fe	712	}
mbed_official	340:28d1f895c6fe	713
mbed_official	340:28d1f895c6fe	714	hspi->State = HAL_SPI_STATE_READY;
mbed_official	340:28d1f895c6fe	715
mbed_official	340:28d1f895c6fe	716	/* Check if CRC error occurred */
mbed_official	340:28d1f895c6fe	717	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
mbed_official	340:28d1f895c6fe	718	{
mbed_official	340:28d1f895c6fe	719	hspi->ErrorCode\|= HAL_SPI_ERROR_CRC;
mbed_official	340:28d1f895c6fe	720	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
mbed_official	340:28d1f895c6fe	721
mbed_official	340:28d1f895c6fe	722	/* Process Unlocked */
mbed_official	340:28d1f895c6fe	723	__HAL_UNLOCK(hspi);
mbed_official	340:28d1f895c6fe	724	return HAL_ERROR;
mbed_official	340:28d1f895c6fe	725	}
mbed_official	340:28d1f895c6fe	726
mbed_official	340:28d1f895c6fe	727	/* Process Unlocked */
mbed_official	340:28d1f895c6fe	728	__HAL_UNLOCK(hspi);
mbed_official	340:28d1f895c6fe	729
mbed_official	340:28d1f895c6fe	730	if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
mbed_official	340:28d1f895c6fe	731	{
mbed_official	340:28d1f895c6fe	732	return HAL_ERROR;
mbed_official	340:28d1f895c6fe	733	}
mbed_official	340:28d1f895c6fe	734	else
mbed_official	340:28d1f895c6fe	735	{
mbed_official	340:28d1f895c6fe	736	return HAL_OK;
mbed_official	340:28d1f895c6fe	737	}
mbed_official	340:28d1f895c6fe	738	}
mbed_official	340:28d1f895c6fe	739
mbed_official	340:28d1f895c6fe	740	/**
mbed_official	340:28d1f895c6fe	741	* @brief Transmit and Receive an amount of data in blocking mode
mbed_official	340:28d1f895c6fe	742	* @param hspi: SPI handle
mbed_official	340:28d1f895c6fe	743	* @param pTxData: pointer to transmission data buffer
mbed_official	340:28d1f895c6fe	744	* @param pRxData: pointer to reception data buffer to be
mbed_official	340:28d1f895c6fe	745	* @param Size: amount of data to be sent
mbed_official	340:28d1f895c6fe	746	* @param Timeout: Timeout duration
mbed_official	340:28d1f895c6fe	747	* @retval HAL status
mbed_official	340:28d1f895c6fe	748	*/
mbed_official	340:28d1f895c6fe	749	HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef hspi, uint8_t pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
mbed_official	340:28d1f895c6fe	750	{
mbed_official	340:28d1f895c6fe	751	__IO uint16_t tmpreg = 0;
mbed_official	340:28d1f895c6fe	752	uint32_t tickstart = 0;
mbed_official	340:28d1f895c6fe	753
mbed_official	340:28d1f895c6fe	754	assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
mbed_official	340:28d1f895c6fe	755
mbed_official	340:28d1f895c6fe	756	if(hspi->State != HAL_SPI_STATE_READY)
mbed_official	340:28d1f895c6fe	757	{
mbed_official	340:28d1f895c6fe	758	return HAL_BUSY;
mbed_official	340:28d1f895c6fe	759	}
mbed_official	340:28d1f895c6fe	760
mbed_official	340:28d1f895c6fe	761	if((pTxData == HAL_NULL) \|\| (pRxData == HAL_NULL) \|\| (Size == 0))
mbed_official	340:28d1f895c6fe	762	{
mbed_official	340:28d1f895c6fe	763	return HAL_ERROR;
mbed_official	340:28d1f895c6fe	764	}
mbed_official	340:28d1f895c6fe	765
mbed_official	340:28d1f895c6fe	766	tickstart = HAL_GetTick();
mbed_official	340:28d1f895c6fe	767
mbed_official	340:28d1f895c6fe	768	/* Process Locked */
mbed_official	340:28d1f895c6fe	769	__HAL_LOCK(hspi);
mbed_official	340:28d1f895c6fe	770
mbed_official	340:28d1f895c6fe	771	hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
mbed_official	340:28d1f895c6fe	772	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official	340:28d1f895c6fe	773	hspi->pRxBuffPtr = pRxData;
mbed_official	340:28d1f895c6fe	774	hspi->RxXferCount = Size;
mbed_official	340:28d1f895c6fe	775	hspi->RxXferSize = Size;
mbed_official	340:28d1f895c6fe	776	hspi->pTxBuffPtr = pTxData;
mbed_official	340:28d1f895c6fe	777	hspi->TxXferCount = Size;
mbed_official	340:28d1f895c6fe	778	hspi->TxXferSize = Size;
mbed_official	340:28d1f895c6fe	779
mbed_official	340:28d1f895c6fe	780	/* Reset CRC Calculation */
mbed_official	340:28d1f895c6fe	781	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	340:28d1f895c6fe	782	{
mbed_official	340:28d1f895c6fe	783	__HAL_SPI_RESET_CRC(hspi);
mbed_official	340:28d1f895c6fe	784	}
mbed_official	340:28d1f895c6fe	785
mbed_official	340:28d1f895c6fe	786	/* Set the Rx Fido threshold */
mbed_official	340:28d1f895c6fe	787	if((hspi->Init.DataSize > SPI_DATASIZE_8BIT) \|\| (hspi->RxXferCount > 1))
mbed_official	340:28d1f895c6fe	788	{
mbed_official	340:28d1f895c6fe	789	/* set fiforxthreshold according the reception data lenght: 16bit */
mbed_official	340:28d1f895c6fe	790	CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
mbed_official	340:28d1f895c6fe	791	}
mbed_official	340:28d1f895c6fe	792	else
mbed_official	340:28d1f895c6fe	793	{
mbed_official	340:28d1f895c6fe	794	/* set fiforxthreshold according the reception data lenght: 8bit */
mbed_official	340:28d1f895c6fe	795	SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
mbed_official	340:28d1f895c6fe	796	}
mbed_official	340:28d1f895c6fe	797
mbed_official	340:28d1f895c6fe	798	/* Check if the SPI is already enabled */
mbed_official	340:28d1f895c6fe	799	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official	340:28d1f895c6fe	800	{
mbed_official	340:28d1f895c6fe	801	/* Enable SPI peripheral */
mbed_official	340:28d1f895c6fe	802	__HAL_SPI_ENABLE(hspi);
mbed_official	340:28d1f895c6fe	803	}
mbed_official	340:28d1f895c6fe	804
mbed_official	340:28d1f895c6fe	805	/* Transmit and Receive data in 16 Bit mode */
mbed_official	340:28d1f895c6fe	806	if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
mbed_official	340:28d1f895c6fe	807	{
mbed_official	340:28d1f895c6fe	808	while ((hspi->TxXferCount > 0 ) \|\| (hspi->RxXferCount > 0))
mbed_official	340:28d1f895c6fe	809	{
mbed_official	340:28d1f895c6fe	810	/* Wait until TXE flag */
mbed_official	340:28d1f895c6fe	811	if((hspi->TxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_TXE) == SPI_FLAG_TXE))
mbed_official	340:28d1f895c6fe	812	{
mbed_official	340:28d1f895c6fe	813	hspi->Instance->DR = ((uint16_t )hspi->pTxBuffPtr);
mbed_official	340:28d1f895c6fe	814	hspi->pTxBuffPtr += sizeof(uint16_t);
mbed_official	340:28d1f895c6fe	815	hspi->TxXferCount--;
mbed_official	340:28d1f895c6fe	816
mbed_official	340:28d1f895c6fe	817	/* Enable CRC Transmission */
mbed_official	340:28d1f895c6fe	818	if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED))
mbed_official	340:28d1f895c6fe	819	{
mbed_official	340:28d1f895c6fe	820	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
mbed_official	340:28d1f895c6fe	821	}
mbed_official	340:28d1f895c6fe	822	}
mbed_official	340:28d1f895c6fe	823
mbed_official	340:28d1f895c6fe	824	/* Wait until RXNE flag */
mbed_official	340:28d1f895c6fe	825	if((hspi->RxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_RXNE) == SPI_FLAG_RXNE))
mbed_official	340:28d1f895c6fe	826	{
mbed_official	340:28d1f895c6fe	827	((uint16_t )hspi->pRxBuffPtr) = hspi->Instance->DR;
mbed_official	340:28d1f895c6fe	828	hspi->pRxBuffPtr += sizeof(uint16_t);
mbed_official	340:28d1f895c6fe	829	hspi->RxXferCount--;
mbed_official	340:28d1f895c6fe	830	}
mbed_official	340:28d1f895c6fe	831	if(Timeout != HAL_MAX_DELAY)
mbed_official	340:28d1f895c6fe	832	{
mbed_official	340:28d1f895c6fe	833	if((Timeout == 0) \|\| ((HAL_GetTick() - tickstart) > Timeout))
mbed_official	340:28d1f895c6fe	834	{
mbed_official	340:28d1f895c6fe	835	hspi->State = HAL_SPI_STATE_READY;
mbed_official	340:28d1f895c6fe	836	__HAL_UNLOCK(hspi);
mbed_official	340:28d1f895c6fe	837	return HAL_TIMEOUT;
mbed_official	340:28d1f895c6fe	838	}
mbed_official	340:28d1f895c6fe	839	}
mbed_official	340:28d1f895c6fe	840	}
mbed_official	340:28d1f895c6fe	841	}
mbed_official	340:28d1f895c6fe	842	/* Transmit and Receive data in 8 Bit mode */
mbed_official	340:28d1f895c6fe	843	else
mbed_official	340:28d1f895c6fe	844	{
mbed_official	340:28d1f895c6fe	845	while((hspi->TxXferCount > 0) \|\| (hspi->RxXferCount > 0))
mbed_official	340:28d1f895c6fe	846	{
mbed_official	340:28d1f895c6fe	847	/* check if TXE flag is set to send data */
mbed_official	340:28d1f895c6fe	848	if((hspi->TxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_TXE) == SPI_FLAG_TXE))
mbed_official	340:28d1f895c6fe	849	{
mbed_official	340:28d1f895c6fe	850	if(hspi->TxXferCount > 2)
mbed_official	340:28d1f895c6fe	851	{
mbed_official	340:28d1f895c6fe	852	hspi->Instance->DR = ((uint16_t)hspi->pTxBuffPtr);
mbed_official	340:28d1f895c6fe	853	hspi->pTxBuffPtr += sizeof(uint16_t);
mbed_official	340:28d1f895c6fe	854	hspi->TxXferCount -= 2;
mbed_official	340:28d1f895c6fe	855	}
mbed_official	340:28d1f895c6fe	856	else
mbed_official	340:28d1f895c6fe	857	{
mbed_official	340:28d1f895c6fe	858	(__IO uint8_t )&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
mbed_official	340:28d1f895c6fe	859	hspi->TxXferCount--;
mbed_official	340:28d1f895c6fe	860	}
mbed_official	340:28d1f895c6fe	861
mbed_official	340:28d1f895c6fe	862	/* Enable CRC Transmission */
mbed_official	340:28d1f895c6fe	863	if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED))
mbed_official	340:28d1f895c6fe	864	{
mbed_official	340:28d1f895c6fe	865	SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
mbed_official	340:28d1f895c6fe	866	}
mbed_official	340:28d1f895c6fe	867	}
mbed_official	340:28d1f895c6fe	868
mbed_official	340:28d1f895c6fe	869	/* Wait until RXNE flag is reset */
mbed_official	340:28d1f895c6fe	870	if((hspi->RxXferCount > 0) && ((hspi->Instance->SR & SPI_FLAG_RXNE) == SPI_FLAG_RXNE))
mbed_official	340:28d1f895c6fe	871	{
mbed_official	340:28d1f895c6fe	872	if(hspi->RxXferCount > 1)
mbed_official	340:28d1f895c6fe	873	{
mbed_official	340:28d1f895c6fe	874	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
mbed_official	340:28d1f895c6fe	875	hspi->pRxBuffPtr += sizeof(uint16_t);
mbed_official	340:28d1f895c6fe	876	hspi->RxXferCount -= 2;
mbed_official	340:28d1f895c6fe	877	if(hspi->RxXferCount <= 1)
mbed_official	340:28d1f895c6fe	878	{
mbed_official	340:28d1f895c6fe	879	/* set fiforxthresold before to switch on 8 bit data size */
mbed_official	340:28d1f895c6fe	880	SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
mbed_official	340:28d1f895c6fe	881	}
mbed_official	340:28d1f895c6fe	882	}
mbed_official	340:28d1f895c6fe	883	else
mbed_official	340:28d1f895c6fe	884	{
mbed_official	340:28d1f895c6fe	885	(hspi->pRxBuffPtr++) = (__IO uint8_t *)&hspi->Instance->DR;
mbed_official	340:28d1f895c6fe	886	hspi->RxXferCount--;
mbed_official	340:28d1f895c6fe	887	}
mbed_official	340:28d1f895c6fe	888	}
mbed_official	340:28d1f895c6fe	889	if(Timeout != HAL_MAX_DELAY)
mbed_official	340:28d1f895c6fe	890	{
mbed_official	340:28d1f895c6fe	891	if((Timeout == 0) \|\| ((HAL_GetTick() - tickstart) > Timeout))
mbed_official	340:28d1f895c6fe	892	{
mbed_official	340:28d1f895c6fe	893	hspi->State = HAL_SPI_STATE_READY;
mbed_official	340:28d1f895c6fe	894	__HAL_UNLOCK(hspi);
mbed_official	340:28d1f895c6fe	895	return HAL_TIMEOUT;
mbed_official	340:28d1f895c6fe	896	}
mbed_official	340:28d1f895c6fe	897	}
mbed_official	340:28d1f895c6fe	898	}
mbed_official	340:28d1f895c6fe	899	}
mbed_official	340:28d1f895c6fe	900
mbed_official	340:28d1f895c6fe	901	/* Read CRC from DR to close CRC calculation process */
mbed_official	340:28d1f895c6fe	902	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	340:28d1f895c6fe	903	{
mbed_official	340:28d1f895c6fe	904	/* Wait until TXE flag */
mbed_official	340:28d1f895c6fe	905	if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
mbed_official	340:28d1f895c6fe	906	{
mbed_official	340:28d1f895c6fe	907	/* Erreur on the CRC reception */
mbed_official	340:28d1f895c6fe	908	hspi->ErrorCode\|= HAL_SPI_ERROR_CRC;
mbed_official	340:28d1f895c6fe	909	}
mbed_official	340:28d1f895c6fe	910
mbed_official	340:28d1f895c6fe	911	if(hspi->Init.DataSize == SPI_DATASIZE_16BIT)
mbed_official	340:28d1f895c6fe	912	{
mbed_official	340:28d1f895c6fe	913	tmpreg = hspi->Instance->DR;
mbed_official	340:28d1f895c6fe	914	}
mbed_official	340:28d1f895c6fe	915	else
mbed_official	340:28d1f895c6fe	916	{
mbed_official	340:28d1f895c6fe	917	tmpreg = (__IO uint8_t )&hspi->Instance->DR;
mbed_official	340:28d1f895c6fe	918	if(hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
mbed_official	340:28d1f895c6fe	919	{
mbed_official	340:28d1f895c6fe	920	if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK)
mbed_official	340:28d1f895c6fe	921	{
mbed_official	340:28d1f895c6fe	922	/* Erreur on the CRC reception */
mbed_official	340:28d1f895c6fe	923	hspi->ErrorCode\|= HAL_SPI_ERROR_CRC;
mbed_official	340:28d1f895c6fe	924	}
mbed_official	340:28d1f895c6fe	925	tmpreg = (__IO uint8_t )&hspi->Instance->DR;
mbed_official	340:28d1f895c6fe	926	}
mbed_official	340:28d1f895c6fe	927	}
mbed_official	340:28d1f895c6fe	928	}
mbed_official	340:28d1f895c6fe	929
mbed_official	340:28d1f895c6fe	930	/* Check the end of the transaction */
mbed_official	340:28d1f895c6fe	931	if(SPI_EndRxTxTransaction(hspi,Timeout) != HAL_OK)
mbed_official	340:28d1f895c6fe	932	{
mbed_official	340:28d1f895c6fe	933	return HAL_TIMEOUT;
mbed_official	340:28d1f895c6fe	934	}
mbed_official	340:28d1f895c6fe	935
mbed_official	340:28d1f895c6fe	936	hspi->State = HAL_SPI_STATE_READY;
mbed_official	340:28d1f895c6fe	937
mbed_official	340:28d1f895c6fe	938	/* Check if CRC error occurred */
mbed_official	340:28d1f895c6fe	939	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
mbed_official	340:28d1f895c6fe	940	{
mbed_official	340:28d1f895c6fe	941	hspi->ErrorCode\|= HAL_SPI_ERROR_CRC;
mbed_official	340:28d1f895c6fe	942	/* Clear CRC Flag */
mbed_official	340:28d1f895c6fe	943	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
mbed_official	340:28d1f895c6fe	944
mbed_official	340:28d1f895c6fe	945	/* Process Unlocked */
mbed_official	340:28d1f895c6fe	946	__HAL_UNLOCK(hspi);
mbed_official	340:28d1f895c6fe	947
mbed_official	340:28d1f895c6fe	948	return HAL_ERROR;
mbed_official	340:28d1f895c6fe	949	}
mbed_official	340:28d1f895c6fe	950
mbed_official	340:28d1f895c6fe	951	/* Process Unlocked */
mbed_official	340:28d1f895c6fe	952	__HAL_UNLOCK(hspi);
mbed_official	340:28d1f895c6fe	953
mbed_official	340:28d1f895c6fe	954	if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
mbed_official	340:28d1f895c6fe	955	{
mbed_official	340:28d1f895c6fe	956	return HAL_ERROR;
mbed_official	340:28d1f895c6fe	957	}
mbed_official	340:28d1f895c6fe	958	else
mbed_official	340:28d1f895c6fe	959	{
mbed_official	340:28d1f895c6fe	960	return HAL_OK;
mbed_official	340:28d1f895c6fe	961	}
mbed_official	340:28d1f895c6fe	962	}
mbed_official	340:28d1f895c6fe	963
mbed_official	340:28d1f895c6fe	964	/**
mbed_official	340:28d1f895c6fe	965	* @brief Transmit an amount of data in no-blocking mode with Interrupt
mbed_official	340:28d1f895c6fe	966	* @param hspi: SPI handle
mbed_official	340:28d1f895c6fe	967	* @param pData: pointer to data buffer
mbed_official	340:28d1f895c6fe	968	* @param Size: amount of data to be sent
mbed_official	340:28d1f895c6fe	969	* @retval HAL status
mbed_official	340:28d1f895c6fe	970	*/
mbed_official	340:28d1f895c6fe	971	HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
mbed_official	340:28d1f895c6fe	972	{
mbed_official	340:28d1f895c6fe	973	assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
mbed_official	340:28d1f895c6fe	974
mbed_official	340:28d1f895c6fe	975	if(hspi->State == HAL_SPI_STATE_READY)
mbed_official	340:28d1f895c6fe	976	{
mbed_official	340:28d1f895c6fe	977	if((pData == HAL_NULL) \|\| (Size == 0))
mbed_official	340:28d1f895c6fe	978	{
mbed_official	340:28d1f895c6fe	979	return HAL_ERROR;
mbed_official	340:28d1f895c6fe	980	}
mbed_official	340:28d1f895c6fe	981
mbed_official	340:28d1f895c6fe	982	/* Process Locked */
mbed_official	340:28d1f895c6fe	983	__HAL_LOCK(hspi);
mbed_official	340:28d1f895c6fe	984
mbed_official	340:28d1f895c6fe	985	hspi->State = HAL_SPI_STATE_BUSY_TX;
mbed_official	340:28d1f895c6fe	986	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official	340:28d1f895c6fe	987	hspi->pTxBuffPtr = pData;
mbed_official	340:28d1f895c6fe	988	hspi->TxXferSize = Size;
mbed_official	340:28d1f895c6fe	989	hspi->TxXferCount = Size;
mbed_official	340:28d1f895c6fe	990	hspi->pRxBuffPtr = HAL_NULL;
mbed_official	340:28d1f895c6fe	991	hspi->RxXferSize = 0;
mbed_official	340:28d1f895c6fe	992	hspi->RxXferCount = 0;
mbed_official	340:28d1f895c6fe	993
mbed_official	340:28d1f895c6fe	994	/* Set the function for IT treatement */
mbed_official	340:28d1f895c6fe	995	if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
mbed_official	340:28d1f895c6fe	996	{
mbed_official	340:28d1f895c6fe	997	hspi->RxISR = HAL_NULL;
mbed_official	340:28d1f895c6fe	998	hspi->TxISR = SPI_TxISR_16BIT;
mbed_official	340:28d1f895c6fe	999	}
mbed_official	340:28d1f895c6fe	1000	else
mbed_official	340:28d1f895c6fe	1001	{
mbed_official	340:28d1f895c6fe	1002	hspi->RxISR = HAL_NULL;
mbed_official	340:28d1f895c6fe	1003	hspi->TxISR = SPI_TxISR_8BIT;
mbed_official	340:28d1f895c6fe	1004	}
mbed_official	340:28d1f895c6fe	1005
mbed_official	340:28d1f895c6fe	1006	/* Configure communication direction : 1Line */
mbed_official	340:28d1f895c6fe	1007	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
mbed_official	340:28d1f895c6fe	1008	{
mbed_official	340:28d1f895c6fe	1009	__HAL_SPI_1LINE_TX(hspi);
mbed_official	340:28d1f895c6fe	1010	}
mbed_official	340:28d1f895c6fe	1011
mbed_official	340:28d1f895c6fe	1012	/* Reset CRC Calculation */
mbed_official	340:28d1f895c6fe	1013	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	340:28d1f895c6fe	1014	{
mbed_official	340:28d1f895c6fe	1015	__HAL_SPI_RESET_CRC(hspi);
mbed_official	340:28d1f895c6fe	1016	}
mbed_official	340:28d1f895c6fe	1017
mbed_official	340:28d1f895c6fe	1018	/* Enable TXE and ERR interrupt */
mbed_official	340:28d1f895c6fe	1019	__HAL_SPI_ENABLE_IT(hspi,(SPI_IT_TXE));
mbed_official	340:28d1f895c6fe	1020
mbed_official	340:28d1f895c6fe	1021	/* Process Unlocked */
mbed_official	340:28d1f895c6fe	1022	__HAL_UNLOCK(hspi);
mbed_official	340:28d1f895c6fe	1023
mbed_official	340:28d1f895c6fe	1024	/* Note : The SPI must be enabled after unlocking current process
mbed_official	340:28d1f895c6fe	1025	to avoid the risk of SPI interrupt handle execution before current
mbed_official	340:28d1f895c6fe	1026	process unlock */
mbed_official	340:28d1f895c6fe	1027
mbed_official	340:28d1f895c6fe	1028	/* Check if the SPI is already enabled */
mbed_official	340:28d1f895c6fe	1029	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official	340:28d1f895c6fe	1030	{
mbed_official	340:28d1f895c6fe	1031	/* Enable SPI peripheral */
mbed_official	340:28d1f895c6fe	1032	__HAL_SPI_ENABLE(hspi);
mbed_official	340:28d1f895c6fe	1033	}
mbed_official	340:28d1f895c6fe	1034
mbed_official	340:28d1f895c6fe	1035	return HAL_OK;
mbed_official	340:28d1f895c6fe	1036	}
mbed_official	340:28d1f895c6fe	1037	else
mbed_official	340:28d1f895c6fe	1038	{
mbed_official	340:28d1f895c6fe	1039	return HAL_BUSY;
mbed_official	340:28d1f895c6fe	1040	}
mbed_official	340:28d1f895c6fe	1041	}
mbed_official	340:28d1f895c6fe	1042
mbed_official	340:28d1f895c6fe	1043	/**
mbed_official	340:28d1f895c6fe	1044	* @brief Receive an amount of data in no-blocking mode with Interrupt
mbed_official	340:28d1f895c6fe	1045	* @param hspi: SPI handle
mbed_official	340:28d1f895c6fe	1046	* @param pData: pointer to data buffer
mbed_official	340:28d1f895c6fe	1047	* @param Size: amount of data to be sent
mbed_official	340:28d1f895c6fe	1048	* @retval HAL status
mbed_official	340:28d1f895c6fe	1049	*/
mbed_official	340:28d1f895c6fe	1050	HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
mbed_official	340:28d1f895c6fe	1051	{
mbed_official	340:28d1f895c6fe	1052	if(hspi->State == HAL_SPI_STATE_READY)
mbed_official	340:28d1f895c6fe	1053	{
mbed_official	340:28d1f895c6fe	1054	if((pData == HAL_NULL) \|\| (Size == 0))
mbed_official	340:28d1f895c6fe	1055	{
mbed_official	340:28d1f895c6fe	1056	return HAL_ERROR;
mbed_official	340:28d1f895c6fe	1057	}
mbed_official	340:28d1f895c6fe	1058
mbed_official	340:28d1f895c6fe	1059	/* Process Locked */
mbed_official	340:28d1f895c6fe	1060	__HAL_LOCK(hspi);
mbed_official	340:28d1f895c6fe	1061
mbed_official	340:28d1f895c6fe	1062	/* Configure communication */
mbed_official	340:28d1f895c6fe	1063	hspi->State = HAL_SPI_STATE_BUSY_RX;
mbed_official	340:28d1f895c6fe	1064	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official	340:28d1f895c6fe	1065	hspi->pRxBuffPtr = pData;
mbed_official	340:28d1f895c6fe	1066	hspi->RxXferSize = Size;
mbed_official	340:28d1f895c6fe	1067	hspi->RxXferCount = Size;
mbed_official	340:28d1f895c6fe	1068	hspi->pTxBuffPtr = HAL_NULL;
mbed_official	340:28d1f895c6fe	1069	hspi->TxXferSize = 0;
mbed_official	340:28d1f895c6fe	1070	hspi->TxXferCount = 0;
mbed_official	340:28d1f895c6fe	1071
mbed_official	340:28d1f895c6fe	1072	if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
mbed_official	340:28d1f895c6fe	1073	{
mbed_official	340:28d1f895c6fe	1074	/* Process Unlocked */
mbed_official	340:28d1f895c6fe	1075	__HAL_UNLOCK(hspi);
mbed_official	340:28d1f895c6fe	1076	/* the receive process is not supported in 2Lines direction master mode */
mbed_official	340:28d1f895c6fe	1077	/* in this we call the transmitReceive process */
mbed_official	340:28d1f895c6fe	1078	return HAL_SPI_TransmitReceive_IT(hspi,pData,pData,Size);
mbed_official	340:28d1f895c6fe	1079	}
mbed_official	340:28d1f895c6fe	1080
mbed_official	340:28d1f895c6fe	1081	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	340:28d1f895c6fe	1082	{
mbed_official	340:28d1f895c6fe	1083	hspi->CRCSize = 1;
mbed_official	340:28d1f895c6fe	1084	if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
mbed_official	340:28d1f895c6fe	1085	{
mbed_official	340:28d1f895c6fe	1086	hspi->CRCSize = 2;
mbed_official	340:28d1f895c6fe	1087	}
mbed_official	340:28d1f895c6fe	1088	}
mbed_official	340:28d1f895c6fe	1089	else
mbed_official	340:28d1f895c6fe	1090	{
mbed_official	340:28d1f895c6fe	1091	hspi->CRCSize = 0;
mbed_official	340:28d1f895c6fe	1092	}
mbed_official	340:28d1f895c6fe	1093
mbed_official	340:28d1f895c6fe	1094	/* check the data size to adapt Rx threshold and the set the function for IT treatement */
mbed_official	340:28d1f895c6fe	1095	if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
mbed_official	340:28d1f895c6fe	1096	{
mbed_official	340:28d1f895c6fe	1097	/* set fiforxthresold according the reception data lenght: 16 bit */
mbed_official	340:28d1f895c6fe	1098	CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
mbed_official	340:28d1f895c6fe	1099	hspi->RxISR = SPI_RxISR_16BIT;
mbed_official	340:28d1f895c6fe	1100	hspi->TxISR = HAL_NULL;
mbed_official	340:28d1f895c6fe	1101	}
mbed_official	340:28d1f895c6fe	1102	else
mbed_official	340:28d1f895c6fe	1103	{
mbed_official	340:28d1f895c6fe	1104	/* set fiforxthresold according the reception data lenght: 8 bit */
mbed_official	340:28d1f895c6fe	1105	SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
mbed_official	340:28d1f895c6fe	1106	hspi->RxISR = SPI_RxISR_8BIT;
mbed_official	340:28d1f895c6fe	1107	hspi->TxISR = HAL_NULL;
mbed_official	340:28d1f895c6fe	1108	}
mbed_official	340:28d1f895c6fe	1109
mbed_official	340:28d1f895c6fe	1110	/* Configure communication direction : 1Line */
mbed_official	340:28d1f895c6fe	1111	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
mbed_official	340:28d1f895c6fe	1112	{
mbed_official	340:28d1f895c6fe	1113	__HAL_SPI_1LINE_RX(hspi);
mbed_official	340:28d1f895c6fe	1114	}
mbed_official	340:28d1f895c6fe	1115
mbed_official	340:28d1f895c6fe	1116	/* Reset CRC Calculation */
mbed_official	340:28d1f895c6fe	1117	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	340:28d1f895c6fe	1118	{
mbed_official	340:28d1f895c6fe	1119	__HAL_SPI_RESET_CRC(hspi);
mbed_official	340:28d1f895c6fe	1120	}
mbed_official	340:28d1f895c6fe	1121
mbed_official	340:28d1f895c6fe	1122	/* Enable TXE and ERR interrupt */
mbed_official	340:28d1f895c6fe	1123	__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE \| SPI_IT_ERR));
mbed_official	340:28d1f895c6fe	1124
mbed_official	340:28d1f895c6fe	1125	/* Process Unlocked */
mbed_official	340:28d1f895c6fe	1126	__HAL_UNLOCK(hspi);
mbed_official	340:28d1f895c6fe	1127
mbed_official	340:28d1f895c6fe	1128	/* Note : The SPI must be enabled after unlocking current process
mbed_official	340:28d1f895c6fe	1129	to avoid the risk of SPI interrupt handle execution before current
mbed_official	340:28d1f895c6fe	1130	process unlock */
mbed_official	340:28d1f895c6fe	1131
mbed_official	340:28d1f895c6fe	1132	/* Check if the SPI is already enabled */
mbed_official	340:28d1f895c6fe	1133	if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official	340:28d1f895c6fe	1134	{
mbed_official	340:28d1f895c6fe	1135	/* Enable SPI peripheral */
mbed_official	340:28d1f895c6fe	1136	__HAL_SPI_ENABLE(hspi);
mbed_official	340:28d1f895c6fe	1137	}
mbed_official	340:28d1f895c6fe	1138
mbed_official	340:28d1f895c6fe	1139	return HAL_OK;
mbed_official	340:28d1f895c6fe	1140	}
mbed_official	340:28d1f895c6fe	1141	else
mbed_official	340:28d1f895c6fe	1142	{
mbed_official	340:28d1f895c6fe	1143	return HAL_BUSY;
mbed_official	340:28d1f895c6fe	1144	}
mbed_official	340:28d1f895c6fe	1145	}
mbed_official	340:28d1f895c6fe	1146
mbed_official	340:28d1f895c6fe	1147	/**
mbed_official	340:28d1f895c6fe	1148	* @brief Transmit and Receive an amount of data in no-blocking mode with Interrupt
mbed_official	340:28d1f895c6fe	1149	* @param hspi: SPI handle
mbed_official	340:28d1f895c6fe	1150	* @param pTxData: pointer to transmission data buffer
mbed_official	340:28d1f895c6fe	1151	* @param pRxData: pointer to reception data buffer to be
mbed_official	340:28d1f895c6fe	1152	* @param Size: amount of data to be sent
mbed_official	340:28d1f895c6fe	1153	* @retval HAL status
mbed_official	340:28d1f895c6fe	1154	*/
mbed_official	340:28d1f895c6fe	1155	HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef hspi, uint8_t pTxData, uint8_t *pRxData, uint16_t Size)
mbed_official	340:28d1f895c6fe	1156	{
mbed_official	340:28d1f895c6fe	1157	assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
mbed_official	340:28d1f895c6fe	1158
mbed_official	340:28d1f895c6fe	1159	if((hspi->State == HAL_SPI_STATE_READY) \|\| \
mbed_official	340:28d1f895c6fe	1160	((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX)))
mbed_official	340:28d1f895c6fe	1161	{
mbed_official	340:28d1f895c6fe	1162	if((pTxData == HAL_NULL ) \|\| (pRxData == HAL_NULL ) \|\| (Size == 0))
mbed_official	340:28d1f895c6fe	1163	{
mbed_official	340:28d1f895c6fe	1164	return HAL_ERROR;
mbed_official	340:28d1f895c6fe	1165	}
mbed_official	340:28d1f895c6fe	1166
mbed_official	340:28d1f895c6fe	1167	/* Process locked */
mbed_official	340:28d1f895c6fe	1168	__HAL_LOCK(hspi);
mbed_official	340:28d1f895c6fe	1169
mbed_official	340:28d1f895c6fe	1170	hspi->CRCSize = 0;
mbed_official	340:28d1f895c6fe	1171	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	340:28d1f895c6fe	1172	{
mbed_official	340:28d1f895c6fe	1173	hspi->CRCSize = 1;
mbed_official	340:28d1f895c6fe	1174	if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT))
mbed_official	340:28d1f895c6fe	1175	{
mbed_official	340:28d1f895c6fe	1176	hspi->CRCSize = 2;
mbed_official	340:28d1f895c6fe	1177	}
mbed_official	340:28d1f895c6fe	1178	}
mbed_official	340:28d1f895c6fe	1179
mbed_official	340:28d1f895c6fe	1180	if(hspi->State != HAL_SPI_STATE_BUSY_RX)
mbed_official	340:28d1f895c6fe	1181	{
mbed_official	340:28d1f895c6fe	1182	hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
mbed_official	340:28d1f895c6fe	1183	}
mbed_official	340:28d1f895c6fe	1184
mbed_official	340:28d1f895c6fe	1185	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official	340:28d1f895c6fe	1186	hspi->pTxBuffPtr = pTxData;
mbed_official	340:28d1f895c6fe	1187	hspi->TxXferSize = Size;
mbed_official	340:28d1f895c6fe	1188	hspi->TxXferCount = Size;
mbed_official	340:28d1f895c6fe	1189	hspi->pRxBuffPtr = pRxData;
mbed_official	340:28d1f895c6fe	1190	hspi->RxXferSize = Size;
mbed_official	340:28d1f895c6fe	1191	hspi->RxXferCount = Size;
mbed_official	340:28d1f895c6fe	1192
mbed_official	340:28d1f895c6fe	1193	/* Set the function for IT treatement */
mbed_official	340:28d1f895c6fe	1194	if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
mbed_official	340:28d1f895c6fe	1195	{
mbed_official	340:28d1f895c6fe	1196	hspi->RxISR = SPI_2linesRxISR_16BIT;
mbed_official	340:28d1f895c6fe	1197	hspi->TxISR = SPI_2linesTxISR_16BIT;
mbed_official	340:28d1f895c6fe	1198	}
mbed_official	340:28d1f895c6fe	1199	else
mbed_official	340:28d1f895c6fe	1200	{
mbed_official	340:28d1f895c6fe	1201	hspi->RxISR = SPI_2linesRxISR_8BIT;
mbed_official	340:28d1f895c6fe	1202	hspi->TxISR = SPI_2linesTxISR_8BIT;
mbed_official	340:28d1f895c6fe	1203	}
mbed_official	340:28d1f895c6fe	1204
mbed_official	340:28d1f895c6fe	1205	/* Reset CRC Calculation */
mbed_official	340:28d1f895c6fe	1206	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	340:28d1f895c6fe	1207	{
mbed_official	340:28d1f895c6fe	1208	__HAL_SPI_RESET_CRC(hspi);
mbed_official	340:28d1f895c6fe	1209	}
mbed_official	340:28d1f895c6fe	1210
mbed_official	340:28d1f895c6fe	1211	/* check if packing mode is enabled and if there is more than 2 data to receive */
mbed_official	340:28d1f895c6fe	1212	if((hspi->Init.DataSize > SPI_DATASIZE_8BIT) \|\| (hspi->RxXferCount >= 2))
mbed_official	340:28d1f895c6fe	1213	{
mbed_official	340:28d1f895c6fe	1214	/* set fiforxthresold according the reception data lenght: 16 bit */
mbed_official	340:28d1f895c6fe	1215	CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
mbed_official	340:28d1f895c6fe	1216	}
mbed_official	340:28d1f895c6fe	1217	else
mbed_official	340:28d1f895c6fe	1218	{
mbed_official	340:28d1f895c6fe	1219	/* set fiforxthresold according the reception data lenght: 8 bit */
mbed_official	340:28d1f895c6fe	1220	SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
mbed_official	340:28d1f895c6fe	1221	}
mbed_official	340:28d1f895c6fe	1222
mbed_official	340:28d1f895c6fe	1223	/* Enable TXE, RXNE and ERR interrupt */
mbed_official	340:28d1f895c6fe	1224	__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_RXNE \| SPI_IT_ERR));
mbed_official	340:28d1f895c6fe	1225
mbed_official	340:28d1f895c6fe	1226	/* Process Unlocked */
mbed_official	340:28d1f895c6fe	1227	__HAL_UNLOCK(hspi);
mbed_official	340:28d1f895c6fe	1228
mbed_official	340:28d1f895c6fe	1229	/* Check if the SPI is already enabled */
mbed_official	340:28d1f895c6fe	1230	if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official	340:28d1f895c6fe	1231	{
mbed_official	340:28d1f895c6fe	1232	/* Enable SPI peripheral */
mbed_official	340:28d1f895c6fe	1233	__HAL_SPI_ENABLE(hspi);
mbed_official	340:28d1f895c6fe	1234	}
mbed_official	340:28d1f895c6fe	1235
mbed_official	340:28d1f895c6fe	1236	return HAL_OK;
mbed_official	340:28d1f895c6fe	1237	}
mbed_official	340:28d1f895c6fe	1238	else
mbed_official	340:28d1f895c6fe	1239	{
mbed_official	340:28d1f895c6fe	1240	return HAL_BUSY;
mbed_official	340:28d1f895c6fe	1241	}
mbed_official	340:28d1f895c6fe	1242	}
mbed_official	340:28d1f895c6fe	1243
mbed_official	340:28d1f895c6fe	1244	/**
mbed_official	340:28d1f895c6fe	1245	* @brief Transmit an amount of data in no-blocking mode with DMA
mbed_official	340:28d1f895c6fe	1246	* @param hspi: SPI handle
mbed_official	340:28d1f895c6fe	1247	* @param pData: pointer to data buffer
mbed_official	340:28d1f895c6fe	1248	* @param Size: amount of data to be sent
mbed_official	340:28d1f895c6fe	1249	* @retval HAL status
mbed_official	340:28d1f895c6fe	1250	*/
mbed_official	340:28d1f895c6fe	1251	HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
mbed_official	340:28d1f895c6fe	1252	{
mbed_official	340:28d1f895c6fe	1253	assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
mbed_official	340:28d1f895c6fe	1254
mbed_official	340:28d1f895c6fe	1255	if(hspi->State != HAL_SPI_STATE_READY)
mbed_official	340:28d1f895c6fe	1256	{
mbed_official	340:28d1f895c6fe	1257	return HAL_BUSY;
mbed_official	340:28d1f895c6fe	1258	}
mbed_official	340:28d1f895c6fe	1259
mbed_official	340:28d1f895c6fe	1260	if((pData == HAL_NULL) \|\| (Size == 0))
mbed_official	340:28d1f895c6fe	1261	{
mbed_official	340:28d1f895c6fe	1262	return HAL_ERROR;
mbed_official	340:28d1f895c6fe	1263	}
mbed_official	340:28d1f895c6fe	1264
mbed_official	340:28d1f895c6fe	1265	/* Process Locked */
mbed_official	340:28d1f895c6fe	1266	__HAL_LOCK(hspi);
mbed_official	340:28d1f895c6fe	1267
mbed_official	340:28d1f895c6fe	1268	hspi->State = HAL_SPI_STATE_BUSY_TX;
mbed_official	340:28d1f895c6fe	1269	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official	340:28d1f895c6fe	1270	hspi->pTxBuffPtr = pData;
mbed_official	340:28d1f895c6fe	1271	hspi->TxXferSize = Size;
mbed_official	340:28d1f895c6fe	1272	hspi->TxXferCount = Size;
mbed_official	340:28d1f895c6fe	1273	hspi->pRxBuffPtr = HAL_NULL;
mbed_official	340:28d1f895c6fe	1274	hspi->RxXferSize = 0;
mbed_official	340:28d1f895c6fe	1275	hspi->RxXferCount = 0;
mbed_official	340:28d1f895c6fe	1276
mbed_official	340:28d1f895c6fe	1277	/* Configure communication direction : 1Line */
mbed_official	340:28d1f895c6fe	1278	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
mbed_official	340:28d1f895c6fe	1279	{
mbed_official	340:28d1f895c6fe	1280	__HAL_SPI_1LINE_TX(hspi);
mbed_official	340:28d1f895c6fe	1281	}
mbed_official	340:28d1f895c6fe	1282
mbed_official	340:28d1f895c6fe	1283	/* Reset CRC Calculation */
mbed_official	340:28d1f895c6fe	1284	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	340:28d1f895c6fe	1285	{
mbed_official	340:28d1f895c6fe	1286	__HAL_SPI_RESET_CRC(hspi);
mbed_official	340:28d1f895c6fe	1287	}
mbed_official	340:28d1f895c6fe	1288
mbed_official	340:28d1f895c6fe	1289	/* Set the SPI TxDMA transfer complete callback */
mbed_official	340:28d1f895c6fe	1290	hspi->hdmatx->XferCpltCallback = HAL_SPI_DMATransmitCplt;
mbed_official	340:28d1f895c6fe	1291
mbed_official	340:28d1f895c6fe	1292	/* Set the DMA error callback */
mbed_official	340:28d1f895c6fe	1293	hspi->hdmatx->XferErrorCallback = HAL_SPI_DMAError;
mbed_official	340:28d1f895c6fe	1294
mbed_official	340:28d1f895c6fe	1295	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
mbed_official	340:28d1f895c6fe	1296	/* packing mode is enabled only if the DMA setting is HALWORD */
mbed_official	340:28d1f895c6fe	1297	if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))
mbed_official	340:28d1f895c6fe	1298	{
mbed_official	340:28d1f895c6fe	1299	/* Check the even/odd of the data size + crc if enabled */
mbed_official	340:28d1f895c6fe	1300	if((hspi->TxXferCount & 0x1) == 0)
mbed_official	340:28d1f895c6fe	1301	{
mbed_official	340:28d1f895c6fe	1302	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
mbed_official	340:28d1f895c6fe	1303	hspi->TxXferCount = (hspi->TxXferCount >> 1);
mbed_official	340:28d1f895c6fe	1304	}
mbed_official	340:28d1f895c6fe	1305	else
mbed_official	340:28d1f895c6fe	1306	{
mbed_official	340:28d1f895c6fe	1307	SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
mbed_official	340:28d1f895c6fe	1308	hspi->TxXferCount = (hspi->TxXferCount >> 1) + 1;
mbed_official	340:28d1f895c6fe	1309	}
mbed_official	340:28d1f895c6fe	1310	}
mbed_official	340:28d1f895c6fe	1311
mbed_official	340:28d1f895c6fe	1312	/* Enable the Tx DMA channel */
mbed_official	340:28d1f895c6fe	1313	HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
mbed_official	340:28d1f895c6fe	1314
mbed_official	340:28d1f895c6fe	1315	/* Check if the SPI is already enabled */
mbed_official	340:28d1f895c6fe	1316	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official	340:28d1f895c6fe	1317	{
mbed_official	340:28d1f895c6fe	1318	/* Enable SPI peripheral */
mbed_official	340:28d1f895c6fe	1319	__HAL_SPI_ENABLE(hspi);
mbed_official	340:28d1f895c6fe	1320	}
mbed_official	340:28d1f895c6fe	1321
mbed_official	340:28d1f895c6fe	1322	/* Enable Tx DMA Request */
mbed_official	340:28d1f895c6fe	1323	hspi->Instance->CR2 \|= SPI_CR2_TXDMAEN;
mbed_official	340:28d1f895c6fe	1324
mbed_official	340:28d1f895c6fe	1325	/* Process Unlocked */
mbed_official	340:28d1f895c6fe	1326	__HAL_UNLOCK(hspi);
mbed_official	340:28d1f895c6fe	1327
mbed_official	340:28d1f895c6fe	1328	return HAL_OK;
mbed_official	340:28d1f895c6fe	1329	}
mbed_official	340:28d1f895c6fe	1330
mbed_official	340:28d1f895c6fe	1331	/**
mbed_official	340:28d1f895c6fe	1332	* @brief Receive an amount of data in no-blocking mode with DMA
mbed_official	340:28d1f895c6fe	1333	* @param hspi: SPI handle
mbed_official	340:28d1f895c6fe	1334	* @param pData: pointer to data buffer
mbed_official	340:28d1f895c6fe	1335	* @param Size: amount of data to be sent
mbed_official	340:28d1f895c6fe	1336	* @retval HAL status
mbed_official	340:28d1f895c6fe	1337	*/
mbed_official	340:28d1f895c6fe	1338	HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef hspi, uint8_t pData, uint16_t Size)
mbed_official	340:28d1f895c6fe	1339	{
mbed_official	340:28d1f895c6fe	1340	if(hspi->State != HAL_SPI_STATE_READY)
mbed_official	340:28d1f895c6fe	1341	{
mbed_official	340:28d1f895c6fe	1342	return HAL_BUSY;
mbed_official	340:28d1f895c6fe	1343	}
mbed_official	340:28d1f895c6fe	1344
mbed_official	340:28d1f895c6fe	1345	if((pData == HAL_NULL) \|\| (Size == 0))
mbed_official	340:28d1f895c6fe	1346	{
mbed_official	340:28d1f895c6fe	1347	return HAL_ERROR;
mbed_official	340:28d1f895c6fe	1348	}
mbed_official	340:28d1f895c6fe	1349
mbed_official	340:28d1f895c6fe	1350	/* Process Locked */
mbed_official	340:28d1f895c6fe	1351	__HAL_LOCK(hspi);
mbed_official	340:28d1f895c6fe	1352
mbed_official	340:28d1f895c6fe	1353	hspi->State = HAL_SPI_STATE_BUSY_RX;
mbed_official	340:28d1f895c6fe	1354	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official	340:28d1f895c6fe	1355	hspi->pRxBuffPtr = pData;
mbed_official	340:28d1f895c6fe	1356	hspi->RxXferSize = Size;
mbed_official	340:28d1f895c6fe	1357	hspi->RxXferCount = Size;
mbed_official	340:28d1f895c6fe	1358	hspi->pTxBuffPtr = HAL_NULL;
mbed_official	340:28d1f895c6fe	1359	hspi->TxXferSize = 0;
mbed_official	340:28d1f895c6fe	1360	hspi->TxXferCount = 0;
mbed_official	340:28d1f895c6fe	1361
mbed_official	340:28d1f895c6fe	1362	if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
mbed_official	340:28d1f895c6fe	1363	{
mbed_official	340:28d1f895c6fe	1364	/* Process Unlocked */
mbed_official	340:28d1f895c6fe	1365	__HAL_UNLOCK(hspi);
mbed_official	340:28d1f895c6fe	1366	/* the receive process is not supported in 2Lines direction master mode */
mbed_official	340:28d1f895c6fe	1367	/* in this case we call the transmitReceive process */
mbed_official	340:28d1f895c6fe	1368	return HAL_SPI_TransmitReceive_DMA(hspi,pData,pData,Size);
mbed_official	340:28d1f895c6fe	1369	}
mbed_official	340:28d1f895c6fe	1370
mbed_official	340:28d1f895c6fe	1371	/* Configure communication direction : 1Line */
mbed_official	340:28d1f895c6fe	1372	if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
mbed_official	340:28d1f895c6fe	1373	{
mbed_official	340:28d1f895c6fe	1374	__HAL_SPI_1LINE_RX(hspi);
mbed_official	340:28d1f895c6fe	1375	}
mbed_official	340:28d1f895c6fe	1376
mbed_official	340:28d1f895c6fe	1377	/* Reset CRC Calculation */
mbed_official	340:28d1f895c6fe	1378	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	340:28d1f895c6fe	1379	{
mbed_official	340:28d1f895c6fe	1380	__HAL_SPI_RESET_CRC(hspi);
mbed_official	340:28d1f895c6fe	1381	}
mbed_official	340:28d1f895c6fe	1382
mbed_official	340:28d1f895c6fe	1383	/* packing mode management is enabled by the DMA settings */
mbed_official	340:28d1f895c6fe	1384	if((hspi->Init.DataSize <= SPI_DATASIZE_8BIT) && (hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD))
mbed_official	340:28d1f895c6fe	1385	{
mbed_official	340:28d1f895c6fe	1386	/* Process Locked */
mbed_official	340:28d1f895c6fe	1387	__HAL_UNLOCK(hspi);
mbed_official	340:28d1f895c6fe	1388	/* Restriction the DMA data received is not allowed in this mode */
mbed_official	340:28d1f895c6fe	1389	return HAL_ERROR;
mbed_official	340:28d1f895c6fe	1390	}
mbed_official	340:28d1f895c6fe	1391
mbed_official	340:28d1f895c6fe	1392	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
mbed_official	340:28d1f895c6fe	1393	if( hspi->Init.DataSize > SPI_DATASIZE_8BIT)
mbed_official	340:28d1f895c6fe	1394	{
mbed_official	340:28d1f895c6fe	1395	/* set fiforxthresold according the reception data lenght: 16bit */
mbed_official	340:28d1f895c6fe	1396	CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
mbed_official	340:28d1f895c6fe	1397	}
mbed_official	340:28d1f895c6fe	1398	else
mbed_official	340:28d1f895c6fe	1399	{
mbed_official	340:28d1f895c6fe	1400	/* set fiforxthresold according the reception data lenght: 8bit */
mbed_official	340:28d1f895c6fe	1401	SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
mbed_official	340:28d1f895c6fe	1402	}
mbed_official	340:28d1f895c6fe	1403
mbed_official	340:28d1f895c6fe	1404	/* Set the SPI Rx DMA transfer complete callback */
mbed_official	340:28d1f895c6fe	1405	hspi->hdmarx->XferCpltCallback = HAL_SPI_DMAReceiveCplt;
mbed_official	340:28d1f895c6fe	1406
mbed_official	340:28d1f895c6fe	1407	/* Set the DMA error callback */
mbed_official	340:28d1f895c6fe	1408	hspi->hdmarx->XferErrorCallback = HAL_SPI_DMAError;
mbed_official	340:28d1f895c6fe	1409
mbed_official	340:28d1f895c6fe	1410	/* Enable Rx DMA Request */
mbed_official	340:28d1f895c6fe	1411	hspi->Instance->CR2 \|= SPI_CR2_RXDMAEN;
mbed_official	340:28d1f895c6fe	1412
mbed_official	340:28d1f895c6fe	1413	/* Enable the Rx DMA channel */
mbed_official	340:28d1f895c6fe	1414	HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
mbed_official	340:28d1f895c6fe	1415
mbed_official	340:28d1f895c6fe	1416	/* Process Unlocked */
mbed_official	340:28d1f895c6fe	1417	__HAL_UNLOCK(hspi);
mbed_official	340:28d1f895c6fe	1418
mbed_official	340:28d1f895c6fe	1419	/* Check if the SPI is already enabled */
mbed_official	340:28d1f895c6fe	1420	if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official	340:28d1f895c6fe	1421	{
mbed_official	340:28d1f895c6fe	1422	/* Enable SPI peripheral */
mbed_official	340:28d1f895c6fe	1423	__HAL_SPI_ENABLE(hspi);
mbed_official	340:28d1f895c6fe	1424	}
mbed_official	340:28d1f895c6fe	1425
mbed_official	340:28d1f895c6fe	1426	return HAL_OK;
mbed_official	340:28d1f895c6fe	1427	}
mbed_official	340:28d1f895c6fe	1428
mbed_official	340:28d1f895c6fe	1429	/**
mbed_official	340:28d1f895c6fe	1430	* @brief Transmit and Receive an amount of data in no-blocking mode with DMA
mbed_official	340:28d1f895c6fe	1431	* @param hspi: SPI handle
mbed_official	340:28d1f895c6fe	1432	* @param pTxData: pointer to transmission data buffer
mbed_official	340:28d1f895c6fe	1433	* @param pRxData: pointer to reception data buffer to be
mbed_official	340:28d1f895c6fe	1434	* @param Size: amount of data to be sent
mbed_official	340:28d1f895c6fe	1435	* @retval HAL status
mbed_official	340:28d1f895c6fe	1436	*/
mbed_official	340:28d1f895c6fe	1437	HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef hspi, uint8_t pTxData, uint8_t *pRxData, uint16_t Size)
mbed_official	340:28d1f895c6fe	1438	{
mbed_official	340:28d1f895c6fe	1439	assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
mbed_official	340:28d1f895c6fe	1440
mbed_official	340:28d1f895c6fe	1441	if((hspi->State == HAL_SPI_STATE_READY) \|\|
mbed_official	340:28d1f895c6fe	1442	((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX)))
mbed_official	340:28d1f895c6fe	1443	{
mbed_official	340:28d1f895c6fe	1444	if((pTxData == HAL_NULL ) \|\| (pRxData == HAL_NULL ) \|\| (Size == 0))
mbed_official	340:28d1f895c6fe	1445	{
mbed_official	340:28d1f895c6fe	1446	return HAL_ERROR;
mbed_official	340:28d1f895c6fe	1447	}
mbed_official	340:28d1f895c6fe	1448
mbed_official	340:28d1f895c6fe	1449	/* Process locked */
mbed_official	340:28d1f895c6fe	1450	__HAL_LOCK(hspi);
mbed_official	340:28d1f895c6fe	1451
mbed_official	340:28d1f895c6fe	1452	/* check if the transmit Receive function is not called by a receive master */
mbed_official	340:28d1f895c6fe	1453	if(hspi->State != HAL_SPI_STATE_BUSY_RX)
mbed_official	340:28d1f895c6fe	1454	{
mbed_official	340:28d1f895c6fe	1455	hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
mbed_official	340:28d1f895c6fe	1456	}
mbed_official	340:28d1f895c6fe	1457
mbed_official	340:28d1f895c6fe	1458	hspi->ErrorCode = HAL_SPI_ERROR_NONE;
mbed_official	340:28d1f895c6fe	1459	hspi->pTxBuffPtr = (uint8_t *)pTxData;
mbed_official	340:28d1f895c6fe	1460	hspi->TxXferSize = Size;
mbed_official	340:28d1f895c6fe	1461	hspi->TxXferCount = Size;
mbed_official	340:28d1f895c6fe	1462	hspi->pRxBuffPtr = (uint8_t *)pRxData;
mbed_official	340:28d1f895c6fe	1463	hspi->RxXferSize = Size;
mbed_official	340:28d1f895c6fe	1464	hspi->RxXferCount = Size;
mbed_official	340:28d1f895c6fe	1465
mbed_official	340:28d1f895c6fe	1466	/* Reset CRC Calculation + increase the rxsize */
mbed_official	340:28d1f895c6fe	1467	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	340:28d1f895c6fe	1468	{
mbed_official	340:28d1f895c6fe	1469	__HAL_SPI_RESET_CRC(hspi);
mbed_official	340:28d1f895c6fe	1470	}
mbed_official	340:28d1f895c6fe	1471
mbed_official	340:28d1f895c6fe	1472	/* Reset the threshold bit */
mbed_official	340:28d1f895c6fe	1473	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
mbed_official	340:28d1f895c6fe	1474	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
mbed_official	340:28d1f895c6fe	1475
mbed_official	340:28d1f895c6fe	1476	/* the packing mode management is enabled by the DMA settings according the spi data size */
mbed_official	340:28d1f895c6fe	1477	if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
mbed_official	340:28d1f895c6fe	1478	{
mbed_official	340:28d1f895c6fe	1479	/* set fiforxthreshold according the reception data lenght: 16bit */
mbed_official	340:28d1f895c6fe	1480	CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
mbed_official	340:28d1f895c6fe	1481	}
mbed_official	340:28d1f895c6fe	1482	else
mbed_official	340:28d1f895c6fe	1483	{
mbed_official	340:28d1f895c6fe	1484	/* set fiforxthresold according the reception data lenght: 8bit */
mbed_official	340:28d1f895c6fe	1485	SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
mbed_official	340:28d1f895c6fe	1486
mbed_official	340:28d1f895c6fe	1487	if(hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
mbed_official	340:28d1f895c6fe	1488	{
mbed_official	340:28d1f895c6fe	1489	if((hspi->TxXferSize & 0x1) == 0x0 )
mbed_official	340:28d1f895c6fe	1490	{
mbed_official	340:28d1f895c6fe	1491	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
mbed_official	340:28d1f895c6fe	1492	hspi->TxXferCount = hspi->TxXferCount >> 1;
mbed_official	340:28d1f895c6fe	1493	}
mbed_official	340:28d1f895c6fe	1494	else
mbed_official	340:28d1f895c6fe	1495	{
mbed_official	340:28d1f895c6fe	1496	SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMATX);
mbed_official	340:28d1f895c6fe	1497	hspi->TxXferCount = (hspi->TxXferCount >> 1) + 1;
mbed_official	340:28d1f895c6fe	1498	}
mbed_official	340:28d1f895c6fe	1499	}
mbed_official	340:28d1f895c6fe	1500
mbed_official	340:28d1f895c6fe	1501	if(hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD)
mbed_official	340:28d1f895c6fe	1502	{
mbed_official	340:28d1f895c6fe	1503	/* set fiforxthresold according the reception data lenght: 16bit */
mbed_official	340:28d1f895c6fe	1504	CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
mbed_official	340:28d1f895c6fe	1505
mbed_official	340:28d1f895c6fe	1506	/* Size must include the CRC lenght */
mbed_official	340:28d1f895c6fe	1507	if((hspi->RxXferCount & 0x1) == 0x0 )
mbed_official	340:28d1f895c6fe	1508	{
mbed_official	340:28d1f895c6fe	1509	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
mbed_official	340:28d1f895c6fe	1510	hspi->RxXferCount = hspi->RxXferCount >> 1;
mbed_official	340:28d1f895c6fe	1511	}
mbed_official	340:28d1f895c6fe	1512	else
mbed_official	340:28d1f895c6fe	1513	{
mbed_official	340:28d1f895c6fe	1514	SET_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX);
mbed_official	340:28d1f895c6fe	1515	hspi->RxXferCount = (hspi->RxXferCount >> 1) + 1;
mbed_official	340:28d1f895c6fe	1516	}
mbed_official	340:28d1f895c6fe	1517	}
mbed_official	340:28d1f895c6fe	1518	}
mbed_official	340:28d1f895c6fe	1519
mbed_official	340:28d1f895c6fe	1520	/* Set the SPI Rx DMA transfer complete callback because the last generated transfer request is
mbed_official	340:28d1f895c6fe	1521	the reception request (RXNE) */
mbed_official	340:28d1f895c6fe	1522	if(hspi->State == HAL_SPI_STATE_BUSY_RX)
mbed_official	340:28d1f895c6fe	1523	{
mbed_official	340:28d1f895c6fe	1524	hspi->hdmarx->XferCpltCallback = HAL_SPI_DMAReceiveCplt;
mbed_official	340:28d1f895c6fe	1525	}
mbed_official	340:28d1f895c6fe	1526	else
mbed_official	340:28d1f895c6fe	1527	{
mbed_official	340:28d1f895c6fe	1528	hspi->hdmarx->XferCpltCallback = HAL_SPI_DMATransmitReceiveCplt;
mbed_official	340:28d1f895c6fe	1529	}
mbed_official	340:28d1f895c6fe	1530	/* Set the DMA error callback */
mbed_official	340:28d1f895c6fe	1531	hspi->hdmarx->XferErrorCallback = HAL_SPI_DMAError;
mbed_official	340:28d1f895c6fe	1532
mbed_official	340:28d1f895c6fe	1533	/* Enable Rx DMA Request */
mbed_official	340:28d1f895c6fe	1534	hspi->Instance->CR2 \|= SPI_CR2_RXDMAEN;
mbed_official	340:28d1f895c6fe	1535
mbed_official	340:28d1f895c6fe	1536	/* Enable the Rx DMA channel */
mbed_official	340:28d1f895c6fe	1537	HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t) hspi->pRxBuffPtr, hspi->RxXferCount);
mbed_official	340:28d1f895c6fe	1538
mbed_official	340:28d1f895c6fe	1539	/* Set the SPI Tx DMA transfer complete callback as HAL_NULL because the communication closing
mbed_official	340:28d1f895c6fe	1540	is performed in DMA reception complete callback */
mbed_official	340:28d1f895c6fe	1541	hspi->hdmatx->XferCpltCallback = HAL_NULL;
mbed_official	340:28d1f895c6fe	1542
mbed_official	340:28d1f895c6fe	1543	/* Set the DMA error callback */
mbed_official	340:28d1f895c6fe	1544	hspi->hdmatx->XferErrorCallback = HAL_SPI_DMAError;
mbed_official	340:28d1f895c6fe	1545
mbed_official	340:28d1f895c6fe	1546	/* Enable the Tx DMA channel */
mbed_official	340:28d1f895c6fe	1547	HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
mbed_official	340:28d1f895c6fe	1548
mbed_official	340:28d1f895c6fe	1549	/* Check if the SPI is already enabled */
mbed_official	340:28d1f895c6fe	1550	if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
mbed_official	340:28d1f895c6fe	1551	{
mbed_official	340:28d1f895c6fe	1552	/* Enable SPI peripheral */
mbed_official	340:28d1f895c6fe	1553	__HAL_SPI_ENABLE(hspi);
mbed_official	340:28d1f895c6fe	1554	}
mbed_official	340:28d1f895c6fe	1555
mbed_official	340:28d1f895c6fe	1556	/* Enable Tx DMA Request */
mbed_official	340:28d1f895c6fe	1557	hspi->Instance->CR2 \|= SPI_CR2_TXDMAEN;
mbed_official	340:28d1f895c6fe	1558
mbed_official	340:28d1f895c6fe	1559	/* Process Unlocked */
mbed_official	340:28d1f895c6fe	1560	__HAL_UNLOCK(hspi);
mbed_official	340:28d1f895c6fe	1561
mbed_official	340:28d1f895c6fe	1562	return HAL_OK;
mbed_official	340:28d1f895c6fe	1563	}
mbed_official	340:28d1f895c6fe	1564	else
mbed_official	340:28d1f895c6fe	1565	{
mbed_official	340:28d1f895c6fe	1566	return HAL_BUSY;
mbed_official	340:28d1f895c6fe	1567	}
mbed_official	340:28d1f895c6fe	1568	}
mbed_official	340:28d1f895c6fe	1569
mbed_official	340:28d1f895c6fe	1570	/**
mbed_official	340:28d1f895c6fe	1571	* @brief This function handles SPI interrupt request.
mbed_official	340:28d1f895c6fe	1572	* @param hspi: SPI handle
mbed_official	340:28d1f895c6fe	1573	* @retval HAL status
mbed_official	340:28d1f895c6fe	1574	*/
mbed_official	340:28d1f895c6fe	1575	void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
mbed_official	340:28d1f895c6fe	1576	{
mbed_official	340:28d1f895c6fe	1577	/* SPI in mode Receiver ----------------------------------------------------*/
mbed_official	340:28d1f895c6fe	1578	if((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_OVR) == RESET) &&
mbed_official	340:28d1f895c6fe	1579	(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE) != RESET) && (__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_RXNE) != RESET))
mbed_official	340:28d1f895c6fe	1580	{
mbed_official	340:28d1f895c6fe	1581	hspi->RxISR(hspi);
mbed_official	340:28d1f895c6fe	1582	return;
mbed_official	340:28d1f895c6fe	1583	}
mbed_official	340:28d1f895c6fe	1584
mbed_official	340:28d1f895c6fe	1585	/* SPI in mode Tramitter ---------------------------------------------------*/
mbed_official	340:28d1f895c6fe	1586	if((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE) != RESET) && (__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_TXE) != RESET))
mbed_official	340:28d1f895c6fe	1587	{
mbed_official	340:28d1f895c6fe	1588	hspi->TxISR(hspi);
mbed_official	340:28d1f895c6fe	1589	return;
mbed_official	340:28d1f895c6fe	1590	}
mbed_official	340:28d1f895c6fe	1591
mbed_official	340:28d1f895c6fe	1592	/* SPI in Erreur Treatment ---------------------------------------------------*/
mbed_official	340:28d1f895c6fe	1593	if((hspi->Instance->SR & (SPI_FLAG_MODF \| SPI_FLAG_OVR \| SPI_FLAG_FRE)) != RESET)
mbed_official	340:28d1f895c6fe	1594	{
mbed_official	340:28d1f895c6fe	1595	/* SPI Overrun error interrupt occured -------------------------------------*/
mbed_official	340:28d1f895c6fe	1596	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_OVR) != RESET)
mbed_official	340:28d1f895c6fe	1597	{
mbed_official	340:28d1f895c6fe	1598	if(hspi->State != HAL_SPI_STATE_BUSY_TX)
mbed_official	340:28d1f895c6fe	1599	{
mbed_official	340:28d1f895c6fe	1600	hspi->ErrorCode \|= HAL_SPI_ERROR_OVR;
mbed_official	340:28d1f895c6fe	1601	__HAL_SPI_CLEAR_OVRFLAG(hspi);
mbed_official	340:28d1f895c6fe	1602	}
mbed_official	340:28d1f895c6fe	1603	else
mbed_official	340:28d1f895c6fe	1604	{
mbed_official	340:28d1f895c6fe	1605	return;
mbed_official	340:28d1f895c6fe	1606	}
mbed_official	340:28d1f895c6fe	1607	}
mbed_official	340:28d1f895c6fe	1608
mbed_official	340:28d1f895c6fe	1609	/* SPI Mode Fault error interrupt occured -------------------------------------*/
mbed_official	340:28d1f895c6fe	1610	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_MODF) != RESET)
mbed_official	340:28d1f895c6fe	1611	{
mbed_official	340:28d1f895c6fe	1612	hspi->ErrorCode \|= HAL_SPI_ERROR_MODF;
mbed_official	340:28d1f895c6fe	1613	__HAL_SPI_CLEAR_MODFFLAG(hspi);
mbed_official	340:28d1f895c6fe	1614	}
mbed_official	340:28d1f895c6fe	1615
mbed_official	340:28d1f895c6fe	1616	/* SPI Frame error interrupt occured ----------------------------------------*/
mbed_official	340:28d1f895c6fe	1617	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_FRE) != RESET)
mbed_official	340:28d1f895c6fe	1618	{
mbed_official	340:28d1f895c6fe	1619	hspi->ErrorCode \|= HAL_SPI_ERROR_FRE;
mbed_official	340:28d1f895c6fe	1620	__HAL_SPI_CLEAR_FREFLAG(hspi);
mbed_official	340:28d1f895c6fe	1621	}
mbed_official	340:28d1f895c6fe	1622
mbed_official	340:28d1f895c6fe	1623	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE \| SPI_IT_TXE \| SPI_IT_ERR);
mbed_official	340:28d1f895c6fe	1624	hspi->State = HAL_SPI_STATE_READY;
mbed_official	340:28d1f895c6fe	1625	HAL_SPI_ErrorCallback(hspi);
mbed_official	340:28d1f895c6fe	1626	return;
mbed_official	340:28d1f895c6fe	1627	}
mbed_official	340:28d1f895c6fe	1628	}
mbed_official	340:28d1f895c6fe	1629
mbed_official	340:28d1f895c6fe	1630	/**
mbed_official	340:28d1f895c6fe	1631	* @brief DMA SPI transmit process complete callback
mbed_official	340:28d1f895c6fe	1632	* @param hdma : DMA handle
mbed_official	340:28d1f895c6fe	1633	* @retval None
mbed_official	340:28d1f895c6fe	1634	*/
mbed_official	340:28d1f895c6fe	1635	static void HAL_SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
mbed_official	340:28d1f895c6fe	1636	{
mbed_official	340:28d1f895c6fe	1637	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official	340:28d1f895c6fe	1638
mbed_official	340:28d1f895c6fe	1639	/* Disable Tx DMA Request */
mbed_official	340:28d1f895c6fe	1640	hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
mbed_official	340:28d1f895c6fe	1641
mbed_official	340:28d1f895c6fe	1642	/* Check the end of the transaction */
mbed_official	340:28d1f895c6fe	1643	SPI_EndRxTxTransaction(hspi,SPI_DEFAULT_TIMEOUT);
mbed_official	340:28d1f895c6fe	1644
mbed_official	340:28d1f895c6fe	1645	/* Clear OVERUN flag in 2 Lines communication mode because received data is not read */
mbed_official	340:28d1f895c6fe	1646	if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
mbed_official	340:28d1f895c6fe	1647	{
mbed_official	340:28d1f895c6fe	1648	__HAL_SPI_CLEAR_OVRFLAG(hspi);
mbed_official	340:28d1f895c6fe	1649	}
mbed_official	340:28d1f895c6fe	1650
mbed_official	340:28d1f895c6fe	1651	hspi->TxXferCount = 0;
mbed_official	340:28d1f895c6fe	1652	hspi->State = HAL_SPI_STATE_READY;
mbed_official	340:28d1f895c6fe	1653
mbed_official	340:28d1f895c6fe	1654	/* Check if CRC error occurred or Error code */
mbed_official	340:28d1f895c6fe	1655	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
mbed_official	340:28d1f895c6fe	1656	{
mbed_official	340:28d1f895c6fe	1657	hspi->ErrorCode\|= HAL_SPI_ERROR_CRC;
mbed_official	340:28d1f895c6fe	1658	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
mbed_official	340:28d1f895c6fe	1659	HAL_SPI_ErrorCallback(hspi);
mbed_official	340:28d1f895c6fe	1660	}
mbed_official	340:28d1f895c6fe	1661	else
mbed_official	340:28d1f895c6fe	1662	{
mbed_official	340:28d1f895c6fe	1663	if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
mbed_official	340:28d1f895c6fe	1664	{
mbed_official	340:28d1f895c6fe	1665	HAL_SPI_TxCpltCallback(hspi);
mbed_official	340:28d1f895c6fe	1666	}
mbed_official	340:28d1f895c6fe	1667	else
mbed_official	340:28d1f895c6fe	1668	{
mbed_official	340:28d1f895c6fe	1669	HAL_SPI_ErrorCallback(hspi);
mbed_official	340:28d1f895c6fe	1670	}
mbed_official	340:28d1f895c6fe	1671	}
mbed_official	340:28d1f895c6fe	1672	}
mbed_official	340:28d1f895c6fe	1673
mbed_official	340:28d1f895c6fe	1674	/**
mbed_official	340:28d1f895c6fe	1675	* @brief DMA SPI receive process complete callback
mbed_official	340:28d1f895c6fe	1676	* @param hdma : DMA handle
mbed_official	340:28d1f895c6fe	1677	* @retval None
mbed_official	340:28d1f895c6fe	1678	*/
mbed_official	340:28d1f895c6fe	1679	static void HAL_SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
mbed_official	340:28d1f895c6fe	1680	{
mbed_official	340:28d1f895c6fe	1681	__IO uint16_t tmpreg;
mbed_official	340:28d1f895c6fe	1682	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official	340:28d1f895c6fe	1683
mbed_official	340:28d1f895c6fe	1684	/* CRC handling */
mbed_official	340:28d1f895c6fe	1685	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	340:28d1f895c6fe	1686	{
mbed_official	340:28d1f895c6fe	1687	/* Wait until TXE flag */
mbed_official	340:28d1f895c6fe	1688	if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT) != HAL_OK)
mbed_official	340:28d1f895c6fe	1689	{
mbed_official	340:28d1f895c6fe	1690	/* Erreur on the CRC reception */
mbed_official	340:28d1f895c6fe	1691	hspi->ErrorCode\|= HAL_SPI_ERROR_CRC;
mbed_official	340:28d1f895c6fe	1692	}
mbed_official	340:28d1f895c6fe	1693	if(hspi->Init.DataSize > SPI_DATASIZE_8BIT)
mbed_official	340:28d1f895c6fe	1694	{
mbed_official	340:28d1f895c6fe	1695	tmpreg = hspi->Instance->DR;
mbed_official	340:28d1f895c6fe	1696	}
mbed_official	340:28d1f895c6fe	1697	else
mbed_official	340:28d1f895c6fe	1698	{
mbed_official	340:28d1f895c6fe	1699	tmpreg = (__IO uint8_t )&hspi->Instance->DR;
mbed_official	340:28d1f895c6fe	1700	if(hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT)
mbed_official	340:28d1f895c6fe	1701	{
mbed_official	340:28d1f895c6fe	1702	if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT) != HAL_OK)
mbed_official	340:28d1f895c6fe	1703	{
mbed_official	340:28d1f895c6fe	1704	/* Erreur on the CRC reception */
mbed_official	340:28d1f895c6fe	1705	hspi->ErrorCode\|= HAL_SPI_ERROR_CRC;
mbed_official	340:28d1f895c6fe	1706	}
mbed_official	340:28d1f895c6fe	1707	tmpreg = (__IO uint8_t )&hspi->Instance->DR;
mbed_official	340:28d1f895c6fe	1708	}
mbed_official	340:28d1f895c6fe	1709	}
mbed_official	340:28d1f895c6fe	1710	}
mbed_official	340:28d1f895c6fe	1711
mbed_official	340:28d1f895c6fe	1712	/* Disable Rx DMA Request */
mbed_official	340:28d1f895c6fe	1713	hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
mbed_official	340:28d1f895c6fe	1714	/* Disable Tx DMA Request (done by default to handle the case master rx direction 2 lines) */
mbed_official	340:28d1f895c6fe	1715	hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
mbed_official	340:28d1f895c6fe	1716
mbed_official	340:28d1f895c6fe	1717	/* Check the end of the transaction */
mbed_official	340:28d1f895c6fe	1718	SPI_EndRxTransaction(hspi,SPI_DEFAULT_TIMEOUT);
mbed_official	340:28d1f895c6fe	1719
mbed_official	340:28d1f895c6fe	1720	hspi->RxXferCount = 0;
mbed_official	340:28d1f895c6fe	1721	hspi->State = HAL_SPI_STATE_READY;
mbed_official	340:28d1f895c6fe	1722
mbed_official	340:28d1f895c6fe	1723	/* Check if CRC error occurred */
mbed_official	340:28d1f895c6fe	1724	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
mbed_official	340:28d1f895c6fe	1725	{
mbed_official	340:28d1f895c6fe	1726	hspi->ErrorCode\|= HAL_SPI_ERROR_CRC;
mbed_official	340:28d1f895c6fe	1727	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
mbed_official	340:28d1f895c6fe	1728	HAL_SPI_RxCpltCallback(hspi);
mbed_official	340:28d1f895c6fe	1729	}
mbed_official	340:28d1f895c6fe	1730	else
mbed_official	340:28d1f895c6fe	1731	{
mbed_official	340:28d1f895c6fe	1732	if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
mbed_official	340:28d1f895c6fe	1733	{
mbed_official	340:28d1f895c6fe	1734	HAL_SPI_RxCpltCallback(hspi);
mbed_official	340:28d1f895c6fe	1735	}
mbed_official	340:28d1f895c6fe	1736	else
mbed_official	340:28d1f895c6fe	1737	{
mbed_official	340:28d1f895c6fe	1738	HAL_SPI_ErrorCallback(hspi);
mbed_official	340:28d1f895c6fe	1739	}
mbed_official	340:28d1f895c6fe	1740	}
mbed_official	340:28d1f895c6fe	1741	}
mbed_official	340:28d1f895c6fe	1742
mbed_official	340:28d1f895c6fe	1743	/**
mbed_official	340:28d1f895c6fe	1744	* @brief DMA SPI transmit receive process complete callback
mbed_official	340:28d1f895c6fe	1745	* @param hdma : DMA handle
mbed_official	340:28d1f895c6fe	1746	* @retval None
mbed_official	340:28d1f895c6fe	1747	*/
mbed_official	340:28d1f895c6fe	1748
mbed_official	340:28d1f895c6fe	1749	static void HAL_SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
mbed_official	340:28d1f895c6fe	1750	{
mbed_official	340:28d1f895c6fe	1751	__IO int16_t tmpreg;
mbed_official	340:28d1f895c6fe	1752	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official	340:28d1f895c6fe	1753
mbed_official	340:28d1f895c6fe	1754	/* CRC handling */
mbed_official	340:28d1f895c6fe	1755	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	340:28d1f895c6fe	1756	{
mbed_official	340:28d1f895c6fe	1757	if((hspi->Init.DataSize == SPI_DATASIZE_8BIT) && (hspi->Init.CRCLength == SPI_CRC_LENGTH_8BIT))
mbed_official	340:28d1f895c6fe	1758	{
mbed_official	340:28d1f895c6fe	1759	if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_QUARTER_FULL, SPI_DEFAULT_TIMEOUT) != HAL_OK)
mbed_official	340:28d1f895c6fe	1760	{
mbed_official	340:28d1f895c6fe	1761	/* Erreur on the CRC reception */
mbed_official	340:28d1f895c6fe	1762	hspi->ErrorCode\|= HAL_SPI_ERROR_CRC;
mbed_official	340:28d1f895c6fe	1763	}
mbed_official	340:28d1f895c6fe	1764	tmpreg = (__IO uint8_t )&hspi->Instance->DR;
mbed_official	340:28d1f895c6fe	1765	}
mbed_official	340:28d1f895c6fe	1766	else
mbed_official	340:28d1f895c6fe	1767	{
mbed_official	340:28d1f895c6fe	1768	if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_HALF_FULL, SPI_DEFAULT_TIMEOUT) != HAL_OK)
mbed_official	340:28d1f895c6fe	1769	{
mbed_official	340:28d1f895c6fe	1770	/* Erreur on the CRC reception */
mbed_official	340:28d1f895c6fe	1771	hspi->ErrorCode\|= HAL_SPI_ERROR_CRC;
mbed_official	340:28d1f895c6fe	1772	}
mbed_official	340:28d1f895c6fe	1773	tmpreg = hspi->Instance->DR;
mbed_official	340:28d1f895c6fe	1774	}
mbed_official	340:28d1f895c6fe	1775	}
mbed_official	340:28d1f895c6fe	1776
mbed_official	340:28d1f895c6fe	1777	/* Check the end of the transaction */
mbed_official	340:28d1f895c6fe	1778	SPI_EndRxTxTransaction(hspi,SPI_DEFAULT_TIMEOUT);
mbed_official	340:28d1f895c6fe	1779
mbed_official	340:28d1f895c6fe	1780	/* Disable Tx DMA Request */
mbed_official	340:28d1f895c6fe	1781	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
mbed_official	340:28d1f895c6fe	1782
mbed_official	340:28d1f895c6fe	1783	/* Disable Rx DMA Request */
mbed_official	340:28d1f895c6fe	1784	CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
mbed_official	340:28d1f895c6fe	1785
mbed_official	340:28d1f895c6fe	1786	hspi->TxXferCount = 0;
mbed_official	340:28d1f895c6fe	1787	hspi->RxXferCount = 0;
mbed_official	340:28d1f895c6fe	1788	hspi->State = HAL_SPI_STATE_READY;
mbed_official	340:28d1f895c6fe	1789
mbed_official	340:28d1f895c6fe	1790	/* Check if CRC error occurred */
mbed_official	340:28d1f895c6fe	1791	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
mbed_official	340:28d1f895c6fe	1792	{
mbed_official	340:28d1f895c6fe	1793	hspi->ErrorCode = HAL_SPI_ERROR_CRC;
mbed_official	340:28d1f895c6fe	1794	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
mbed_official	340:28d1f895c6fe	1795	HAL_SPI_ErrorCallback(hspi);
mbed_official	340:28d1f895c6fe	1796	}
mbed_official	340:28d1f895c6fe	1797	else
mbed_official	340:28d1f895c6fe	1798	{
mbed_official	340:28d1f895c6fe	1799	if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
mbed_official	340:28d1f895c6fe	1800	{
mbed_official	340:28d1f895c6fe	1801	HAL_SPI_TxRxCpltCallback(hspi);
mbed_official	340:28d1f895c6fe	1802	}
mbed_official	340:28d1f895c6fe	1803	else
mbed_official	340:28d1f895c6fe	1804	{
mbed_official	340:28d1f895c6fe	1805	HAL_SPI_ErrorCallback(hspi);
mbed_official	340:28d1f895c6fe	1806	}
mbed_official	340:28d1f895c6fe	1807	}
mbed_official	340:28d1f895c6fe	1808	}
mbed_official	340:28d1f895c6fe	1809
mbed_official	340:28d1f895c6fe	1810	/**
mbed_official	340:28d1f895c6fe	1811	* @brief DMA SPI communication error callback
mbed_official	340:28d1f895c6fe	1812	* @param hdma : DMA handle
mbed_official	340:28d1f895c6fe	1813	* @retval None
mbed_official	340:28d1f895c6fe	1814	*/
mbed_official	340:28d1f895c6fe	1815	static void HAL_SPI_DMAError(DMA_HandleTypeDef *hdma)
mbed_official	340:28d1f895c6fe	1816	{
mbed_official	340:28d1f895c6fe	1817	SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
mbed_official	340:28d1f895c6fe	1818	hspi->TxXferCount = 0;
mbed_official	340:28d1f895c6fe	1819	hspi->RxXferCount = 0;
mbed_official	340:28d1f895c6fe	1820	hspi->ErrorCode\|= HAL_SPI_ERROR_DMA;
mbed_official	340:28d1f895c6fe	1821	hspi->State = HAL_SPI_STATE_READY;
mbed_official	340:28d1f895c6fe	1822	HAL_SPI_ErrorCallback(hspi);
mbed_official	340:28d1f895c6fe	1823	}
mbed_official	340:28d1f895c6fe	1824
mbed_official	340:28d1f895c6fe	1825	/**
mbed_official	340:28d1f895c6fe	1826	* @brief Tx Transfer completed callbacks
mbed_official	340:28d1f895c6fe	1827	* @param hspi: SPI handle
mbed_official	340:28d1f895c6fe	1828	* @retval None
mbed_official	340:28d1f895c6fe	1829	*/
mbed_official	340:28d1f895c6fe	1830	__weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
mbed_official	340:28d1f895c6fe	1831	{
mbed_official	340:28d1f895c6fe	1832	/* NOTE : This function Should not be modified, when the callback is needed,
mbed_official	340:28d1f895c6fe	1833	the HAL_SPI_TxCpltCallback could be implenetd in the user file
mbed_official	340:28d1f895c6fe	1834	*/
mbed_official	340:28d1f895c6fe	1835	}
mbed_official	340:28d1f895c6fe	1836
mbed_official	340:28d1f895c6fe	1837	/**
mbed_official	340:28d1f895c6fe	1838	* @brief Rx Transfer completed callbacks
mbed_official	340:28d1f895c6fe	1839	* @param hspi: SPI handle
mbed_official	340:28d1f895c6fe	1840	* @retval None
mbed_official	340:28d1f895c6fe	1841	*/
mbed_official	340:28d1f895c6fe	1842	__weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
mbed_official	340:28d1f895c6fe	1843	{
mbed_official	340:28d1f895c6fe	1844	/* NOTE : This function Should not be modified, when the callback is needed,
mbed_official	340:28d1f895c6fe	1845	the HAL_SPI_RxCpltCallback could be implenetd in the user file
mbed_official	340:28d1f895c6fe	1846	*/
mbed_official	340:28d1f895c6fe	1847	}
mbed_official	340:28d1f895c6fe	1848
mbed_official	340:28d1f895c6fe	1849	/**
mbed_official	340:28d1f895c6fe	1850	* @brief Tx and Rx Transfer completed callbacks
mbed_official	340:28d1f895c6fe	1851	* @param hspi: SPI handle
mbed_official	340:28d1f895c6fe	1852	* @retval None
mbed_official	340:28d1f895c6fe	1853	*/
mbed_official	340:28d1f895c6fe	1854	__weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
mbed_official	340:28d1f895c6fe	1855	{
mbed_official	340:28d1f895c6fe	1856	/* NOTE : This function Should not be modified, when the callback is needed,
mbed_official	340:28d1f895c6fe	1857	the HAL_SPI_TxRxCpltCallback could be implenetd in the user file
mbed_official	340:28d1f895c6fe	1858	*/
mbed_official	340:28d1f895c6fe	1859	}
mbed_official	340:28d1f895c6fe	1860
mbed_official	340:28d1f895c6fe	1861	/**
mbed_official	340:28d1f895c6fe	1862	* @brief SPI error callbacks
mbed_official	340:28d1f895c6fe	1863	* @param hspi: SPI handle
mbed_official	340:28d1f895c6fe	1864	* @retval None
mbed_official	340:28d1f895c6fe	1865	*/
mbed_official	340:28d1f895c6fe	1866	__weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
mbed_official	340:28d1f895c6fe	1867	{
mbed_official	340:28d1f895c6fe	1868	/* NOTE : This function Should not be modified, when the callback is needed,
mbed_official	340:28d1f895c6fe	1869	the HAL_SPI_ErrorCallback could be implenetd in the user file
mbed_official	340:28d1f895c6fe	1870	*/
mbed_official	340:28d1f895c6fe	1871	}
mbed_official	340:28d1f895c6fe	1872
mbed_official	340:28d1f895c6fe	1873	/**
mbed_official	340:28d1f895c6fe	1874	* @}
mbed_official	340:28d1f895c6fe	1875	*/
mbed_official	340:28d1f895c6fe	1876
mbed_official	340:28d1f895c6fe	1877	/** @defgroup SPI_Exported_Functions_Group3 Peripheral Control functions
mbed_official	340:28d1f895c6fe	1878	* @brief SPI control functions
mbed_official	340:28d1f895c6fe	1879	*
mbed_official	340:28d1f895c6fe	1880	@verbatim
mbed_official	340:28d1f895c6fe	1881	===============================================================================
mbed_official	340:28d1f895c6fe	1882	##### Peripheral Control functions #####
mbed_official	340:28d1f895c6fe	1883	===============================================================================
mbed_official	340:28d1f895c6fe	1884	[..]
mbed_official	340:28d1f895c6fe	1885	This subsection provides a set of functions allowing to control the SPI.
mbed_official	340:28d1f895c6fe	1886	(+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral.
mbed_official	340:28d1f895c6fe	1887	(+) HAL_SPI_Ctl() API can be used to update the spi configuration (only one parameter)
mbed_official	340:28d1f895c6fe	1888	without calling the HAL_SPI_Init() API
mbed_official	340:28d1f895c6fe	1889	@endverbatim
mbed_official	340:28d1f895c6fe	1890	* @{
mbed_official	340:28d1f895c6fe	1891	*/
mbed_official	340:28d1f895c6fe	1892
mbed_official	340:28d1f895c6fe	1893	/**
mbed_official	340:28d1f895c6fe	1894	* @brief Return the SPI state
mbed_official	340:28d1f895c6fe	1895	* @param hspi : SPI handle
mbed_official	340:28d1f895c6fe	1896	* @retval HAL state
mbed_official	340:28d1f895c6fe	1897	*/
mbed_official	340:28d1f895c6fe	1898	HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
mbed_official	340:28d1f895c6fe	1899	{
mbed_official	340:28d1f895c6fe	1900	return hspi->State;
mbed_official	340:28d1f895c6fe	1901	}
mbed_official	340:28d1f895c6fe	1902	/**
mbed_official	340:28d1f895c6fe	1903	* @}
mbed_official	340:28d1f895c6fe	1904	*/
mbed_official	340:28d1f895c6fe	1905
mbed_official	340:28d1f895c6fe	1906	/**
mbed_official	340:28d1f895c6fe	1907	* @}
mbed_official	340:28d1f895c6fe	1908	*/
mbed_official	340:28d1f895c6fe	1909
mbed_official	340:28d1f895c6fe	1910	/** @addtogroup SPI_Private_Functions SPI Private Functions
mbed_official	340:28d1f895c6fe	1911	* @brief Data transfers Private functions
mbed_official	340:28d1f895c6fe	1912	* @{
mbed_official	340:28d1f895c6fe	1913	*/
mbed_official	340:28d1f895c6fe	1914
mbed_official	340:28d1f895c6fe	1915	/**
mbed_official	340:28d1f895c6fe	1916	* @brief Rx Handler for Transmit and Receive in Interrupt mode
mbed_official	340:28d1f895c6fe	1917	* @param hspi: SPI handle
mbed_official	340:28d1f895c6fe	1918	*/
mbed_official	340:28d1f895c6fe	1919	static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
mbed_official	340:28d1f895c6fe	1920	{
mbed_official	340:28d1f895c6fe	1921	/* Receive data in packing mode */
mbed_official	340:28d1f895c6fe	1922	if(hspi->RxXferCount > 1)
mbed_official	340:28d1f895c6fe	1923	{
mbed_official	340:28d1f895c6fe	1924	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
mbed_official	340:28d1f895c6fe	1925	hspi->pRxBuffPtr += sizeof(uint16_t);
mbed_official	340:28d1f895c6fe	1926	hspi->RxXferCount -= 2;
mbed_official	340:28d1f895c6fe	1927	if(hspi->RxXferCount == 1)
mbed_official	340:28d1f895c6fe	1928	{
mbed_official	340:28d1f895c6fe	1929	/* set fiforxthresold according the reception data lenght: 8bit */
mbed_official	340:28d1f895c6fe	1930	SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD);
mbed_official	340:28d1f895c6fe	1931	}
mbed_official	340:28d1f895c6fe	1932	}
mbed_official	340:28d1f895c6fe	1933	/* Receive data in 8 Bit mode */
mbed_official	340:28d1f895c6fe	1934	else
mbed_official	340:28d1f895c6fe	1935	{
mbed_official	340:28d1f895c6fe	1936	hspi->pRxBuffPtr++ = ((__IO uint8_t *)&hspi->Instance->DR);
mbed_official	340:28d1f895c6fe	1937	hspi->RxXferCount--;
mbed_official	340:28d1f895c6fe	1938	}
mbed_official	340:28d1f895c6fe	1939
mbed_official	340:28d1f895c6fe	1940	/* check end of the reception */
mbed_official	340:28d1f895c6fe	1941	if(hspi->RxXferCount == 0)
mbed_official	340:28d1f895c6fe	1942	{
mbed_official	340:28d1f895c6fe	1943	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	340:28d1f895c6fe	1944	{
mbed_official	340:28d1f895c6fe	1945	hspi->RxISR = SPI_2linesRxISR_8BITCRC;
mbed_official	340:28d1f895c6fe	1946	return;
mbed_official	340:28d1f895c6fe	1947	}
mbed_official	340:28d1f895c6fe	1948
mbed_official	340:28d1f895c6fe	1949	/* Disable RXNE interrupt */
mbed_official	340:28d1f895c6fe	1950	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
mbed_official	340:28d1f895c6fe	1951
mbed_official	340:28d1f895c6fe	1952	if(hspi->TxXferCount == 0)
mbed_official	340:28d1f895c6fe	1953	{
mbed_official	340:28d1f895c6fe	1954	SPI_CloseRxTx_ISR(hspi);
mbed_official	340:28d1f895c6fe	1955	}
mbed_official	340:28d1f895c6fe	1956	}
mbed_official	340:28d1f895c6fe	1957	}
mbed_official	340:28d1f895c6fe	1958
mbed_official	340:28d1f895c6fe	1959	/**
mbed_official	340:28d1f895c6fe	1960	* @brief Rx Handler for Transmit and Receive in Interrupt mode
mbed_official	340:28d1f895c6fe	1961	* @param hspi: SPI handle
mbed_official	340:28d1f895c6fe	1962	*/
mbed_official	340:28d1f895c6fe	1963	static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
mbed_official	340:28d1f895c6fe	1964	{
mbed_official	340:28d1f895c6fe	1965	__IO uint8_t tmpreg;
mbed_official	340:28d1f895c6fe	1966
mbed_official	340:28d1f895c6fe	1967	tmpreg = ((__IO uint8_t )&hspi->Instance->DR);
mbed_official	340:28d1f895c6fe	1968	hspi->CRCSize--;
mbed_official	340:28d1f895c6fe	1969
mbed_official	340:28d1f895c6fe	1970	/* check end of the reception */
mbed_official	340:28d1f895c6fe	1971	if(hspi->CRCSize == 0)
mbed_official	340:28d1f895c6fe	1972	{
mbed_official	340:28d1f895c6fe	1973	/* Disable RXNE interrupt */
mbed_official	340:28d1f895c6fe	1974	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
mbed_official	340:28d1f895c6fe	1975
mbed_official	340:28d1f895c6fe	1976	if(hspi->TxXferCount == 0)
mbed_official	340:28d1f895c6fe	1977	{
mbed_official	340:28d1f895c6fe	1978	SPI_CloseRxTx_ISR(hspi);
mbed_official	340:28d1f895c6fe	1979	}
mbed_official	340:28d1f895c6fe	1980	}
mbed_official	340:28d1f895c6fe	1981	}
mbed_official	340:28d1f895c6fe	1982
mbed_official	340:28d1f895c6fe	1983	/**
mbed_official	340:28d1f895c6fe	1984	* @brief Tx Handler for Transmit and Receive in Interrupt mode
mbed_official	340:28d1f895c6fe	1985	* @param hspi: SPI handle
mbed_official	340:28d1f895c6fe	1986	*/
mbed_official	340:28d1f895c6fe	1987	static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
mbed_official	340:28d1f895c6fe	1988	{
mbed_official	340:28d1f895c6fe	1989	/* Transmit data in packing Bit mode */
mbed_official	340:28d1f895c6fe	1990	if(hspi->TxXferCount >= 2)
mbed_official	340:28d1f895c6fe	1991	{
mbed_official	340:28d1f895c6fe	1992	hspi->Instance->DR = ((uint16_t )hspi->pTxBuffPtr);
mbed_official	340:28d1f895c6fe	1993	hspi->pTxBuffPtr += sizeof(uint16_t);
mbed_official	340:28d1f895c6fe	1994	hspi->TxXferCount -= 2;
mbed_official	340:28d1f895c6fe	1995	}
mbed_official	340:28d1f895c6fe	1996	/* Transmit data in 8 Bit mode */
mbed_official	340:28d1f895c6fe	1997	else
mbed_official	340:28d1f895c6fe	1998	{
mbed_official	340:28d1f895c6fe	1999	(__IO uint8_t )&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
mbed_official	340:28d1f895c6fe	2000	hspi->TxXferCount--;
mbed_official	340:28d1f895c6fe	2001	}
mbed_official	340:28d1f895c6fe	2002
mbed_official	340:28d1f895c6fe	2003	/* check the end of the transmission */
mbed_official	340:28d1f895c6fe	2004	if(hspi->TxXferCount == 0)
mbed_official	340:28d1f895c6fe	2005	{
mbed_official	340:28d1f895c6fe	2006	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	340:28d1f895c6fe	2007	{
mbed_official	340:28d1f895c6fe	2008	hspi->Instance->CR1 \|= SPI_CR1_CRCNEXT;
mbed_official	340:28d1f895c6fe	2009	}
mbed_official	340:28d1f895c6fe	2010	/* Disable TXE interrupt */
mbed_official	340:28d1f895c6fe	2011	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
mbed_official	340:28d1f895c6fe	2012
mbed_official	340:28d1f895c6fe	2013	if(hspi->RxXferCount == 0)
mbed_official	340:28d1f895c6fe	2014	{
mbed_official	340:28d1f895c6fe	2015	SPI_CloseRxTx_ISR(hspi);
mbed_official	340:28d1f895c6fe	2016	}
mbed_official	340:28d1f895c6fe	2017	}
mbed_official	340:28d1f895c6fe	2018	}
mbed_official	340:28d1f895c6fe	2019
mbed_official	340:28d1f895c6fe	2020	/**
mbed_official	340:28d1f895c6fe	2021	* @brief Rx 16Bit Handler for Transmit and Receive in Interrupt mode
mbed_official	340:28d1f895c6fe	2022	* @param hspi: SPI handle
mbed_official	340:28d1f895c6fe	2023	*/
mbed_official	340:28d1f895c6fe	2024	static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
mbed_official	340:28d1f895c6fe	2025	{
mbed_official	340:28d1f895c6fe	2026	/* Receive data in 16 Bit mode */
mbed_official	340:28d1f895c6fe	2027	((uint16_t)hspi->pRxBuffPtr) = hspi->Instance->DR;
mbed_official	340:28d1f895c6fe	2028	hspi->pRxBuffPtr += sizeof(uint16_t);
mbed_official	340:28d1f895c6fe	2029	hspi->RxXferCount--;
mbed_official	340:28d1f895c6fe	2030
mbed_official	340:28d1f895c6fe	2031	if(hspi->RxXferCount == 0)
mbed_official	340:28d1f895c6fe	2032	{
mbed_official	340:28d1f895c6fe	2033	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	340:28d1f895c6fe	2034	{
mbed_official	340:28d1f895c6fe	2035	hspi->RxISR = SPI_2linesRxISR_16BITCRC;
mbed_official	340:28d1f895c6fe	2036	return;
mbed_official	340:28d1f895c6fe	2037	}
mbed_official	340:28d1f895c6fe	2038
mbed_official	340:28d1f895c6fe	2039	/* Disable RXNE interrupt */
mbed_official	340:28d1f895c6fe	2040	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
mbed_official	340:28d1f895c6fe	2041
mbed_official	340:28d1f895c6fe	2042	if(hspi->TxXferCount == 0)
mbed_official	340:28d1f895c6fe	2043	{
mbed_official	340:28d1f895c6fe	2044	SPI_CloseRxTx_ISR(hspi);
mbed_official	340:28d1f895c6fe	2045	}
mbed_official	340:28d1f895c6fe	2046	}
mbed_official	340:28d1f895c6fe	2047	}
mbed_official	340:28d1f895c6fe	2048
mbed_official	340:28d1f895c6fe	2049	/**
mbed_official	340:28d1f895c6fe	2050	* @brief Manage the CRC 16bit receive for Transmit and Receive in Interrupt mode
mbed_official	340:28d1f895c6fe	2051	* @param hspi: SPI handle
mbed_official	340:28d1f895c6fe	2052	*/
mbed_official	340:28d1f895c6fe	2053	static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
mbed_official	340:28d1f895c6fe	2054	{
mbed_official	340:28d1f895c6fe	2055	__IO uint16_t tmpreg;
mbed_official	340:28d1f895c6fe	2056	/* Receive data in 16 Bit mode */
mbed_official	340:28d1f895c6fe	2057	tmpreg = hspi->Instance->DR;
mbed_official	340:28d1f895c6fe	2058
mbed_official	340:28d1f895c6fe	2059	/* Disable RXNE interrupt */
mbed_official	340:28d1f895c6fe	2060	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
mbed_official	340:28d1f895c6fe	2061
mbed_official	340:28d1f895c6fe	2062	SPI_CloseRxTx_ISR(hspi);
mbed_official	340:28d1f895c6fe	2063	}
mbed_official	340:28d1f895c6fe	2064
mbed_official	340:28d1f895c6fe	2065	/**
mbed_official	340:28d1f895c6fe	2066	* @brief Tx Handler for Transmit and Receive in Interrupt mode
mbed_official	340:28d1f895c6fe	2067	* @param hspi: SPI handle
mbed_official	340:28d1f895c6fe	2068	*/
mbed_official	340:28d1f895c6fe	2069	static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
mbed_official	340:28d1f895c6fe	2070	{
mbed_official	340:28d1f895c6fe	2071	/* Transmit data in 16 Bit mode */
mbed_official	340:28d1f895c6fe	2072	hspi->Instance->DR = ((uint16_t )hspi->pTxBuffPtr);
mbed_official	340:28d1f895c6fe	2073	hspi->pTxBuffPtr += sizeof(uint16_t);
mbed_official	340:28d1f895c6fe	2074	hspi->TxXferCount--;
mbed_official	340:28d1f895c6fe	2075
mbed_official	340:28d1f895c6fe	2076	/* Enable CRC Transmission */
mbed_official	340:28d1f895c6fe	2077	if(hspi->TxXferCount == 0)
mbed_official	340:28d1f895c6fe	2078	{
mbed_official	340:28d1f895c6fe	2079	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	340:28d1f895c6fe	2080	{
mbed_official	340:28d1f895c6fe	2081	hspi->Instance->CR1 \|= SPI_CR1_CRCNEXT;
mbed_official	340:28d1f895c6fe	2082	}
mbed_official	340:28d1f895c6fe	2083	/* Disable TXE interrupt */
mbed_official	340:28d1f895c6fe	2084	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
mbed_official	340:28d1f895c6fe	2085
mbed_official	340:28d1f895c6fe	2086	if(hspi->RxXferCount == 0)
mbed_official	340:28d1f895c6fe	2087	{
mbed_official	340:28d1f895c6fe	2088	SPI_CloseRxTx_ISR(hspi);
mbed_official	340:28d1f895c6fe	2089	}
mbed_official	340:28d1f895c6fe	2090	}
mbed_official	340:28d1f895c6fe	2091	}
mbed_official	340:28d1f895c6fe	2092
mbed_official	340:28d1f895c6fe	2093	/**
mbed_official	340:28d1f895c6fe	2094	* @brief Manage the CRC receive in Interrupt context
mbed_official	340:28d1f895c6fe	2095	* @param hspi: SPI handle
mbed_official	340:28d1f895c6fe	2096	*/
mbed_official	340:28d1f895c6fe	2097	static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
mbed_official	340:28d1f895c6fe	2098	{
mbed_official	340:28d1f895c6fe	2099	__IO uint8_t tmpreg;
mbed_official	340:28d1f895c6fe	2100	tmpreg = ((__IO uint8_t)&hspi->Instance->DR);
mbed_official	340:28d1f895c6fe	2101	hspi->CRCSize--;
mbed_official	340:28d1f895c6fe	2102
mbed_official	340:28d1f895c6fe	2103	if(hspi->CRCSize == 0)
mbed_official	340:28d1f895c6fe	2104	{
mbed_official	340:28d1f895c6fe	2105	SPI_CloseRx_ISR(hspi);
mbed_official	340:28d1f895c6fe	2106	}
mbed_official	340:28d1f895c6fe	2107	}
mbed_official	340:28d1f895c6fe	2108
mbed_official	340:28d1f895c6fe	2109	/**
mbed_official	340:28d1f895c6fe	2110	* @brief Manage the recieve in Interrupt context
mbed_official	340:28d1f895c6fe	2111	* @param hspi: SPI handle
mbed_official	340:28d1f895c6fe	2112	*/
mbed_official	340:28d1f895c6fe	2113	static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
mbed_official	340:28d1f895c6fe	2114	{
mbed_official	340:28d1f895c6fe	2115	hspi->pRxBuffPtr++ = ((__IO uint8_t *)&hspi->Instance->DR);
mbed_official	340:28d1f895c6fe	2116	hspi->RxXferCount--;
mbed_official	340:28d1f895c6fe	2117
mbed_official	340:28d1f895c6fe	2118	/* Enable CRC Transmission */
mbed_official	340:28d1f895c6fe	2119	if((hspi->RxXferCount == 1) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED))
mbed_official	340:28d1f895c6fe	2120	{
mbed_official	340:28d1f895c6fe	2121	hspi->Instance->CR1 \|= SPI_CR1_CRCNEXT;
mbed_official	340:28d1f895c6fe	2122	}
mbed_official	340:28d1f895c6fe	2123
mbed_official	340:28d1f895c6fe	2124	if(hspi->RxXferCount == 0)
mbed_official	340:28d1f895c6fe	2125	{
mbed_official	340:28d1f895c6fe	2126	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	340:28d1f895c6fe	2127	{
mbed_official	340:28d1f895c6fe	2128	hspi->RxISR = SPI_RxISR_8BITCRC;
mbed_official	340:28d1f895c6fe	2129	return;
mbed_official	340:28d1f895c6fe	2130	}
mbed_official	340:28d1f895c6fe	2131	SPI_CloseRx_ISR(hspi);
mbed_official	340:28d1f895c6fe	2132	}
mbed_official	340:28d1f895c6fe	2133	}
mbed_official	340:28d1f895c6fe	2134
mbed_official	340:28d1f895c6fe	2135	/**
mbed_official	340:28d1f895c6fe	2136	* @brief Manage the CRC 16bit recieve in Interrupt context
mbed_official	340:28d1f895c6fe	2137	* @param hspi: SPI handle
mbed_official	340:28d1f895c6fe	2138	*/
mbed_official	340:28d1f895c6fe	2139	static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
mbed_official	340:28d1f895c6fe	2140	{
mbed_official	340:28d1f895c6fe	2141	__IO uint16_t tmpreg;
mbed_official	340:28d1f895c6fe	2142
mbed_official	340:28d1f895c6fe	2143	tmpreg = hspi->Instance->DR;
mbed_official	340:28d1f895c6fe	2144
mbed_official	340:28d1f895c6fe	2145	/* Disable RXNE and ERR interrupt */
mbed_official	340:28d1f895c6fe	2146	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE \| SPI_IT_ERR));
mbed_official	340:28d1f895c6fe	2147
mbed_official	340:28d1f895c6fe	2148	SPI_CloseRx_ISR(hspi);
mbed_official	340:28d1f895c6fe	2149	}
mbed_official	340:28d1f895c6fe	2150
mbed_official	340:28d1f895c6fe	2151	/**
mbed_official	340:28d1f895c6fe	2152	* @brief Manage the 16Bit recieve in Interrupt context
mbed_official	340:28d1f895c6fe	2153	* @param hspi: SPI handle
mbed_official	340:28d1f895c6fe	2154	*/
mbed_official	340:28d1f895c6fe	2155	static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
mbed_official	340:28d1f895c6fe	2156	{
mbed_official	340:28d1f895c6fe	2157	((uint16_t )hspi->pRxBuffPtr) = hspi->Instance->DR;
mbed_official	340:28d1f895c6fe	2158	hspi->pRxBuffPtr += sizeof(uint16_t);
mbed_official	340:28d1f895c6fe	2159	hspi->RxXferCount--;
mbed_official	340:28d1f895c6fe	2160
mbed_official	340:28d1f895c6fe	2161	/* Enable CRC Transmission */
mbed_official	340:28d1f895c6fe	2162	if((hspi->RxXferCount == 1) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED))
mbed_official	340:28d1f895c6fe	2163	{
mbed_official	340:28d1f895c6fe	2164	hspi->Instance->CR1 \|= SPI_CR1_CRCNEXT;
mbed_official	340:28d1f895c6fe	2165	}
mbed_official	340:28d1f895c6fe	2166
mbed_official	340:28d1f895c6fe	2167	if(hspi->RxXferCount == 0)
mbed_official	340:28d1f895c6fe	2168	{
mbed_official	340:28d1f895c6fe	2169	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	340:28d1f895c6fe	2170	{
mbed_official	340:28d1f895c6fe	2171	hspi->RxISR = SPI_RxISR_16BITCRC;
mbed_official	340:28d1f895c6fe	2172	return;
mbed_official	340:28d1f895c6fe	2173	}
mbed_official	340:28d1f895c6fe	2174	SPI_CloseRx_ISR(hspi);
mbed_official	340:28d1f895c6fe	2175	}
mbed_official	340:28d1f895c6fe	2176	}
mbed_official	340:28d1f895c6fe	2177
mbed_official	340:28d1f895c6fe	2178	/**
mbed_official	340:28d1f895c6fe	2179	* @brief Handle the data 8Bit transmit in Interrupt mode
mbed_official	340:28d1f895c6fe	2180	* @param hspi: SPI handle
mbed_official	340:28d1f895c6fe	2181	*/
mbed_official	340:28d1f895c6fe	2182	static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
mbed_official	340:28d1f895c6fe	2183	{
mbed_official	340:28d1f895c6fe	2184	(__IO uint8_t )&hspi->Instance->DR = (*hspi->pTxBuffPtr++);
mbed_official	340:28d1f895c6fe	2185	hspi->TxXferCount--;
mbed_official	340:28d1f895c6fe	2186
mbed_official	340:28d1f895c6fe	2187	if(hspi->TxXferCount == 0)
mbed_official	340:28d1f895c6fe	2188	{
mbed_official	340:28d1f895c6fe	2189	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	340:28d1f895c6fe	2190	{
mbed_official	340:28d1f895c6fe	2191	/* Enable CRC Transmission */
mbed_official	340:28d1f895c6fe	2192	hspi->Instance->CR1 \|= SPI_CR1_CRCNEXT;
mbed_official	340:28d1f895c6fe	2193	}
mbed_official	340:28d1f895c6fe	2194	SPI_CloseTx_ISR(hspi);
mbed_official	340:28d1f895c6fe	2195	}
mbed_official	340:28d1f895c6fe	2196	}
mbed_official	340:28d1f895c6fe	2197
mbed_official	340:28d1f895c6fe	2198	/**
mbed_official	340:28d1f895c6fe	2199	* @brief Handle the data 16Bit transmit in Interrupt mode
mbed_official	340:28d1f895c6fe	2200	* @param hspi: SPI handle
mbed_official	340:28d1f895c6fe	2201	*/
mbed_official	340:28d1f895c6fe	2202	static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
mbed_official	340:28d1f895c6fe	2203	{
mbed_official	340:28d1f895c6fe	2204	/* Transmit data in 16 Bit mode */
mbed_official	340:28d1f895c6fe	2205	hspi->Instance->DR = ((uint16_t )hspi->pTxBuffPtr);
mbed_official	340:28d1f895c6fe	2206	hspi->pTxBuffPtr += sizeof(uint16_t);
mbed_official	340:28d1f895c6fe	2207	hspi->TxXferCount--;
mbed_official	340:28d1f895c6fe	2208
mbed_official	340:28d1f895c6fe	2209	if(hspi->TxXferCount == 0)
mbed_official	340:28d1f895c6fe	2210	{
mbed_official	340:28d1f895c6fe	2211	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	340:28d1f895c6fe	2212	{
mbed_official	340:28d1f895c6fe	2213	/* Enable CRC Transmission */
mbed_official	340:28d1f895c6fe	2214	hspi->Instance->CR1 \|= SPI_CR1_CRCNEXT;
mbed_official	340:28d1f895c6fe	2215	}
mbed_official	340:28d1f895c6fe	2216	SPI_CloseTx_ISR(hspi);
mbed_official	340:28d1f895c6fe	2217	}
mbed_official	340:28d1f895c6fe	2218	}
mbed_official	340:28d1f895c6fe	2219
mbed_official	340:28d1f895c6fe	2220	/**
mbed_official	340:28d1f895c6fe	2221	* @brief This function handles SPI Communication Timeout.
mbed_official	340:28d1f895c6fe	2222	* @param hspi: SPI handle
mbed_official	340:28d1f895c6fe	2223	* @param Flag : SPI flag to check
mbed_official	340:28d1f895c6fe	2224	* @param State : flag state to check
mbed_official	340:28d1f895c6fe	2225	* @param Timeout : Timeout duration
mbed_official	340:28d1f895c6fe	2226	* @retval HAL status
mbed_official	340:28d1f895c6fe	2227	*/
mbed_official	340:28d1f895c6fe	2228	static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout)
mbed_official	340:28d1f895c6fe	2229	{
mbed_official	340:28d1f895c6fe	2230	uint32_t tickstart = HAL_GetTick();
mbed_official	340:28d1f895c6fe	2231
mbed_official	340:28d1f895c6fe	2232	while((hspi->Instance->SR & Flag) != State)
mbed_official	340:28d1f895c6fe	2233	{
mbed_official	340:28d1f895c6fe	2234	if(Timeout != HAL_MAX_DELAY)
mbed_official	340:28d1f895c6fe	2235	{
mbed_official	340:28d1f895c6fe	2236	if((Timeout == 0) \|\| ((HAL_GetTick() - tickstart) > Timeout))
mbed_official	340:28d1f895c6fe	2237	{
mbed_official	340:28d1f895c6fe	2238	/* Disable the SPI and reset the CRC: the CRC value should be cleared
mbed_official	340:28d1f895c6fe	2239	on both master and slave sides in order to resynchronize the master
mbed_official	340:28d1f895c6fe	2240	and slave for their respective CRC calculation */
mbed_official	340:28d1f895c6fe	2241
mbed_official	340:28d1f895c6fe	2242	/* Disable TXE, RXNE and ERR interrupts for the interrupt process */
mbed_official	340:28d1f895c6fe	2243	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_RXNE \| SPI_IT_ERR));
mbed_official	340:28d1f895c6fe	2244
mbed_official	340:28d1f895c6fe	2245	if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)\|\|(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
mbed_official	340:28d1f895c6fe	2246	{
mbed_official	340:28d1f895c6fe	2247	/* Disable SPI peripheral */
mbed_official	340:28d1f895c6fe	2248	__HAL_SPI_DISABLE(hspi);
mbed_official	340:28d1f895c6fe	2249	}
mbed_official	340:28d1f895c6fe	2250
mbed_official	340:28d1f895c6fe	2251	/* Reset CRC Calculation */
mbed_official	340:28d1f895c6fe	2252	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	340:28d1f895c6fe	2253	{
mbed_official	340:28d1f895c6fe	2254	__HAL_SPI_RESET_CRC(hspi);
mbed_official	340:28d1f895c6fe	2255	}
mbed_official	340:28d1f895c6fe	2256
mbed_official	340:28d1f895c6fe	2257	hspi->State= HAL_SPI_STATE_READY;
mbed_official	340:28d1f895c6fe	2258
mbed_official	340:28d1f895c6fe	2259	/* Process Unlocked */
mbed_official	340:28d1f895c6fe	2260	__HAL_UNLOCK(hspi);
mbed_official	340:28d1f895c6fe	2261
mbed_official	340:28d1f895c6fe	2262	return HAL_TIMEOUT;
mbed_official	340:28d1f895c6fe	2263	}
mbed_official	340:28d1f895c6fe	2264	}
mbed_official	340:28d1f895c6fe	2265	}
mbed_official	340:28d1f895c6fe	2266
mbed_official	340:28d1f895c6fe	2267	return HAL_OK;
mbed_official	340:28d1f895c6fe	2268	}
mbed_official	340:28d1f895c6fe	2269
mbed_official	340:28d1f895c6fe	2270	/**
mbed_official	340:28d1f895c6fe	2271	* @brief This function handles SPI Communication Timeout.
mbed_official	340:28d1f895c6fe	2272	* @param hspi: SPI handle
mbed_official	340:28d1f895c6fe	2273	* @param Fifo: Fifo to check
mbed_official	340:28d1f895c6fe	2274	* @param State: Fifo state to check
mbed_official	340:28d1f895c6fe	2275	* @param Timeout : Timeout duration
mbed_official	340:28d1f895c6fe	2276	* @retval HAL status
mbed_official	340:28d1f895c6fe	2277	*/
mbed_official	340:28d1f895c6fe	2278	static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State, uint32_t Timeout)
mbed_official	340:28d1f895c6fe	2279	{
mbed_official	340:28d1f895c6fe	2280	__IO uint8_t tmpreg;
mbed_official	340:28d1f895c6fe	2281	uint32_t tickstart = HAL_GetTick();
mbed_official	340:28d1f895c6fe	2282
mbed_official	340:28d1f895c6fe	2283	while((hspi->Instance->SR & Fifo) != State)
mbed_official	340:28d1f895c6fe	2284	{
mbed_official	340:28d1f895c6fe	2285	if((Fifo == SPI_SR_FRLVL) && (State == SPI_FRLVL_EMPTY))
mbed_official	340:28d1f895c6fe	2286	{
mbed_official	340:28d1f895c6fe	2287	tmpreg = ((__IO uint8_t)&hspi->Instance->DR);
mbed_official	340:28d1f895c6fe	2288	}
mbed_official	340:28d1f895c6fe	2289	if(Timeout != HAL_MAX_DELAY)
mbed_official	340:28d1f895c6fe	2290	{
mbed_official	340:28d1f895c6fe	2291	if((Timeout == 0) \|\| ((HAL_GetTick() - tickstart) > Timeout))
mbed_official	340:28d1f895c6fe	2292	{
mbed_official	340:28d1f895c6fe	2293	/* Disable the SPI and reset the CRC: the CRC value should be cleared
mbed_official	340:28d1f895c6fe	2294	on both master and slave sides in order to resynchronize the master
mbed_official	340:28d1f895c6fe	2295	and slave for their respective CRC calculation */
mbed_official	340:28d1f895c6fe	2296
mbed_official	340:28d1f895c6fe	2297	/* Disable TXE, RXNE and ERR interrupts for the interrupt process */
mbed_official	340:28d1f895c6fe	2298	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_RXNE \| SPI_IT_ERR));
mbed_official	340:28d1f895c6fe	2299
mbed_official	340:28d1f895c6fe	2300	if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)\|\|(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
mbed_official	340:28d1f895c6fe	2301	{
mbed_official	340:28d1f895c6fe	2302	/* Disable SPI peripheral */
mbed_official	340:28d1f895c6fe	2303	__HAL_SPI_DISABLE(hspi);
mbed_official	340:28d1f895c6fe	2304	}
mbed_official	340:28d1f895c6fe	2305
mbed_official	340:28d1f895c6fe	2306	/* Reset CRC Calculation */
mbed_official	340:28d1f895c6fe	2307	if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
mbed_official	340:28d1f895c6fe	2308	{
mbed_official	340:28d1f895c6fe	2309	__HAL_SPI_RESET_CRC(hspi);
mbed_official	340:28d1f895c6fe	2310	}
mbed_official	340:28d1f895c6fe	2311
mbed_official	340:28d1f895c6fe	2312	hspi->State = HAL_SPI_STATE_READY;
mbed_official	340:28d1f895c6fe	2313
mbed_official	340:28d1f895c6fe	2314	/* Process Unlocked */
mbed_official	340:28d1f895c6fe	2315	__HAL_UNLOCK(hspi);
mbed_official	340:28d1f895c6fe	2316
mbed_official	340:28d1f895c6fe	2317	return HAL_TIMEOUT;
mbed_official	340:28d1f895c6fe	2318	}
mbed_official	340:28d1f895c6fe	2319	}
mbed_official	340:28d1f895c6fe	2320	}
mbed_official	340:28d1f895c6fe	2321
mbed_official	340:28d1f895c6fe	2322	return HAL_OK;
mbed_official	340:28d1f895c6fe	2323	}
mbed_official	340:28d1f895c6fe	2324
mbed_official	340:28d1f895c6fe	2325	/**
mbed_official	340:28d1f895c6fe	2326	* @brief This function handles the check of the RX transaction complete.
mbed_official	340:28d1f895c6fe	2327	* @param hspi: SPI handle
mbed_official	340:28d1f895c6fe	2328	* @param Timeout : Timeout duration
mbed_official	340:28d1f895c6fe	2329	*/
mbed_official	340:28d1f895c6fe	2330	static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout)
mbed_official	340:28d1f895c6fe	2331	{
mbed_official	340:28d1f895c6fe	2332	if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)\|\|(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
mbed_official	340:28d1f895c6fe	2333	{
mbed_official	340:28d1f895c6fe	2334	/* Disable SPI peripheral */
mbed_official	340:28d1f895c6fe	2335	__HAL_SPI_DISABLE(hspi);
mbed_official	340:28d1f895c6fe	2336	}
mbed_official	340:28d1f895c6fe	2337	if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout) != HAL_OK)
mbed_official	340:28d1f895c6fe	2338	{
mbed_official	340:28d1f895c6fe	2339	hspi->ErrorCode \|= HAL_SPI_ERROR_FLAG;
mbed_official	340:28d1f895c6fe	2340	return HAL_TIMEOUT;
mbed_official	340:28d1f895c6fe	2341	}
mbed_official	340:28d1f895c6fe	2342	if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout) != HAL_OK)
mbed_official	340:28d1f895c6fe	2343	{
mbed_official	340:28d1f895c6fe	2344	hspi->ErrorCode \|= HAL_SPI_ERROR_FLAG;
mbed_official	340:28d1f895c6fe	2345	return HAL_TIMEOUT;
mbed_official	340:28d1f895c6fe	2346	}
mbed_official	340:28d1f895c6fe	2347
mbed_official	340:28d1f895c6fe	2348	return HAL_OK;
mbed_official	340:28d1f895c6fe	2349	}
mbed_official	340:28d1f895c6fe	2350
mbed_official	340:28d1f895c6fe	2351	/**
mbed_official	340:28d1f895c6fe	2352	* @brief This function handles the check of the RXTX or TX transaction complete.
mbed_official	340:28d1f895c6fe	2353	* @param hspi: SPI handle
mbed_official	340:28d1f895c6fe	2354	* @param Timeout : Timeout duration
mbed_official	340:28d1f895c6fe	2355	*/
mbed_official	340:28d1f895c6fe	2356	static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout)
mbed_official	340:28d1f895c6fe	2357	{
mbed_official	340:28d1f895c6fe	2358	/* Procedure to check the transaction complete */
mbed_official	340:28d1f895c6fe	2359	if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FTLVL, SPI_FTLVL_EMPTY, Timeout) != HAL_OK)
mbed_official	340:28d1f895c6fe	2360	{
mbed_official	340:28d1f895c6fe	2361	hspi->ErrorCode \|= HAL_SPI_ERROR_FLAG;
mbed_official	340:28d1f895c6fe	2362	return HAL_TIMEOUT;
mbed_official	340:28d1f895c6fe	2363	}
mbed_official	340:28d1f895c6fe	2364	if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout) != HAL_OK)
mbed_official	340:28d1f895c6fe	2365	{
mbed_official	340:28d1f895c6fe	2366	hspi->ErrorCode \|= HAL_SPI_ERROR_FLAG;
mbed_official	340:28d1f895c6fe	2367	return HAL_TIMEOUT;
mbed_official	340:28d1f895c6fe	2368	}
mbed_official	340:28d1f895c6fe	2369	if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, Timeout) != HAL_OK)
mbed_official	340:28d1f895c6fe	2370	{
mbed_official	340:28d1f895c6fe	2371	hspi->ErrorCode \|= HAL_SPI_ERROR_FLAG;
mbed_official	340:28d1f895c6fe	2372	return HAL_TIMEOUT;
mbed_official	340:28d1f895c6fe	2373	}
mbed_official	340:28d1f895c6fe	2374	return HAL_OK;
mbed_official	340:28d1f895c6fe	2375	}
mbed_official	340:28d1f895c6fe	2376
mbed_official	340:28d1f895c6fe	2377	/**
mbed_official	340:28d1f895c6fe	2378	* @brief This function handles the close of the RXTX transaction.
mbed_official	340:28d1f895c6fe	2379	* @param hspi: SPI handle
mbed_official	340:28d1f895c6fe	2380	*/
mbed_official	340:28d1f895c6fe	2381	static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)
mbed_official	340:28d1f895c6fe	2382	{
mbed_official	340:28d1f895c6fe	2383	/* Disable ERR interrupt */
mbed_official	340:28d1f895c6fe	2384	__HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
mbed_official	340:28d1f895c6fe	2385
mbed_official	340:28d1f895c6fe	2386	/* Check the end of the transaction */
mbed_official	340:28d1f895c6fe	2387	SPI_EndRxTxTransaction(hspi,SPI_DEFAULT_TIMEOUT);
mbed_official	340:28d1f895c6fe	2388
mbed_official	340:28d1f895c6fe	2389	/* Check if CRC error occurred */
mbed_official	340:28d1f895c6fe	2390	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
mbed_official	340:28d1f895c6fe	2391	{
mbed_official	340:28d1f895c6fe	2392	hspi->State = HAL_SPI_STATE_READY;
mbed_official	340:28d1f895c6fe	2393	hspi->ErrorCode\|= HAL_SPI_ERROR_CRC;
mbed_official	340:28d1f895c6fe	2394	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
mbed_official	340:28d1f895c6fe	2395	HAL_SPI_ErrorCallback(hspi);
mbed_official	340:28d1f895c6fe	2396	}
mbed_official	340:28d1f895c6fe	2397	else
mbed_official	340:28d1f895c6fe	2398	{
mbed_official	340:28d1f895c6fe	2399	if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
mbed_official	340:28d1f895c6fe	2400	{
mbed_official	340:28d1f895c6fe	2401	if(hspi->State == HAL_SPI_STATE_BUSY_RX)
mbed_official	340:28d1f895c6fe	2402	{
mbed_official	340:28d1f895c6fe	2403	hspi->State = HAL_SPI_STATE_READY;
mbed_official	340:28d1f895c6fe	2404	HAL_SPI_RxCpltCallback(hspi);
mbed_official	340:28d1f895c6fe	2405	}
mbed_official	340:28d1f895c6fe	2406	else
mbed_official	340:28d1f895c6fe	2407	{
mbed_official	340:28d1f895c6fe	2408	hspi->State = HAL_SPI_STATE_READY;
mbed_official	340:28d1f895c6fe	2409	HAL_SPI_TxRxCpltCallback(hspi);
mbed_official	340:28d1f895c6fe	2410	}
mbed_official	340:28d1f895c6fe	2411	}
mbed_official	340:28d1f895c6fe	2412	else
mbed_official	340:28d1f895c6fe	2413	{
mbed_official	340:28d1f895c6fe	2414	hspi->State = HAL_SPI_STATE_READY;
mbed_official	340:28d1f895c6fe	2415	HAL_SPI_ErrorCallback(hspi);
mbed_official	340:28d1f895c6fe	2416	}
mbed_official	340:28d1f895c6fe	2417	}
mbed_official	340:28d1f895c6fe	2418	}
mbed_official	340:28d1f895c6fe	2419
mbed_official	340:28d1f895c6fe	2420	/**
mbed_official	340:28d1f895c6fe	2421	* @brief This function handles the close of the RX transaction.
mbed_official	340:28d1f895c6fe	2422	* @param hspi: SPI handle
mbed_official	340:28d1f895c6fe	2423	*/
mbed_official	340:28d1f895c6fe	2424	static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi)
mbed_official	340:28d1f895c6fe	2425	{
mbed_official	340:28d1f895c6fe	2426	/* Disable RXNE and ERR interrupt */
mbed_official	340:28d1f895c6fe	2427	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE \| SPI_IT_ERR));
mbed_official	340:28d1f895c6fe	2428
mbed_official	340:28d1f895c6fe	2429	/* Check the end of the transaction */
mbed_official	340:28d1f895c6fe	2430	SPI_EndRxTransaction(hspi,SPI_DEFAULT_TIMEOUT);
mbed_official	340:28d1f895c6fe	2431
mbed_official	340:28d1f895c6fe	2432	hspi->State = HAL_SPI_STATE_READY;
mbed_official	340:28d1f895c6fe	2433
mbed_official	340:28d1f895c6fe	2434	/* Check if CRC error occurred */
mbed_official	340:28d1f895c6fe	2435	if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
mbed_official	340:28d1f895c6fe	2436	{
mbed_official	340:28d1f895c6fe	2437	hspi->ErrorCode\|= HAL_SPI_ERROR_CRC;
mbed_official	340:28d1f895c6fe	2438	__HAL_SPI_CLEAR_CRCERRFLAG(hspi);
mbed_official	340:28d1f895c6fe	2439	HAL_SPI_ErrorCallback(hspi);
mbed_official	340:28d1f895c6fe	2440	}
mbed_official	340:28d1f895c6fe	2441	else
mbed_official	340:28d1f895c6fe	2442	{
mbed_official	340:28d1f895c6fe	2443	if(hspi->ErrorCode == HAL_SPI_ERROR_NONE)
mbed_official	340:28d1f895c6fe	2444	{
mbed_official	340:28d1f895c6fe	2445	HAL_SPI_RxCpltCallback(hspi);
mbed_official	340:28d1f895c6fe	2446	}
mbed_official	340:28d1f895c6fe	2447	else
mbed_official	340:28d1f895c6fe	2448	{
mbed_official	340:28d1f895c6fe	2449	HAL_SPI_ErrorCallback(hspi);
mbed_official	340:28d1f895c6fe	2450	}
mbed_official	340:28d1f895c6fe	2451	}
mbed_official	340:28d1f895c6fe	2452	}
mbed_official	340:28d1f895c6fe	2453
mbed_official	340:28d1f895c6fe	2454	/**
mbed_official	340:28d1f895c6fe	2455	* @brief This function handles the close of the TX transaction.
mbed_official	340:28d1f895c6fe	2456	* @param hspi: SPI handle
mbed_official	340:28d1f895c6fe	2457	*/
mbed_official	340:28d1f895c6fe	2458	static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi)
mbed_official	340:28d1f895c6fe	2459	{
mbed_official	340:28d1f895c6fe	2460	/* Disable TXE and ERR interrupt */
mbed_official	340:28d1f895c6fe	2461	__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE \| SPI_IT_ERR));
mbed_official	340:28d1f895c6fe	2462
mbed_official	340:28d1f895c6fe	2463	/* Check the end of the transaction */
mbed_official	340:28d1f895c6fe	2464	SPI_EndRxTxTransaction(hspi,SPI_DEFAULT_TIMEOUT);
mbed_official	340:28d1f895c6fe	2465
mbed_official	340:28d1f895c6fe	2466	/* Clear OVERUN flag in 2 Lines communication mode because received is not read */
mbed_official	340:28d1f895c6fe	2467	if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
mbed_official	340:28d1f895c6fe	2468	{
mbed_official	340:28d1f895c6fe	2469	__HAL_SPI_CLEAR_OVRFLAG(hspi);
mbed_official	340:28d1f895c6fe	2470	}
mbed_official	340:28d1f895c6fe	2471
mbed_official	340:28d1f895c6fe	2472	hspi->State = HAL_SPI_STATE_READY;
mbed_official	340:28d1f895c6fe	2473	if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
mbed_official	340:28d1f895c6fe	2474	{
mbed_official	340:28d1f895c6fe	2475	HAL_SPI_ErrorCallback(hspi);
mbed_official	340:28d1f895c6fe	2476	}
mbed_official	340:28d1f895c6fe	2477	else
mbed_official	340:28d1f895c6fe	2478	{
mbed_official	340:28d1f895c6fe	2479	HAL_SPI_TxCpltCallback(hspi);
mbed_official	340:28d1f895c6fe	2480	}
mbed_official	340:28d1f895c6fe	2481	}
mbed_official	340:28d1f895c6fe	2482
mbed_official	340:28d1f895c6fe	2483	/**
mbed_official	340:28d1f895c6fe	2484	* @}
mbed_official	340:28d1f895c6fe	2485	*/
mbed_official	340:28d1f895c6fe	2486
mbed_official	340:28d1f895c6fe	2487	#endif /* HAL_SPI_MODULE_ENABLED */
mbed_official	340:28d1f895c6fe	2488	/**
mbed_official	340:28d1f895c6fe	2489	* @}
mbed_official	340:28d1f895c6fe	2490	*/
mbed_official	340:28d1f895c6fe	2491
mbed_official	340:28d1f895c6fe	2492	/**
mbed_official	340:28d1f895c6fe	2493	* @}
mbed_official	340:28d1f895c6fe	2494	*/
mbed_official	340:28d1f895c6fe	2495
mbed_official	340:28d1f895c6fe	2496	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/