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targets/cmsis/TARGET_STM/TARGET_DISCO_F429ZI/stm32f4xx_hal_sram.c@340:28d1f895c6fe, 2014-10-09 (annotated)

Committer:
mbed_official
Date:
Thu Oct 09 08:15:07 2014 +0100
Revision:
340:28d1f895c6fe
Synchronized with git revision b5a4c8e80393336b2656fb29ab46d405d3068602



Full URL: https://github.com/mbedmicro/mbed/commit/b5a4c8e80393336b2656fb29ab46d405d3068602/



HAL: nrf51822 - Few fixes for PWM and Serial

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 340:28d1f895c6fe 1 /**
mbed_official 340:28d1f895c6fe 2 ******************************************************************************
mbed_official 340:28d1f895c6fe 3 * @file stm32f4xx_hal_sram.c
mbed_official 340:28d1f895c6fe 4 * @author MCD Application Team
mbed_official 340:28d1f895c6fe 5 * @version V1.1.0
mbed_official 340:28d1f895c6fe 6 * @date 19-June-2014
mbed_official 340:28d1f895c6fe 7 * @brief SRAM HAL module driver.
mbed_official 340:28d1f895c6fe 8 * This file provides a generic firmware to drive SRAM memories
mbed_official 340:28d1f895c6fe 9 * mounted as external device.
mbed_official 340:28d1f895c6fe 10 *
mbed_official 340:28d1f895c6fe 11 @verbatim
mbed_official 340:28d1f895c6fe 12 ==============================================================================
mbed_official 340:28d1f895c6fe 13 ##### How to use this driver #####
mbed_official 340:28d1f895c6fe 14 ==============================================================================
mbed_official 340:28d1f895c6fe 15 [..]
mbed_official 340:28d1f895c6fe 16 This driver is a generic layered driver which contains a set of APIs used to
mbed_official 340:28d1f895c6fe 17 control SRAM memories. It uses the FMC layer functions to interface
mbed_official 340:28d1f895c6fe 18 with SRAM devices.
mbed_official 340:28d1f895c6fe 19 The following sequence should be followed to configure the FMC/FSMC to interface
mbed_official 340:28d1f895c6fe 20 with SRAM/PSRAM memories:
mbed_official 340:28d1f895c6fe 21
mbed_official 340:28d1f895c6fe 22 (#) Declare a SRAM_HandleTypeDef handle structure, for example:
mbed_official 340:28d1f895c6fe 23 SRAM_HandleTypeDef hsram; and:
mbed_official 340:28d1f895c6fe 24
mbed_official 340:28d1f895c6fe 25 (++) Fill the SRAM_HandleTypeDef handle "Init" field with the allowed
mbed_official 340:28d1f895c6fe 26 values of the structure member.
mbed_official 340:28d1f895c6fe 27
mbed_official 340:28d1f895c6fe 28 (++) Fill the SRAM_HandleTypeDef handle "Instance" field with a predefined
mbed_official 340:28d1f895c6fe 29 base register instance for NOR or SRAM device
mbed_official 340:28d1f895c6fe 30
mbed_official 340:28d1f895c6fe 31 (++) Fill the SRAM_HandleTypeDef handle "Extended" field with a predefined
mbed_official 340:28d1f895c6fe 32 base register instance for NOR or SRAM extended mode
mbed_official 340:28d1f895c6fe 33
mbed_official 340:28d1f895c6fe 34 (#) Declare two FMC_NORSRAM_TimingTypeDef structures, for both normal and extended
mbed_official 340:28d1f895c6fe 35 mode timings; for example:
mbed_official 340:28d1f895c6fe 36 FMC_NORSRAM_TimingTypeDef Timing and FMC_NORSRAM_TimingTypeDef ExTiming;
mbed_official 340:28d1f895c6fe 37 and fill its fields with the allowed values of the structure member.
mbed_official 340:28d1f895c6fe 38
mbed_official 340:28d1f895c6fe 39 (#) Initialize the SRAM Controller by calling the function HAL_SRAM_Init(). This function
mbed_official 340:28d1f895c6fe 40 performs the following sequence:
mbed_official 340:28d1f895c6fe 41
mbed_official 340:28d1f895c6fe 42 (##) MSP hardware layer configuration using the function HAL_SRAM_MspInit()
mbed_official 340:28d1f895c6fe 43 (##) Control register configuration using the FMC NORSRAM interface function
mbed_official 340:28d1f895c6fe 44 FMC_NORSRAM_Init()
mbed_official 340:28d1f895c6fe 45 (##) Timing register configuration using the FMC NORSRAM interface function
mbed_official 340:28d1f895c6fe 46 FMC_NORSRAM_Timing_Init()
mbed_official 340:28d1f895c6fe 47 (##) Extended mode Timing register configuration using the FMC NORSRAM interface function
mbed_official 340:28d1f895c6fe 48 FMC_NORSRAM_Extended_Timing_Init()
mbed_official 340:28d1f895c6fe 49 (##) Enable the SRAM device using the macro __FMC_NORSRAM_ENABLE()
mbed_official 340:28d1f895c6fe 50
mbed_official 340:28d1f895c6fe 51 (#) At this stage you can perform read/write accesses from/to the memory connected
mbed_official 340:28d1f895c6fe 52 to the NOR/SRAM Bank. You can perform either polling or DMA transfer using the
mbed_official 340:28d1f895c6fe 53 following APIs:
mbed_official 340:28d1f895c6fe 54 (++) HAL_SRAM_Read()/HAL_SRAM_Write() for polling read/write access
mbed_official 340:28d1f895c6fe 55 (++) HAL_SRAM_Read_DMA()/HAL_SRAM_Write_DMA() for DMA read/write transfer
mbed_official 340:28d1f895c6fe 56
mbed_official 340:28d1f895c6fe 57 (#) You can also control the SRAM device by calling the control APIs HAL_SRAM_WriteOperation_Enable()/
mbed_official 340:28d1f895c6fe 58 HAL_SRAM_WriteOperation_Disable() to respectively enable/disable the SRAM write operation
mbed_official 340:28d1f895c6fe 59
mbed_official 340:28d1f895c6fe 60 (#) You can continuously monitor the SRAM device HAL state by calling the function
mbed_official 340:28d1f895c6fe 61 HAL_SRAM_GetState()
mbed_official 340:28d1f895c6fe 62
mbed_official 340:28d1f895c6fe 63 @endverbatim
mbed_official 340:28d1f895c6fe 64 ******************************************************************************
mbed_official 340:28d1f895c6fe 65 * @attention
mbed_official 340:28d1f895c6fe 66 *
mbed_official 340:28d1f895c6fe 67 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
mbed_official 340:28d1f895c6fe 68 *
mbed_official 340:28d1f895c6fe 69 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 340:28d1f895c6fe 70 * are permitted provided that the following conditions are met:
mbed_official 340:28d1f895c6fe 71 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 340:28d1f895c6fe 72 * this list of conditions and the following disclaimer.
mbed_official 340:28d1f895c6fe 73 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 340:28d1f895c6fe 74 * this list of conditions and the following disclaimer in the documentation
mbed_official 340:28d1f895c6fe 75 * and/or other materials provided with the distribution.
mbed_official 340:28d1f895c6fe 76 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 340:28d1f895c6fe 77 * may be used to endorse or promote products derived from this software
mbed_official 340:28d1f895c6fe 78 * without specific prior written permission.
mbed_official 340:28d1f895c6fe 79 *
mbed_official 340:28d1f895c6fe 80 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 340:28d1f895c6fe 81 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 340:28d1f895c6fe 82 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 340:28d1f895c6fe 83 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 340:28d1f895c6fe 84 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 340:28d1f895c6fe 85 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 340:28d1f895c6fe 86 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 340:28d1f895c6fe 87 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 340:28d1f895c6fe 88 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 340:28d1f895c6fe 89 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 340:28d1f895c6fe 90 *
mbed_official 340:28d1f895c6fe 91 ******************************************************************************
mbed_official 340:28d1f895c6fe 92 */
mbed_official 340:28d1f895c6fe 93
mbed_official 340:28d1f895c6fe 94 /* Includes ------------------------------------------------------------------*/
mbed_official 340:28d1f895c6fe 95 #include "stm32f4xx_hal.h"
mbed_official 340:28d1f895c6fe 96
mbed_official 340:28d1f895c6fe 97 /** @addtogroup STM32F4xx_HAL_Driver
mbed_official 340:28d1f895c6fe 98 * @{
mbed_official 340:28d1f895c6fe 99 */
mbed_official 340:28d1f895c6fe 100
mbed_official 340:28d1f895c6fe 101 /** @defgroup SRAM
mbed_official 340:28d1f895c6fe 102 * @brief SRAM driver modules
mbed_official 340:28d1f895c6fe 103 * @{
mbed_official 340:28d1f895c6fe 104 */
mbed_official 340:28d1f895c6fe 105 #ifdef HAL_SRAM_MODULE_ENABLED
mbed_official 340:28d1f895c6fe 106
mbed_official 340:28d1f895c6fe 107 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
mbed_official 340:28d1f895c6fe 108
mbed_official 340:28d1f895c6fe 109 /* Private typedef -----------------------------------------------------------*/
mbed_official 340:28d1f895c6fe 110 /* Private define ------------------------------------------------------------*/
mbed_official 340:28d1f895c6fe 111 /* Private macro -------------------------------------------------------------*/
mbed_official 340:28d1f895c6fe 112 /* Private variables ---------------------------------------------------------*/
mbed_official 340:28d1f895c6fe 113 /* Private function prototypes -----------------------------------------------*/
mbed_official 340:28d1f895c6fe 114
mbed_official 340:28d1f895c6fe 115 /* Private functions ---------------------------------------------------------*/
mbed_official 340:28d1f895c6fe 116
mbed_official 340:28d1f895c6fe 117 /** @defgroup SRAM_Private_Functions
mbed_official 340:28d1f895c6fe 118 * @{
mbed_official 340:28d1f895c6fe 119 */
mbed_official 340:28d1f895c6fe 120
mbed_official 340:28d1f895c6fe 121 /** @defgroup SRAM_Group1 Initialization and de-initialization functions
mbed_official 340:28d1f895c6fe 122 * @brief Initialization and Configuration functions
mbed_official 340:28d1f895c6fe 123 *
mbed_official 340:28d1f895c6fe 124 @verbatim
mbed_official 340:28d1f895c6fe 125 ==============================================================================
mbed_official 340:28d1f895c6fe 126 ##### SRAM Initialization and de_initialization functions #####
mbed_official 340:28d1f895c6fe 127 ==============================================================================
mbed_official 340:28d1f895c6fe 128 [..] This section provides functions allowing to initialize/de-initialize
mbed_official 340:28d1f895c6fe 129 the SRAM memory
mbed_official 340:28d1f895c6fe 130
mbed_official 340:28d1f895c6fe 131 @endverbatim
mbed_official 340:28d1f895c6fe 132 * @{
mbed_official 340:28d1f895c6fe 133 */
mbed_official 340:28d1f895c6fe 134
mbed_official 340:28d1f895c6fe 135 /**
mbed_official 340:28d1f895c6fe 136 * @brief Performs the SRAM device initialization sequence
mbed_official 340:28d1f895c6fe 137 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
mbed_official 340:28d1f895c6fe 138 * the configuration information for SRAM module.
mbed_official 340:28d1f895c6fe 139 * @param Timing: Pointer to SRAM control timing structure
mbed_official 340:28d1f895c6fe 140 * @param ExtTiming: Pointer to SRAM extended mode timing structure
mbed_official 340:28d1f895c6fe 141 * @retval HAL status
mbed_official 340:28d1f895c6fe 142 */
mbed_official 340:28d1f895c6fe 143 HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming)
mbed_official 340:28d1f895c6fe 144 {
mbed_official 340:28d1f895c6fe 145 /* Check the SRAM handle parameter */
mbed_official 340:28d1f895c6fe 146 if(hsram == NULL)
mbed_official 340:28d1f895c6fe 147 {
mbed_official 340:28d1f895c6fe 148 return HAL_ERROR;
mbed_official 340:28d1f895c6fe 149 }
mbed_official 340:28d1f895c6fe 150
mbed_official 340:28d1f895c6fe 151 if(hsram->State == HAL_SRAM_STATE_RESET)
mbed_official 340:28d1f895c6fe 152 {
mbed_official 340:28d1f895c6fe 153 /* Initialize the low level hardware (MSP) */
mbed_official 340:28d1f895c6fe 154 HAL_SRAM_MspInit(hsram);
mbed_official 340:28d1f895c6fe 155 }
mbed_official 340:28d1f895c6fe 156
mbed_official 340:28d1f895c6fe 157 /* Initialize SRAM control Interface */
mbed_official 340:28d1f895c6fe 158 FMC_NORSRAM_Init(hsram->Instance, &(hsram->Init));
mbed_official 340:28d1f895c6fe 159
mbed_official 340:28d1f895c6fe 160 /* Initialize SRAM timing Interface */
mbed_official 340:28d1f895c6fe 161 FMC_NORSRAM_Timing_Init(hsram->Instance, Timing, hsram->Init.NSBank);
mbed_official 340:28d1f895c6fe 162
mbed_official 340:28d1f895c6fe 163 /* Initialize SRAM extended mode timing Interface */
mbed_official 340:28d1f895c6fe 164 FMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank, hsram->Init.ExtendedMode);
mbed_official 340:28d1f895c6fe 165
mbed_official 340:28d1f895c6fe 166 /* Enable the NORSRAM device */
mbed_official 340:28d1f895c6fe 167 __FMC_NORSRAM_ENABLE(hsram->Instance, hsram->Init.NSBank);
mbed_official 340:28d1f895c6fe 168
mbed_official 340:28d1f895c6fe 169 return HAL_OK;
mbed_official 340:28d1f895c6fe 170 }
mbed_official 340:28d1f895c6fe 171
mbed_official 340:28d1f895c6fe 172 /**
mbed_official 340:28d1f895c6fe 173 * @brief Performs the SRAM device De-initialization sequence.
mbed_official 340:28d1f895c6fe 174 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
mbed_official 340:28d1f895c6fe 175 * the configuration information for SRAM module.
mbed_official 340:28d1f895c6fe 176 * @retval HAL status
mbed_official 340:28d1f895c6fe 177 */
mbed_official 340:28d1f895c6fe 178 HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram)
mbed_official 340:28d1f895c6fe 179 {
mbed_official 340:28d1f895c6fe 180 /* De-Initialize the low level hardware (MSP) */
mbed_official 340:28d1f895c6fe 181 HAL_SRAM_MspDeInit(hsram);
mbed_official 340:28d1f895c6fe 182
mbed_official 340:28d1f895c6fe 183 /* Configure the SRAM registers with their reset values */
mbed_official 340:28d1f895c6fe 184 FMC_NORSRAM_DeInit(hsram->Instance, hsram->Extended, hsram->Init.NSBank);
mbed_official 340:28d1f895c6fe 185
mbed_official 340:28d1f895c6fe 186 hsram->State = HAL_SRAM_STATE_RESET;
mbed_official 340:28d1f895c6fe 187
mbed_official 340:28d1f895c6fe 188 /* Release Lock */
mbed_official 340:28d1f895c6fe 189 __HAL_UNLOCK(hsram);
mbed_official 340:28d1f895c6fe 190
mbed_official 340:28d1f895c6fe 191 return HAL_OK;
mbed_official 340:28d1f895c6fe 192 }
mbed_official 340:28d1f895c6fe 193
mbed_official 340:28d1f895c6fe 194 /**
mbed_official 340:28d1f895c6fe 195 * @brief SRAM MSP Init.
mbed_official 340:28d1f895c6fe 196 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
mbed_official 340:28d1f895c6fe 197 * the configuration information for SRAM module.
mbed_official 340:28d1f895c6fe 198 * @retval None
mbed_official 340:28d1f895c6fe 199 */
mbed_official 340:28d1f895c6fe 200 __weak void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram)
mbed_official 340:28d1f895c6fe 201 {
mbed_official 340:28d1f895c6fe 202 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 340:28d1f895c6fe 203 the HAL_SRAM_MspInit could be implemented in the user file
mbed_official 340:28d1f895c6fe 204 */
mbed_official 340:28d1f895c6fe 205 }
mbed_official 340:28d1f895c6fe 206
mbed_official 340:28d1f895c6fe 207 /**
mbed_official 340:28d1f895c6fe 208 * @brief SRAM MSP DeInit.
mbed_official 340:28d1f895c6fe 209 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
mbed_official 340:28d1f895c6fe 210 * the configuration information for SRAM module.
mbed_official 340:28d1f895c6fe 211 * @retval None
mbed_official 340:28d1f895c6fe 212 */
mbed_official 340:28d1f895c6fe 213 __weak void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram)
mbed_official 340:28d1f895c6fe 214 {
mbed_official 340:28d1f895c6fe 215 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 340:28d1f895c6fe 216 the HAL_SRAM_MspDeInit could be implemented in the user file
mbed_official 340:28d1f895c6fe 217 */
mbed_official 340:28d1f895c6fe 218 }
mbed_official 340:28d1f895c6fe 219
mbed_official 340:28d1f895c6fe 220 /**
mbed_official 340:28d1f895c6fe 221 * @brief DMA transfer complete callback.
mbed_official 340:28d1f895c6fe 222 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
mbed_official 340:28d1f895c6fe 223 * the configuration information for SRAM module.
mbed_official 340:28d1f895c6fe 224 * @retval None
mbed_official 340:28d1f895c6fe 225 */
mbed_official 340:28d1f895c6fe 226 __weak void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma)
mbed_official 340:28d1f895c6fe 227 {
mbed_official 340:28d1f895c6fe 228 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 340:28d1f895c6fe 229 the HAL_SRAM_DMA_XferCpltCallback could be implemented in the user file
mbed_official 340:28d1f895c6fe 230 */
mbed_official 340:28d1f895c6fe 231 }
mbed_official 340:28d1f895c6fe 232
mbed_official 340:28d1f895c6fe 233 /**
mbed_official 340:28d1f895c6fe 234 * @brief DMA transfer complete error callback.
mbed_official 340:28d1f895c6fe 235 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
mbed_official 340:28d1f895c6fe 236 * the configuration information for SRAM module.
mbed_official 340:28d1f895c6fe 237 * @retval None
mbed_official 340:28d1f895c6fe 238 */
mbed_official 340:28d1f895c6fe 239 __weak void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma)
mbed_official 340:28d1f895c6fe 240 {
mbed_official 340:28d1f895c6fe 241 /* NOTE : This function Should not be modified, when the callback is needed,
mbed_official 340:28d1f895c6fe 242 the HAL_SRAM_DMA_XferErrorCallback could be implemented in the user file
mbed_official 340:28d1f895c6fe 243 */
mbed_official 340:28d1f895c6fe 244 }
mbed_official 340:28d1f895c6fe 245
mbed_official 340:28d1f895c6fe 246 /**
mbed_official 340:28d1f895c6fe 247 * @}
mbed_official 340:28d1f895c6fe 248 */
mbed_official 340:28d1f895c6fe 249
mbed_official 340:28d1f895c6fe 250 /** @defgroup SRAM_Group2 Input and Output functions
mbed_official 340:28d1f895c6fe 251 * @brief Input Output and memory control functions
mbed_official 340:28d1f895c6fe 252 *
mbed_official 340:28d1f895c6fe 253 @verbatim
mbed_official 340:28d1f895c6fe 254 ==============================================================================
mbed_official 340:28d1f895c6fe 255 ##### SRAM Input and Output functions #####
mbed_official 340:28d1f895c6fe 256 ==============================================================================
mbed_official 340:28d1f895c6fe 257 [..]
mbed_official 340:28d1f895c6fe 258 This section provides functions allowing to use and control the SRAM memory
mbed_official 340:28d1f895c6fe 259
mbed_official 340:28d1f895c6fe 260 @endverbatim
mbed_official 340:28d1f895c6fe 261 * @{
mbed_official 340:28d1f895c6fe 262 */
mbed_official 340:28d1f895c6fe 263
mbed_official 340:28d1f895c6fe 264 /**
mbed_official 340:28d1f895c6fe 265 * @brief Reads 8-bit buffer from SRAM memory.
mbed_official 340:28d1f895c6fe 266 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
mbed_official 340:28d1f895c6fe 267 * the configuration information for SRAM module.
mbed_official 340:28d1f895c6fe 268 * @param pAddress: Pointer to read start address
mbed_official 340:28d1f895c6fe 269 * @param pDstBuffer: Pointer to destination buffer
mbed_official 340:28d1f895c6fe 270 * @param BufferSize: Size of the buffer to read from memory
mbed_official 340:28d1f895c6fe 271 * @retval HAL status
mbed_official 340:28d1f895c6fe 272 */
mbed_official 340:28d1f895c6fe 273 HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize)
mbed_official 340:28d1f895c6fe 274 {
mbed_official 340:28d1f895c6fe 275 __IO uint8_t * pSramAddress = (uint8_t *)pAddress;
mbed_official 340:28d1f895c6fe 276
mbed_official 340:28d1f895c6fe 277 /* Process Locked */
mbed_official 340:28d1f895c6fe 278 __HAL_LOCK(hsram);
mbed_official 340:28d1f895c6fe 279
mbed_official 340:28d1f895c6fe 280 /* Update the SRAM controller state */
mbed_official 340:28d1f895c6fe 281 hsram->State = HAL_SRAM_STATE_BUSY;
mbed_official 340:28d1f895c6fe 282
mbed_official 340:28d1f895c6fe 283 /* Read data from memory */
mbed_official 340:28d1f895c6fe 284 for(; BufferSize != 0; BufferSize--)
mbed_official 340:28d1f895c6fe 285 {
mbed_official 340:28d1f895c6fe 286 *pDstBuffer = *(__IO uint8_t *)pSramAddress;
mbed_official 340:28d1f895c6fe 287 pDstBuffer++;
mbed_official 340:28d1f895c6fe 288 pSramAddress++;
mbed_official 340:28d1f895c6fe 289 }
mbed_official 340:28d1f895c6fe 290
mbed_official 340:28d1f895c6fe 291 /* Update the SRAM controller state */
mbed_official 340:28d1f895c6fe 292 hsram->State = HAL_SRAM_STATE_READY;
mbed_official 340:28d1f895c6fe 293
mbed_official 340:28d1f895c6fe 294 /* Process unlocked */
mbed_official 340:28d1f895c6fe 295 __HAL_UNLOCK(hsram);
mbed_official 340:28d1f895c6fe 296
mbed_official 340:28d1f895c6fe 297 return HAL_OK;
mbed_official 340:28d1f895c6fe 298 }
mbed_official 340:28d1f895c6fe 299
mbed_official 340:28d1f895c6fe 300 /**
mbed_official 340:28d1f895c6fe 301 * @brief Writes 8-bit buffer to SRAM memory.
mbed_official 340:28d1f895c6fe 302 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
mbed_official 340:28d1f895c6fe 303 * the configuration information for SRAM module.
mbed_official 340:28d1f895c6fe 304 * @param pAddress: Pointer to write start address
mbed_official 340:28d1f895c6fe 305 * @param pSrcBuffer: Pointer to source buffer to write
mbed_official 340:28d1f895c6fe 306 * @param BufferSize: Size of the buffer to write to memory
mbed_official 340:28d1f895c6fe 307 * @retval HAL status
mbed_official 340:28d1f895c6fe 308 */
mbed_official 340:28d1f895c6fe 309 HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize)
mbed_official 340:28d1f895c6fe 310 {
mbed_official 340:28d1f895c6fe 311 __IO uint8_t * pSramAddress = (uint8_t *)pAddress;
mbed_official 340:28d1f895c6fe 312
mbed_official 340:28d1f895c6fe 313 /* Check the SRAM controller state */
mbed_official 340:28d1f895c6fe 314 if(hsram->State == HAL_SRAM_STATE_PROTECTED)
mbed_official 340:28d1f895c6fe 315 {
mbed_official 340:28d1f895c6fe 316 return HAL_ERROR;
mbed_official 340:28d1f895c6fe 317 }
mbed_official 340:28d1f895c6fe 318
mbed_official 340:28d1f895c6fe 319 /* Process Locked */
mbed_official 340:28d1f895c6fe 320 __HAL_LOCK(hsram);
mbed_official 340:28d1f895c6fe 321
mbed_official 340:28d1f895c6fe 322 /* Update the SRAM controller state */
mbed_official 340:28d1f895c6fe 323 hsram->State = HAL_SRAM_STATE_BUSY;
mbed_official 340:28d1f895c6fe 324
mbed_official 340:28d1f895c6fe 325 /* Write data to memory */
mbed_official 340:28d1f895c6fe 326 for(; BufferSize != 0; BufferSize--)
mbed_official 340:28d1f895c6fe 327 {
mbed_official 340:28d1f895c6fe 328 *(__IO uint8_t *)pSramAddress = *pSrcBuffer;
mbed_official 340:28d1f895c6fe 329 pSrcBuffer++;
mbed_official 340:28d1f895c6fe 330 pSramAddress++;
mbed_official 340:28d1f895c6fe 331 }
mbed_official 340:28d1f895c6fe 332
mbed_official 340:28d1f895c6fe 333 /* Update the SRAM controller state */
mbed_official 340:28d1f895c6fe 334 hsram->State = HAL_SRAM_STATE_READY;
mbed_official 340:28d1f895c6fe 335
mbed_official 340:28d1f895c6fe 336 /* Process unlocked */
mbed_official 340:28d1f895c6fe 337 __HAL_UNLOCK(hsram);
mbed_official 340:28d1f895c6fe 338
mbed_official 340:28d1f895c6fe 339 return HAL_OK;
mbed_official 340:28d1f895c6fe 340 }
mbed_official 340:28d1f895c6fe 341
mbed_official 340:28d1f895c6fe 342 /**
mbed_official 340:28d1f895c6fe 343 * @brief Reads 16-bit buffer from SRAM memory.
mbed_official 340:28d1f895c6fe 344 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
mbed_official 340:28d1f895c6fe 345 * the configuration information for SRAM module.
mbed_official 340:28d1f895c6fe 346 * @param pAddress: Pointer to read start address
mbed_official 340:28d1f895c6fe 347 * @param pDstBuffer: Pointer to destination buffer
mbed_official 340:28d1f895c6fe 348 * @param BufferSize: Size of the buffer to read from memory
mbed_official 340:28d1f895c6fe 349 * @retval HAL status
mbed_official 340:28d1f895c6fe 350 */
mbed_official 340:28d1f895c6fe 351 HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize)
mbed_official 340:28d1f895c6fe 352 {
mbed_official 340:28d1f895c6fe 353 __IO uint16_t * pSramAddress = (uint16_t *)pAddress;
mbed_official 340:28d1f895c6fe 354
mbed_official 340:28d1f895c6fe 355 /* Process Locked */
mbed_official 340:28d1f895c6fe 356 __HAL_LOCK(hsram);
mbed_official 340:28d1f895c6fe 357
mbed_official 340:28d1f895c6fe 358 /* Update the SRAM controller state */
mbed_official 340:28d1f895c6fe 359 hsram->State = HAL_SRAM_STATE_BUSY;
mbed_official 340:28d1f895c6fe 360
mbed_official 340:28d1f895c6fe 361 /* Read data from memory */
mbed_official 340:28d1f895c6fe 362 for(; BufferSize != 0; BufferSize--)
mbed_official 340:28d1f895c6fe 363 {
mbed_official 340:28d1f895c6fe 364 *pDstBuffer = *(__IO uint16_t *)pSramAddress;
mbed_official 340:28d1f895c6fe 365 pDstBuffer++;
mbed_official 340:28d1f895c6fe 366 pSramAddress++;
mbed_official 340:28d1f895c6fe 367 }
mbed_official 340:28d1f895c6fe 368
mbed_official 340:28d1f895c6fe 369 /* Update the SRAM controller state */
mbed_official 340:28d1f895c6fe 370 hsram->State = HAL_SRAM_STATE_READY;
mbed_official 340:28d1f895c6fe 371
mbed_official 340:28d1f895c6fe 372 /* Process unlocked */
mbed_official 340:28d1f895c6fe 373 __HAL_UNLOCK(hsram);
mbed_official 340:28d1f895c6fe 374
mbed_official 340:28d1f895c6fe 375 return HAL_OK;
mbed_official 340:28d1f895c6fe 376 }
mbed_official 340:28d1f895c6fe 377
mbed_official 340:28d1f895c6fe 378 /**
mbed_official 340:28d1f895c6fe 379 * @brief Writes 16-bit buffer to SRAM memory.
mbed_official 340:28d1f895c6fe 380 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
mbed_official 340:28d1f895c6fe 381 * the configuration information for SRAM module.
mbed_official 340:28d1f895c6fe 382 * @param pAddress: Pointer to write start address
mbed_official 340:28d1f895c6fe 383 * @param pSrcBuffer: Pointer to source buffer to write
mbed_official 340:28d1f895c6fe 384 * @param BufferSize: Size of the buffer to write to memory
mbed_official 340:28d1f895c6fe 385 * @retval HAL status
mbed_official 340:28d1f895c6fe 386 */
mbed_official 340:28d1f895c6fe 387 HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize)
mbed_official 340:28d1f895c6fe 388 {
mbed_official 340:28d1f895c6fe 389 __IO uint16_t * pSramAddress = (uint16_t *)pAddress;
mbed_official 340:28d1f895c6fe 390
mbed_official 340:28d1f895c6fe 391 /* Check the SRAM controller state */
mbed_official 340:28d1f895c6fe 392 if(hsram->State == HAL_SRAM_STATE_PROTECTED)
mbed_official 340:28d1f895c6fe 393 {
mbed_official 340:28d1f895c6fe 394 return HAL_ERROR;
mbed_official 340:28d1f895c6fe 395 }
mbed_official 340:28d1f895c6fe 396
mbed_official 340:28d1f895c6fe 397 /* Process Locked */
mbed_official 340:28d1f895c6fe 398 __HAL_LOCK(hsram);
mbed_official 340:28d1f895c6fe 399
mbed_official 340:28d1f895c6fe 400 /* Update the SRAM controller state */
mbed_official 340:28d1f895c6fe 401 hsram->State = HAL_SRAM_STATE_BUSY;
mbed_official 340:28d1f895c6fe 402
mbed_official 340:28d1f895c6fe 403 /* Write data to memory */
mbed_official 340:28d1f895c6fe 404 for(; BufferSize != 0; BufferSize--)
mbed_official 340:28d1f895c6fe 405 {
mbed_official 340:28d1f895c6fe 406 *(__IO uint16_t *)pSramAddress = *pSrcBuffer;
mbed_official 340:28d1f895c6fe 407 pSrcBuffer++;
mbed_official 340:28d1f895c6fe 408 pSramAddress++;
mbed_official 340:28d1f895c6fe 409 }
mbed_official 340:28d1f895c6fe 410
mbed_official 340:28d1f895c6fe 411 /* Update the SRAM controller state */
mbed_official 340:28d1f895c6fe 412 hsram->State = HAL_SRAM_STATE_READY;
mbed_official 340:28d1f895c6fe 413
mbed_official 340:28d1f895c6fe 414 /* Process unlocked */
mbed_official 340:28d1f895c6fe 415 __HAL_UNLOCK(hsram);
mbed_official 340:28d1f895c6fe 416
mbed_official 340:28d1f895c6fe 417 return HAL_OK;
mbed_official 340:28d1f895c6fe 418 }
mbed_official 340:28d1f895c6fe 419
mbed_official 340:28d1f895c6fe 420 /**
mbed_official 340:28d1f895c6fe 421 * @brief Reads 32-bit buffer from SRAM memory.
mbed_official 340:28d1f895c6fe 422 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
mbed_official 340:28d1f895c6fe 423 * the configuration information for SRAM module.
mbed_official 340:28d1f895c6fe 424 * @param pAddress: Pointer to read start address
mbed_official 340:28d1f895c6fe 425 * @param pDstBuffer: Pointer to destination buffer
mbed_official 340:28d1f895c6fe 426 * @param BufferSize: Size of the buffer to read from memory
mbed_official 340:28d1f895c6fe 427 * @retval HAL status
mbed_official 340:28d1f895c6fe 428 */
mbed_official 340:28d1f895c6fe 429 HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
mbed_official 340:28d1f895c6fe 430 {
mbed_official 340:28d1f895c6fe 431 /* Process Locked */
mbed_official 340:28d1f895c6fe 432 __HAL_LOCK(hsram);
mbed_official 340:28d1f895c6fe 433
mbed_official 340:28d1f895c6fe 434 /* Update the SRAM controller state */
mbed_official 340:28d1f895c6fe 435 hsram->State = HAL_SRAM_STATE_BUSY;
mbed_official 340:28d1f895c6fe 436
mbed_official 340:28d1f895c6fe 437 /* Read data from memory */
mbed_official 340:28d1f895c6fe 438 for(; BufferSize != 0; BufferSize--)
mbed_official 340:28d1f895c6fe 439 {
mbed_official 340:28d1f895c6fe 440 *pDstBuffer = *(__IO uint32_t *)pAddress;
mbed_official 340:28d1f895c6fe 441 pDstBuffer++;
mbed_official 340:28d1f895c6fe 442 pAddress++;
mbed_official 340:28d1f895c6fe 443 }
mbed_official 340:28d1f895c6fe 444
mbed_official 340:28d1f895c6fe 445 /* Update the SRAM controller state */
mbed_official 340:28d1f895c6fe 446 hsram->State = HAL_SRAM_STATE_READY;
mbed_official 340:28d1f895c6fe 447
mbed_official 340:28d1f895c6fe 448 /* Process unlocked */
mbed_official 340:28d1f895c6fe 449 __HAL_UNLOCK(hsram);
mbed_official 340:28d1f895c6fe 450
mbed_official 340:28d1f895c6fe 451 return HAL_OK;
mbed_official 340:28d1f895c6fe 452 }
mbed_official 340:28d1f895c6fe 453
mbed_official 340:28d1f895c6fe 454 /**
mbed_official 340:28d1f895c6fe 455 * @brief Writes 32-bit buffer to SRAM memory.
mbed_official 340:28d1f895c6fe 456 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
mbed_official 340:28d1f895c6fe 457 * the configuration information for SRAM module.
mbed_official 340:28d1f895c6fe 458 * @param pAddress: Pointer to write start address
mbed_official 340:28d1f895c6fe 459 * @param pSrcBuffer: Pointer to source buffer to write
mbed_official 340:28d1f895c6fe 460 * @param BufferSize: Size of the buffer to write to memory
mbed_official 340:28d1f895c6fe 461 * @retval HAL status
mbed_official 340:28d1f895c6fe 462 */
mbed_official 340:28d1f895c6fe 463 HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
mbed_official 340:28d1f895c6fe 464 {
mbed_official 340:28d1f895c6fe 465 /* Check the SRAM controller state */
mbed_official 340:28d1f895c6fe 466 if(hsram->State == HAL_SRAM_STATE_PROTECTED)
mbed_official 340:28d1f895c6fe 467 {
mbed_official 340:28d1f895c6fe 468 return HAL_ERROR;
mbed_official 340:28d1f895c6fe 469 }
mbed_official 340:28d1f895c6fe 470
mbed_official 340:28d1f895c6fe 471 /* Process Locked */
mbed_official 340:28d1f895c6fe 472 __HAL_LOCK(hsram);
mbed_official 340:28d1f895c6fe 473
mbed_official 340:28d1f895c6fe 474 /* Update the SRAM controller state */
mbed_official 340:28d1f895c6fe 475 hsram->State = HAL_SRAM_STATE_BUSY;
mbed_official 340:28d1f895c6fe 476
mbed_official 340:28d1f895c6fe 477 /* Write data to memory */
mbed_official 340:28d1f895c6fe 478 for(; BufferSize != 0; BufferSize--)
mbed_official 340:28d1f895c6fe 479 {
mbed_official 340:28d1f895c6fe 480 *(__IO uint32_t *)pAddress = *pSrcBuffer;
mbed_official 340:28d1f895c6fe 481 pSrcBuffer++;
mbed_official 340:28d1f895c6fe 482 pAddress++;
mbed_official 340:28d1f895c6fe 483 }
mbed_official 340:28d1f895c6fe 484
mbed_official 340:28d1f895c6fe 485 /* Update the SRAM controller state */
mbed_official 340:28d1f895c6fe 486 hsram->State = HAL_SRAM_STATE_READY;
mbed_official 340:28d1f895c6fe 487
mbed_official 340:28d1f895c6fe 488 /* Process unlocked */
mbed_official 340:28d1f895c6fe 489 __HAL_UNLOCK(hsram);
mbed_official 340:28d1f895c6fe 490
mbed_official 340:28d1f895c6fe 491 return HAL_OK;
mbed_official 340:28d1f895c6fe 492 }
mbed_official 340:28d1f895c6fe 493
mbed_official 340:28d1f895c6fe 494 /**
mbed_official 340:28d1f895c6fe 495 * @brief Reads a Words data from the SRAM memory using DMA transfer.
mbed_official 340:28d1f895c6fe 496 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
mbed_official 340:28d1f895c6fe 497 * the configuration information for SRAM module.
mbed_official 340:28d1f895c6fe 498 * @param pAddress: Pointer to read start address
mbed_official 340:28d1f895c6fe 499 * @param pDstBuffer: Pointer to destination buffer
mbed_official 340:28d1f895c6fe 500 * @param BufferSize: Size of the buffer to read from memory
mbed_official 340:28d1f895c6fe 501 * @retval HAL status
mbed_official 340:28d1f895c6fe 502 */
mbed_official 340:28d1f895c6fe 503 HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
mbed_official 340:28d1f895c6fe 504 {
mbed_official 340:28d1f895c6fe 505 /* Process Locked */
mbed_official 340:28d1f895c6fe 506 __HAL_LOCK(hsram);
mbed_official 340:28d1f895c6fe 507
mbed_official 340:28d1f895c6fe 508 /* Update the SRAM controller state */
mbed_official 340:28d1f895c6fe 509 hsram->State = HAL_SRAM_STATE_BUSY;
mbed_official 340:28d1f895c6fe 510
mbed_official 340:28d1f895c6fe 511 /* Configure DMA user callbacks */
mbed_official 340:28d1f895c6fe 512 hsram->hdma->XferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
mbed_official 340:28d1f895c6fe 513 hsram->hdma->XferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
mbed_official 340:28d1f895c6fe 514
mbed_official 340:28d1f895c6fe 515 /* Enable the DMA Stream */
mbed_official 340:28d1f895c6fe 516 HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize);
mbed_official 340:28d1f895c6fe 517
mbed_official 340:28d1f895c6fe 518 /* Update the SRAM controller state */
mbed_official 340:28d1f895c6fe 519 hsram->State = HAL_SRAM_STATE_READY;
mbed_official 340:28d1f895c6fe 520
mbed_official 340:28d1f895c6fe 521 /* Process unlocked */
mbed_official 340:28d1f895c6fe 522 __HAL_UNLOCK(hsram);
mbed_official 340:28d1f895c6fe 523
mbed_official 340:28d1f895c6fe 524 return HAL_OK;
mbed_official 340:28d1f895c6fe 525 }
mbed_official 340:28d1f895c6fe 526
mbed_official 340:28d1f895c6fe 527 /**
mbed_official 340:28d1f895c6fe 528 * @brief Writes a Words data buffer to SRAM memory using DMA transfer.
mbed_official 340:28d1f895c6fe 529 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
mbed_official 340:28d1f895c6fe 530 * the configuration information for SRAM module.
mbed_official 340:28d1f895c6fe 531 * @param pAddress: Pointer to write start address
mbed_official 340:28d1f895c6fe 532 * @param pSrcBuffer: Pointer to source buffer to write
mbed_official 340:28d1f895c6fe 533 * @param BufferSize: Size of the buffer to write to memory
mbed_official 340:28d1f895c6fe 534 * @retval HAL status
mbed_official 340:28d1f895c6fe 535 */
mbed_official 340:28d1f895c6fe 536 HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
mbed_official 340:28d1f895c6fe 537 {
mbed_official 340:28d1f895c6fe 538 /* Check the SRAM controller state */
mbed_official 340:28d1f895c6fe 539 if(hsram->State == HAL_SRAM_STATE_PROTECTED)
mbed_official 340:28d1f895c6fe 540 {
mbed_official 340:28d1f895c6fe 541 return HAL_ERROR;
mbed_official 340:28d1f895c6fe 542 }
mbed_official 340:28d1f895c6fe 543
mbed_official 340:28d1f895c6fe 544 /* Process Locked */
mbed_official 340:28d1f895c6fe 545 __HAL_LOCK(hsram);
mbed_official 340:28d1f895c6fe 546
mbed_official 340:28d1f895c6fe 547 /* Update the SRAM controller state */
mbed_official 340:28d1f895c6fe 548 hsram->State = HAL_SRAM_STATE_BUSY;
mbed_official 340:28d1f895c6fe 549
mbed_official 340:28d1f895c6fe 550 /* Configure DMA user callbacks */
mbed_official 340:28d1f895c6fe 551 hsram->hdma->XferCpltCallback = HAL_SRAM_DMA_XferCpltCallback;
mbed_official 340:28d1f895c6fe 552 hsram->hdma->XferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
mbed_official 340:28d1f895c6fe 553
mbed_official 340:28d1f895c6fe 554 /* Enable the DMA Stream */
mbed_official 340:28d1f895c6fe 555 HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize);
mbed_official 340:28d1f895c6fe 556
mbed_official 340:28d1f895c6fe 557 /* Update the SRAM controller state */
mbed_official 340:28d1f895c6fe 558 hsram->State = HAL_SRAM_STATE_READY;
mbed_official 340:28d1f895c6fe 559
mbed_official 340:28d1f895c6fe 560 /* Process unlocked */
mbed_official 340:28d1f895c6fe 561 __HAL_UNLOCK(hsram);
mbed_official 340:28d1f895c6fe 562
mbed_official 340:28d1f895c6fe 563 return HAL_OK;
mbed_official 340:28d1f895c6fe 564 }
mbed_official 340:28d1f895c6fe 565
mbed_official 340:28d1f895c6fe 566 /**
mbed_official 340:28d1f895c6fe 567 * @}
mbed_official 340:28d1f895c6fe 568 */
mbed_official 340:28d1f895c6fe 569
mbed_official 340:28d1f895c6fe 570 /** @defgroup SRAM_Group3 Control functions
mbed_official 340:28d1f895c6fe 571 * @brief management functions
mbed_official 340:28d1f895c6fe 572 *
mbed_official 340:28d1f895c6fe 573 @verbatim
mbed_official 340:28d1f895c6fe 574 ==============================================================================
mbed_official 340:28d1f895c6fe 575 ##### SRAM Control functions #####
mbed_official 340:28d1f895c6fe 576 ==============================================================================
mbed_official 340:28d1f895c6fe 577 [..]
mbed_official 340:28d1f895c6fe 578 This subsection provides a set of functions allowing to control dynamically
mbed_official 340:28d1f895c6fe 579 the SRAM interface.
mbed_official 340:28d1f895c6fe 580
mbed_official 340:28d1f895c6fe 581 @endverbatim
mbed_official 340:28d1f895c6fe 582 * @{
mbed_official 340:28d1f895c6fe 583 */
mbed_official 340:28d1f895c6fe 584
mbed_official 340:28d1f895c6fe 585 /**
mbed_official 340:28d1f895c6fe 586 * @brief Enables dynamically SRAM write operation.
mbed_official 340:28d1f895c6fe 587 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
mbed_official 340:28d1f895c6fe 588 * the configuration information for SRAM module.
mbed_official 340:28d1f895c6fe 589 * @retval HAL status
mbed_official 340:28d1f895c6fe 590 */
mbed_official 340:28d1f895c6fe 591 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram)
mbed_official 340:28d1f895c6fe 592 {
mbed_official 340:28d1f895c6fe 593 /* Process Locked */
mbed_official 340:28d1f895c6fe 594 __HAL_LOCK(hsram);
mbed_official 340:28d1f895c6fe 595
mbed_official 340:28d1f895c6fe 596 /* Enable write operation */
mbed_official 340:28d1f895c6fe 597 FMC_NORSRAM_WriteOperation_Enable(hsram->Instance, hsram->Init.NSBank);
mbed_official 340:28d1f895c6fe 598
mbed_official 340:28d1f895c6fe 599 /* Update the SRAM controller state */
mbed_official 340:28d1f895c6fe 600 hsram->State = HAL_SRAM_STATE_READY;
mbed_official 340:28d1f895c6fe 601
mbed_official 340:28d1f895c6fe 602 /* Process unlocked */
mbed_official 340:28d1f895c6fe 603 __HAL_UNLOCK(hsram);
mbed_official 340:28d1f895c6fe 604
mbed_official 340:28d1f895c6fe 605 return HAL_OK;
mbed_official 340:28d1f895c6fe 606 }
mbed_official 340:28d1f895c6fe 607
mbed_official 340:28d1f895c6fe 608 /**
mbed_official 340:28d1f895c6fe 609 * @brief Disables dynamically SRAM write operation.
mbed_official 340:28d1f895c6fe 610 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
mbed_official 340:28d1f895c6fe 611 * the configuration information for SRAM module.
mbed_official 340:28d1f895c6fe 612 * @retval HAL status
mbed_official 340:28d1f895c6fe 613 */
mbed_official 340:28d1f895c6fe 614 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram)
mbed_official 340:28d1f895c6fe 615 {
mbed_official 340:28d1f895c6fe 616 /* Process Locked */
mbed_official 340:28d1f895c6fe 617 __HAL_LOCK(hsram);
mbed_official 340:28d1f895c6fe 618
mbed_official 340:28d1f895c6fe 619 /* Update the SRAM controller state */
mbed_official 340:28d1f895c6fe 620 hsram->State = HAL_SRAM_STATE_BUSY;
mbed_official 340:28d1f895c6fe 621
mbed_official 340:28d1f895c6fe 622 /* Disable write operation */
mbed_official 340:28d1f895c6fe 623 FMC_NORSRAM_WriteOperation_Disable(hsram->Instance, hsram->Init.NSBank);
mbed_official 340:28d1f895c6fe 624
mbed_official 340:28d1f895c6fe 625 /* Update the SRAM controller state */
mbed_official 340:28d1f895c6fe 626 hsram->State = HAL_SRAM_STATE_PROTECTED;
mbed_official 340:28d1f895c6fe 627
mbed_official 340:28d1f895c6fe 628 /* Process unlocked */
mbed_official 340:28d1f895c6fe 629 __HAL_UNLOCK(hsram);
mbed_official 340:28d1f895c6fe 630
mbed_official 340:28d1f895c6fe 631 return HAL_OK;
mbed_official 340:28d1f895c6fe 632 }
mbed_official 340:28d1f895c6fe 633
mbed_official 340:28d1f895c6fe 634 /**
mbed_official 340:28d1f895c6fe 635 * @}
mbed_official 340:28d1f895c6fe 636 */
mbed_official 340:28d1f895c6fe 637
mbed_official 340:28d1f895c6fe 638 /** @defgroup SRAM_Group4 State functions
mbed_official 340:28d1f895c6fe 639 * @brief Peripheral State functions
mbed_official 340:28d1f895c6fe 640 *
mbed_official 340:28d1f895c6fe 641 @verbatim
mbed_official 340:28d1f895c6fe 642 ==============================================================================
mbed_official 340:28d1f895c6fe 643 ##### SRAM State functions #####
mbed_official 340:28d1f895c6fe 644 ==============================================================================
mbed_official 340:28d1f895c6fe 645 [..]
mbed_official 340:28d1f895c6fe 646 This subsection permits to get in run-time the status of the SRAM controller
mbed_official 340:28d1f895c6fe 647 and the data flow.
mbed_official 340:28d1f895c6fe 648
mbed_official 340:28d1f895c6fe 649 @endverbatim
mbed_official 340:28d1f895c6fe 650 * @{
mbed_official 340:28d1f895c6fe 651 */
mbed_official 340:28d1f895c6fe 652
mbed_official 340:28d1f895c6fe 653 /**
mbed_official 340:28d1f895c6fe 654 * @brief Returns the SRAM controller state
mbed_official 340:28d1f895c6fe 655 * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
mbed_official 340:28d1f895c6fe 656 * the configuration information for SRAM module.
mbed_official 340:28d1f895c6fe 657 * @retval HAL state
mbed_official 340:28d1f895c6fe 658 */
mbed_official 340:28d1f895c6fe 659 HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram)
mbed_official 340:28d1f895c6fe 660 {
mbed_official 340:28d1f895c6fe 661 return hsram->State;
mbed_official 340:28d1f895c6fe 662 }
mbed_official 340:28d1f895c6fe 663
mbed_official 340:28d1f895c6fe 664 /**
mbed_official 340:28d1f895c6fe 665 * @}
mbed_official 340:28d1f895c6fe 666 */
mbed_official 340:28d1f895c6fe 667
mbed_official 340:28d1f895c6fe 668 /**
mbed_official 340:28d1f895c6fe 669 * @}
mbed_official 340:28d1f895c6fe 670 */
mbed_official 340:28d1f895c6fe 671 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
mbed_official 340:28d1f895c6fe 672 #endif /* HAL_SRAM_MODULE_ENABLED */
mbed_official 340:28d1f895c6fe 673 /**
mbed_official 340:28d1f895c6fe 674 * @}
mbed_official 340:28d1f895c6fe 675 */
mbed_official 340:28d1f895c6fe 676
mbed_official 340:28d1f895c6fe 677 /**
mbed_official 340:28d1f895c6fe 678 * @}
mbed_official 340:28d1f895c6fe 679 */
mbed_official 340:28d1f895c6fe 680
mbed_official 340:28d1f895c6fe 681 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/