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targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/system_stm32f0xx.c@431:255afbe6270c, 2014-12-09 (annotated)

Committer:: mbed_official
Date:: Tue Dec 09 14:45:08 2014 +0000
Revision:: 431:255afbe6270c
Parent:: 392:2b59412bb664
Child:: 441:d2c15dda23c1

Synchronized with git revision ea49132428ba76f828a3398a05088186c036de90

Full URL: https://github.com/mbedmicro/mbed/commit/ea49132428ba76f828a3398a05088186c036de90/

Fix IAR serial fgets fgetc

Taken from PR #770:

setbuf(_file, NULL), and std::setvbuf(_file,NULL,_IONBF,NULL) should both give an unbuffered stream (the data is directly written to the input buffer). IAR sets a buffer anyway of size 512 bytes for these calls. Calling setvbuff(_file,buf,_IONBF,NULL) with a buffer that is not a NULL pointer sets the buffer to size one. Which means that as soon as a char is read it is written to the real buffer. If people are interested in looking at this further they can look at the files under ARM/src/dlib: fgets.c, fflush.c, xfrpep.c and xfwprep.c

Who changed what in which revision?

User	Revision	Line number	New contents of line
mbed_official	340:28d1f895c6fe	1	/**
mbed_official	340:28d1f895c6fe	2	******************************************************************************
mbed_official	340:28d1f895c6fe	3	* @file system_stm32f0xx.c
mbed_official	340:28d1f895c6fe	4	* @author MCD Application Team
mbed_official	340:28d1f895c6fe	5	* @version V2.1.0
mbed_official	340:28d1f895c6fe	6	* @date 03-Oct-2014
mbed_official	340:28d1f895c6fe	7	* @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Source File.
mbed_official	340:28d1f895c6fe	8	*
mbed_official	340:28d1f895c6fe	9	* 1. This file provides two functions and one global variable to be called from
mbed_official	340:28d1f895c6fe	10	* user application:
mbed_official	340:28d1f895c6fe	11	* - SystemInit(): This function is called at startup just after reset and
mbed_official	340:28d1f895c6fe	12	* before branch to main program. This call is made inside
mbed_official	340:28d1f895c6fe	13	* the "startup_stm32f0xx.s" file.
mbed_official	340:28d1f895c6fe	14	*
mbed_official	340:28d1f895c6fe	15	* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
mbed_official	340:28d1f895c6fe	16	* by the user application to setup the SysTick
mbed_official	340:28d1f895c6fe	17	* timer or configure other parameters.
mbed_official	340:28d1f895c6fe	18	*
mbed_official	340:28d1f895c6fe	19	* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
mbed_official	340:28d1f895c6fe	20	* be called whenever the core clock is changed
mbed_official	340:28d1f895c6fe	21	* during program execution.
mbed_official	340:28d1f895c6fe	22	*
mbed_official	340:28d1f895c6fe	23	* 2. After each device reset the HSI (8 MHz) is used as system clock source.
mbed_official	340:28d1f895c6fe	24	* Then SystemInit() function is called, in "startup_stm32f0xx.s" file, to
mbed_official	340:28d1f895c6fe	25	* configure the system clock before to branch to main program.
mbed_official	340:28d1f895c6fe	26	*
mbed_official	340:28d1f895c6fe	27	* 3. This file configures the system clock as follows:
mbed_official	340:28d1f895c6fe	28	*=============================================================================
mbed_official	340:28d1f895c6fe	29	* System clock source \| 1- PLL_HSE_EXTC \| 3- PLL_HSI
mbed_official	340:28d1f895c6fe	30	* \| (external 8 MHz clock) \| (internal 48 MHz)
mbed_official	340:28d1f895c6fe	31	* \| 2- PLL_HSE_XTAL \|
mbed_official	340:28d1f895c6fe	32	* \| (external 8 MHz xtal) \|
mbed_official	340:28d1f895c6fe	33	*-----------------------------------------------------------------------------
mbed_official	340:28d1f895c6fe	34	* SYSCLK(MHz) \| 48 \| 48
mbed_official	340:28d1f895c6fe	35	*-----------------------------------------------------------------------------
mbed_official	340:28d1f895c6fe	36	* AHBCLK (MHz) \| 48 \| 48
mbed_official	340:28d1f895c6fe	37	*-----------------------------------------------------------------------------
mbed_official	340:28d1f895c6fe	38	* APB1CLK (MHz) \| 48 \| 48
mbed_official	340:28d1f895c6fe	39	*-----------------------------------------------------------------------------
mbed_official	340:28d1f895c6fe	40	* USB capable (48 MHz precise clock) \| YES \| YES
mbed_official	340:28d1f895c6fe	41	*=============================================================================
mbed_official	340:28d1f895c6fe	42	******************************************************************************
mbed_official	340:28d1f895c6fe	43	* @attention
mbed_official	340:28d1f895c6fe	44	*
mbed_official	340:28d1f895c6fe	45	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
mbed_official	340:28d1f895c6fe	46	*
mbed_official	340:28d1f895c6fe	47	* Redistribution and use in source and binary forms, with or without modification,
mbed_official	340:28d1f895c6fe	48	* are permitted provided that the following conditions are met:
mbed_official	340:28d1f895c6fe	49	* 1. Redistributions of source code must retain the above copyright notice,
mbed_official	340:28d1f895c6fe	50	* this list of conditions and the following disclaimer.
mbed_official	340:28d1f895c6fe	51	* 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official	340:28d1f895c6fe	52	* this list of conditions and the following disclaimer in the documentation
mbed_official	340:28d1f895c6fe	53	* and/or other materials provided with the distribution.
mbed_official	340:28d1f895c6fe	54	* 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official	340:28d1f895c6fe	55	* may be used to endorse or promote products derived from this software
mbed_official	340:28d1f895c6fe	56	* without specific prior written permission.
mbed_official	340:28d1f895c6fe	57	*
mbed_official	340:28d1f895c6fe	58	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official	340:28d1f895c6fe	59	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official	340:28d1f895c6fe	60	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official	340:28d1f895c6fe	61	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official	340:28d1f895c6fe	62	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official	340:28d1f895c6fe	63	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official	340:28d1f895c6fe	64	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official	340:28d1f895c6fe	65	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official	340:28d1f895c6fe	66	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official	340:28d1f895c6fe	67	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official	340:28d1f895c6fe	68	*
mbed_official	340:28d1f895c6fe	69	******************************************************************************
mbed_official	340:28d1f895c6fe	70	*/
mbed_official	340:28d1f895c6fe	71
mbed_official	340:28d1f895c6fe	72	/** @addtogroup CMSIS
mbed_official	340:28d1f895c6fe	73	* @{
mbed_official	340:28d1f895c6fe	74	*/
mbed_official	340:28d1f895c6fe	75
mbed_official	340:28d1f895c6fe	76	/** @addtogroup stm32f0xx_system
mbed_official	340:28d1f895c6fe	77	* @{
mbed_official	340:28d1f895c6fe	78	*/
mbed_official	340:28d1f895c6fe	79
mbed_official	340:28d1f895c6fe	80	/** @addtogroup STM32F0xx_System_Private_Includes
mbed_official	340:28d1f895c6fe	81	* @{
mbed_official	340:28d1f895c6fe	82	*/
mbed_official	340:28d1f895c6fe	83
mbed_official	340:28d1f895c6fe	84	#include "stm32f0xx.h"
mbed_official	431:255afbe6270c	85	#include "hal_tick.h"
mbed_official	340:28d1f895c6fe	86
mbed_official	340:28d1f895c6fe	87	/**
mbed_official	340:28d1f895c6fe	88	* @}
mbed_official	340:28d1f895c6fe	89	*/
mbed_official	340:28d1f895c6fe	90
mbed_official	340:28d1f895c6fe	91	/** @addtogroup STM32F0xx_System_Private_TypesDefinitions
mbed_official	340:28d1f895c6fe	92	* @{
mbed_official	340:28d1f895c6fe	93	*/
mbed_official	340:28d1f895c6fe	94
mbed_official	340:28d1f895c6fe	95	/**
mbed_official	340:28d1f895c6fe	96	* @}
mbed_official	340:28d1f895c6fe	97	*/
mbed_official	340:28d1f895c6fe	98
mbed_official	340:28d1f895c6fe	99	/** @addtogroup STM32F0xx_System_Private_Defines
mbed_official	340:28d1f895c6fe	100	* @{
mbed_official	340:28d1f895c6fe	101	*/
mbed_official	340:28d1f895c6fe	102	#if !defined (HSE_VALUE)
mbed_official	340:28d1f895c6fe	103	#define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz.
mbed_official	340:28d1f895c6fe	104	This value can be provided and adapted by the user application. */
mbed_official	340:28d1f895c6fe	105	#endif /* HSE_VALUE */
mbed_official	340:28d1f895c6fe	106
mbed_official	340:28d1f895c6fe	107	#if !defined (HSI_VALUE)
mbed_official	340:28d1f895c6fe	108	#define HSI_VALUE ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz.
mbed_official	340:28d1f895c6fe	109	This value can be provided and adapted by the user application. */
mbed_official	340:28d1f895c6fe	110	#endif /* HSI_VALUE */
mbed_official	340:28d1f895c6fe	111	/**
mbed_official	340:28d1f895c6fe	112	* @}
mbed_official	340:28d1f895c6fe	113	*/
mbed_official	340:28d1f895c6fe	114
mbed_official	340:28d1f895c6fe	115	/** @addtogroup STM32F0xx_System_Private_Macros
mbed_official	340:28d1f895c6fe	116	* @{
mbed_official	340:28d1f895c6fe	117	*/
mbed_official	340:28d1f895c6fe	118
mbed_official	340:28d1f895c6fe	119	/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
mbed_official	340:28d1f895c6fe	120	#define USE_PLL_HSE_EXTC (1) /* Use external clock */
mbed_official	340:28d1f895c6fe	121	#define USE_PLL_HSE_XTAL (1) /* Use external xtal */
mbed_official	340:28d1f895c6fe	122
mbed_official	340:28d1f895c6fe	123	/**
mbed_official	340:28d1f895c6fe	124	* @}
mbed_official	340:28d1f895c6fe	125	*/
mbed_official	340:28d1f895c6fe	126
mbed_official	340:28d1f895c6fe	127	/** @addtogroup STM32F0xx_System_Private_Variables
mbed_official	340:28d1f895c6fe	128	* @{
mbed_official	340:28d1f895c6fe	129	*/
mbed_official	340:28d1f895c6fe	130	/* This variable is updated in three ways:
mbed_official	340:28d1f895c6fe	131	1) by calling CMSIS function SystemCoreClockUpdate()
mbed_official	340:28d1f895c6fe	132	2) by calling HAL API function HAL_RCC_GetHCLKFreq()
mbed_official	340:28d1f895c6fe	133	3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
mbed_official	340:28d1f895c6fe	134	Note: If you use this function to configure the system clock there is no need to
mbed_official	340:28d1f895c6fe	135	call the 2 first functions listed above, since SystemCoreClock variable is
mbed_official	340:28d1f895c6fe	136	updated automatically.
mbed_official	340:28d1f895c6fe	137	*/
mbed_official	340:28d1f895c6fe	138	uint32_t SystemCoreClock = 48000000;
mbed_official	340:28d1f895c6fe	139	const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
mbed_official	340:28d1f895c6fe	140
mbed_official	340:28d1f895c6fe	141	/**
mbed_official	340:28d1f895c6fe	142	* @}
mbed_official	340:28d1f895c6fe	143	*/
mbed_official	340:28d1f895c6fe	144
mbed_official	340:28d1f895c6fe	145	/** @addtogroup STM32F0xx_System_Private_FunctionPrototypes
mbed_official	340:28d1f895c6fe	146	* @{
mbed_official	340:28d1f895c6fe	147	*/
mbed_official	340:28d1f895c6fe	148
mbed_official	340:28d1f895c6fe	149	#if (USE_PLL_HSE_XTAL != 0) \|\| (USE_PLL_HSE_EXTC != 0)
mbed_official	340:28d1f895c6fe	150	uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
mbed_official	340:28d1f895c6fe	151	#endif
mbed_official	340:28d1f895c6fe	152
mbed_official	340:28d1f895c6fe	153	uint8_t SetSysClock_PLL_HSI(void);
mbed_official	340:28d1f895c6fe	154
mbed_official	340:28d1f895c6fe	155	/**
mbed_official	340:28d1f895c6fe	156	* @}
mbed_official	340:28d1f895c6fe	157	*/
mbed_official	340:28d1f895c6fe	158
mbed_official	340:28d1f895c6fe	159	/** @addtogroup STM32F0xx_System_Private_Functions
mbed_official	340:28d1f895c6fe	160	* @{
mbed_official	340:28d1f895c6fe	161	*/
mbed_official	340:28d1f895c6fe	162
mbed_official	431:255afbe6270c	163	extern int NVIC_vtor_remap;
mbed_official	431:255afbe6270c	164
mbed_official	340:28d1f895c6fe	165	/**
mbed_official	340:28d1f895c6fe	166	* @brief Setup the microcontroller system.
mbed_official	340:28d1f895c6fe	167	* Initialize the default HSI clock source, vector table location and the PLL configuration is reset.
mbed_official	340:28d1f895c6fe	168	* @param None
mbed_official	340:28d1f895c6fe	169	* @retval None
mbed_official	340:28d1f895c6fe	170	*/
mbed_official	340:28d1f895c6fe	171	void SystemInit(void)
mbed_official	340:28d1f895c6fe	172	{
mbed_official	340:28d1f895c6fe	173	/* Reset the RCC clock configuration to the default reset state ------------*/
mbed_official	340:28d1f895c6fe	174	/* Set HSION bit */
mbed_official	340:28d1f895c6fe	175	RCC->CR \|= (uint32_t)0x00000001;
mbed_official	340:28d1f895c6fe	176
mbed_official	340:28d1f895c6fe	177	#if defined (STM32F051x8) \|\| defined (STM32F058x8)
mbed_official	340:28d1f895c6fe	178	/* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE and MCOSEL[2:0] bits */
mbed_official	340:28d1f895c6fe	179	RCC->CFGR &= (uint32_t)0xF8FFB80C;
mbed_official	340:28d1f895c6fe	180	#else
mbed_official	340:28d1f895c6fe	181	/* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE, MCOSEL[2:0], MCOPRE[2:0] and PLLNODIV bits */
mbed_official	340:28d1f895c6fe	182	RCC->CFGR &= (uint32_t)0x08FFB80C;
mbed_official	340:28d1f895c6fe	183	#endif /* STM32F051x8 or STM32F058x8 */
mbed_official	340:28d1f895c6fe	184
mbed_official	340:28d1f895c6fe	185	/* Reset HSEON, CSSON and PLLON bits */
mbed_official	340:28d1f895c6fe	186	RCC->CR &= (uint32_t)0xFEF6FFFF;
mbed_official	340:28d1f895c6fe	187
mbed_official	340:28d1f895c6fe	188	/* Reset HSEBYP bit */
mbed_official	340:28d1f895c6fe	189	RCC->CR &= (uint32_t)0xFFFBFFFF;
mbed_official	340:28d1f895c6fe	190
mbed_official	340:28d1f895c6fe	191	/* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
mbed_official	340:28d1f895c6fe	192	RCC->CFGR &= (uint32_t)0xFFC0FFFF;
mbed_official	340:28d1f895c6fe	193
mbed_official	340:28d1f895c6fe	194	/* Reset PREDIV[3:0] bits */
mbed_official	340:28d1f895c6fe	195	RCC->CFGR2 &= (uint32_t)0xFFFFFFF0;
mbed_official	340:28d1f895c6fe	196
mbed_official	340:28d1f895c6fe	197	#if defined (STM32F071xB) \|\| defined (STM32F072xB) \|\| defined (STM32F078xB)
mbed_official	340:28d1f895c6fe	198	/* Reset USART2SW[1:0] USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
mbed_official	340:28d1f895c6fe	199	RCC->CFGR3 &= (uint32_t)0xFFFCFE2C;
mbed_official	340:28d1f895c6fe	200	#elif defined (STM32F091xC) \|\| defined (STM32F098xx)
mbed_official	340:28d1f895c6fe	201	/* Reset USART3SW[1:0], USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW bits */
mbed_official	340:28d1f895c6fe	202	RCC->CFGR3 &= (uint32_t)0xFFF0FFAC;
mbed_official	340:28d1f895c6fe	203	#else
mbed_official	340:28d1f895c6fe	204	/* Reset USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
mbed_official	340:28d1f895c6fe	205	RCC->CFGR3 &= (uint32_t)0xFFFFFE2C;
mbed_official	340:28d1f895c6fe	206	#endif
mbed_official	340:28d1f895c6fe	207
mbed_official	340:28d1f895c6fe	208	/* Reset HSI14 bit */
mbed_official	340:28d1f895c6fe	209	RCC->CR2 &= (uint32_t)0xFFFFFFFE;
mbed_official	340:28d1f895c6fe	210
mbed_official	340:28d1f895c6fe	211	/* Disable all interrupts */
mbed_official	340:28d1f895c6fe	212	RCC->CIR = 0x00000000;
mbed_official	340:28d1f895c6fe	213
mbed_official	340:28d1f895c6fe	214	/* Configure the Cube driver */
mbed_official	431:255afbe6270c	215	SystemCoreClock = 8000000; // At this stage the HSI is used as system clock
mbed_official	431:255afbe6270c	216	NVIC_vtor_remap = 0; // Because it is not cleared the first time we enter in NVIC_SetVector()
mbed_official	340:28d1f895c6fe	217	HAL_Init();
mbed_official	340:28d1f895c6fe	218
mbed_official	340:28d1f895c6fe	219	/* Configure the System clock source, PLL Multiplier and Divider factors,
mbed_official	340:28d1f895c6fe	220	AHB/APBx prescalers and Flash settings */
mbed_official	340:28d1f895c6fe	221	SetSysClock();
mbed_official	431:255afbe6270c	222
mbed_official	431:255afbe6270c	223	/* Reset the timer to avoid issues after the RAM initialization */
mbed_official	431:255afbe6270c	224	TIM_MST_RESET_ON;
mbed_official	431:255afbe6270c	225	TIM_MST_RESET_OFF;
mbed_official	340:28d1f895c6fe	226	}
mbed_official	340:28d1f895c6fe	227
mbed_official	340:28d1f895c6fe	228	/**
mbed_official	340:28d1f895c6fe	229	* @brief Update SystemCoreClock variable according to Clock Register Values.
mbed_official	340:28d1f895c6fe	230	* The SystemCoreClock variable contains the core clock (HCLK), it can
mbed_official	340:28d1f895c6fe	231	* be used by the user application to setup the SysTick timer or configure
mbed_official	340:28d1f895c6fe	232	* other parameters.
mbed_official	340:28d1f895c6fe	233	*
mbed_official	340:28d1f895c6fe	234	* @note Each time the core clock (HCLK) changes, this function must be called
mbed_official	340:28d1f895c6fe	235	* to update SystemCoreClock variable value. Otherwise, any configuration
mbed_official	340:28d1f895c6fe	236	* based on this variable will be incorrect.
mbed_official	340:28d1f895c6fe	237	*
mbed_official	340:28d1f895c6fe	238	* @note - The system frequency computed by this function is not the real
mbed_official	340:28d1f895c6fe	239	* frequency in the chip. It is calculated based on the predefined
mbed_official	340:28d1f895c6fe	240	* constant and the selected clock source:
mbed_official	340:28d1f895c6fe	241	*
mbed_official	340:28d1f895c6fe	242	* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
mbed_official	340:28d1f895c6fe	243	*
mbed_official	340:28d1f895c6fe	244	* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
mbed_official	340:28d1f895c6fe	245	*
mbed_official	340:28d1f895c6fe	246	* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
mbed_official	340:28d1f895c6fe	247	* or HSI_VALUE(*) multiplied/divided by the PLL factors.
mbed_official	340:28d1f895c6fe	248	*
mbed_official	340:28d1f895c6fe	249	* (*) HSI_VALUE is a constant defined in stm32f0xx_hal.h file (default value
mbed_official	340:28d1f895c6fe	250	* 8 MHz) but the real value may vary depending on the variations
mbed_official	340:28d1f895c6fe	251	* in voltage and temperature.
mbed_official	340:28d1f895c6fe	252	*
mbed_official	340:28d1f895c6fe	253	* (**) HSE_VALUE is a constant defined in stm32f0xx_hal.h file (default value
mbed_official	340:28d1f895c6fe	254	* 8 MHz), user has to ensure that HSE_VALUE is same as the real
mbed_official	340:28d1f895c6fe	255	* frequency of the crystal used. Otherwise, this function may
mbed_official	340:28d1f895c6fe	256	* have wrong result.
mbed_official	340:28d1f895c6fe	257	*
mbed_official	340:28d1f895c6fe	258	* - The result of this function could be not correct when using fractional
mbed_official	340:28d1f895c6fe	259	* value for HSE crystal.
mbed_official	340:28d1f895c6fe	260	*
mbed_official	340:28d1f895c6fe	261	* @param None
mbed_official	340:28d1f895c6fe	262	* @retval None
mbed_official	340:28d1f895c6fe	263	*/
mbed_official	340:28d1f895c6fe	264	void SystemCoreClockUpdate (void)
mbed_official	340:28d1f895c6fe	265	{
mbed_official	340:28d1f895c6fe	266	uint32_t tmp = 0, pllmull = 0, pllsource = 0, predivfactor = 0;
mbed_official	340:28d1f895c6fe	267
mbed_official	340:28d1f895c6fe	268	/* Get SYSCLK source -------------------------------------------------------*/
mbed_official	340:28d1f895c6fe	269	tmp = RCC->CFGR & RCC_CFGR_SWS;
mbed_official	340:28d1f895c6fe	270
mbed_official	340:28d1f895c6fe	271	switch (tmp)
mbed_official	340:28d1f895c6fe	272	{
mbed_official	340:28d1f895c6fe	273	case RCC_CFGR_SWS_HSI: /* HSI used as system clock */
mbed_official	340:28d1f895c6fe	274	SystemCoreClock = HSI_VALUE;
mbed_official	340:28d1f895c6fe	275	break;
mbed_official	340:28d1f895c6fe	276	case RCC_CFGR_SWS_HSE: /* HSE used as system clock */
mbed_official	340:28d1f895c6fe	277	SystemCoreClock = HSE_VALUE;
mbed_official	340:28d1f895c6fe	278	break;
mbed_official	340:28d1f895c6fe	279	case RCC_CFGR_SWS_PLL: /* PLL used as system clock */
mbed_official	340:28d1f895c6fe	280	/* Get PLL clock source and multiplication factor ----------------------*/
mbed_official	340:28d1f895c6fe	281	pllmull = RCC->CFGR & RCC_CFGR_PLLMUL;
mbed_official	340:28d1f895c6fe	282	pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
mbed_official	340:28d1f895c6fe	283	pllmull = ( pllmull >> 18) + 2;
mbed_official	340:28d1f895c6fe	284	predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
mbed_official	340:28d1f895c6fe	285
mbed_official	340:28d1f895c6fe	286	if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV)
mbed_official	340:28d1f895c6fe	287	{
mbed_official	340:28d1f895c6fe	288	/* HSE used as PLL clock source : SystemCoreClock = HSE/PREDIV * PLLMUL */
mbed_official	340:28d1f895c6fe	289	SystemCoreClock = (HSE_VALUE/predivfactor) * pllmull;
mbed_official	340:28d1f895c6fe	290	}
mbed_official	340:28d1f895c6fe	291	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	340:28d1f895c6fe	292	else if (pllsource == RCC_CFGR_PLLSRC_HSI48_PREDIV)
mbed_official	340:28d1f895c6fe	293	{
mbed_official	340:28d1f895c6fe	294	/* HSI48 used as PLL clock source : SystemCoreClock = HSI48/PREDIV * PLLMUL */
mbed_official	340:28d1f895c6fe	295	SystemCoreClock = (HSI48_VALUE/predivfactor) * pllmull;
mbed_official	340:28d1f895c6fe	296	}
mbed_official	340:28d1f895c6fe	297	#endif /* STM32F042x6 \|\| STM32F048xx \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F091xC \|\| STM32F098xx */
mbed_official	340:28d1f895c6fe	298	else
mbed_official	340:28d1f895c6fe	299	{
mbed_official	340:28d1f895c6fe	300	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F091xC) \|\| defined(STM32F098xx)
mbed_official	340:28d1f895c6fe	301	/* HSI used as PLL clock source : SystemCoreClock = HSI/PREDIV * PLLMUL */
mbed_official	340:28d1f895c6fe	302	SystemCoreClock = (HSI_VALUE/predivfactor) * pllmull;
mbed_official	340:28d1f895c6fe	303	#else
mbed_official	340:28d1f895c6fe	304	/* HSI used as PLL clock source : SystemCoreClock = HSI/2 * PLLMUL */
mbed_official	340:28d1f895c6fe	305	SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
mbed_official	340:28d1f895c6fe	306	#endif /* STM32F042x6 \|\| STM32F048xx \|\| STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F091xC \|\| STM32F098xx */
mbed_official	340:28d1f895c6fe	307	}
mbed_official	340:28d1f895c6fe	308	break;
mbed_official	340:28d1f895c6fe	309	default: /* HSI used as system clock */
mbed_official	340:28d1f895c6fe	310	SystemCoreClock = HSI_VALUE;
mbed_official	340:28d1f895c6fe	311	break;
mbed_official	340:28d1f895c6fe	312	}
mbed_official	340:28d1f895c6fe	313	/* Compute HCLK clock frequency ----------------*/
mbed_official	340:28d1f895c6fe	314	/* Get HCLK prescaler */
mbed_official	340:28d1f895c6fe	315	tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
mbed_official	340:28d1f895c6fe	316	/* HCLK clock frequency */
mbed_official	340:28d1f895c6fe	317	SystemCoreClock >>= tmp;
mbed_official	340:28d1f895c6fe	318	}
mbed_official	340:28d1f895c6fe	319
mbed_official	340:28d1f895c6fe	320	/**
mbed_official	340:28d1f895c6fe	321	* @brief Configures the System clock source, PLL Multiplier and Divider factors,
mbed_official	340:28d1f895c6fe	322	* AHB/APBx prescalers and Flash settings
mbed_official	340:28d1f895c6fe	323	* @note This function should be called only once the RCC clock configuration
mbed_official	340:28d1f895c6fe	324	* is reset to the default reset state (done in SystemInit() function).
mbed_official	340:28d1f895c6fe	325	* @param None
mbed_official	340:28d1f895c6fe	326	* @retval None
mbed_official	340:28d1f895c6fe	327	*/
mbed_official	340:28d1f895c6fe	328	void SetSysClock(void)
mbed_official	340:28d1f895c6fe	329	{
mbed_official	340:28d1f895c6fe	330	/* 1- Try to start with HSE and external clock */
mbed_official	340:28d1f895c6fe	331	#if USE_PLL_HSE_EXTC != 0
mbed_official	340:28d1f895c6fe	332	if (SetSysClock_PLL_HSE(1) == 0)
mbed_official	340:28d1f895c6fe	333	#endif
mbed_official	340:28d1f895c6fe	334	{
mbed_official	340:28d1f895c6fe	335	/* 2- If fail try to start with HSE and external xtal */
mbed_official	340:28d1f895c6fe	336	#if USE_PLL_HSE_XTAL != 0
mbed_official	340:28d1f895c6fe	337	if (SetSysClock_PLL_HSE(0) == 0)
mbed_official	340:28d1f895c6fe	338	#endif
mbed_official	340:28d1f895c6fe	339	{
mbed_official	340:28d1f895c6fe	340	/* 3- If fail start with HSI clock */
mbed_official	340:28d1f895c6fe	341	if (SetSysClock_PLL_HSI() == 0)
mbed_official	340:28d1f895c6fe	342	{
mbed_official	340:28d1f895c6fe	343	while(1)
mbed_official	340:28d1f895c6fe	344	{
mbed_official	340:28d1f895c6fe	345	// [TODO] Put something here to tell the user that a problem occured...
mbed_official	340:28d1f895c6fe	346	}
mbed_official	340:28d1f895c6fe	347	}
mbed_official	340:28d1f895c6fe	348	}
mbed_official	340:28d1f895c6fe	349	}
mbed_official	340:28d1f895c6fe	350
mbed_official	340:28d1f895c6fe	351	// Output clock on MCO pin(PA8) for debugging purpose
mbed_official	340:28d1f895c6fe	352	//HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_SYSCLK, RCC_MCO_DIV1); // 48 MHz
mbed_official	340:28d1f895c6fe	353	}
mbed_official	340:28d1f895c6fe	354
mbed_official	340:28d1f895c6fe	355	#if (USE_PLL_HSE_XTAL != 0) \|\| (USE_PLL_HSE_EXTC != 0)
mbed_official	340:28d1f895c6fe	356	/******************************************************************************/
mbed_official	340:28d1f895c6fe	357	/* PLL (clocked by HSE) used as System clock source */
mbed_official	340:28d1f895c6fe	358	/******************************************************************************/
mbed_official	340:28d1f895c6fe	359	uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
mbed_official	340:28d1f895c6fe	360	{
mbed_official	340:28d1f895c6fe	361	RCC_ClkInitTypeDef RCC_ClkInitStruct;
mbed_official	340:28d1f895c6fe	362	RCC_OscInitTypeDef RCC_OscInitStruct;
mbed_official	340:28d1f895c6fe	363
mbed_official	340:28d1f895c6fe	364	// Select HSE oscillator as PLL source
mbed_official	340:28d1f895c6fe	365	RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE \| RCC_OSCILLATORTYPE_HSI48;
mbed_official	340:28d1f895c6fe	366	if (bypass == 0) {
mbed_official	340:28d1f895c6fe	367	RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT
mbed_official	340:28d1f895c6fe	368	} else {
mbed_official	340:28d1f895c6fe	369	RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN only
mbed_official	340:28d1f895c6fe	370	}
mbed_official	340:28d1f895c6fe	371	RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
mbed_official	340:28d1f895c6fe	372	RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
mbed_official	340:28d1f895c6fe	373	RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
mbed_official	340:28d1f895c6fe	374	RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV2;
mbed_official	340:28d1f895c6fe	375	RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL12;
mbed_official	340:28d1f895c6fe	376	if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
mbed_official	340:28d1f895c6fe	377	return 0; // FAIL
mbed_official	340:28d1f895c6fe	378	}
mbed_official	340:28d1f895c6fe	379
mbed_official	340:28d1f895c6fe	380	// Select PLL as system clock source and configure the HCLK and PCLK1 clocks dividers
mbed_official	340:28d1f895c6fe	381	RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK \| RCC_CLOCKTYPE_HCLK \| RCC_CLOCKTYPE_PCLK1);
mbed_official	340:28d1f895c6fe	382	RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 48 MHz
mbed_official	340:28d1f895c6fe	383	RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 48 MHz
mbed_official	340:28d1f895c6fe	384	RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 48 MHz
mbed_official	340:28d1f895c6fe	385	if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
mbed_official	340:28d1f895c6fe	386	return 0; // FAIL
mbed_official	340:28d1f895c6fe	387	}
mbed_official	340:28d1f895c6fe	388
mbed_official	340:28d1f895c6fe	389	// Output clock on MCO pin(PA8) for debugging purpose
mbed_official	340:28d1f895c6fe	390	//if (bypass == 0)
mbed_official	340:28d1f895c6fe	391	// HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV2); // 4 MHz with xtal
mbed_official	340:28d1f895c6fe	392	//else
mbed_official	340:28d1f895c6fe	393	// HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV4); // 2 MHz with ST-Link MCO
mbed_official	340:28d1f895c6fe	394
mbed_official	340:28d1f895c6fe	395	return 1; // OK
mbed_official	340:28d1f895c6fe	396	}
mbed_official	340:28d1f895c6fe	397	#endif
mbed_official	340:28d1f895c6fe	398
mbed_official	340:28d1f895c6fe	399	/******************************************************************************/
mbed_official	340:28d1f895c6fe	400	/* PLL (clocked by HSI) used as System clock source */
mbed_official	340:28d1f895c6fe	401	/******************************************************************************/
mbed_official	340:28d1f895c6fe	402	uint8_t SetSysClock_PLL_HSI(void)
mbed_official	340:28d1f895c6fe	403	{
mbed_official	340:28d1f895c6fe	404	RCC_ClkInitTypeDef RCC_ClkInitStruct;
mbed_official	340:28d1f895c6fe	405	RCC_OscInitTypeDef RCC_OscInitStruct;
mbed_official	340:28d1f895c6fe	406
mbed_official	340:28d1f895c6fe	407	// Select HSI48 oscillator as PLL source
mbed_official	340:28d1f895c6fe	408	RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48;
mbed_official	340:28d1f895c6fe	409	RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
mbed_official	340:28d1f895c6fe	410	RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
mbed_official	340:28d1f895c6fe	411	RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI48;
mbed_official	340:28d1f895c6fe	412	RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV2;
mbed_official	340:28d1f895c6fe	413	RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL2;
mbed_official	340:28d1f895c6fe	414	if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
mbed_official	340:28d1f895c6fe	415	return 0; // FAIL
mbed_official	340:28d1f895c6fe	416	}
mbed_official	340:28d1f895c6fe	417
mbed_official	340:28d1f895c6fe	418	// Select PLL as system clock source and configure the HCLK and PCLK1 clocks dividers
mbed_official	340:28d1f895c6fe	419	RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK \| RCC_CLOCKTYPE_HCLK \| RCC_CLOCKTYPE_PCLK1);
mbed_official	340:28d1f895c6fe	420	RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 48 MHz
mbed_official	340:28d1f895c6fe	421	RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 48 MHz
mbed_official	340:28d1f895c6fe	422	RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 48 MHz
mbed_official	340:28d1f895c6fe	423	if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
mbed_official	340:28d1f895c6fe	424	return 0; // FAIL
mbed_official	340:28d1f895c6fe	425	}
mbed_official	340:28d1f895c6fe	426
mbed_official	340:28d1f895c6fe	427	// Output clock on MCO1 pin(PA8) for debugging purpose
mbed_official	340:28d1f895c6fe	428	//HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSI48, RCC_MCO_DIV1); // 48 MHz
mbed_official	340:28d1f895c6fe	429
mbed_official	340:28d1f895c6fe	430	return 1; // OK
mbed_official	340:28d1f895c6fe	431	}
mbed_official	340:28d1f895c6fe	432
mbed_official	340:28d1f895c6fe	433	/**
mbed_official	340:28d1f895c6fe	434	* @}
mbed_official	340:28d1f895c6fe	435	*/
mbed_official	340:28d1f895c6fe	436
mbed_official	340:28d1f895c6fe	437	/**
mbed_official	340:28d1f895c6fe	438	* @}
mbed_official	340:28d1f895c6fe	439	*/
mbed_official	340:28d1f895c6fe	440
mbed_official	340:28d1f895c6fe	441	/**
mbed_official	340:28d1f895c6fe	442	* @}
mbed_official	340:28d1f895c6fe	443	*/
mbed_official	340:28d1f895c6fe	444
mbed_official	340:28d1f895c6fe	445	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/
mbed_official	340:28d1f895c6fe	446