mbed library sources. Supersedes mbed-src.
Dependents: Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more
targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_rmu.c@179:b0033dcd6934, 2017-12-07 (annotated)
- Committer:
- AnnaBridge
- Date:
- Thu Dec 07 14:01:42 2017 +0000
- Revision:
- 179:b0033dcd6934
- Parent:
- 161:2cc1468da177
mbed-dev library. Release version 157
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
<> | 144:ef7eb2e8f9f7 | 1 | /***************************************************************************//** |
<> | 144:ef7eb2e8f9f7 | 2 | * @file em_rmu.c |
<> | 144:ef7eb2e8f9f7 | 3 | * @brief Reset Management Unit (RMU) peripheral module peripheral API |
<> | 144:ef7eb2e8f9f7 | 4 | * |
AnnaBridge | 179:b0033dcd6934 | 5 | * @version 5.3.3 |
<> | 144:ef7eb2e8f9f7 | 6 | ******************************************************************************* |
AnnaBridge | 179:b0033dcd6934 | 7 | * # License |
<> | 150:02e0a0aed4ec | 8 | * <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b> |
<> | 144:ef7eb2e8f9f7 | 9 | ******************************************************************************* |
<> | 144:ef7eb2e8f9f7 | 10 | * |
<> | 144:ef7eb2e8f9f7 | 11 | * Permission is granted to anyone to use this software for any purpose, |
<> | 144:ef7eb2e8f9f7 | 12 | * including commercial applications, and to alter it and redistribute it |
<> | 144:ef7eb2e8f9f7 | 13 | * freely, subject to the following restrictions: |
<> | 144:ef7eb2e8f9f7 | 14 | * |
<> | 144:ef7eb2e8f9f7 | 15 | * 1. The origin of this software must not be misrepresented; you must not |
<> | 144:ef7eb2e8f9f7 | 16 | * claim that you wrote the original software. |
<> | 144:ef7eb2e8f9f7 | 17 | * 2. Altered source versions must be plainly marked as such, and must not be |
<> | 144:ef7eb2e8f9f7 | 18 | * misrepresented as being the original software. |
<> | 144:ef7eb2e8f9f7 | 19 | * 3. This notice may not be removed or altered from any source distribution. |
<> | 144:ef7eb2e8f9f7 | 20 | * |
<> | 144:ef7eb2e8f9f7 | 21 | * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no |
<> | 144:ef7eb2e8f9f7 | 22 | * obligation to support this Software. Silicon Labs is providing the |
<> | 144:ef7eb2e8f9f7 | 23 | * Software "AS IS", with no express or implied warranties of any kind, |
<> | 144:ef7eb2e8f9f7 | 24 | * including, but not limited to, any implied warranties of merchantability |
<> | 144:ef7eb2e8f9f7 | 25 | * or fitness for any particular purpose or warranties against infringement |
<> | 144:ef7eb2e8f9f7 | 26 | * of any proprietary rights of a third party. |
<> | 144:ef7eb2e8f9f7 | 27 | * |
<> | 144:ef7eb2e8f9f7 | 28 | * Silicon Labs will not be liable for any consequential, incidental, or |
<> | 144:ef7eb2e8f9f7 | 29 | * special damages, or any other relief, or for any claim by any third party, |
<> | 144:ef7eb2e8f9f7 | 30 | * arising from your use of this Software. |
<> | 144:ef7eb2e8f9f7 | 31 | * |
<> | 144:ef7eb2e8f9f7 | 32 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 33 | |
<> | 144:ef7eb2e8f9f7 | 34 | #include "em_rmu.h" |
<> | 144:ef7eb2e8f9f7 | 35 | #if defined(RMU_COUNT) && (RMU_COUNT > 0) |
<> | 144:ef7eb2e8f9f7 | 36 | |
<> | 144:ef7eb2e8f9f7 | 37 | #include "em_common.h" |
<> | 144:ef7eb2e8f9f7 | 38 | #include "em_emu.h" |
<> | 144:ef7eb2e8f9f7 | 39 | #include "em_bus.h" |
<> | 144:ef7eb2e8f9f7 | 40 | |
<> | 144:ef7eb2e8f9f7 | 41 | /***************************************************************************//** |
<> | 150:02e0a0aed4ec | 42 | * @addtogroup emlib |
<> | 144:ef7eb2e8f9f7 | 43 | * @{ |
<> | 144:ef7eb2e8f9f7 | 44 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 45 | |
<> | 144:ef7eb2e8f9f7 | 46 | /***************************************************************************//** |
<> | 144:ef7eb2e8f9f7 | 47 | * @addtogroup RMU |
<> | 144:ef7eb2e8f9f7 | 48 | * @brief Reset Management Unit (RMU) Peripheral API |
<> | 150:02e0a0aed4ec | 49 | * @details |
<> | 150:02e0a0aed4ec | 50 | * This module contains functions to control the RMU peripheral of Silicon |
<> | 150:02e0a0aed4ec | 51 | * Labs 32-bit MCUs and SoCs. The RMU ensures correct reset operation. It is |
<> | 150:02e0a0aed4ec | 52 | * responsible for connecting the different reset sources to the reset lines of |
<> | 150:02e0a0aed4ec | 53 | * the MCU or SoC. |
<> | 144:ef7eb2e8f9f7 | 54 | * @{ |
<> | 144:ef7eb2e8f9f7 | 55 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 56 | |
<> | 144:ef7eb2e8f9f7 | 57 | /******************************************************************************* |
<> | 144:ef7eb2e8f9f7 | 58 | ***************************** DEFINES ********************************* |
<> | 144:ef7eb2e8f9f7 | 59 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 60 | |
<> | 144:ef7eb2e8f9f7 | 61 | /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ |
<> | 144:ef7eb2e8f9f7 | 62 | |
<> | 150:02e0a0aed4ec | 63 | /* Reset cause zero and "don't care" bit definitions (XMASKs). |
<> | 150:02e0a0aed4ec | 64 | A XMASK 1 bit marks a bit that must be zero in RMU_RSTCAUSE. A 0 in XMASK |
<> | 150:02e0a0aed4ec | 65 | is a "don't care" bit in RMU_RSTCAUSE if also 0 in resetCauseMask |
<> | 150:02e0a0aed4ec | 66 | in @ref RMU_ResetCauseMasks_Typedef. */ |
<> | 150:02e0a0aed4ec | 67 | |
<> | 150:02e0a0aed4ec | 68 | /* EFM32G */ |
<> | 144:ef7eb2e8f9f7 | 69 | #if (_RMU_RSTCAUSE_MASK == 0x0000007FUL) |
<> | 150:02e0a0aed4ec | 70 | #define RMU_RSTCAUSE_PORST_XMASK 0x00000000UL /** 0000000000000000 < Power On Reset */ |
<> | 150:02e0a0aed4ec | 71 | #define RMU_RSTCAUSE_BODUNREGRST_XMASK 0x00000001UL /** 0000000000000001 < Brown Out Detector Unregulated Domain Reset */ |
<> | 150:02e0a0aed4ec | 72 | #define RMU_RSTCAUSE_BODREGRST_XMASK 0x0000001BUL /** 0000000000011011 < Brown Out Detector Regulated Domain Reset */ |
<> | 150:02e0a0aed4ec | 73 | #define RMU_RSTCAUSE_EXTRST_XMASK 0x00000003UL /** 0000000000000011 < External Pin Reset */ |
<> | 150:02e0a0aed4ec | 74 | #define RMU_RSTCAUSE_WDOGRST_XMASK 0x00000003UL /** 0000000000000011 < Watchdog Reset */ |
<> | 150:02e0a0aed4ec | 75 | #define RMU_RSTCAUSE_LOCKUPRST_XMASK 0x0000001FUL /** 0000000000011111 < LOCKUP Reset */ |
<> | 150:02e0a0aed4ec | 76 | #define RMU_RSTCAUSE_SYSREQRST_XMASK 0x0000001FUL /** 0000000000011111 < System Request Reset */ |
<> | 150:02e0a0aed4ec | 77 | #define NUM_RSTCAUSES 7 |
<> | 144:ef7eb2e8f9f7 | 78 | |
<> | 150:02e0a0aed4ec | 79 | /* EFM32TG, EFM32HG, EZR32HG, EFM32ZG */ |
<> | 144:ef7eb2e8f9f7 | 80 | #elif (_RMU_RSTCAUSE_MASK == 0x000007FFUL) |
<> | 150:02e0a0aed4ec | 81 | #define RMU_RSTCAUSE_PORST_XMASK 0x00000000UL /** 0000000000000000 < Power On Reset */ |
<> | 150:02e0a0aed4ec | 82 | #define RMU_RSTCAUSE_BODUNREGRST_XMASK 0x00000081UL /** 0000000010000001 < Brown Out Detector Unregulated Domain Reset */ |
<> | 150:02e0a0aed4ec | 83 | #define RMU_RSTCAUSE_BODREGRST_XMASK 0x00000091UL /** 0000000010010001 < Brown Out Detector Regulated Domain Reset */ |
<> | 150:02e0a0aed4ec | 84 | #define RMU_RSTCAUSE_EXTRST_XMASK 0x00000001UL /** 0000000000000001 < External Pin Reset */ |
<> | 150:02e0a0aed4ec | 85 | #define RMU_RSTCAUSE_WDOGRST_XMASK 0x00000003UL /** 0000000000000011 < Watchdog Reset */ |
<> | 150:02e0a0aed4ec | 86 | #define RMU_RSTCAUSE_LOCKUPRST_XMASK 0x0000EFDFUL /** 1110111111011111 < LOCKUP Reset */ |
<> | 150:02e0a0aed4ec | 87 | #define RMU_RSTCAUSE_SYSREQRST_XMASK 0x0000EF9FUL /** 1110111110011111 < System Request Reset */ |
<> | 150:02e0a0aed4ec | 88 | #define RMU_RSTCAUSE_EM4RST_XMASK 0x00000719UL /** 0000011100011001 < EM4 Reset */ |
<> | 150:02e0a0aed4ec | 89 | #define RMU_RSTCAUSE_EM4WURST_XMASK 0x00000619UL /** 0000011000011001 < EM4 Wake-up Reset */ |
<> | 150:02e0a0aed4ec | 90 | #define RMU_RSTCAUSE_BODAVDD0_XMASK 0x0000041FUL /** 0000010000011111 < AVDD0 Bod Reset. */ |
<> | 150:02e0a0aed4ec | 91 | #define RMU_RSTCAUSE_BODAVDD1_XMASK 0x0000021FUL /** 0000001000011111 < AVDD1 Bod Reset. */ |
<> | 150:02e0a0aed4ec | 92 | #define NUM_RSTCAUSES 11 |
<> | 144:ef7eb2e8f9f7 | 93 | |
<> | 150:02e0a0aed4ec | 94 | /* EFM32GG, EFM32LG, EZR32LG, EFM32WG, EZR32WG */ |
<> | 144:ef7eb2e8f9f7 | 95 | #elif (_RMU_RSTCAUSE_MASK == 0x0000FFFFUL) |
<> | 150:02e0a0aed4ec | 96 | #define RMU_RSTCAUSE_PORST_XMASK 0x00000000UL /** 0000000000000000 < Power On Reset */ |
<> | 150:02e0a0aed4ec | 97 | #define RMU_RSTCAUSE_BODUNREGRST_XMASK 0x00000081UL /** 0000000010000001 < Brown Out Detector Unregulated Domain Reset */ |
<> | 150:02e0a0aed4ec | 98 | #define RMU_RSTCAUSE_BODREGRST_XMASK 0x00000091UL /** 0000000010010001 < Brown Out Detector Regulated Domain Reset */ |
<> | 150:02e0a0aed4ec | 99 | #define RMU_RSTCAUSE_EXTRST_XMASK 0x00000001UL /** 0000000000000001 < External Pin Reset */ |
<> | 150:02e0a0aed4ec | 100 | #define RMU_RSTCAUSE_WDOGRST_XMASK 0x00000003UL /** 0000000000000011 < Watchdog Reset */ |
<> | 150:02e0a0aed4ec | 101 | #define RMU_RSTCAUSE_LOCKUPRST_XMASK 0x0000EFDFUL /** 1110111111011111 < LOCKUP Reset */ |
<> | 150:02e0a0aed4ec | 102 | #define RMU_RSTCAUSE_SYSREQRST_XMASK 0x0000EF9FUL /** 1110111110011111 < System Request Reset */ |
<> | 150:02e0a0aed4ec | 103 | #define RMU_RSTCAUSE_EM4RST_XMASK 0x00000719UL /** 0000011100011001 < EM4 Reset */ |
<> | 150:02e0a0aed4ec | 104 | #define RMU_RSTCAUSE_EM4WURST_XMASK 0x00000619UL /** 0000011000011001 < EM4 Wake-up Reset */ |
<> | 150:02e0a0aed4ec | 105 | #define RMU_RSTCAUSE_BODAVDD0_XMASK 0x0000041FUL /** 0000010000011111 < AVDD0 Bod Reset */ |
<> | 150:02e0a0aed4ec | 106 | #define RMU_RSTCAUSE_BODAVDD1_XMASK 0x0000021FUL /** 0000001000011111 < AVDD1 Bod Reset */ |
<> | 150:02e0a0aed4ec | 107 | #define RMU_RSTCAUSE_BUBODVDDDREG_XMASK 0x00000001UL /** 0000000000000001 < Backup Brown Out Detector, VDD_DREG */ |
<> | 150:02e0a0aed4ec | 108 | #define RMU_RSTCAUSE_BUBODBUVIN_XMASK 0x00000001UL /** 0000000000000001 < Backup Brown Out Detector, BU_VIN */ |
<> | 150:02e0a0aed4ec | 109 | #define RMU_RSTCAUSE_BUBODUNREG_XMASK 0x00000001UL /** 0000000000000001 < Backup Brown Out Detector Unregulated Domain */ |
<> | 150:02e0a0aed4ec | 110 | #define RMU_RSTCAUSE_BUBODREG_XMASK 0x00000001UL /** 0000000000000001 < Backup Brown Out Detector Regulated Domain */ |
<> | 150:02e0a0aed4ec | 111 | #define RMU_RSTCAUSE_BUMODERST_XMASK 0x00000001UL /** 0000000000000001 < Backup mode reset */ |
<> | 150:02e0a0aed4ec | 112 | #define NUM_RSTCAUSES 16 |
<> | 144:ef7eb2e8f9f7 | 113 | |
<> | 161:2cc1468da177 | 114 | /* EFM32xG1, EFM32xG12, EFM32xG13 */ |
<> | 144:ef7eb2e8f9f7 | 115 | #elif ((_RMU_RSTCAUSE_MASK & 0x0FFFFFFF) == 0x00010F1DUL) |
<> | 150:02e0a0aed4ec | 116 | #define RMU_RSTCAUSE_PORST_XMASK 0x00000000UL /** 0000000000000000 < Power On Reset */ |
<> | 150:02e0a0aed4ec | 117 | #define RMU_RSTCAUSE_BODAVDD_XMASK 0x00000001UL /** 0000000000000001 < AVDD BOD Reset */ |
<> | 150:02e0a0aed4ec | 118 | #define RMU_RSTCAUSE_BODDVDD_XMASK 0x00000001UL /** 0000000000000001 < DVDD BOD Reset */ |
<> | 150:02e0a0aed4ec | 119 | #define RMU_RSTCAUSE_BODREGRST_XMASK 0x00000001UL /** 0000000000000001 < Regulated Domain (DEC) BOD Reset */ |
<> | 150:02e0a0aed4ec | 120 | #define RMU_RSTCAUSE_EXTRST_XMASK 0x00000001UL /** 0000000000000001 < External Pin Reset */ |
<> | 150:02e0a0aed4ec | 121 | #define RMU_RSTCAUSE_LOCKUPRST_XMASK 0x0000001DUL /** 0000000000011101 < LOCKUP Reset */ |
<> | 150:02e0a0aed4ec | 122 | #define RMU_RSTCAUSE_SYSREQRST_XMASK 0x0000001DUL /** 0000000000011101 < System Request Reset */ |
<> | 150:02e0a0aed4ec | 123 | #define RMU_RSTCAUSE_WDOGRST_XMASK 0x0000001DUL /** 0000000000011101 < Watchdog Reset */ |
<> | 150:02e0a0aed4ec | 124 | #define RMU_RSTCAUSE_EM4RST_XMASK 0x0000001DUL /** 0000000000011101 < EM4H/S Reset */ |
<> | 150:02e0a0aed4ec | 125 | #define NUM_RSTCAUSES 9 |
<> | 144:ef7eb2e8f9f7 | 126 | |
AnnaBridge | 179:b0033dcd6934 | 127 | /* EFM32GG11 */ |
AnnaBridge | 179:b0033dcd6934 | 128 | #elif ((_RMU_RSTCAUSE_MASK & 0x0FFFFFFF) == 0x00011F1DUL) |
AnnaBridge | 179:b0033dcd6934 | 129 | #define RMU_RSTCAUSE_PORST_XMASK 0x00000000UL /** 0000000000000000 < Power On Reset */ |
AnnaBridge | 179:b0033dcd6934 | 130 | #define RMU_RSTCAUSE_BODAVDD_XMASK 0x00000001UL /** 0000000000000001 < AVDD BOD Reset */ |
AnnaBridge | 179:b0033dcd6934 | 131 | #define RMU_RSTCAUSE_BODDVDD_XMASK 0x00000001UL /** 0000000000000001 < DVDD BOD Reset */ |
AnnaBridge | 179:b0033dcd6934 | 132 | #define RMU_RSTCAUSE_BODREGRST_XMASK 0x00000001UL /** 0000000000000001 < Regulated Domain (DEC) BOD Reset */ |
AnnaBridge | 179:b0033dcd6934 | 133 | #define RMU_RSTCAUSE_EXTRST_XMASK 0x00000001UL /** 0000000000000001 < External Pin Reset */ |
AnnaBridge | 179:b0033dcd6934 | 134 | #define RMU_RSTCAUSE_LOCKUPRST_XMASK 0x0000001DUL /** 0000000000011101 < LOCKUP Reset */ |
AnnaBridge | 179:b0033dcd6934 | 135 | #define RMU_RSTCAUSE_SYSREQRST_XMASK 0x0000001DUL /** 0000000000011101 < System Request Reset */ |
AnnaBridge | 179:b0033dcd6934 | 136 | #define RMU_RSTCAUSE_WDOGRST_XMASK 0x0000001DUL /** 0000000000011101 < Watchdog Reset */ |
AnnaBridge | 179:b0033dcd6934 | 137 | #define RMU_RSTCAUSE_BUMODERST_XMASK 0x0000001DUL /** 0000000000011101 < Backup mode reset */ |
AnnaBridge | 179:b0033dcd6934 | 138 | #define RMU_RSTCAUSE_EM4RST_XMASK 0x0000001DUL /** 0000000000011101 < EM4H/S Reset */ |
AnnaBridge | 179:b0033dcd6934 | 139 | #define NUM_RSTCAUSES 10 |
AnnaBridge | 179:b0033dcd6934 | 140 | |
<> | 144:ef7eb2e8f9f7 | 141 | #else |
<> | 150:02e0a0aed4ec | 142 | #error "RMU_RSTCAUSE XMASKs are not defined for this family." |
<> | 150:02e0a0aed4ec | 143 | #endif |
<> | 150:02e0a0aed4ec | 144 | |
AnnaBridge | 179:b0033dcd6934 | 145 | #if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) |
<> | 150:02e0a0aed4ec | 146 | /* Fix for errata EMU_E208 - Occasional Full Reset After Exiting EM4H */ |
<> | 150:02e0a0aed4ec | 147 | #define ERRATA_FIX_EMU_E208_EN |
<> | 144:ef7eb2e8f9f7 | 148 | #endif |
<> | 144:ef7eb2e8f9f7 | 149 | |
<> | 144:ef7eb2e8f9f7 | 150 | /******************************************************************************* |
<> | 144:ef7eb2e8f9f7 | 151 | ******************************* STRUCTS *********************************** |
<> | 144:ef7eb2e8f9f7 | 152 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 153 | |
<> | 144:ef7eb2e8f9f7 | 154 | /** Reset cause mask type. */ |
AnnaBridge | 179:b0033dcd6934 | 155 | typedef struct { |
<> | 150:02e0a0aed4ec | 156 | /** Reset-cause 1 bits */ |
<> | 144:ef7eb2e8f9f7 | 157 | uint32_t resetCauseMask; |
<> | 150:02e0a0aed4ec | 158 | /** Reset-cause 0 and "don't care" bits */ |
<> | 150:02e0a0aed4ec | 159 | uint32_t resetCauseZeroXMask; |
<> | 144:ef7eb2e8f9f7 | 160 | } RMU_ResetCauseMasks_Typedef; |
<> | 144:ef7eb2e8f9f7 | 161 | |
<> | 144:ef7eb2e8f9f7 | 162 | /******************************************************************************* |
<> | 144:ef7eb2e8f9f7 | 163 | ******************************* TYPEDEFS ********************************** |
<> | 144:ef7eb2e8f9f7 | 164 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 165 | |
<> | 144:ef7eb2e8f9f7 | 166 | /** Reset cause mask table. */ |
<> | 144:ef7eb2e8f9f7 | 167 | static const RMU_ResetCauseMasks_Typedef resetCauseMasks[NUM_RSTCAUSES] = |
AnnaBridge | 179:b0033dcd6934 | 168 | { |
AnnaBridge | 179:b0033dcd6934 | 169 | { RMU_RSTCAUSE_PORST, RMU_RSTCAUSE_PORST_XMASK }, |
<> | 144:ef7eb2e8f9f7 | 170 | #if defined(RMU_RSTCAUSE_BODUNREGRST) |
AnnaBridge | 179:b0033dcd6934 | 171 | { RMU_RSTCAUSE_BODUNREGRST, RMU_RSTCAUSE_BODUNREGRST_XMASK }, |
<> | 144:ef7eb2e8f9f7 | 172 | #endif |
<> | 144:ef7eb2e8f9f7 | 173 | #if defined(RMU_RSTCAUSE_BODREGRST) |
AnnaBridge | 179:b0033dcd6934 | 174 | { RMU_RSTCAUSE_BODREGRST, RMU_RSTCAUSE_BODREGRST_XMASK }, |
<> | 144:ef7eb2e8f9f7 | 175 | #endif |
<> | 144:ef7eb2e8f9f7 | 176 | #if defined(RMU_RSTCAUSE_AVDDBOD) |
AnnaBridge | 179:b0033dcd6934 | 177 | { RMU_RSTCAUSE_AVDDBOD, RMU_RSTCAUSE_BODAVDD_XMASK }, |
<> | 144:ef7eb2e8f9f7 | 178 | #endif |
<> | 144:ef7eb2e8f9f7 | 179 | #if defined(RMU_RSTCAUSE_DVDDBOD) |
AnnaBridge | 179:b0033dcd6934 | 180 | { RMU_RSTCAUSE_DVDDBOD, RMU_RSTCAUSE_BODDVDD_XMASK }, |
<> | 144:ef7eb2e8f9f7 | 181 | #endif |
<> | 144:ef7eb2e8f9f7 | 182 | #if defined(RMU_RSTCAUSE_DECBOD) |
AnnaBridge | 179:b0033dcd6934 | 183 | { RMU_RSTCAUSE_DECBOD, RMU_RSTCAUSE_BODREGRST_XMASK }, |
<> | 144:ef7eb2e8f9f7 | 184 | #endif |
AnnaBridge | 179:b0033dcd6934 | 185 | { RMU_RSTCAUSE_EXTRST, RMU_RSTCAUSE_EXTRST_XMASK }, |
AnnaBridge | 179:b0033dcd6934 | 186 | { RMU_RSTCAUSE_WDOGRST, RMU_RSTCAUSE_WDOGRST_XMASK }, |
AnnaBridge | 179:b0033dcd6934 | 187 | { RMU_RSTCAUSE_LOCKUPRST, RMU_RSTCAUSE_LOCKUPRST_XMASK }, |
AnnaBridge | 179:b0033dcd6934 | 188 | { RMU_RSTCAUSE_SYSREQRST, RMU_RSTCAUSE_SYSREQRST_XMASK }, |
<> | 144:ef7eb2e8f9f7 | 189 | #if defined(RMU_RSTCAUSE_EM4RST) |
AnnaBridge | 179:b0033dcd6934 | 190 | { RMU_RSTCAUSE_EM4RST, RMU_RSTCAUSE_EM4RST_XMASK }, |
<> | 144:ef7eb2e8f9f7 | 191 | #endif |
<> | 144:ef7eb2e8f9f7 | 192 | #if defined(RMU_RSTCAUSE_EM4WURST) |
AnnaBridge | 179:b0033dcd6934 | 193 | { RMU_RSTCAUSE_EM4WURST, RMU_RSTCAUSE_EM4WURST_XMASK }, |
<> | 144:ef7eb2e8f9f7 | 194 | #endif |
<> | 144:ef7eb2e8f9f7 | 195 | #if defined(RMU_RSTCAUSE_BODAVDD0) |
AnnaBridge | 179:b0033dcd6934 | 196 | { RMU_RSTCAUSE_BODAVDD0, RMU_RSTCAUSE_BODAVDD0_XMASK }, |
<> | 144:ef7eb2e8f9f7 | 197 | #endif |
<> | 144:ef7eb2e8f9f7 | 198 | #if defined(RMU_RSTCAUSE_BODAVDD1) |
AnnaBridge | 179:b0033dcd6934 | 199 | { RMU_RSTCAUSE_BODAVDD1, RMU_RSTCAUSE_BODAVDD1_XMASK }, |
<> | 144:ef7eb2e8f9f7 | 200 | #endif |
AnnaBridge | 179:b0033dcd6934 | 201 | #if defined(BU_PRESENT) && defined(_SILICON_LABS_32B_SERIES_0) |
AnnaBridge | 179:b0033dcd6934 | 202 | { RMU_RSTCAUSE_BUBODVDDDREG, RMU_RSTCAUSE_BUBODVDDDREG_XMASK }, |
AnnaBridge | 179:b0033dcd6934 | 203 | { RMU_RSTCAUSE_BUBODBUVIN, RMU_RSTCAUSE_BUBODBUVIN_XMASK }, |
AnnaBridge | 179:b0033dcd6934 | 204 | { RMU_RSTCAUSE_BUBODUNREG, RMU_RSTCAUSE_BUBODUNREG_XMASK }, |
AnnaBridge | 179:b0033dcd6934 | 205 | { RMU_RSTCAUSE_BUBODREG, RMU_RSTCAUSE_BUBODREG_XMASK }, |
AnnaBridge | 179:b0033dcd6934 | 206 | { RMU_RSTCAUSE_BUMODERST, RMU_RSTCAUSE_BUMODERST_XMASK }, |
AnnaBridge | 179:b0033dcd6934 | 207 | #elif defined(RMU_RSTCAUSE_BUMODERST) |
AnnaBridge | 179:b0033dcd6934 | 208 | { RMU_RSTCAUSE_BUMODERST, RMU_RSTCAUSE_BUMODERST_XMASK }, |
<> | 144:ef7eb2e8f9f7 | 209 | #endif |
AnnaBridge | 179:b0033dcd6934 | 210 | }; |
<> | 144:ef7eb2e8f9f7 | 211 | |
<> | 144:ef7eb2e8f9f7 | 212 | /******************************************************************************* |
<> | 144:ef7eb2e8f9f7 | 213 | ******************************** TEST ******************************** |
<> | 144:ef7eb2e8f9f7 | 214 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 215 | #if defined(EMLIB_REGRESSION_TEST) |
<> | 144:ef7eb2e8f9f7 | 216 | /* Test variable that replaces the RSTCAUSE cause register when testing |
<> | 144:ef7eb2e8f9f7 | 217 | the RMU_ResetCauseGet function. */ |
<> | 144:ef7eb2e8f9f7 | 218 | extern uint32_t rstCause; |
<> | 144:ef7eb2e8f9f7 | 219 | #endif |
<> | 144:ef7eb2e8f9f7 | 220 | |
<> | 144:ef7eb2e8f9f7 | 221 | /** @endcond */ |
<> | 144:ef7eb2e8f9f7 | 222 | |
<> | 144:ef7eb2e8f9f7 | 223 | /******************************************************************************* |
<> | 144:ef7eb2e8f9f7 | 224 | ************************** GLOBAL FUNCTIONS ******************************* |
<> | 144:ef7eb2e8f9f7 | 225 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 226 | |
<> | 144:ef7eb2e8f9f7 | 227 | /***************************************************************************//** |
<> | 144:ef7eb2e8f9f7 | 228 | * @brief |
<> | 144:ef7eb2e8f9f7 | 229 | * Disable/enable reset for various peripherals and signal sources |
<> | 144:ef7eb2e8f9f7 | 230 | * |
<> | 144:ef7eb2e8f9f7 | 231 | * @param[in] reset Reset types to enable/disable |
<> | 144:ef7eb2e8f9f7 | 232 | * |
<> | 144:ef7eb2e8f9f7 | 233 | * @param[in] mode Reset mode |
<> | 144:ef7eb2e8f9f7 | 234 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 235 | void RMU_ResetControl(RMU_Reset_TypeDef reset, RMU_ResetMode_TypeDef mode) |
<> | 144:ef7eb2e8f9f7 | 236 | { |
<> | 144:ef7eb2e8f9f7 | 237 | /* Note that the RMU supports bit-band access, but not peripheral bit-field set/clear */ |
<> | 144:ef7eb2e8f9f7 | 238 | #if defined(_RMU_CTRL_PINRMODE_MASK) |
<> | 144:ef7eb2e8f9f7 | 239 | uint32_t val; |
<> | 144:ef7eb2e8f9f7 | 240 | #endif |
<> | 144:ef7eb2e8f9f7 | 241 | uint32_t shift; |
<> | 144:ef7eb2e8f9f7 | 242 | |
<> | 150:02e0a0aed4ec | 243 | shift = SL_CTZ((uint32_t)reset); |
<> | 144:ef7eb2e8f9f7 | 244 | #if defined(_RMU_CTRL_PINRMODE_MASK) |
<> | 144:ef7eb2e8f9f7 | 245 | val = (uint32_t)mode << shift; |
<> | 144:ef7eb2e8f9f7 | 246 | RMU->CTRL = (RMU->CTRL & ~reset) | val; |
<> | 144:ef7eb2e8f9f7 | 247 | #else |
<> | 144:ef7eb2e8f9f7 | 248 | BUS_RegBitWrite(&RMU->CTRL, (uint32_t)shift, mode ? 1 : 0); |
<> | 144:ef7eb2e8f9f7 | 249 | #endif |
<> | 144:ef7eb2e8f9f7 | 250 | } |
<> | 144:ef7eb2e8f9f7 | 251 | |
<> | 144:ef7eb2e8f9f7 | 252 | /***************************************************************************//** |
<> | 144:ef7eb2e8f9f7 | 253 | * @brief |
<> | 144:ef7eb2e8f9f7 | 254 | * Clear the reset cause register. |
<> | 144:ef7eb2e8f9f7 | 255 | * |
<> | 144:ef7eb2e8f9f7 | 256 | * @details |
<> | 144:ef7eb2e8f9f7 | 257 | * This function clears all the reset cause bits of the RSTCAUSE register. |
<> | 144:ef7eb2e8f9f7 | 258 | * The reset cause bits must be cleared by SW before a new reset occurs, |
<> | 144:ef7eb2e8f9f7 | 259 | * otherwise reset causes may accumulate. See @ref RMU_ResetCauseGet(). |
<> | 144:ef7eb2e8f9f7 | 260 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 261 | void RMU_ResetCauseClear(void) |
<> | 144:ef7eb2e8f9f7 | 262 | { |
<> | 144:ef7eb2e8f9f7 | 263 | RMU->CMD = RMU_CMD_RCCLR; |
<> | 144:ef7eb2e8f9f7 | 264 | |
<> | 144:ef7eb2e8f9f7 | 265 | #if defined(EMU_AUXCTRL_HRCCLR) |
<> | 144:ef7eb2e8f9f7 | 266 | { |
<> | 144:ef7eb2e8f9f7 | 267 | uint32_t locked; |
<> | 144:ef7eb2e8f9f7 | 268 | |
<> | 144:ef7eb2e8f9f7 | 269 | /* Clear some reset causes not cleared with RMU CMD register */ |
<> | 144:ef7eb2e8f9f7 | 270 | /* (If EMU registers locked, they must be unlocked first) */ |
<> | 144:ef7eb2e8f9f7 | 271 | locked = EMU->LOCK & EMU_LOCK_LOCKKEY_LOCKED; |
AnnaBridge | 179:b0033dcd6934 | 272 | if (locked) { |
<> | 144:ef7eb2e8f9f7 | 273 | EMU_Unlock(); |
<> | 144:ef7eb2e8f9f7 | 274 | } |
<> | 144:ef7eb2e8f9f7 | 275 | |
<> | 144:ef7eb2e8f9f7 | 276 | BUS_RegBitWrite(&(EMU->AUXCTRL), _EMU_AUXCTRL_HRCCLR_SHIFT, 1); |
<> | 144:ef7eb2e8f9f7 | 277 | BUS_RegBitWrite(&(EMU->AUXCTRL), _EMU_AUXCTRL_HRCCLR_SHIFT, 0); |
<> | 144:ef7eb2e8f9f7 | 278 | |
AnnaBridge | 179:b0033dcd6934 | 279 | if (locked) { |
<> | 144:ef7eb2e8f9f7 | 280 | EMU_Lock(); |
<> | 144:ef7eb2e8f9f7 | 281 | } |
<> | 144:ef7eb2e8f9f7 | 282 | } |
<> | 144:ef7eb2e8f9f7 | 283 | #endif |
<> | 144:ef7eb2e8f9f7 | 284 | } |
<> | 144:ef7eb2e8f9f7 | 285 | |
<> | 144:ef7eb2e8f9f7 | 286 | /***************************************************************************//** |
<> | 144:ef7eb2e8f9f7 | 287 | * @brief |
<> | 144:ef7eb2e8f9f7 | 288 | * Get the cause of the last reset. |
<> | 144:ef7eb2e8f9f7 | 289 | * |
<> | 144:ef7eb2e8f9f7 | 290 | * @details |
<> | 144:ef7eb2e8f9f7 | 291 | * In order to be useful, the reset cause must be cleared by software before a new |
<> | 144:ef7eb2e8f9f7 | 292 | * reset occurs, otherwise reset causes may accumulate. See @ref |
<> | 144:ef7eb2e8f9f7 | 293 | * RMU_ResetCauseClear(). This function call will return the main cause for |
<> | 144:ef7eb2e8f9f7 | 294 | * reset, which can be a bit mask (several causes), and clear away "noise". |
<> | 144:ef7eb2e8f9f7 | 295 | * |
<> | 144:ef7eb2e8f9f7 | 296 | * @return |
<> | 144:ef7eb2e8f9f7 | 297 | * Reset cause mask. Please consult the reference manual for description |
<> | 144:ef7eb2e8f9f7 | 298 | * of the reset cause mask. |
<> | 144:ef7eb2e8f9f7 | 299 | ******************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 300 | uint32_t RMU_ResetCauseGet(void) |
<> | 144:ef7eb2e8f9f7 | 301 | { |
AnnaBridge | 179:b0033dcd6934 | 302 | #define LB_CLW0 (*((volatile uint32_t *)(LOCKBITS_BASE) +122)) |
<> | 150:02e0a0aed4ec | 303 | #define LB_CLW0_PINRESETSOFT (1 << 2) |
<> | 150:02e0a0aed4ec | 304 | |
<> | 144:ef7eb2e8f9f7 | 305 | #if !defined(EMLIB_REGRESSION_TEST) |
<> | 144:ef7eb2e8f9f7 | 306 | uint32_t rstCause = RMU->RSTCAUSE; |
<> | 144:ef7eb2e8f9f7 | 307 | #endif |
<> | 144:ef7eb2e8f9f7 | 308 | uint32_t validRstCause = 0; |
<> | 150:02e0a0aed4ec | 309 | uint32_t zeroXMask; |
<> | 144:ef7eb2e8f9f7 | 310 | uint32_t i; |
<> | 144:ef7eb2e8f9f7 | 311 | |
AnnaBridge | 179:b0033dcd6934 | 312 | for (i = 0; i < NUM_RSTCAUSES; i++) { |
<> | 150:02e0a0aed4ec | 313 | zeroXMask = resetCauseMasks[i].resetCauseZeroXMask; |
AnnaBridge | 179:b0033dcd6934 | 314 | #if defined(_SILICON_LABS_32B_SERIES_1) |
<> | 150:02e0a0aed4ec | 315 | /* Handle soft/hard pin reset */ |
AnnaBridge | 179:b0033dcd6934 | 316 | if (!(LB_CLW0 & LB_CLW0_PINRESETSOFT)) { |
<> | 150:02e0a0aed4ec | 317 | /* RSTCAUSE_EXTRST must be 0 if pin reset is configured as hard reset */ |
AnnaBridge | 179:b0033dcd6934 | 318 | switch (resetCauseMasks[i].resetCauseMask) { |
<> | 150:02e0a0aed4ec | 319 | case RMU_RSTCAUSE_LOCKUPRST: |
AnnaBridge | 179:b0033dcd6934 | 320 | /* Fallthrough */ |
<> | 150:02e0a0aed4ec | 321 | case RMU_RSTCAUSE_SYSREQRST: |
AnnaBridge | 179:b0033dcd6934 | 322 | /* Fallthrough */ |
<> | 150:02e0a0aed4ec | 323 | case RMU_RSTCAUSE_WDOGRST: |
AnnaBridge | 179:b0033dcd6934 | 324 | /* Fallthrough */ |
<> | 150:02e0a0aed4ec | 325 | case RMU_RSTCAUSE_EM4RST: |
<> | 150:02e0a0aed4ec | 326 | zeroXMask |= RMU_RSTCAUSE_EXTRST; |
<> | 150:02e0a0aed4ec | 327 | break; |
<> | 150:02e0a0aed4ec | 328 | } |
<> | 150:02e0a0aed4ec | 329 | } |
<> | 150:02e0a0aed4ec | 330 | #endif |
<> | 150:02e0a0aed4ec | 331 | |
AnnaBridge | 179:b0033dcd6934 | 332 | #if defined(_EMU_EM4CTRL_MASK) && defined(ERRATA_FIX_EMU_E208_EN) |
<> | 150:02e0a0aed4ec | 333 | /* Ignore BOD flags impacted by EMU_E208 */ |
AnnaBridge | 179:b0033dcd6934 | 334 | if (*(volatile uint32_t *)(EMU_BASE + 0x88) & (0x1 << 8)) { |
<> | 150:02e0a0aed4ec | 335 | zeroXMask &= ~(RMU_RSTCAUSE_DECBOD |
<> | 150:02e0a0aed4ec | 336 | | RMU_RSTCAUSE_DVDDBOD |
<> | 150:02e0a0aed4ec | 337 | | RMU_RSTCAUSE_AVDDBOD); |
<> | 150:02e0a0aed4ec | 338 | } |
<> | 150:02e0a0aed4ec | 339 | #endif |
<> | 150:02e0a0aed4ec | 340 | |
<> | 150:02e0a0aed4ec | 341 | /* Check reset cause requirements. Note that a bit is "don't care" if 0 in |
<> | 150:02e0a0aed4ec | 342 | both resetCauseMask and resetCauseZeroXMask. */ |
<> | 144:ef7eb2e8f9f7 | 343 | if ((rstCause & resetCauseMasks[i].resetCauseMask) |
AnnaBridge | 179:b0033dcd6934 | 344 | && !(rstCause & zeroXMask)) { |
<> | 150:02e0a0aed4ec | 345 | /* Add this reset-cause to the mask of qualified reset-causes */ |
<> | 144:ef7eb2e8f9f7 | 346 | validRstCause |= resetCauseMasks[i].resetCauseMask; |
<> | 144:ef7eb2e8f9f7 | 347 | } |
<> | 144:ef7eb2e8f9f7 | 348 | } |
AnnaBridge | 179:b0033dcd6934 | 349 | #if defined(_EMU_EM4CTRL_MASK) && defined(ERRATA_FIX_EMU_E208_EN) |
<> | 150:02e0a0aed4ec | 350 | /* Clear BOD flags impacted by EMU_E208 */ |
AnnaBridge | 179:b0033dcd6934 | 351 | if (validRstCause & RMU_RSTCAUSE_EM4RST) { |
<> | 150:02e0a0aed4ec | 352 | validRstCause &= ~(RMU_RSTCAUSE_DECBOD |
AnnaBridge | 179:b0033dcd6934 | 353 | | RMU_RSTCAUSE_DVDDBOD |
AnnaBridge | 179:b0033dcd6934 | 354 | | RMU_RSTCAUSE_AVDDBOD); |
<> | 150:02e0a0aed4ec | 355 | } |
<> | 150:02e0a0aed4ec | 356 | #endif |
<> | 144:ef7eb2e8f9f7 | 357 | return validRstCause; |
<> | 144:ef7eb2e8f9f7 | 358 | } |
<> | 144:ef7eb2e8f9f7 | 359 | |
<> | 144:ef7eb2e8f9f7 | 360 | /** @} (end addtogroup RMU) */ |
<> | 150:02e0a0aed4ec | 361 | /** @} (end addtogroup emlib) */ |
<> | 144:ef7eb2e8f9f7 | 362 | #endif /* defined(RMU_COUNT) && (RMU_COUNT > 0) */ |