mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

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targets/TARGET_Silicon_Labs/TARGET_EFM32/emlib/src/em_rmu.c@161:2cc1468da177, 2017-03-30 (annotated)

Committer:
<>
Date:
Thu Mar 30 13:45:57 2017 +0100
Revision:
161:2cc1468da177
Parent:
150:02e0a0aed4ec
Child:
179:b0033dcd6934
This updates the lib to the mbed lib v139

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 2 * @file em_rmu.c
<> 144:ef7eb2e8f9f7 3 * @brief Reset Management Unit (RMU) peripheral module peripheral API
<> 144:ef7eb2e8f9f7 4 *
<> 161:2cc1468da177 5 * @version 5.1.2
<> 144:ef7eb2e8f9f7 6 *******************************************************************************
<> 144:ef7eb2e8f9f7 7 * @section License
<> 150:02e0a0aed4ec 8 * <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
<> 144:ef7eb2e8f9f7 9 *******************************************************************************
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * Permission is granted to anyone to use this software for any purpose,
<> 144:ef7eb2e8f9f7 12 * including commercial applications, and to alter it and redistribute it
<> 144:ef7eb2e8f9f7 13 * freely, subject to the following restrictions:
<> 144:ef7eb2e8f9f7 14 *
<> 144:ef7eb2e8f9f7 15 * 1. The origin of this software must not be misrepresented; you must not
<> 144:ef7eb2e8f9f7 16 * claim that you wrote the original software.
<> 144:ef7eb2e8f9f7 17 * 2. Altered source versions must be plainly marked as such, and must not be
<> 144:ef7eb2e8f9f7 18 * misrepresented as being the original software.
<> 144:ef7eb2e8f9f7 19 * 3. This notice may not be removed or altered from any source distribution.
<> 144:ef7eb2e8f9f7 20 *
<> 144:ef7eb2e8f9f7 21 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no
<> 144:ef7eb2e8f9f7 22 * obligation to support this Software. Silicon Labs is providing the
<> 144:ef7eb2e8f9f7 23 * Software "AS IS", with no express or implied warranties of any kind,
<> 144:ef7eb2e8f9f7 24 * including, but not limited to, any implied warranties of merchantability
<> 144:ef7eb2e8f9f7 25 * or fitness for any particular purpose or warranties against infringement
<> 144:ef7eb2e8f9f7 26 * of any proprietary rights of a third party.
<> 144:ef7eb2e8f9f7 27 *
<> 144:ef7eb2e8f9f7 28 * Silicon Labs will not be liable for any consequential, incidental, or
<> 144:ef7eb2e8f9f7 29 * special damages, or any other relief, or for any claim by any third party,
<> 144:ef7eb2e8f9f7 30 * arising from your use of this Software.
<> 144:ef7eb2e8f9f7 31 *
<> 144:ef7eb2e8f9f7 32 ******************************************************************************/
<> 144:ef7eb2e8f9f7 33
<> 144:ef7eb2e8f9f7 34 #include "em_rmu.h"
<> 144:ef7eb2e8f9f7 35 #if defined(RMU_COUNT) && (RMU_COUNT > 0)
<> 144:ef7eb2e8f9f7 36
<> 144:ef7eb2e8f9f7 37 #include "em_common.h"
<> 144:ef7eb2e8f9f7 38 #include "em_emu.h"
<> 144:ef7eb2e8f9f7 39 #include "em_bus.h"
<> 144:ef7eb2e8f9f7 40
<> 144:ef7eb2e8f9f7 41 /***************************************************************************//**
<> 150:02e0a0aed4ec 42 * @addtogroup emlib
<> 144:ef7eb2e8f9f7 43 * @{
<> 144:ef7eb2e8f9f7 44 ******************************************************************************/
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 47 * @addtogroup RMU
<> 144:ef7eb2e8f9f7 48 * @brief Reset Management Unit (RMU) Peripheral API
<> 150:02e0a0aed4ec 49 * @details
<> 150:02e0a0aed4ec 50 * This module contains functions to control the RMU peripheral of Silicon
<> 150:02e0a0aed4ec 51 * Labs 32-bit MCUs and SoCs. The RMU ensures correct reset operation. It is
<> 150:02e0a0aed4ec 52 * responsible for connecting the different reset sources to the reset lines of
<> 150:02e0a0aed4ec 53 * the MCU or SoC.
<> 144:ef7eb2e8f9f7 54 * @{
<> 144:ef7eb2e8f9f7 55 ******************************************************************************/
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 /*******************************************************************************
<> 144:ef7eb2e8f9f7 58 ***************************** DEFINES *********************************
<> 144:ef7eb2e8f9f7 59 ******************************************************************************/
<> 144:ef7eb2e8f9f7 60
<> 144:ef7eb2e8f9f7 61 /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */
<> 144:ef7eb2e8f9f7 62
<> 150:02e0a0aed4ec 63 /* Reset cause zero and "don't care" bit definitions (XMASKs).
<> 150:02e0a0aed4ec 64 A XMASK 1 bit marks a bit that must be zero in RMU_RSTCAUSE. A 0 in XMASK
<> 150:02e0a0aed4ec 65 is a "don't care" bit in RMU_RSTCAUSE if also 0 in resetCauseMask
<> 150:02e0a0aed4ec 66 in @ref RMU_ResetCauseMasks_Typedef. */
<> 150:02e0a0aed4ec 67
<> 150:02e0a0aed4ec 68 /* EFM32G */
<> 144:ef7eb2e8f9f7 69 #if (_RMU_RSTCAUSE_MASK == 0x0000007FUL)
<> 150:02e0a0aed4ec 70 #define RMU_RSTCAUSE_PORST_XMASK 0x00000000UL /** 0000000000000000 < Power On Reset */
<> 150:02e0a0aed4ec 71 #define RMU_RSTCAUSE_BODUNREGRST_XMASK 0x00000001UL /** 0000000000000001 < Brown Out Detector Unregulated Domain Reset */
<> 150:02e0a0aed4ec 72 #define RMU_RSTCAUSE_BODREGRST_XMASK 0x0000001BUL /** 0000000000011011 < Brown Out Detector Regulated Domain Reset */
<> 150:02e0a0aed4ec 73 #define RMU_RSTCAUSE_EXTRST_XMASK 0x00000003UL /** 0000000000000011 < External Pin Reset */
<> 150:02e0a0aed4ec 74 #define RMU_RSTCAUSE_WDOGRST_XMASK 0x00000003UL /** 0000000000000011 < Watchdog Reset */
<> 150:02e0a0aed4ec 75 #define RMU_RSTCAUSE_LOCKUPRST_XMASK 0x0000001FUL /** 0000000000011111 < LOCKUP Reset */
<> 150:02e0a0aed4ec 76 #define RMU_RSTCAUSE_SYSREQRST_XMASK 0x0000001FUL /** 0000000000011111 < System Request Reset */
<> 150:02e0a0aed4ec 77 #define NUM_RSTCAUSES 7
<> 144:ef7eb2e8f9f7 78
<> 150:02e0a0aed4ec 79 /* EFM32TG, EFM32HG, EZR32HG, EFM32ZG */
<> 144:ef7eb2e8f9f7 80 #elif (_RMU_RSTCAUSE_MASK == 0x000007FFUL)
<> 150:02e0a0aed4ec 81 #define RMU_RSTCAUSE_PORST_XMASK 0x00000000UL /** 0000000000000000 < Power On Reset */
<> 150:02e0a0aed4ec 82 #define RMU_RSTCAUSE_BODUNREGRST_XMASK 0x00000081UL /** 0000000010000001 < Brown Out Detector Unregulated Domain Reset */
<> 150:02e0a0aed4ec 83 #define RMU_RSTCAUSE_BODREGRST_XMASK 0x00000091UL /** 0000000010010001 < Brown Out Detector Regulated Domain Reset */
<> 150:02e0a0aed4ec 84 #define RMU_RSTCAUSE_EXTRST_XMASK 0x00000001UL /** 0000000000000001 < External Pin Reset */
<> 150:02e0a0aed4ec 85 #define RMU_RSTCAUSE_WDOGRST_XMASK 0x00000003UL /** 0000000000000011 < Watchdog Reset */
<> 150:02e0a0aed4ec 86 #define RMU_RSTCAUSE_LOCKUPRST_XMASK 0x0000EFDFUL /** 1110111111011111 < LOCKUP Reset */
<> 150:02e0a0aed4ec 87 #define RMU_RSTCAUSE_SYSREQRST_XMASK 0x0000EF9FUL /** 1110111110011111 < System Request Reset */
<> 150:02e0a0aed4ec 88 #define RMU_RSTCAUSE_EM4RST_XMASK 0x00000719UL /** 0000011100011001 < EM4 Reset */
<> 150:02e0a0aed4ec 89 #define RMU_RSTCAUSE_EM4WURST_XMASK 0x00000619UL /** 0000011000011001 < EM4 Wake-up Reset */
<> 150:02e0a0aed4ec 90 #define RMU_RSTCAUSE_BODAVDD0_XMASK 0x0000041FUL /** 0000010000011111 < AVDD0 Bod Reset. */
<> 150:02e0a0aed4ec 91 #define RMU_RSTCAUSE_BODAVDD1_XMASK 0x0000021FUL /** 0000001000011111 < AVDD1 Bod Reset. */
<> 150:02e0a0aed4ec 92 #define NUM_RSTCAUSES 11
<> 144:ef7eb2e8f9f7 93
<> 150:02e0a0aed4ec 94 /* EFM32GG, EFM32LG, EZR32LG, EFM32WG, EZR32WG */
<> 144:ef7eb2e8f9f7 95 #elif (_RMU_RSTCAUSE_MASK == 0x0000FFFFUL)
<> 150:02e0a0aed4ec 96 #define RMU_RSTCAUSE_PORST_XMASK 0x00000000UL /** 0000000000000000 < Power On Reset */
<> 150:02e0a0aed4ec 97 #define RMU_RSTCAUSE_BODUNREGRST_XMASK 0x00000081UL /** 0000000010000001 < Brown Out Detector Unregulated Domain Reset */
<> 150:02e0a0aed4ec 98 #define RMU_RSTCAUSE_BODREGRST_XMASK 0x00000091UL /** 0000000010010001 < Brown Out Detector Regulated Domain Reset */
<> 150:02e0a0aed4ec 99 #define RMU_RSTCAUSE_EXTRST_XMASK 0x00000001UL /** 0000000000000001 < External Pin Reset */
<> 150:02e0a0aed4ec 100 #define RMU_RSTCAUSE_WDOGRST_XMASK 0x00000003UL /** 0000000000000011 < Watchdog Reset */
<> 150:02e0a0aed4ec 101 #define RMU_RSTCAUSE_LOCKUPRST_XMASK 0x0000EFDFUL /** 1110111111011111 < LOCKUP Reset */
<> 150:02e0a0aed4ec 102 #define RMU_RSTCAUSE_SYSREQRST_XMASK 0x0000EF9FUL /** 1110111110011111 < System Request Reset */
<> 150:02e0a0aed4ec 103 #define RMU_RSTCAUSE_EM4RST_XMASK 0x00000719UL /** 0000011100011001 < EM4 Reset */
<> 150:02e0a0aed4ec 104 #define RMU_RSTCAUSE_EM4WURST_XMASK 0x00000619UL /** 0000011000011001 < EM4 Wake-up Reset */
<> 150:02e0a0aed4ec 105 #define RMU_RSTCAUSE_BODAVDD0_XMASK 0x0000041FUL /** 0000010000011111 < AVDD0 Bod Reset */
<> 150:02e0a0aed4ec 106 #define RMU_RSTCAUSE_BODAVDD1_XMASK 0x0000021FUL /** 0000001000011111 < AVDD1 Bod Reset */
<> 150:02e0a0aed4ec 107 #define RMU_RSTCAUSE_BUBODVDDDREG_XMASK 0x00000001UL /** 0000000000000001 < Backup Brown Out Detector, VDD_DREG */
<> 150:02e0a0aed4ec 108 #define RMU_RSTCAUSE_BUBODBUVIN_XMASK 0x00000001UL /** 0000000000000001 < Backup Brown Out Detector, BU_VIN */
<> 150:02e0a0aed4ec 109 #define RMU_RSTCAUSE_BUBODUNREG_XMASK 0x00000001UL /** 0000000000000001 < Backup Brown Out Detector Unregulated Domain */
<> 150:02e0a0aed4ec 110 #define RMU_RSTCAUSE_BUBODREG_XMASK 0x00000001UL /** 0000000000000001 < Backup Brown Out Detector Regulated Domain */
<> 150:02e0a0aed4ec 111 #define RMU_RSTCAUSE_BUMODERST_XMASK 0x00000001UL /** 0000000000000001 < Backup mode reset */
<> 150:02e0a0aed4ec 112 #define NUM_RSTCAUSES 16
<> 144:ef7eb2e8f9f7 113
<> 161:2cc1468da177 114 /* EFM32xG1, EFM32xG12, EFM32xG13 */
<> 144:ef7eb2e8f9f7 115 #elif ((_RMU_RSTCAUSE_MASK & 0x0FFFFFFF) == 0x00010F1DUL)
<> 150:02e0a0aed4ec 116 #define RMU_RSTCAUSE_PORST_XMASK 0x00000000UL /** 0000000000000000 < Power On Reset */
<> 150:02e0a0aed4ec 117 #define RMU_RSTCAUSE_BODAVDD_XMASK 0x00000001UL /** 0000000000000001 < AVDD BOD Reset */
<> 150:02e0a0aed4ec 118 #define RMU_RSTCAUSE_BODDVDD_XMASK 0x00000001UL /** 0000000000000001 < DVDD BOD Reset */
<> 150:02e0a0aed4ec 119 #define RMU_RSTCAUSE_BODREGRST_XMASK 0x00000001UL /** 0000000000000001 < Regulated Domain (DEC) BOD Reset */
<> 150:02e0a0aed4ec 120 #define RMU_RSTCAUSE_EXTRST_XMASK 0x00000001UL /** 0000000000000001 < External Pin Reset */
<> 150:02e0a0aed4ec 121 #define RMU_RSTCAUSE_LOCKUPRST_XMASK 0x0000001DUL /** 0000000000011101 < LOCKUP Reset */
<> 150:02e0a0aed4ec 122 #define RMU_RSTCAUSE_SYSREQRST_XMASK 0x0000001DUL /** 0000000000011101 < System Request Reset */
<> 150:02e0a0aed4ec 123 #define RMU_RSTCAUSE_WDOGRST_XMASK 0x0000001DUL /** 0000000000011101 < Watchdog Reset */
<> 150:02e0a0aed4ec 124 #define RMU_RSTCAUSE_EM4RST_XMASK 0x0000001DUL /** 0000000000011101 < EM4H/S Reset */
<> 150:02e0a0aed4ec 125 #define NUM_RSTCAUSES 9
<> 144:ef7eb2e8f9f7 126
<> 144:ef7eb2e8f9f7 127 #else
<> 150:02e0a0aed4ec 128 #error "RMU_RSTCAUSE XMASKs are not defined for this family."
<> 150:02e0a0aed4ec 129 #endif
<> 150:02e0a0aed4ec 130
<> 161:2cc1468da177 131 #if defined( _SILICON_LABS_GECKO_INTERNAL_SDID_80 )
<> 150:02e0a0aed4ec 132 /* Fix for errata EMU_E208 - Occasional Full Reset After Exiting EM4H */
<> 150:02e0a0aed4ec 133 #define ERRATA_FIX_EMU_E208_EN
<> 144:ef7eb2e8f9f7 134 #endif
<> 144:ef7eb2e8f9f7 135
<> 144:ef7eb2e8f9f7 136 /*******************************************************************************
<> 144:ef7eb2e8f9f7 137 ******************************* STRUCTS ***********************************
<> 144:ef7eb2e8f9f7 138 ******************************************************************************/
<> 144:ef7eb2e8f9f7 139
<> 144:ef7eb2e8f9f7 140 /** Reset cause mask type. */
<> 144:ef7eb2e8f9f7 141 typedef struct
<> 144:ef7eb2e8f9f7 142 {
<> 150:02e0a0aed4ec 143 /** Reset-cause 1 bits */
<> 144:ef7eb2e8f9f7 144 uint32_t resetCauseMask;
<> 150:02e0a0aed4ec 145 /** Reset-cause 0 and "don't care" bits */
<> 150:02e0a0aed4ec 146 uint32_t resetCauseZeroXMask;
<> 144:ef7eb2e8f9f7 147 } RMU_ResetCauseMasks_Typedef;
<> 144:ef7eb2e8f9f7 148
<> 144:ef7eb2e8f9f7 149
<> 144:ef7eb2e8f9f7 150 /*******************************************************************************
<> 144:ef7eb2e8f9f7 151 ******************************* TYPEDEFS **********************************
<> 144:ef7eb2e8f9f7 152 ******************************************************************************/
<> 144:ef7eb2e8f9f7 153
<> 144:ef7eb2e8f9f7 154 /** Reset cause mask table. */
<> 144:ef7eb2e8f9f7 155 static const RMU_ResetCauseMasks_Typedef resetCauseMasks[NUM_RSTCAUSES] =
<> 144:ef7eb2e8f9f7 156 {
<> 144:ef7eb2e8f9f7 157 { RMU_RSTCAUSE_PORST, RMU_RSTCAUSE_PORST_XMASK },
<> 144:ef7eb2e8f9f7 158 #if defined(RMU_RSTCAUSE_BODUNREGRST)
<> 144:ef7eb2e8f9f7 159 { RMU_RSTCAUSE_BODUNREGRST, RMU_RSTCAUSE_BODUNREGRST_XMASK },
<> 144:ef7eb2e8f9f7 160 #endif
<> 144:ef7eb2e8f9f7 161 #if defined(RMU_RSTCAUSE_BODREGRST)
<> 144:ef7eb2e8f9f7 162 { RMU_RSTCAUSE_BODREGRST, RMU_RSTCAUSE_BODREGRST_XMASK },
<> 144:ef7eb2e8f9f7 163 #endif
<> 144:ef7eb2e8f9f7 164 #if defined(RMU_RSTCAUSE_AVDDBOD)
<> 144:ef7eb2e8f9f7 165 { RMU_RSTCAUSE_AVDDBOD, RMU_RSTCAUSE_BODAVDD_XMASK },
<> 144:ef7eb2e8f9f7 166 #endif
<> 144:ef7eb2e8f9f7 167 #if defined(RMU_RSTCAUSE_DVDDBOD)
<> 144:ef7eb2e8f9f7 168 { RMU_RSTCAUSE_DVDDBOD, RMU_RSTCAUSE_BODDVDD_XMASK },
<> 144:ef7eb2e8f9f7 169 #endif
<> 144:ef7eb2e8f9f7 170 #if defined(RMU_RSTCAUSE_DECBOD)
<> 144:ef7eb2e8f9f7 171 { RMU_RSTCAUSE_DECBOD, RMU_RSTCAUSE_BODREGRST_XMASK },
<> 144:ef7eb2e8f9f7 172 #endif
<> 144:ef7eb2e8f9f7 173 { RMU_RSTCAUSE_EXTRST, RMU_RSTCAUSE_EXTRST_XMASK },
<> 144:ef7eb2e8f9f7 174 { RMU_RSTCAUSE_WDOGRST, RMU_RSTCAUSE_WDOGRST_XMASK },
<> 144:ef7eb2e8f9f7 175 { RMU_RSTCAUSE_LOCKUPRST, RMU_RSTCAUSE_LOCKUPRST_XMASK },
<> 144:ef7eb2e8f9f7 176 { RMU_RSTCAUSE_SYSREQRST, RMU_RSTCAUSE_SYSREQRST_XMASK },
<> 144:ef7eb2e8f9f7 177 #if defined(RMU_RSTCAUSE_EM4RST)
<> 144:ef7eb2e8f9f7 178 { RMU_RSTCAUSE_EM4RST, RMU_RSTCAUSE_EM4RST_XMASK },
<> 144:ef7eb2e8f9f7 179 #endif
<> 144:ef7eb2e8f9f7 180 #if defined(RMU_RSTCAUSE_EM4WURST)
<> 144:ef7eb2e8f9f7 181 { RMU_RSTCAUSE_EM4WURST, RMU_RSTCAUSE_EM4WURST_XMASK },
<> 144:ef7eb2e8f9f7 182 #endif
<> 144:ef7eb2e8f9f7 183 #if defined(RMU_RSTCAUSE_BODAVDD0)
<> 144:ef7eb2e8f9f7 184 { RMU_RSTCAUSE_BODAVDD0, RMU_RSTCAUSE_BODAVDD0_XMASK },
<> 144:ef7eb2e8f9f7 185 #endif
<> 144:ef7eb2e8f9f7 186 #if defined(RMU_RSTCAUSE_BODAVDD1)
<> 144:ef7eb2e8f9f7 187 { RMU_RSTCAUSE_BODAVDD1, RMU_RSTCAUSE_BODAVDD1_XMASK },
<> 144:ef7eb2e8f9f7 188 #endif
<> 144:ef7eb2e8f9f7 189 #if defined(BU_PRESENT)
<> 144:ef7eb2e8f9f7 190 { RMU_RSTCAUSE_BUBODVDDDREG, RMU_RSTCAUSE_BUBODVDDDREG_XMASK },
<> 144:ef7eb2e8f9f7 191 { RMU_RSTCAUSE_BUBODBUVIN, RMU_RSTCAUSE_BUBODBUVIN_XMASK },
<> 144:ef7eb2e8f9f7 192 { RMU_RSTCAUSE_BUBODUNREG, RMU_RSTCAUSE_BUBODUNREG_XMASK },
<> 144:ef7eb2e8f9f7 193 { RMU_RSTCAUSE_BUBODREG, RMU_RSTCAUSE_BUBODREG_XMASK },
<> 144:ef7eb2e8f9f7 194 { RMU_RSTCAUSE_BUMODERST, RMU_RSTCAUSE_BUMODERST_XMASK },
<> 144:ef7eb2e8f9f7 195 #endif
<> 144:ef7eb2e8f9f7 196 };
<> 144:ef7eb2e8f9f7 197
<> 144:ef7eb2e8f9f7 198
<> 144:ef7eb2e8f9f7 199 /*******************************************************************************
<> 144:ef7eb2e8f9f7 200 ******************************** TEST ********************************
<> 144:ef7eb2e8f9f7 201 ******************************************************************************/
<> 144:ef7eb2e8f9f7 202 #if defined(EMLIB_REGRESSION_TEST)
<> 144:ef7eb2e8f9f7 203 /* Test variable that replaces the RSTCAUSE cause register when testing
<> 144:ef7eb2e8f9f7 204 the RMU_ResetCauseGet function. */
<> 144:ef7eb2e8f9f7 205 extern uint32_t rstCause;
<> 144:ef7eb2e8f9f7 206 #endif
<> 144:ef7eb2e8f9f7 207
<> 144:ef7eb2e8f9f7 208 /** @endcond */
<> 144:ef7eb2e8f9f7 209
<> 144:ef7eb2e8f9f7 210 /*******************************************************************************
<> 144:ef7eb2e8f9f7 211 ************************** GLOBAL FUNCTIONS *******************************
<> 144:ef7eb2e8f9f7 212 ******************************************************************************/
<> 144:ef7eb2e8f9f7 213
<> 144:ef7eb2e8f9f7 214 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 215 * @brief
<> 144:ef7eb2e8f9f7 216 * Disable/enable reset for various peripherals and signal sources
<> 144:ef7eb2e8f9f7 217 *
<> 144:ef7eb2e8f9f7 218 * @param[in] reset Reset types to enable/disable
<> 144:ef7eb2e8f9f7 219 *
<> 144:ef7eb2e8f9f7 220 * @param[in] mode Reset mode
<> 144:ef7eb2e8f9f7 221 ******************************************************************************/
<> 144:ef7eb2e8f9f7 222 void RMU_ResetControl(RMU_Reset_TypeDef reset, RMU_ResetMode_TypeDef mode)
<> 144:ef7eb2e8f9f7 223 {
<> 144:ef7eb2e8f9f7 224 /* Note that the RMU supports bit-band access, but not peripheral bit-field set/clear */
<> 144:ef7eb2e8f9f7 225 #if defined(_RMU_CTRL_PINRMODE_MASK)
<> 144:ef7eb2e8f9f7 226 uint32_t val;
<> 144:ef7eb2e8f9f7 227 #endif
<> 144:ef7eb2e8f9f7 228 uint32_t shift;
<> 144:ef7eb2e8f9f7 229
<> 150:02e0a0aed4ec 230 shift = SL_CTZ((uint32_t)reset);
<> 144:ef7eb2e8f9f7 231 #if defined(_RMU_CTRL_PINRMODE_MASK)
<> 144:ef7eb2e8f9f7 232 val = (uint32_t)mode << shift;
<> 144:ef7eb2e8f9f7 233 RMU->CTRL = (RMU->CTRL & ~reset) | val;
<> 144:ef7eb2e8f9f7 234 #else
<> 144:ef7eb2e8f9f7 235 BUS_RegBitWrite(&RMU->CTRL, (uint32_t)shift, mode ? 1 : 0);
<> 144:ef7eb2e8f9f7 236 #endif
<> 144:ef7eb2e8f9f7 237 }
<> 144:ef7eb2e8f9f7 238
<> 144:ef7eb2e8f9f7 239
<> 144:ef7eb2e8f9f7 240 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 241 * @brief
<> 144:ef7eb2e8f9f7 242 * Clear the reset cause register.
<> 144:ef7eb2e8f9f7 243 *
<> 144:ef7eb2e8f9f7 244 * @details
<> 144:ef7eb2e8f9f7 245 * This function clears all the reset cause bits of the RSTCAUSE register.
<> 144:ef7eb2e8f9f7 246 * The reset cause bits must be cleared by SW before a new reset occurs,
<> 144:ef7eb2e8f9f7 247 * otherwise reset causes may accumulate. See @ref RMU_ResetCauseGet().
<> 144:ef7eb2e8f9f7 248 ******************************************************************************/
<> 144:ef7eb2e8f9f7 249 void RMU_ResetCauseClear(void)
<> 144:ef7eb2e8f9f7 250 {
<> 144:ef7eb2e8f9f7 251 RMU->CMD = RMU_CMD_RCCLR;
<> 144:ef7eb2e8f9f7 252
<> 144:ef7eb2e8f9f7 253 #if defined(EMU_AUXCTRL_HRCCLR)
<> 144:ef7eb2e8f9f7 254 {
<> 144:ef7eb2e8f9f7 255 uint32_t locked;
<> 144:ef7eb2e8f9f7 256
<> 144:ef7eb2e8f9f7 257 /* Clear some reset causes not cleared with RMU CMD register */
<> 144:ef7eb2e8f9f7 258 /* (If EMU registers locked, they must be unlocked first) */
<> 144:ef7eb2e8f9f7 259 locked = EMU->LOCK & EMU_LOCK_LOCKKEY_LOCKED;
<> 144:ef7eb2e8f9f7 260 if (locked)
<> 144:ef7eb2e8f9f7 261 {
<> 144:ef7eb2e8f9f7 262 EMU_Unlock();
<> 144:ef7eb2e8f9f7 263 }
<> 144:ef7eb2e8f9f7 264
<> 144:ef7eb2e8f9f7 265 BUS_RegBitWrite(&(EMU->AUXCTRL), _EMU_AUXCTRL_HRCCLR_SHIFT, 1);
<> 144:ef7eb2e8f9f7 266 BUS_RegBitWrite(&(EMU->AUXCTRL), _EMU_AUXCTRL_HRCCLR_SHIFT, 0);
<> 144:ef7eb2e8f9f7 267
<> 144:ef7eb2e8f9f7 268 if (locked)
<> 144:ef7eb2e8f9f7 269 {
<> 144:ef7eb2e8f9f7 270 EMU_Lock();
<> 144:ef7eb2e8f9f7 271 }
<> 144:ef7eb2e8f9f7 272 }
<> 144:ef7eb2e8f9f7 273 #endif
<> 144:ef7eb2e8f9f7 274 }
<> 144:ef7eb2e8f9f7 275
<> 144:ef7eb2e8f9f7 276
<> 144:ef7eb2e8f9f7 277 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 278 * @brief
<> 144:ef7eb2e8f9f7 279 * Get the cause of the last reset.
<> 144:ef7eb2e8f9f7 280 *
<> 144:ef7eb2e8f9f7 281 * @details
<> 144:ef7eb2e8f9f7 282 * In order to be useful, the reset cause must be cleared by software before a new
<> 144:ef7eb2e8f9f7 283 * reset occurs, otherwise reset causes may accumulate. See @ref
<> 144:ef7eb2e8f9f7 284 * RMU_ResetCauseClear(). This function call will return the main cause for
<> 144:ef7eb2e8f9f7 285 * reset, which can be a bit mask (several causes), and clear away "noise".
<> 144:ef7eb2e8f9f7 286 *
<> 144:ef7eb2e8f9f7 287 * @return
<> 144:ef7eb2e8f9f7 288 * Reset cause mask. Please consult the reference manual for description
<> 144:ef7eb2e8f9f7 289 * of the reset cause mask.
<> 144:ef7eb2e8f9f7 290 ******************************************************************************/
<> 144:ef7eb2e8f9f7 291 uint32_t RMU_ResetCauseGet(void)
<> 144:ef7eb2e8f9f7 292 {
<> 150:02e0a0aed4ec 293 #define LB_CLW0 (* ((volatile uint32_t *)(LOCKBITS_BASE) + 122))
<> 150:02e0a0aed4ec 294 #define LB_CLW0_PINRESETSOFT (1 << 2)
<> 150:02e0a0aed4ec 295
<> 144:ef7eb2e8f9f7 296 #if !defined(EMLIB_REGRESSION_TEST)
<> 144:ef7eb2e8f9f7 297 uint32_t rstCause = RMU->RSTCAUSE;
<> 144:ef7eb2e8f9f7 298 #endif
<> 144:ef7eb2e8f9f7 299 uint32_t validRstCause = 0;
<> 150:02e0a0aed4ec 300 uint32_t zeroXMask;
<> 144:ef7eb2e8f9f7 301 uint32_t i;
<> 144:ef7eb2e8f9f7 302
<> 144:ef7eb2e8f9f7 303 for (i = 0; i < NUM_RSTCAUSES; i++)
<> 144:ef7eb2e8f9f7 304 {
<> 150:02e0a0aed4ec 305 zeroXMask = resetCauseMasks[i].resetCauseZeroXMask;
<> 161:2cc1468da177 306 #if defined( _SILICON_LABS_32B_SERIES_1 )
<> 150:02e0a0aed4ec 307 /* Handle soft/hard pin reset */
<> 150:02e0a0aed4ec 308 if (!(LB_CLW0 & LB_CLW0_PINRESETSOFT))
<> 150:02e0a0aed4ec 309 {
<> 150:02e0a0aed4ec 310 /* RSTCAUSE_EXTRST must be 0 if pin reset is configured as hard reset */
<> 150:02e0a0aed4ec 311 switch (resetCauseMasks[i].resetCauseMask)
<> 150:02e0a0aed4ec 312 {
<> 150:02e0a0aed4ec 313 case RMU_RSTCAUSE_LOCKUPRST:
<> 150:02e0a0aed4ec 314 /* Fallthrough */
<> 150:02e0a0aed4ec 315 case RMU_RSTCAUSE_SYSREQRST:
<> 150:02e0a0aed4ec 316 /* Fallthrough */
<> 150:02e0a0aed4ec 317 case RMU_RSTCAUSE_WDOGRST:
<> 150:02e0a0aed4ec 318 /* Fallthrough */
<> 150:02e0a0aed4ec 319 case RMU_RSTCAUSE_EM4RST:
<> 150:02e0a0aed4ec 320 zeroXMask |= RMU_RSTCAUSE_EXTRST;
<> 150:02e0a0aed4ec 321 break;
<> 150:02e0a0aed4ec 322 }
<> 150:02e0a0aed4ec 323 }
<> 150:02e0a0aed4ec 324 #endif
<> 150:02e0a0aed4ec 325
<> 150:02e0a0aed4ec 326 #if defined( _EMU_EM4CTRL_MASK ) && defined( ERRATA_FIX_EMU_E208_EN )
<> 150:02e0a0aed4ec 327 /* Ignore BOD flags impacted by EMU_E208 */
<> 150:02e0a0aed4ec 328 if (*(volatile uint32_t *)(EMU_BASE + 0x88) & (0x1 << 8))
<> 150:02e0a0aed4ec 329 {
<> 150:02e0a0aed4ec 330 zeroXMask &= ~(RMU_RSTCAUSE_DECBOD
<> 150:02e0a0aed4ec 331 | RMU_RSTCAUSE_DVDDBOD
<> 150:02e0a0aed4ec 332 | RMU_RSTCAUSE_AVDDBOD);
<> 150:02e0a0aed4ec 333 }
<> 150:02e0a0aed4ec 334 #endif
<> 150:02e0a0aed4ec 335
<> 150:02e0a0aed4ec 336 /* Check reset cause requirements. Note that a bit is "don't care" if 0 in
<> 150:02e0a0aed4ec 337 both resetCauseMask and resetCauseZeroXMask. */
<> 144:ef7eb2e8f9f7 338 if ((rstCause & resetCauseMasks[i].resetCauseMask)
<> 150:02e0a0aed4ec 339 && !(rstCause & zeroXMask))
<> 144:ef7eb2e8f9f7 340 {
<> 150:02e0a0aed4ec 341 /* Add this reset-cause to the mask of qualified reset-causes */
<> 144:ef7eb2e8f9f7 342 validRstCause |= resetCauseMasks[i].resetCauseMask;
<> 144:ef7eb2e8f9f7 343 }
<> 144:ef7eb2e8f9f7 344 }
<> 150:02e0a0aed4ec 345 #if defined( _EMU_EM4CTRL_MASK ) && defined( ERRATA_FIX_EMU_E208_EN )
<> 150:02e0a0aed4ec 346 /* Clear BOD flags impacted by EMU_E208 */
<> 150:02e0a0aed4ec 347 if (validRstCause & RMU_RSTCAUSE_EM4RST)
<> 150:02e0a0aed4ec 348 {
<> 150:02e0a0aed4ec 349 validRstCause &= ~(RMU_RSTCAUSE_DECBOD
<> 150:02e0a0aed4ec 350 | RMU_RSTCAUSE_DVDDBOD
<> 150:02e0a0aed4ec 351 | RMU_RSTCAUSE_AVDDBOD);
<> 150:02e0a0aed4ec 352 }
<> 150:02e0a0aed4ec 353 #endif
<> 144:ef7eb2e8f9f7 354 return validRstCause;
<> 144:ef7eb2e8f9f7 355 }
<> 144:ef7eb2e8f9f7 356
<> 144:ef7eb2e8f9f7 357
<> 144:ef7eb2e8f9f7 358 /** @} (end addtogroup RMU) */
<> 150:02e0a0aed4ec 359 /** @} (end addtogroup emlib) */
<> 144:ef7eb2e8f9f7 360 #endif /* defined(RMU_COUNT) && (RMU_COUNT > 0) */