mbed official
mbed library sources. Supersedes mbed-src.
Dependents: Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more
Diff: targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_eth.h
- Revision:
- 165:e614a9f1c9e2
- Parent:
- 154:37f96f9d4de2
- Child:
- 187:0387e8f68319
--- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_eth.h Wed May 10 12:06:41 2017 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_eth.h Fri May 26 12:39:01 2017 +0100
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f1xx_hal_eth.h
* @author MCD Application Team
- * @version V1.0.5
- * @date 06-December-2016
+ * @version V1.1.0
+ * @date 14-April-2017
* @brief Header file of ETH HAL module.
******************************************************************************
* @attention
@@ -58,7 +58,7 @@
/** @addtogroup ETH_Private_Macros
* @{
*/
-#define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20)
+#define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20U)
#define IS_ETH_AUTONEGOTIATION(CMD) (((CMD) == ETH_AUTONEGOTIATION_ENABLE) || \
((CMD) == ETH_AUTONEGOTIATION_DISABLE))
#define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_SPEED_10M) || \
@@ -122,7 +122,7 @@
#define IS_ETH_UNICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE) || \
((FILTER) == ETH_UNICASTFRAMESFILTER_HASHTABLE) || \
((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECT))
-#define IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFF)
+#define IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFFU)
#define IS_ETH_ZEROQUANTA_PAUSE(CMD) (((CMD) == ETH_ZEROQUANTAPAUSE_ENABLE) || \
((CMD) == ETH_ZEROQUANTAPAUSE_DISABLE))
#define IS_ETH_PAUSE_LOW_THRESHOLD(THRESHOLD) (((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS4) || \
@@ -137,7 +137,7 @@
((CMD) == ETH_TRANSMITFLOWCONTROL_DISABLE))
#define IS_ETH_VLAN_TAG_COMPARISON(COMPARISON) (((COMPARISON) == ETH_VLANTAGCOMPARISON_12BIT) || \
((COMPARISON) == ETH_VLANTAGCOMPARISON_16BIT))
-#define IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFF)
+#define IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFFU)
#define IS_ETH_MAC_ADDRESS0123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS0) || \
((ADDRESS) == ETH_MAC_ADDRESS1) || \
((ADDRESS) == ETH_MAC_ADDRESS2) || \
@@ -207,80 +207,157 @@
((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_32BEAT) || \
((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_64BEAT) || \
((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_128BEAT))
-#define IS_ETH_DMA_DESC_SKIP_LENGTH(LENGTH) ((LENGTH) <= 0x1F)
+#define IS_ETH_DMA_DESC_SKIP_LENGTH(LENGTH) ((LENGTH) <= 0x1FU)
#define IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(RATIO) (((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1) || \
((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1) || \
((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1) || \
((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1) || \
((RATIO) == ETH_DMAARBITRATION_RXPRIORTX))
-
+#define IS_ETH_DMATXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMATXDESC_OWN) || \
+ ((FLAG) == ETH_DMATXDESC_IC) || \
+ ((FLAG) == ETH_DMATXDESC_LS) || \
+ ((FLAG) == ETH_DMATXDESC_FS) || \
+ ((FLAG) == ETH_DMATXDESC_DC) || \
+ ((FLAG) == ETH_DMATXDESC_DP) || \
+ ((FLAG) == ETH_DMATXDESC_TTSE) || \
+ ((FLAG) == ETH_DMATXDESC_TER) || \
+ ((FLAG) == ETH_DMATXDESC_TCH) || \
+ ((FLAG) == ETH_DMATXDESC_TTSS) || \
+ ((FLAG) == ETH_DMATXDESC_IHE) || \
+ ((FLAG) == ETH_DMATXDESC_ES) || \
+ ((FLAG) == ETH_DMATXDESC_JT) || \
+ ((FLAG) == ETH_DMATXDESC_FF) || \
+ ((FLAG) == ETH_DMATXDESC_PCE) || \
+ ((FLAG) == ETH_DMATXDESC_LCA) || \
+ ((FLAG) == ETH_DMATXDESC_NC) || \
+ ((FLAG) == ETH_DMATXDESC_LCO) || \
+ ((FLAG) == ETH_DMATXDESC_EC) || \
+ ((FLAG) == ETH_DMATXDESC_VF) || \
+ ((FLAG) == ETH_DMATXDESC_CC) || \
+ ((FLAG) == ETH_DMATXDESC_ED) || \
+ ((FLAG) == ETH_DMATXDESC_UF) || \
+ ((FLAG) == ETH_DMATXDESC_DB))
#define IS_ETH_DMA_TXDESC_SEGMENT(SEGMENT) (((SEGMENT) == ETH_DMATXDESC_LASTSEGMENTS) || \
((SEGMENT) == ETH_DMATXDESC_FIRSTSEGMENT))
#define IS_ETH_DMA_TXDESC_CHECKSUM(CHECKSUM) (((CHECKSUM) == ETH_DMATXDESC_CHECKSUMBYPASS) || \
((CHECKSUM) == ETH_DMATXDESC_CHECKSUMIPV4HEADER) || \
((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT) || \
((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL))
-#define IS_ETH_DMATXDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFF)
-
+#define IS_ETH_DMATXDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFFU)
+#define IS_ETH_DMARXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMARXDESC_OWN) || \
+ ((FLAG) == ETH_DMARXDESC_AFM) || \
+ ((FLAG) == ETH_DMARXDESC_ES) || \
+ ((FLAG) == ETH_DMARXDESC_DE) || \
+ ((FLAG) == ETH_DMARXDESC_SAF) || \
+ ((FLAG) == ETH_DMARXDESC_LE) || \
+ ((FLAG) == ETH_DMARXDESC_OE) || \
+ ((FLAG) == ETH_DMARXDESC_VLAN) || \
+ ((FLAG) == ETH_DMARXDESC_FS) || \
+ ((FLAG) == ETH_DMARXDESC_LS) || \
+ ((FLAG) == ETH_DMARXDESC_IPV4HCE) || \
+ ((FLAG) == ETH_DMARXDESC_LC) || \
+ ((FLAG) == ETH_DMARXDESC_FT) || \
+ ((FLAG) == ETH_DMARXDESC_RWT) || \
+ ((FLAG) == ETH_DMARXDESC_RE) || \
+ ((FLAG) == ETH_DMARXDESC_DBE) || \
+ ((FLAG) == ETH_DMARXDESC_CE) || \
+ ((FLAG) == ETH_DMARXDESC_MAMPCE))
#define IS_ETH_DMA_RXDESC_BUFFER(BUFFER) (((BUFFER) == ETH_DMARXDESC_BUFFER1) || \
((BUFFER) == ETH_DMARXDESC_BUFFER2))
-
+#define IS_ETH_PMT_GET_FLAG(FLAG) (((FLAG) == ETH_PMT_FLAG_WUFR) || \
+ ((FLAG) == ETH_PMT_FLAG_MPR))
+#define IS_ETH_DMA_FLAG(FLAG) ((((FLAG) & 0xC7FE1800U) == 0x00U) && ((FLAG) != 0x00U))
+#define IS_ETH_DMA_GET_FLAG(FLAG) (((FLAG) == ETH_DMA_FLAG_TST) || ((FLAG) == ETH_DMA_FLAG_PMT) || \
+ ((FLAG) == ETH_DMA_FLAG_MMC) || ((FLAG) == ETH_DMA_FLAG_DATATRANSFERERROR) || \
+ ((FLAG) == ETH_DMA_FLAG_READWRITEERROR) || ((FLAG) == ETH_DMA_FLAG_ACCESSERROR) || \
+ ((FLAG) == ETH_DMA_FLAG_NIS) || ((FLAG) == ETH_DMA_FLAG_AIS) || \
+ ((FLAG) == ETH_DMA_FLAG_ER) || ((FLAG) == ETH_DMA_FLAG_FBE) || \
+ ((FLAG) == ETH_DMA_FLAG_ET) || ((FLAG) == ETH_DMA_FLAG_RWT) || \
+ ((FLAG) == ETH_DMA_FLAG_RPS) || ((FLAG) == ETH_DMA_FLAG_RBU) || \
+ ((FLAG) == ETH_DMA_FLAG_R) || ((FLAG) == ETH_DMA_FLAG_TU) || \
+ ((FLAG) == ETH_DMA_FLAG_RO) || ((FLAG) == ETH_DMA_FLAG_TJT) || \
+ ((FLAG) == ETH_DMA_FLAG_TBU) || ((FLAG) == ETH_DMA_FLAG_TPS) || \
+ ((FLAG) == ETH_DMA_FLAG_T))
+#define IS_ETH_MAC_IT(IT) ((((IT) & 0xFFFFFDF1U) == 0x00U) && ((IT) != 0x00U))
+#define IS_ETH_MAC_GET_IT(IT) (((IT) == ETH_MAC_IT_TST) || ((IT) == ETH_MAC_IT_MMCT) || \
+ ((IT) == ETH_MAC_IT_MMCR) || ((IT) == ETH_MAC_IT_MMC) || \
+ ((IT) == ETH_MAC_IT_PMT))
+#define IS_ETH_MAC_GET_FLAG(FLAG) (((FLAG) == ETH_MAC_FLAG_TST) || ((FLAG) == ETH_MAC_FLAG_MMCT) || \
+ ((FLAG) == ETH_MAC_FLAG_MMCR) || ((FLAG) == ETH_MAC_FLAG_MMC) || \
+ ((FLAG) == ETH_MAC_FLAG_PMT))
+#define IS_ETH_DMA_IT(IT) ((((IT) & 0xC7FE1800U) == 0x00U) && ((IT) != 0x00U))
+#define IS_ETH_DMA_GET_IT(IT) (((IT) == ETH_DMA_IT_TST) || ((IT) == ETH_DMA_IT_PMT) || \
+ ((IT) == ETH_DMA_IT_MMC) || ((IT) == ETH_DMA_IT_NIS) || \
+ ((IT) == ETH_DMA_IT_AIS) || ((IT) == ETH_DMA_IT_ER) || \
+ ((IT) == ETH_DMA_IT_FBE) || ((IT) == ETH_DMA_IT_ET) || \
+ ((IT) == ETH_DMA_IT_RWT) || ((IT) == ETH_DMA_IT_RPS) || \
+ ((IT) == ETH_DMA_IT_RBU) || ((IT) == ETH_DMA_IT_R) || \
+ ((IT) == ETH_DMA_IT_TU) || ((IT) == ETH_DMA_IT_RO) || \
+ ((IT) == ETH_DMA_IT_TJT) || ((IT) == ETH_DMA_IT_TBU) || \
+ ((IT) == ETH_DMA_IT_TPS) || ((IT) == ETH_DMA_IT_T))
#define IS_ETH_DMA_GET_OVERFLOW(OVERFLOW) (((OVERFLOW) == ETH_DMA_OVERFLOW_RXFIFOCOUNTER) || \
((OVERFLOW) == ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER))
+#define IS_ETH_MMC_IT(IT) (((((IT) & 0xFFDF3FFFU) == 0x00U) || (((IT) & 0xEFFDFF9FU) == 0x00U)) && \
+ ((IT) != 0x00U))
+#define IS_ETH_MMC_GET_IT(IT) (((IT) == ETH_MMC_IT_TGF) || ((IT) == ETH_MMC_IT_TGFMSC) || \
+ ((IT) == ETH_MMC_IT_TGFSC) || ((IT) == ETH_MMC_IT_RGUF) || \
+ ((IT) == ETH_MMC_IT_RFAE) || ((IT) == ETH_MMC_IT_RFCE))
+#define IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(CMD) (((CMD) == ETH_DMAENHANCEDDESCRIPTOR_ENABLE) || \
+ ((CMD) == ETH_DMAENHANCEDDESCRIPTOR_DISABLE))
/**
* @}
*/
-/** @addtogroup ETH_Private_Constants
+/** @addtogroup ETH_Private_Defines
* @{
*/
/* Delay to wait when writing to some Ethernet registers */
-#define ETH_REG_WRITE_DELAY ((uint32_t)0x00000001)
+#define ETH_REG_WRITE_DELAY 0x00000001U
/* ETHERNET Errors */
-#define ETH_SUCCESS ((uint32_t)0)
-#define ETH_ERROR ((uint32_t)1)
+#define ETH_SUCCESS 0U
+#define ETH_ERROR 1U
/* ETHERNET DMA Tx descriptors Collision Count Shift */
-#define ETH_DMATXDESC_COLLISION_COUNTSHIFT ((uint32_t)3)
+#define ETH_DMATXDESC_COLLISION_COUNTSHIFT 3U
/* ETHERNET DMA Tx descriptors Buffer2 Size Shift */
-#define ETH_DMATXDESC_BUFFER2_SIZESHIFT ((uint32_t)16)
+#define ETH_DMATXDESC_BUFFER2_SIZESHIFT 16U
/* ETHERNET DMA Rx descriptors Frame Length Shift */
-#define ETH_DMARXDESC_FRAME_LENGTHSHIFT ((uint32_t)16)
+#define ETH_DMARXDESC_FRAME_LENGTHSHIFT 16U
/* ETHERNET DMA Rx descriptors Buffer2 Size Shift */
-#define ETH_DMARXDESC_BUFFER2_SIZESHIFT ((uint32_t)16)
+#define ETH_DMARXDESC_BUFFER2_SIZESHIFT 16U
/* ETHERNET DMA Rx descriptors Frame length Shift */
-#define ETH_DMARXDESC_FRAMELENGTHSHIFT ((uint32_t)16)
+#define ETH_DMARXDESC_FRAMELENGTHSHIFT 16U
/* ETHERNET MAC address offsets */
-#define ETH_MAC_ADDR_HBASE (uint32_t)(ETH_MAC_BASE + (uint32_t)0x40) /* ETHERNET MAC address high offset */
-#define ETH_MAC_ADDR_LBASE (uint32_t)(ETH_MAC_BASE + (uint32_t)0x44) /* ETHERNET MAC address low offset */
+#define ETH_MAC_ADDR_HBASE (uint32_t)(ETH_MAC_BASE + 0x40U) /* ETHERNET MAC address high offset */
+#define ETH_MAC_ADDR_LBASE (uint32_t)(ETH_MAC_BASE + 0x44U) /* ETHERNET MAC address low offset */
/* ETHERNET MACMIIAR register Mask */
-#define ETH_MACMIIAR_CR_MASK ((uint32_t)0xFFFFFFE3)
+#define ETH_MACMIIAR_CR_MASK 0xFFFFFFE3U
/* ETHERNET MACCR register Mask */
-#define ETH_MACCR_CLEAR_MASK ((uint32_t)0xFF20810F)
+#define ETH_MACCR_CLEAR_MASK 0xFF20810FU
/* ETHERNET MACFCR register Mask */
-#define ETH_MACFCR_CLEAR_MASK ((uint32_t)0x0000FF41)
+#define ETH_MACFCR_CLEAR_MASK 0x0000FF41U
/* ETHERNET DMAOMR register Mask */
-#define ETH_DMAOMR_CLEAR_MASK ((uint32_t)0xF8DE3F23)
+#define ETH_DMAOMR_CLEAR_MASK 0xF8DE3F23U
/* ETHERNET Remote Wake-up frame register length */
-#define ETH_WAKEUP_REGISTER_LENGTH 8
+#define ETH_WAKEUP_REGISTER_LENGTH 8U
/* ETHERNET Missed frames counter Shift */
-#define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT 17
+#define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT 17U
/**
* @}
- */
+ */
/* Exported types ------------------------------------------------------------*/
/** @defgroup ETH_Exported_Types ETH Exported Types
@@ -292,16 +369,16 @@
*/
typedef enum
{
- HAL_ETH_STATE_RESET = 0x00, /*!< Peripheral not yet Initialized or disabled */
- HAL_ETH_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
- HAL_ETH_STATE_BUSY = 0x02, /*!< an internal process is ongoing */
- HAL_ETH_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */
- HAL_ETH_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */
- HAL_ETH_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */
- HAL_ETH_STATE_BUSY_WR = 0x42, /*!< Write process is ongoing */
- HAL_ETH_STATE_BUSY_RD = 0x82, /*!< Read process is ongoing */
- HAL_ETH_STATE_TIMEOUT = 0x03, /*!< Timeout state */
- HAL_ETH_STATE_ERROR = 0x04 /*!< Reception process is ongoing */
+ HAL_ETH_STATE_RESET = 0x00U, /*!< Peripheral not yet Initialized or disabled */
+ HAL_ETH_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
+ HAL_ETH_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */
+ HAL_ETH_STATE_BUSY_TX = 0x12U, /*!< Data Transmission process is ongoing */
+ HAL_ETH_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */
+ HAL_ETH_STATE_BUSY_TX_RX = 0x32U, /*!< Data Transmission and Reception process is ongoing */
+ HAL_ETH_STATE_BUSY_WR = 0x42U, /*!< Write process is ongoing */
+ HAL_ETH_STATE_BUSY_RD = 0x82U, /*!< Read process is ongoing */
+ HAL_ETH_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
+ HAL_ETH_STATE_ERROR = 0x04U /*!< Reception process is ongoing */
}HAL_ETH_StateTypeDef;
/**
@@ -332,7 +409,7 @@
uint32_t ChecksumMode; /*!< Selects if the checksum is check by hardware or by software.
This parameter can be a value of @ref ETH_Checksum_Mode */
- uint32_t MediaInterface ; /*!< Selects the media-independent interface or the reduced media-independent interface.
+ uint32_t MediaInterface; /*!< Selects the media-independent interface or the reduced media-independent interface.
This parameter can be a value of @ref ETH_Media_Interface */
} ETH_InitTypeDef;
@@ -387,10 +464,10 @@
uint32_t ReceiveAll; /*!< Selects or not all frames reception by the MAC (No filtering).
This parameter can be a value of @ref ETH_Receive_All */
- uint32_t SourceAddrFilter; /*!< Selects the Source Address Filter mode.
- This parameter can be a value of @ref ETH_Source_Addr_Filter */
+ uint32_t SourceAddrFilter; /*!< Selects the Source Address Filter mode.
+ This parameter can be a value of @ref ETH_Source_Addr_Filter */
- uint32_t PassControlFrames; /*!< Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames)
+ uint32_t PassControlFrames; /*!< Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames)
This parameter can be a value of @ref ETH_Pass_Control_Frames */
uint32_t BroadcastFramesReception; /*!< Selects or not the reception of Broadcast Frames.
@@ -409,13 +486,13 @@
This parameter can be a value of @ref ETH_Unicast_Frames_Filter */
uint32_t HashTableHigh; /*!< This field holds the higher 32 bits of Hash table.
- This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */
+ This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFFU */
uint32_t HashTableLow; /*!< This field holds the lower 32 bits of Hash table.
- This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */
+ This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFFU */
uint32_t PauseTime; /*!< This field holds the value to be used in the Pause Time field in the transmit control frame.
- This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFF */
+ This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFU */
uint32_t ZeroQuantaPause; /*!< Selects or not the automatic generation of Zero-Quanta Pause Control frames.
This parameter can be a value of @ref ETH_Zero_Quanta_Pause */
@@ -423,7 +500,7 @@
uint32_t PauseLowThreshold; /*!< This field configures the threshold of the PAUSE to be checked for
automatic retransmission of PAUSE Frame.
This parameter can be a value of @ref ETH_Pause_Low_Threshold */
-
+
uint32_t UnicastPauseFrameDetect; /*!< Selects or not the MAC detection of the Pause frames (with MAC Address0
unicast address and unique multicast address).
This parameter can be a value of @ref ETH_Unicast_Pause_Frame_Detect */
@@ -444,7 +521,6 @@
} ETH_MACInitTypeDef;
-
/**
* @brief ETH DMA Configuration Structure definition
*/
@@ -485,7 +561,7 @@
uint32_t FixedBurst; /*!< Enables or disables the AHB Master interface fixed burst transfers.
This parameter can be a value of @ref ETH_Fixed_Burst */
-
+
uint32_t RxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction.
This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */
@@ -493,7 +569,7 @@
This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */
uint32_t DescriptorSkipLength; /*!< Specifies the number of word to skip between two unchained descriptors (Ring mode)
- This parameter must be a number between Min_Data = 0 and Max_Data = 32 */
+ This parameter must be a number between Min_Data = 0 and Max_Data = 32 */
uint32_t DMAArbitration; /*!< Selects the DMA Tx/Rx arbitration.
This parameter can be a value of @ref ETH_DMA_Arbitration */
@@ -516,7 +592,6 @@
} ETH_DMADescTypeDef;
-
/**
* @brief Received Frame Informations structure definition
*/
@@ -534,7 +609,6 @@
} ETH_DMARxFrameInfos;
-
/**
* @brief ETH Handle Structure definition
*/
@@ -571,14 +645,14 @@
/** @defgroup ETH_Buffers_setting ETH Buffers setting
* @{
*/
-#define ETH_MAX_PACKET_SIZE ((uint32_t)1524) /*!< ETH_HEADER + ETH_EXTRA + ETH_VLAN_TAG + ETH_MAX_ETH_PAYLOAD + ETH_CRC */
-#define ETH_HEADER ((uint32_t)14) /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */
-#define ETH_CRC ((uint32_t)4) /*!< Ethernet CRC */
-#define ETH_EXTRA ((uint32_t)2) /*!< Extra bytes in some cases */
-#define ETH_VLAN_TAG ((uint32_t)4) /*!< optional 802.1q VLAN Tag */
-#define ETH_MIN_ETH_PAYLOAD ((uint32_t)46) /*!< Minimum Ethernet payload size */
-#define ETH_MAX_ETH_PAYLOAD ((uint32_t)1500) /*!< Maximum Ethernet payload size */
-#define ETH_JUMBO_FRAME_PAYLOAD ((uint32_t)9000) /*!< Jumbo frame payload size */
+#define ETH_MAX_PACKET_SIZE 1524U /*!< ETH_HEADER + ETH_EXTRA + ETH_VLAN_TAG + ETH_MAX_ETH_PAYLOAD + ETH_CRC */
+#define ETH_HEADER 14U /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */
+#define ETH_CRC 4U /*!< Ethernet CRC */
+#define ETH_EXTRA 2U /*!< Extra bytes in some cases */
+#define ETH_VLAN_TAG 4U /*!< optional 802.1q VLAN Tag */
+#define ETH_MIN_ETH_PAYLOAD 46U /*!< Minimum Ethernet payload size */
+#define ETH_MAX_ETH_PAYLOAD 1500U /*!< Maximum Ethernet payload size */
+#define ETH_JUMBO_FRAME_PAYLOAD 9000U /*!< Jumbo frame payload size */
/* Ethernet driver receive buffers are organized in a chained linked-list, when
an ethernet packet is received, the Rx-DMA will transfer the packet from RxFIFO
@@ -603,7 +677,7 @@
/* 5 Ethernet driver receive buffers are used (in a chained linked list)*/
#ifndef ETH_RXBUFNB
- #define ETH_RXBUFNB ((uint32_t)5 /* 5 Rx buffers of size ETH_RX_BUF_SIZE */
+ #define ETH_RXBUFNB 5U /* 5 Rx buffers of size ETH_RX_BUF_SIZE */
#endif
@@ -630,7 +704,7 @@
/* 5 ethernet driver transmit buffers are used (in a chained linked list)*/
#ifndef ETH_TXBUFNB
- #define ETH_TXBUFNB ((uint32_t)5 /* 5 Tx buffers of size ETH_TX_BUF_SIZE */
+ #define ETH_TXBUFNB 5U /* 5 Tx buffers of size ETH_TX_BUF_SIZE */
#endif
/**
@@ -642,7 +716,7 @@
*/
/*
- DMA Tx Desciptor
+ DMA Tx Descriptor
-----------------------------------------------------------------------------------------------
TDES0 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] |
-----------------------------------------------------------------------------------------------
@@ -657,56 +731,56 @@
/**
* @brief Bit definition of TDES0 register: DMA Tx descriptor status register
*/
-#define ETH_DMATXDESC_OWN ((uint32_t)0x80000000) /*!< OWN bit: descriptor is owned by DMA engine */
-#define ETH_DMATXDESC_IC ((uint32_t)0x40000000) /*!< Interrupt on Completion */
-#define ETH_DMATXDESC_LS ((uint32_t)0x20000000) /*!< Last Segment */
-#define ETH_DMATXDESC_FS ((uint32_t)0x10000000) /*!< First Segment */
-#define ETH_DMATXDESC_DC ((uint32_t)0x08000000) /*!< Disable CRC */
-#define ETH_DMATXDESC_DP ((uint32_t)0x04000000) /*!< Disable Padding */
-#define ETH_DMATXDESC_TTSE ((uint32_t)0x02000000) /*!< Transmit Time Stamp Enable */
-#define ETH_DMATXDESC_CIC ((uint32_t)0x00C00000) /*!< Checksum Insertion Control: 4 cases */
-#define ETH_DMATXDESC_CIC_BYPASS ((uint32_t)0x00000000) /*!< Do Nothing: Checksum Engine is bypassed */
-#define ETH_DMATXDESC_CIC_IPV4HEADER ((uint32_t)0x00400000) /*!< IPV4 header Checksum Insertion */
-#define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT ((uint32_t)0x00800000) /*!< TCP/UDP/ICMP Checksum Insertion calculated over segment only */
-#define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL ((uint32_t)0x00C00000) /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */
-#define ETH_DMATXDESC_TER ((uint32_t)0x00200000) /*!< Transmit End of Ring */
-#define ETH_DMATXDESC_TCH ((uint32_t)0x00100000) /*!< Second Address Chained */
-#define ETH_DMATXDESC_TTSS ((uint32_t)0x00020000) /*!< Tx Time Stamp Status */
-#define ETH_DMATXDESC_IHE ((uint32_t)0x00010000) /*!< IP Header Error */
-#define ETH_DMATXDESC_ES ((uint32_t)0x00008000) /*!< Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT */
-#define ETH_DMATXDESC_JT ((uint32_t)0x00004000) /*!< Jabber Timeout */
-#define ETH_DMATXDESC_FF ((uint32_t)0x00002000) /*!< Frame Flushed: DMA/MTL flushed the frame due to SW flush */
-#define ETH_DMATXDESC_PCE ((uint32_t)0x00001000) /*!< Payload Checksum Error */
-#define ETH_DMATXDESC_LCA ((uint32_t)0x00000800) /*!< Loss of Carrier: carrier lost during transmission */
-#define ETH_DMATXDESC_NC ((uint32_t)0x00000400) /*!< No Carrier: no carrier signal from the transceiver */
-#define ETH_DMATXDESC_LCO ((uint32_t)0x00000200) /*!< Late Collision: transmission aborted due to collision */
-#define ETH_DMATXDESC_EC ((uint32_t)0x00000100) /*!< Excessive Collision: transmission aborted after 16 collisions */
-#define ETH_DMATXDESC_VF ((uint32_t)0x00000080) /*!< VLAN Frame */
-#define ETH_DMATXDESC_CC ((uint32_t)0x00000078) /*!< Collision Count */
-#define ETH_DMATXDESC_ED ((uint32_t)0x00000004) /*!< Excessive Deferral */
-#define ETH_DMATXDESC_UF ((uint32_t)0x00000002) /*!< Underflow Error: late data arrival from the memory */
-#define ETH_DMATXDESC_DB ((uint32_t)0x00000001) /*!< Deferred Bit */
+#define ETH_DMATXDESC_OWN 0x80000000U /*!< OWN bit: descriptor is owned by DMA engine */
+#define ETH_DMATXDESC_IC 0x40000000U /*!< Interrupt on Completion */
+#define ETH_DMATXDESC_LS 0x20000000U /*!< Last Segment */
+#define ETH_DMATXDESC_FS 0x10000000U /*!< First Segment */
+#define ETH_DMATXDESC_DC 0x08000000U /*!< Disable CRC */
+#define ETH_DMATXDESC_DP 0x04000000U /*!< Disable Padding */
+#define ETH_DMATXDESC_TTSE 0x02000000U /*!< Transmit Time Stamp Enable */
+#define ETH_DMATXDESC_CIC 0x00C00000U /*!< Checksum Insertion Control: 4 cases */
+#define ETH_DMATXDESC_CIC_BYPASS 0x00000000U /*!< Do Nothing: Checksum Engine is bypassed */
+#define ETH_DMATXDESC_CIC_IPV4HEADER 0x00400000U /*!< IPV4 header Checksum Insertion */
+#define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT 0x00800000U /*!< TCP/UDP/ICMP Checksum Insertion calculated over segment only */
+#define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL 0x00C00000U /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */
+#define ETH_DMATXDESC_TER 0x00200000U /*!< Transmit End of Ring */
+#define ETH_DMATXDESC_TCH 0x00100000U /*!< Second Address Chained */
+#define ETH_DMATXDESC_TTSS 0x00020000U /*!< Tx Time Stamp Status */
+#define ETH_DMATXDESC_IHE 0x00010000U /*!< IP Header Error */
+#define ETH_DMATXDESC_ES 0x00008000U /*!< Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT */
+#define ETH_DMATXDESC_JT 0x00004000U /*!< Jabber Timeout */
+#define ETH_DMATXDESC_FF 0x00002000U /*!< Frame Flushed: DMA/MTL flushed the frame due to SW flush */
+#define ETH_DMATXDESC_PCE 0x00001000U /*!< Payload Checksum Error */
+#define ETH_DMATXDESC_LCA 0x00000800U /*!< Loss of Carrier: carrier lost during transmission */
+#define ETH_DMATXDESC_NC 0x00000400U /*!< No Carrier: no carrier signal from the transceiver */
+#define ETH_DMATXDESC_LCO 0x00000200U /*!< Late Collision: transmission aborted due to collision */
+#define ETH_DMATXDESC_EC 0x00000100U /*!< Excessive Collision: transmission aborted after 16 collisions */
+#define ETH_DMATXDESC_VF 0x00000080U /*!< VLAN Frame */
+#define ETH_DMATXDESC_CC 0x00000078U /*!< Collision Count */
+#define ETH_DMATXDESC_ED 0x00000004U /*!< Excessive Deferral */
+#define ETH_DMATXDESC_UF 0x00000002U /*!< Underflow Error: late data arrival from the memory */
+#define ETH_DMATXDESC_DB 0x00000001U /*!< Deferred Bit */
/**
* @brief Bit definition of TDES1 register
*/
-#define ETH_DMATXDESC_TBS2 ((uint32_t)0x1FFF0000) /*!< Transmit Buffer2 Size */
-#define ETH_DMATXDESC_TBS1 ((uint32_t)0x00001FFF) /*!< Transmit Buffer1 Size */
+#define ETH_DMATXDESC_TBS2 0x1FFF0000U /*!< Transmit Buffer2 Size */
+#define ETH_DMATXDESC_TBS1 0x00001FFFU /*!< Transmit Buffer1 Size */
/**
* @brief Bit definition of TDES2 register
*/
-#define ETH_DMATXDESC_B1AP ((uint32_t)0xFFFFFFFF) /*!< Buffer1 Address Pointer */
+#define ETH_DMATXDESC_B1AP 0xFFFFFFFFU /*!< Buffer1 Address Pointer */
/**
* @brief Bit definition of TDES3 register
*/
-#define ETH_DMATXDESC_B2AP ((uint32_t)0xFFFFFFFF) /*!< Buffer2 Address Pointer */
+#define ETH_DMATXDESC_B2AP 0xFFFFFFFFU /*!< Buffer2 Address Pointer */
/**
* @}
*/
-/** @defgroup ETH_DMA_RX_Descriptor ETH DMA RX Descriptor
+/** @defgroup ETH_DMA_RX_Descriptor ETH DMA RX Descriptor
* @{
*/
@@ -726,44 +800,44 @@
/**
* @brief Bit definition of RDES0 register: DMA Rx descriptor status register
*/
-#define ETH_DMARXDESC_OWN ((uint32_t)0x80000000) /*!< OWN bit: descriptor is owned by DMA engine */
-#define ETH_DMARXDESC_AFM ((uint32_t)0x40000000) /*!< DA Filter Fail for the rx frame */
-#define ETH_DMARXDESC_FL ((uint32_t)0x3FFF0000) /*!< Receive descriptor frame length */
-#define ETH_DMARXDESC_ES ((uint32_t)0x00008000) /*!< Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */
-#define ETH_DMARXDESC_DE ((uint32_t)0x00004000) /*!< Descriptor error: no more descriptors for receive frame */
-#define ETH_DMARXDESC_SAF ((uint32_t)0x00002000) /*!< SA Filter Fail for the received frame */
-#define ETH_DMARXDESC_LE ((uint32_t)0x00001000) /*!< Frame size not matching with length field */
-#define ETH_DMARXDESC_OE ((uint32_t)0x00000800) /*!< Overflow Error: Frame was damaged due to buffer overflow */
-#define ETH_DMARXDESC_VLAN ((uint32_t)0x00000400) /*!< VLAN Tag: received frame is a VLAN frame */
-#define ETH_DMARXDESC_FS ((uint32_t)0x00000200) /*!< First descriptor of the frame */
-#define ETH_DMARXDESC_LS ((uint32_t)0x00000100) /*!< Last descriptor of the frame */
-#define ETH_DMARXDESC_IPV4HCE ((uint32_t)0x00000080) /*!< IPC Checksum Error: Rx Ipv4 header checksum error */
-#define ETH_DMARXDESC_LC ((uint32_t)0x00000040) /*!< Late collision occurred during reception */
-#define ETH_DMARXDESC_FT ((uint32_t)0x00000020) /*!< Frame type - Ethernet, otherwise 802.3 */
-#define ETH_DMARXDESC_RWT ((uint32_t)0x00000010) /*!< Receive Watchdog Timeout: watchdog timer expired during reception */
-#define ETH_DMARXDESC_RE ((uint32_t)0x00000008) /*!< Receive error: error reported by MII interface */
-#define ETH_DMARXDESC_DBE ((uint32_t)0x00000004) /*!< Dribble bit error: frame contains non int multiple of 8 bits */
-#define ETH_DMARXDESC_CE ((uint32_t)0x00000002) /*!< CRC error */
-#define ETH_DMARXDESC_MAMPCE ((uint32_t)0x00000001) /*!< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */
+#define ETH_DMARXDESC_OWN 0x80000000U /*!< OWN bit: descriptor is owned by DMA engine */
+#define ETH_DMARXDESC_AFM 0x40000000U /*!< DA Filter Fail for the rx frame */
+#define ETH_DMARXDESC_FL 0x3FFF0000U /*!< Receive descriptor frame length */
+#define ETH_DMARXDESC_ES 0x00008000U /*!< Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */
+#define ETH_DMARXDESC_DE 0x00004000U /*!< Descriptor error: no more descriptors for receive frame */
+#define ETH_DMARXDESC_SAF 0x00002000U /*!< SA Filter Fail for the received frame */
+#define ETH_DMARXDESC_LE 0x00001000U /*!< Frame size not matching with length field */
+#define ETH_DMARXDESC_OE 0x00000800U /*!< Overflow Error: Frame was damaged due to buffer overflow */
+#define ETH_DMARXDESC_VLAN 0x00000400U /*!< VLAN Tag: received frame is a VLAN frame */
+#define ETH_DMARXDESC_FS 0x00000200U /*!< First descriptor of the frame */
+#define ETH_DMARXDESC_LS 0x00000100U /*!< Last descriptor of the frame */
+#define ETH_DMARXDESC_IPV4HCE 0x00000080U /*!< IPC Checksum Error: Rx Ipv4 header checksum error */
+#define ETH_DMARXDESC_LC 0x00000040U /*!< Late collision occurred during reception */
+#define ETH_DMARXDESC_FT 0x00000020U /*!< Frame type - Ethernet, otherwise 802.3 */
+#define ETH_DMARXDESC_RWT 0x00000010U /*!< Receive Watchdog Timeout: watchdog timer expired during reception */
+#define ETH_DMARXDESC_RE 0x00000008U /*!< Receive error: error reported by MII interface */
+#define ETH_DMARXDESC_DBE 0x00000004U /*!< Dribble bit error: frame contains non int multiple of 8 bits */
+#define ETH_DMARXDESC_CE 0x00000002U /*!< CRC error */
+#define ETH_DMARXDESC_MAMPCE 0x00000001U /*!< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */
/**
* @brief Bit definition of RDES1 register
*/
-#define ETH_DMARXDESC_DIC ((uint32_t)0x80000000) /*!< Disable Interrupt on Completion */
-#define ETH_DMARXDESC_RBS2 ((uint32_t)0x1FFF0000) /*!< Receive Buffer2 Size */
-#define ETH_DMARXDESC_RER ((uint32_t)0x00008000) /*!< Receive End of Ring */
-#define ETH_DMARXDESC_RCH ((uint32_t)0x00004000) /*!< Second Address Chained */
-#define ETH_DMARXDESC_RBS1 ((uint32_t)0x00001FFF) /*!< Receive Buffer1 Size */
+#define ETH_DMARXDESC_DIC 0x80000000U /*!< Disable Interrupt on Completion */
+#define ETH_DMARXDESC_RBS2 0x1FFF0000U /*!< Receive Buffer2 Size */
+#define ETH_DMARXDESC_RER 0x00008000U /*!< Receive End of Ring */
+#define ETH_DMARXDESC_RCH 0x00004000U /*!< Second Address Chained */
+#define ETH_DMARXDESC_RBS1 0x00001FFFU /*!< Receive Buffer1 Size */
/**
* @brief Bit definition of RDES2 register
*/
-#define ETH_DMARXDESC_B1AP ((uint32_t)0xFFFFFFFF) /*!< Buffer1 Address Pointer */
+#define ETH_DMARXDESC_B1AP 0xFFFFFFFFU /*!< Buffer1 Address Pointer */
/**
* @brief Bit definition of RDES3 register
*/
-#define ETH_DMARXDESC_B2AP ((uint32_t)0xFFFFFFFF) /*!< Buffer2 Address Pointer */
+#define ETH_DMARXDESC_B2AP 0xFFFFFFFFU /*!< Buffer2 Address Pointer */
/**
* @}
@@ -771,8 +845,8 @@
/** @defgroup ETH_AutoNegotiation ETH AutoNegotiation
* @{
*/
-#define ETH_AUTONEGOTIATION_ENABLE ((uint32_t)0x00000001)
-#define ETH_AUTONEGOTIATION_DISABLE ((uint32_t)0x00000000)
+#define ETH_AUTONEGOTIATION_ENABLE 0x00000001U
+#define ETH_AUTONEGOTIATION_DISABLE 0x00000000U
/**
* @}
@@ -780,25 +854,25 @@
/** @defgroup ETH_Speed ETH Speed
* @{
*/
-#define ETH_SPEED_10M ((uint32_t)0x00000000)
-#define ETH_SPEED_100M ((uint32_t)0x00004000)
+#define ETH_SPEED_10M 0x00000000U
+#define ETH_SPEED_100M 0x00004000U
/**
* @}
*/
-/** @defgroup ETH_Duplex_Mode ETH Duplex Mode
+/** @defgroup ETH_Duplex_Mode ETH Duplex Mode
* @{
*/
-#define ETH_MODE_FULLDUPLEX ((uint32_t)0x00000800)
-#define ETH_MODE_HALFDUPLEX ((uint32_t)0x00000000)
+#define ETH_MODE_FULLDUPLEX 0x00000800U
+#define ETH_MODE_HALFDUPLEX 0x00000000U
/**
* @}
*/
-/** @defgroup ETH_Rx_Mode ETH Rx Mode
+/** @defgroup ETH_Rx_Mode ETH Rx Mode
* @{
*/
-#define ETH_RXPOLLING_MODE ((uint32_t)0x00000000)
-#define ETH_RXINTERRUPT_MODE ((uint32_t)0x00000001)
+#define ETH_RXPOLLING_MODE 0x00000000U
+#define ETH_RXINTERRUPT_MODE 0x00000001U
/**
* @}
*/
@@ -806,8 +880,8 @@
/** @defgroup ETH_Checksum_Mode ETH Checksum Mode
* @{
*/
-#define ETH_CHECKSUM_BY_HARDWARE ((uint32_t)0x00000000)
-#define ETH_CHECKSUM_BY_SOFTWARE ((uint32_t)0x00000001)
+#define ETH_CHECKSUM_BY_HARDWARE 0x00000000U
+#define ETH_CHECKSUM_BY_SOFTWARE 0x00000001U
/**
* @}
*/
@@ -815,7 +889,7 @@
/** @defgroup ETH_Media_Interface ETH Media Interface
* @{
*/
-#define ETH_MEDIA_INTERFACE_MII ((uint32_t)0x00000000)
+#define ETH_MEDIA_INTERFACE_MII 0x00000000U
#define ETH_MEDIA_INTERFACE_RMII ((uint32_t)AFIO_MAPR_MII_RMII_SEL)
/**
@@ -825,19 +899,17 @@
/** @defgroup ETH_Watchdog ETH Watchdog
* @{
*/
-#define ETH_WATCHDOG_ENABLE ((uint32_t)0x00000000)
-#define ETH_WATCHDOG_DISABLE ((uint32_t)0x00800000)
-
+#define ETH_WATCHDOG_ENABLE 0x00000000U
+#define ETH_WATCHDOG_DISABLE 0x00800000U
/**
* @}
*/
-/** @defgroup ETH_Jabber ETH Jabber
+/** @defgroup ETH_Jabber ETH Jabber
* @{
*/
-#define ETH_JABBER_ENABLE ((uint32_t)0x00000000)
-#define ETH_JABBER_DISABLE ((uint32_t)0x00400000)
-
+#define ETH_JABBER_ENABLE 0x00000000U
+#define ETH_JABBER_DISABLE 0x00400000U
/**
* @}
*/
@@ -845,15 +917,14 @@
/** @defgroup ETH_Inter_Frame_Gap ETH Inter Frame Gap
* @{
*/
-#define ETH_INTERFRAMEGAP_96BIT ((uint32_t)0x00000000) /*!< minimum IFG between frames during transmission is 96Bit */
-#define ETH_INTERFRAMEGAP_88BIT ((uint32_t)0x00020000) /*!< minimum IFG between frames during transmission is 88Bit */
-#define ETH_INTERFRAMEGAP_80BIT ((uint32_t)0x00040000) /*!< minimum IFG between frames during transmission is 80Bit */
-#define ETH_INTERFRAMEGAP_72BIT ((uint32_t)0x00060000) /*!< minimum IFG between frames during transmission is 72Bit */
-#define ETH_INTERFRAMEGAP_64BIT ((uint32_t)0x00080000) /*!< minimum IFG between frames during transmission is 64Bit */
-#define ETH_INTERFRAMEGAP_56BIT ((uint32_t)0x000A0000) /*!< minimum IFG between frames during transmission is 56Bit */
-#define ETH_INTERFRAMEGAP_48BIT ((uint32_t)0x000C0000) /*!< minimum IFG between frames during transmission is 48Bit */
-#define ETH_INTERFRAMEGAP_40BIT ((uint32_t)0x000E0000) /*!< minimum IFG between frames during transmission is 40Bit */
-
+#define ETH_INTERFRAMEGAP_96BIT 0x00000000U /*!< minimum IFG between frames during transmission is 96Bit */
+#define ETH_INTERFRAMEGAP_88BIT 0x00020000U /*!< minimum IFG between frames during transmission is 88Bit */
+#define ETH_INTERFRAMEGAP_80BIT 0x00040000U /*!< minimum IFG between frames during transmission is 80Bit */
+#define ETH_INTERFRAMEGAP_72BIT 0x00060000U /*!< minimum IFG between frames during transmission is 72Bit */
+#define ETH_INTERFRAMEGAP_64BIT 0x00080000U /*!< minimum IFG between frames during transmission is 64Bit */
+#define ETH_INTERFRAMEGAP_56BIT 0x000A0000U /*!< minimum IFG between frames during transmission is 56Bit */
+#define ETH_INTERFRAMEGAP_48BIT 0x000C0000U /*!< minimum IFG between frames during transmission is 48Bit */
+#define ETH_INTERFRAMEGAP_40BIT 0x000E0000U /*!< minimum IFG between frames during transmission is 40Bit */
/**
* @}
*/
@@ -861,9 +932,8 @@
/** @defgroup ETH_Carrier_Sense ETH Carrier Sense
* @{
*/
-#define ETH_CARRIERSENCE_ENABLE ((uint32_t)0x00000000)
-#define ETH_CARRIERSENCE_DISABLE ((uint32_t)0x00010000)
-
+#define ETH_CARRIERSENCE_ENABLE 0x00000000U
+#define ETH_CARRIERSENCE_DISABLE 0x00010000U
/**
* @}
*/
@@ -871,19 +941,17 @@
/** @defgroup ETH_Receive_Own ETH Receive Own
* @{
*/
-#define ETH_RECEIVEOWN_ENABLE ((uint32_t)0x00000000)
-#define ETH_RECEIVEOWN_DISABLE ((uint32_t)0x00002000)
-
+#define ETH_RECEIVEOWN_ENABLE 0x00000000U
+#define ETH_RECEIVEOWN_DISABLE 0x00002000U
/**
* @}
*/
-/** @defgroup ETH_Loop_Back_Mode ETH Loop Back Mode
+/** @defgroup ETH_Loop_Back_Mode ETH Loop Back Mode
* @{
*/
-#define ETH_LOOPBACKMODE_ENABLE ((uint32_t)0x00001000)
-#define ETH_LOOPBACKMODE_DISABLE ((uint32_t)0x00000000)
-
+#define ETH_LOOPBACKMODE_ENABLE 0x00001000U
+#define ETH_LOOPBACKMODE_DISABLE 0x00000000U
/**
* @}
*/
@@ -891,9 +959,8 @@
/** @defgroup ETH_Checksum_Offload ETH Checksum Offload
* @{
*/
-#define ETH_CHECKSUMOFFLAOD_ENABLE ((uint32_t)0x00000400)
-#define ETH_CHECKSUMOFFLAOD_DISABLE ((uint32_t)0x00000000)
-
+#define ETH_CHECKSUMOFFLAOD_ENABLE 0x00000400U
+#define ETH_CHECKSUMOFFLAOD_DISABLE 0x00000000U
/**
* @}
*/
@@ -901,9 +968,8 @@
/** @defgroup ETH_Retry_Transmission ETH Retry Transmission
* @{
*/
-#define ETH_RETRYTRANSMISSION_ENABLE ((uint32_t)0x00000000)
-#define ETH_RETRYTRANSMISSION_DISABLE ((uint32_t)0x00000200)
-
+#define ETH_RETRYTRANSMISSION_ENABLE 0x00000000U
+#define ETH_RETRYTRANSMISSION_DISABLE 0x00000200U
/**
* @}
*/
@@ -911,9 +977,8 @@
/** @defgroup ETH_Automatic_Pad_CRC_Strip ETH Automatic Pad CRC Strip
* @{
*/
-#define ETH_AUTOMATICPADCRCSTRIP_ENABLE ((uint32_t)0x00000080)
-#define ETH_AUTOMATICPADCRCSTRIP_DISABLE ((uint32_t)0x00000000)
-
+#define ETH_AUTOMATICPADCRCSTRIP_ENABLE 0x00000080U
+#define ETH_AUTOMATICPADCRCSTRIP_DISABLE 0x00000000U
/**
* @}
*/
@@ -921,11 +986,10 @@
/** @defgroup ETH_Back_Off_Limit ETH Back Off Limit
* @{
*/
-#define ETH_BACKOFFLIMIT_10 ((uint32_t)0x00000000)
-#define ETH_BACKOFFLIMIT_8 ((uint32_t)0x00000020)
-#define ETH_BACKOFFLIMIT_4 ((uint32_t)0x00000040)
-#define ETH_BACKOFFLIMIT_1 ((uint32_t)0x00000060)
-
+#define ETH_BACKOFFLIMIT_10 0x00000000U
+#define ETH_BACKOFFLIMIT_8 0x00000020U
+#define ETH_BACKOFFLIMIT_4 0x00000040U
+#define ETH_BACKOFFLIMIT_1 0x00000060U
/**
* @}
*/
@@ -933,9 +997,8 @@
/** @defgroup ETH_Deferral_Check ETH Deferral Check
* @{
*/
-#define ETH_DEFFERRALCHECK_ENABLE ((uint32_t)0x00000010)
-#define ETH_DEFFERRALCHECK_DISABLE ((uint32_t)0x00000000)
-
+#define ETH_DEFFERRALCHECK_ENABLE 0x00000010U
+#define ETH_DEFFERRALCHECK_DISABLE 0x00000000U
/**
* @}
*/
@@ -943,9 +1006,8 @@
/** @defgroup ETH_Receive_All ETH Receive All
* @{
*/
-#define ETH_RECEIVEALL_ENABLE ((uint32_t)0x80000000)
-#define ETH_RECEIVEAll_DISABLE ((uint32_t)0x00000000)
-
+#define ETH_RECEIVEALL_ENABLE 0x80000000U
+#define ETH_RECEIVEAll_DISABLE 0x00000000U
/**
* @}
*/
@@ -953,10 +1015,9 @@
/** @defgroup ETH_Source_Addr_Filter ETH Source Addr Filter
* @{
*/
-#define ETH_SOURCEADDRFILTER_NORMAL_ENABLE ((uint32_t)0x00000200)
-#define ETH_SOURCEADDRFILTER_INVERSE_ENABLE ((uint32_t)0x00000300)
-#define ETH_SOURCEADDRFILTER_DISABLE ((uint32_t)0x00000000)
-
+#define ETH_SOURCEADDRFILTER_NORMAL_ENABLE 0x00000200U
+#define ETH_SOURCEADDRFILTER_INVERSE_ENABLE 0x00000300U
+#define ETH_SOURCEADDRFILTER_DISABLE 0x00000000U
/**
* @}
*/
@@ -964,10 +1025,9 @@
/** @defgroup ETH_Pass_Control_Frames ETH Pass Control Frames
* @{
*/
-#define ETH_PASSCONTROLFRAMES_BLOCKALL ((uint32_t)0x00000040) /*!< MAC filters all control frames from reaching the application */
-#define ETH_PASSCONTROLFRAMES_FORWARDALL ((uint32_t)0x00000080) /*!< MAC forwards all control frames to application even if they fail the Address Filter */
-#define ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER ((uint32_t)0x000000C0) /*!< MAC forwards control frames that pass the Address Filter. */
-
+#define ETH_PASSCONTROLFRAMES_BLOCKALL 0x00000040U /*!< MAC filters all control frames from reaching the application */
+#define ETH_PASSCONTROLFRAMES_FORWARDALL 0x00000080U /*!< MAC forwards all control frames to application even if they fail the Address Filter */
+#define ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER 0x000000C0U /*!< MAC forwards control frames that pass the Address Filter. */
/**
* @}
*/
@@ -975,9 +1035,8 @@
/** @defgroup ETH_Broadcast_Frames_Reception ETH Broadcast Frames Reception
* @{
*/
-#define ETH_BROADCASTFRAMESRECEPTION_ENABLE ((uint32_t)0x00000000)
-#define ETH_BROADCASTFRAMESRECEPTION_DISABLE ((uint32_t)0x00000020)
-
+#define ETH_BROADCASTFRAMESRECEPTION_ENABLE 0x00000000U
+#define ETH_BROADCASTFRAMESRECEPTION_DISABLE 0x00000020U
/**
* @}
*/
@@ -985,9 +1044,8 @@
/** @defgroup ETH_Destination_Addr_Filter ETH Destination Addr Filter
* @{
*/
-#define ETH_DESTINATIONADDRFILTER_NORMAL ((uint32_t)0x00000000)
-#define ETH_DESTINATIONADDRFILTER_INVERSE ((uint32_t)0x00000008)
-
+#define ETH_DESTINATIONADDRFILTER_NORMAL 0x00000000U
+#define ETH_DESTINATIONADDRFILTER_INVERSE 0x00000008U
/**
* @}
*/
@@ -995,9 +1053,8 @@
/** @defgroup ETH_Promiscuous_Mode ETH Promiscuous Mode
* @{
*/
-#define ETH_PROMISCUOUS_MODE_ENABLE ((uint32_t)0x00000001)
-#define ETH_PROMISCUOUS_MODE_DISABLE ((uint32_t)0x00000000)
-
+#define ETH_PROMISCUOUS_MODE_ENABLE 0x00000001U
+#define ETH_PROMISCUOUS_MODE_DISABLE 0x00000000U
/**
* @}
*/
@@ -1005,11 +1062,10 @@
/** @defgroup ETH_Multicast_Frames_Filter ETH Multicast Frames Filter
* @{
*/
-#define ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE ((uint32_t)0x00000404)
-#define ETH_MULTICASTFRAMESFILTER_HASHTABLE ((uint32_t)0x00000004)
-#define ETH_MULTICASTFRAMESFILTER_PERFECT ((uint32_t)0x00000000)
-#define ETH_MULTICASTFRAMESFILTER_NONE ((uint32_t)0x00000010)
-
+#define ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE 0x00000404U
+#define ETH_MULTICASTFRAMESFILTER_HASHTABLE 0x00000004U
+#define ETH_MULTICASTFRAMESFILTER_PERFECT 0x00000000U
+#define ETH_MULTICASTFRAMESFILTER_NONE 0x00000010U
/**
* @}
*/
@@ -1017,20 +1073,18 @@
/** @defgroup ETH_Unicast_Frames_Filter ETH Unicast Frames Filter
* @{
*/
-#define ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE ((uint32_t)0x00000402)
-#define ETH_UNICASTFRAMESFILTER_HASHTABLE ((uint32_t)0x00000002)
-#define ETH_UNICASTFRAMESFILTER_PERFECT ((uint32_t)0x00000000)
-
+#define ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE 0x00000402U
+#define ETH_UNICASTFRAMESFILTER_HASHTABLE 0x00000002U
+#define ETH_UNICASTFRAMESFILTER_PERFECT 0x00000000U
/**
* @}
*/
-/** @defgroup ETH_Zero_Quanta_Pause ETH Zero Quanta Pause
+/** @defgroup ETH_Zero_Quanta_Pause ETH Zero Quanta Pause
* @{
*/
-#define ETH_ZEROQUANTAPAUSE_ENABLE ((uint32_t)0x00000000)
-#define ETH_ZEROQUANTAPAUSE_DISABLE ((uint32_t)0x00000080)
-
+#define ETH_ZEROQUANTAPAUSE_ENABLE 0x00000000U
+#define ETH_ZEROQUANTAPAUSE_DISABLE 0x00000080U
/**
* @}
*/
@@ -1038,11 +1092,10 @@
/** @defgroup ETH_Pause_Low_Threshold ETH Pause Low Threshold
* @{
*/
-#define ETH_PAUSELOWTHRESHOLD_MINUS4 ((uint32_t)0x00000000) /*!< Pause time minus 4 slot times */
-#define ETH_PAUSELOWTHRESHOLD_MINUS28 ((uint32_t)0x00000010) /*!< Pause time minus 28 slot times */
-#define ETH_PAUSELOWTHRESHOLD_MINUS144 ((uint32_t)0x00000020) /*!< Pause time minus 144 slot times */
-#define ETH_PAUSELOWTHRESHOLD_MINUS256 ((uint32_t)0x00000030) /*!< Pause time minus 256 slot times */
-
+#define ETH_PAUSELOWTHRESHOLD_MINUS4 0x00000000U /*!< Pause time minus 4 slot times */
+#define ETH_PAUSELOWTHRESHOLD_MINUS28 0x00000010U /*!< Pause time minus 28 slot times */
+#define ETH_PAUSELOWTHRESHOLD_MINUS144 0x00000020U /*!< Pause time minus 144 slot times */
+#define ETH_PAUSELOWTHRESHOLD_MINUS256 0x00000030U /*!< Pause time minus 256 slot times */
/**
* @}
*/
@@ -1050,9 +1103,8 @@
/** @defgroup ETH_Unicast_Pause_Frame_Detect ETH Unicast Pause Frame Detect
* @{
*/
-#define ETH_UNICASTPAUSEFRAMEDETECT_ENABLE ((uint32_t)0x00000008)
-#define ETH_UNICASTPAUSEFRAMEDETECT_DISABLE ((uint32_t)0x00000000)
-
+#define ETH_UNICASTPAUSEFRAMEDETECT_ENABLE 0x00000008U
+#define ETH_UNICASTPAUSEFRAMEDETECT_DISABLE 0x00000000U
/**
* @}
*/
@@ -1060,9 +1112,8 @@
/** @defgroup ETH_Receive_Flow_Control ETH Receive Flow Control
* @{
*/
-#define ETH_RECEIVEFLOWCONTROL_ENABLE ((uint32_t)0x00000004)
-#define ETH_RECEIVEFLOWCONTROL_DISABLE ((uint32_t)0x00000000)
-
+#define ETH_RECEIVEFLOWCONTROL_ENABLE 0x00000004U
+#define ETH_RECEIVEFLOWCONTROL_DISABLE 0x00000000U
/**
* @}
*/
@@ -1070,9 +1121,8 @@
/** @defgroup ETH_Transmit_Flow_Control ETH Transmit Flow Control
* @{
*/
-#define ETH_TRANSMITFLOWCONTROL_ENABLE ((uint32_t)0x00000002)
-#define ETH_TRANSMITFLOWCONTROL_DISABLE ((uint32_t)0x00000000)
-
+#define ETH_TRANSMITFLOWCONTROL_ENABLE 0x00000002U
+#define ETH_TRANSMITFLOWCONTROL_DISABLE 0x00000000U
/**
* @}
*/
@@ -1080,9 +1130,8 @@
/** @defgroup ETH_VLAN_Tag_Comparison ETH VLAN Tag Comparison
* @{
*/
-#define ETH_VLANTAGCOMPARISON_12BIT ((uint32_t)0x00010000)
-#define ETH_VLANTAGCOMPARISON_16BIT ((uint32_t)0x00000000)
-
+#define ETH_VLANTAGCOMPARISON_12BIT 0x00010000U
+#define ETH_VLANTAGCOMPARISON_16BIT 0x00000000U
/**
* @}
*/
@@ -1090,34 +1139,32 @@
/** @defgroup ETH_MAC_addresses ETH MAC addresses
* @{
*/
-#define ETH_MAC_ADDRESS0 ((uint32_t)0x00000000)
-#define ETH_MAC_ADDRESS1 ((uint32_t)0x00000008)
-#define ETH_MAC_ADDRESS2 ((uint32_t)0x00000010)
-#define ETH_MAC_ADDRESS3 ((uint32_t)0x00000018)
-
+#define ETH_MAC_ADDRESS0 0x00000000U
+#define ETH_MAC_ADDRESS1 0x00000008U
+#define ETH_MAC_ADDRESS2 0x00000010U
+#define ETH_MAC_ADDRESS3 0x00000018U
/**
* @}
*/
-/** @defgroup ETH_MAC_Addresses_Filter_SA_DA ETH MAC Addresses Filter SA DA
+/** @defgroup ETH_MAC_addresses_filter_SA_DA ETH MAC addresses filter SA DA
* @{
*/
-#define ETH_MAC_ADDRESSFILTER_SA ((uint32_t)0x00000000)
-#define ETH_MAC_ADDRESSFILTER_DA ((uint32_t)0x00000008)
+#define ETH_MAC_ADDRESSFILTER_SA 0x00000000U
+#define ETH_MAC_ADDRESSFILTER_DA 0x00000008U
/**
* @}
*/
-/** @defgroup ETH_MAC_Addresses_Filter_Mask_Bytes ETH_MAC Addresses Filter Mask Bytes
+/** @defgroup ETH_MAC_addresses_filter_Mask_bytes ETH MAC addresses filter Mask bytes
* @{
*/
-#define ETH_MAC_ADDRESSMASK_BYTE6 ((uint32_t)0x20000000) /*!< Mask MAC Address high reg bits [15:8] */
-#define ETH_MAC_ADDRESSMASK_BYTE5 ((uint32_t)0x10000000) /*!< Mask MAC Address high reg bits [7:0] */
-#define ETH_MAC_ADDRESSMASK_BYTE4 ((uint32_t)0x08000000) /*!< Mask MAC Address low reg bits [31:24] */
-#define ETH_MAC_ADDRESSMASK_BYTE3 ((uint32_t)0x04000000) /*!< Mask MAC Address low reg bits [23:16] */
-#define ETH_MAC_ADDRESSMASK_BYTE2 ((uint32_t)0x02000000) /*!< Mask MAC Address low reg bits [15:8] */
-#define ETH_MAC_ADDRESSMASK_BYTE1 ((uint32_t)0x01000000) /*!< Mask MAC Address low reg bits [70] */
-
+#define ETH_MAC_ADDRESSMASK_BYTE6 0x20000000U /*!< Mask MAC Address high reg bits [15:8] */
+#define ETH_MAC_ADDRESSMASK_BYTE5 0x10000000U /*!< Mask MAC Address high reg bits [7:0] */
+#define ETH_MAC_ADDRESSMASK_BYTE4 0x08000000U /*!< Mask MAC Address low reg bits [31:24] */
+#define ETH_MAC_ADDRESSMASK_BYTE3 0x04000000U /*!< Mask MAC Address low reg bits [23:16] */
+#define ETH_MAC_ADDRESSMASK_BYTE2 0x02000000U /*!< Mask MAC Address low reg bits [15:8] */
+#define ETH_MAC_ADDRESSMASK_BYTE1 0x01000000U /*!< Mask MAC Address low reg bits [70] */
/**
* @}
*/
@@ -1125,19 +1172,17 @@
/** @defgroup ETH_Drop_TCP_IP_Checksum_Error_Frame ETH Drop TCP IP Checksum Error Frame
* @{
*/
-#define ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE ((uint32_t)0x00000000)
-#define ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE ((uint32_t)0x04000000)
-
+#define ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE 0x00000000U
+#define ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE 0x04000000U
/**
* @}
*/
-/** @defgroup ETH_Receive_Store_Forward ETH Receive Store Forward
+/** @defgroup ETH_Receive_Store_Forward ETH Receive Store Forward
* @{
*/
-#define ETH_RECEIVESTOREFORWARD_ENABLE ((uint32_t)0x02000000)
-#define ETH_RECEIVESTOREFORWARD_DISABLE ((uint32_t)0x00000000)
-
+#define ETH_RECEIVESTOREFORWARD_ENABLE 0x02000000U
+#define ETH_RECEIVESTOREFORWARD_DISABLE 0x00000000U
/**
* @}
*/
@@ -1145,9 +1190,8 @@
/** @defgroup ETH_Flush_Received_Frame ETH Flush Received Frame
* @{
*/
-#define ETH_FLUSHRECEIVEDFRAME_ENABLE ((uint32_t)0x00000000)
-#define ETH_FLUSHRECEIVEDFRAME_DISABLE ((uint32_t)0x01000000)
-
+#define ETH_FLUSHRECEIVEDFRAME_ENABLE 0x00000000U
+#define ETH_FLUSHRECEIVEDFRAME_DISABLE 0x01000000U
/**
* @}
*/
@@ -1155,9 +1199,8 @@
/** @defgroup ETH_Transmit_Store_Forward ETH Transmit Store Forward
* @{
*/
-#define ETH_TRANSMITSTOREFORWARD_ENABLE ((uint32_t)0x00200000)
-#define ETH_TRANSMITSTOREFORWARD_DISABLE ((uint32_t)0x00000000)
-
+#define ETH_TRANSMITSTOREFORWARD_ENABLE 0x00200000U
+#define ETH_TRANSMITSTOREFORWARD_DISABLE 0x00000000U
/**
* @}
*/
@@ -1165,15 +1208,14 @@
/** @defgroup ETH_Transmit_Threshold_Control ETH Transmit Threshold Control
* @{
*/
-#define ETH_TRANSMITTHRESHOLDCONTROL_64BYTES ((uint32_t)0x00000000) /*!< threshold level of the MTL Transmit FIFO is 64 Bytes */
-#define ETH_TRANSMITTHRESHOLDCONTROL_128BYTES ((uint32_t)0x00004000) /*!< threshold level of the MTL Transmit FIFO is 128 Bytes */
-#define ETH_TRANSMITTHRESHOLDCONTROL_192BYTES ((uint32_t)0x00008000) /*!< threshold level of the MTL Transmit FIFO is 192 Bytes */
-#define ETH_TRANSMITTHRESHOLDCONTROL_256BYTES ((uint32_t)0x0000C000) /*!< threshold level of the MTL Transmit FIFO is 256 Bytes */
-#define ETH_TRANSMITTHRESHOLDCONTROL_40BYTES ((uint32_t)0x00010000) /*!< threshold level of the MTL Transmit FIFO is 40 Bytes */
-#define ETH_TRANSMITTHRESHOLDCONTROL_32BYTES ((uint32_t)0x00014000) /*!< threshold level of the MTL Transmit FIFO is 32 Bytes */
-#define ETH_TRANSMITTHRESHOLDCONTROL_24BYTES ((uint32_t)0x00018000) /*!< threshold level of the MTL Transmit FIFO is 24 Bytes */
-#define ETH_TRANSMITTHRESHOLDCONTROL_16BYTES ((uint32_t)0x0001C000) /*!< threshold level of the MTL Transmit FIFO is 16 Bytes */
-
+#define ETH_TRANSMITTHRESHOLDCONTROL_64BYTES 0x00000000U /*!< threshold level of the MTL Transmit FIFO is 64 Bytes */
+#define ETH_TRANSMITTHRESHOLDCONTROL_128BYTES 0x00004000U /*!< threshold level of the MTL Transmit FIFO is 128 Bytes */
+#define ETH_TRANSMITTHRESHOLDCONTROL_192BYTES 0x00008000U /*!< threshold level of the MTL Transmit FIFO is 192 Bytes */
+#define ETH_TRANSMITTHRESHOLDCONTROL_256BYTES 0x0000C000U /*!< threshold level of the MTL Transmit FIFO is 256 Bytes */
+#define ETH_TRANSMITTHRESHOLDCONTROL_40BYTES 0x00010000U /*!< threshold level of the MTL Transmit FIFO is 40 Bytes */
+#define ETH_TRANSMITTHRESHOLDCONTROL_32BYTES 0x00014000U /*!< threshold level of the MTL Transmit FIFO is 32 Bytes */
+#define ETH_TRANSMITTHRESHOLDCONTROL_24BYTES 0x00018000U /*!< threshold level of the MTL Transmit FIFO is 24 Bytes */
+#define ETH_TRANSMITTHRESHOLDCONTROL_16BYTES 0x0001C000U /*!< threshold level of the MTL Transmit FIFO is 16 Bytes */
/**
* @}
*/
@@ -1181,9 +1223,8 @@
/** @defgroup ETH_Forward_Error_Frames ETH Forward Error Frames
* @{
*/
-#define ETH_FORWARDERRORFRAMES_ENABLE ((uint32_t)0x00000080)
-#define ETH_FORWARDERRORFRAMES_DISABLE ((uint32_t)0x00000000)
-
+#define ETH_FORWARDERRORFRAMES_ENABLE 0x00000080U
+#define ETH_FORWARDERRORFRAMES_DISABLE 0x00000000U
/**
* @}
*/
@@ -1191,9 +1232,8 @@
/** @defgroup ETH_Forward_Undersized_Good_Frames ETH Forward Undersized Good Frames
* @{
*/
-#define ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE ((uint32_t)0x00000040)
-#define ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE ((uint32_t)0x00000000)
-
+#define ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE 0x00000040U
+#define ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE 0x00000000U
/**
* @}
*/
@@ -1201,11 +1241,10 @@
/** @defgroup ETH_Receive_Threshold_Control ETH Receive Threshold Control
* @{
*/
-#define ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES ((uint32_t)0x00000000) /*!< threshold level of the MTL Receive FIFO is 64 Bytes */
-#define ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES ((uint32_t)0x00000008) /*!< threshold level of the MTL Receive FIFO is 32 Bytes */
-#define ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES ((uint32_t)0x00000010) /*!< threshold level of the MTL Receive FIFO is 96 Bytes */
-#define ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES ((uint32_t)0x00000018) /*!< threshold level of the MTL Receive FIFO is 128 Bytes */
-
+#define ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES 0x00000000U /*!< threshold level of the MTL Receive FIFO is 64 Bytes */
+#define ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES 0x00000008U /*!< threshold level of the MTL Receive FIFO is 32 Bytes */
+#define ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES 0x00000010U /*!< threshold level of the MTL Receive FIFO is 96 Bytes */
+#define ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES 0x00000018U /*!< threshold level of the MTL Receive FIFO is 128 Bytes */
/**
* @}
*/
@@ -1213,19 +1252,17 @@
/** @defgroup ETH_Second_Frame_Operate ETH Second Frame Operate
* @{
*/
-#define ETH_SECONDFRAMEOPERARTE_ENABLE ((uint32_t)0x00000004)
-#define ETH_SECONDFRAMEOPERARTE_DISABLE ((uint32_t)0x00000000)
-
+#define ETH_SECONDFRAMEOPERARTE_ENABLE 0x00000004U
+#define ETH_SECONDFRAMEOPERARTE_DISABLE 0x00000000U
/**
* @}
*/
-/** @defgroup ETH_Address_Aligned_Beats ETH Address Aligned Beats
+/** @defgroup ETH_Address_Aligned_Beats ETH Address Aligned Beats
* @{
*/
-#define ETH_ADDRESSALIGNEDBEATS_ENABLE ((uint32_t)0x02000000)
-#define ETH_ADDRESSALIGNEDBEATS_DISABLE ((uint32_t)0x00000000)
-
+#define ETH_ADDRESSALIGNEDBEATS_ENABLE 0x02000000U
+#define ETH_ADDRESSALIGNEDBEATS_DISABLE 0x00000000U
/**
* @}
*/
@@ -1233,29 +1270,27 @@
/** @defgroup ETH_Fixed_Burst ETH Fixed Burst
* @{
*/
-#define ETH_FIXEDBURST_ENABLE ((uint32_t)0x00010000)
-#define ETH_FIXEDBURST_DISABLE ((uint32_t)0x00000000)
-
+#define ETH_FIXEDBURST_ENABLE 0x00010000U
+#define ETH_FIXEDBURST_DISABLE 0x00000000U
/**
* @}
*/
-/** @defgroup ETH_Rx_DMA_Burst_Length ETH Rx DMA_Burst Length
+/** @defgroup ETH_Rx_DMA_Burst_Length ETH Rx DMA Burst Length
* @{
*/
-#define ETH_RXDMABURSTLENGTH_1BEAT ((uint32_t)0x00020000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 1 */
-#define ETH_RXDMABURSTLENGTH_2BEAT ((uint32_t)0x00040000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 2 */
-#define ETH_RXDMABURSTLENGTH_4BEAT ((uint32_t)0x00080000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */
-#define ETH_RXDMABURSTLENGTH_8BEAT ((uint32_t)0x00100000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */
-#define ETH_RXDMABURSTLENGTH_16BEAT ((uint32_t)0x00200000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */
-#define ETH_RXDMABURSTLENGTH_32BEAT ((uint32_t)0x00400000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */
-#define ETH_RXDMABURSTLENGTH_4XPBL_4BEAT ((uint32_t)0x01020000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */
-#define ETH_RXDMABURSTLENGTH_4XPBL_8BEAT ((uint32_t)0x01040000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */
-#define ETH_RXDMABURSTLENGTH_4XPBL_16BEAT ((uint32_t)0x01080000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */
-#define ETH_RXDMABURSTLENGTH_4XPBL_32BEAT ((uint32_t)0x01100000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */
-#define ETH_RXDMABURSTLENGTH_4XPBL_64BEAT ((uint32_t)0x01200000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 64 */
-#define ETH_RXDMABURSTLENGTH_4XPBL_128BEAT ((uint32_t)0x01400000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 128 */
-
+#define ETH_RXDMABURSTLENGTH_1BEAT 0x00020000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 1 */
+#define ETH_RXDMABURSTLENGTH_2BEAT 0x00040000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 2 */
+#define ETH_RXDMABURSTLENGTH_4BEAT 0x00080000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */
+#define ETH_RXDMABURSTLENGTH_8BEAT 0x00100000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */
+#define ETH_RXDMABURSTLENGTH_16BEAT 0x00200000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */
+#define ETH_RXDMABURSTLENGTH_32BEAT 0x00400000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */
+#define ETH_RXDMABURSTLENGTH_4XPBL_4BEAT 0x01020000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */
+#define ETH_RXDMABURSTLENGTH_4XPBL_8BEAT 0x01040000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */
+#define ETH_RXDMABURSTLENGTH_4XPBL_16BEAT 0x01080000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */
+#define ETH_RXDMABURSTLENGTH_4XPBL_32BEAT 0x01100000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */
+#define ETH_RXDMABURSTLENGTH_4XPBL_64BEAT 0x01200000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 64 */
+#define ETH_RXDMABURSTLENGTH_4XPBL_128BEAT 0x01400000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 128 */
/**
* @}
*/
@@ -1263,18 +1298,18 @@
/** @defgroup ETH_Tx_DMA_Burst_Length ETH Tx DMA Burst Length
* @{
*/
-#define ETH_TXDMABURSTLENGTH_1BEAT ((uint32_t)0x00000100) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
-#define ETH_TXDMABURSTLENGTH_2BEAT ((uint32_t)0x00000200) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
-#define ETH_TXDMABURSTLENGTH_4BEAT ((uint32_t)0x00000400) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
-#define ETH_TXDMABURSTLENGTH_8BEAT ((uint32_t)0x00000800) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
-#define ETH_TXDMABURSTLENGTH_16BEAT ((uint32_t)0x00001000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
-#define ETH_TXDMABURSTLENGTH_32BEAT ((uint32_t)0x00002000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
-#define ETH_TXDMABURSTLENGTH_4XPBL_4BEAT ((uint32_t)0x01000100) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
-#define ETH_TXDMABURSTLENGTH_4XPBL_8BEAT ((uint32_t)0x01000200) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
-#define ETH_TXDMABURSTLENGTH_4XPBL_16BEAT ((uint32_t)0x01000400) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
-#define ETH_TXDMABURSTLENGTH_4XPBL_32BEAT ((uint32_t)0x01000800) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
-#define ETH_TXDMABURSTLENGTH_4XPBL_64BEAT ((uint32_t)0x01001000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
-#define ETH_TXDMABURSTLENGTH_4XPBL_128BEAT ((uint32_t)0x01002000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
+#define ETH_TXDMABURSTLENGTH_1BEAT 0x00000100U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
+#define ETH_TXDMABURSTLENGTH_2BEAT 0x00000200U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
+#define ETH_TXDMABURSTLENGTH_4BEAT 0x00000400U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+#define ETH_TXDMABURSTLENGTH_8BEAT 0x00000800U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+#define ETH_TXDMABURSTLENGTH_16BEAT 0x00001000U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+#define ETH_TXDMABURSTLENGTH_32BEAT 0x00002000U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
+#define ETH_TXDMABURSTLENGTH_4XPBL_4BEAT 0x01000100U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
+#define ETH_TXDMABURSTLENGTH_4XPBL_8BEAT 0x01000200U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
+#define ETH_TXDMABURSTLENGTH_4XPBL_16BEAT 0x01000400U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
+#define ETH_TXDMABURSTLENGTH_4XPBL_32BEAT 0x01000800U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
+#define ETH_TXDMABURSTLENGTH_4XPBL_64BEAT 0x01001000U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
+#define ETH_TXDMABURSTLENGTH_4XPBL_128BEAT 0x01002000U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
/**
* @}
@@ -1283,44 +1318,40 @@
/** @defgroup ETH_DMA_Arbitration ETH DMA Arbitration
* @{
*/
-#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1 ((uint32_t)0x00000000)
-#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1 ((uint32_t)0x00004000)
-#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1 ((uint32_t)0x00008000)
-#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1 ((uint32_t)0x0000C000)
-#define ETH_DMAARBITRATION_RXPRIORTX ((uint32_t)0x00000002)
-
+#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1 0x00000000U
+#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1 0x00004000U
+#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1 0x00008000U
+#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1 0x0000C000U
+#define ETH_DMAARBITRATION_RXPRIORTX 0x00000002U
/**
* @}
*/
-/** @defgroup ETH_DMA_Tx_Descriptor_Segment ETH DMA Tx Descriptor Segment
+/** @defgroup ETH_DMA_Tx_descriptor_segment ETH DMA Tx descriptor segment
* @{
*/
-#define ETH_DMATXDESC_LASTSEGMENTS ((uint32_t)0x40000000) /*!< Last Segment */
-#define ETH_DMATXDESC_FIRSTSEGMENT ((uint32_t)0x20000000) /*!< First Segment */
-
+#define ETH_DMATXDESC_LASTSEGMENTS 0x40000000U /*!< Last Segment */
+#define ETH_DMATXDESC_FIRSTSEGMENT 0x20000000U /*!< First Segment */
/**
* @}
*/
-/** @defgroup ETH_DMA_Tx_Descriptor_Checksum_Insertion_Control ETH DMA Tx Descriptor Checksum Insertion Control
+/** @defgroup ETH_DMA_Tx_descriptor_Checksum_Insertion_Control ETH DMA Tx descriptor Checksum Insertion Control
* @{
*/
-#define ETH_DMATXDESC_CHECKSUMBYPASS ((uint32_t)0x00000000) /*!< Checksum engine bypass */
-#define ETH_DMATXDESC_CHECKSUMIPV4HEADER ((uint32_t)0x00400000) /*!< IPv4 header checksum insertion */
-#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT ((uint32_t)0x00800000) /*!< TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present */
-#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL ((uint32_t)0x00C00000) /*!< TCP/UDP/ICMP checksum fully in hardware including pseudo header */
-
+#define ETH_DMATXDESC_CHECKSUMBYPASS 0x00000000U /*!< Checksum engine bypass */
+#define ETH_DMATXDESC_CHECKSUMIPV4HEADER 0x00400000U /*!< IPv4 header checksum insertion */
+#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT 0x00800000U /*!< TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present */
+#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL 0x00C00000U /*!< TCP/UDP/ICMP checksum fully in hardware including pseudo header */
/**
* @}
*/
-/** @defgroup ETH_DMA_Rx_Descriptor_Buffers ETH DMA Rx Descriptor Buffers
+/** @defgroup ETH_DMA_Rx_descriptor_buffers ETH DMA Rx descriptor buffers
* @{
*/
-#define ETH_DMARXDESC_BUFFER1 ((uint32_t)0x00000000) /*!< DMA Rx Desc Buffer1 */
-#define ETH_DMARXDESC_BUFFER2 ((uint32_t)0x00000001) /*!< DMA Rx Desc Buffer2 */
-
+#define ETH_DMARXDESC_BUFFER1 0x00000000U /*!< DMA Rx Desc Buffer1 */
+#define ETH_DMARXDESC_BUFFER2 0x00000001U /*!< DMA Rx Desc Buffer2 */
/**
* @}
*/
@@ -1328,10 +1359,9 @@
/** @defgroup ETH_PMT_Flags ETH PMT Flags
* @{
*/
-#define ETH_PMT_FLAG_WUFFRPR ((uint32_t)0x80000000) /*!< Wake-Up Frame Filter Register Pointer Reset */
-#define ETH_PMT_FLAG_WUFR ((uint32_t)0x00000040) /*!< Wake-Up Frame Received */
-#define ETH_PMT_FLAG_MPR ((uint32_t)0x00000020) /*!< Magic Packet Received */
-
+#define ETH_PMT_FLAG_WUFFRPR 0x80000000U /*!< Wake-Up Frame Filter Register Pointer Reset */
+#define ETH_PMT_FLAG_WUFR 0x00000040U /*!< Wake-Up Frame Received */
+#define ETH_PMT_FLAG_MPR 0x00000020U /*!< Magic Packet Received */
/**
* @}
*/
@@ -1339,10 +1369,9 @@
/** @defgroup ETH_MMC_Tx_Interrupts ETH MMC Tx Interrupts
* @{
*/
-#define ETH_MMC_IT_TGF ((uint32_t)0x00200000) /*!< When Tx good frame counter reaches half the maximum value */
-#define ETH_MMC_IT_TGFMSC ((uint32_t)0x00008000) /*!< When Tx good multi col counter reaches half the maximum value */
-#define ETH_MMC_IT_TGFSC ((uint32_t)0x00004000) /*!< When Tx good single col counter reaches half the maximum value */
-
+#define ETH_MMC_IT_TGF 0x00200000U /*!< When Tx good frame counter reaches half the maximum value */
+#define ETH_MMC_IT_TGFMSC 0x00008000U /*!< When Tx good multi col counter reaches half the maximum value */
+#define ETH_MMC_IT_TGFSC 0x00004000U /*!< When Tx good single col counter reaches half the maximum value */
/**
* @}
*/
@@ -1350,10 +1379,9 @@
/** @defgroup ETH_MMC_Rx_Interrupts ETH MMC Rx Interrupts
* @{
*/
-#define ETH_MMC_IT_RGUF ((uint32_t)0x10020000) /*!< When Rx good unicast frames counter reaches half the maximum value */
-#define ETH_MMC_IT_RFAE ((uint32_t)0x10000040) /*!< When Rx alignment error counter reaches half the maximum value */
-#define ETH_MMC_IT_RFCE ((uint32_t)0x10000020) /*!< When Rx crc error counter reaches half the maximum value */
-
+#define ETH_MMC_IT_RGUF 0x10020000U /*!< When Rx good unicast frames counter reaches half the maximum value */
+#define ETH_MMC_IT_RFAE 0x10000040U /*!< When Rx alignment error counter reaches half the maximum value */
+#define ETH_MMC_IT_RFCE 0x10000020U /*!< When Rx crc error counter reaches half the maximum value */
/**
* @}
*/
@@ -1361,12 +1389,11 @@
/** @defgroup ETH_MAC_Flags ETH MAC Flags
* @{
*/
-#define ETH_MAC_FLAG_TST ((uint32_t)0x00000200) /*!< Time stamp trigger flag (on MAC) */
-#define ETH_MAC_FLAG_MMCT ((uint32_t)0x00000040) /*!< MMC transmit flag */
-#define ETH_MAC_FLAG_MMCR ((uint32_t)0x00000020) /*!< MMC receive flag */
-#define ETH_MAC_FLAG_MMC ((uint32_t)0x00000010) /*!< MMC flag (on MAC) */
-#define ETH_MAC_FLAG_PMT ((uint32_t)0x00000008) /*!< PMT flag (on MAC) */
-
+#define ETH_MAC_FLAG_TST 0x00000200U /*!< Time stamp trigger flag (on MAC) */
+#define ETH_MAC_FLAG_MMCT 0x00000040U /*!< MMC transmit flag */
+#define ETH_MAC_FLAG_MMCR 0x00000020U /*!< MMC receive flag */
+#define ETH_MAC_FLAG_MMC 0x00000010U /*!< MMC flag (on MAC) */
+#define ETH_MAC_FLAG_PMT 0x00000008U /*!< PMT flag (on MAC) */
/**
* @}
*/
@@ -1374,67 +1401,64 @@
/** @defgroup ETH_DMA_Flags ETH DMA Flags
* @{
*/
-#define ETH_DMA_FLAG_TST ((uint32_t)0x20000000) /*!< Time-stamp trigger interrupt (on DMA) */
-#define ETH_DMA_FLAG_PMT ((uint32_t)0x10000000) /*!< PMT interrupt (on DMA) */
-#define ETH_DMA_FLAG_MMC ((uint32_t)0x08000000) /*!< MMC interrupt (on DMA) */
-#define ETH_DMA_FLAG_DATATRANSFERERROR ((uint32_t)0x00800000) /*!< Error bits 0-Rx DMA, 1-Tx DMA */
-#define ETH_DMA_FLAG_READWRITEERROR ((uint32_t)0x01000000) /*!< Error bits 0-write trnsf, 1-read transfr */
-#define ETH_DMA_FLAG_ACCESSERROR ((uint32_t)0x02000000) /*!< Error bits 0-data buffer, 1-desc. access */
-#define ETH_DMA_FLAG_NIS ((uint32_t)0x00010000) /*!< Normal interrupt summary flag */
-#define ETH_DMA_FLAG_AIS ((uint32_t)0x00008000) /*!< Abnormal interrupt summary flag */
-#define ETH_DMA_FLAG_ER ((uint32_t)0x00004000) /*!< Early receive flag */
-#define ETH_DMA_FLAG_FBE ((uint32_t)0x00002000) /*!< Fatal bus error flag */
-#define ETH_DMA_FLAG_ET ((uint32_t)0x00000400) /*!< Early transmit flag */
-#define ETH_DMA_FLAG_RWT ((uint32_t)0x00000200) /*!< Receive watchdog timeout flag */
-#define ETH_DMA_FLAG_RPS ((uint32_t)0x00000100) /*!< Receive process stopped flag */
-#define ETH_DMA_FLAG_RBU ((uint32_t)0x00000080) /*!< Receive buffer unavailable flag */
-#define ETH_DMA_FLAG_R ((uint32_t)0x00000040) /*!< Receive flag */
-#define ETH_DMA_FLAG_TU ((uint32_t)0x00000020) /*!< Underflow flag */
-#define ETH_DMA_FLAG_RO ((uint32_t)0x00000010) /*!< Overflow flag */
-#define ETH_DMA_FLAG_TJT ((uint32_t)0x00000008) /*!< Transmit jabber timeout flag */
-#define ETH_DMA_FLAG_TBU ((uint32_t)0x00000004) /*!< Transmit buffer unavailable flag */
-#define ETH_DMA_FLAG_TPS ((uint32_t)0x00000002) /*!< Transmit process stopped flag */
-#define ETH_DMA_FLAG_T ((uint32_t)0x00000001) /*!< Transmit flag */
-
+#define ETH_DMA_FLAG_TST 0x20000000U /*!< Time-stamp trigger interrupt (on DMA) */
+#define ETH_DMA_FLAG_PMT 0x10000000U /*!< PMT interrupt (on DMA) */
+#define ETH_DMA_FLAG_MMC 0x08000000U /*!< MMC interrupt (on DMA) */
+#define ETH_DMA_FLAG_DATATRANSFERERROR 0x00800000U /*!< Error bits 0-Rx DMA, 1-Tx DMA */
+#define ETH_DMA_FLAG_READWRITEERROR 0x01000000U /*!< Error bits 0-write transfer, 1-read transfer */
+#define ETH_DMA_FLAG_ACCESSERROR 0x02000000U /*!< Error bits 0-data buffer, 1-desc. access */
+#define ETH_DMA_FLAG_NIS 0x00010000U /*!< Normal interrupt summary flag */
+#define ETH_DMA_FLAG_AIS 0x00008000U /*!< Abnormal interrupt summary flag */
+#define ETH_DMA_FLAG_ER 0x00004000U /*!< Early receive flag */
+#define ETH_DMA_FLAG_FBE 0x00002000U /*!< Fatal bus error flag */
+#define ETH_DMA_FLAG_ET 0x00000400U /*!< Early transmit flag */
+#define ETH_DMA_FLAG_RWT 0x00000200U /*!< Receive watchdog timeout flag */
+#define ETH_DMA_FLAG_RPS 0x00000100U /*!< Receive process stopped flag */
+#define ETH_DMA_FLAG_RBU 0x00000080U /*!< Receive buffer unavailable flag */
+#define ETH_DMA_FLAG_R 0x00000040U /*!< Receive flag */
+#define ETH_DMA_FLAG_TU 0x00000020U /*!< Underflow flag */
+#define ETH_DMA_FLAG_RO 0x00000010U /*!< Overflow flag */
+#define ETH_DMA_FLAG_TJT 0x00000008U /*!< Transmit jabber timeout flag */
+#define ETH_DMA_FLAG_TBU 0x00000004U /*!< Transmit buffer unavailable flag */
+#define ETH_DMA_FLAG_TPS 0x00000002U /*!< Transmit process stopped flag */
+#define ETH_DMA_FLAG_T 0x00000001U /*!< Transmit flag */
/**
* @}
*/
-/** @defgroup ETH_MAC_Interrupts ETH MAC Interrupts
+/** @defgroup ETH_MAC_Interrupts ETH MAC Interrupts
* @{
*/
-#define ETH_MAC_IT_TST ((uint32_t)0x00000200) /*!< Time stamp trigger interrupt (on MAC) */
-#define ETH_MAC_IT_MMCT ((uint32_t)0x00000040) /*!< MMC transmit interrupt */
-#define ETH_MAC_IT_MMCR ((uint32_t)0x00000020) /*!< MMC receive interrupt */
-#define ETH_MAC_IT_MMC ((uint32_t)0x00000010) /*!< MMC interrupt (on MAC) */
-#define ETH_MAC_IT_PMT ((uint32_t)0x00000008) /*!< PMT interrupt (on MAC) */
-
+#define ETH_MAC_IT_TST 0x00000200U /*!< Time stamp trigger interrupt (on MAC) */
+#define ETH_MAC_IT_MMCT 0x00000040U /*!< MMC transmit interrupt */
+#define ETH_MAC_IT_MMCR 0x00000020U /*!< MMC receive interrupt */
+#define ETH_MAC_IT_MMC 0x00000010U /*!< MMC interrupt (on MAC) */
+#define ETH_MAC_IT_PMT 0x00000008U /*!< PMT interrupt (on MAC) */
/**
* @}
*/
-/** @defgroup ETH_DMA_Interrupts ETH DMA Interrupts
+/** @defgroup ETH_DMA_Interrupts ETH DMA Interrupts
* @{
*/
-#define ETH_DMA_IT_TST ((uint32_t)0x20000000) /*!< Time-stamp trigger interrupt (on DMA) */
-#define ETH_DMA_IT_PMT ((uint32_t)0x10000000) /*!< PMT interrupt (on DMA) */
-#define ETH_DMA_IT_MMC ((uint32_t)0x08000000) /*!< MMC interrupt (on DMA) */
-#define ETH_DMA_IT_NIS ((uint32_t)0x00010000) /*!< Normal interrupt summary */
-#define ETH_DMA_IT_AIS ((uint32_t)0x00008000) /*!< Abnormal interrupt summary */
-#define ETH_DMA_IT_ER ((uint32_t)0x00004000) /*!< Early receive interrupt */
-#define ETH_DMA_IT_FBE ((uint32_t)0x00002000) /*!< Fatal bus error interrupt */
-#define ETH_DMA_IT_ET ((uint32_t)0x00000400) /*!< Early transmit interrupt */
-#define ETH_DMA_IT_RWT ((uint32_t)0x00000200) /*!< Receive watchdog timeout interrupt */
-#define ETH_DMA_IT_RPS ((uint32_t)0x00000100) /*!< Receive process stopped interrupt */
-#define ETH_DMA_IT_RBU ((uint32_t)0x00000080) /*!< Receive buffer unavailable interrupt */
-#define ETH_DMA_IT_R ((uint32_t)0x00000040) /*!< Receive interrupt */
-#define ETH_DMA_IT_TU ((uint32_t)0x00000020) /*!< Underflow interrupt */
-#define ETH_DMA_IT_RO ((uint32_t)0x00000010) /*!< Overflow interrupt */
-#define ETH_DMA_IT_TJT ((uint32_t)0x00000008) /*!< Transmit jabber timeout interrupt */
-#define ETH_DMA_IT_TBU ((uint32_t)0x00000004) /*!< Transmit buffer unavailable interrupt */
-#define ETH_DMA_IT_TPS ((uint32_t)0x00000002) /*!< Transmit process stopped interrupt */
-#define ETH_DMA_IT_T ((uint32_t)0x00000001) /*!< Transmit interrupt */
-
+#define ETH_DMA_IT_TST 0x20000000U /*!< Time-stamp trigger interrupt (on DMA) */
+#define ETH_DMA_IT_PMT 0x10000000U /*!< PMT interrupt (on DMA) */
+#define ETH_DMA_IT_MMC 0x08000000U /*!< MMC interrupt (on DMA) */
+#define ETH_DMA_IT_NIS 0x00010000U /*!< Normal interrupt summary */
+#define ETH_DMA_IT_AIS 0x00008000U /*!< Abnormal interrupt summary */
+#define ETH_DMA_IT_ER 0x00004000U /*!< Early receive interrupt */
+#define ETH_DMA_IT_FBE 0x00002000U /*!< Fatal bus error interrupt */
+#define ETH_DMA_IT_ET 0x00000400U /*!< Early transmit interrupt */
+#define ETH_DMA_IT_RWT 0x00000200U /*!< Receive watchdog timeout interrupt */
+#define ETH_DMA_IT_RPS 0x00000100U /*!< Receive process stopped interrupt */
+#define ETH_DMA_IT_RBU 0x00000080U /*!< Receive buffer unavailable interrupt */
+#define ETH_DMA_IT_R 0x00000040U /*!< Receive interrupt */
+#define ETH_DMA_IT_TU 0x00000020U /*!< Underflow interrupt */
+#define ETH_DMA_IT_RO 0x00000010U /*!< Overflow interrupt */
+#define ETH_DMA_IT_TJT 0x00000008U /*!< Transmit jabber timeout interrupt */
+#define ETH_DMA_IT_TBU 0x00000004U /*!< Transmit buffer unavailable interrupt */
+#define ETH_DMA_IT_TPS 0x00000002U /*!< Transmit process stopped interrupt */
+#define ETH_DMA_IT_T 0x00000001U /*!< Transmit interrupt */
/**
* @}
*/
@@ -1442,12 +1466,12 @@
/** @defgroup ETH_DMA_transmit_process_state ETH DMA transmit process state
* @{
*/
-#define ETH_DMA_TRANSMITPROCESS_STOPPED ((uint32_t)0x00000000) /*!< Stopped - Reset or Stop Tx Command issued */
-#define ETH_DMA_TRANSMITPROCESS_FETCHING ((uint32_t)0x00100000) /*!< Running - fetching the Tx descriptor */
-#define ETH_DMA_TRANSMITPROCESS_WAITING ((uint32_t)0x00200000) /*!< Running - waiting for status */
-#define ETH_DMA_TRANSMITPROCESS_READING ((uint32_t)0x00300000) /*!< Running - reading the data from host memory */
-#define ETH_DMA_TRANSMITPROCESS_SUSPENDED ((uint32_t)0x00600000) /*!< Suspended - Tx Descriptor unavailable */
-#define ETH_DMA_TRANSMITPROCESS_CLOSING ((uint32_t)0x00700000) /*!< Running - closing Rx descriptor */
+#define ETH_DMA_TRANSMITPROCESS_STOPPED 0x00000000U /*!< Stopped - Reset or Stop Tx Command issued */
+#define ETH_DMA_TRANSMITPROCESS_FETCHING 0x00100000U /*!< Running - fetching the Tx descriptor */
+#define ETH_DMA_TRANSMITPROCESS_WAITING 0x00200000U /*!< Running - waiting for status */
+#define ETH_DMA_TRANSMITPROCESS_READING 0x00300000U /*!< Running - reading the data from host memory */
+#define ETH_DMA_TRANSMITPROCESS_SUSPENDED 0x00600000U /*!< Suspended - Tx Descriptor unavailable */
+#define ETH_DMA_TRANSMITPROCESS_CLOSING 0x00700000U /*!< Running - closing Rx descriptor */
/**
* @}
@@ -1457,12 +1481,12 @@
/** @defgroup ETH_DMA_receive_process_state ETH DMA receive process state
* @{
*/
-#define ETH_DMA_RECEIVEPROCESS_STOPPED ((uint32_t)0x00000000) /*!< Stopped - Reset or Stop Rx Command issued */
-#define ETH_DMA_RECEIVEPROCESS_FETCHING ((uint32_t)0x00020000) /*!< Running - fetching the Rx descriptor */
-#define ETH_DMA_RECEIVEPROCESS_WAITING ((uint32_t)0x00060000) /*!< Running - waiting for packet */
-#define ETH_DMA_RECEIVEPROCESS_SUSPENDED ((uint32_t)0x00080000) /*!< Suspended - Rx Descriptor unavailable */
-#define ETH_DMA_RECEIVEPROCESS_CLOSING ((uint32_t)0x000A0000) /*!< Running - closing descriptor */
-#define ETH_DMA_RECEIVEPROCESS_QUEUING ((uint32_t)0x000E0000) /*!< Running - queuing the receive frame into host memory */
+#define ETH_DMA_RECEIVEPROCESS_STOPPED 0x00000000U /*!< Stopped - Reset or Stop Rx Command issued */
+#define ETH_DMA_RECEIVEPROCESS_FETCHING 0x00020000U /*!< Running - fetching the Rx descriptor */
+#define ETH_DMA_RECEIVEPROCESS_WAITING 0x00060000U /*!< Running - waiting for packet */
+#define ETH_DMA_RECEIVEPROCESS_SUSPENDED 0x00080000U /*!< Suspended - Rx Descriptor unavailable */
+#define ETH_DMA_RECEIVEPROCESS_CLOSING 0x000A0000U /*!< Running - closing descriptor */
+#define ETH_DMA_RECEIVEPROCESS_QUEUING 0x000E0000U /*!< Running - queuing the receive frame into host memory */
/**
* @}
@@ -1471,17 +1495,16 @@
/** @defgroup ETH_DMA_overflow ETH DMA overflow
* @{
*/
-#define ETH_DMA_OVERFLOW_RXFIFOCOUNTER ((uint32_t)0x10000000) /*!< Overflow bit for FIFO overflow counter */
-#define ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER ((uint32_t)0x00010000) /*!< Overflow bit for missed frame counter */
-
+#define ETH_DMA_OVERFLOW_RXFIFOCOUNTER 0x10000000U /*!< Overflow bit for FIFO overflow counter */
+#define ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER 0x00010000U /*!< Overflow bit for missed frame counter */
/**
* @}
*/
- /** @defgroup ETH_EXTI_LINE_WAKEUP ETH EXTI LINE WAKEUP
+/** @defgroup ETH_EXTI_LINE_WAKEUP ETH EXTI LINE WAKEUP
* @{
*/
-#define ETH_EXTI_LINE_WAKEUP ((uint32_t)0x00080000) /*!< External interrupt line 19 Connected to the ETH EXTI Line */
+#define ETH_EXTI_LINE_WAKEUP 0x00080000U /*!< External interrupt line 19 Connected to the ETH EXTI Line */
/**
* @}
@@ -1506,7 +1529,7 @@
/**
* @brief Checks whether the specified ETHERNET DMA Tx Desc flag is set or not.
* @param __HANDLE__: ETH Handle
- * @param __FLAG__: specifies the flag of TDES0 to check .
+ * @param __FLAG__: specifies the flag of TDES0 to check.
* @retval the ETH_DMATxDescFlag (SET or RESET).
*/
#define __HAL_ETH_DMATXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->TxDesc->Status & (__FLAG__) == (__FLAG__))
@@ -1576,7 +1599,7 @@
* @arg ETH_DMATXDESC_CHECKSUMBYPASS : Checksum bypass
* @arg ETH_DMATXDESC_CHECKSUMIPV4HEADER : IPv4 header checksum
* @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT : TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present
- * @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL : TCP/UDP/ICMP checksum fully in hardware including pseudo header
+ * @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL : TCP/UDP/ICMP checksum fully in hardware including pseudo header
* @retval None
*/
#define __HAL_ETH_DMATXDESC_CHECKSUM_INSERTION(__HANDLE__, __CHECKSUM__) ((__HANDLE__)->TxDesc->Status |= (__CHECKSUM__))
@@ -1819,7 +1842,7 @@
* @retval None
*/
#define __HAL_ETH_MMC_COUNTER_HALF_PRESET(__HANDLE__) do{(__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCFHP;\
- (__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCP;} while (0)
+ (__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCP;} while(0U)
/**
* @brief Enables the MMC Counter Freeze.
@@ -1880,7 +1903,7 @@
* @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value
* @retval None
*/
-#define __HAL_ETH_MMC_RX_IT_ENABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR &= ~((__INTERRUPT__) & 0xEFFFFFFF)
+#define __HAL_ETH_MMC_RX_IT_ENABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR &= ~((__INTERRUPT__) & 0xEFFFFFFFU)
/**
* @brief Disables the specified ETHERNET MMC Rx interrupts.
* @param __HANDLE__: ETH Handle.
@@ -1891,7 +1914,7 @@
* @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value
* @retval None
*/
-#define __HAL_ETH_MMC_RX_IT_DISABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR |= ((__INTERRUPT__) & 0xEFFFFFFF)
+#define __HAL_ETH_MMC_RX_IT_DISABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR |= ((__INTERRUPT__) & 0xEFFFFFFFU)
/**
* @brief Enables the specified ETHERNET MMC Tx interrupts.
* @param __HANDLE__: ETH Handle.
@@ -1957,17 +1980,17 @@
* @retval None
*/
#define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER() EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP
-
+
/**
* @brief Disables the rising edge trigger to the ETH External interrupt line.
* @retval None
*/
-#define __HAL_ETH_WAKEUP_EXTI_DISABLE_RISING_EDGE_TRIGGER() EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP)
+#define __HAL_ETH_WAKEUP_EXTI_DISABLE_RISING_EDGE_TRIGGER() EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP)
/**
* @brief Enables falling edge trigger to the ETH External interrupt line.
* @retval None
- */
+ */
#define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR |= (ETH_EXTI_LINE_WAKEUP)
/**
@@ -1975,27 +1998,22 @@
* @retval None
*/
#define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP)
-
/**
* @brief Enables rising/falling edge trigger to the ETH External interrupt line.
* @retval None
*/
-#define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER() \
- do{ \
- EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP;\
- EXTI->FTSR |= ETH_EXTI_LINE_WAKEUP;\
- } while(0)
+#define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER() do{EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP;\
+ EXTI->FTSR |= ETH_EXTI_LINE_WAKEUP;\
+ }while(0U)
/**
* @brief Disables rising/falling edge trigger to the ETH External interrupt line.
* @retval None
*/
-#define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLINGRISING_TRIGGER() \
- do{ \
- EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP);\
- EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP);\
- } while(0)
+#define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLINGRISING_TRIGGER() do{EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP);\
+ EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP);\
+ }while(0U)
/**
* @brief Generate a Software interrupt on selected EXTI line.
@@ -2006,7 +2024,6 @@
/**
* @}
*/
-
/* Exported functions --------------------------------------------------------*/
/** @addtogroup ETH_Exported_Functions
@@ -2018,7 +2035,6 @@
/** @addtogroup ETH_Exported_Functions_Group1
* @{
*/
-
HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth);
HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth);
void HAL_ETH_MspInit(ETH_HandleTypeDef *heth);
@@ -2029,7 +2045,6 @@
/**
* @}
*/
-
/* IO operation functions ****************************************************/
/** @addtogroup ETH_Exported_Functions_Group2
@@ -2040,14 +2055,13 @@
/* Communication with PHY functions*/
HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue);
HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue);
- /* Non-Blocking mode: Interrupt */
+/* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth);
void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth);
- /* Callback in non blocking modes (Interrupt) */
+/* Callback in non blocking modes (Interrupt) */
void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth);
void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth);
void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth);
-
/**
* @}
*/
@@ -2057,6 +2071,7 @@
/** @addtogroup ETH_Exported_Functions_Group3
* @{
*/
+
HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth);
HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth);
HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf);
@@ -2064,22 +2079,21 @@
/**
* @}
*/
-
+
/* Peripheral State functions ************************************************/
/** @addtogroup ETH_Exported_Functions_Group4
* @{
*/
HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth);
+/**
+ * @}
+ */
/**
* @}
*/
-
-/**
- * @}
- */
-
+
/**
* @}
*/
@@ -2087,7 +2101,7 @@
#endif /* STM32F107xC */
/**
* @}
- */
+ */
#ifdef __cplusplus
}
@@ -2096,5 +2110,4 @@
#endif /* __STM32F1xx_HAL_ETH_H */
-
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
