mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_eth.h@165:e614a9f1c9e2, 2017-05-26 (annotated)

Committer:
AnnaBridge
Date:
Fri May 26 12:39:01 2017 +0100
Revision:
165:e614a9f1c9e2
Parent:
154:37f96f9d4de2
Child:
187:0387e8f68319
This updates the lib to the mbed lib v 143

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f1xx_hal_eth.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
AnnaBridge 165:e614a9f1c9e2 5 * @version V1.1.0
AnnaBridge 165:e614a9f1c9e2 6 * @date 14-April-2017
<> 144:ef7eb2e8f9f7 7 * @brief Header file of ETH HAL module.
<> 144:ef7eb2e8f9f7 8 ******************************************************************************
<> 144:ef7eb2e8f9f7 9 * @attention
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 12 *
<> 144:ef7eb2e8f9f7 13 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 14 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 16 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 18 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 19 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 21 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 22 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 23 *
<> 144:ef7eb2e8f9f7 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 34 *
<> 144:ef7eb2e8f9f7 35 ******************************************************************************
<> 144:ef7eb2e8f9f7 36 */
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 /* Define to prevent recursive inclusion -------------------------------------*/
<> 144:ef7eb2e8f9f7 39 #ifndef __STM32F1xx_HAL_ETH_H
<> 144:ef7eb2e8f9f7 40 #define __STM32F1xx_HAL_ETH_H
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 43 extern "C" {
<> 144:ef7eb2e8f9f7 44 #endif
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 47 #include "stm32f1xx_hal_def.h"
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 /** @addtogroup STM32F1xx_HAL_Driver
<> 144:ef7eb2e8f9f7 50 * @{
<> 144:ef7eb2e8f9f7 51 */
<> 144:ef7eb2e8f9f7 52 #if defined (STM32F107xC)
<> 144:ef7eb2e8f9f7 53
<> 144:ef7eb2e8f9f7 54 /** @addtogroup ETH
<> 144:ef7eb2e8f9f7 55 * @{
<> 144:ef7eb2e8f9f7 56 */
<> 144:ef7eb2e8f9f7 57
<> 144:ef7eb2e8f9f7 58 /** @addtogroup ETH_Private_Macros
<> 144:ef7eb2e8f9f7 59 * @{
<> 144:ef7eb2e8f9f7 60 */
AnnaBridge 165:e614a9f1c9e2 61 #define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20U)
<> 144:ef7eb2e8f9f7 62 #define IS_ETH_AUTONEGOTIATION(CMD) (((CMD) == ETH_AUTONEGOTIATION_ENABLE) || \
<> 144:ef7eb2e8f9f7 63 ((CMD) == ETH_AUTONEGOTIATION_DISABLE))
<> 144:ef7eb2e8f9f7 64 #define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_SPEED_10M) || \
<> 144:ef7eb2e8f9f7 65 ((SPEED) == ETH_SPEED_100M))
<> 144:ef7eb2e8f9f7 66 #define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_MODE_FULLDUPLEX) || \
<> 144:ef7eb2e8f9f7 67 ((MODE) == ETH_MODE_HALFDUPLEX))
<> 144:ef7eb2e8f9f7 68 #define IS_ETH_RX_MODE(MODE) (((MODE) == ETH_RXPOLLING_MODE) || \
<> 144:ef7eb2e8f9f7 69 ((MODE) == ETH_RXINTERRUPT_MODE))
<> 144:ef7eb2e8f9f7 70 #define IS_ETH_CHECKSUM_MODE(MODE) (((MODE) == ETH_CHECKSUM_BY_HARDWARE) || \
<> 144:ef7eb2e8f9f7 71 ((MODE) == ETH_CHECKSUM_BY_SOFTWARE))
<> 144:ef7eb2e8f9f7 72 #define IS_ETH_MEDIA_INTERFACE(MODE) (((MODE) == ETH_MEDIA_INTERFACE_MII) || \
<> 144:ef7eb2e8f9f7 73 ((MODE) == ETH_MEDIA_INTERFACE_RMII))
<> 144:ef7eb2e8f9f7 74 #define IS_ETH_WATCHDOG(CMD) (((CMD) == ETH_WATCHDOG_ENABLE) || \
<> 144:ef7eb2e8f9f7 75 ((CMD) == ETH_WATCHDOG_DISABLE))
<> 144:ef7eb2e8f9f7 76 #define IS_ETH_JABBER(CMD) (((CMD) == ETH_JABBER_ENABLE) || \
<> 144:ef7eb2e8f9f7 77 ((CMD) == ETH_JABBER_DISABLE))
<> 144:ef7eb2e8f9f7 78 #define IS_ETH_INTER_FRAME_GAP(GAP) (((GAP) == ETH_INTERFRAMEGAP_96BIT) || \
<> 144:ef7eb2e8f9f7 79 ((GAP) == ETH_INTERFRAMEGAP_88BIT) || \
<> 144:ef7eb2e8f9f7 80 ((GAP) == ETH_INTERFRAMEGAP_80BIT) || \
<> 144:ef7eb2e8f9f7 81 ((GAP) == ETH_INTERFRAMEGAP_72BIT) || \
<> 144:ef7eb2e8f9f7 82 ((GAP) == ETH_INTERFRAMEGAP_64BIT) || \
<> 144:ef7eb2e8f9f7 83 ((GAP) == ETH_INTERFRAMEGAP_56BIT) || \
<> 144:ef7eb2e8f9f7 84 ((GAP) == ETH_INTERFRAMEGAP_48BIT) || \
<> 144:ef7eb2e8f9f7 85 ((GAP) == ETH_INTERFRAMEGAP_40BIT))
<> 144:ef7eb2e8f9f7 86 #define IS_ETH_CARRIER_SENSE(CMD) (((CMD) == ETH_CARRIERSENCE_ENABLE) || \
<> 144:ef7eb2e8f9f7 87 ((CMD) == ETH_CARRIERSENCE_DISABLE))
<> 144:ef7eb2e8f9f7 88 #define IS_ETH_RECEIVE_OWN(CMD) (((CMD) == ETH_RECEIVEOWN_ENABLE) || \
<> 144:ef7eb2e8f9f7 89 ((CMD) == ETH_RECEIVEOWN_DISABLE))
<> 144:ef7eb2e8f9f7 90 #define IS_ETH_LOOPBACK_MODE(CMD) (((CMD) == ETH_LOOPBACKMODE_ENABLE) || \
<> 144:ef7eb2e8f9f7 91 ((CMD) == ETH_LOOPBACKMODE_DISABLE))
<> 144:ef7eb2e8f9f7 92 #define IS_ETH_CHECKSUM_OFFLOAD(CMD) (((CMD) == ETH_CHECKSUMOFFLAOD_ENABLE) || \
<> 144:ef7eb2e8f9f7 93 ((CMD) == ETH_CHECKSUMOFFLAOD_DISABLE))
<> 144:ef7eb2e8f9f7 94 #define IS_ETH_RETRY_TRANSMISSION(CMD) (((CMD) == ETH_RETRYTRANSMISSION_ENABLE) || \
<> 144:ef7eb2e8f9f7 95 ((CMD) == ETH_RETRYTRANSMISSION_DISABLE))
<> 144:ef7eb2e8f9f7 96 #define IS_ETH_AUTOMATIC_PADCRC_STRIP(CMD) (((CMD) == ETH_AUTOMATICPADCRCSTRIP_ENABLE) || \
<> 144:ef7eb2e8f9f7 97 ((CMD) == ETH_AUTOMATICPADCRCSTRIP_DISABLE))
<> 144:ef7eb2e8f9f7 98 #define IS_ETH_BACKOFF_LIMIT(LIMIT) (((LIMIT) == ETH_BACKOFFLIMIT_10) || \
<> 144:ef7eb2e8f9f7 99 ((LIMIT) == ETH_BACKOFFLIMIT_8) || \
<> 144:ef7eb2e8f9f7 100 ((LIMIT) == ETH_BACKOFFLIMIT_4) || \
<> 144:ef7eb2e8f9f7 101 ((LIMIT) == ETH_BACKOFFLIMIT_1))
<> 144:ef7eb2e8f9f7 102 #define IS_ETH_DEFERRAL_CHECK(CMD) (((CMD) == ETH_DEFFERRALCHECK_ENABLE) || \
<> 144:ef7eb2e8f9f7 103 ((CMD) == ETH_DEFFERRALCHECK_DISABLE))
<> 144:ef7eb2e8f9f7 104 #define IS_ETH_RECEIVE_ALL(CMD) (((CMD) == ETH_RECEIVEALL_ENABLE) || \
<> 144:ef7eb2e8f9f7 105 ((CMD) == ETH_RECEIVEAll_DISABLE))
<> 144:ef7eb2e8f9f7 106 #define IS_ETH_SOURCE_ADDR_FILTER(CMD) (((CMD) == ETH_SOURCEADDRFILTER_NORMAL_ENABLE) || \
<> 144:ef7eb2e8f9f7 107 ((CMD) == ETH_SOURCEADDRFILTER_INVERSE_ENABLE) || \
<> 144:ef7eb2e8f9f7 108 ((CMD) == ETH_SOURCEADDRFILTER_DISABLE))
<> 144:ef7eb2e8f9f7 109 #define IS_ETH_CONTROL_FRAMES(PASS) (((PASS) == ETH_PASSCONTROLFRAMES_BLOCKALL) || \
<> 144:ef7eb2e8f9f7 110 ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDALL) || \
<> 144:ef7eb2e8f9f7 111 ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER))
<> 144:ef7eb2e8f9f7 112 #define IS_ETH_BROADCAST_FRAMES_RECEPTION(CMD) (((CMD) == ETH_BROADCASTFRAMESRECEPTION_ENABLE) || \
<> 144:ef7eb2e8f9f7 113 ((CMD) == ETH_BROADCASTFRAMESRECEPTION_DISABLE))
<> 144:ef7eb2e8f9f7 114 #define IS_ETH_DESTINATION_ADDR_FILTER(FILTER) (((FILTER) == ETH_DESTINATIONADDRFILTER_NORMAL) || \
<> 144:ef7eb2e8f9f7 115 ((FILTER) == ETH_DESTINATIONADDRFILTER_INVERSE))
<> 144:ef7eb2e8f9f7 116 #define IS_ETH_PROMISCUOUS_MODE(CMD) (((CMD) == ETH_PROMISCUOUS_MODE_ENABLE) || \
<> 144:ef7eb2e8f9f7 117 ((CMD) == ETH_PROMISCUOUS_MODE_DISABLE))
<> 144:ef7eb2e8f9f7 118 #define IS_ETH_MULTICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE) || \
<> 144:ef7eb2e8f9f7 119 ((FILTER) == ETH_MULTICASTFRAMESFILTER_HASHTABLE) || \
<> 144:ef7eb2e8f9f7 120 ((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECT) || \
<> 144:ef7eb2e8f9f7 121 ((FILTER) == ETH_MULTICASTFRAMESFILTER_NONE))
<> 144:ef7eb2e8f9f7 122 #define IS_ETH_UNICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE) || \
<> 144:ef7eb2e8f9f7 123 ((FILTER) == ETH_UNICASTFRAMESFILTER_HASHTABLE) || \
<> 144:ef7eb2e8f9f7 124 ((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECT))
AnnaBridge 165:e614a9f1c9e2 125 #define IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFFU)
<> 144:ef7eb2e8f9f7 126 #define IS_ETH_ZEROQUANTA_PAUSE(CMD) (((CMD) == ETH_ZEROQUANTAPAUSE_ENABLE) || \
<> 144:ef7eb2e8f9f7 127 ((CMD) == ETH_ZEROQUANTAPAUSE_DISABLE))
<> 144:ef7eb2e8f9f7 128 #define IS_ETH_PAUSE_LOW_THRESHOLD(THRESHOLD) (((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS4) || \
<> 144:ef7eb2e8f9f7 129 ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS28) || \
<> 144:ef7eb2e8f9f7 130 ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS144) || \
<> 144:ef7eb2e8f9f7 131 ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS256))
<> 144:ef7eb2e8f9f7 132 #define IS_ETH_UNICAST_PAUSE_FRAME_DETECT(CMD) (((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_ENABLE) || \
<> 144:ef7eb2e8f9f7 133 ((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_DISABLE))
<> 144:ef7eb2e8f9f7 134 #define IS_ETH_RECEIVE_FLOWCONTROL(CMD) (((CMD) == ETH_RECEIVEFLOWCONTROL_ENABLE) || \
<> 144:ef7eb2e8f9f7 135 ((CMD) == ETH_RECEIVEFLOWCONTROL_DISABLE))
<> 144:ef7eb2e8f9f7 136 #define IS_ETH_TRANSMIT_FLOWCONTROL(CMD) (((CMD) == ETH_TRANSMITFLOWCONTROL_ENABLE) || \
<> 144:ef7eb2e8f9f7 137 ((CMD) == ETH_TRANSMITFLOWCONTROL_DISABLE))
<> 144:ef7eb2e8f9f7 138 #define IS_ETH_VLAN_TAG_COMPARISON(COMPARISON) (((COMPARISON) == ETH_VLANTAGCOMPARISON_12BIT) || \
<> 144:ef7eb2e8f9f7 139 ((COMPARISON) == ETH_VLANTAGCOMPARISON_16BIT))
AnnaBridge 165:e614a9f1c9e2 140 #define IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFFU)
<> 144:ef7eb2e8f9f7 141 #define IS_ETH_MAC_ADDRESS0123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS0) || \
<> 144:ef7eb2e8f9f7 142 ((ADDRESS) == ETH_MAC_ADDRESS1) || \
<> 144:ef7eb2e8f9f7 143 ((ADDRESS) == ETH_MAC_ADDRESS2) || \
<> 144:ef7eb2e8f9f7 144 ((ADDRESS) == ETH_MAC_ADDRESS3))
<> 144:ef7eb2e8f9f7 145 #define IS_ETH_MAC_ADDRESS123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS1) || \
<> 144:ef7eb2e8f9f7 146 ((ADDRESS) == ETH_MAC_ADDRESS2) || \
<> 144:ef7eb2e8f9f7 147 ((ADDRESS) == ETH_MAC_ADDRESS3))
<> 144:ef7eb2e8f9f7 148 #define IS_ETH_MAC_ADDRESS_FILTER(FILTER) (((FILTER) == ETH_MAC_ADDRESSFILTER_SA) || \
<> 144:ef7eb2e8f9f7 149 ((FILTER) == ETH_MAC_ADDRESSFILTER_DA))
<> 144:ef7eb2e8f9f7 150 #define IS_ETH_MAC_ADDRESS_MASK(MASK) (((MASK) == ETH_MAC_ADDRESSMASK_BYTE6) || \
<> 144:ef7eb2e8f9f7 151 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE5) || \
<> 144:ef7eb2e8f9f7 152 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE4) || \
<> 144:ef7eb2e8f9f7 153 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE3) || \
<> 144:ef7eb2e8f9f7 154 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE2) || \
<> 144:ef7eb2e8f9f7 155 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE1))
<> 144:ef7eb2e8f9f7 156 #define IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(CMD) (((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE) || \
<> 144:ef7eb2e8f9f7 157 ((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE))
<> 144:ef7eb2e8f9f7 158 #define IS_ETH_RECEIVE_STORE_FORWARD(CMD) (((CMD) == ETH_RECEIVESTOREFORWARD_ENABLE) || \
<> 144:ef7eb2e8f9f7 159 ((CMD) == ETH_RECEIVESTOREFORWARD_DISABLE))
<> 144:ef7eb2e8f9f7 160 #define IS_ETH_FLUSH_RECEIVE_FRAME(CMD) (((CMD) == ETH_FLUSHRECEIVEDFRAME_ENABLE) || \
<> 144:ef7eb2e8f9f7 161 ((CMD) == ETH_FLUSHRECEIVEDFRAME_DISABLE))
<> 144:ef7eb2e8f9f7 162 #define IS_ETH_TRANSMIT_STORE_FORWARD(CMD) (((CMD) == ETH_TRANSMITSTOREFORWARD_ENABLE) || \
<> 144:ef7eb2e8f9f7 163 ((CMD) == ETH_TRANSMITSTOREFORWARD_DISABLE))
<> 144:ef7eb2e8f9f7 164 #define IS_ETH_TRANSMIT_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_64BYTES) || \
<> 144:ef7eb2e8f9f7 165 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_128BYTES) || \
<> 144:ef7eb2e8f9f7 166 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_192BYTES) || \
<> 144:ef7eb2e8f9f7 167 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_256BYTES) || \
<> 144:ef7eb2e8f9f7 168 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_40BYTES) || \
<> 144:ef7eb2e8f9f7 169 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_32BYTES) || \
<> 144:ef7eb2e8f9f7 170 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_24BYTES) || \
<> 144:ef7eb2e8f9f7 171 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_16BYTES))
<> 144:ef7eb2e8f9f7 172 #define IS_ETH_FORWARD_ERROR_FRAMES(CMD) (((CMD) == ETH_FORWARDERRORFRAMES_ENABLE) || \
<> 144:ef7eb2e8f9f7 173 ((CMD) == ETH_FORWARDERRORFRAMES_DISABLE))
<> 144:ef7eb2e8f9f7 174 #define IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(CMD) (((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE) || \
<> 144:ef7eb2e8f9f7 175 ((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE))
<> 144:ef7eb2e8f9f7 176 #define IS_ETH_RECEIVE_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES) || \
<> 144:ef7eb2e8f9f7 177 ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES) || \
<> 144:ef7eb2e8f9f7 178 ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES) || \
<> 144:ef7eb2e8f9f7 179 ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES))
<> 144:ef7eb2e8f9f7 180 #define IS_ETH_SECOND_FRAME_OPERATE(CMD) (((CMD) == ETH_SECONDFRAMEOPERARTE_ENABLE) || \
<> 144:ef7eb2e8f9f7 181 ((CMD) == ETH_SECONDFRAMEOPERARTE_DISABLE))
<> 144:ef7eb2e8f9f7 182 #define IS_ETH_ADDRESS_ALIGNED_BEATS(CMD) (((CMD) == ETH_ADDRESSALIGNEDBEATS_ENABLE) || \
<> 144:ef7eb2e8f9f7 183 ((CMD) == ETH_ADDRESSALIGNEDBEATS_DISABLE))
<> 144:ef7eb2e8f9f7 184 #define IS_ETH_FIXED_BURST(CMD) (((CMD) == ETH_FIXEDBURST_ENABLE) || \
<> 144:ef7eb2e8f9f7 185 ((CMD) == ETH_FIXEDBURST_DISABLE))
<> 144:ef7eb2e8f9f7 186 #define IS_ETH_RXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_RXDMABURSTLENGTH_1BEAT) || \
<> 144:ef7eb2e8f9f7 187 ((LENGTH) == ETH_RXDMABURSTLENGTH_2BEAT) || \
<> 144:ef7eb2e8f9f7 188 ((LENGTH) == ETH_RXDMABURSTLENGTH_4BEAT) || \
<> 144:ef7eb2e8f9f7 189 ((LENGTH) == ETH_RXDMABURSTLENGTH_8BEAT) || \
<> 144:ef7eb2e8f9f7 190 ((LENGTH) == ETH_RXDMABURSTLENGTH_16BEAT) || \
<> 144:ef7eb2e8f9f7 191 ((LENGTH) == ETH_RXDMABURSTLENGTH_32BEAT) || \
<> 144:ef7eb2e8f9f7 192 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_4BEAT) || \
<> 144:ef7eb2e8f9f7 193 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_8BEAT) || \
<> 144:ef7eb2e8f9f7 194 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_16BEAT) || \
<> 144:ef7eb2e8f9f7 195 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_32BEAT) || \
<> 144:ef7eb2e8f9f7 196 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_64BEAT) || \
<> 144:ef7eb2e8f9f7 197 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_128BEAT))
<> 144:ef7eb2e8f9f7 198 #define IS_ETH_TXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_TXDMABURSTLENGTH_1BEAT) || \
<> 144:ef7eb2e8f9f7 199 ((LENGTH) == ETH_TXDMABURSTLENGTH_2BEAT) || \
<> 144:ef7eb2e8f9f7 200 ((LENGTH) == ETH_TXDMABURSTLENGTH_4BEAT) || \
<> 144:ef7eb2e8f9f7 201 ((LENGTH) == ETH_TXDMABURSTLENGTH_8BEAT) || \
<> 144:ef7eb2e8f9f7 202 ((LENGTH) == ETH_TXDMABURSTLENGTH_16BEAT) || \
<> 144:ef7eb2e8f9f7 203 ((LENGTH) == ETH_TXDMABURSTLENGTH_32BEAT) || \
<> 144:ef7eb2e8f9f7 204 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_4BEAT) || \
<> 144:ef7eb2e8f9f7 205 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_8BEAT) || \
<> 144:ef7eb2e8f9f7 206 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_16BEAT) || \
<> 144:ef7eb2e8f9f7 207 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_32BEAT) || \
<> 144:ef7eb2e8f9f7 208 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_64BEAT) || \
<> 144:ef7eb2e8f9f7 209 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_128BEAT))
AnnaBridge 165:e614a9f1c9e2 210 #define IS_ETH_DMA_DESC_SKIP_LENGTH(LENGTH) ((LENGTH) <= 0x1FU)
<> 144:ef7eb2e8f9f7 211 #define IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(RATIO) (((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1) || \
<> 144:ef7eb2e8f9f7 212 ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1) || \
<> 144:ef7eb2e8f9f7 213 ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1) || \
<> 144:ef7eb2e8f9f7 214 ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1) || \
<> 144:ef7eb2e8f9f7 215 ((RATIO) == ETH_DMAARBITRATION_RXPRIORTX))
AnnaBridge 165:e614a9f1c9e2 216 #define IS_ETH_DMATXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMATXDESC_OWN) || \
AnnaBridge 165:e614a9f1c9e2 217 ((FLAG) == ETH_DMATXDESC_IC) || \
AnnaBridge 165:e614a9f1c9e2 218 ((FLAG) == ETH_DMATXDESC_LS) || \
AnnaBridge 165:e614a9f1c9e2 219 ((FLAG) == ETH_DMATXDESC_FS) || \
AnnaBridge 165:e614a9f1c9e2 220 ((FLAG) == ETH_DMATXDESC_DC) || \
AnnaBridge 165:e614a9f1c9e2 221 ((FLAG) == ETH_DMATXDESC_DP) || \
AnnaBridge 165:e614a9f1c9e2 222 ((FLAG) == ETH_DMATXDESC_TTSE) || \
AnnaBridge 165:e614a9f1c9e2 223 ((FLAG) == ETH_DMATXDESC_TER) || \
AnnaBridge 165:e614a9f1c9e2 224 ((FLAG) == ETH_DMATXDESC_TCH) || \
AnnaBridge 165:e614a9f1c9e2 225 ((FLAG) == ETH_DMATXDESC_TTSS) || \
AnnaBridge 165:e614a9f1c9e2 226 ((FLAG) == ETH_DMATXDESC_IHE) || \
AnnaBridge 165:e614a9f1c9e2 227 ((FLAG) == ETH_DMATXDESC_ES) || \
AnnaBridge 165:e614a9f1c9e2 228 ((FLAG) == ETH_DMATXDESC_JT) || \
AnnaBridge 165:e614a9f1c9e2 229 ((FLAG) == ETH_DMATXDESC_FF) || \
AnnaBridge 165:e614a9f1c9e2 230 ((FLAG) == ETH_DMATXDESC_PCE) || \
AnnaBridge 165:e614a9f1c9e2 231 ((FLAG) == ETH_DMATXDESC_LCA) || \
AnnaBridge 165:e614a9f1c9e2 232 ((FLAG) == ETH_DMATXDESC_NC) || \
AnnaBridge 165:e614a9f1c9e2 233 ((FLAG) == ETH_DMATXDESC_LCO) || \
AnnaBridge 165:e614a9f1c9e2 234 ((FLAG) == ETH_DMATXDESC_EC) || \
AnnaBridge 165:e614a9f1c9e2 235 ((FLAG) == ETH_DMATXDESC_VF) || \
AnnaBridge 165:e614a9f1c9e2 236 ((FLAG) == ETH_DMATXDESC_CC) || \
AnnaBridge 165:e614a9f1c9e2 237 ((FLAG) == ETH_DMATXDESC_ED) || \
AnnaBridge 165:e614a9f1c9e2 238 ((FLAG) == ETH_DMATXDESC_UF) || \
AnnaBridge 165:e614a9f1c9e2 239 ((FLAG) == ETH_DMATXDESC_DB))
<> 144:ef7eb2e8f9f7 240 #define IS_ETH_DMA_TXDESC_SEGMENT(SEGMENT) (((SEGMENT) == ETH_DMATXDESC_LASTSEGMENTS) || \
<> 144:ef7eb2e8f9f7 241 ((SEGMENT) == ETH_DMATXDESC_FIRSTSEGMENT))
<> 144:ef7eb2e8f9f7 242 #define IS_ETH_DMA_TXDESC_CHECKSUM(CHECKSUM) (((CHECKSUM) == ETH_DMATXDESC_CHECKSUMBYPASS) || \
<> 144:ef7eb2e8f9f7 243 ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMIPV4HEADER) || \
<> 144:ef7eb2e8f9f7 244 ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT) || \
<> 144:ef7eb2e8f9f7 245 ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL))
AnnaBridge 165:e614a9f1c9e2 246 #define IS_ETH_DMATXDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFFU)
AnnaBridge 165:e614a9f1c9e2 247 #define IS_ETH_DMARXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMARXDESC_OWN) || \
AnnaBridge 165:e614a9f1c9e2 248 ((FLAG) == ETH_DMARXDESC_AFM) || \
AnnaBridge 165:e614a9f1c9e2 249 ((FLAG) == ETH_DMARXDESC_ES) || \
AnnaBridge 165:e614a9f1c9e2 250 ((FLAG) == ETH_DMARXDESC_DE) || \
AnnaBridge 165:e614a9f1c9e2 251 ((FLAG) == ETH_DMARXDESC_SAF) || \
AnnaBridge 165:e614a9f1c9e2 252 ((FLAG) == ETH_DMARXDESC_LE) || \
AnnaBridge 165:e614a9f1c9e2 253 ((FLAG) == ETH_DMARXDESC_OE) || \
AnnaBridge 165:e614a9f1c9e2 254 ((FLAG) == ETH_DMARXDESC_VLAN) || \
AnnaBridge 165:e614a9f1c9e2 255 ((FLAG) == ETH_DMARXDESC_FS) || \
AnnaBridge 165:e614a9f1c9e2 256 ((FLAG) == ETH_DMARXDESC_LS) || \
AnnaBridge 165:e614a9f1c9e2 257 ((FLAG) == ETH_DMARXDESC_IPV4HCE) || \
AnnaBridge 165:e614a9f1c9e2 258 ((FLAG) == ETH_DMARXDESC_LC) || \
AnnaBridge 165:e614a9f1c9e2 259 ((FLAG) == ETH_DMARXDESC_FT) || \
AnnaBridge 165:e614a9f1c9e2 260 ((FLAG) == ETH_DMARXDESC_RWT) || \
AnnaBridge 165:e614a9f1c9e2 261 ((FLAG) == ETH_DMARXDESC_RE) || \
AnnaBridge 165:e614a9f1c9e2 262 ((FLAG) == ETH_DMARXDESC_DBE) || \
AnnaBridge 165:e614a9f1c9e2 263 ((FLAG) == ETH_DMARXDESC_CE) || \
AnnaBridge 165:e614a9f1c9e2 264 ((FLAG) == ETH_DMARXDESC_MAMPCE))
<> 144:ef7eb2e8f9f7 265 #define IS_ETH_DMA_RXDESC_BUFFER(BUFFER) (((BUFFER) == ETH_DMARXDESC_BUFFER1) || \
<> 144:ef7eb2e8f9f7 266 ((BUFFER) == ETH_DMARXDESC_BUFFER2))
AnnaBridge 165:e614a9f1c9e2 267 #define IS_ETH_PMT_GET_FLAG(FLAG) (((FLAG) == ETH_PMT_FLAG_WUFR) || \
AnnaBridge 165:e614a9f1c9e2 268 ((FLAG) == ETH_PMT_FLAG_MPR))
AnnaBridge 165:e614a9f1c9e2 269 #define IS_ETH_DMA_FLAG(FLAG) ((((FLAG) & 0xC7FE1800U) == 0x00U) && ((FLAG) != 0x00U))
AnnaBridge 165:e614a9f1c9e2 270 #define IS_ETH_DMA_GET_FLAG(FLAG) (((FLAG) == ETH_DMA_FLAG_TST) || ((FLAG) == ETH_DMA_FLAG_PMT) || \
AnnaBridge 165:e614a9f1c9e2 271 ((FLAG) == ETH_DMA_FLAG_MMC) || ((FLAG) == ETH_DMA_FLAG_DATATRANSFERERROR) || \
AnnaBridge 165:e614a9f1c9e2 272 ((FLAG) == ETH_DMA_FLAG_READWRITEERROR) || ((FLAG) == ETH_DMA_FLAG_ACCESSERROR) || \
AnnaBridge 165:e614a9f1c9e2 273 ((FLAG) == ETH_DMA_FLAG_NIS) || ((FLAG) == ETH_DMA_FLAG_AIS) || \
AnnaBridge 165:e614a9f1c9e2 274 ((FLAG) == ETH_DMA_FLAG_ER) || ((FLAG) == ETH_DMA_FLAG_FBE) || \
AnnaBridge 165:e614a9f1c9e2 275 ((FLAG) == ETH_DMA_FLAG_ET) || ((FLAG) == ETH_DMA_FLAG_RWT) || \
AnnaBridge 165:e614a9f1c9e2 276 ((FLAG) == ETH_DMA_FLAG_RPS) || ((FLAG) == ETH_DMA_FLAG_RBU) || \
AnnaBridge 165:e614a9f1c9e2 277 ((FLAG) == ETH_DMA_FLAG_R) || ((FLAG) == ETH_DMA_FLAG_TU) || \
AnnaBridge 165:e614a9f1c9e2 278 ((FLAG) == ETH_DMA_FLAG_RO) || ((FLAG) == ETH_DMA_FLAG_TJT) || \
AnnaBridge 165:e614a9f1c9e2 279 ((FLAG) == ETH_DMA_FLAG_TBU) || ((FLAG) == ETH_DMA_FLAG_TPS) || \
AnnaBridge 165:e614a9f1c9e2 280 ((FLAG) == ETH_DMA_FLAG_T))
AnnaBridge 165:e614a9f1c9e2 281 #define IS_ETH_MAC_IT(IT) ((((IT) & 0xFFFFFDF1U) == 0x00U) && ((IT) != 0x00U))
AnnaBridge 165:e614a9f1c9e2 282 #define IS_ETH_MAC_GET_IT(IT) (((IT) == ETH_MAC_IT_TST) || ((IT) == ETH_MAC_IT_MMCT) || \
AnnaBridge 165:e614a9f1c9e2 283 ((IT) == ETH_MAC_IT_MMCR) || ((IT) == ETH_MAC_IT_MMC) || \
AnnaBridge 165:e614a9f1c9e2 284 ((IT) == ETH_MAC_IT_PMT))
AnnaBridge 165:e614a9f1c9e2 285 #define IS_ETH_MAC_GET_FLAG(FLAG) (((FLAG) == ETH_MAC_FLAG_TST) || ((FLAG) == ETH_MAC_FLAG_MMCT) || \
AnnaBridge 165:e614a9f1c9e2 286 ((FLAG) == ETH_MAC_FLAG_MMCR) || ((FLAG) == ETH_MAC_FLAG_MMC) || \
AnnaBridge 165:e614a9f1c9e2 287 ((FLAG) == ETH_MAC_FLAG_PMT))
AnnaBridge 165:e614a9f1c9e2 288 #define IS_ETH_DMA_IT(IT) ((((IT) & 0xC7FE1800U) == 0x00U) && ((IT) != 0x00U))
AnnaBridge 165:e614a9f1c9e2 289 #define IS_ETH_DMA_GET_IT(IT) (((IT) == ETH_DMA_IT_TST) || ((IT) == ETH_DMA_IT_PMT) || \
AnnaBridge 165:e614a9f1c9e2 290 ((IT) == ETH_DMA_IT_MMC) || ((IT) == ETH_DMA_IT_NIS) || \
AnnaBridge 165:e614a9f1c9e2 291 ((IT) == ETH_DMA_IT_AIS) || ((IT) == ETH_DMA_IT_ER) || \
AnnaBridge 165:e614a9f1c9e2 292 ((IT) == ETH_DMA_IT_FBE) || ((IT) == ETH_DMA_IT_ET) || \
AnnaBridge 165:e614a9f1c9e2 293 ((IT) == ETH_DMA_IT_RWT) || ((IT) == ETH_DMA_IT_RPS) || \
AnnaBridge 165:e614a9f1c9e2 294 ((IT) == ETH_DMA_IT_RBU) || ((IT) == ETH_DMA_IT_R) || \
AnnaBridge 165:e614a9f1c9e2 295 ((IT) == ETH_DMA_IT_TU) || ((IT) == ETH_DMA_IT_RO) || \
AnnaBridge 165:e614a9f1c9e2 296 ((IT) == ETH_DMA_IT_TJT) || ((IT) == ETH_DMA_IT_TBU) || \
AnnaBridge 165:e614a9f1c9e2 297 ((IT) == ETH_DMA_IT_TPS) || ((IT) == ETH_DMA_IT_T))
<> 144:ef7eb2e8f9f7 298 #define IS_ETH_DMA_GET_OVERFLOW(OVERFLOW) (((OVERFLOW) == ETH_DMA_OVERFLOW_RXFIFOCOUNTER) || \
<> 144:ef7eb2e8f9f7 299 ((OVERFLOW) == ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER))
AnnaBridge 165:e614a9f1c9e2 300 #define IS_ETH_MMC_IT(IT) (((((IT) & 0xFFDF3FFFU) == 0x00U) || (((IT) & 0xEFFDFF9FU) == 0x00U)) && \
AnnaBridge 165:e614a9f1c9e2 301 ((IT) != 0x00U))
AnnaBridge 165:e614a9f1c9e2 302 #define IS_ETH_MMC_GET_IT(IT) (((IT) == ETH_MMC_IT_TGF) || ((IT) == ETH_MMC_IT_TGFMSC) || \
AnnaBridge 165:e614a9f1c9e2 303 ((IT) == ETH_MMC_IT_TGFSC) || ((IT) == ETH_MMC_IT_RGUF) || \
AnnaBridge 165:e614a9f1c9e2 304 ((IT) == ETH_MMC_IT_RFAE) || ((IT) == ETH_MMC_IT_RFCE))
AnnaBridge 165:e614a9f1c9e2 305 #define IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(CMD) (((CMD) == ETH_DMAENHANCEDDESCRIPTOR_ENABLE) || \
AnnaBridge 165:e614a9f1c9e2 306 ((CMD) == ETH_DMAENHANCEDDESCRIPTOR_DISABLE))
<> 144:ef7eb2e8f9f7 307
<> 144:ef7eb2e8f9f7 308 /**
<> 144:ef7eb2e8f9f7 309 * @}
<> 144:ef7eb2e8f9f7 310 */
<> 144:ef7eb2e8f9f7 311
AnnaBridge 165:e614a9f1c9e2 312 /** @addtogroup ETH_Private_Defines
<> 144:ef7eb2e8f9f7 313 * @{
<> 144:ef7eb2e8f9f7 314 */
<> 144:ef7eb2e8f9f7 315 /* Delay to wait when writing to some Ethernet registers */
AnnaBridge 165:e614a9f1c9e2 316 #define ETH_REG_WRITE_DELAY 0x00000001U
<> 144:ef7eb2e8f9f7 317
<> 144:ef7eb2e8f9f7 318 /* ETHERNET Errors */
AnnaBridge 165:e614a9f1c9e2 319 #define ETH_SUCCESS 0U
AnnaBridge 165:e614a9f1c9e2 320 #define ETH_ERROR 1U
<> 144:ef7eb2e8f9f7 321
<> 144:ef7eb2e8f9f7 322 /* ETHERNET DMA Tx descriptors Collision Count Shift */
AnnaBridge 165:e614a9f1c9e2 323 #define ETH_DMATXDESC_COLLISION_COUNTSHIFT 3U
<> 144:ef7eb2e8f9f7 324
<> 144:ef7eb2e8f9f7 325 /* ETHERNET DMA Tx descriptors Buffer2 Size Shift */
AnnaBridge 165:e614a9f1c9e2 326 #define ETH_DMATXDESC_BUFFER2_SIZESHIFT 16U
<> 144:ef7eb2e8f9f7 327
<> 144:ef7eb2e8f9f7 328 /* ETHERNET DMA Rx descriptors Frame Length Shift */
AnnaBridge 165:e614a9f1c9e2 329 #define ETH_DMARXDESC_FRAME_LENGTHSHIFT 16U
<> 144:ef7eb2e8f9f7 330
<> 144:ef7eb2e8f9f7 331 /* ETHERNET DMA Rx descriptors Buffer2 Size Shift */
AnnaBridge 165:e614a9f1c9e2 332 #define ETH_DMARXDESC_BUFFER2_SIZESHIFT 16U
<> 144:ef7eb2e8f9f7 333
<> 144:ef7eb2e8f9f7 334 /* ETHERNET DMA Rx descriptors Frame length Shift */
AnnaBridge 165:e614a9f1c9e2 335 #define ETH_DMARXDESC_FRAMELENGTHSHIFT 16U
<> 144:ef7eb2e8f9f7 336
<> 144:ef7eb2e8f9f7 337 /* ETHERNET MAC address offsets */
AnnaBridge 165:e614a9f1c9e2 338 #define ETH_MAC_ADDR_HBASE (uint32_t)(ETH_MAC_BASE + 0x40U) /* ETHERNET MAC address high offset */
AnnaBridge 165:e614a9f1c9e2 339 #define ETH_MAC_ADDR_LBASE (uint32_t)(ETH_MAC_BASE + 0x44U) /* ETHERNET MAC address low offset */
<> 144:ef7eb2e8f9f7 340
<> 144:ef7eb2e8f9f7 341 /* ETHERNET MACMIIAR register Mask */
AnnaBridge 165:e614a9f1c9e2 342 #define ETH_MACMIIAR_CR_MASK 0xFFFFFFE3U
<> 144:ef7eb2e8f9f7 343
<> 144:ef7eb2e8f9f7 344 /* ETHERNET MACCR register Mask */
AnnaBridge 165:e614a9f1c9e2 345 #define ETH_MACCR_CLEAR_MASK 0xFF20810FU
<> 144:ef7eb2e8f9f7 346
<> 144:ef7eb2e8f9f7 347 /* ETHERNET MACFCR register Mask */
AnnaBridge 165:e614a9f1c9e2 348 #define ETH_MACFCR_CLEAR_MASK 0x0000FF41U
<> 144:ef7eb2e8f9f7 349
<> 144:ef7eb2e8f9f7 350 /* ETHERNET DMAOMR register Mask */
AnnaBridge 165:e614a9f1c9e2 351 #define ETH_DMAOMR_CLEAR_MASK 0xF8DE3F23U
<> 144:ef7eb2e8f9f7 352
<> 144:ef7eb2e8f9f7 353 /* ETHERNET Remote Wake-up frame register length */
AnnaBridge 165:e614a9f1c9e2 354 #define ETH_WAKEUP_REGISTER_LENGTH 8U
<> 144:ef7eb2e8f9f7 355
<> 144:ef7eb2e8f9f7 356 /* ETHERNET Missed frames counter Shift */
AnnaBridge 165:e614a9f1c9e2 357 #define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT 17U
<> 144:ef7eb2e8f9f7 358 /**
<> 144:ef7eb2e8f9f7 359 * @}
AnnaBridge 165:e614a9f1c9e2 360 */
<> 144:ef7eb2e8f9f7 361
<> 144:ef7eb2e8f9f7 362 /* Exported types ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 363 /** @defgroup ETH_Exported_Types ETH Exported Types
<> 144:ef7eb2e8f9f7 364 * @{
<> 144:ef7eb2e8f9f7 365 */
<> 144:ef7eb2e8f9f7 366
<> 144:ef7eb2e8f9f7 367 /**
<> 144:ef7eb2e8f9f7 368 * @brief HAL State structures definition
<> 144:ef7eb2e8f9f7 369 */
<> 144:ef7eb2e8f9f7 370 typedef enum
<> 144:ef7eb2e8f9f7 371 {
AnnaBridge 165:e614a9f1c9e2 372 HAL_ETH_STATE_RESET = 0x00U, /*!< Peripheral not yet Initialized or disabled */
AnnaBridge 165:e614a9f1c9e2 373 HAL_ETH_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
AnnaBridge 165:e614a9f1c9e2 374 HAL_ETH_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */
AnnaBridge 165:e614a9f1c9e2 375 HAL_ETH_STATE_BUSY_TX = 0x12U, /*!< Data Transmission process is ongoing */
AnnaBridge 165:e614a9f1c9e2 376 HAL_ETH_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */
AnnaBridge 165:e614a9f1c9e2 377 HAL_ETH_STATE_BUSY_TX_RX = 0x32U, /*!< Data Transmission and Reception process is ongoing */
AnnaBridge 165:e614a9f1c9e2 378 HAL_ETH_STATE_BUSY_WR = 0x42U, /*!< Write process is ongoing */
AnnaBridge 165:e614a9f1c9e2 379 HAL_ETH_STATE_BUSY_RD = 0x82U, /*!< Read process is ongoing */
AnnaBridge 165:e614a9f1c9e2 380 HAL_ETH_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
AnnaBridge 165:e614a9f1c9e2 381 HAL_ETH_STATE_ERROR = 0x04U /*!< Reception process is ongoing */
<> 144:ef7eb2e8f9f7 382 }HAL_ETH_StateTypeDef;
<> 144:ef7eb2e8f9f7 383
<> 144:ef7eb2e8f9f7 384 /**
<> 144:ef7eb2e8f9f7 385 * @brief ETH Init Structure definition
<> 144:ef7eb2e8f9f7 386 */
<> 144:ef7eb2e8f9f7 387
<> 144:ef7eb2e8f9f7 388 typedef struct
<> 144:ef7eb2e8f9f7 389 {
<> 144:ef7eb2e8f9f7 390 uint32_t AutoNegotiation; /*!< Selects or not the AutoNegotiation mode for the external PHY
<> 144:ef7eb2e8f9f7 391 The AutoNegotiation allows an automatic setting of the Speed (10/100Mbps)
<> 144:ef7eb2e8f9f7 392 and the mode (half/full-duplex).
<> 144:ef7eb2e8f9f7 393 This parameter can be a value of @ref ETH_AutoNegotiation */
<> 144:ef7eb2e8f9f7 394
<> 144:ef7eb2e8f9f7 395 uint32_t Speed; /*!< Sets the Ethernet speed: 10/100 Mbps.
<> 144:ef7eb2e8f9f7 396 This parameter can be a value of @ref ETH_Speed */
<> 144:ef7eb2e8f9f7 397
<> 144:ef7eb2e8f9f7 398 uint32_t DuplexMode; /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode
<> 144:ef7eb2e8f9f7 399 This parameter can be a value of @ref ETH_Duplex_Mode */
<> 144:ef7eb2e8f9f7 400
<> 144:ef7eb2e8f9f7 401 uint16_t PhyAddress; /*!< Ethernet PHY address.
<> 144:ef7eb2e8f9f7 402 This parameter must be a number between Min_Data = 0 and Max_Data = 32 */
<> 144:ef7eb2e8f9f7 403
<> 144:ef7eb2e8f9f7 404 uint8_t *MACAddr; /*!< MAC Address of used Hardware: must be pointer on an array of 6 bytes */
<> 144:ef7eb2e8f9f7 405
<> 144:ef7eb2e8f9f7 406 uint32_t RxMode; /*!< Selects the Ethernet Rx mode: Polling mode, Interrupt mode.
<> 144:ef7eb2e8f9f7 407 This parameter can be a value of @ref ETH_Rx_Mode */
<> 144:ef7eb2e8f9f7 408
<> 144:ef7eb2e8f9f7 409 uint32_t ChecksumMode; /*!< Selects if the checksum is check by hardware or by software.
<> 144:ef7eb2e8f9f7 410 This parameter can be a value of @ref ETH_Checksum_Mode */
<> 144:ef7eb2e8f9f7 411
AnnaBridge 165:e614a9f1c9e2 412 uint32_t MediaInterface; /*!< Selects the media-independent interface or the reduced media-independent interface.
<> 144:ef7eb2e8f9f7 413 This parameter can be a value of @ref ETH_Media_Interface */
<> 144:ef7eb2e8f9f7 414
<> 144:ef7eb2e8f9f7 415 } ETH_InitTypeDef;
<> 144:ef7eb2e8f9f7 416
<> 144:ef7eb2e8f9f7 417
<> 144:ef7eb2e8f9f7 418 /**
<> 144:ef7eb2e8f9f7 419 * @brief ETH MAC Configuration Structure definition
<> 144:ef7eb2e8f9f7 420 */
<> 144:ef7eb2e8f9f7 421
<> 144:ef7eb2e8f9f7 422 typedef struct
<> 144:ef7eb2e8f9f7 423 {
<> 144:ef7eb2e8f9f7 424 uint32_t Watchdog; /*!< Selects or not the Watchdog timer
<> 144:ef7eb2e8f9f7 425 When enabled, the MAC allows no more then 2048 bytes to be received.
<> 144:ef7eb2e8f9f7 426 When disabled, the MAC can receive up to 16384 bytes.
<> 144:ef7eb2e8f9f7 427 This parameter can be a value of @ref ETH_Watchdog */
<> 144:ef7eb2e8f9f7 428
<> 144:ef7eb2e8f9f7 429 uint32_t Jabber; /*!< Selects or not Jabber timer
<> 144:ef7eb2e8f9f7 430 When enabled, the MAC allows no more then 2048 bytes to be sent.
<> 144:ef7eb2e8f9f7 431 When disabled, the MAC can send up to 16384 bytes.
<> 144:ef7eb2e8f9f7 432 This parameter can be a value of @ref ETH_Jabber */
<> 144:ef7eb2e8f9f7 433
<> 144:ef7eb2e8f9f7 434 uint32_t InterFrameGap; /*!< Selects the minimum IFG between frames during transmission.
<> 144:ef7eb2e8f9f7 435 This parameter can be a value of @ref ETH_Inter_Frame_Gap */
<> 144:ef7eb2e8f9f7 436
<> 144:ef7eb2e8f9f7 437 uint32_t CarrierSense; /*!< Selects or not the Carrier Sense.
<> 144:ef7eb2e8f9f7 438 This parameter can be a value of @ref ETH_Carrier_Sense */
<> 144:ef7eb2e8f9f7 439
<> 144:ef7eb2e8f9f7 440 uint32_t ReceiveOwn; /*!< Selects or not the ReceiveOwn,
<> 144:ef7eb2e8f9f7 441 ReceiveOwn allows the reception of frames when the TX_EN signal is asserted
<> 144:ef7eb2e8f9f7 442 in Half-Duplex mode.
<> 144:ef7eb2e8f9f7 443 This parameter can be a value of @ref ETH_Receive_Own */
<> 144:ef7eb2e8f9f7 444
<> 144:ef7eb2e8f9f7 445 uint32_t LoopbackMode; /*!< Selects or not the internal MAC MII Loopback mode.
<> 144:ef7eb2e8f9f7 446 This parameter can be a value of @ref ETH_Loop_Back_Mode */
<> 144:ef7eb2e8f9f7 447
<> 144:ef7eb2e8f9f7 448 uint32_t ChecksumOffload; /*!< Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers.
<> 144:ef7eb2e8f9f7 449 This parameter can be a value of @ref ETH_Checksum_Offload */
<> 144:ef7eb2e8f9f7 450
<> 144:ef7eb2e8f9f7 451 uint32_t RetryTransmission; /*!< Selects or not the MAC attempt retries transmission, based on the settings of BL,
<> 144:ef7eb2e8f9f7 452 when a collision occurs (Half-Duplex mode).
<> 144:ef7eb2e8f9f7 453 This parameter can be a value of @ref ETH_Retry_Transmission */
<> 144:ef7eb2e8f9f7 454
<> 144:ef7eb2e8f9f7 455 uint32_t AutomaticPadCRCStrip; /*!< Selects or not the Automatic MAC Pad/CRC Stripping.
<> 144:ef7eb2e8f9f7 456 This parameter can be a value of @ref ETH_Automatic_Pad_CRC_Strip */
<> 144:ef7eb2e8f9f7 457
<> 144:ef7eb2e8f9f7 458 uint32_t BackOffLimit; /*!< Selects the BackOff limit value.
<> 144:ef7eb2e8f9f7 459 This parameter can be a value of @ref ETH_Back_Off_Limit */
<> 144:ef7eb2e8f9f7 460
<> 144:ef7eb2e8f9f7 461 uint32_t DeferralCheck; /*!< Selects or not the deferral check function (Half-Duplex mode).
<> 144:ef7eb2e8f9f7 462 This parameter can be a value of @ref ETH_Deferral_Check */
<> 144:ef7eb2e8f9f7 463
<> 144:ef7eb2e8f9f7 464 uint32_t ReceiveAll; /*!< Selects or not all frames reception by the MAC (No filtering).
<> 144:ef7eb2e8f9f7 465 This parameter can be a value of @ref ETH_Receive_All */
<> 144:ef7eb2e8f9f7 466
AnnaBridge 165:e614a9f1c9e2 467 uint32_t SourceAddrFilter; /*!< Selects the Source Address Filter mode.
AnnaBridge 165:e614a9f1c9e2 468 This parameter can be a value of @ref ETH_Source_Addr_Filter */
<> 144:ef7eb2e8f9f7 469
AnnaBridge 165:e614a9f1c9e2 470 uint32_t PassControlFrames; /*!< Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames)
<> 144:ef7eb2e8f9f7 471 This parameter can be a value of @ref ETH_Pass_Control_Frames */
<> 144:ef7eb2e8f9f7 472
<> 144:ef7eb2e8f9f7 473 uint32_t BroadcastFramesReception; /*!< Selects or not the reception of Broadcast Frames.
<> 144:ef7eb2e8f9f7 474 This parameter can be a value of @ref ETH_Broadcast_Frames_Reception */
<> 144:ef7eb2e8f9f7 475
<> 144:ef7eb2e8f9f7 476 uint32_t DestinationAddrFilter; /*!< Sets the destination filter mode for both unicast and multicast frames.
<> 144:ef7eb2e8f9f7 477 This parameter can be a value of @ref ETH_Destination_Addr_Filter */
<> 144:ef7eb2e8f9f7 478
<> 144:ef7eb2e8f9f7 479 uint32_t PromiscuousMode; /*!< Selects or not the Promiscuous Mode
<> 144:ef7eb2e8f9f7 480 This parameter can be a value of @ref ETH_Promiscuous_Mode */
<> 144:ef7eb2e8f9f7 481
<> 144:ef7eb2e8f9f7 482 uint32_t MulticastFramesFilter; /*!< Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter.
<> 144:ef7eb2e8f9f7 483 This parameter can be a value of @ref ETH_Multicast_Frames_Filter */
<> 144:ef7eb2e8f9f7 484
<> 144:ef7eb2e8f9f7 485 uint32_t UnicastFramesFilter; /*!< Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter.
<> 144:ef7eb2e8f9f7 486 This parameter can be a value of @ref ETH_Unicast_Frames_Filter */
<> 144:ef7eb2e8f9f7 487
<> 144:ef7eb2e8f9f7 488 uint32_t HashTableHigh; /*!< This field holds the higher 32 bits of Hash table.
AnnaBridge 165:e614a9f1c9e2 489 This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFFU */
<> 144:ef7eb2e8f9f7 490
<> 144:ef7eb2e8f9f7 491 uint32_t HashTableLow; /*!< This field holds the lower 32 bits of Hash table.
AnnaBridge 165:e614a9f1c9e2 492 This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFFU */
<> 144:ef7eb2e8f9f7 493
<> 144:ef7eb2e8f9f7 494 uint32_t PauseTime; /*!< This field holds the value to be used in the Pause Time field in the transmit control frame.
AnnaBridge 165:e614a9f1c9e2 495 This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFU */
<> 144:ef7eb2e8f9f7 496
<> 144:ef7eb2e8f9f7 497 uint32_t ZeroQuantaPause; /*!< Selects or not the automatic generation of Zero-Quanta Pause Control frames.
<> 144:ef7eb2e8f9f7 498 This parameter can be a value of @ref ETH_Zero_Quanta_Pause */
<> 144:ef7eb2e8f9f7 499
<> 144:ef7eb2e8f9f7 500 uint32_t PauseLowThreshold; /*!< This field configures the threshold of the PAUSE to be checked for
<> 144:ef7eb2e8f9f7 501 automatic retransmission of PAUSE Frame.
<> 144:ef7eb2e8f9f7 502 This parameter can be a value of @ref ETH_Pause_Low_Threshold */
AnnaBridge 165:e614a9f1c9e2 503
<> 144:ef7eb2e8f9f7 504 uint32_t UnicastPauseFrameDetect; /*!< Selects or not the MAC detection of the Pause frames (with MAC Address0
<> 144:ef7eb2e8f9f7 505 unicast address and unique multicast address).
<> 144:ef7eb2e8f9f7 506 This parameter can be a value of @ref ETH_Unicast_Pause_Frame_Detect */
<> 144:ef7eb2e8f9f7 507
<> 144:ef7eb2e8f9f7 508 uint32_t ReceiveFlowControl; /*!< Enables or disables the MAC to decode the received Pause frame and
<> 144:ef7eb2e8f9f7 509 disable its transmitter for a specified time (Pause Time)
<> 144:ef7eb2e8f9f7 510 This parameter can be a value of @ref ETH_Receive_Flow_Control */
<> 144:ef7eb2e8f9f7 511
<> 144:ef7eb2e8f9f7 512 uint32_t TransmitFlowControl; /*!< Enables or disables the MAC to transmit Pause frames (Full-Duplex mode)
<> 144:ef7eb2e8f9f7 513 or the MAC back-pressure operation (Half-Duplex mode)
<> 144:ef7eb2e8f9f7 514 This parameter can be a value of @ref ETH_Transmit_Flow_Control */
<> 144:ef7eb2e8f9f7 515
<> 144:ef7eb2e8f9f7 516 uint32_t VLANTagComparison; /*!< Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for
<> 144:ef7eb2e8f9f7 517 comparison and filtering.
<> 144:ef7eb2e8f9f7 518 This parameter can be a value of @ref ETH_VLAN_Tag_Comparison */
<> 144:ef7eb2e8f9f7 519
<> 144:ef7eb2e8f9f7 520 uint32_t VLANTagIdentifier; /*!< Holds the VLAN tag identifier for receive frames */
<> 144:ef7eb2e8f9f7 521
<> 144:ef7eb2e8f9f7 522 } ETH_MACInitTypeDef;
<> 144:ef7eb2e8f9f7 523
<> 144:ef7eb2e8f9f7 524 /**
<> 144:ef7eb2e8f9f7 525 * @brief ETH DMA Configuration Structure definition
<> 144:ef7eb2e8f9f7 526 */
<> 144:ef7eb2e8f9f7 527
<> 144:ef7eb2e8f9f7 528 typedef struct
<> 144:ef7eb2e8f9f7 529 {
<> 144:ef7eb2e8f9f7 530 uint32_t DropTCPIPChecksumErrorFrame; /*!< Selects or not the Dropping of TCP/IP Checksum Error Frames.
<> 144:ef7eb2e8f9f7 531 This parameter can be a value of @ref ETH_Drop_TCP_IP_Checksum_Error_Frame */
<> 144:ef7eb2e8f9f7 532
<> 144:ef7eb2e8f9f7 533 uint32_t ReceiveStoreForward; /*!< Enables or disables the Receive store and forward mode.
<> 144:ef7eb2e8f9f7 534 This parameter can be a value of @ref ETH_Receive_Store_Forward */
<> 144:ef7eb2e8f9f7 535
<> 144:ef7eb2e8f9f7 536 uint32_t FlushReceivedFrame; /*!< Enables or disables the flushing of received frames.
<> 144:ef7eb2e8f9f7 537 This parameter can be a value of @ref ETH_Flush_Received_Frame */
<> 144:ef7eb2e8f9f7 538
<> 144:ef7eb2e8f9f7 539 uint32_t TransmitStoreForward; /*!< Enables or disables Transmit store and forward mode.
<> 144:ef7eb2e8f9f7 540 This parameter can be a value of @ref ETH_Transmit_Store_Forward */
<> 144:ef7eb2e8f9f7 541
<> 144:ef7eb2e8f9f7 542 uint32_t TransmitThresholdControl; /*!< Selects or not the Transmit Threshold Control.
<> 144:ef7eb2e8f9f7 543 This parameter can be a value of @ref ETH_Transmit_Threshold_Control */
<> 144:ef7eb2e8f9f7 544
<> 144:ef7eb2e8f9f7 545 uint32_t ForwardErrorFrames; /*!< Selects or not the forward to the DMA of erroneous frames.
<> 144:ef7eb2e8f9f7 546 This parameter can be a value of @ref ETH_Forward_Error_Frames */
<> 144:ef7eb2e8f9f7 547
<> 144:ef7eb2e8f9f7 548 uint32_t ForwardUndersizedGoodFrames; /*!< Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error
<> 144:ef7eb2e8f9f7 549 and length less than 64 bytes) including pad-bytes and CRC)
<> 144:ef7eb2e8f9f7 550 This parameter can be a value of @ref ETH_Forward_Undersized_Good_Frames */
<> 144:ef7eb2e8f9f7 551
<> 144:ef7eb2e8f9f7 552 uint32_t ReceiveThresholdControl; /*!< Selects the threshold level of the Receive FIFO.
<> 144:ef7eb2e8f9f7 553 This parameter can be a value of @ref ETH_Receive_Threshold_Control */
<> 144:ef7eb2e8f9f7 554
<> 144:ef7eb2e8f9f7 555 uint32_t SecondFrameOperate; /*!< Selects or not the Operate on second frame mode, which allows the DMA to process a second
<> 144:ef7eb2e8f9f7 556 frame of Transmit data even before obtaining the status for the first frame.
<> 144:ef7eb2e8f9f7 557 This parameter can be a value of @ref ETH_Second_Frame_Operate */
<> 144:ef7eb2e8f9f7 558
<> 144:ef7eb2e8f9f7 559 uint32_t AddressAlignedBeats; /*!< Enables or disables the Address Aligned Beats.
<> 144:ef7eb2e8f9f7 560 This parameter can be a value of @ref ETH_Address_Aligned_Beats */
<> 144:ef7eb2e8f9f7 561
<> 144:ef7eb2e8f9f7 562 uint32_t FixedBurst; /*!< Enables or disables the AHB Master interface fixed burst transfers.
<> 144:ef7eb2e8f9f7 563 This parameter can be a value of @ref ETH_Fixed_Burst */
AnnaBridge 165:e614a9f1c9e2 564
<> 144:ef7eb2e8f9f7 565 uint32_t RxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction.
<> 144:ef7eb2e8f9f7 566 This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */
<> 144:ef7eb2e8f9f7 567
<> 144:ef7eb2e8f9f7 568 uint32_t TxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Tx DMA transaction.
<> 144:ef7eb2e8f9f7 569 This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */
<> 144:ef7eb2e8f9f7 570
<> 144:ef7eb2e8f9f7 571 uint32_t DescriptorSkipLength; /*!< Specifies the number of word to skip between two unchained descriptors (Ring mode)
AnnaBridge 165:e614a9f1c9e2 572 This parameter must be a number between Min_Data = 0 and Max_Data = 32 */
<> 144:ef7eb2e8f9f7 573
<> 144:ef7eb2e8f9f7 574 uint32_t DMAArbitration; /*!< Selects the DMA Tx/Rx arbitration.
<> 144:ef7eb2e8f9f7 575 This parameter can be a value of @ref ETH_DMA_Arbitration */
<> 144:ef7eb2e8f9f7 576 } ETH_DMAInitTypeDef;
<> 144:ef7eb2e8f9f7 577
<> 144:ef7eb2e8f9f7 578
<> 144:ef7eb2e8f9f7 579 /**
<> 144:ef7eb2e8f9f7 580 * @brief ETH DMA Descriptors data structure definition
<> 144:ef7eb2e8f9f7 581 */
<> 144:ef7eb2e8f9f7 582
<> 144:ef7eb2e8f9f7 583 typedef struct
<> 144:ef7eb2e8f9f7 584 {
<> 144:ef7eb2e8f9f7 585 __IO uint32_t Status; /*!< Status */
<> 144:ef7eb2e8f9f7 586
<> 144:ef7eb2e8f9f7 587 uint32_t ControlBufferSize; /*!< Control and Buffer1, Buffer2 lengths */
<> 144:ef7eb2e8f9f7 588
<> 144:ef7eb2e8f9f7 589 uint32_t Buffer1Addr; /*!< Buffer1 address pointer */
<> 144:ef7eb2e8f9f7 590
<> 144:ef7eb2e8f9f7 591 uint32_t Buffer2NextDescAddr; /*!< Buffer2 or next descriptor address pointer */
<> 144:ef7eb2e8f9f7 592
<> 144:ef7eb2e8f9f7 593 } ETH_DMADescTypeDef;
<> 144:ef7eb2e8f9f7 594
<> 144:ef7eb2e8f9f7 595 /**
<> 144:ef7eb2e8f9f7 596 * @brief Received Frame Informations structure definition
<> 144:ef7eb2e8f9f7 597 */
<> 144:ef7eb2e8f9f7 598 typedef struct
<> 144:ef7eb2e8f9f7 599 {
<> 144:ef7eb2e8f9f7 600 ETH_DMADescTypeDef *FSRxDesc; /*!< First Segment Rx Desc */
<> 144:ef7eb2e8f9f7 601
<> 144:ef7eb2e8f9f7 602 ETH_DMADescTypeDef *LSRxDesc; /*!< Last Segment Rx Desc */
<> 144:ef7eb2e8f9f7 603
<> 144:ef7eb2e8f9f7 604 uint32_t SegCount; /*!< Segment count */
<> 144:ef7eb2e8f9f7 605
<> 144:ef7eb2e8f9f7 606 uint32_t length; /*!< Frame length */
<> 144:ef7eb2e8f9f7 607
<> 144:ef7eb2e8f9f7 608 uint32_t buffer; /*!< Frame buffer */
<> 144:ef7eb2e8f9f7 609
<> 144:ef7eb2e8f9f7 610 } ETH_DMARxFrameInfos;
<> 144:ef7eb2e8f9f7 611
<> 144:ef7eb2e8f9f7 612 /**
<> 144:ef7eb2e8f9f7 613 * @brief ETH Handle Structure definition
<> 144:ef7eb2e8f9f7 614 */
<> 144:ef7eb2e8f9f7 615
<> 144:ef7eb2e8f9f7 616 typedef struct
<> 144:ef7eb2e8f9f7 617 {
<> 144:ef7eb2e8f9f7 618 ETH_TypeDef *Instance; /*!< Register base address */
<> 144:ef7eb2e8f9f7 619
<> 144:ef7eb2e8f9f7 620 ETH_InitTypeDef Init; /*!< Ethernet Init Configuration */
<> 144:ef7eb2e8f9f7 621
<> 144:ef7eb2e8f9f7 622 uint32_t LinkStatus; /*!< Ethernet link status */
<> 144:ef7eb2e8f9f7 623
<> 144:ef7eb2e8f9f7 624 ETH_DMADescTypeDef *RxDesc; /*!< Rx descriptor to Get */
<> 144:ef7eb2e8f9f7 625
<> 144:ef7eb2e8f9f7 626 ETH_DMADescTypeDef *TxDesc; /*!< Tx descriptor to Set */
<> 144:ef7eb2e8f9f7 627
<> 144:ef7eb2e8f9f7 628 ETH_DMARxFrameInfos RxFrameInfos; /*!< last Rx frame infos */
<> 144:ef7eb2e8f9f7 629
<> 144:ef7eb2e8f9f7 630 __IO HAL_ETH_StateTypeDef State; /*!< ETH communication state */
<> 144:ef7eb2e8f9f7 631
<> 144:ef7eb2e8f9f7 632 HAL_LockTypeDef Lock; /*!< ETH Lock */
<> 144:ef7eb2e8f9f7 633
<> 144:ef7eb2e8f9f7 634 } ETH_HandleTypeDef;
<> 144:ef7eb2e8f9f7 635
<> 144:ef7eb2e8f9f7 636 /**
<> 144:ef7eb2e8f9f7 637 * @}
<> 144:ef7eb2e8f9f7 638 */
<> 144:ef7eb2e8f9f7 639
<> 144:ef7eb2e8f9f7 640 /* Exported constants --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 641 /** @defgroup ETH_Exported_Constants ETH Exported Constants
<> 144:ef7eb2e8f9f7 642 * @{
<> 144:ef7eb2e8f9f7 643 */
<> 144:ef7eb2e8f9f7 644
<> 144:ef7eb2e8f9f7 645 /** @defgroup ETH_Buffers_setting ETH Buffers setting
<> 144:ef7eb2e8f9f7 646 * @{
<> 144:ef7eb2e8f9f7 647 */
AnnaBridge 165:e614a9f1c9e2 648 #define ETH_MAX_PACKET_SIZE 1524U /*!< ETH_HEADER + ETH_EXTRA + ETH_VLAN_TAG + ETH_MAX_ETH_PAYLOAD + ETH_CRC */
AnnaBridge 165:e614a9f1c9e2 649 #define ETH_HEADER 14U /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */
AnnaBridge 165:e614a9f1c9e2 650 #define ETH_CRC 4U /*!< Ethernet CRC */
AnnaBridge 165:e614a9f1c9e2 651 #define ETH_EXTRA 2U /*!< Extra bytes in some cases */
AnnaBridge 165:e614a9f1c9e2 652 #define ETH_VLAN_TAG 4U /*!< optional 802.1q VLAN Tag */
AnnaBridge 165:e614a9f1c9e2 653 #define ETH_MIN_ETH_PAYLOAD 46U /*!< Minimum Ethernet payload size */
AnnaBridge 165:e614a9f1c9e2 654 #define ETH_MAX_ETH_PAYLOAD 1500U /*!< Maximum Ethernet payload size */
AnnaBridge 165:e614a9f1c9e2 655 #define ETH_JUMBO_FRAME_PAYLOAD 9000U /*!< Jumbo frame payload size */
<> 144:ef7eb2e8f9f7 656
<> 144:ef7eb2e8f9f7 657 /* Ethernet driver receive buffers are organized in a chained linked-list, when
<> 144:ef7eb2e8f9f7 658 an ethernet packet is received, the Rx-DMA will transfer the packet from RxFIFO
<> 144:ef7eb2e8f9f7 659 to the driver receive buffers memory.
<> 144:ef7eb2e8f9f7 660
<> 144:ef7eb2e8f9f7 661 Depending on the size of the received ethernet packet and the size of
<> 144:ef7eb2e8f9f7 662 each ethernet driver receive buffer, the received packet can take one or more
<> 144:ef7eb2e8f9f7 663 ethernet driver receive buffer.
<> 144:ef7eb2e8f9f7 664
<> 144:ef7eb2e8f9f7 665 In below are defined the size of one ethernet driver receive buffer ETH_RX_BUF_SIZE
<> 144:ef7eb2e8f9f7 666 and the total count of the driver receive buffers ETH_RXBUFNB.
<> 144:ef7eb2e8f9f7 667
<> 144:ef7eb2e8f9f7 668 The configured value for ETH_RX_BUF_SIZE and ETH_RXBUFNB are only provided as
<> 144:ef7eb2e8f9f7 669 example, they can be reconfigured in the application layer to fit the application
<> 144:ef7eb2e8f9f7 670 needs */
<> 144:ef7eb2e8f9f7 671
<> 144:ef7eb2e8f9f7 672 /* Here we configure each Ethernet driver receive buffer to fit the Max size Ethernet
<> 144:ef7eb2e8f9f7 673 packet */
<> 144:ef7eb2e8f9f7 674 #ifndef ETH_RX_BUF_SIZE
<> 144:ef7eb2e8f9f7 675 #define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE
<> 144:ef7eb2e8f9f7 676 #endif
<> 144:ef7eb2e8f9f7 677
<> 144:ef7eb2e8f9f7 678 /* 5 Ethernet driver receive buffers are used (in a chained linked list)*/
<> 144:ef7eb2e8f9f7 679 #ifndef ETH_RXBUFNB
AnnaBridge 165:e614a9f1c9e2 680 #define ETH_RXBUFNB 5U /* 5 Rx buffers of size ETH_RX_BUF_SIZE */
<> 144:ef7eb2e8f9f7 681 #endif
<> 144:ef7eb2e8f9f7 682
<> 144:ef7eb2e8f9f7 683
<> 144:ef7eb2e8f9f7 684 /* Ethernet driver transmit buffers are organized in a chained linked-list, when
<> 144:ef7eb2e8f9f7 685 an ethernet packet is transmitted, Tx-DMA will transfer the packet from the
<> 144:ef7eb2e8f9f7 686 driver transmit buffers memory to the TxFIFO.
<> 144:ef7eb2e8f9f7 687
<> 144:ef7eb2e8f9f7 688 Depending on the size of the Ethernet packet to be transmitted and the size of
<> 144:ef7eb2e8f9f7 689 each ethernet driver transmit buffer, the packet to be transmitted can take
<> 144:ef7eb2e8f9f7 690 one or more ethernet driver transmit buffer.
<> 144:ef7eb2e8f9f7 691
<> 144:ef7eb2e8f9f7 692 In below are defined the size of one ethernet driver transmit buffer ETH_TX_BUF_SIZE
<> 144:ef7eb2e8f9f7 693 and the total count of the driver transmit buffers ETH_TXBUFNB.
<> 144:ef7eb2e8f9f7 694
<> 144:ef7eb2e8f9f7 695 The configured value for ETH_TX_BUF_SIZE and ETH_TXBUFNB are only provided as
<> 144:ef7eb2e8f9f7 696 example, they can be reconfigured in the application layer to fit the application
<> 144:ef7eb2e8f9f7 697 needs */
<> 144:ef7eb2e8f9f7 698
<> 144:ef7eb2e8f9f7 699 /* Here we configure each Ethernet driver transmit buffer to fit the Max size Ethernet
<> 144:ef7eb2e8f9f7 700 packet */
<> 144:ef7eb2e8f9f7 701 #ifndef ETH_TX_BUF_SIZE
<> 144:ef7eb2e8f9f7 702 #define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE
<> 144:ef7eb2e8f9f7 703 #endif
<> 144:ef7eb2e8f9f7 704
<> 144:ef7eb2e8f9f7 705 /* 5 ethernet driver transmit buffers are used (in a chained linked list)*/
<> 144:ef7eb2e8f9f7 706 #ifndef ETH_TXBUFNB
AnnaBridge 165:e614a9f1c9e2 707 #define ETH_TXBUFNB 5U /* 5 Tx buffers of size ETH_TX_BUF_SIZE */
<> 144:ef7eb2e8f9f7 708 #endif
<> 144:ef7eb2e8f9f7 709
<> 144:ef7eb2e8f9f7 710 /**
<> 144:ef7eb2e8f9f7 711 * @}
<> 144:ef7eb2e8f9f7 712 */
<> 144:ef7eb2e8f9f7 713
<> 144:ef7eb2e8f9f7 714 /** @defgroup ETH_DMA_TX_Descriptor ETH DMA TX Descriptor
<> 144:ef7eb2e8f9f7 715 * @{
<> 144:ef7eb2e8f9f7 716 */
<> 144:ef7eb2e8f9f7 717
<> 144:ef7eb2e8f9f7 718 /*
AnnaBridge 165:e614a9f1c9e2 719 DMA Tx Descriptor
<> 144:ef7eb2e8f9f7 720 -----------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 721 TDES0 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] |
<> 144:ef7eb2e8f9f7 722 -----------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 723 TDES1 | Reserved[31:29] | Buffer2 ByteCount[28:16] | Reserved[15:13] | Buffer1 ByteCount[12:0] |
<> 144:ef7eb2e8f9f7 724 -----------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 725 TDES2 | Buffer1 Address [31:0] |
<> 144:ef7eb2e8f9f7 726 -----------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 727 TDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] |
<> 144:ef7eb2e8f9f7 728 -----------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 729 */
<> 144:ef7eb2e8f9f7 730
<> 144:ef7eb2e8f9f7 731 /**
<> 144:ef7eb2e8f9f7 732 * @brief Bit definition of TDES0 register: DMA Tx descriptor status register
<> 144:ef7eb2e8f9f7 733 */
AnnaBridge 165:e614a9f1c9e2 734 #define ETH_DMATXDESC_OWN 0x80000000U /*!< OWN bit: descriptor is owned by DMA engine */
AnnaBridge 165:e614a9f1c9e2 735 #define ETH_DMATXDESC_IC 0x40000000U /*!< Interrupt on Completion */
AnnaBridge 165:e614a9f1c9e2 736 #define ETH_DMATXDESC_LS 0x20000000U /*!< Last Segment */
AnnaBridge 165:e614a9f1c9e2 737 #define ETH_DMATXDESC_FS 0x10000000U /*!< First Segment */
AnnaBridge 165:e614a9f1c9e2 738 #define ETH_DMATXDESC_DC 0x08000000U /*!< Disable CRC */
AnnaBridge 165:e614a9f1c9e2 739 #define ETH_DMATXDESC_DP 0x04000000U /*!< Disable Padding */
AnnaBridge 165:e614a9f1c9e2 740 #define ETH_DMATXDESC_TTSE 0x02000000U /*!< Transmit Time Stamp Enable */
AnnaBridge 165:e614a9f1c9e2 741 #define ETH_DMATXDESC_CIC 0x00C00000U /*!< Checksum Insertion Control: 4 cases */
AnnaBridge 165:e614a9f1c9e2 742 #define ETH_DMATXDESC_CIC_BYPASS 0x00000000U /*!< Do Nothing: Checksum Engine is bypassed */
AnnaBridge 165:e614a9f1c9e2 743 #define ETH_DMATXDESC_CIC_IPV4HEADER 0x00400000U /*!< IPV4 header Checksum Insertion */
AnnaBridge 165:e614a9f1c9e2 744 #define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT 0x00800000U /*!< TCP/UDP/ICMP Checksum Insertion calculated over segment only */
AnnaBridge 165:e614a9f1c9e2 745 #define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL 0x00C00000U /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */
AnnaBridge 165:e614a9f1c9e2 746 #define ETH_DMATXDESC_TER 0x00200000U /*!< Transmit End of Ring */
AnnaBridge 165:e614a9f1c9e2 747 #define ETH_DMATXDESC_TCH 0x00100000U /*!< Second Address Chained */
AnnaBridge 165:e614a9f1c9e2 748 #define ETH_DMATXDESC_TTSS 0x00020000U /*!< Tx Time Stamp Status */
AnnaBridge 165:e614a9f1c9e2 749 #define ETH_DMATXDESC_IHE 0x00010000U /*!< IP Header Error */
AnnaBridge 165:e614a9f1c9e2 750 #define ETH_DMATXDESC_ES 0x00008000U /*!< Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT */
AnnaBridge 165:e614a9f1c9e2 751 #define ETH_DMATXDESC_JT 0x00004000U /*!< Jabber Timeout */
AnnaBridge 165:e614a9f1c9e2 752 #define ETH_DMATXDESC_FF 0x00002000U /*!< Frame Flushed: DMA/MTL flushed the frame due to SW flush */
AnnaBridge 165:e614a9f1c9e2 753 #define ETH_DMATXDESC_PCE 0x00001000U /*!< Payload Checksum Error */
AnnaBridge 165:e614a9f1c9e2 754 #define ETH_DMATXDESC_LCA 0x00000800U /*!< Loss of Carrier: carrier lost during transmission */
AnnaBridge 165:e614a9f1c9e2 755 #define ETH_DMATXDESC_NC 0x00000400U /*!< No Carrier: no carrier signal from the transceiver */
AnnaBridge 165:e614a9f1c9e2 756 #define ETH_DMATXDESC_LCO 0x00000200U /*!< Late Collision: transmission aborted due to collision */
AnnaBridge 165:e614a9f1c9e2 757 #define ETH_DMATXDESC_EC 0x00000100U /*!< Excessive Collision: transmission aborted after 16 collisions */
AnnaBridge 165:e614a9f1c9e2 758 #define ETH_DMATXDESC_VF 0x00000080U /*!< VLAN Frame */
AnnaBridge 165:e614a9f1c9e2 759 #define ETH_DMATXDESC_CC 0x00000078U /*!< Collision Count */
AnnaBridge 165:e614a9f1c9e2 760 #define ETH_DMATXDESC_ED 0x00000004U /*!< Excessive Deferral */
AnnaBridge 165:e614a9f1c9e2 761 #define ETH_DMATXDESC_UF 0x00000002U /*!< Underflow Error: late data arrival from the memory */
AnnaBridge 165:e614a9f1c9e2 762 #define ETH_DMATXDESC_DB 0x00000001U /*!< Deferred Bit */
<> 144:ef7eb2e8f9f7 763
<> 144:ef7eb2e8f9f7 764 /**
<> 144:ef7eb2e8f9f7 765 * @brief Bit definition of TDES1 register
<> 144:ef7eb2e8f9f7 766 */
AnnaBridge 165:e614a9f1c9e2 767 #define ETH_DMATXDESC_TBS2 0x1FFF0000U /*!< Transmit Buffer2 Size */
AnnaBridge 165:e614a9f1c9e2 768 #define ETH_DMATXDESC_TBS1 0x00001FFFU /*!< Transmit Buffer1 Size */
<> 144:ef7eb2e8f9f7 769
<> 144:ef7eb2e8f9f7 770 /**
<> 144:ef7eb2e8f9f7 771 * @brief Bit definition of TDES2 register
<> 144:ef7eb2e8f9f7 772 */
AnnaBridge 165:e614a9f1c9e2 773 #define ETH_DMATXDESC_B1AP 0xFFFFFFFFU /*!< Buffer1 Address Pointer */
<> 144:ef7eb2e8f9f7 774
<> 144:ef7eb2e8f9f7 775 /**
<> 144:ef7eb2e8f9f7 776 * @brief Bit definition of TDES3 register
<> 144:ef7eb2e8f9f7 777 */
AnnaBridge 165:e614a9f1c9e2 778 #define ETH_DMATXDESC_B2AP 0xFFFFFFFFU /*!< Buffer2 Address Pointer */
<> 144:ef7eb2e8f9f7 779
<> 144:ef7eb2e8f9f7 780 /**
<> 144:ef7eb2e8f9f7 781 * @}
<> 144:ef7eb2e8f9f7 782 */
AnnaBridge 165:e614a9f1c9e2 783 /** @defgroup ETH_DMA_RX_Descriptor ETH DMA RX Descriptor
<> 144:ef7eb2e8f9f7 784 * @{
<> 144:ef7eb2e8f9f7 785 */
<> 144:ef7eb2e8f9f7 786
<> 144:ef7eb2e8f9f7 787 /*
<> 144:ef7eb2e8f9f7 788 DMA Rx Descriptor
<> 144:ef7eb2e8f9f7 789 --------------------------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 790 RDES0 | OWN(31) | Status [30:0] |
<> 144:ef7eb2e8f9f7 791 ---------------------------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 792 RDES1 | CTRL(31) | Reserved[30:29] | Buffer2 ByteCount[28:16] | CTRL[15:14] | Reserved(13) | Buffer1 ByteCount[12:0] |
<> 144:ef7eb2e8f9f7 793 ---------------------------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 794 RDES2 | Buffer1 Address [31:0] |
<> 144:ef7eb2e8f9f7 795 ---------------------------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 796 RDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] |
<> 144:ef7eb2e8f9f7 797 ---------------------------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 798 */
<> 144:ef7eb2e8f9f7 799
<> 144:ef7eb2e8f9f7 800 /**
<> 144:ef7eb2e8f9f7 801 * @brief Bit definition of RDES0 register: DMA Rx descriptor status register
<> 144:ef7eb2e8f9f7 802 */
AnnaBridge 165:e614a9f1c9e2 803 #define ETH_DMARXDESC_OWN 0x80000000U /*!< OWN bit: descriptor is owned by DMA engine */
AnnaBridge 165:e614a9f1c9e2 804 #define ETH_DMARXDESC_AFM 0x40000000U /*!< DA Filter Fail for the rx frame */
AnnaBridge 165:e614a9f1c9e2 805 #define ETH_DMARXDESC_FL 0x3FFF0000U /*!< Receive descriptor frame length */
AnnaBridge 165:e614a9f1c9e2 806 #define ETH_DMARXDESC_ES 0x00008000U /*!< Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */
AnnaBridge 165:e614a9f1c9e2 807 #define ETH_DMARXDESC_DE 0x00004000U /*!< Descriptor error: no more descriptors for receive frame */
AnnaBridge 165:e614a9f1c9e2 808 #define ETH_DMARXDESC_SAF 0x00002000U /*!< SA Filter Fail for the received frame */
AnnaBridge 165:e614a9f1c9e2 809 #define ETH_DMARXDESC_LE 0x00001000U /*!< Frame size not matching with length field */
AnnaBridge 165:e614a9f1c9e2 810 #define ETH_DMARXDESC_OE 0x00000800U /*!< Overflow Error: Frame was damaged due to buffer overflow */
AnnaBridge 165:e614a9f1c9e2 811 #define ETH_DMARXDESC_VLAN 0x00000400U /*!< VLAN Tag: received frame is a VLAN frame */
AnnaBridge 165:e614a9f1c9e2 812 #define ETH_DMARXDESC_FS 0x00000200U /*!< First descriptor of the frame */
AnnaBridge 165:e614a9f1c9e2 813 #define ETH_DMARXDESC_LS 0x00000100U /*!< Last descriptor of the frame */
AnnaBridge 165:e614a9f1c9e2 814 #define ETH_DMARXDESC_IPV4HCE 0x00000080U /*!< IPC Checksum Error: Rx Ipv4 header checksum error */
AnnaBridge 165:e614a9f1c9e2 815 #define ETH_DMARXDESC_LC 0x00000040U /*!< Late collision occurred during reception */
AnnaBridge 165:e614a9f1c9e2 816 #define ETH_DMARXDESC_FT 0x00000020U /*!< Frame type - Ethernet, otherwise 802.3 */
AnnaBridge 165:e614a9f1c9e2 817 #define ETH_DMARXDESC_RWT 0x00000010U /*!< Receive Watchdog Timeout: watchdog timer expired during reception */
AnnaBridge 165:e614a9f1c9e2 818 #define ETH_DMARXDESC_RE 0x00000008U /*!< Receive error: error reported by MII interface */
AnnaBridge 165:e614a9f1c9e2 819 #define ETH_DMARXDESC_DBE 0x00000004U /*!< Dribble bit error: frame contains non int multiple of 8 bits */
AnnaBridge 165:e614a9f1c9e2 820 #define ETH_DMARXDESC_CE 0x00000002U /*!< CRC error */
AnnaBridge 165:e614a9f1c9e2 821 #define ETH_DMARXDESC_MAMPCE 0x00000001U /*!< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */
<> 144:ef7eb2e8f9f7 822
<> 144:ef7eb2e8f9f7 823 /**
<> 144:ef7eb2e8f9f7 824 * @brief Bit definition of RDES1 register
<> 144:ef7eb2e8f9f7 825 */
AnnaBridge 165:e614a9f1c9e2 826 #define ETH_DMARXDESC_DIC 0x80000000U /*!< Disable Interrupt on Completion */
AnnaBridge 165:e614a9f1c9e2 827 #define ETH_DMARXDESC_RBS2 0x1FFF0000U /*!< Receive Buffer2 Size */
AnnaBridge 165:e614a9f1c9e2 828 #define ETH_DMARXDESC_RER 0x00008000U /*!< Receive End of Ring */
AnnaBridge 165:e614a9f1c9e2 829 #define ETH_DMARXDESC_RCH 0x00004000U /*!< Second Address Chained */
AnnaBridge 165:e614a9f1c9e2 830 #define ETH_DMARXDESC_RBS1 0x00001FFFU /*!< Receive Buffer1 Size */
<> 144:ef7eb2e8f9f7 831
<> 144:ef7eb2e8f9f7 832 /**
<> 144:ef7eb2e8f9f7 833 * @brief Bit definition of RDES2 register
<> 144:ef7eb2e8f9f7 834 */
AnnaBridge 165:e614a9f1c9e2 835 #define ETH_DMARXDESC_B1AP 0xFFFFFFFFU /*!< Buffer1 Address Pointer */
<> 144:ef7eb2e8f9f7 836
<> 144:ef7eb2e8f9f7 837 /**
<> 144:ef7eb2e8f9f7 838 * @brief Bit definition of RDES3 register
<> 144:ef7eb2e8f9f7 839 */
AnnaBridge 165:e614a9f1c9e2 840 #define ETH_DMARXDESC_B2AP 0xFFFFFFFFU /*!< Buffer2 Address Pointer */
<> 144:ef7eb2e8f9f7 841
<> 144:ef7eb2e8f9f7 842 /**
<> 144:ef7eb2e8f9f7 843 * @}
<> 144:ef7eb2e8f9f7 844 */
<> 144:ef7eb2e8f9f7 845 /** @defgroup ETH_AutoNegotiation ETH AutoNegotiation
<> 144:ef7eb2e8f9f7 846 * @{
<> 144:ef7eb2e8f9f7 847 */
AnnaBridge 165:e614a9f1c9e2 848 #define ETH_AUTONEGOTIATION_ENABLE 0x00000001U
AnnaBridge 165:e614a9f1c9e2 849 #define ETH_AUTONEGOTIATION_DISABLE 0x00000000U
<> 144:ef7eb2e8f9f7 850
<> 144:ef7eb2e8f9f7 851 /**
<> 144:ef7eb2e8f9f7 852 * @}
<> 144:ef7eb2e8f9f7 853 */
<> 144:ef7eb2e8f9f7 854 /** @defgroup ETH_Speed ETH Speed
<> 144:ef7eb2e8f9f7 855 * @{
<> 144:ef7eb2e8f9f7 856 */
AnnaBridge 165:e614a9f1c9e2 857 #define ETH_SPEED_10M 0x00000000U
AnnaBridge 165:e614a9f1c9e2 858 #define ETH_SPEED_100M 0x00004000U
<> 144:ef7eb2e8f9f7 859
<> 144:ef7eb2e8f9f7 860 /**
<> 144:ef7eb2e8f9f7 861 * @}
<> 144:ef7eb2e8f9f7 862 */
AnnaBridge 165:e614a9f1c9e2 863 /** @defgroup ETH_Duplex_Mode ETH Duplex Mode
<> 144:ef7eb2e8f9f7 864 * @{
<> 144:ef7eb2e8f9f7 865 */
AnnaBridge 165:e614a9f1c9e2 866 #define ETH_MODE_FULLDUPLEX 0x00000800U
AnnaBridge 165:e614a9f1c9e2 867 #define ETH_MODE_HALFDUPLEX 0x00000000U
<> 144:ef7eb2e8f9f7 868 /**
<> 144:ef7eb2e8f9f7 869 * @}
<> 144:ef7eb2e8f9f7 870 */
AnnaBridge 165:e614a9f1c9e2 871 /** @defgroup ETH_Rx_Mode ETH Rx Mode
<> 144:ef7eb2e8f9f7 872 * @{
<> 144:ef7eb2e8f9f7 873 */
AnnaBridge 165:e614a9f1c9e2 874 #define ETH_RXPOLLING_MODE 0x00000000U
AnnaBridge 165:e614a9f1c9e2 875 #define ETH_RXINTERRUPT_MODE 0x00000001U
<> 144:ef7eb2e8f9f7 876 /**
<> 144:ef7eb2e8f9f7 877 * @}
<> 144:ef7eb2e8f9f7 878 */
<> 144:ef7eb2e8f9f7 879
<> 144:ef7eb2e8f9f7 880 /** @defgroup ETH_Checksum_Mode ETH Checksum Mode
<> 144:ef7eb2e8f9f7 881 * @{
<> 144:ef7eb2e8f9f7 882 */
AnnaBridge 165:e614a9f1c9e2 883 #define ETH_CHECKSUM_BY_HARDWARE 0x00000000U
AnnaBridge 165:e614a9f1c9e2 884 #define ETH_CHECKSUM_BY_SOFTWARE 0x00000001U
<> 144:ef7eb2e8f9f7 885 /**
<> 144:ef7eb2e8f9f7 886 * @}
<> 144:ef7eb2e8f9f7 887 */
<> 144:ef7eb2e8f9f7 888
<> 144:ef7eb2e8f9f7 889 /** @defgroup ETH_Media_Interface ETH Media Interface
<> 144:ef7eb2e8f9f7 890 * @{
<> 144:ef7eb2e8f9f7 891 */
AnnaBridge 165:e614a9f1c9e2 892 #define ETH_MEDIA_INTERFACE_MII 0x00000000U
<> 144:ef7eb2e8f9f7 893 #define ETH_MEDIA_INTERFACE_RMII ((uint32_t)AFIO_MAPR_MII_RMII_SEL)
<> 144:ef7eb2e8f9f7 894
<> 144:ef7eb2e8f9f7 895 /**
<> 144:ef7eb2e8f9f7 896 * @}
<> 144:ef7eb2e8f9f7 897 */
<> 144:ef7eb2e8f9f7 898
<> 144:ef7eb2e8f9f7 899 /** @defgroup ETH_Watchdog ETH Watchdog
<> 144:ef7eb2e8f9f7 900 * @{
<> 144:ef7eb2e8f9f7 901 */
AnnaBridge 165:e614a9f1c9e2 902 #define ETH_WATCHDOG_ENABLE 0x00000000U
AnnaBridge 165:e614a9f1c9e2 903 #define ETH_WATCHDOG_DISABLE 0x00800000U
<> 144:ef7eb2e8f9f7 904 /**
<> 144:ef7eb2e8f9f7 905 * @}
<> 144:ef7eb2e8f9f7 906 */
<> 144:ef7eb2e8f9f7 907
AnnaBridge 165:e614a9f1c9e2 908 /** @defgroup ETH_Jabber ETH Jabber
<> 144:ef7eb2e8f9f7 909 * @{
<> 144:ef7eb2e8f9f7 910 */
AnnaBridge 165:e614a9f1c9e2 911 #define ETH_JABBER_ENABLE 0x00000000U
AnnaBridge 165:e614a9f1c9e2 912 #define ETH_JABBER_DISABLE 0x00400000U
<> 144:ef7eb2e8f9f7 913 /**
<> 144:ef7eb2e8f9f7 914 * @}
<> 144:ef7eb2e8f9f7 915 */
<> 144:ef7eb2e8f9f7 916
<> 144:ef7eb2e8f9f7 917 /** @defgroup ETH_Inter_Frame_Gap ETH Inter Frame Gap
<> 144:ef7eb2e8f9f7 918 * @{
<> 144:ef7eb2e8f9f7 919 */
AnnaBridge 165:e614a9f1c9e2 920 #define ETH_INTERFRAMEGAP_96BIT 0x00000000U /*!< minimum IFG between frames during transmission is 96Bit */
AnnaBridge 165:e614a9f1c9e2 921 #define ETH_INTERFRAMEGAP_88BIT 0x00020000U /*!< minimum IFG between frames during transmission is 88Bit */
AnnaBridge 165:e614a9f1c9e2 922 #define ETH_INTERFRAMEGAP_80BIT 0x00040000U /*!< minimum IFG between frames during transmission is 80Bit */
AnnaBridge 165:e614a9f1c9e2 923 #define ETH_INTERFRAMEGAP_72BIT 0x00060000U /*!< minimum IFG between frames during transmission is 72Bit */
AnnaBridge 165:e614a9f1c9e2 924 #define ETH_INTERFRAMEGAP_64BIT 0x00080000U /*!< minimum IFG between frames during transmission is 64Bit */
AnnaBridge 165:e614a9f1c9e2 925 #define ETH_INTERFRAMEGAP_56BIT 0x000A0000U /*!< minimum IFG between frames during transmission is 56Bit */
AnnaBridge 165:e614a9f1c9e2 926 #define ETH_INTERFRAMEGAP_48BIT 0x000C0000U /*!< minimum IFG between frames during transmission is 48Bit */
AnnaBridge 165:e614a9f1c9e2 927 #define ETH_INTERFRAMEGAP_40BIT 0x000E0000U /*!< minimum IFG between frames during transmission is 40Bit */
<> 144:ef7eb2e8f9f7 928 /**
<> 144:ef7eb2e8f9f7 929 * @}
<> 144:ef7eb2e8f9f7 930 */
<> 144:ef7eb2e8f9f7 931
<> 144:ef7eb2e8f9f7 932 /** @defgroup ETH_Carrier_Sense ETH Carrier Sense
<> 144:ef7eb2e8f9f7 933 * @{
<> 144:ef7eb2e8f9f7 934 */
AnnaBridge 165:e614a9f1c9e2 935 #define ETH_CARRIERSENCE_ENABLE 0x00000000U
AnnaBridge 165:e614a9f1c9e2 936 #define ETH_CARRIERSENCE_DISABLE 0x00010000U
<> 144:ef7eb2e8f9f7 937 /**
<> 144:ef7eb2e8f9f7 938 * @}
<> 144:ef7eb2e8f9f7 939 */
<> 144:ef7eb2e8f9f7 940
<> 144:ef7eb2e8f9f7 941 /** @defgroup ETH_Receive_Own ETH Receive Own
<> 144:ef7eb2e8f9f7 942 * @{
<> 144:ef7eb2e8f9f7 943 */
AnnaBridge 165:e614a9f1c9e2 944 #define ETH_RECEIVEOWN_ENABLE 0x00000000U
AnnaBridge 165:e614a9f1c9e2 945 #define ETH_RECEIVEOWN_DISABLE 0x00002000U
<> 144:ef7eb2e8f9f7 946 /**
<> 144:ef7eb2e8f9f7 947 * @}
<> 144:ef7eb2e8f9f7 948 */
<> 144:ef7eb2e8f9f7 949
AnnaBridge 165:e614a9f1c9e2 950 /** @defgroup ETH_Loop_Back_Mode ETH Loop Back Mode
<> 144:ef7eb2e8f9f7 951 * @{
<> 144:ef7eb2e8f9f7 952 */
AnnaBridge 165:e614a9f1c9e2 953 #define ETH_LOOPBACKMODE_ENABLE 0x00001000U
AnnaBridge 165:e614a9f1c9e2 954 #define ETH_LOOPBACKMODE_DISABLE 0x00000000U
<> 144:ef7eb2e8f9f7 955 /**
<> 144:ef7eb2e8f9f7 956 * @}
<> 144:ef7eb2e8f9f7 957 */
<> 144:ef7eb2e8f9f7 958
<> 144:ef7eb2e8f9f7 959 /** @defgroup ETH_Checksum_Offload ETH Checksum Offload
<> 144:ef7eb2e8f9f7 960 * @{
<> 144:ef7eb2e8f9f7 961 */
AnnaBridge 165:e614a9f1c9e2 962 #define ETH_CHECKSUMOFFLAOD_ENABLE 0x00000400U
AnnaBridge 165:e614a9f1c9e2 963 #define ETH_CHECKSUMOFFLAOD_DISABLE 0x00000000U
<> 144:ef7eb2e8f9f7 964 /**
<> 144:ef7eb2e8f9f7 965 * @}
<> 144:ef7eb2e8f9f7 966 */
<> 144:ef7eb2e8f9f7 967
<> 144:ef7eb2e8f9f7 968 /** @defgroup ETH_Retry_Transmission ETH Retry Transmission
<> 144:ef7eb2e8f9f7 969 * @{
<> 144:ef7eb2e8f9f7 970 */
AnnaBridge 165:e614a9f1c9e2 971 #define ETH_RETRYTRANSMISSION_ENABLE 0x00000000U
AnnaBridge 165:e614a9f1c9e2 972 #define ETH_RETRYTRANSMISSION_DISABLE 0x00000200U
<> 144:ef7eb2e8f9f7 973 /**
<> 144:ef7eb2e8f9f7 974 * @}
<> 144:ef7eb2e8f9f7 975 */
<> 144:ef7eb2e8f9f7 976
<> 144:ef7eb2e8f9f7 977 /** @defgroup ETH_Automatic_Pad_CRC_Strip ETH Automatic Pad CRC Strip
<> 144:ef7eb2e8f9f7 978 * @{
<> 144:ef7eb2e8f9f7 979 */
AnnaBridge 165:e614a9f1c9e2 980 #define ETH_AUTOMATICPADCRCSTRIP_ENABLE 0x00000080U
AnnaBridge 165:e614a9f1c9e2 981 #define ETH_AUTOMATICPADCRCSTRIP_DISABLE 0x00000000U
<> 144:ef7eb2e8f9f7 982 /**
<> 144:ef7eb2e8f9f7 983 * @}
<> 144:ef7eb2e8f9f7 984 */
<> 144:ef7eb2e8f9f7 985
<> 144:ef7eb2e8f9f7 986 /** @defgroup ETH_Back_Off_Limit ETH Back Off Limit
<> 144:ef7eb2e8f9f7 987 * @{
<> 144:ef7eb2e8f9f7 988 */
AnnaBridge 165:e614a9f1c9e2 989 #define ETH_BACKOFFLIMIT_10 0x00000000U
AnnaBridge 165:e614a9f1c9e2 990 #define ETH_BACKOFFLIMIT_8 0x00000020U
AnnaBridge 165:e614a9f1c9e2 991 #define ETH_BACKOFFLIMIT_4 0x00000040U
AnnaBridge 165:e614a9f1c9e2 992 #define ETH_BACKOFFLIMIT_1 0x00000060U
<> 144:ef7eb2e8f9f7 993 /**
<> 144:ef7eb2e8f9f7 994 * @}
<> 144:ef7eb2e8f9f7 995 */
<> 144:ef7eb2e8f9f7 996
<> 144:ef7eb2e8f9f7 997 /** @defgroup ETH_Deferral_Check ETH Deferral Check
<> 144:ef7eb2e8f9f7 998 * @{
<> 144:ef7eb2e8f9f7 999 */
AnnaBridge 165:e614a9f1c9e2 1000 #define ETH_DEFFERRALCHECK_ENABLE 0x00000010U
AnnaBridge 165:e614a9f1c9e2 1001 #define ETH_DEFFERRALCHECK_DISABLE 0x00000000U
<> 144:ef7eb2e8f9f7 1002 /**
<> 144:ef7eb2e8f9f7 1003 * @}
<> 144:ef7eb2e8f9f7 1004 */
<> 144:ef7eb2e8f9f7 1005
<> 144:ef7eb2e8f9f7 1006 /** @defgroup ETH_Receive_All ETH Receive All
<> 144:ef7eb2e8f9f7 1007 * @{
<> 144:ef7eb2e8f9f7 1008 */
AnnaBridge 165:e614a9f1c9e2 1009 #define ETH_RECEIVEALL_ENABLE 0x80000000U
AnnaBridge 165:e614a9f1c9e2 1010 #define ETH_RECEIVEAll_DISABLE 0x00000000U
<> 144:ef7eb2e8f9f7 1011 /**
<> 144:ef7eb2e8f9f7 1012 * @}
<> 144:ef7eb2e8f9f7 1013 */
<> 144:ef7eb2e8f9f7 1014
<> 144:ef7eb2e8f9f7 1015 /** @defgroup ETH_Source_Addr_Filter ETH Source Addr Filter
<> 144:ef7eb2e8f9f7 1016 * @{
<> 144:ef7eb2e8f9f7 1017 */
AnnaBridge 165:e614a9f1c9e2 1018 #define ETH_SOURCEADDRFILTER_NORMAL_ENABLE 0x00000200U
AnnaBridge 165:e614a9f1c9e2 1019 #define ETH_SOURCEADDRFILTER_INVERSE_ENABLE 0x00000300U
AnnaBridge 165:e614a9f1c9e2 1020 #define ETH_SOURCEADDRFILTER_DISABLE 0x00000000U
<> 144:ef7eb2e8f9f7 1021 /**
<> 144:ef7eb2e8f9f7 1022 * @}
<> 144:ef7eb2e8f9f7 1023 */
<> 144:ef7eb2e8f9f7 1024
<> 144:ef7eb2e8f9f7 1025 /** @defgroup ETH_Pass_Control_Frames ETH Pass Control Frames
<> 144:ef7eb2e8f9f7 1026 * @{
<> 144:ef7eb2e8f9f7 1027 */
AnnaBridge 165:e614a9f1c9e2 1028 #define ETH_PASSCONTROLFRAMES_BLOCKALL 0x00000040U /*!< MAC filters all control frames from reaching the application */
AnnaBridge 165:e614a9f1c9e2 1029 #define ETH_PASSCONTROLFRAMES_FORWARDALL 0x00000080U /*!< MAC forwards all control frames to application even if they fail the Address Filter */
AnnaBridge 165:e614a9f1c9e2 1030 #define ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER 0x000000C0U /*!< MAC forwards control frames that pass the Address Filter. */
<> 144:ef7eb2e8f9f7 1031 /**
<> 144:ef7eb2e8f9f7 1032 * @}
<> 144:ef7eb2e8f9f7 1033 */
<> 144:ef7eb2e8f9f7 1034
<> 144:ef7eb2e8f9f7 1035 /** @defgroup ETH_Broadcast_Frames_Reception ETH Broadcast Frames Reception
<> 144:ef7eb2e8f9f7 1036 * @{
<> 144:ef7eb2e8f9f7 1037 */
AnnaBridge 165:e614a9f1c9e2 1038 #define ETH_BROADCASTFRAMESRECEPTION_ENABLE 0x00000000U
AnnaBridge 165:e614a9f1c9e2 1039 #define ETH_BROADCASTFRAMESRECEPTION_DISABLE 0x00000020U
<> 144:ef7eb2e8f9f7 1040 /**
<> 144:ef7eb2e8f9f7 1041 * @}
<> 144:ef7eb2e8f9f7 1042 */
<> 144:ef7eb2e8f9f7 1043
<> 144:ef7eb2e8f9f7 1044 /** @defgroup ETH_Destination_Addr_Filter ETH Destination Addr Filter
<> 144:ef7eb2e8f9f7 1045 * @{
<> 144:ef7eb2e8f9f7 1046 */
AnnaBridge 165:e614a9f1c9e2 1047 #define ETH_DESTINATIONADDRFILTER_NORMAL 0x00000000U
AnnaBridge 165:e614a9f1c9e2 1048 #define ETH_DESTINATIONADDRFILTER_INVERSE 0x00000008U
<> 144:ef7eb2e8f9f7 1049 /**
<> 144:ef7eb2e8f9f7 1050 * @}
<> 144:ef7eb2e8f9f7 1051 */
<> 144:ef7eb2e8f9f7 1052
<> 144:ef7eb2e8f9f7 1053 /** @defgroup ETH_Promiscuous_Mode ETH Promiscuous Mode
<> 144:ef7eb2e8f9f7 1054 * @{
<> 144:ef7eb2e8f9f7 1055 */
AnnaBridge 165:e614a9f1c9e2 1056 #define ETH_PROMISCUOUS_MODE_ENABLE 0x00000001U
AnnaBridge 165:e614a9f1c9e2 1057 #define ETH_PROMISCUOUS_MODE_DISABLE 0x00000000U
<> 144:ef7eb2e8f9f7 1058 /**
<> 144:ef7eb2e8f9f7 1059 * @}
<> 144:ef7eb2e8f9f7 1060 */
<> 144:ef7eb2e8f9f7 1061
<> 144:ef7eb2e8f9f7 1062 /** @defgroup ETH_Multicast_Frames_Filter ETH Multicast Frames Filter
<> 144:ef7eb2e8f9f7 1063 * @{
<> 144:ef7eb2e8f9f7 1064 */
AnnaBridge 165:e614a9f1c9e2 1065 #define ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE 0x00000404U
AnnaBridge 165:e614a9f1c9e2 1066 #define ETH_MULTICASTFRAMESFILTER_HASHTABLE 0x00000004U
AnnaBridge 165:e614a9f1c9e2 1067 #define ETH_MULTICASTFRAMESFILTER_PERFECT 0x00000000U
AnnaBridge 165:e614a9f1c9e2 1068 #define ETH_MULTICASTFRAMESFILTER_NONE 0x00000010U
<> 144:ef7eb2e8f9f7 1069 /**
<> 144:ef7eb2e8f9f7 1070 * @}
<> 144:ef7eb2e8f9f7 1071 */
<> 144:ef7eb2e8f9f7 1072
<> 144:ef7eb2e8f9f7 1073 /** @defgroup ETH_Unicast_Frames_Filter ETH Unicast Frames Filter
<> 144:ef7eb2e8f9f7 1074 * @{
<> 144:ef7eb2e8f9f7 1075 */
AnnaBridge 165:e614a9f1c9e2 1076 #define ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE 0x00000402U
AnnaBridge 165:e614a9f1c9e2 1077 #define ETH_UNICASTFRAMESFILTER_HASHTABLE 0x00000002U
AnnaBridge 165:e614a9f1c9e2 1078 #define ETH_UNICASTFRAMESFILTER_PERFECT 0x00000000U
<> 144:ef7eb2e8f9f7 1079 /**
<> 144:ef7eb2e8f9f7 1080 * @}
<> 144:ef7eb2e8f9f7 1081 */
<> 144:ef7eb2e8f9f7 1082
AnnaBridge 165:e614a9f1c9e2 1083 /** @defgroup ETH_Zero_Quanta_Pause ETH Zero Quanta Pause
<> 144:ef7eb2e8f9f7 1084 * @{
<> 144:ef7eb2e8f9f7 1085 */
AnnaBridge 165:e614a9f1c9e2 1086 #define ETH_ZEROQUANTAPAUSE_ENABLE 0x00000000U
AnnaBridge 165:e614a9f1c9e2 1087 #define ETH_ZEROQUANTAPAUSE_DISABLE 0x00000080U
<> 144:ef7eb2e8f9f7 1088 /**
<> 144:ef7eb2e8f9f7 1089 * @}
<> 144:ef7eb2e8f9f7 1090 */
<> 144:ef7eb2e8f9f7 1091
<> 144:ef7eb2e8f9f7 1092 /** @defgroup ETH_Pause_Low_Threshold ETH Pause Low Threshold
<> 144:ef7eb2e8f9f7 1093 * @{
<> 144:ef7eb2e8f9f7 1094 */
AnnaBridge 165:e614a9f1c9e2 1095 #define ETH_PAUSELOWTHRESHOLD_MINUS4 0x00000000U /*!< Pause time minus 4 slot times */
AnnaBridge 165:e614a9f1c9e2 1096 #define ETH_PAUSELOWTHRESHOLD_MINUS28 0x00000010U /*!< Pause time minus 28 slot times */
AnnaBridge 165:e614a9f1c9e2 1097 #define ETH_PAUSELOWTHRESHOLD_MINUS144 0x00000020U /*!< Pause time minus 144 slot times */
AnnaBridge 165:e614a9f1c9e2 1098 #define ETH_PAUSELOWTHRESHOLD_MINUS256 0x00000030U /*!< Pause time minus 256 slot times */
<> 144:ef7eb2e8f9f7 1099 /**
<> 144:ef7eb2e8f9f7 1100 * @}
<> 144:ef7eb2e8f9f7 1101 */
<> 144:ef7eb2e8f9f7 1102
<> 144:ef7eb2e8f9f7 1103 /** @defgroup ETH_Unicast_Pause_Frame_Detect ETH Unicast Pause Frame Detect
<> 144:ef7eb2e8f9f7 1104 * @{
<> 144:ef7eb2e8f9f7 1105 */
AnnaBridge 165:e614a9f1c9e2 1106 #define ETH_UNICASTPAUSEFRAMEDETECT_ENABLE 0x00000008U
AnnaBridge 165:e614a9f1c9e2 1107 #define ETH_UNICASTPAUSEFRAMEDETECT_DISABLE 0x00000000U
<> 144:ef7eb2e8f9f7 1108 /**
<> 144:ef7eb2e8f9f7 1109 * @}
<> 144:ef7eb2e8f9f7 1110 */
<> 144:ef7eb2e8f9f7 1111
<> 144:ef7eb2e8f9f7 1112 /** @defgroup ETH_Receive_Flow_Control ETH Receive Flow Control
<> 144:ef7eb2e8f9f7 1113 * @{
<> 144:ef7eb2e8f9f7 1114 */
AnnaBridge 165:e614a9f1c9e2 1115 #define ETH_RECEIVEFLOWCONTROL_ENABLE 0x00000004U
AnnaBridge 165:e614a9f1c9e2 1116 #define ETH_RECEIVEFLOWCONTROL_DISABLE 0x00000000U
<> 144:ef7eb2e8f9f7 1117 /**
<> 144:ef7eb2e8f9f7 1118 * @}
<> 144:ef7eb2e8f9f7 1119 */
<> 144:ef7eb2e8f9f7 1120
<> 144:ef7eb2e8f9f7 1121 /** @defgroup ETH_Transmit_Flow_Control ETH Transmit Flow Control
<> 144:ef7eb2e8f9f7 1122 * @{
<> 144:ef7eb2e8f9f7 1123 */
AnnaBridge 165:e614a9f1c9e2 1124 #define ETH_TRANSMITFLOWCONTROL_ENABLE 0x00000002U
AnnaBridge 165:e614a9f1c9e2 1125 #define ETH_TRANSMITFLOWCONTROL_DISABLE 0x00000000U
<> 144:ef7eb2e8f9f7 1126 /**
<> 144:ef7eb2e8f9f7 1127 * @}
<> 144:ef7eb2e8f9f7 1128 */
<> 144:ef7eb2e8f9f7 1129
<> 144:ef7eb2e8f9f7 1130 /** @defgroup ETH_VLAN_Tag_Comparison ETH VLAN Tag Comparison
<> 144:ef7eb2e8f9f7 1131 * @{
<> 144:ef7eb2e8f9f7 1132 */
AnnaBridge 165:e614a9f1c9e2 1133 #define ETH_VLANTAGCOMPARISON_12BIT 0x00010000U
AnnaBridge 165:e614a9f1c9e2 1134 #define ETH_VLANTAGCOMPARISON_16BIT 0x00000000U
<> 144:ef7eb2e8f9f7 1135 /**
<> 144:ef7eb2e8f9f7 1136 * @}
<> 144:ef7eb2e8f9f7 1137 */
<> 144:ef7eb2e8f9f7 1138
<> 144:ef7eb2e8f9f7 1139 /** @defgroup ETH_MAC_addresses ETH MAC addresses
<> 144:ef7eb2e8f9f7 1140 * @{
<> 144:ef7eb2e8f9f7 1141 */
AnnaBridge 165:e614a9f1c9e2 1142 #define ETH_MAC_ADDRESS0 0x00000000U
AnnaBridge 165:e614a9f1c9e2 1143 #define ETH_MAC_ADDRESS1 0x00000008U
AnnaBridge 165:e614a9f1c9e2 1144 #define ETH_MAC_ADDRESS2 0x00000010U
AnnaBridge 165:e614a9f1c9e2 1145 #define ETH_MAC_ADDRESS3 0x00000018U
<> 144:ef7eb2e8f9f7 1146 /**
<> 144:ef7eb2e8f9f7 1147 * @}
<> 144:ef7eb2e8f9f7 1148 */
<> 144:ef7eb2e8f9f7 1149
AnnaBridge 165:e614a9f1c9e2 1150 /** @defgroup ETH_MAC_addresses_filter_SA_DA ETH MAC addresses filter SA DA
<> 144:ef7eb2e8f9f7 1151 * @{
<> 144:ef7eb2e8f9f7 1152 */
AnnaBridge 165:e614a9f1c9e2 1153 #define ETH_MAC_ADDRESSFILTER_SA 0x00000000U
AnnaBridge 165:e614a9f1c9e2 1154 #define ETH_MAC_ADDRESSFILTER_DA 0x00000008U
<> 144:ef7eb2e8f9f7 1155 /**
<> 144:ef7eb2e8f9f7 1156 * @}
<> 144:ef7eb2e8f9f7 1157 */
<> 144:ef7eb2e8f9f7 1158
AnnaBridge 165:e614a9f1c9e2 1159 /** @defgroup ETH_MAC_addresses_filter_Mask_bytes ETH MAC addresses filter Mask bytes
<> 144:ef7eb2e8f9f7 1160 * @{
<> 144:ef7eb2e8f9f7 1161 */
AnnaBridge 165:e614a9f1c9e2 1162 #define ETH_MAC_ADDRESSMASK_BYTE6 0x20000000U /*!< Mask MAC Address high reg bits [15:8] */
AnnaBridge 165:e614a9f1c9e2 1163 #define ETH_MAC_ADDRESSMASK_BYTE5 0x10000000U /*!< Mask MAC Address high reg bits [7:0] */
AnnaBridge 165:e614a9f1c9e2 1164 #define ETH_MAC_ADDRESSMASK_BYTE4 0x08000000U /*!< Mask MAC Address low reg bits [31:24] */
AnnaBridge 165:e614a9f1c9e2 1165 #define ETH_MAC_ADDRESSMASK_BYTE3 0x04000000U /*!< Mask MAC Address low reg bits [23:16] */
AnnaBridge 165:e614a9f1c9e2 1166 #define ETH_MAC_ADDRESSMASK_BYTE2 0x02000000U /*!< Mask MAC Address low reg bits [15:8] */
AnnaBridge 165:e614a9f1c9e2 1167 #define ETH_MAC_ADDRESSMASK_BYTE1 0x01000000U /*!< Mask MAC Address low reg bits [70] */
<> 144:ef7eb2e8f9f7 1168 /**
<> 144:ef7eb2e8f9f7 1169 * @}
<> 144:ef7eb2e8f9f7 1170 */
<> 144:ef7eb2e8f9f7 1171
<> 144:ef7eb2e8f9f7 1172 /** @defgroup ETH_Drop_TCP_IP_Checksum_Error_Frame ETH Drop TCP IP Checksum Error Frame
<> 144:ef7eb2e8f9f7 1173 * @{
<> 144:ef7eb2e8f9f7 1174 */
AnnaBridge 165:e614a9f1c9e2 1175 #define ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE 0x00000000U
AnnaBridge 165:e614a9f1c9e2 1176 #define ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE 0x04000000U
<> 144:ef7eb2e8f9f7 1177 /**
<> 144:ef7eb2e8f9f7 1178 * @}
<> 144:ef7eb2e8f9f7 1179 */
<> 144:ef7eb2e8f9f7 1180
AnnaBridge 165:e614a9f1c9e2 1181 /** @defgroup ETH_Receive_Store_Forward ETH Receive Store Forward
<> 144:ef7eb2e8f9f7 1182 * @{
<> 144:ef7eb2e8f9f7 1183 */
AnnaBridge 165:e614a9f1c9e2 1184 #define ETH_RECEIVESTOREFORWARD_ENABLE 0x02000000U
AnnaBridge 165:e614a9f1c9e2 1185 #define ETH_RECEIVESTOREFORWARD_DISABLE 0x00000000U
<> 144:ef7eb2e8f9f7 1186 /**
<> 144:ef7eb2e8f9f7 1187 * @}
<> 144:ef7eb2e8f9f7 1188 */
<> 144:ef7eb2e8f9f7 1189
<> 144:ef7eb2e8f9f7 1190 /** @defgroup ETH_Flush_Received_Frame ETH Flush Received Frame
<> 144:ef7eb2e8f9f7 1191 * @{
<> 144:ef7eb2e8f9f7 1192 */
AnnaBridge 165:e614a9f1c9e2 1193 #define ETH_FLUSHRECEIVEDFRAME_ENABLE 0x00000000U
AnnaBridge 165:e614a9f1c9e2 1194 #define ETH_FLUSHRECEIVEDFRAME_DISABLE 0x01000000U
<> 144:ef7eb2e8f9f7 1195 /**
<> 144:ef7eb2e8f9f7 1196 * @}
<> 144:ef7eb2e8f9f7 1197 */
<> 144:ef7eb2e8f9f7 1198
<> 144:ef7eb2e8f9f7 1199 /** @defgroup ETH_Transmit_Store_Forward ETH Transmit Store Forward
<> 144:ef7eb2e8f9f7 1200 * @{
<> 144:ef7eb2e8f9f7 1201 */
AnnaBridge 165:e614a9f1c9e2 1202 #define ETH_TRANSMITSTOREFORWARD_ENABLE 0x00200000U
AnnaBridge 165:e614a9f1c9e2 1203 #define ETH_TRANSMITSTOREFORWARD_DISABLE 0x00000000U
<> 144:ef7eb2e8f9f7 1204 /**
<> 144:ef7eb2e8f9f7 1205 * @}
<> 144:ef7eb2e8f9f7 1206 */
<> 144:ef7eb2e8f9f7 1207
<> 144:ef7eb2e8f9f7 1208 /** @defgroup ETH_Transmit_Threshold_Control ETH Transmit Threshold Control
<> 144:ef7eb2e8f9f7 1209 * @{
<> 144:ef7eb2e8f9f7 1210 */
AnnaBridge 165:e614a9f1c9e2 1211 #define ETH_TRANSMITTHRESHOLDCONTROL_64BYTES 0x00000000U /*!< threshold level of the MTL Transmit FIFO is 64 Bytes */
AnnaBridge 165:e614a9f1c9e2 1212 #define ETH_TRANSMITTHRESHOLDCONTROL_128BYTES 0x00004000U /*!< threshold level of the MTL Transmit FIFO is 128 Bytes */
AnnaBridge 165:e614a9f1c9e2 1213 #define ETH_TRANSMITTHRESHOLDCONTROL_192BYTES 0x00008000U /*!< threshold level of the MTL Transmit FIFO is 192 Bytes */
AnnaBridge 165:e614a9f1c9e2 1214 #define ETH_TRANSMITTHRESHOLDCONTROL_256BYTES 0x0000C000U /*!< threshold level of the MTL Transmit FIFO is 256 Bytes */
AnnaBridge 165:e614a9f1c9e2 1215 #define ETH_TRANSMITTHRESHOLDCONTROL_40BYTES 0x00010000U /*!< threshold level of the MTL Transmit FIFO is 40 Bytes */
AnnaBridge 165:e614a9f1c9e2 1216 #define ETH_TRANSMITTHRESHOLDCONTROL_32BYTES 0x00014000U /*!< threshold level of the MTL Transmit FIFO is 32 Bytes */
AnnaBridge 165:e614a9f1c9e2 1217 #define ETH_TRANSMITTHRESHOLDCONTROL_24BYTES 0x00018000U /*!< threshold level of the MTL Transmit FIFO is 24 Bytes */
AnnaBridge 165:e614a9f1c9e2 1218 #define ETH_TRANSMITTHRESHOLDCONTROL_16BYTES 0x0001C000U /*!< threshold level of the MTL Transmit FIFO is 16 Bytes */
<> 144:ef7eb2e8f9f7 1219 /**
<> 144:ef7eb2e8f9f7 1220 * @}
<> 144:ef7eb2e8f9f7 1221 */
<> 144:ef7eb2e8f9f7 1222
<> 144:ef7eb2e8f9f7 1223 /** @defgroup ETH_Forward_Error_Frames ETH Forward Error Frames
<> 144:ef7eb2e8f9f7 1224 * @{
<> 144:ef7eb2e8f9f7 1225 */
AnnaBridge 165:e614a9f1c9e2 1226 #define ETH_FORWARDERRORFRAMES_ENABLE 0x00000080U
AnnaBridge 165:e614a9f1c9e2 1227 #define ETH_FORWARDERRORFRAMES_DISABLE 0x00000000U
<> 144:ef7eb2e8f9f7 1228 /**
<> 144:ef7eb2e8f9f7 1229 * @}
<> 144:ef7eb2e8f9f7 1230 */
<> 144:ef7eb2e8f9f7 1231
<> 144:ef7eb2e8f9f7 1232 /** @defgroup ETH_Forward_Undersized_Good_Frames ETH Forward Undersized Good Frames
<> 144:ef7eb2e8f9f7 1233 * @{
<> 144:ef7eb2e8f9f7 1234 */
AnnaBridge 165:e614a9f1c9e2 1235 #define ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE 0x00000040U
AnnaBridge 165:e614a9f1c9e2 1236 #define ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE 0x00000000U
<> 144:ef7eb2e8f9f7 1237 /**
<> 144:ef7eb2e8f9f7 1238 * @}
<> 144:ef7eb2e8f9f7 1239 */
<> 144:ef7eb2e8f9f7 1240
<> 144:ef7eb2e8f9f7 1241 /** @defgroup ETH_Receive_Threshold_Control ETH Receive Threshold Control
<> 144:ef7eb2e8f9f7 1242 * @{
<> 144:ef7eb2e8f9f7 1243 */
AnnaBridge 165:e614a9f1c9e2 1244 #define ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES 0x00000000U /*!< threshold level of the MTL Receive FIFO is 64 Bytes */
AnnaBridge 165:e614a9f1c9e2 1245 #define ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES 0x00000008U /*!< threshold level of the MTL Receive FIFO is 32 Bytes */
AnnaBridge 165:e614a9f1c9e2 1246 #define ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES 0x00000010U /*!< threshold level of the MTL Receive FIFO is 96 Bytes */
AnnaBridge 165:e614a9f1c9e2 1247 #define ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES 0x00000018U /*!< threshold level of the MTL Receive FIFO is 128 Bytes */
<> 144:ef7eb2e8f9f7 1248 /**
<> 144:ef7eb2e8f9f7 1249 * @}
<> 144:ef7eb2e8f9f7 1250 */
<> 144:ef7eb2e8f9f7 1251
<> 144:ef7eb2e8f9f7 1252 /** @defgroup ETH_Second_Frame_Operate ETH Second Frame Operate
<> 144:ef7eb2e8f9f7 1253 * @{
<> 144:ef7eb2e8f9f7 1254 */
AnnaBridge 165:e614a9f1c9e2 1255 #define ETH_SECONDFRAMEOPERARTE_ENABLE 0x00000004U
AnnaBridge 165:e614a9f1c9e2 1256 #define ETH_SECONDFRAMEOPERARTE_DISABLE 0x00000000U
<> 144:ef7eb2e8f9f7 1257 /**
<> 144:ef7eb2e8f9f7 1258 * @}
<> 144:ef7eb2e8f9f7 1259 */
<> 144:ef7eb2e8f9f7 1260
AnnaBridge 165:e614a9f1c9e2 1261 /** @defgroup ETH_Address_Aligned_Beats ETH Address Aligned Beats
<> 144:ef7eb2e8f9f7 1262 * @{
<> 144:ef7eb2e8f9f7 1263 */
AnnaBridge 165:e614a9f1c9e2 1264 #define ETH_ADDRESSALIGNEDBEATS_ENABLE 0x02000000U
AnnaBridge 165:e614a9f1c9e2 1265 #define ETH_ADDRESSALIGNEDBEATS_DISABLE 0x00000000U
<> 144:ef7eb2e8f9f7 1266 /**
<> 144:ef7eb2e8f9f7 1267 * @}
<> 144:ef7eb2e8f9f7 1268 */
<> 144:ef7eb2e8f9f7 1269
<> 144:ef7eb2e8f9f7 1270 /** @defgroup ETH_Fixed_Burst ETH Fixed Burst
<> 144:ef7eb2e8f9f7 1271 * @{
<> 144:ef7eb2e8f9f7 1272 */
AnnaBridge 165:e614a9f1c9e2 1273 #define ETH_FIXEDBURST_ENABLE 0x00010000U
AnnaBridge 165:e614a9f1c9e2 1274 #define ETH_FIXEDBURST_DISABLE 0x00000000U
<> 144:ef7eb2e8f9f7 1275 /**
<> 144:ef7eb2e8f9f7 1276 * @}
<> 144:ef7eb2e8f9f7 1277 */
<> 144:ef7eb2e8f9f7 1278
AnnaBridge 165:e614a9f1c9e2 1279 /** @defgroup ETH_Rx_DMA_Burst_Length ETH Rx DMA Burst Length
<> 144:ef7eb2e8f9f7 1280 * @{
<> 144:ef7eb2e8f9f7 1281 */
AnnaBridge 165:e614a9f1c9e2 1282 #define ETH_RXDMABURSTLENGTH_1BEAT 0x00020000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 1 */
AnnaBridge 165:e614a9f1c9e2 1283 #define ETH_RXDMABURSTLENGTH_2BEAT 0x00040000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 2 */
AnnaBridge 165:e614a9f1c9e2 1284 #define ETH_RXDMABURSTLENGTH_4BEAT 0x00080000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */
AnnaBridge 165:e614a9f1c9e2 1285 #define ETH_RXDMABURSTLENGTH_8BEAT 0x00100000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */
AnnaBridge 165:e614a9f1c9e2 1286 #define ETH_RXDMABURSTLENGTH_16BEAT 0x00200000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */
AnnaBridge 165:e614a9f1c9e2 1287 #define ETH_RXDMABURSTLENGTH_32BEAT 0x00400000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */
AnnaBridge 165:e614a9f1c9e2 1288 #define ETH_RXDMABURSTLENGTH_4XPBL_4BEAT 0x01020000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */
AnnaBridge 165:e614a9f1c9e2 1289 #define ETH_RXDMABURSTLENGTH_4XPBL_8BEAT 0x01040000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */
AnnaBridge 165:e614a9f1c9e2 1290 #define ETH_RXDMABURSTLENGTH_4XPBL_16BEAT 0x01080000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */
AnnaBridge 165:e614a9f1c9e2 1291 #define ETH_RXDMABURSTLENGTH_4XPBL_32BEAT 0x01100000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */
AnnaBridge 165:e614a9f1c9e2 1292 #define ETH_RXDMABURSTLENGTH_4XPBL_64BEAT 0x01200000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 64 */
AnnaBridge 165:e614a9f1c9e2 1293 #define ETH_RXDMABURSTLENGTH_4XPBL_128BEAT 0x01400000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 128 */
<> 144:ef7eb2e8f9f7 1294 /**
<> 144:ef7eb2e8f9f7 1295 * @}
<> 144:ef7eb2e8f9f7 1296 */
<> 144:ef7eb2e8f9f7 1297
<> 144:ef7eb2e8f9f7 1298 /** @defgroup ETH_Tx_DMA_Burst_Length ETH Tx DMA Burst Length
<> 144:ef7eb2e8f9f7 1299 * @{
<> 144:ef7eb2e8f9f7 1300 */
AnnaBridge 165:e614a9f1c9e2 1301 #define ETH_TXDMABURSTLENGTH_1BEAT 0x00000100U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
AnnaBridge 165:e614a9f1c9e2 1302 #define ETH_TXDMABURSTLENGTH_2BEAT 0x00000200U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
AnnaBridge 165:e614a9f1c9e2 1303 #define ETH_TXDMABURSTLENGTH_4BEAT 0x00000400U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
AnnaBridge 165:e614a9f1c9e2 1304 #define ETH_TXDMABURSTLENGTH_8BEAT 0x00000800U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
AnnaBridge 165:e614a9f1c9e2 1305 #define ETH_TXDMABURSTLENGTH_16BEAT 0x00001000U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
AnnaBridge 165:e614a9f1c9e2 1306 #define ETH_TXDMABURSTLENGTH_32BEAT 0x00002000U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
AnnaBridge 165:e614a9f1c9e2 1307 #define ETH_TXDMABURSTLENGTH_4XPBL_4BEAT 0x01000100U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
AnnaBridge 165:e614a9f1c9e2 1308 #define ETH_TXDMABURSTLENGTH_4XPBL_8BEAT 0x01000200U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
AnnaBridge 165:e614a9f1c9e2 1309 #define ETH_TXDMABURSTLENGTH_4XPBL_16BEAT 0x01000400U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
AnnaBridge 165:e614a9f1c9e2 1310 #define ETH_TXDMABURSTLENGTH_4XPBL_32BEAT 0x01000800U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
AnnaBridge 165:e614a9f1c9e2 1311 #define ETH_TXDMABURSTLENGTH_4XPBL_64BEAT 0x01001000U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
AnnaBridge 165:e614a9f1c9e2 1312 #define ETH_TXDMABURSTLENGTH_4XPBL_128BEAT 0x01002000U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
<> 144:ef7eb2e8f9f7 1313
<> 144:ef7eb2e8f9f7 1314 /**
<> 144:ef7eb2e8f9f7 1315 * @}
<> 144:ef7eb2e8f9f7 1316 */
<> 144:ef7eb2e8f9f7 1317
<> 144:ef7eb2e8f9f7 1318 /** @defgroup ETH_DMA_Arbitration ETH DMA Arbitration
<> 144:ef7eb2e8f9f7 1319 * @{
<> 144:ef7eb2e8f9f7 1320 */
AnnaBridge 165:e614a9f1c9e2 1321 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1 0x00000000U
AnnaBridge 165:e614a9f1c9e2 1322 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1 0x00004000U
AnnaBridge 165:e614a9f1c9e2 1323 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1 0x00008000U
AnnaBridge 165:e614a9f1c9e2 1324 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1 0x0000C000U
AnnaBridge 165:e614a9f1c9e2 1325 #define ETH_DMAARBITRATION_RXPRIORTX 0x00000002U
<> 144:ef7eb2e8f9f7 1326 /**
<> 144:ef7eb2e8f9f7 1327 * @}
<> 144:ef7eb2e8f9f7 1328 */
<> 144:ef7eb2e8f9f7 1329
AnnaBridge 165:e614a9f1c9e2 1330 /** @defgroup ETH_DMA_Tx_descriptor_segment ETH DMA Tx descriptor segment
<> 144:ef7eb2e8f9f7 1331 * @{
<> 144:ef7eb2e8f9f7 1332 */
AnnaBridge 165:e614a9f1c9e2 1333 #define ETH_DMATXDESC_LASTSEGMENTS 0x40000000U /*!< Last Segment */
AnnaBridge 165:e614a9f1c9e2 1334 #define ETH_DMATXDESC_FIRSTSEGMENT 0x20000000U /*!< First Segment */
<> 144:ef7eb2e8f9f7 1335 /**
<> 144:ef7eb2e8f9f7 1336 * @}
<> 144:ef7eb2e8f9f7 1337 */
<> 144:ef7eb2e8f9f7 1338
AnnaBridge 165:e614a9f1c9e2 1339 /** @defgroup ETH_DMA_Tx_descriptor_Checksum_Insertion_Control ETH DMA Tx descriptor Checksum Insertion Control
<> 144:ef7eb2e8f9f7 1340 * @{
<> 144:ef7eb2e8f9f7 1341 */
AnnaBridge 165:e614a9f1c9e2 1342 #define ETH_DMATXDESC_CHECKSUMBYPASS 0x00000000U /*!< Checksum engine bypass */
AnnaBridge 165:e614a9f1c9e2 1343 #define ETH_DMATXDESC_CHECKSUMIPV4HEADER 0x00400000U /*!< IPv4 header checksum insertion */
AnnaBridge 165:e614a9f1c9e2 1344 #define ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT 0x00800000U /*!< TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present */
AnnaBridge 165:e614a9f1c9e2 1345 #define ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL 0x00C00000U /*!< TCP/UDP/ICMP checksum fully in hardware including pseudo header */
<> 144:ef7eb2e8f9f7 1346 /**
<> 144:ef7eb2e8f9f7 1347 * @}
<> 144:ef7eb2e8f9f7 1348 */
<> 144:ef7eb2e8f9f7 1349
AnnaBridge 165:e614a9f1c9e2 1350 /** @defgroup ETH_DMA_Rx_descriptor_buffers ETH DMA Rx descriptor buffers
<> 144:ef7eb2e8f9f7 1351 * @{
<> 144:ef7eb2e8f9f7 1352 */
AnnaBridge 165:e614a9f1c9e2 1353 #define ETH_DMARXDESC_BUFFER1 0x00000000U /*!< DMA Rx Desc Buffer1 */
AnnaBridge 165:e614a9f1c9e2 1354 #define ETH_DMARXDESC_BUFFER2 0x00000001U /*!< DMA Rx Desc Buffer2 */
<> 144:ef7eb2e8f9f7 1355 /**
<> 144:ef7eb2e8f9f7 1356 * @}
<> 144:ef7eb2e8f9f7 1357 */
<> 144:ef7eb2e8f9f7 1358
<> 144:ef7eb2e8f9f7 1359 /** @defgroup ETH_PMT_Flags ETH PMT Flags
<> 144:ef7eb2e8f9f7 1360 * @{
<> 144:ef7eb2e8f9f7 1361 */
AnnaBridge 165:e614a9f1c9e2 1362 #define ETH_PMT_FLAG_WUFFRPR 0x80000000U /*!< Wake-Up Frame Filter Register Pointer Reset */
AnnaBridge 165:e614a9f1c9e2 1363 #define ETH_PMT_FLAG_WUFR 0x00000040U /*!< Wake-Up Frame Received */
AnnaBridge 165:e614a9f1c9e2 1364 #define ETH_PMT_FLAG_MPR 0x00000020U /*!< Magic Packet Received */
<> 144:ef7eb2e8f9f7 1365 /**
<> 144:ef7eb2e8f9f7 1366 * @}
<> 144:ef7eb2e8f9f7 1367 */
<> 144:ef7eb2e8f9f7 1368
<> 144:ef7eb2e8f9f7 1369 /** @defgroup ETH_MMC_Tx_Interrupts ETH MMC Tx Interrupts
<> 144:ef7eb2e8f9f7 1370 * @{
<> 144:ef7eb2e8f9f7 1371 */
AnnaBridge 165:e614a9f1c9e2 1372 #define ETH_MMC_IT_TGF 0x00200000U /*!< When Tx good frame counter reaches half the maximum value */
AnnaBridge 165:e614a9f1c9e2 1373 #define ETH_MMC_IT_TGFMSC 0x00008000U /*!< When Tx good multi col counter reaches half the maximum value */
AnnaBridge 165:e614a9f1c9e2 1374 #define ETH_MMC_IT_TGFSC 0x00004000U /*!< When Tx good single col counter reaches half the maximum value */
<> 144:ef7eb2e8f9f7 1375 /**
<> 144:ef7eb2e8f9f7 1376 * @}
<> 144:ef7eb2e8f9f7 1377 */
<> 144:ef7eb2e8f9f7 1378
<> 144:ef7eb2e8f9f7 1379 /** @defgroup ETH_MMC_Rx_Interrupts ETH MMC Rx Interrupts
<> 144:ef7eb2e8f9f7 1380 * @{
<> 144:ef7eb2e8f9f7 1381 */
AnnaBridge 165:e614a9f1c9e2 1382 #define ETH_MMC_IT_RGUF 0x10020000U /*!< When Rx good unicast frames counter reaches half the maximum value */
AnnaBridge 165:e614a9f1c9e2 1383 #define ETH_MMC_IT_RFAE 0x10000040U /*!< When Rx alignment error counter reaches half the maximum value */
AnnaBridge 165:e614a9f1c9e2 1384 #define ETH_MMC_IT_RFCE 0x10000020U /*!< When Rx crc error counter reaches half the maximum value */
<> 144:ef7eb2e8f9f7 1385 /**
<> 144:ef7eb2e8f9f7 1386 * @}
<> 144:ef7eb2e8f9f7 1387 */
<> 144:ef7eb2e8f9f7 1388
<> 144:ef7eb2e8f9f7 1389 /** @defgroup ETH_MAC_Flags ETH MAC Flags
<> 144:ef7eb2e8f9f7 1390 * @{
<> 144:ef7eb2e8f9f7 1391 */
AnnaBridge 165:e614a9f1c9e2 1392 #define ETH_MAC_FLAG_TST 0x00000200U /*!< Time stamp trigger flag (on MAC) */
AnnaBridge 165:e614a9f1c9e2 1393 #define ETH_MAC_FLAG_MMCT 0x00000040U /*!< MMC transmit flag */
AnnaBridge 165:e614a9f1c9e2 1394 #define ETH_MAC_FLAG_MMCR 0x00000020U /*!< MMC receive flag */
AnnaBridge 165:e614a9f1c9e2 1395 #define ETH_MAC_FLAG_MMC 0x00000010U /*!< MMC flag (on MAC) */
AnnaBridge 165:e614a9f1c9e2 1396 #define ETH_MAC_FLAG_PMT 0x00000008U /*!< PMT flag (on MAC) */
<> 144:ef7eb2e8f9f7 1397 /**
<> 144:ef7eb2e8f9f7 1398 * @}
<> 144:ef7eb2e8f9f7 1399 */
<> 144:ef7eb2e8f9f7 1400
<> 144:ef7eb2e8f9f7 1401 /** @defgroup ETH_DMA_Flags ETH DMA Flags
<> 144:ef7eb2e8f9f7 1402 * @{
<> 144:ef7eb2e8f9f7 1403 */
AnnaBridge 165:e614a9f1c9e2 1404 #define ETH_DMA_FLAG_TST 0x20000000U /*!< Time-stamp trigger interrupt (on DMA) */
AnnaBridge 165:e614a9f1c9e2 1405 #define ETH_DMA_FLAG_PMT 0x10000000U /*!< PMT interrupt (on DMA) */
AnnaBridge 165:e614a9f1c9e2 1406 #define ETH_DMA_FLAG_MMC 0x08000000U /*!< MMC interrupt (on DMA) */
AnnaBridge 165:e614a9f1c9e2 1407 #define ETH_DMA_FLAG_DATATRANSFERERROR 0x00800000U /*!< Error bits 0-Rx DMA, 1-Tx DMA */
AnnaBridge 165:e614a9f1c9e2 1408 #define ETH_DMA_FLAG_READWRITEERROR 0x01000000U /*!< Error bits 0-write transfer, 1-read transfer */
AnnaBridge 165:e614a9f1c9e2 1409 #define ETH_DMA_FLAG_ACCESSERROR 0x02000000U /*!< Error bits 0-data buffer, 1-desc. access */
AnnaBridge 165:e614a9f1c9e2 1410 #define ETH_DMA_FLAG_NIS 0x00010000U /*!< Normal interrupt summary flag */
AnnaBridge 165:e614a9f1c9e2 1411 #define ETH_DMA_FLAG_AIS 0x00008000U /*!< Abnormal interrupt summary flag */
AnnaBridge 165:e614a9f1c9e2 1412 #define ETH_DMA_FLAG_ER 0x00004000U /*!< Early receive flag */
AnnaBridge 165:e614a9f1c9e2 1413 #define ETH_DMA_FLAG_FBE 0x00002000U /*!< Fatal bus error flag */
AnnaBridge 165:e614a9f1c9e2 1414 #define ETH_DMA_FLAG_ET 0x00000400U /*!< Early transmit flag */
AnnaBridge 165:e614a9f1c9e2 1415 #define ETH_DMA_FLAG_RWT 0x00000200U /*!< Receive watchdog timeout flag */
AnnaBridge 165:e614a9f1c9e2 1416 #define ETH_DMA_FLAG_RPS 0x00000100U /*!< Receive process stopped flag */
AnnaBridge 165:e614a9f1c9e2 1417 #define ETH_DMA_FLAG_RBU 0x00000080U /*!< Receive buffer unavailable flag */
AnnaBridge 165:e614a9f1c9e2 1418 #define ETH_DMA_FLAG_R 0x00000040U /*!< Receive flag */
AnnaBridge 165:e614a9f1c9e2 1419 #define ETH_DMA_FLAG_TU 0x00000020U /*!< Underflow flag */
AnnaBridge 165:e614a9f1c9e2 1420 #define ETH_DMA_FLAG_RO 0x00000010U /*!< Overflow flag */
AnnaBridge 165:e614a9f1c9e2 1421 #define ETH_DMA_FLAG_TJT 0x00000008U /*!< Transmit jabber timeout flag */
AnnaBridge 165:e614a9f1c9e2 1422 #define ETH_DMA_FLAG_TBU 0x00000004U /*!< Transmit buffer unavailable flag */
AnnaBridge 165:e614a9f1c9e2 1423 #define ETH_DMA_FLAG_TPS 0x00000002U /*!< Transmit process stopped flag */
AnnaBridge 165:e614a9f1c9e2 1424 #define ETH_DMA_FLAG_T 0x00000001U /*!< Transmit flag */
<> 144:ef7eb2e8f9f7 1425 /**
<> 144:ef7eb2e8f9f7 1426 * @}
<> 144:ef7eb2e8f9f7 1427 */
<> 144:ef7eb2e8f9f7 1428
AnnaBridge 165:e614a9f1c9e2 1429 /** @defgroup ETH_MAC_Interrupts ETH MAC Interrupts
<> 144:ef7eb2e8f9f7 1430 * @{
<> 144:ef7eb2e8f9f7 1431 */
AnnaBridge 165:e614a9f1c9e2 1432 #define ETH_MAC_IT_TST 0x00000200U /*!< Time stamp trigger interrupt (on MAC) */
AnnaBridge 165:e614a9f1c9e2 1433 #define ETH_MAC_IT_MMCT 0x00000040U /*!< MMC transmit interrupt */
AnnaBridge 165:e614a9f1c9e2 1434 #define ETH_MAC_IT_MMCR 0x00000020U /*!< MMC receive interrupt */
AnnaBridge 165:e614a9f1c9e2 1435 #define ETH_MAC_IT_MMC 0x00000010U /*!< MMC interrupt (on MAC) */
AnnaBridge 165:e614a9f1c9e2 1436 #define ETH_MAC_IT_PMT 0x00000008U /*!< PMT interrupt (on MAC) */
<> 144:ef7eb2e8f9f7 1437 /**
<> 144:ef7eb2e8f9f7 1438 * @}
<> 144:ef7eb2e8f9f7 1439 */
<> 144:ef7eb2e8f9f7 1440
AnnaBridge 165:e614a9f1c9e2 1441 /** @defgroup ETH_DMA_Interrupts ETH DMA Interrupts
<> 144:ef7eb2e8f9f7 1442 * @{
<> 144:ef7eb2e8f9f7 1443 */
AnnaBridge 165:e614a9f1c9e2 1444 #define ETH_DMA_IT_TST 0x20000000U /*!< Time-stamp trigger interrupt (on DMA) */
AnnaBridge 165:e614a9f1c9e2 1445 #define ETH_DMA_IT_PMT 0x10000000U /*!< PMT interrupt (on DMA) */
AnnaBridge 165:e614a9f1c9e2 1446 #define ETH_DMA_IT_MMC 0x08000000U /*!< MMC interrupt (on DMA) */
AnnaBridge 165:e614a9f1c9e2 1447 #define ETH_DMA_IT_NIS 0x00010000U /*!< Normal interrupt summary */
AnnaBridge 165:e614a9f1c9e2 1448 #define ETH_DMA_IT_AIS 0x00008000U /*!< Abnormal interrupt summary */
AnnaBridge 165:e614a9f1c9e2 1449 #define ETH_DMA_IT_ER 0x00004000U /*!< Early receive interrupt */
AnnaBridge 165:e614a9f1c9e2 1450 #define ETH_DMA_IT_FBE 0x00002000U /*!< Fatal bus error interrupt */
AnnaBridge 165:e614a9f1c9e2 1451 #define ETH_DMA_IT_ET 0x00000400U /*!< Early transmit interrupt */
AnnaBridge 165:e614a9f1c9e2 1452 #define ETH_DMA_IT_RWT 0x00000200U /*!< Receive watchdog timeout interrupt */
AnnaBridge 165:e614a9f1c9e2 1453 #define ETH_DMA_IT_RPS 0x00000100U /*!< Receive process stopped interrupt */
AnnaBridge 165:e614a9f1c9e2 1454 #define ETH_DMA_IT_RBU 0x00000080U /*!< Receive buffer unavailable interrupt */
AnnaBridge 165:e614a9f1c9e2 1455 #define ETH_DMA_IT_R 0x00000040U /*!< Receive interrupt */
AnnaBridge 165:e614a9f1c9e2 1456 #define ETH_DMA_IT_TU 0x00000020U /*!< Underflow interrupt */
AnnaBridge 165:e614a9f1c9e2 1457 #define ETH_DMA_IT_RO 0x00000010U /*!< Overflow interrupt */
AnnaBridge 165:e614a9f1c9e2 1458 #define ETH_DMA_IT_TJT 0x00000008U /*!< Transmit jabber timeout interrupt */
AnnaBridge 165:e614a9f1c9e2 1459 #define ETH_DMA_IT_TBU 0x00000004U /*!< Transmit buffer unavailable interrupt */
AnnaBridge 165:e614a9f1c9e2 1460 #define ETH_DMA_IT_TPS 0x00000002U /*!< Transmit process stopped interrupt */
AnnaBridge 165:e614a9f1c9e2 1461 #define ETH_DMA_IT_T 0x00000001U /*!< Transmit interrupt */
<> 144:ef7eb2e8f9f7 1462 /**
<> 144:ef7eb2e8f9f7 1463 * @}
<> 144:ef7eb2e8f9f7 1464 */
<> 144:ef7eb2e8f9f7 1465
<> 144:ef7eb2e8f9f7 1466 /** @defgroup ETH_DMA_transmit_process_state ETH DMA transmit process state
<> 144:ef7eb2e8f9f7 1467 * @{
<> 144:ef7eb2e8f9f7 1468 */
AnnaBridge 165:e614a9f1c9e2 1469 #define ETH_DMA_TRANSMITPROCESS_STOPPED 0x00000000U /*!< Stopped - Reset or Stop Tx Command issued */
AnnaBridge 165:e614a9f1c9e2 1470 #define ETH_DMA_TRANSMITPROCESS_FETCHING 0x00100000U /*!< Running - fetching the Tx descriptor */
AnnaBridge 165:e614a9f1c9e2 1471 #define ETH_DMA_TRANSMITPROCESS_WAITING 0x00200000U /*!< Running - waiting for status */
AnnaBridge 165:e614a9f1c9e2 1472 #define ETH_DMA_TRANSMITPROCESS_READING 0x00300000U /*!< Running - reading the data from host memory */
AnnaBridge 165:e614a9f1c9e2 1473 #define ETH_DMA_TRANSMITPROCESS_SUSPENDED 0x00600000U /*!< Suspended - Tx Descriptor unavailable */
AnnaBridge 165:e614a9f1c9e2 1474 #define ETH_DMA_TRANSMITPROCESS_CLOSING 0x00700000U /*!< Running - closing Rx descriptor */
<> 144:ef7eb2e8f9f7 1475
<> 144:ef7eb2e8f9f7 1476 /**
<> 144:ef7eb2e8f9f7 1477 * @}
<> 144:ef7eb2e8f9f7 1478 */
<> 144:ef7eb2e8f9f7 1479
<> 144:ef7eb2e8f9f7 1480
<> 144:ef7eb2e8f9f7 1481 /** @defgroup ETH_DMA_receive_process_state ETH DMA receive process state
<> 144:ef7eb2e8f9f7 1482 * @{
<> 144:ef7eb2e8f9f7 1483 */
AnnaBridge 165:e614a9f1c9e2 1484 #define ETH_DMA_RECEIVEPROCESS_STOPPED 0x00000000U /*!< Stopped - Reset or Stop Rx Command issued */
AnnaBridge 165:e614a9f1c9e2 1485 #define ETH_DMA_RECEIVEPROCESS_FETCHING 0x00020000U /*!< Running - fetching the Rx descriptor */
AnnaBridge 165:e614a9f1c9e2 1486 #define ETH_DMA_RECEIVEPROCESS_WAITING 0x00060000U /*!< Running - waiting for packet */
AnnaBridge 165:e614a9f1c9e2 1487 #define ETH_DMA_RECEIVEPROCESS_SUSPENDED 0x00080000U /*!< Suspended - Rx Descriptor unavailable */
AnnaBridge 165:e614a9f1c9e2 1488 #define ETH_DMA_RECEIVEPROCESS_CLOSING 0x000A0000U /*!< Running - closing descriptor */
AnnaBridge 165:e614a9f1c9e2 1489 #define ETH_DMA_RECEIVEPROCESS_QUEUING 0x000E0000U /*!< Running - queuing the receive frame into host memory */
<> 144:ef7eb2e8f9f7 1490
<> 144:ef7eb2e8f9f7 1491 /**
<> 144:ef7eb2e8f9f7 1492 * @}
<> 144:ef7eb2e8f9f7 1493 */
<> 144:ef7eb2e8f9f7 1494
<> 144:ef7eb2e8f9f7 1495 /** @defgroup ETH_DMA_overflow ETH DMA overflow
<> 144:ef7eb2e8f9f7 1496 * @{
<> 144:ef7eb2e8f9f7 1497 */
AnnaBridge 165:e614a9f1c9e2 1498 #define ETH_DMA_OVERFLOW_RXFIFOCOUNTER 0x10000000U /*!< Overflow bit for FIFO overflow counter */
AnnaBridge 165:e614a9f1c9e2 1499 #define ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER 0x00010000U /*!< Overflow bit for missed frame counter */
<> 144:ef7eb2e8f9f7 1500 /**
<> 144:ef7eb2e8f9f7 1501 * @}
<> 144:ef7eb2e8f9f7 1502 */
<> 144:ef7eb2e8f9f7 1503
AnnaBridge 165:e614a9f1c9e2 1504 /** @defgroup ETH_EXTI_LINE_WAKEUP ETH EXTI LINE WAKEUP
<> 144:ef7eb2e8f9f7 1505 * @{
<> 144:ef7eb2e8f9f7 1506 */
AnnaBridge 165:e614a9f1c9e2 1507 #define ETH_EXTI_LINE_WAKEUP 0x00080000U /*!< External interrupt line 19 Connected to the ETH EXTI Line */
<> 144:ef7eb2e8f9f7 1508
<> 144:ef7eb2e8f9f7 1509 /**
<> 144:ef7eb2e8f9f7 1510 * @}
<> 144:ef7eb2e8f9f7 1511 */
<> 144:ef7eb2e8f9f7 1512
<> 144:ef7eb2e8f9f7 1513 /**
<> 144:ef7eb2e8f9f7 1514 * @}
<> 144:ef7eb2e8f9f7 1515 */
<> 144:ef7eb2e8f9f7 1516
<> 144:ef7eb2e8f9f7 1517 /* Exported macro ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 1518 /** @defgroup ETH_Exported_Macros ETH Exported Macros
<> 144:ef7eb2e8f9f7 1519 * @brief macros to handle interrupts and specific clock configurations
<> 144:ef7eb2e8f9f7 1520 * @{
<> 144:ef7eb2e8f9f7 1521 */
<> 144:ef7eb2e8f9f7 1522
<> 144:ef7eb2e8f9f7 1523 /** @brief Reset ETH handle state
<> 144:ef7eb2e8f9f7 1524 * @param __HANDLE__: specifies the ETH handle.
<> 144:ef7eb2e8f9f7 1525 * @retval None
<> 144:ef7eb2e8f9f7 1526 */
<> 144:ef7eb2e8f9f7 1527 #define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ETH_STATE_RESET)
<> 144:ef7eb2e8f9f7 1528
<> 144:ef7eb2e8f9f7 1529 /**
<> 144:ef7eb2e8f9f7 1530 * @brief Checks whether the specified ETHERNET DMA Tx Desc flag is set or not.
<> 144:ef7eb2e8f9f7 1531 * @param __HANDLE__: ETH Handle
AnnaBridge 165:e614a9f1c9e2 1532 * @param __FLAG__: specifies the flag of TDES0 to check.
<> 144:ef7eb2e8f9f7 1533 * @retval the ETH_DMATxDescFlag (SET or RESET).
<> 144:ef7eb2e8f9f7 1534 */
<> 144:ef7eb2e8f9f7 1535 #define __HAL_ETH_DMATXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->TxDesc->Status & (__FLAG__) == (__FLAG__))
<> 144:ef7eb2e8f9f7 1536
<> 144:ef7eb2e8f9f7 1537 /**
<> 144:ef7eb2e8f9f7 1538 * @brief Checks whether the specified ETHERNET DMA Rx Desc flag is set or not.
<> 144:ef7eb2e8f9f7 1539 * @param __HANDLE__: ETH Handle
<> 144:ef7eb2e8f9f7 1540 * @param __FLAG__: specifies the flag of RDES0 to check.
<> 144:ef7eb2e8f9f7 1541 * @retval the ETH_DMATxDescFlag (SET or RESET).
<> 144:ef7eb2e8f9f7 1542 */
<> 144:ef7eb2e8f9f7 1543 #define __HAL_ETH_DMARXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->RxDesc->Status & (__FLAG__) == (__FLAG__))
<> 144:ef7eb2e8f9f7 1544
<> 144:ef7eb2e8f9f7 1545 /**
<> 144:ef7eb2e8f9f7 1546 * @brief Enables the specified DMA Rx Desc receive interrupt.
<> 144:ef7eb2e8f9f7 1547 * @param __HANDLE__: ETH Handle
<> 144:ef7eb2e8f9f7 1548 * @retval None
<> 144:ef7eb2e8f9f7 1549 */
<> 144:ef7eb2e8f9f7 1550 #define __HAL_ETH_DMARXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARXDESC_DIC))
<> 144:ef7eb2e8f9f7 1551
<> 144:ef7eb2e8f9f7 1552 /**
<> 144:ef7eb2e8f9f7 1553 * @brief Disables the specified DMA Rx Desc receive interrupt.
<> 144:ef7eb2e8f9f7 1554 * @param __HANDLE__: ETH Handle
<> 144:ef7eb2e8f9f7 1555 * @retval None
<> 144:ef7eb2e8f9f7 1556 */
<> 144:ef7eb2e8f9f7 1557 #define __HAL_ETH_DMARXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize |= ETH_DMARXDESC_DIC)
<> 144:ef7eb2e8f9f7 1558
<> 144:ef7eb2e8f9f7 1559 /**
<> 144:ef7eb2e8f9f7 1560 * @brief Set the specified DMA Rx Desc Own bit.
<> 144:ef7eb2e8f9f7 1561 * @param __HANDLE__: ETH Handle
<> 144:ef7eb2e8f9f7 1562 * @retval None
<> 144:ef7eb2e8f9f7 1563 */
<> 144:ef7eb2e8f9f7 1564 #define __HAL_ETH_DMARXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->RxDesc->Status |= ETH_DMARXDESC_OWN)
<> 144:ef7eb2e8f9f7 1565
<> 144:ef7eb2e8f9f7 1566 /**
<> 144:ef7eb2e8f9f7 1567 * @brief Returns the specified ETHERNET DMA Tx Desc collision count.
<> 144:ef7eb2e8f9f7 1568 * @param __HANDLE__: ETH Handle
<> 144:ef7eb2e8f9f7 1569 * @retval The Transmit descriptor collision counter value.
<> 144:ef7eb2e8f9f7 1570 */
<> 144:ef7eb2e8f9f7 1571 #define __HAL_ETH_DMATXDESC_GET_COLLISION_COUNT(__HANDLE__) (((__HANDLE__)->TxDesc->Status & ETH_DMATXDESC_CC) >> ETH_DMATXDESC_COLLISION_COUNTSHIFT)
<> 144:ef7eb2e8f9f7 1572
<> 144:ef7eb2e8f9f7 1573 /**
<> 144:ef7eb2e8f9f7 1574 * @brief Set the specified DMA Tx Desc Own bit.
<> 144:ef7eb2e8f9f7 1575 * @param __HANDLE__: ETH Handle
<> 144:ef7eb2e8f9f7 1576 * @retval None
<> 144:ef7eb2e8f9f7 1577 */
<> 144:ef7eb2e8f9f7 1578 #define __HAL_ETH_DMATXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_OWN)
<> 144:ef7eb2e8f9f7 1579
<> 144:ef7eb2e8f9f7 1580 /**
<> 144:ef7eb2e8f9f7 1581 * @brief Enables the specified DMA Tx Desc Transmit interrupt.
<> 144:ef7eb2e8f9f7 1582 * @param __HANDLE__: ETH Handle
<> 144:ef7eb2e8f9f7 1583 * @retval None
<> 144:ef7eb2e8f9f7 1584 */
<> 144:ef7eb2e8f9f7 1585 #define __HAL_ETH_DMATXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_IC)
<> 144:ef7eb2e8f9f7 1586
<> 144:ef7eb2e8f9f7 1587 /**
<> 144:ef7eb2e8f9f7 1588 * @brief Disables the specified DMA Tx Desc Transmit interrupt.
<> 144:ef7eb2e8f9f7 1589 * @param __HANDLE__: ETH Handle
<> 144:ef7eb2e8f9f7 1590 * @retval None
<> 144:ef7eb2e8f9f7 1591 */
<> 144:ef7eb2e8f9f7 1592 #define __HAL_ETH_DMATXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_IC)
<> 144:ef7eb2e8f9f7 1593
<> 144:ef7eb2e8f9f7 1594 /**
<> 144:ef7eb2e8f9f7 1595 * @brief Selects the specified ETHERNET DMA Tx Desc Checksum Insertion.
<> 144:ef7eb2e8f9f7 1596 * @param __HANDLE__: ETH Handle
<> 144:ef7eb2e8f9f7 1597 * @param __CHECKSUM__: specifies is the DMA Tx desc checksum insertion.
<> 144:ef7eb2e8f9f7 1598 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1599 * @arg ETH_DMATXDESC_CHECKSUMBYPASS : Checksum bypass
<> 144:ef7eb2e8f9f7 1600 * @arg ETH_DMATXDESC_CHECKSUMIPV4HEADER : IPv4 header checksum
<> 144:ef7eb2e8f9f7 1601 * @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT : TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present
AnnaBridge 165:e614a9f1c9e2 1602 * @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL : TCP/UDP/ICMP checksum fully in hardware including pseudo header
<> 144:ef7eb2e8f9f7 1603 * @retval None
<> 144:ef7eb2e8f9f7 1604 */
<> 144:ef7eb2e8f9f7 1605 #define __HAL_ETH_DMATXDESC_CHECKSUM_INSERTION(__HANDLE__, __CHECKSUM__) ((__HANDLE__)->TxDesc->Status |= (__CHECKSUM__))
<> 144:ef7eb2e8f9f7 1606
<> 144:ef7eb2e8f9f7 1607 /**
<> 144:ef7eb2e8f9f7 1608 * @brief Enables the DMA Tx Desc CRC.
<> 144:ef7eb2e8f9f7 1609 * @param __HANDLE__: ETH Handle
<> 144:ef7eb2e8f9f7 1610 * @retval None
<> 144:ef7eb2e8f9f7 1611 */
<> 144:ef7eb2e8f9f7 1612 #define __HAL_ETH_DMATXDESC_CRC_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DC)
<> 144:ef7eb2e8f9f7 1613
<> 144:ef7eb2e8f9f7 1614 /**
<> 144:ef7eb2e8f9f7 1615 * @brief Disables the DMA Tx Desc CRC.
<> 144:ef7eb2e8f9f7 1616 * @param __HANDLE__: ETH Handle
<> 144:ef7eb2e8f9f7 1617 * @retval None
<> 144:ef7eb2e8f9f7 1618 */
<> 144:ef7eb2e8f9f7 1619 #define __HAL_ETH_DMATXDESC_CRC_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DC)
<> 144:ef7eb2e8f9f7 1620
<> 144:ef7eb2e8f9f7 1621 /**
<> 144:ef7eb2e8f9f7 1622 * @brief Enables the DMA Tx Desc padding for frame shorter than 64 bytes.
<> 144:ef7eb2e8f9f7 1623 * @param __HANDLE__: ETH Handle
<> 144:ef7eb2e8f9f7 1624 * @retval None
<> 144:ef7eb2e8f9f7 1625 */
<> 144:ef7eb2e8f9f7 1626 #define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DP)
<> 144:ef7eb2e8f9f7 1627
<> 144:ef7eb2e8f9f7 1628 /**
<> 144:ef7eb2e8f9f7 1629 * @brief Disables the DMA Tx Desc padding for frame shorter than 64 bytes.
<> 144:ef7eb2e8f9f7 1630 * @param __HANDLE__: ETH Handle
<> 144:ef7eb2e8f9f7 1631 * @retval None
<> 144:ef7eb2e8f9f7 1632 */
<> 144:ef7eb2e8f9f7 1633 #define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DP)
<> 144:ef7eb2e8f9f7 1634
<> 144:ef7eb2e8f9f7 1635 /**
<> 144:ef7eb2e8f9f7 1636 * @brief Enables the specified ETHERNET MAC interrupts.
<> 144:ef7eb2e8f9f7 1637 * @param __HANDLE__ : ETH Handle
<> 144:ef7eb2e8f9f7 1638 * @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be
<> 144:ef7eb2e8f9f7 1639 * enabled or disabled.
<> 144:ef7eb2e8f9f7 1640 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 1641 * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt
<> 144:ef7eb2e8f9f7 1642 * @arg ETH_MAC_IT_PMT : PMT interrupt
<> 144:ef7eb2e8f9f7 1643 * @retval None
<> 144:ef7eb2e8f9f7 1644 */
<> 144:ef7eb2e8f9f7 1645 #define __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR |= (__INTERRUPT__))
<> 144:ef7eb2e8f9f7 1646
<> 144:ef7eb2e8f9f7 1647 /**
<> 144:ef7eb2e8f9f7 1648 * @brief Disables the specified ETHERNET MAC interrupts.
<> 144:ef7eb2e8f9f7 1649 * @param __HANDLE__ : ETH Handle
<> 144:ef7eb2e8f9f7 1650 * @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be
<> 144:ef7eb2e8f9f7 1651 * enabled or disabled.
<> 144:ef7eb2e8f9f7 1652 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 1653 * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt
<> 144:ef7eb2e8f9f7 1654 * @arg ETH_MAC_IT_PMT : PMT interrupt
<> 144:ef7eb2e8f9f7 1655 * @retval None
<> 144:ef7eb2e8f9f7 1656 */
<> 144:ef7eb2e8f9f7 1657 #define __HAL_ETH_MAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR &= ~(__INTERRUPT__))
<> 144:ef7eb2e8f9f7 1658
<> 144:ef7eb2e8f9f7 1659 /**
<> 144:ef7eb2e8f9f7 1660 * @brief Initiate a Pause Control Frame (Full-duplex only).
<> 144:ef7eb2e8f9f7 1661 * @param __HANDLE__: ETH Handle
<> 144:ef7eb2e8f9f7 1662 * @retval None
<> 144:ef7eb2e8f9f7 1663 */
<> 144:ef7eb2e8f9f7 1664 #define __HAL_ETH_INITIATE_PAUSE_CONTROL_FRAME(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA)
<> 144:ef7eb2e8f9f7 1665
<> 144:ef7eb2e8f9f7 1666 /**
<> 144:ef7eb2e8f9f7 1667 * @brief Checks whether the ETHERNET flow control busy bit is set or not.
<> 144:ef7eb2e8f9f7 1668 * @param __HANDLE__: ETH Handle
<> 144:ef7eb2e8f9f7 1669 * @retval The new state of flow control busy status bit (SET or RESET).
<> 144:ef7eb2e8f9f7 1670 */
<> 144:ef7eb2e8f9f7 1671 #define __HAL_ETH_GET_FLOW_CONTROL_BUSY_STATUS(__HANDLE__) (((__HANDLE__)->Instance->MACFCR & ETH_MACFCR_FCBBPA) == ETH_MACFCR_FCBBPA)
<> 144:ef7eb2e8f9f7 1672
<> 144:ef7eb2e8f9f7 1673 /**
<> 144:ef7eb2e8f9f7 1674 * @brief Enables the MAC Back Pressure operation activation (Half-duplex only).
<> 144:ef7eb2e8f9f7 1675 * @param __HANDLE__: ETH Handle
<> 144:ef7eb2e8f9f7 1676 * @retval None
<> 144:ef7eb2e8f9f7 1677 */
<> 144:ef7eb2e8f9f7 1678 #define __HAL_ETH_BACK_PRESSURE_ACTIVATION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA)
<> 144:ef7eb2e8f9f7 1679
<> 144:ef7eb2e8f9f7 1680 /**
<> 144:ef7eb2e8f9f7 1681 * @brief Disables the MAC BackPressure operation activation (Half-duplex only).
<> 144:ef7eb2e8f9f7 1682 * @param __HANDLE__: ETH Handle
<> 144:ef7eb2e8f9f7 1683 * @retval None
<> 144:ef7eb2e8f9f7 1684 */
<> 144:ef7eb2e8f9f7 1685 #define __HAL_ETH_BACK_PRESSURE_ACTIVATION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR &= ~ETH_MACFCR_FCBBPA)
<> 144:ef7eb2e8f9f7 1686
<> 144:ef7eb2e8f9f7 1687 /**
<> 144:ef7eb2e8f9f7 1688 * @brief Checks whether the specified ETHERNET MAC flag is set or not.
<> 144:ef7eb2e8f9f7 1689 * @param __HANDLE__: ETH Handle
<> 144:ef7eb2e8f9f7 1690 * @param __FLAG__: specifies the flag to check.
<> 144:ef7eb2e8f9f7 1691 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1692 * @arg ETH_MAC_FLAG_TST : Time stamp trigger flag
<> 144:ef7eb2e8f9f7 1693 * @arg ETH_MAC_FLAG_MMCT : MMC transmit flag
<> 144:ef7eb2e8f9f7 1694 * @arg ETH_MAC_FLAG_MMCR : MMC receive flag
<> 144:ef7eb2e8f9f7 1695 * @arg ETH_MAC_FLAG_MMC : MMC flag
<> 144:ef7eb2e8f9f7 1696 * @arg ETH_MAC_FLAG_PMT : PMT flag
<> 144:ef7eb2e8f9f7 1697 * @retval The state of ETHERNET MAC flag.
<> 144:ef7eb2e8f9f7 1698 */
<> 144:ef7eb2e8f9f7 1699 #define __HAL_ETH_MAC_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACSR &( __FLAG__)) == ( __FLAG__))
<> 144:ef7eb2e8f9f7 1700
<> 144:ef7eb2e8f9f7 1701 /**
<> 144:ef7eb2e8f9f7 1702 * @brief Enables the specified ETHERNET DMA interrupts.
<> 144:ef7eb2e8f9f7 1703 * @param __HANDLE__ : ETH Handle
<> 144:ef7eb2e8f9f7 1704 * @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be
<> 144:ef7eb2e8f9f7 1705 * enabled @ref ETH_DMA_Interrupts
<> 144:ef7eb2e8f9f7 1706 * @retval None
<> 144:ef7eb2e8f9f7 1707 */
<> 144:ef7eb2e8f9f7 1708 #define __HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER |= (__INTERRUPT__))
<> 144:ef7eb2e8f9f7 1709
<> 144:ef7eb2e8f9f7 1710 /**
<> 144:ef7eb2e8f9f7 1711 * @brief Disables the specified ETHERNET DMA interrupts.
<> 144:ef7eb2e8f9f7 1712 * @param __HANDLE__ : ETH Handle
<> 144:ef7eb2e8f9f7 1713 * @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be
<> 144:ef7eb2e8f9f7 1714 * disabled. @ref ETH_DMA_Interrupts
<> 144:ef7eb2e8f9f7 1715 * @retval None
<> 144:ef7eb2e8f9f7 1716 */
<> 144:ef7eb2e8f9f7 1717 #define __HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER &= ~(__INTERRUPT__))
<> 144:ef7eb2e8f9f7 1718
<> 144:ef7eb2e8f9f7 1719 /**
<> 144:ef7eb2e8f9f7 1720 * @brief Clears the ETHERNET DMA IT pending bit.
<> 144:ef7eb2e8f9f7 1721 * @param __HANDLE__ : ETH Handle
<> 144:ef7eb2e8f9f7 1722 * @param __INTERRUPT__: specifies the interrupt pending bit to clear. @ref ETH_DMA_Interrupts
<> 144:ef7eb2e8f9f7 1723 * @retval None
<> 144:ef7eb2e8f9f7 1724 */
<> 144:ef7eb2e8f9f7 1725 #define __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMASR =(__INTERRUPT__))
<> 144:ef7eb2e8f9f7 1726
<> 144:ef7eb2e8f9f7 1727 /**
<> 144:ef7eb2e8f9f7 1728 * @brief Checks whether the specified ETHERNET DMA flag is set or not.
<> 144:ef7eb2e8f9f7 1729 * @param __HANDLE__: ETH Handle
<> 144:ef7eb2e8f9f7 1730 * @param __FLAG__: specifies the flag to check. @ref ETH_DMA_Flags
<> 144:ef7eb2e8f9f7 1731 * @retval The new state of ETH_DMA_FLAG (SET or RESET).
<> 144:ef7eb2e8f9f7 1732 */
<> 144:ef7eb2e8f9f7 1733 #define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->DMASR &( __FLAG__)) == ( __FLAG__))
<> 144:ef7eb2e8f9f7 1734
<> 144:ef7eb2e8f9f7 1735 /**
<> 144:ef7eb2e8f9f7 1736 * @brief Checks whether the specified ETHERNET DMA flag is set or not.
<> 144:ef7eb2e8f9f7 1737 * @param __HANDLE__: ETH Handle
<> 144:ef7eb2e8f9f7 1738 * @param __FLAG__: specifies the flag to clear. @ref ETH_DMA_Flags
<> 144:ef7eb2e8f9f7 1739 * @retval The new state of ETH_DMA_FLAG (SET or RESET).
<> 144:ef7eb2e8f9f7 1740 */
<> 144:ef7eb2e8f9f7 1741 #define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->DMASR = (__FLAG__))
<> 144:ef7eb2e8f9f7 1742
<> 144:ef7eb2e8f9f7 1743 /**
<> 144:ef7eb2e8f9f7 1744 * @brief Checks whether the specified ETHERNET DMA overflow flag is set or not.
<> 144:ef7eb2e8f9f7 1745 * @param __HANDLE__: ETH Handle
<> 144:ef7eb2e8f9f7 1746 * @param __OVERFLOW__: specifies the DMA overflow flag to check.
<> 144:ef7eb2e8f9f7 1747 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1748 * @arg ETH_DMA_OVERFLOW_RXFIFOCOUNTER : Overflow for FIFO Overflows Counter
<> 144:ef7eb2e8f9f7 1749 * @arg ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER : Overflow for Buffer Unavailable Missed Frame Counter
<> 144:ef7eb2e8f9f7 1750 * @retval The state of ETHERNET DMA overflow Flag (SET or RESET).
<> 144:ef7eb2e8f9f7 1751 */
<> 144:ef7eb2e8f9f7 1752 #define __HAL_ETH_GET_DMA_OVERFLOW_STATUS(__HANDLE__, __OVERFLOW__) (((__HANDLE__)->Instance->DMAMFBOCR & (__OVERFLOW__)) == (__OVERFLOW__))
<> 144:ef7eb2e8f9f7 1753
<> 144:ef7eb2e8f9f7 1754 /**
<> 144:ef7eb2e8f9f7 1755 * @brief Set the DMA Receive status watchdog timer register value
<> 144:ef7eb2e8f9f7 1756 * @param __HANDLE__: ETH Handle
<> 144:ef7eb2e8f9f7 1757 * @param __VALUE__: DMA Receive status watchdog timer register value
<> 144:ef7eb2e8f9f7 1758 * @retval None
<> 144:ef7eb2e8f9f7 1759 */
<> 144:ef7eb2e8f9f7 1760 #define __HAL_ETH_SET_RECEIVE_WATCHDOG_TIMER(__HANDLE__, __VALUE__) ((__HANDLE__)->Instance->DMARSWTR = (__VALUE__))
<> 144:ef7eb2e8f9f7 1761
<> 144:ef7eb2e8f9f7 1762 /**
<> 144:ef7eb2e8f9f7 1763 * @brief Enables any unicast packet filtered by the MAC address
<> 144:ef7eb2e8f9f7 1764 * recognition to be a wake-up frame.
<> 144:ef7eb2e8f9f7 1765 * @param __HANDLE__: ETH Handle.
<> 144:ef7eb2e8f9f7 1766 * @retval None
<> 144:ef7eb2e8f9f7 1767 */
<> 144:ef7eb2e8f9f7 1768 #define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_GU)
<> 144:ef7eb2e8f9f7 1769
<> 144:ef7eb2e8f9f7 1770 /**
<> 144:ef7eb2e8f9f7 1771 * @brief Disables any unicast packet filtered by the MAC address
<> 144:ef7eb2e8f9f7 1772 * recognition to be a wake-up frame.
<> 144:ef7eb2e8f9f7 1773 * @param __HANDLE__: ETH Handle.
<> 144:ef7eb2e8f9f7 1774 * @retval None
<> 144:ef7eb2e8f9f7 1775 */
<> 144:ef7eb2e8f9f7 1776 #define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_GU)
<> 144:ef7eb2e8f9f7 1777
<> 144:ef7eb2e8f9f7 1778 /**
<> 144:ef7eb2e8f9f7 1779 * @brief Enables the MAC Wake-Up Frame Detection.
<> 144:ef7eb2e8f9f7 1780 * @param __HANDLE__: ETH Handle.
<> 144:ef7eb2e8f9f7 1781 * @retval None
<> 144:ef7eb2e8f9f7 1782 */
<> 144:ef7eb2e8f9f7 1783 #define __HAL_ETH_WAKEUP_FRAME_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_WFE)
<> 144:ef7eb2e8f9f7 1784
<> 144:ef7eb2e8f9f7 1785 /**
<> 144:ef7eb2e8f9f7 1786 * @brief Disables the MAC Wake-Up Frame Detection.
<> 144:ef7eb2e8f9f7 1787 * @param __HANDLE__: ETH Handle.
<> 144:ef7eb2e8f9f7 1788 * @retval None
<> 144:ef7eb2e8f9f7 1789 */
<> 144:ef7eb2e8f9f7 1790 #define __HAL_ETH_WAKEUP_FRAME_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)
<> 144:ef7eb2e8f9f7 1791
<> 144:ef7eb2e8f9f7 1792 /**
<> 144:ef7eb2e8f9f7 1793 * @brief Enables the MAC Magic Packet Detection.
<> 144:ef7eb2e8f9f7 1794 * @param __HANDLE__: ETH Handle.
<> 144:ef7eb2e8f9f7 1795 * @retval None
<> 144:ef7eb2e8f9f7 1796 */
<> 144:ef7eb2e8f9f7 1797 #define __HAL_ETH_MAGIC_PACKET_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_MPE)
<> 144:ef7eb2e8f9f7 1798
<> 144:ef7eb2e8f9f7 1799 /**
<> 144:ef7eb2e8f9f7 1800 * @brief Disables the MAC Magic Packet Detection.
<> 144:ef7eb2e8f9f7 1801 * @param __HANDLE__: ETH Handle.
<> 144:ef7eb2e8f9f7 1802 * @retval None
<> 144:ef7eb2e8f9f7 1803 */
<> 144:ef7eb2e8f9f7 1804 #define __HAL_ETH_MAGIC_PACKET_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)
<> 144:ef7eb2e8f9f7 1805
<> 144:ef7eb2e8f9f7 1806 /**
<> 144:ef7eb2e8f9f7 1807 * @brief Enables the MAC Power Down.
<> 144:ef7eb2e8f9f7 1808 * @param __HANDLE__: ETH Handle
<> 144:ef7eb2e8f9f7 1809 * @retval None
<> 144:ef7eb2e8f9f7 1810 */
<> 144:ef7eb2e8f9f7 1811 #define __HAL_ETH_POWER_DOWN_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_PD)
<> 144:ef7eb2e8f9f7 1812
<> 144:ef7eb2e8f9f7 1813 /**
<> 144:ef7eb2e8f9f7 1814 * @brief Disables the MAC Power Down.
<> 144:ef7eb2e8f9f7 1815 * @param __HANDLE__: ETH Handle
<> 144:ef7eb2e8f9f7 1816 * @retval None
<> 144:ef7eb2e8f9f7 1817 */
<> 144:ef7eb2e8f9f7 1818 #define __HAL_ETH_POWER_DOWN_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_PD)
<> 144:ef7eb2e8f9f7 1819
<> 144:ef7eb2e8f9f7 1820 /**
<> 144:ef7eb2e8f9f7 1821 * @brief Checks whether the specified ETHERNET PMT flag is set or not.
<> 144:ef7eb2e8f9f7 1822 * @param __HANDLE__: ETH Handle.
<> 144:ef7eb2e8f9f7 1823 * @param __FLAG__: specifies the flag to check.
<> 144:ef7eb2e8f9f7 1824 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1825 * @arg ETH_PMT_FLAG_WUFFRPR : Wake-Up Frame Filter Register Pointer Reset
<> 144:ef7eb2e8f9f7 1826 * @arg ETH_PMT_FLAG_WUFR : Wake-Up Frame Received
<> 144:ef7eb2e8f9f7 1827 * @arg ETH_PMT_FLAG_MPR : Magic Packet Received
<> 144:ef7eb2e8f9f7 1828 * @retval The new state of ETHERNET PMT Flag (SET or RESET).
<> 144:ef7eb2e8f9f7 1829 */
<> 144:ef7eb2e8f9f7 1830 #define __HAL_ETH_GET_PMT_FLAG_STATUS(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACPMTCSR &( __FLAG__)) == ( __FLAG__))
<> 144:ef7eb2e8f9f7 1831
<> 144:ef7eb2e8f9f7 1832 /**
<> 144:ef7eb2e8f9f7 1833 * @brief Preset and Initialize the MMC counters to almost-full value: 0xFFFF_FFF0 (full - 16)
<> 144:ef7eb2e8f9f7 1834 * @param __HANDLE__: ETH Handle.
<> 144:ef7eb2e8f9f7 1835 * @retval None
<> 144:ef7eb2e8f9f7 1836 */
<> 144:ef7eb2e8f9f7 1837 #define __HAL_ETH_MMC_COUNTER_FULL_PRESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= (ETH_MMCCR_MCFHP | ETH_MMCCR_MCP))
<> 144:ef7eb2e8f9f7 1838
<> 144:ef7eb2e8f9f7 1839 /**
<> 144:ef7eb2e8f9f7 1840 * @brief Preset and Initialize the MMC counters to almost-half value: 0x7FFF_FFF0 (half - 16)
<> 144:ef7eb2e8f9f7 1841 * @param __HANDLE__: ETH Handle.
<> 144:ef7eb2e8f9f7 1842 * @retval None
<> 144:ef7eb2e8f9f7 1843 */
<> 144:ef7eb2e8f9f7 1844 #define __HAL_ETH_MMC_COUNTER_HALF_PRESET(__HANDLE__) do{(__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCFHP;\
AnnaBridge 165:e614a9f1c9e2 1845 (__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCP;} while(0U)
<> 144:ef7eb2e8f9f7 1846
<> 144:ef7eb2e8f9f7 1847 /**
<> 144:ef7eb2e8f9f7 1848 * @brief Enables the MMC Counter Freeze.
<> 144:ef7eb2e8f9f7 1849 * @param __HANDLE__: ETH Handle.
<> 144:ef7eb2e8f9f7 1850 * @retval None
<> 144:ef7eb2e8f9f7 1851 */
<> 144:ef7eb2e8f9f7 1852 #define __HAL_ETH_MMC_COUNTER_FREEZE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCF)
<> 144:ef7eb2e8f9f7 1853
<> 144:ef7eb2e8f9f7 1854 /**
<> 144:ef7eb2e8f9f7 1855 * @brief Disables the MMC Counter Freeze.
<> 144:ef7eb2e8f9f7 1856 * @param __HANDLE__: ETH Handle.
<> 144:ef7eb2e8f9f7 1857 * @retval None
<> 144:ef7eb2e8f9f7 1858 */
<> 144:ef7eb2e8f9f7 1859 #define __HAL_ETH_MMC_COUNTER_FREEZE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCF)
<> 144:ef7eb2e8f9f7 1860
<> 144:ef7eb2e8f9f7 1861 /**
<> 144:ef7eb2e8f9f7 1862 * @brief Enables the MMC Reset On Read.
<> 144:ef7eb2e8f9f7 1863 * @param __HANDLE__: ETH Handle.
<> 144:ef7eb2e8f9f7 1864 * @retval None
<> 144:ef7eb2e8f9f7 1865 */
<> 144:ef7eb2e8f9f7 1866 #define __HAL_ETH_ETH_MMC_RESET_ONREAD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_ROR)
<> 144:ef7eb2e8f9f7 1867
<> 144:ef7eb2e8f9f7 1868 /**
<> 144:ef7eb2e8f9f7 1869 * @brief Disables the MMC Reset On Read.
<> 144:ef7eb2e8f9f7 1870 * @param __HANDLE__: ETH Handle.
<> 144:ef7eb2e8f9f7 1871 * @retval None
<> 144:ef7eb2e8f9f7 1872 */
<> 144:ef7eb2e8f9f7 1873 #define __HAL_ETH_ETH_MMC_RESET_ONREAD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_ROR)
<> 144:ef7eb2e8f9f7 1874
<> 144:ef7eb2e8f9f7 1875 /**
<> 144:ef7eb2e8f9f7 1876 * @brief Enables the MMC Counter Stop Rollover.
<> 144:ef7eb2e8f9f7 1877 * @param __HANDLE__: ETH Handle.
<> 144:ef7eb2e8f9f7 1878 * @retval None
<> 144:ef7eb2e8f9f7 1879 */
<> 144:ef7eb2e8f9f7 1880 #define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_CSR)
<> 144:ef7eb2e8f9f7 1881
<> 144:ef7eb2e8f9f7 1882 /**
<> 144:ef7eb2e8f9f7 1883 * @brief Disables the MMC Counter Stop Rollover.
<> 144:ef7eb2e8f9f7 1884 * @param __HANDLE__: ETH Handle.
<> 144:ef7eb2e8f9f7 1885 * @retval None
<> 144:ef7eb2e8f9f7 1886 */
<> 144:ef7eb2e8f9f7 1887 #define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CSR)
<> 144:ef7eb2e8f9f7 1888
<> 144:ef7eb2e8f9f7 1889 /**
<> 144:ef7eb2e8f9f7 1890 * @brief Resets the MMC Counters.
<> 144:ef7eb2e8f9f7 1891 * @param __HANDLE__: ETH Handle.
<> 144:ef7eb2e8f9f7 1892 * @retval None
<> 144:ef7eb2e8f9f7 1893 */
<> 144:ef7eb2e8f9f7 1894 #define __HAL_ETH_MMC_COUNTERS_RESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CR)
<> 144:ef7eb2e8f9f7 1895
<> 144:ef7eb2e8f9f7 1896 /**
<> 144:ef7eb2e8f9f7 1897 * @brief Enables the specified ETHERNET MMC Rx interrupts.
<> 144:ef7eb2e8f9f7 1898 * @param __HANDLE__: ETH Handle.
<> 144:ef7eb2e8f9f7 1899 * @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
<> 144:ef7eb2e8f9f7 1900 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1901 * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value
<> 144:ef7eb2e8f9f7 1902 * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value
<> 144:ef7eb2e8f9f7 1903 * @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value
<> 144:ef7eb2e8f9f7 1904 * @retval None
<> 144:ef7eb2e8f9f7 1905 */
AnnaBridge 165:e614a9f1c9e2 1906 #define __HAL_ETH_MMC_RX_IT_ENABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR &= ~((__INTERRUPT__) & 0xEFFFFFFFU)
<> 144:ef7eb2e8f9f7 1907 /**
<> 144:ef7eb2e8f9f7 1908 * @brief Disables the specified ETHERNET MMC Rx interrupts.
<> 144:ef7eb2e8f9f7 1909 * @param __HANDLE__: ETH Handle.
<> 144:ef7eb2e8f9f7 1910 * @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
<> 144:ef7eb2e8f9f7 1911 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1912 * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value
<> 144:ef7eb2e8f9f7 1913 * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value
<> 144:ef7eb2e8f9f7 1914 * @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value
<> 144:ef7eb2e8f9f7 1915 * @retval None
<> 144:ef7eb2e8f9f7 1916 */
AnnaBridge 165:e614a9f1c9e2 1917 #define __HAL_ETH_MMC_RX_IT_DISABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR |= ((__INTERRUPT__) & 0xEFFFFFFFU)
<> 144:ef7eb2e8f9f7 1918 /**
<> 144:ef7eb2e8f9f7 1919 * @brief Enables the specified ETHERNET MMC Tx interrupts.
<> 144:ef7eb2e8f9f7 1920 * @param __HANDLE__: ETH Handle.
<> 144:ef7eb2e8f9f7 1921 * @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
<> 144:ef7eb2e8f9f7 1922 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1923 * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value
<> 144:ef7eb2e8f9f7 1924 * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value
<> 144:ef7eb2e8f9f7 1925 * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value
<> 144:ef7eb2e8f9f7 1926 * @retval None
<> 144:ef7eb2e8f9f7 1927 */
<> 144:ef7eb2e8f9f7 1928 #define __HAL_ETH_MMC_TX_IT_ENABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR &= ~ (__INTERRUPT__))
<> 144:ef7eb2e8f9f7 1929
<> 144:ef7eb2e8f9f7 1930 /**
<> 144:ef7eb2e8f9f7 1931 * @brief Disables the specified ETHERNET MMC Tx interrupts.
<> 144:ef7eb2e8f9f7 1932 * @param __HANDLE__: ETH Handle.
<> 144:ef7eb2e8f9f7 1933 * @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
<> 144:ef7eb2e8f9f7 1934 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1935 * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value
<> 144:ef7eb2e8f9f7 1936 * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value
<> 144:ef7eb2e8f9f7 1937 * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value
<> 144:ef7eb2e8f9f7 1938 * @retval None
<> 144:ef7eb2e8f9f7 1939 */
<> 144:ef7eb2e8f9f7 1940 #define __HAL_ETH_MMC_TX_IT_DISABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR |= (__INTERRUPT__))
<> 144:ef7eb2e8f9f7 1941
<> 144:ef7eb2e8f9f7 1942 /**
<> 144:ef7eb2e8f9f7 1943 * @brief Enables the ETH External interrupt line.
<> 144:ef7eb2e8f9f7 1944 * @retval None
<> 144:ef7eb2e8f9f7 1945 */
<> 144:ef7eb2e8f9f7 1946 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= (ETH_EXTI_LINE_WAKEUP)
<> 144:ef7eb2e8f9f7 1947
<> 144:ef7eb2e8f9f7 1948 /**
<> 144:ef7eb2e8f9f7 1949 * @brief Disables the ETH External interrupt line.
<> 144:ef7eb2e8f9f7 1950 * @retval None
<> 144:ef7eb2e8f9f7 1951 */
<> 144:ef7eb2e8f9f7 1952 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(ETH_EXTI_LINE_WAKEUP)
<> 144:ef7eb2e8f9f7 1953
<> 144:ef7eb2e8f9f7 1954 /**
<> 144:ef7eb2e8f9f7 1955 * @brief Enable event on ETH External event line.
<> 144:ef7eb2e8f9f7 1956 * @retval None.
<> 144:ef7eb2e8f9f7 1957 */
<> 144:ef7eb2e8f9f7 1958 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_EVENT() EXTI->EMR |= (ETH_EXTI_LINE_WAKEUP)
<> 144:ef7eb2e8f9f7 1959
<> 144:ef7eb2e8f9f7 1960 /**
<> 144:ef7eb2e8f9f7 1961 * @brief Disable event on ETH External event line
<> 144:ef7eb2e8f9f7 1962 * @retval None.
<> 144:ef7eb2e8f9f7 1963 */
<> 144:ef7eb2e8f9f7 1964 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_EVENT() EXTI->EMR &= ~(ETH_EXTI_LINE_WAKEUP)
<> 144:ef7eb2e8f9f7 1965
<> 144:ef7eb2e8f9f7 1966 /**
<> 144:ef7eb2e8f9f7 1967 * @brief Get flag of the ETH External interrupt line.
<> 144:ef7eb2e8f9f7 1968 * @retval None
<> 144:ef7eb2e8f9f7 1969 */
<> 144:ef7eb2e8f9f7 1970 #define __HAL_ETH_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (ETH_EXTI_LINE_WAKEUP)
<> 144:ef7eb2e8f9f7 1971
<> 144:ef7eb2e8f9f7 1972 /**
<> 144:ef7eb2e8f9f7 1973 * @brief Clear flag of the ETH External interrupt line.
<> 144:ef7eb2e8f9f7 1974 * @retval None
<> 144:ef7eb2e8f9f7 1975 */
<> 144:ef7eb2e8f9f7 1976 #define __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = (ETH_EXTI_LINE_WAKEUP)
<> 144:ef7eb2e8f9f7 1977
<> 144:ef7eb2e8f9f7 1978 /**
<> 144:ef7eb2e8f9f7 1979 * @brief Enables rising edge trigger to the ETH External interrupt line.
<> 144:ef7eb2e8f9f7 1980 * @retval None
<> 144:ef7eb2e8f9f7 1981 */
<> 144:ef7eb2e8f9f7 1982 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER() EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP
AnnaBridge 165:e614a9f1c9e2 1983
<> 144:ef7eb2e8f9f7 1984 /**
<> 144:ef7eb2e8f9f7 1985 * @brief Disables the rising edge trigger to the ETH External interrupt line.
<> 144:ef7eb2e8f9f7 1986 * @retval None
<> 144:ef7eb2e8f9f7 1987 */
AnnaBridge 165:e614a9f1c9e2 1988 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_RISING_EDGE_TRIGGER() EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP)
<> 144:ef7eb2e8f9f7 1989
<> 144:ef7eb2e8f9f7 1990 /**
<> 144:ef7eb2e8f9f7 1991 * @brief Enables falling edge trigger to the ETH External interrupt line.
<> 144:ef7eb2e8f9f7 1992 * @retval None
AnnaBridge 165:e614a9f1c9e2 1993 */
<> 144:ef7eb2e8f9f7 1994 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR |= (ETH_EXTI_LINE_WAKEUP)
<> 144:ef7eb2e8f9f7 1995
<> 144:ef7eb2e8f9f7 1996 /**
<> 144:ef7eb2e8f9f7 1997 * @brief Disables falling edge trigger to the ETH External interrupt line.
<> 144:ef7eb2e8f9f7 1998 * @retval None
<> 144:ef7eb2e8f9f7 1999 */
<> 144:ef7eb2e8f9f7 2000 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP)
<> 144:ef7eb2e8f9f7 2001
<> 144:ef7eb2e8f9f7 2002 /**
<> 144:ef7eb2e8f9f7 2003 * @brief Enables rising/falling edge trigger to the ETH External interrupt line.
<> 144:ef7eb2e8f9f7 2004 * @retval None
<> 144:ef7eb2e8f9f7 2005 */
AnnaBridge 165:e614a9f1c9e2 2006 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER() do{EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP;\
AnnaBridge 165:e614a9f1c9e2 2007 EXTI->FTSR |= ETH_EXTI_LINE_WAKEUP;\
AnnaBridge 165:e614a9f1c9e2 2008 }while(0U)
<> 144:ef7eb2e8f9f7 2009
<> 144:ef7eb2e8f9f7 2010 /**
<> 144:ef7eb2e8f9f7 2011 * @brief Disables rising/falling edge trigger to the ETH External interrupt line.
<> 144:ef7eb2e8f9f7 2012 * @retval None
<> 144:ef7eb2e8f9f7 2013 */
AnnaBridge 165:e614a9f1c9e2 2014 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLINGRISING_TRIGGER() do{EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP);\
AnnaBridge 165:e614a9f1c9e2 2015 EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP);\
AnnaBridge 165:e614a9f1c9e2 2016 }while(0U)
<> 144:ef7eb2e8f9f7 2017
<> 144:ef7eb2e8f9f7 2018 /**
<> 144:ef7eb2e8f9f7 2019 * @brief Generate a Software interrupt on selected EXTI line.
<> 144:ef7eb2e8f9f7 2020 * @retval None.
<> 144:ef7eb2e8f9f7 2021 */
<> 144:ef7eb2e8f9f7 2022 #define __HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT() EXTI->SWIER|= ETH_EXTI_LINE_WAKEUP
<> 144:ef7eb2e8f9f7 2023
<> 144:ef7eb2e8f9f7 2024 /**
<> 144:ef7eb2e8f9f7 2025 * @}
<> 144:ef7eb2e8f9f7 2026 */
<> 144:ef7eb2e8f9f7 2027 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 2028
<> 144:ef7eb2e8f9f7 2029 /** @addtogroup ETH_Exported_Functions
<> 144:ef7eb2e8f9f7 2030 * @{
<> 144:ef7eb2e8f9f7 2031 */
<> 144:ef7eb2e8f9f7 2032
<> 144:ef7eb2e8f9f7 2033 /* Initialization and de-initialization functions ****************************/
<> 144:ef7eb2e8f9f7 2034
<> 144:ef7eb2e8f9f7 2035 /** @addtogroup ETH_Exported_Functions_Group1
<> 144:ef7eb2e8f9f7 2036 * @{
<> 144:ef7eb2e8f9f7 2037 */
<> 144:ef7eb2e8f9f7 2038 HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth);
<> 144:ef7eb2e8f9f7 2039 HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth);
<> 144:ef7eb2e8f9f7 2040 void HAL_ETH_MspInit(ETH_HandleTypeDef *heth);
<> 144:ef7eb2e8f9f7 2041 void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth);
<> 144:ef7eb2e8f9f7 2042 HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount);
<> 144:ef7eb2e8f9f7 2043 HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount);
<> 144:ef7eb2e8f9f7 2044
<> 144:ef7eb2e8f9f7 2045 /**
<> 144:ef7eb2e8f9f7 2046 * @}
<> 144:ef7eb2e8f9f7 2047 */
<> 144:ef7eb2e8f9f7 2048 /* IO operation functions ****************************************************/
<> 144:ef7eb2e8f9f7 2049
<> 144:ef7eb2e8f9f7 2050 /** @addtogroup ETH_Exported_Functions_Group2
<> 144:ef7eb2e8f9f7 2051 * @{
<> 144:ef7eb2e8f9f7 2052 */
<> 144:ef7eb2e8f9f7 2053 HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength);
<> 144:ef7eb2e8f9f7 2054 HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth);
<> 144:ef7eb2e8f9f7 2055 /* Communication with PHY functions*/
<> 144:ef7eb2e8f9f7 2056 HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue);
<> 144:ef7eb2e8f9f7 2057 HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue);
AnnaBridge 165:e614a9f1c9e2 2058 /* Non-Blocking mode: Interrupt */
<> 144:ef7eb2e8f9f7 2059 HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth);
<> 144:ef7eb2e8f9f7 2060 void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth);
AnnaBridge 165:e614a9f1c9e2 2061 /* Callback in non blocking modes (Interrupt) */
<> 144:ef7eb2e8f9f7 2062 void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth);
<> 144:ef7eb2e8f9f7 2063 void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth);
<> 144:ef7eb2e8f9f7 2064 void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth);
<> 144:ef7eb2e8f9f7 2065 /**
<> 144:ef7eb2e8f9f7 2066 * @}
<> 144:ef7eb2e8f9f7 2067 */
<> 144:ef7eb2e8f9f7 2068
<> 144:ef7eb2e8f9f7 2069 /* Peripheral Control functions **********************************************/
<> 144:ef7eb2e8f9f7 2070
<> 144:ef7eb2e8f9f7 2071 /** @addtogroup ETH_Exported_Functions_Group3
<> 144:ef7eb2e8f9f7 2072 * @{
<> 144:ef7eb2e8f9f7 2073 */
AnnaBridge 165:e614a9f1c9e2 2074
<> 144:ef7eb2e8f9f7 2075 HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth);
<> 144:ef7eb2e8f9f7 2076 HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth);
<> 144:ef7eb2e8f9f7 2077 HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf);
<> 144:ef7eb2e8f9f7 2078 HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf);
<> 144:ef7eb2e8f9f7 2079 /**
<> 144:ef7eb2e8f9f7 2080 * @}
<> 144:ef7eb2e8f9f7 2081 */
AnnaBridge 165:e614a9f1c9e2 2082
<> 144:ef7eb2e8f9f7 2083 /* Peripheral State functions ************************************************/
<> 144:ef7eb2e8f9f7 2084
<> 144:ef7eb2e8f9f7 2085 /** @addtogroup ETH_Exported_Functions_Group4
<> 144:ef7eb2e8f9f7 2086 * @{
<> 144:ef7eb2e8f9f7 2087 */
<> 144:ef7eb2e8f9f7 2088 HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth);
AnnaBridge 165:e614a9f1c9e2 2089 /**
AnnaBridge 165:e614a9f1c9e2 2090 * @}
AnnaBridge 165:e614a9f1c9e2 2091 */
<> 144:ef7eb2e8f9f7 2092
<> 144:ef7eb2e8f9f7 2093 /**
<> 144:ef7eb2e8f9f7 2094 * @}
<> 144:ef7eb2e8f9f7 2095 */
AnnaBridge 165:e614a9f1c9e2 2096
<> 144:ef7eb2e8f9f7 2097 /**
<> 144:ef7eb2e8f9f7 2098 * @}
<> 144:ef7eb2e8f9f7 2099 */
<> 144:ef7eb2e8f9f7 2100
<> 144:ef7eb2e8f9f7 2101 #endif /* STM32F107xC */
<> 144:ef7eb2e8f9f7 2102 /**
<> 144:ef7eb2e8f9f7 2103 * @}
AnnaBridge 165:e614a9f1c9e2 2104 */
<> 144:ef7eb2e8f9f7 2105
<> 144:ef7eb2e8f9f7 2106 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 2107 }
<> 144:ef7eb2e8f9f7 2108 #endif
<> 144:ef7eb2e8f9f7 2109
<> 144:ef7eb2e8f9f7 2110 #endif /* __STM32F1xx_HAL_ETH_H */
<> 144:ef7eb2e8f9f7 2111
<> 144:ef7eb2e8f9f7 2112
<> 144:ef7eb2e8f9f7 2113 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/